From 8ee0719a48f6e1987a50b1f1de2fb3ce02bb2658 Mon Sep 17 00:00:00 2001 From: Andrey Zgarbul Date: Fri, 29 Mar 2024 17:55:17 +0300 Subject: [PATCH] generate SVD-YAML --- esp32/svd/esp32.svd.yaml | 31810 +++++++++ esp32c2/svd/esp32c2.svd.yaml | 15269 ++++ esp32c3/svd/esp32c3.svd.yaml | 24629 +++++++ esp32c6-lp/svd/esp32c6-lp.svd.yaml | 4582 ++ esp32c6/svd/esp32c6.svd.yaml | 49968 +++++++++++++ esp32h2/svd/esp32h2.svd.yaml | 37846 ++++++++++ esp32p4/svd/esp32p4.svd.yaml | 92833 +++++++++++++++++++++++++ esp32s2-ulp/svd/esp32s2-ulp.svd.yaml | 1905 + esp32s2/svd/esp32s2.svd.yaml | 33272 +++++++++ esp32s3-ulp/svd/esp32s3-ulp.svd.yaml | 3359 + esp32s3/svd/esp32s3.svd.yaml | 49533 +++++++++++++ xtask/Cargo.lock | 4 +- xtask/Cargo.toml | 2 +- xtask/src/main.rs | 41 +- 14 files changed, 345048 insertions(+), 5 deletions(-) create mode 100644 esp32/svd/esp32.svd.yaml create mode 100644 esp32c2/svd/esp32c2.svd.yaml create mode 100644 esp32c3/svd/esp32c3.svd.yaml create mode 100644 esp32c6-lp/svd/esp32c6-lp.svd.yaml create mode 100644 esp32c6/svd/esp32c6.svd.yaml create mode 100644 esp32h2/svd/esp32h2.svd.yaml create mode 100644 esp32p4/svd/esp32p4.svd.yaml create mode 100644 esp32s2-ulp/svd/esp32s2-ulp.svd.yaml create mode 100644 esp32s2/svd/esp32s2.svd.yaml create mode 100644 esp32s3-ulp/svd/esp32s3-ulp.svd.yaml create mode 100644 esp32s3/svd/esp32s3.svd.yaml diff --git a/esp32/svd/esp32.svd.yaml b/esp32/svd/esp32.svd.yaml new file mode 100644 index 0000000000..45784c84d9 --- /dev/null +++ b/esp32/svd/esp32.svd.yaml @@ -0,0 +1,31810 @@ +--- +vendor: "ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD." +vendorID: ESPRESSIF +name: ESP32 +series: ESP32 Series +version: "16" +description: 32-bit MCU & 2.4 GHz Wi-Fi & Bluetooth/Bluetooth LE +licenseText: "Copyright 2024 Espressif Systems (Shanghai) PTE LTD\n\n Licensed under the Apache License, Version 2.0 (the \"License\");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an \"AS IS\" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License." +cpu: + name: Xtensa LX6 + revision: r0p0 + endian: little + mpuPresent: false + fpuPresent: true + nvicPrioBits: 0 + vendorSystickConfig: false +addressUnitBits: 32 +width: 32 +resetValue: 0 +resetMask: 4294967295 +peripherals: + - name: AES + description: AES (Advanced Encryption Standard) Accelerator + groupName: AES + baseAddress: 1072697344 + addressBlock: + - offset: 0 + size: 64 + usage: registers + registers: + - register: + name: START + addressOffset: 0 + size: 32 + fields: + - name: START + description: Write 1 to start the AES operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: IDLE + addressOffset: 4 + size: 32 + fields: + - name: IDLE + description: AES Idle register. Reads ’zero’ while the AES Accelerator is busy processing; reads ’one’ otherwise. + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: MODE + addressOffset: 8 + size: 32 + fields: + - name: MODE + description: Selects the AES accelerator mode of operation. See Table 22-1 for details. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + name: "KEY[%s]" + addressOffset: 16 + size: 32 + fields: + - name: KEY + description: AES key material register. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: "TEXT[%s]" + addressOffset: 48 + size: 32 + fields: + - name: TEXT + description: Plaintext and ciphertext register. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: ENDIAN + addressOffset: 64 + size: 32 + fields: + - name: ENDIAN + description: Endianness selection register. See Table 22-2 for details. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: APB_CTRL + description: APB (Advanced Peripheral Bus) Controller + groupName: APB_CTRL + baseAddress: 1073111040 + addressBlock: + - offset: 0 + size: 68 + usage: registers + registers: + - register: + name: SYSCLK_CONF + addressOffset: 0 + size: 32 + resetValue: 8192 + fields: + - name: PRE_DIV_CNT + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: CLK_320M_EN + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CLK_EN + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RST_TICK_CNT + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: QUICK_CLK_CHNG + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: XTAL_TICK_CONF + addressOffset: 4 + size: 32 + resetValue: 39 + fields: + - name: XTAL_TICK_NUM + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: PLL_TICK_CONF + addressOffset: 8 + size: 32 + resetValue: 79 + fields: + - name: PLL_TICK_NUM + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CK8M_TICK_CONF + addressOffset: 12 + size: 32 + resetValue: 11 + fields: + - name: CK8M_TICK_NUM + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: APB_SARADC_CTRL + addressOffset: 16 + size: 32 + resetValue: 8356416 + fields: + - name: SARADC_START_FORCE + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SARADC_START + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SARADC_SAR2_MUX + description: "1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SARADC_WORK_MODE + description: "0: single mode 1: double mode 2: alternate mode" + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: SARADC_SAR_SEL + description: "0: SAR1 1: SAR2 only work for single SAR mode" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SARADC_SAR_CLK_GATED + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SARADC_SAR_CLK_DIV + description: SAR clock divider + bitOffset: 7 + bitWidth: 8 + access: read-write + - name: SARADC_SAR1_PATT_LEN + description: 0 ~ 15 means length 1 ~ 16 + bitOffset: 15 + bitWidth: 4 + access: read-write + - name: SARADC_SAR2_PATT_LEN + description: 0 ~ 15 means length 1 ~ 16 + bitOffset: 19 + bitWidth: 4 + access: read-write + - name: SARADC_SAR1_PATT_P_CLEAR + description: clear the pointer of pattern table for DIG ADC1 CTRL + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SARADC_SAR2_PATT_P_CLEAR + description: clear the pointer of pattern table for DIG ADC2 CTRL + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SARADC_DATA_SAR_SEL + description: "1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: SARADC_DATA_TO_I2S + description: "1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix" + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: APB_SARADC_CTRL2 + addressOffset: 20 + size: 32 + resetValue: 510 + fields: + - name: SARADC_MEAS_NUM_LIMIT + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SARADC_MAX_MEAS_NUM + description: max conversion number + bitOffset: 1 + bitWidth: 8 + access: read-write + - name: SARADC_SAR1_INV + description: "1: data to DIG ADC1 CTRL is inverted otherwise not" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SARADC_SAR2_INV + description: "1: data to DIG ADC2 CTRL is inverted otherwise not" + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: APB_SARADC_FSM + addressOffset: 24 + size: 32 + resetValue: 34144008 + fields: + - name: SARADC_RSTB_WAIT + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SARADC_STANDBY_WAIT + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SARADC_START_WAIT + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SARADC_SAMPLE_CYCLE + description: sample cycles + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + dimIndex: "1,2,3,4" + name: APB_SARADC_SAR1_PATT_TAB%s + addressOffset: 28 + size: 32 + resetValue: 252645135 + fields: + - name: SARADC_SAR1_PATT_TAB1 + description: item 0 ~ 3 for pattern table 1 (each item one byte) + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + dimIndex: "1,2,3,4" + name: APB_SARADC_SAR2_PATT_TAB%s + addressOffset: 44 + size: 32 + resetValue: 252645135 + fields: + - name: SARADC_SAR2_PATT_TAB1 + description: item 0 ~ 3 for pattern table 2 (each item one byte) + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: APLL_TICK_CONF + addressOffset: 60 + size: 32 + resetValue: 99 + fields: + - name: APLL_TICK_NUM + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATE + addressOffset: 124 + size: 32 + resetValue: 369369088 + fields: + - name: DATE + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: BB + description: BB Peripheral + groupName: BB + baseAddress: 1073074176 + addressBlock: + - offset: 0 + size: 4 + usage: registers + registers: + - register: + name: BBPD_CTRL + description: Baseband control register + addressOffset: 84 + size: 32 + fields: + - name: DC_EST_FORCE_PD + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DC_EST_FORCE_PU + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FFT_FORCE_PD + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FFT_FORCE_PU + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DPORT + description: DPORT Peripheral + groupName: DPORT + baseAddress: 1072693248 + addressBlock: + - offset: 0 + size: 1472 + usage: registers + interrupt: + - name: WIFI_MAC + value: 0 + - name: WIFI_NMI + value: 1 + - name: WIFI_BB + value: 2 + - name: BT_MAC + value: 3 + - name: BT_BB + value: 4 + - name: BT_BB_NMI + value: 5 + - name: RWBT + value: 6 + - name: RWBLE + value: 7 + - name: RWBT_NMI + value: 8 + - name: RWBLE_NMI + value: 9 + - name: FROM_CPU_INTR0 + value: 24 + - name: FROM_CPU_INTR1 + value: 25 + - name: FROM_CPU_INTR2 + value: 26 + - name: FROM_CPU_INTR3 + value: 27 + - name: SDIO_HOST + value: 37 + - name: ETH_MAC + value: 38 + - name: WDT + value: 55 + - name: MMU_IA + value: 66 + - name: MPU_IA + value: 67 + - name: CACHE_IA + value: 68 + registers: + - register: + name: PRO_BOOT_REMAP_CTRL + addressOffset: 0 + size: 32 + fields: + - name: PRO_BOOT_REMAP + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: APP_BOOT_REMAP_CTRL + addressOffset: 4 + size: 32 + fields: + - name: APP_BOOT_REMAP + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: ACCESS_CHECK + addressOffset: 8 + size: 32 + fields: + - name: PRO + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: APP + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: PRO_DPORT_APB_MASK0 + addressOffset: 12 + size: 32 + fields: + - name: PRODPORT_APB_MASK0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PRO_DPORT_APB_MASK1 + addressOffset: 16 + size: 32 + fields: + - name: PRODPORT_APB_MASK1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: APP_DPORT_APB_MASK0 + addressOffset: 20 + size: 32 + fields: + - name: APPDPORT_APB_MASK0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: APP_DPORT_APB_MASK1 + addressOffset: 24 + size: 32 + fields: + - name: APPDPORT_APB_MASK1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PERI_CLK_EN + addressOffset: 28 + size: 32 + fields: + - name: PERI_CLK_EN + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PERI_RST_EN + addressOffset: 32 + size: 32 + fields: + - name: PERI_RST_EN + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WIFI_BB_CFG + addressOffset: 36 + size: 32 + fields: + - name: WIFI_BB_CFG + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WIFI_BB_CFG_2 + addressOffset: 40 + size: 32 + fields: + - name: WIFI_BB_CFG_2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: APPCPU_CTRL_A + addressOffset: 44 + size: 32 + resetValue: 1 + fields: + - name: APPCPU_RESETTING + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: APPCPU_CTRL_B + addressOffset: 48 + size: 32 + fields: + - name: APPCPU_CLKGATE_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: APPCPU_CTRL_C + addressOffset: 52 + size: 32 + fields: + - name: APPCPU_RUNSTALL + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: APPCPU_CTRL_D + addressOffset: 56 + size: 32 + fields: + - name: APPCPU_BOOT_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CPU_PER_CONF + addressOffset: 60 + size: 32 + fields: + - name: CPUPERIOD_SEL + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: LOWSPEED_CLK_SEL + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FAST_CLK_RTC_SEL + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: PRO_CACHE_CTRL + addressOffset: 64 + size: 32 + resetValue: 16 + fields: + - name: PRO_CACHE_MODE + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_ENABLE + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_FLUSH_ENA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_FLUSH_DONE + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: PRO_CACHE_LOCK_0_EN + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_LOCK_1_EN + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_LOCK_2_EN + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_LOCK_3_EN + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PRO_SINGLE_IRAM_ENA + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: PRO_DRAM_SPLIT + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: PRO_AHB_SPI_REQ + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: PRO_SLAVE_REQ + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: AHB_SPI_REQ + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SLAVE_REQ + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: PRO_DRAM_HL + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: PRO_CACHE_CTRL1 + addressOffset: 68 + size: 32 + resetValue: 2303 + fields: + - name: PRO_CACHE_MASK_IRAM0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_MASK_IRAM1 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_MASK_IROM0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_MASK_DRAM1 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_MASK_DROM0 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_MASK_OPSDRAM + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: PRO_CMMU_SRAM_PAGE_MODE + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: PRO_CMMU_FLASH_PAGE_MODE + bitOffset: 9 + bitWidth: 2 + access: read-write + - name: PRO_CMMU_FORCE_ON + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: PRO_CMMU_PD + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_MMU_IA_CLR + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: PRO_CACHE_LOCK_0_ADDR + addressOffset: 72 + size: 32 + fields: + - name: PRE + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: MIN + bitOffset: 14 + bitWidth: 4 + access: read-write + - name: MAX + bitOffset: 18 + bitWidth: 4 + access: read-write + - register: + name: PRO_CACHE_LOCK_1_ADDR + addressOffset: 76 + size: 32 + fields: + - name: PRE + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: MIN + bitOffset: 14 + bitWidth: 4 + access: read-write + - name: MAX + bitOffset: 18 + bitWidth: 4 + access: read-write + - register: + name: PRO_CACHE_LOCK_2_ADDR + addressOffset: 80 + size: 32 + fields: + - name: PRE + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: MIN + bitOffset: 14 + bitWidth: 4 + access: read-write + - name: MAX + bitOffset: 18 + bitWidth: 4 + access: read-write + - register: + name: PRO_CACHE_LOCK_3_ADDR + addressOffset: 84 + size: 32 + fields: + - name: PRE + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: MIN + bitOffset: 14 + bitWidth: 4 + access: read-write + - name: MAX + bitOffset: 18 + bitWidth: 4 + access: read-write + - register: + name: APP_CACHE_CTRL + addressOffset: 88 + size: 32 + resetValue: 16 + fields: + - name: APP_CACHE_MODE + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: APP_CACHE_ENABLE + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: APP_CACHE_FLUSH_ENA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: APP_CACHE_FLUSH_DONE + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: APP_CACHE_LOCK_0_EN + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: APP_CACHE_LOCK_1_EN + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: APP_CACHE_LOCK_2_EN + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: APP_CACHE_LOCK_3_EN + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: APP_SINGLE_IRAM_ENA + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: APP_DRAM_SPLIT + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: APP_AHB_SPI_REQ + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: APP_SLAVE_REQ + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: APP_DRAM_HL + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: APP_CACHE_CTRL1 + addressOffset: 92 + size: 32 + resetValue: 2303 + fields: + - name: APP_CACHE_MASK_IRAM0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: APP_CACHE_MASK_IRAM1 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: APP_CACHE_MASK_IROM0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: APP_CACHE_MASK_DRAM1 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: APP_CACHE_MASK_DROM0 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: APP_CACHE_MASK_OPSDRAM + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: APP_CMMU_SRAM_PAGE_MODE + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: APP_CMMU_FLASH_PAGE_MODE + bitOffset: 9 + bitWidth: 2 + access: read-write + - name: APP_CMMU_FORCE_ON + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: APP_CMMU_PD + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: APP_CACHE_MMU_IA_CLR + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: APP_CACHE_LOCK_0_ADDR + addressOffset: 96 + size: 32 + fields: + - name: PRE + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: MIN + bitOffset: 14 + bitWidth: 4 + access: read-write + - name: MAX + bitOffset: 18 + bitWidth: 4 + access: read-write + - register: + name: APP_CACHE_LOCK_1_ADDR + addressOffset: 100 + size: 32 + fields: + - name: PRE + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: MIN + bitOffset: 14 + bitWidth: 4 + access: read-write + - name: MAX + bitOffset: 18 + bitWidth: 4 + access: read-write + - register: + name: APP_CACHE_LOCK_2_ADDR + addressOffset: 104 + size: 32 + fields: + - name: PRE + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: MIN + bitOffset: 14 + bitWidth: 4 + access: read-write + - name: MAX + bitOffset: 18 + bitWidth: 4 + access: read-write + - register: + name: APP_CACHE_LOCK_3_ADDR + addressOffset: 108 + size: 32 + fields: + - name: PRE + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: MIN + bitOffset: 14 + bitWidth: 4 + access: read-write + - name: MAX + bitOffset: 18 + bitWidth: 4 + access: read-write + - register: + name: TRACEMEM_MUX_MODE + addressOffset: 112 + size: 32 + fields: + - name: TRACEMEM_MUX_MODE + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: PRO_TRACEMEM_ENA + addressOffset: 116 + size: 32 + fields: + - name: PRO_TRACEMEM_ENA + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: APP_TRACEMEM_ENA + addressOffset: 120 + size: 32 + fields: + - name: APP_TRACEMEM_ENA + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CACHE_MUX_MODE + addressOffset: 124 + size: 32 + fields: + - name: CACHE_MUX_MODE + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: IMMU_PAGE_MODE + addressOffset: 128 + size: 32 + fields: + - name: INTERNAL_SRAM_IMMU_ENA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IMMU_PAGE_MODE + bitOffset: 1 + bitWidth: 2 + access: read-write + - register: + name: DMMU_PAGE_MODE + addressOffset: 132 + size: 32 + fields: + - name: INTERNAL_SRAM_DMMU_ENA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DMMU_PAGE_MODE + bitOffset: 1 + bitWidth: 2 + access: read-write + - register: + name: ROM_MPU_ENA + addressOffset: 136 + size: 32 + fields: + - name: SHARE_ROM_MPU_ENA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_ROM_MPU_ENA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: APP_ROM_MPU_ENA + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: MEM_PD_MASK + addressOffset: 140 + size: 32 + resetValue: 1 + fields: + - name: LSLP_MEM_PD_MASK + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: ROM_PD_CTRL + addressOffset: 144 + size: 32 + fields: + - name: PRO_ROM_PD + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: APP_ROM_PD + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SHARE_ROM_PD + bitOffset: 2 + bitWidth: 6 + access: read-write + - register: + name: ROM_FO_CTRL + addressOffset: 148 + size: 32 + resetValue: 3 + fields: + - name: PRO_ROM_FO + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: APP_ROM_FO + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SHARE_ROM_FO + bitOffset: 2 + bitWidth: 6 + access: read-write + - register: + name: SRAM_PD_CTRL_0 + addressOffset: 152 + size: 32 + fields: + - name: SRAM_PD_0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SRAM_PD_CTRL_1 + addressOffset: 156 + size: 32 + fields: + - name: SRAM_PD_1 + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SRAM_FO_CTRL_0 + addressOffset: 160 + size: 32 + resetValue: 4294967295 + fields: + - name: SRAM_FO_0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SRAM_FO_CTRL_1 + addressOffset: 164 + size: 32 + resetValue: 1 + fields: + - name: SRAM_FO_1 + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: IRAM_DRAM_AHB_SEL + addressOffset: 168 + size: 32 + fields: + - name: MASK_PRO_IRAM + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MASK_APP_IRAM + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MASK_PRO_DRAM + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MASK_APP_DRAM + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MASK_AHB + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MAC_DUMP_MODE + bitOffset: 5 + bitWidth: 2 + access: read-write + - register: + name: TAG_FO_CTRL + addressOffset: 172 + size: 32 + resetValue: 257 + fields: + - name: PRO_CACHE_TAG_FORCE_ON + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_TAG_PD + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: APP_CACHE_TAG_FORCE_ON + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: APP_CACHE_TAG_PD + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: AHB_LITE_MASK + addressOffset: 176 + size: 32 + fields: + - name: PRO + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: APP + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SDIO + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: PRODPORT + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: APPDPORT + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: AHB_LITE_SDHOST_PID + bitOffset: 11 + bitWidth: 3 + access: read-write + - register: + name: AHB_MPU_TABLE_0 + addressOffset: 180 + size: 32 + resetValue: 4294967295 + fields: + - name: AHB_ACCESS_GRANT_0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: AHB_MPU_TABLE_1 + addressOffset: 184 + size: 32 + resetValue: 511 + fields: + - name: AHB_ACCESS_GRANT_1 + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: HOST_INF_SEL + addressOffset: 188 + size: 32 + fields: + - name: PERI_IO_SWAP + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: LINK_DEVICE_SEL + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: PERIP_CLK_EN + addressOffset: 192 + size: 32 + resetValue: 4190232687 + fields: + - name: TIMERS_CLK_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI01_CLK_EN + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UART_CLK_EN + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: WDG_CLK_EN + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: I2S0_CLK_EN + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: UART1_CLK_EN + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI2_CLK_EN + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: I2C0_EXT0_CLK_EN + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: UHCI0_CLK_EN + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RMT_CLK_EN + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PCNT_CLK_EN + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: LEDC_CLK_EN + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: UHCI1_CLK_EN + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TIMERGROUP_CLK_EN + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: EFUSE_CLK_EN + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TIMERGROUP1_CLK_EN + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI3_CLK_EN + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PWM0_CLK_EN + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: I2C_EXT1_CLK_EN + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TWAI_CLK_EN + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PWM1_CLK_EN + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: I2S1_CLK_EN + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_DMA_CLK_EN + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: UART2_CLK_EN + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: UART_MEM_CLK_EN + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PWM2_CLK_EN + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PWM3_CLK_EN + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: PERIP_RST_EN + addressOffset: 196 + size: 32 + fields: + - name: TIMERS_RST + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI01_RST + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UART_RST + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: WDG_RST + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: I2S0_RST + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: UART1_RST + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI2_RST + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: I2C0_EXT0_RST + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: UHCI0_RST + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RMT_RST + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PCNT_RST + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: LEDC_RST + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: UHCI1_RST + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TIMERGROUP_RST + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: EFUSE_RST + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TIMERGROUP1_RST + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI3_RST + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PWM0_RST + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: I2C_EXT1_RST + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TWAI_RST + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PWM1_RST + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: I2S1_RST + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_DMA_RST + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: UART2_RST + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: UART_MEM_RST + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PWM2_RST + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PWM3_RST + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: SLAVE_SPI_CONFIG + addressOffset: 200 + size: 32 + fields: + - name: SLAVE_SPI_MASK_PRO + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLAVE_SPI_MASK_APP + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_ENCRYPT_ENABLE + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SPI_DECRYPT_ENABLE + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: WIFI_CLK_EN + addressOffset: 204 + size: 32 + resetValue: 4294762544 + fields: + - name: WIFI_CLK_EN + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: WIFI_CLK_WIFI_EN + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: WIFI_CLK_WIFI_BT_COMMON + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: WIFI_CLK_BT_EN + bitOffset: 11 + bitWidth: 3 + access: read-write + - register: + name: CORE_RST_EN + addressOffset: 208 + size: 32 + fields: + - name: CORE_RST + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: BT_LPCK_DIV_INT + addressOffset: 212 + size: 32 + resetValue: 255 + fields: + - name: BT_LPCK_DIV_NUM + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: BTEXTWAKEUP_REQ + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: BT_LPCK_DIV_FRAC + addressOffset: 216 + size: 32 + resetValue: 33558529 + fields: + - name: BT_LPCK_DIV_B + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: BT_LPCK_DIV_A + bitOffset: 12 + bitWidth: 12 + access: read-write + - name: LPCLK_SEL_RTC_SLOW + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: LPCLK_SEL_8M + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LPCLK_SEL_XTAL + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LPCLK_SEL_XTAL32K + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_0 + addressOffset: 220 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_1 + addressOffset: 224 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_1 + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_2 + addressOffset: 228 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_2 + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_3 + addressOffset: 232 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_3 + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: PRO_INTR_STATUS_0 + addressOffset: 236 + size: 32 + fields: + - name: PRO_INTR_STATUS_0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PRO_INTR_STATUS_1 + addressOffset: 240 + size: 32 + fields: + - name: PRO_INTR_STATUS_1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PRO_INTR_STATUS_2 + addressOffset: 244 + size: 32 + fields: + - name: PRO_INTR_STATUS_2 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APP_INTR_STATUS_0 + addressOffset: 248 + size: 32 + fields: + - name: APP_INTR_STATUS_0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APP_INTR_STATUS_1 + addressOffset: 252 + size: 32 + fields: + - name: APP_INTR_STATUS_1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APP_INTR_STATUS_2 + addressOffset: 256 + size: 32 + fields: + - name: APP_INTR_STATUS_2 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PRO_MAC_INTR_MAP + addressOffset: 260 + size: 32 + resetValue: 16 + fields: + - name: PRO_MAC_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_MAC_NMI_MAP + addressOffset: 264 + size: 32 + resetValue: 16 + fields: + - name: PRO_MAC_NMI_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_BB_INT_MAP + addressOffset: 268 + size: 32 + resetValue: 16 + fields: + - name: PRO_BB_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_BT_MAC_INT_MAP + addressOffset: 272 + size: 32 + resetValue: 16 + fields: + - name: PRO_BT_MAC_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_BT_BB_INT_MAP + addressOffset: 276 + size: 32 + resetValue: 16 + fields: + - name: PRO_BT_BB_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_BT_BB_NMI_MAP + addressOffset: 280 + size: 32 + resetValue: 16 + fields: + - name: PRO_BT_BB_NMI_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_RWBT_IRQ_MAP + addressOffset: 284 + size: 32 + resetValue: 16 + fields: + - name: PRO_RWBT_IRQ_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_RWBLE_IRQ_MAP + addressOffset: 288 + size: 32 + resetValue: 16 + fields: + - name: PRO_RWBLE_IRQ_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_RWBT_NMI_MAP + addressOffset: 292 + size: 32 + resetValue: 16 + fields: + - name: PRO_RWBT_NMI_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_RWBLE_NMI_MAP + addressOffset: 296 + size: 32 + resetValue: 16 + fields: + - name: PRO_RWBLE_NMI_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SLC0_INTR_MAP + addressOffset: 300 + size: 32 + resetValue: 16 + fields: + - name: PRO_SLC0_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SLC1_INTR_MAP + addressOffset: 304 + size: 32 + resetValue: 16 + fields: + - name: PRO_SLC1_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_UHCI0_INTR_MAP + addressOffset: 308 + size: 32 + resetValue: 16 + fields: + - name: PRO_UHCI0_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_UHCI1_INTR_MAP + addressOffset: 312 + size: 32 + resetValue: 16 + fields: + - name: PRO_UHCI1_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG_T0_LEVEL_INT_MAP + addressOffset: 316 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG_T0_LEVEL_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG_T1_LEVEL_INT_MAP + addressOffset: 320 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG_T1_LEVEL_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG_WDT_LEVEL_INT_MAP + addressOffset: 324 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG_WDT_LEVEL_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG_LACT_LEVEL_INT_MAP + addressOffset: 328 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG_LACT_LEVEL_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG1_T0_LEVEL_INT_MAP + addressOffset: 332 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG1_T0_LEVEL_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG1_T1_LEVEL_INT_MAP + addressOffset: 336 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG1_T1_LEVEL_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG1_WDT_LEVEL_INT_MAP + addressOffset: 340 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG1_WDT_LEVEL_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG1_LACT_LEVEL_INT_MAP + addressOffset: 344 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG1_LACT_LEVEL_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_GPIO_INTERRUPT_MAP + addressOffset: 348 + size: 32 + resetValue: 16 + fields: + - name: PRO_GPIO_INTERRUPT_PRO_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_GPIO_INTERRUPT_NMI_MAP + addressOffset: 352 + size: 32 + resetValue: 16 + fields: + - name: PRO_GPIO_INTERRUPT_PRO_NMI_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_CPU_INTR_FROM_CPU_0_MAP + addressOffset: 356 + size: 32 + resetValue: 16 + fields: + - name: PRO_CPU_INTR_FROM_CPU_0_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_CPU_INTR_FROM_CPU_1_MAP + addressOffset: 360 + size: 32 + resetValue: 16 + fields: + - name: PRO_CPU_INTR_FROM_CPU_1_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_CPU_INTR_FROM_CPU_2_MAP + addressOffset: 364 + size: 32 + resetValue: 16 + fields: + - name: PRO_CPU_INTR_FROM_CPU_2_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_CPU_INTR_FROM_CPU_3_MAP + addressOffset: 368 + size: 32 + resetValue: 16 + fields: + - name: PRO_CPU_INTR_FROM_CPU_3_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SPI_INTR_0_MAP + addressOffset: 372 + size: 32 + resetValue: 16 + fields: + - name: PRO_SPI_INTR_0_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SPI_INTR_1_MAP + addressOffset: 376 + size: 32 + resetValue: 16 + fields: + - name: PRO_SPI_INTR_1_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SPI_INTR_2_MAP + addressOffset: 380 + size: 32 + resetValue: 16 + fields: + - name: PRO_SPI_INTR_2_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SPI_INTR_3_MAP + addressOffset: 384 + size: 32 + resetValue: 16 + fields: + - name: PRO_SPI_INTR_3_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_I2S0_INT_MAP + addressOffset: 388 + size: 32 + resetValue: 16 + fields: + - name: PRO_I2S0_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_I2S1_INT_MAP + addressOffset: 392 + size: 32 + resetValue: 16 + fields: + - name: PRO_I2S1_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_UART_INTR_MAP + addressOffset: 396 + size: 32 + resetValue: 16 + fields: + - name: PRO_UART_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_UART1_INTR_MAP + addressOffset: 400 + size: 32 + resetValue: 16 + fields: + - name: PRO_UART1_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_UART2_INTR_MAP + addressOffset: 404 + size: 32 + resetValue: 16 + fields: + - name: PRO_UART2_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SDIO_HOST_INTERRUPT_MAP + addressOffset: 408 + size: 32 + resetValue: 16 + fields: + - name: PRO_SDIO_HOST_INTERRUPT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_EMAC_INT_MAP + addressOffset: 412 + size: 32 + resetValue: 16 + fields: + - name: PRO_EMAC_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_PWM0_INTR_MAP + addressOffset: 416 + size: 32 + resetValue: 16 + fields: + - name: PRO_PWM0_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_PWM1_INTR_MAP + addressOffset: 420 + size: 32 + resetValue: 16 + fields: + - name: PRO_PWM1_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_PWM2_INTR_MAP + addressOffset: 424 + size: 32 + resetValue: 16 + fields: + - name: PRO_PWM2_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_PWM3_INTR_MAP + addressOffset: 428 + size: 32 + resetValue: 16 + fields: + - name: PRO_PWM3_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_LEDC_INT_MAP + addressOffset: 432 + size: 32 + resetValue: 16 + fields: + - name: PRO_LEDC_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_EFUSE_INT_MAP + addressOffset: 436 + size: 32 + resetValue: 16 + fields: + - name: PRO_EFUSE_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_CAN_INT_MAP + addressOffset: 440 + size: 32 + resetValue: 16 + fields: + - name: PRO_CAN_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_RTC_CORE_INTR_MAP + addressOffset: 444 + size: 32 + resetValue: 16 + fields: + - name: PRO_RTC_CORE_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_RMT_INTR_MAP + addressOffset: 448 + size: 32 + resetValue: 16 + fields: + - name: PRO_RMT_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_PCNT_INTR_MAP + addressOffset: 452 + size: 32 + resetValue: 16 + fields: + - name: PRO_PCNT_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_I2C_EXT0_INTR_MAP + addressOffset: 456 + size: 32 + resetValue: 16 + fields: + - name: PRO_I2C_EXT0_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_I2C_EXT1_INTR_MAP + addressOffset: 460 + size: 32 + resetValue: 16 + fields: + - name: PRO_I2C_EXT1_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_RSA_INTR_MAP + addressOffset: 464 + size: 32 + resetValue: 16 + fields: + - name: PRO_RSA_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SPI1_DMA_INT_MAP + addressOffset: 468 + size: 32 + resetValue: 16 + fields: + - name: PRO_SPI1_DMA_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SPI2_DMA_INT_MAP + addressOffset: 472 + size: 32 + resetValue: 16 + fields: + - name: PRO_SPI2_DMA_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SPI3_DMA_INT_MAP + addressOffset: 476 + size: 32 + resetValue: 16 + fields: + - name: PRO_SPI3_DMA_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_WDG_INT_MAP + addressOffset: 480 + size: 32 + resetValue: 16 + fields: + - name: PRO_WDG_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TIMER_INT1_MAP + addressOffset: 484 + size: 32 + resetValue: 16 + fields: + - name: PRO_TIMER_INT1_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TIMER_INT2_MAP + addressOffset: 488 + size: 32 + resetValue: 16 + fields: + - name: PRO_TIMER_INT2_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG_T0_EDGE_INT_MAP + addressOffset: 492 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG_T0_EDGE_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG_T1_EDGE_INT_MAP + addressOffset: 496 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG_T1_EDGE_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG_WDT_EDGE_INT_MAP + addressOffset: 500 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG_WDT_EDGE_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG_LACT_EDGE_INT_MAP + addressOffset: 504 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG_LACT_EDGE_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG1_T0_EDGE_INT_MAP + addressOffset: 508 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG1_T0_EDGE_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG1_T1_EDGE_INT_MAP + addressOffset: 512 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG1_T1_EDGE_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG1_WDT_EDGE_INT_MAP + addressOffset: 516 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG1_WDT_EDGE_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG1_LACT_EDGE_INT_MAP + addressOffset: 520 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG1_LACT_EDGE_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_MMU_IA_INT_MAP + addressOffset: 524 + size: 32 + resetValue: 16 + fields: + - name: PRO_MMU_IA_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_MPU_IA_INT_MAP + addressOffset: 528 + size: 32 + resetValue: 16 + fields: + - name: PRO_MPU_IA_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_CACHE_IA_INT_MAP + addressOffset: 532 + size: 32 + resetValue: 16 + fields: + - name: PRO_CACHE_IA_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_MAC_INTR_MAP + addressOffset: 536 + size: 32 + resetValue: 16 + fields: + - name: APP_MAC_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_MAC_NMI_MAP + addressOffset: 540 + size: 32 + resetValue: 16 + fields: + - name: APP_MAC_NMI_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_BB_INT_MAP + addressOffset: 544 + size: 32 + resetValue: 16 + fields: + - name: APP_BB_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_BT_MAC_INT_MAP + addressOffset: 548 + size: 32 + resetValue: 16 + fields: + - name: APP_BT_MAC_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_BT_BB_INT_MAP + addressOffset: 552 + size: 32 + resetValue: 16 + fields: + - name: APP_BT_BB_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_BT_BB_NMI_MAP + addressOffset: 556 + size: 32 + resetValue: 16 + fields: + - name: APP_BT_BB_NMI_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_RWBT_IRQ_MAP + addressOffset: 560 + size: 32 + resetValue: 16 + fields: + - name: APP_RWBT_IRQ_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_RWBLE_IRQ_MAP + addressOffset: 564 + size: 32 + resetValue: 16 + fields: + - name: APP_RWBLE_IRQ_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_RWBT_NMI_MAP + addressOffset: 568 + size: 32 + resetValue: 16 + fields: + - name: APP_RWBT_NMI_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_RWBLE_NMI_MAP + addressOffset: 572 + size: 32 + resetValue: 16 + fields: + - name: APP_RWBLE_NMI_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_SLC0_INTR_MAP + addressOffset: 576 + size: 32 + resetValue: 16 + fields: + - name: APP_SLC0_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_SLC1_INTR_MAP + addressOffset: 580 + size: 32 + resetValue: 16 + fields: + - name: APP_SLC1_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_UHCI0_INTR_MAP + addressOffset: 584 + size: 32 + resetValue: 16 + fields: + - name: APP_UHCI0_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_UHCI1_INTR_MAP + addressOffset: 588 + size: 32 + resetValue: 16 + fields: + - name: APP_UHCI1_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_TG_T0_LEVEL_INT_MAP + addressOffset: 592 + size: 32 + resetValue: 16 + fields: + - name: APP_TG_T0_LEVEL_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_TG_T1_LEVEL_INT_MAP + addressOffset: 596 + size: 32 + resetValue: 16 + fields: + - name: APP_TG_T1_LEVEL_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_TG_WDT_LEVEL_INT_MAP + addressOffset: 600 + size: 32 + resetValue: 16 + fields: + - name: APP_TG_WDT_LEVEL_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_TG_LACT_LEVEL_INT_MAP + addressOffset: 604 + size: 32 + resetValue: 16 + fields: + - name: APP_TG_LACT_LEVEL_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_TG1_T0_LEVEL_INT_MAP + addressOffset: 608 + size: 32 + resetValue: 16 + fields: + - name: APP_TG1_T0_LEVEL_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_TG1_T1_LEVEL_INT_MAP + addressOffset: 612 + size: 32 + resetValue: 16 + fields: + - name: APP_TG1_T1_LEVEL_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_TG1_WDT_LEVEL_INT_MAP + addressOffset: 616 + size: 32 + resetValue: 16 + fields: + - name: APP_TG1_WDT_LEVEL_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_TG1_LACT_LEVEL_INT_MAP + addressOffset: 620 + size: 32 + resetValue: 16 + fields: + - name: APP_TG1_LACT_LEVEL_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_GPIO_INTERRUPT_MAP + addressOffset: 624 + size: 32 + resetValue: 16 + fields: + - name: APP_GPIO_INTERRUPT_APP_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_GPIO_INTERRUPT_NMI_MAP + addressOffset: 628 + size: 32 + resetValue: 16 + fields: + - name: APP_GPIO_INTERRUPT_APP_NMI_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_CPU_INTR_FROM_CPU_0_MAP + addressOffset: 632 + size: 32 + resetValue: 16 + fields: + - name: APP_CPU_INTR_FROM_CPU_0_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_CPU_INTR_FROM_CPU_1_MAP + addressOffset: 636 + size: 32 + resetValue: 16 + fields: + - name: APP_CPU_INTR_FROM_CPU_1_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_CPU_INTR_FROM_CPU_2_MAP + addressOffset: 640 + size: 32 + resetValue: 16 + fields: + - name: APP_CPU_INTR_FROM_CPU_2_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_CPU_INTR_FROM_CPU_3_MAP + addressOffset: 644 + size: 32 + resetValue: 16 + fields: + - name: APP_CPU_INTR_FROM_CPU_3_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_SPI_INTR_0_MAP + addressOffset: 648 + size: 32 + resetValue: 16 + fields: + - name: APP_SPI_INTR_0_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_SPI_INTR_1_MAP + addressOffset: 652 + size: 32 + resetValue: 16 + fields: + - name: APP_SPI_INTR_1_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_SPI_INTR_2_MAP + addressOffset: 656 + size: 32 + resetValue: 16 + fields: + - name: APP_SPI_INTR_2_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_SPI_INTR_3_MAP + addressOffset: 660 + size: 32 + resetValue: 16 + fields: + - name: APP_SPI_INTR_3_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_I2S0_INT_MAP + addressOffset: 664 + size: 32 + resetValue: 16 + fields: + - name: APP_I2S0_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_I2S1_INT_MAP + addressOffset: 668 + size: 32 + resetValue: 16 + fields: + - name: APP_I2S1_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_UART_INTR_MAP + addressOffset: 672 + size: 32 + resetValue: 16 + fields: + - name: APP_UART_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_UART1_INTR_MAP + addressOffset: 676 + size: 32 + resetValue: 16 + fields: + - name: APP_UART1_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_UART2_INTR_MAP + addressOffset: 680 + size: 32 + resetValue: 16 + fields: + - name: APP_UART2_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_SDIO_HOST_INTERRUPT_MAP + addressOffset: 684 + size: 32 + resetValue: 16 + fields: + - name: APP_SDIO_HOST_INTERRUPT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_EMAC_INT_MAP + addressOffset: 688 + size: 32 + resetValue: 16 + fields: + - name: APP_EMAC_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_PWM0_INTR_MAP + addressOffset: 692 + size: 32 + resetValue: 16 + fields: + - name: APP_PWM0_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_PWM1_INTR_MAP + addressOffset: 696 + size: 32 + resetValue: 16 + fields: + - name: APP_PWM1_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_PWM2_INTR_MAP + addressOffset: 700 + size: 32 + resetValue: 16 + fields: + - name: APP_PWM2_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_PWM3_INTR_MAP + addressOffset: 704 + size: 32 + resetValue: 16 + fields: + - name: APP_PWM3_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_LEDC_INT_MAP + addressOffset: 708 + size: 32 + resetValue: 16 + fields: + - name: APP_LEDC_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_EFUSE_INT_MAP + addressOffset: 712 + size: 32 + resetValue: 16 + fields: + - name: APP_EFUSE_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_CAN_INT_MAP + addressOffset: 716 + size: 32 + resetValue: 16 + fields: + - name: APP_CAN_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_RTC_CORE_INTR_MAP + addressOffset: 720 + size: 32 + resetValue: 16 + fields: + - name: APP_RTC_CORE_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_RMT_INTR_MAP + addressOffset: 724 + size: 32 + resetValue: 16 + fields: + - name: APP_RMT_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_PCNT_INTR_MAP + addressOffset: 728 + size: 32 + resetValue: 16 + fields: + - name: APP_PCNT_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_I2C_EXT0_INTR_MAP + addressOffset: 732 + size: 32 + resetValue: 16 + fields: + - name: APP_I2C_EXT0_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_I2C_EXT1_INTR_MAP + addressOffset: 736 + size: 32 + resetValue: 16 + fields: + - name: APP_I2C_EXT1_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_RSA_INTR_MAP + addressOffset: 740 + size: 32 + resetValue: 16 + fields: + - name: APP_RSA_INTR_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_SPI1_DMA_INT_MAP + addressOffset: 744 + size: 32 + resetValue: 16 + fields: + - name: APP_SPI1_DMA_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_SPI2_DMA_INT_MAP + addressOffset: 748 + size: 32 + resetValue: 16 + fields: + - name: APP_SPI2_DMA_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_SPI3_DMA_INT_MAP + addressOffset: 752 + size: 32 + resetValue: 16 + fields: + - name: APP_SPI3_DMA_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_WDG_INT_MAP + addressOffset: 756 + size: 32 + resetValue: 16 + fields: + - name: APP_WDG_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_TIMER_INT1_MAP + addressOffset: 760 + size: 32 + resetValue: 16 + fields: + - name: APP_TIMER_INT1_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_TIMER_INT2_MAP + addressOffset: 764 + size: 32 + resetValue: 16 + fields: + - name: APP_TIMER_INT2_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_TG_T0_EDGE_INT_MAP + addressOffset: 768 + size: 32 + resetValue: 16 + fields: + - name: APP_TG_T0_EDGE_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_TG_T1_EDGE_INT_MAP + addressOffset: 772 + size: 32 + resetValue: 16 + fields: + - name: APP_TG_T1_EDGE_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_TG_WDT_EDGE_INT_MAP + addressOffset: 776 + size: 32 + resetValue: 16 + fields: + - name: APP_TG_WDT_EDGE_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_TG_LACT_EDGE_INT_MAP + addressOffset: 780 + size: 32 + resetValue: 16 + fields: + - name: APP_TG_LACT_EDGE_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_TG1_T0_EDGE_INT_MAP + addressOffset: 784 + size: 32 + resetValue: 16 + fields: + - name: APP_TG1_T0_EDGE_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_TG1_T1_EDGE_INT_MAP + addressOffset: 788 + size: 32 + resetValue: 16 + fields: + - name: APP_TG1_T1_EDGE_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_TG1_WDT_EDGE_INT_MAP + addressOffset: 792 + size: 32 + resetValue: 16 + fields: + - name: APP_TG1_WDT_EDGE_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_TG1_LACT_EDGE_INT_MAP + addressOffset: 796 + size: 32 + resetValue: 16 + fields: + - name: APP_TG1_LACT_EDGE_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_MMU_IA_INT_MAP + addressOffset: 800 + size: 32 + resetValue: 16 + fields: + - name: APP_MMU_IA_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_MPU_IA_INT_MAP + addressOffset: 804 + size: 32 + resetValue: 16 + fields: + - name: APP_MPU_IA_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_CACHE_IA_INT_MAP + addressOffset: 808 + size: 32 + resetValue: 16 + fields: + - name: APP_CACHE_IA_INT_MAP + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_UART + addressOffset: 812 + size: 32 + fields: + - name: UART_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_SPI1 + addressOffset: 816 + size: 32 + fields: + - name: SPI1_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_SPI0 + addressOffset: 820 + size: 32 + fields: + - name: SPI0_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_GPIO + addressOffset: 824 + size: 32 + fields: + - name: GPIO_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_FE2 + addressOffset: 828 + size: 32 + fields: + - name: FE2_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_FE + addressOffset: 832 + size: 32 + fields: + - name: FE_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_TIMER + addressOffset: 836 + size: 32 + fields: + - name: TIMER_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_RTC + addressOffset: 840 + size: 32 + fields: + - name: RTC_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_IO_MUX + addressOffset: 844 + size: 32 + fields: + - name: IOMUX_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_WDG + addressOffset: 848 + size: 32 + fields: + - name: WDG_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_HINF + addressOffset: 852 + size: 32 + fields: + - name: HINF_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_UHCI1 + addressOffset: 856 + size: 32 + fields: + - name: UHCI1_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_MISC + addressOffset: 860 + size: 32 + fields: + - name: MISC_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_I2C + addressOffset: 864 + size: 32 + fields: + - name: I2C_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_I2S0 + addressOffset: 868 + size: 32 + fields: + - name: I2S0_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_UART1 + addressOffset: 872 + size: 32 + fields: + - name: UART1_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_BT + addressOffset: 876 + size: 32 + fields: + - name: BT_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_BT_BUFFER + addressOffset: 880 + size: 32 + fields: + - name: BTBUFFER_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_I2C_EXT0 + addressOffset: 884 + size: 32 + fields: + - name: I2CEXT0_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_UHCI0 + addressOffset: 888 + size: 32 + fields: + - name: UHCI0_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_SLCHOST + addressOffset: 892 + size: 32 + fields: + - name: SLCHOST_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_RMT + addressOffset: 896 + size: 32 + fields: + - name: RMT_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_PCNT + addressOffset: 900 + size: 32 + fields: + - name: PCNT_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_SLC + addressOffset: 904 + size: 32 + fields: + - name: SLC_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_LEDC + addressOffset: 908 + size: 32 + fields: + - name: LEDC_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_EFUSE + addressOffset: 912 + size: 32 + fields: + - name: EFUSE_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_SPI_ENCRYPT + addressOffset: 916 + size: 32 + fields: + - name: SPI_ENCRYPY_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_BB + addressOffset: 920 + size: 32 + fields: + - name: BB_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_PWM0 + addressOffset: 924 + size: 32 + fields: + - name: PWM0_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_TIMERGROUP + addressOffset: 928 + size: 32 + fields: + - name: TIMERGROUP_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_TIMERGROUP1 + addressOffset: 932 + size: 32 + fields: + - name: TIMERGROUP1_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_SPI2 + addressOffset: 936 + size: 32 + fields: + - name: SPI2_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_SPI3 + addressOffset: 940 + size: 32 + fields: + - name: SPI3_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_APB_CTRL + addressOffset: 944 + size: 32 + fields: + - name: APBCTRL_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_I2C_EXT1 + addressOffset: 948 + size: 32 + fields: + - name: I2CEXT1_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_SDIO_HOST + addressOffset: 952 + size: 32 + fields: + - name: SDIOHOST_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_EMAC + addressOffset: 956 + size: 32 + fields: + - name: EMAC_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_CAN + addressOffset: 960 + size: 32 + fields: + - name: CAN_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_PWM1 + addressOffset: 964 + size: 32 + fields: + - name: PWM1_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_I2S1 + addressOffset: 968 + size: 32 + fields: + - name: I2S1_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_UART2 + addressOffset: 972 + size: 32 + fields: + - name: UART2_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_PWM2 + addressOffset: 976 + size: 32 + fields: + - name: PWM2_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_PWM3 + addressOffset: 980 + size: 32 + fields: + - name: PWM3_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_RWBT + addressOffset: 984 + size: 32 + fields: + - name: RWBT_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_BTMAC + addressOffset: 988 + size: 32 + fields: + - name: BTMAC_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_WIFIMAC + addressOffset: 992 + size: 32 + fields: + - name: WIFIMAC_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHBLITE_MPU_TABLE_PWR + addressOffset: 996 + size: 32 + fields: + - name: PWR_ACCESS_GRANT_CONFIG + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: MEM_ACCESS_DBUG0 + addressOffset: 1000 + size: 32 + fields: + - name: PRO_ROM_MPU_AD + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PRO_ROM_IA + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: APP_ROM_MPU_AD + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: APP_ROM_IA + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SHARE_ROM_MPU_AD + bitOffset: 4 + bitWidth: 2 + access: read-only + - name: SHARE_ROM_IA + bitOffset: 6 + bitWidth: 4 + access: read-only + - name: INTERNAL_SRAM_MMU_AD + bitOffset: 10 + bitWidth: 4 + access: read-only + - name: INTERNAL_SRAM_IA + bitOffset: 14 + bitWidth: 12 + access: read-only + - name: INTERNAL_SRAM_MMU_MULTI_HIT + bitOffset: 26 + bitWidth: 4 + access: read-only + - register: + name: MEM_ACCESS_DBUG1 + addressOffset: 1004 + size: 32 + fields: + - name: INTERNAL_SRAM_MMU_MISS + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: ARB_IA + bitOffset: 4 + bitWidth: 2 + access: read-only + - name: PIDGEN_IA + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: AHB_ACCESS_DENY + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: AHBLITE_ACCESS_DENY + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: AHBLITE_IA + bitOffset: 10 + bitWidth: 1 + access: read-only + - register: + name: PRO_DCACHE_DBUG0 + addressOffset: 1008 + size: 32 + fields: + - name: PRO_SLAVE_WDATA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_MMU_IA + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PRO_CACHE_IA + bitOffset: 1 + bitWidth: 6 + access: read-only + - name: PRO_CACHE_STATE + bitOffset: 7 + bitWidth: 12 + access: read-only + - name: PRO_WR_BAK_TO_READ + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: PRO_TX_END + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: PRO_SLAVE_WR + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: PRO_SLAVE_WDATA_V + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: PRO_RX_END + bitOffset: 23 + bitWidth: 1 + access: read-only + - register: + name: PRO_DCACHE_DBUG1 + addressOffset: 1012 + size: 32 + fields: + - name: PRO_CTAG_RAM_RDATA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PRO_DCACHE_DBUG2 + addressOffset: 1016 + size: 32 + fields: + - name: PRO_CACHE_VADDR + bitOffset: 0 + bitWidth: 27 + access: read-only + - register: + name: PRO_DCACHE_DBUG3 + addressOffset: 1020 + size: 32 + fields: + - name: PRO_MMU_RDATA + bitOffset: 0 + bitWidth: 9 + access: read-only + - name: PRO_CPU_DISABLED_CACHE_IA + bitOffset: 9 + bitWidth: 6 + access: read-only + - name: PRO_CPU_DISABLED_CACHE_IA_OPPOSITE + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PRO_CPU_DISABLED_CACHE_IA_DRAM1 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: PRO_CPU_DISABLED_CACHE_IA_IROM0 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: PRO_CPU_DISABLED_CACHE_IA_IRAM1 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PRO_CPU_DISABLED_CACHE_IA_IRAM0 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: PRO_CPU_DISABLED_CACHE_IA_DROM0 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_IRAM0_PID_ERROR + bitOffset: 15 + bitWidth: 1 + access: read-only + - register: + name: PRO_DCACHE_DBUG4 + addressOffset: 1024 + size: 32 + fields: + - name: PRO_DRAM1ADDR0_IA + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: PRO_DCACHE_DBUG5 + addressOffset: 1028 + size: 32 + fields: + - name: PRO_DROM0ADDR0_IA + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: PRO_DCACHE_DBUG6 + addressOffset: 1032 + size: 32 + fields: + - name: PRO_IRAM0ADDR_IA + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: PRO_DCACHE_DBUG7 + addressOffset: 1036 + size: 32 + fields: + - name: PRO_IRAM1ADDR_IA + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: PRO_DCACHE_DBUG8 + addressOffset: 1040 + size: 32 + fields: + - name: PRO_IROM0ADDR_IA + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: PRO_DCACHE_DBUG9 + addressOffset: 1044 + size: 32 + fields: + - name: PRO_OPSDRAMADDR_IA + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: APP_DCACHE_DBUG0 + addressOffset: 1048 + size: 32 + fields: + - name: APP_SLAVE_WDATA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: APP_CACHE_MMU_IA + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: APP_CACHE_IA + bitOffset: 1 + bitWidth: 6 + access: read-only + - name: APP_CACHE_STATE + bitOffset: 7 + bitWidth: 12 + access: read-only + - name: APP_WR_BAK_TO_READ + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: APP_TX_END + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: APP_SLAVE_WR + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: APP_SLAVE_WDATA_V + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: APP_RX_END + bitOffset: 23 + bitWidth: 1 + access: read-only + - register: + name: APP_DCACHE_DBUG1 + addressOffset: 1052 + size: 32 + fields: + - name: APP_CTAG_RAM_RDATA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APP_DCACHE_DBUG2 + addressOffset: 1056 + size: 32 + fields: + - name: APP_CACHE_VADDR + bitOffset: 0 + bitWidth: 27 + access: read-only + - register: + name: APP_DCACHE_DBUG3 + addressOffset: 1060 + size: 32 + fields: + - name: APP_MMU_RDATA + bitOffset: 0 + bitWidth: 9 + access: read-only + - name: APP_CPU_DISABLED_CACHE_IA + bitOffset: 9 + bitWidth: 6 + access: read-only + - name: APP_CPU_DISABLED_CACHE_IA_OPPOSITE + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: APP_CPU_DISABLED_CACHE_IA_DRAM1 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: APP_CPU_DISABLED_CACHE_IA_IROM0 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: APP_CPU_DISABLED_CACHE_IA_IRAM1 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: APP_CPU_DISABLED_CACHE_IA_IRAM0 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: APP_CPU_DISABLED_CACHE_IA_DROM0 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: APP_CACHE_IRAM0_PID_ERROR + bitOffset: 15 + bitWidth: 1 + access: read-only + - register: + name: APP_DCACHE_DBUG4 + addressOffset: 1064 + size: 32 + fields: + - name: APP_DRAM1ADDR0_IA + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: APP_DCACHE_DBUG5 + addressOffset: 1068 + size: 32 + fields: + - name: APP_DROM0ADDR0_IA + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: APP_DCACHE_DBUG6 + addressOffset: 1072 + size: 32 + fields: + - name: APP_IRAM0ADDR_IA + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: APP_DCACHE_DBUG7 + addressOffset: 1076 + size: 32 + fields: + - name: APP_IRAM1ADDR_IA + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: APP_DCACHE_DBUG8 + addressOffset: 1080 + size: 32 + fields: + - name: APP_IROM0ADDR_IA + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: APP_DCACHE_DBUG9 + addressOffset: 1084 + size: 32 + fields: + - name: APP_OPSDRAMADDR_IA + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: PRO_CPU_RECORD_CTRL + addressOffset: 1088 + size: 32 + resetValue: 256 + fields: + - name: PRO_CPU_RECORD_ENABLE + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_CPU_RECORD_DISABLE + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: PRO_CPU_PDEBUG_ENABLE + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: PRO_CPU_RECORD_STATUS + addressOffset: 1092 + size: 32 + fields: + - name: PRO_CPU_RECORDING + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: PRO_CPU_RECORD_PID + addressOffset: 1096 + size: 32 + fields: + - name: RECORD_PRO_PID + bitOffset: 0 + bitWidth: 3 + access: read-only + - register: + name: PRO_CPU_RECORD_PDEBUGINST + addressOffset: 1100 + size: 32 + fields: + - name: RECORD_PRO_PDEBUGINST + bitOffset: 0 + bitWidth: 32 + access: read-only + - name: RECORD_PDEBUGINST_SZ + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: RECORD_PDEBUGINST_ISRC + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: RECORD_PDEBUGINST_LOOP_REP + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGINST_LOOP + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGINST_CINTL + bitOffset: 24 + bitWidth: 4 + access: read-write + - register: + name: PRO_CPU_RECORD_PDEBUGSTATUS + addressOffset: 1104 + size: 32 + fields: + - name: RECORD_PRO_PDEBUGSTATUS + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: RECORD_PDEBUGSTATUS_BBCAUSE + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: RECORD_PDEBUGSTATUS_INSNTYPE + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: PRO_CPU_RECORD_PDEBUGDATA + addressOffset: 1108 + size: 32 + fields: + - name: RECORD_PRO_PDEBUGDATA + bitOffset: 0 + bitWidth: 32 + access: read-only + - name: RECORD_PDEBUGDATA_DEP_OTHER + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_EXCVEC + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: RECORD_PDEBUGDATA_INSNTYPE_SR + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: RECORD_PDEBUGDATA_INSNTYPE_RER + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_STALL_BUFF + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_INSNTYPE_WER + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_STALL_BUFFCONFL + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_INSNTYPE_ER + bitOffset: 2 + bitWidth: 12 + access: read-write + - name: RECORD_PDEBUGDATA_STALL_DCM + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_STALL_LSU + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_STALL_ICM + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_STALL_IRAMBUSY + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_DEP_LSU + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_STALL_IPIF + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_INSNTYPE_RSR + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_STALL_TIE + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_INSNTYPE_WSR + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_STALL_RUN + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_INSNTYPE_XSR + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_DEP_STR + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_DEP + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_STALL_BPIFETCH + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_STALL_L32R + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_STALL_LSPROC + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_STALL_BPLOAD + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_DEP_MEMW + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_EXCCAUSE + bitOffset: 16 + bitWidth: 6 + access: read-write + - name: RECORD_PDEBUGDATA_STALL_BANKCONFL + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_DEP_HALT + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_STALL_ITERMUL + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGDATA_STALL_ITERDIV + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: PRO_CPU_RECORD_PDEBUGPC + addressOffset: 1112 + size: 32 + fields: + - name: RECORD_PRO_PDEBUGPC + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PRO_CPU_RECORD_PDEBUGLS0STAT + addressOffset: 1116 + size: 32 + fields: + - name: RECORD_PRO_PDEBUGLS0STAT + bitOffset: 0 + bitWidth: 32 + access: read-only + - name: RECORD_PDEBUGLS0STAT_TYPE + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: RECORD_PDEBUGLS0STAT_SZ + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: RECORD_PDEBUGLS0STAT_DTLBM + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGLS0STAT_DCM + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGLS0STAT_DCH + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGLS0STAT_UC + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGLS0STAT_WB + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGLS0STAT_COH + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RECORD_PDEBUGLS0STAT_STCOH + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: RECORD_PDEBUGLS0STAT_TGT + bitOffset: 20 + bitWidth: 4 + access: read-write + - register: + name: PRO_CPU_RECORD_PDEBUGLS0ADDR + addressOffset: 1120 + size: 32 + fields: + - name: RECORD_PRO_PDEBUGLS0ADDR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PRO_CPU_RECORD_PDEBUGLS0DATA + addressOffset: 1124 + size: 32 + fields: + - name: RECORD_PRO_PDEBUGLS0DATA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APP_CPU_RECORD_CTRL + addressOffset: 1128 + size: 32 + resetValue: 256 + fields: + - name: APP_CPU_RECORD_ENABLE + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: APP_CPU_RECORD_DISABLE + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: APP_CPU_PDEBUG_ENABLE + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: APP_CPU_RECORD_STATUS + addressOffset: 1132 + size: 32 + fields: + - name: APP_CPU_RECORDING + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: APP_CPU_RECORD_PID + addressOffset: 1136 + size: 32 + fields: + - name: RECORD_APP_PID + bitOffset: 0 + bitWidth: 3 + access: read-only + - register: + name: APP_CPU_RECORD_PDEBUGINST + addressOffset: 1140 + size: 32 + fields: + - name: RECORD_APP_PDEBUGINST + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APP_CPU_RECORD_PDEBUGSTATUS + addressOffset: 1144 + size: 32 + fields: + - name: RECORD_APP_PDEBUGSTATUS + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: APP_CPU_RECORD_PDEBUGDATA + addressOffset: 1148 + size: 32 + fields: + - name: RECORD_APP_PDEBUGDATA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APP_CPU_RECORD_PDEBUGPC + addressOffset: 1152 + size: 32 + fields: + - name: RECORD_APP_PDEBUGPC + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APP_CPU_RECORD_PDEBUGLS0STAT + addressOffset: 1156 + size: 32 + fields: + - name: RECORD_APP_PDEBUGLS0STAT + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APP_CPU_RECORD_PDEBUGLS0ADDR + addressOffset: 1160 + size: 32 + fields: + - name: RECORD_APP_PDEBUGLS0ADDR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APP_CPU_RECORD_PDEBUGLS0DATA + addressOffset: 1164 + size: 32 + fields: + - name: RECORD_APP_PDEBUGLS0DATA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RSA_PD_CTRL + addressOffset: 1168 + size: 32 + fields: + - name: RSA_PD + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: ROM_MPU_TABLE0 + addressOffset: 1172 + size: 32 + resetValue: 1 + fields: + - name: ROM_MPU_TABLE0 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: ROM_MPU_TABLE1 + addressOffset: 1176 + size: 32 + resetValue: 1 + fields: + - name: ROM_MPU_TABLE1 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: ROM_MPU_TABLE2 + addressOffset: 1180 + size: 32 + resetValue: 1 + fields: + - name: ROM_MPU_TABLE2 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: ROM_MPU_TABLE3 + addressOffset: 1184 + size: 32 + resetValue: 1 + fields: + - name: ROM_MPU_TABLE3 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SHROM_MPU_TABLE0 + addressOffset: 1188 + size: 32 + resetValue: 1 + fields: + - name: SHROM_MPU_TABLE0 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SHROM_MPU_TABLE1 + addressOffset: 1192 + size: 32 + resetValue: 1 + fields: + - name: SHROM_MPU_TABLE1 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SHROM_MPU_TABLE2 + addressOffset: 1196 + size: 32 + resetValue: 1 + fields: + - name: SHROM_MPU_TABLE2 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SHROM_MPU_TABLE3 + addressOffset: 1200 + size: 32 + resetValue: 1 + fields: + - name: SHROM_MPU_TABLE3 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SHROM_MPU_TABLE4 + addressOffset: 1204 + size: 32 + resetValue: 1 + fields: + - name: SHROM_MPU_TABLE4 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SHROM_MPU_TABLE5 + addressOffset: 1208 + size: 32 + resetValue: 1 + fields: + - name: SHROM_MPU_TABLE5 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SHROM_MPU_TABLE6 + addressOffset: 1212 + size: 32 + resetValue: 1 + fields: + - name: SHROM_MPU_TABLE6 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SHROM_MPU_TABLE7 + addressOffset: 1216 + size: 32 + resetValue: 1 + fields: + - name: SHROM_MPU_TABLE7 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SHROM_MPU_TABLE8 + addressOffset: 1220 + size: 32 + resetValue: 1 + fields: + - name: SHROM_MPU_TABLE8 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SHROM_MPU_TABLE9 + addressOffset: 1224 + size: 32 + resetValue: 1 + fields: + - name: SHROM_MPU_TABLE9 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SHROM_MPU_TABLE10 + addressOffset: 1228 + size: 32 + resetValue: 1 + fields: + - name: SHROM_MPU_TABLE10 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SHROM_MPU_TABLE11 + addressOffset: 1232 + size: 32 + resetValue: 1 + fields: + - name: SHROM_MPU_TABLE11 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SHROM_MPU_TABLE12 + addressOffset: 1236 + size: 32 + resetValue: 1 + fields: + - name: SHROM_MPU_TABLE12 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SHROM_MPU_TABLE13 + addressOffset: 1240 + size: 32 + resetValue: 1 + fields: + - name: SHROM_MPU_TABLE13 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SHROM_MPU_TABLE14 + addressOffset: 1244 + size: 32 + resetValue: 1 + fields: + - name: SHROM_MPU_TABLE14 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SHROM_MPU_TABLE15 + addressOffset: 1248 + size: 32 + resetValue: 1 + fields: + - name: SHROM_MPU_TABLE15 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SHROM_MPU_TABLE16 + addressOffset: 1252 + size: 32 + resetValue: 1 + fields: + - name: SHROM_MPU_TABLE16 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SHROM_MPU_TABLE17 + addressOffset: 1256 + size: 32 + resetValue: 1 + fields: + - name: SHROM_MPU_TABLE17 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SHROM_MPU_TABLE18 + addressOffset: 1260 + size: 32 + resetValue: 1 + fields: + - name: SHROM_MPU_TABLE18 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SHROM_MPU_TABLE19 + addressOffset: 1264 + size: 32 + resetValue: 1 + fields: + - name: SHROM_MPU_TABLE19 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SHROM_MPU_TABLE20 + addressOffset: 1268 + size: 32 + resetValue: 1 + fields: + - name: SHROM_MPU_TABLE20 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SHROM_MPU_TABLE21 + addressOffset: 1272 + size: 32 + resetValue: 1 + fields: + - name: SHROM_MPU_TABLE21 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SHROM_MPU_TABLE22 + addressOffset: 1276 + size: 32 + resetValue: 1 + fields: + - name: SHROM_MPU_TABLE22 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SHROM_MPU_TABLE23 + addressOffset: 1280 + size: 32 + resetValue: 1 + fields: + - name: SHROM_MPU_TABLE23 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: IMMU_TABLE0 + addressOffset: 1284 + size: 32 + fields: + - name: IMMU_TABLE0 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: IMMU_TABLE1 + addressOffset: 1288 + size: 32 + resetValue: 1 + fields: + - name: IMMU_TABLE1 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: IMMU_TABLE2 + addressOffset: 1292 + size: 32 + resetValue: 2 + fields: + - name: IMMU_TABLE2 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: IMMU_TABLE3 + addressOffset: 1296 + size: 32 + resetValue: 3 + fields: + - name: IMMU_TABLE3 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: IMMU_TABLE4 + addressOffset: 1300 + size: 32 + resetValue: 4 + fields: + - name: IMMU_TABLE4 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: IMMU_TABLE5 + addressOffset: 1304 + size: 32 + resetValue: 5 + fields: + - name: IMMU_TABLE5 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: IMMU_TABLE6 + addressOffset: 1308 + size: 32 + resetValue: 6 + fields: + - name: IMMU_TABLE6 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: IMMU_TABLE7 + addressOffset: 1312 + size: 32 + resetValue: 7 + fields: + - name: IMMU_TABLE7 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: IMMU_TABLE8 + addressOffset: 1316 + size: 32 + resetValue: 8 + fields: + - name: IMMU_TABLE8 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: IMMU_TABLE9 + addressOffset: 1320 + size: 32 + resetValue: 9 + fields: + - name: IMMU_TABLE9 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: IMMU_TABLE10 + addressOffset: 1324 + size: 32 + resetValue: 10 + fields: + - name: IMMU_TABLE10 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: IMMU_TABLE11 + addressOffset: 1328 + size: 32 + resetValue: 11 + fields: + - name: IMMU_TABLE11 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: IMMU_TABLE12 + addressOffset: 1332 + size: 32 + resetValue: 12 + fields: + - name: IMMU_TABLE12 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: IMMU_TABLE13 + addressOffset: 1336 + size: 32 + resetValue: 13 + fields: + - name: IMMU_TABLE13 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: IMMU_TABLE14 + addressOffset: 1340 + size: 32 + resetValue: 14 + fields: + - name: IMMU_TABLE14 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: IMMU_TABLE15 + addressOffset: 1344 + size: 32 + resetValue: 15 + fields: + - name: IMMU_TABLE15 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: DMMU_TABLE0 + addressOffset: 1348 + size: 32 + fields: + - name: DMMU_TABLE0 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: DMMU_TABLE1 + addressOffset: 1352 + size: 32 + resetValue: 1 + fields: + - name: DMMU_TABLE1 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: DMMU_TABLE2 + addressOffset: 1356 + size: 32 + resetValue: 2 + fields: + - name: DMMU_TABLE2 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: DMMU_TABLE3 + addressOffset: 1360 + size: 32 + resetValue: 3 + fields: + - name: DMMU_TABLE3 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: DMMU_TABLE4 + addressOffset: 1364 + size: 32 + resetValue: 4 + fields: + - name: DMMU_TABLE4 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: DMMU_TABLE5 + addressOffset: 1368 + size: 32 + resetValue: 5 + fields: + - name: DMMU_TABLE5 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: DMMU_TABLE6 + addressOffset: 1372 + size: 32 + resetValue: 6 + fields: + - name: DMMU_TABLE6 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: DMMU_TABLE7 + addressOffset: 1376 + size: 32 + resetValue: 7 + fields: + - name: DMMU_TABLE7 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: DMMU_TABLE8 + addressOffset: 1380 + size: 32 + resetValue: 8 + fields: + - name: DMMU_TABLE8 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: DMMU_TABLE9 + addressOffset: 1384 + size: 32 + resetValue: 9 + fields: + - name: DMMU_TABLE9 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: DMMU_TABLE10 + addressOffset: 1388 + size: 32 + resetValue: 10 + fields: + - name: DMMU_TABLE10 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: DMMU_TABLE11 + addressOffset: 1392 + size: 32 + resetValue: 11 + fields: + - name: DMMU_TABLE11 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: DMMU_TABLE12 + addressOffset: 1396 + size: 32 + resetValue: 12 + fields: + - name: DMMU_TABLE12 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: DMMU_TABLE13 + addressOffset: 1400 + size: 32 + resetValue: 13 + fields: + - name: DMMU_TABLE13 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: DMMU_TABLE14 + addressOffset: 1404 + size: 32 + resetValue: 14 + fields: + - name: DMMU_TABLE14 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: DMMU_TABLE15 + addressOffset: 1408 + size: 32 + resetValue: 15 + fields: + - name: DMMU_TABLE15 + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: PRO_INTRUSION_CTRL + addressOffset: 1412 + size: 32 + resetValue: 1 + fields: + - name: PRO_INTRUSION_RECORD_RESET_N + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: PRO_INTRUSION_STATUS + addressOffset: 1416 + size: 32 + fields: + - name: PRO_INTRUSION_RECORD + bitOffset: 0 + bitWidth: 4 + access: read-only + - register: + name: APP_INTRUSION_CTRL + addressOffset: 1420 + size: 32 + resetValue: 1 + fields: + - name: APP_INTRUSION_RECORD_RESET_N + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: APP_INTRUSION_STATUS + addressOffset: 1424 + size: 32 + fields: + - name: APP_INTRUSION_RECORD + bitOffset: 0 + bitWidth: 4 + access: read-only + - register: + name: FRONT_END_MEM_PD + addressOffset: 1428 + size: 32 + resetValue: 5 + fields: + - name: AGC_MEM_FORCE_PU + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: AGC_MEM_FORCE_PD + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PBUS_MEM_FORCE_PU + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PBUS_MEM_FORCE_PD + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: MMU_IA_INT_EN + addressOffset: 1432 + size: 32 + fields: + - name: MMU_IA_INT_EN + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: MPU_IA_INT_EN + addressOffset: 1436 + size: 32 + fields: + - name: MPU_IA_INT_EN + bitOffset: 0 + bitWidth: 17 + access: read-write + - register: + name: CACHE_IA_INT_EN + addressOffset: 1440 + size: 32 + fields: + - name: CACHE_IA_INT_EN + description: Interrupt enable bits for various invalid cache access reasons + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: CACHE_IA_INT_APP_DROM0 + description: APP CPU invalid access to DROM0 when cache is disabled + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CACHE_IA_INT_APP_IRAM0 + description: APP CPU invalid access to IRAM0 when cache is disabled + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CACHE_IA_INT_APP_IRAM1 + description: APP CPU invalid access to IRAM1 when cache is disabled + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CACHE_IA_INT_APP_IROM0 + description: APP CPU invalid access to IROM0 when cache is disabled + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CACHE_IA_INT_APP_DRAM1 + description: APP CPU invalid access to DRAM1 when cache is disabled + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CACHE_IA_INT_APP_OPPOSITE + description: APP CPU invalid access to APP CPU cache when cache disabled + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CACHE_IA_INT_PRO_DROM0 + description: PRO CPU invalid access to DROM0 when cache is disabled + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CACHE_IA_INT_PRO_IRAM0 + description: PRO CPU invalid access to IRAM0 when cache is disabled + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CACHE_IA_INT_PRO_IRAM1 + description: PRO CPU invalid access to IRAM1 when cache is disabled + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CACHE_IA_INT_PRO_IROM0 + description: PRO CPU invalid access to IROM0 when cache is disabled + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: CACHE_IA_INT_PRO_DRAM1 + description: PRO CPU invalid access to DRAM1 when cache is disabled + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: CACHE_IA_INT_PRO_OPPOSITE + description: PRO CPU invalid access to APP CPU cache when cache disabled + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: SECURE_BOOT_CTRL + addressOffset: 1444 + size: 32 + fields: + - name: SW_BOOTLOADER_SEL + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SPI_DMA_CHAN_SEL + addressOffset: 1448 + size: 32 + fields: + - name: SPI1_DMA_CHAN_SEL + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SPI2_DMA_CHAN_SEL + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: SPI3_DMA_CHAN_SEL + bitOffset: 4 + bitWidth: 2 + access: read-write + - register: + name: PRO_VECBASE_CTRL + addressOffset: 1452 + size: 32 + fields: + - name: PRO_OUT_VECBASE_SEL + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: PRO_VECBASE_SET + addressOffset: 1456 + size: 32 + fields: + - name: PRO_OUT_VECBASE + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: APP_VECBASE_CTRL + addressOffset: 1460 + size: 32 + fields: + - name: APP_OUT_VECBASE_SEL + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: APP_VECBASE_SET + addressOffset: 1464 + size: 32 + fields: + - name: APP_OUT_VECBASE + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: DATE + addressOffset: 4092 + size: 32 + resetValue: 23089552 + fields: + - name: DATE + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: EFUSE + description: eFuse Controller + groupName: EFUSE + baseAddress: 1073061888 + addressBlock: + - offset: 0 + size: 292 + usage: registers + interrupt: + - name: EFUSE + value: 44 + registers: + - register: + name: BLK0_RDATA0 + addressOffset: 0 + size: 32 + fields: + - name: RD_EFUSE_WR_DIS + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: RD_EFUSE_RD_DIS + bitOffset: 16 + bitWidth: 4 + access: read-only + - name: RD_FLASH_CRYPT_CNT + bitOffset: 20 + bitWidth: 7 + access: read-only + - name: RD_UART_DOWNLOAD_DIS + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: RESERVED_0_28 + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: BLK0_RDATA1 + addressOffset: 4 + size: 32 + fields: + - name: RD_MAC + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_RDATA2 + addressOffset: 8 + size: 32 + fields: + - name: RD_MAC_1 + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: RD_MAC_CRC + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: RD_RESERVE_0_88 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: BLK0_RDATA3 + addressOffset: 12 + size: 32 + fields: + - name: RD_DISABLE_APP_CPU + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RD_DISABLE_BT + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RD_CHIP_PACKAGE_4BIT + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: RD_DIS_CACHE + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: RD_SPI_PAD_CONFIG_HD + bitOffset: 4 + bitWidth: 5 + access: read-only + - name: RD_CHIP_PACKAGE + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: RD_CHIP_CPU_FREQ_LOW + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RD_CHIP_CPU_FREQ_RATED + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: RD_BLK3_PART_RESERVE + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RD_CHIP_VER_REV1 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RD_RESERVE_0_112 + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: BLK0_RDATA4 + addressOffset: 16 + size: 32 + fields: + - name: RD_CLK8M_FREQ + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: RD_ADC_VREF + bitOffset: 8 + bitWidth: 5 + access: read-write + - name: RD_RESERVE_0_141 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: RD_XPD_SDIO + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: RD_XPD_SDIO_TIEH + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: RD_XPD_SDIO_FORCE + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: RD_RESERVE_0_145 + bitOffset: 17 + bitWidth: 15 + access: read-write + - register: + name: BLK0_RDATA5 + addressOffset: 20 + size: 32 + fields: + - name: RD_SPI_PAD_CONFIG_CLK + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: RD_SPI_PAD_CONFIG_Q + bitOffset: 5 + bitWidth: 5 + access: read-only + - name: RD_SPI_PAD_CONFIG_D + bitOffset: 10 + bitWidth: 5 + access: read-only + - name: RD_SPI_PAD_CONFIG_CS0 + bitOffset: 15 + bitWidth: 5 + access: read-only + - name: RD_CHIP_VER_REV2 + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: RD_RESERVE_0_181 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: RD_VOL_LEVEL_HP_INV + bitOffset: 22 + bitWidth: 2 + access: read-only + - name: RD_WAFER_VERSION_MINOR + bitOffset: 24 + bitWidth: 2 + access: read-only + - name: RD_RESERVE_0_186 + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: RD_FLASH_CRYPT_CONFIG + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: BLK0_RDATA6 + addressOffset: 24 + size: 32 + fields: + - name: RD_CODING_SCHEME + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: RD_CONSOLE_DEBUG_DISABLE + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: RD_DISABLE_SDIO_HOST + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: RD_ABS_DONE_0 + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: RD_ABS_DONE_1 + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: RD_JTAG_DISABLE + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: RD_DISABLE_DL_ENCRYPT + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: RD_DISABLE_DL_DECRYPT + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: RD_DISABLE_DL_CACHE + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: RD_KEY_STATUS + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: RD_RESERVE_0_203 + bitOffset: 11 + bitWidth: 21 + access: read-write + - register: + name: BLK0_WDATA0 + addressOffset: 28 + size: 32 + fields: + - name: WR_DIS + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: RD_DIS + bitOffset: 16 + bitWidth: 4 + access: read-write + - name: FLASH_CRYPT_CNT + bitOffset: 20 + bitWidth: 7 + access: read-write + - register: + name: BLK0_WDATA1 + addressOffset: 32 + size: 32 + fields: + - name: WIFI_MAC_CRC_LOW + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BLK0_WDATA2 + addressOffset: 36 + size: 32 + fields: + - name: WIFI_MAC_CRC_HIGH + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: BLK0_WDATA3 + addressOffset: 40 + size: 32 + fields: + - name: DISABLE_APP_CPU + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DISABLE_BT + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CHIP_PACKAGE_4BIT + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: DIS_CACHE + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SPI_PAD_CONFIG_HD + bitOffset: 4 + bitWidth: 5 + access: read-only + - name: CHIP_PACKAGE + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: CHIP_CPU_FREQ_LOW + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CHIP_CPU_FREQ_RATED + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: BLK3_PART_RESERVE + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CHIP_VER_REV1 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RESERVE_0_112 + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: BLK0_WDATA4 + addressOffset: 44 + size: 32 + fields: + - name: CLK8M_FREQ + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: ADC_VREF + bitOffset: 8 + bitWidth: 5 + access: read-write + - name: RESERVE_0_141 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: XPD_SDIO + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: XPD_SDIO_TIEH + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: XPD_SDIO_FORCE + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: RESERVE_0_145 + bitOffset: 17 + bitWidth: 15 + access: read-write + - register: + name: BLK0_WDATA5 + addressOffset: 48 + size: 32 + fields: + - name: SPI_PAD_CONFIG_CLK + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: SPI_PAD_CONFIG_Q + bitOffset: 5 + bitWidth: 5 + access: read-only + - name: SPI_PAD_CONFIG_D + bitOffset: 10 + bitWidth: 5 + access: read-only + - name: SPI_PAD_CONFIG_CS0 + bitOffset: 15 + bitWidth: 5 + access: read-only + - name: CHIP_VER_REV2 + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: RESERVE_0_181 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: VOL_LEVEL_HP_INV + bitOffset: 22 + bitWidth: 2 + access: read-only + - name: WAFER_VERSION_MINOR + bitOffset: 24 + bitWidth: 2 + access: read-only + - name: RESERVE_0_186 + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: FLASH_CRYPT_CONFIG + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: BLK0_WDATA6 + addressOffset: 52 + size: 32 + fields: + - name: CODING_SCHEME + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CONSOLE_DEBUG_DISABLE + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DISABLE_SDIO_HOST + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ABS_DONE_0 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ABS_DONE_1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DISABLE_JTAG + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: DISABLE_DL_ENCRYPT + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DISABLE_DL_DECRYPT + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DISABLE_DL_CACHE + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: KEY_STATUS + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: BLK1_RDATA0 + addressOffset: 56 + size: 32 + fields: + - name: RD_BLOCK1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_RDATA1 + addressOffset: 60 + size: 32 + fields: + - name: RD_BLOCK1_1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_RDATA2 + addressOffset: 64 + size: 32 + fields: + - name: RD_BLOCK1_2 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_RDATA3 + addressOffset: 68 + size: 32 + fields: + - name: RD_BLOCK1_3 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_RDATA4 + addressOffset: 72 + size: 32 + fields: + - name: RD_BLOCK1_4 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_RDATA5 + addressOffset: 76 + size: 32 + fields: + - name: RD_BLOCK1_5 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_RDATA6 + addressOffset: 80 + size: 32 + fields: + - name: RD_BLOCK1_6 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_RDATA7 + addressOffset: 84 + size: 32 + fields: + - name: RD_BLOCK1_7 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_RDATA0 + addressOffset: 88 + size: 32 + fields: + - name: RD_BLOCK2 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_RDATA1 + addressOffset: 92 + size: 32 + fields: + - name: RD_BLOCK2_1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_RDATA2 + addressOffset: 96 + size: 32 + fields: + - name: RD_BLOCK2_2 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_RDATA3 + addressOffset: 100 + size: 32 + fields: + - name: RD_BLOCK2_3 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_RDATA4 + addressOffset: 104 + size: 32 + fields: + - name: RD_BLOCK2_4 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_RDATA5 + addressOffset: 108 + size: 32 + fields: + - name: RD_BLOCK2_5 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_RDATA6 + addressOffset: 112 + size: 32 + fields: + - name: RD_BLOCK2_6 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_RDATA7 + addressOffset: 116 + size: 32 + fields: + - name: RD_BLOCK2_7 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_RDATA0 + addressOffset: 120 + size: 32 + fields: + - name: RD_CUSTOM_MAC_CRC + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: RD_CUSTOM_MAC + bitOffset: 8 + bitWidth: 24 + access: read-only + - register: + name: BLK3_RDATA1 + addressOffset: 124 + size: 32 + fields: + - name: RD_CUSTOM_MAC_1 + bitOffset: 0 + bitWidth: 24 + access: read-only + - name: RESERVED_3_56 + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: BLK3_RDATA2 + addressOffset: 128 + size: 32 + fields: + - name: RD_BLK3_RESERVED_2 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_RDATA3 + addressOffset: 132 + size: 32 + fields: + - name: RD_ADC1_TP_LOW + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: RD_ADC1_TP_HIGH + bitOffset: 7 + bitWidth: 9 + access: read-write + - name: RD_ADC2_TP_LOW + bitOffset: 16 + bitWidth: 7 + access: read-write + - name: RD_ADC2_TP_HIGH + bitOffset: 23 + bitWidth: 9 + access: read-write + - register: + name: BLK3_RDATA4 + addressOffset: 136 + size: 32 + fields: + - name: RD_SECURE_VERSION + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_RDATA5 + addressOffset: 140 + size: 32 + fields: + - name: RESERVED_3_160 + bitOffset: 0 + bitWidth: 24 + access: read-only + - name: RD_MAC_VERSION + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: BLK3_RDATA6 + addressOffset: 144 + size: 32 + fields: + - name: RD_BLK3_RESERVED_6 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_RDATA7 + addressOffset: 148 + size: 32 + fields: + - name: RD_BLK3_RESERVED_7 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_WDATA0 + addressOffset: 152 + size: 32 + fields: + - name: BLK1_DIN0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BLK1_WDATA1 + addressOffset: 156 + size: 32 + fields: + - name: BLK1_DIN1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BLK1_WDATA2 + addressOffset: 160 + size: 32 + fields: + - name: BLK1_DIN2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BLK1_WDATA3 + addressOffset: 164 + size: 32 + fields: + - name: BLK1_DIN3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BLK1_WDATA4 + addressOffset: 168 + size: 32 + fields: + - name: BLK1_DIN4 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BLK1_WDATA5 + addressOffset: 172 + size: 32 + fields: + - name: BLK1_DIN5 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BLK1_WDATA6 + addressOffset: 176 + size: 32 + fields: + - name: BLK1_DIN6 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BLK1_WDATA7 + addressOffset: 180 + size: 32 + fields: + - name: BLK1_DIN7 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BLK2_WDATA0 + addressOffset: 184 + size: 32 + fields: + - name: BLK2_DIN0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BLK2_WDATA1 + addressOffset: 188 + size: 32 + fields: + - name: BLK2_DIN1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BLK2_WDATA2 + addressOffset: 192 + size: 32 + fields: + - name: BLK2_DIN2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BLK2_WDATA3 + addressOffset: 196 + size: 32 + fields: + - name: BLK2_DIN3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BLK2_WDATA4 + addressOffset: 200 + size: 32 + fields: + - name: BLK2_DIN4 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BLK2_WDATA5 + addressOffset: 204 + size: 32 + fields: + - name: BLK2_DIN5 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BLK2_WDATA6 + addressOffset: 208 + size: 32 + fields: + - name: BLK2_DIN6 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BLK2_WDATA7 + addressOffset: 212 + size: 32 + fields: + - name: BLK2_DIN7 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BLK3_WDATA0 + addressOffset: 216 + size: 32 + fields: + - name: BLK3_DIN0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BLK3_WDATA1 + addressOffset: 220 + size: 32 + fields: + - name: BLK3_DIN1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BLK3_WDATA2 + addressOffset: 224 + size: 32 + fields: + - name: BLK3_DIN2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BLK3_WDATA3 + addressOffset: 228 + size: 32 + fields: + - name: ADC1_TP_LOW + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: ADC1_TP_HIGH + bitOffset: 7 + bitWidth: 9 + access: read-write + - name: ADC2_TP_LOW + bitOffset: 16 + bitWidth: 7 + access: read-write + - name: ADC2_TP_HIGH + bitOffset: 23 + bitWidth: 9 + access: read-write + - register: + name: BLK3_WDATA4 + addressOffset: 232 + size: 32 + fields: + - name: SECURE_VERSION + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_WDATA5 + addressOffset: 236 + size: 32 + fields: + - name: BLK3_DIN5 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BLK3_WDATA6 + addressOffset: 240 + size: 32 + fields: + - name: BLK3_DIN6 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BLK3_WDATA7 + addressOffset: 244 + size: 32 + fields: + - name: BLK3_DIN7 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CLK + addressOffset: 248 + size: 32 + resetValue: 16466 + fields: + - name: SEL0 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SEL1 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: EN + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: CONF + addressOffset: 252 + size: 32 + resetValue: 65536 + fields: + - name: OP_CODE + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: FORCE_NO_WR_RD_DIS + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: STATUS + addressOffset: 256 + size: 32 + fields: + - name: DEBUG + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CMD + addressOffset: 260 + size: 32 + fields: + - name: READ_CMD + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PGM_CMD + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + addressOffset: 264 + size: 32 + fields: + - name: READ_DONE_INT_RAW + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PGM_DONE_INT_RAW + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + addressOffset: 268 + size: 32 + fields: + - name: READ_DONE_INT_ST + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PGM_DONE_INT_ST + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + addressOffset: 272 + size: 32 + fields: + - name: READ_DONE_INT_ENA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PGM_DONE_INT_ENA + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + addressOffset: 276 + size: 32 + fields: + - name: READ_DONE_INT_CLR + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: PGM_DONE_INT_CLR + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: DAC_CONF + addressOffset: 280 + size: 32 + resetValue: 40 + fields: + - name: DAC_CLK_DIV + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: DAC_CLK_PAD_SEL + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: DEC_STATUS + addressOffset: 284 + size: 32 + fields: + - name: DEC_WARNINGS + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: DATE + addressOffset: 508 + size: 32 + resetValue: 369370624 + fields: + - name: DATE + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: EMAC_DMA + description: Ethernet DMA configuration and control registers + groupName: EMAC_DMA + baseAddress: 1073123328 + addressBlock: + - offset: 0 + size: 56 + usage: registers + registers: + - register: + name: DMABUSMODE + description: Bus mode configuration + addressOffset: 0 + size: 32 + fields: + - name: SW_RST + description: When this bit is set the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation is complete in all of the ETH_MAC clock domains. Before reprogramming any register of the ETH_MAC you should read a zero (0) value in this bit. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DMA_ARB_SCH + description: "This bit specifies the arbitration scheme between the transmit and receive paths.1'b0: weighted round-robin with RX:TX or TX:RX priority specified in PR (bit[15:14]). 1'b1 Fixed priority (Rx priority to Tx)." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DESC_SKIP_LEN + description: This bit specifies the number of Word to skip between two unchained descriptors.The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL(DESC_SKIP_LEN) value is equal to zero the descriptor table is taken as contiguous by the DMA in Ring mode. + bitOffset: 2 + bitWidth: 5 + access: read-write + - name: ALT_DESC_SIZE + description: When set the size of the alternate descriptor increases to 32 bytes. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: PROG_BURST_LEN + description: "These bits indicate the maximum number of beats to be transferred in one DMA transaction. If the number of beats to be transferred is more than 32 then perform the following steps: 1. Set the PBLx8 mode 2. Set the PBL(PROG_BURST_LEN)." + bitOffset: 8 + bitWidth: 6 + access: read-write + - name: PRI_RATIO + description: "These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio Rx:Tx represented by each bit: 2'b00 -- 1: 1 2'b01 -- 2: 0 2'b10 -- 3: 1 2'b11 -- 4: 1" + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: FIXED_BURST + description: This bit controls whether the AHB master interface performs fixed burst transfers or not. When set the AHB interface uses only SINGLE INCR4 INCR8 or INCR16 during start of the normal burst transfers. When reset the AHB interface uses SINGLE and INCR burst transfer Operations. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RX_DMA_PBL + description: This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write.The Rx DMA always attempts to burst as specified in the RPBL(RX_DMA_PBL) bit each time it starts a burst transfer on the host bus. You can program RPBL with values of 1 2 4 8 16 and 32. Any other value results in undefined behavior. This field is valid and applicable only when USP(USE_SEP_PBL) is set high. + bitOffset: 17 + bitWidth: 6 + access: read-write + - name: USE_SEP_PBL + description: "When set high this bit configures the Rx DMA to use the value configured in Bits[22:17] as PBL. The PBL value in Bits[13:8] is applicable only to the Tx DMA operations. When reset to low the PBL value in Bits[13:8] is applicable for both DMA engines." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: PBLX8_MODE + description: "When set high this bit multiplies the programmed PBL value (Bits[22:17] and Bits[13:8]) eight times. Therefore the DMA transfers the data in 8 16 32 64 128 and 256 beats depending on the PBL value." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: DMAADDRALIBEA + description: When this bit is set high and the FIXED_BURST bit is 1 the AHB interface generates all bursts aligned to the start address LS bits. If the FIXED_BURST bit is 0 the first burst (accessing the start address of data buffer) is not aligned but subsequent bursts are aligned to the address. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: DMAMIXEDBURST + description: When this bit is set high and the FIXED_BURST bit is low the AHB master interface starts all bursts of a length more than 16 with INCR (undefined burst) whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: DMATXPOLLDEMAND + description: "When these bits are written with any value the DMA reads the current descriptor to which the Register (Current Host Transmit Descriptor Register) is pointing. If that descriptor is not available (owned by the Host) the transmission returns to the suspend state and Bit[2] (TU) of Status Register is asserted. If the descriptor is available the transmission resumes." + addressOffset: 4 + size: 32 + access: read-only + - register: + name: DMARXPOLLDEMAND + description: "When these bits are written with any value the DMA reads the current descriptor to which the Current Host Receive Descriptor Register is pointing. If that descriptor is not available (owned by the Host) the reception returns to the Suspended state and Bit[7] (RU) of Status Register is asserted. If the descriptor is available the Rx DMA returns to the active state." + addressOffset: 8 + size: 32 + access: read-only + - register: + name: DMARXBASEADDR + description: "This field contains the base address of the first descriptor in the Receive Descriptor list. The LSB Bits[1:0] are ignored and internally taken as all-zero by the DMA. Therefore these LSB bits are read-only." + addressOffset: 12 + size: 32 + - register: + name: DMATXBASEADDR + description: "This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB Bits[1:0] are ignored and are internally taken as all-zero by the DMA.Therefore these LSB bits are read-only." + addressOffset: 16 + size: 32 + - register: + name: DMASTATUS + description: "State of interrupts, errors and other events" + addressOffset: 20 + size: 32 + fields: + - name: TRANS_INT + description: "This bit indicates that the frame transmission is complete. When transmission is complete Bit[31] (OWN) of TDES0 is reset and the specific frame status information is updated in the Descriptor." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TRANS_PROC_STOP + description: This bit is set when the transmission is stopped. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TRANS_BUF_UNAVAIL + description: "This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions. To resume processing Transmit descriptors the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand Command." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TRANS_JABBER_TO + description: "This bit indicates that the Transmit Jabber Timer expired which happens when the frame size exceeds 2 048 (10 240 bytes when the Jumbo frame is enabled). When the Jabber Timeout occurs the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RECV_OVFLOW + description: "This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application the overflow status is set in RDES0[11]." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TRANS_UNDFLOW + description: "This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RECV_INT + description: "This bit indicates that the frame reception is complete. When reception is complete the Bit[31] of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor and the specific frame status information is updated in the descriptor. The reception remains in the Running state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RECV_BUF_UNAVAIL + description: This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive descriptors the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor is owned by the DMA. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RECV_PROC_STOP + description: This bit is asserted when the Receive Process enters the Stopped state. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RECV_WDT_TO + description: When set this bit indicates that the Receive Watchdog Timer expired while receiving the current frame and the current frame is truncated after the watchdog timeout. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: EARLY_TRANS_INT + description: This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FATAL_BUS_ERR_INT + description: "This bit indicates that a bus error occurred as described in Bits [25:23]. When this bit is set the corresponding DMA engine disables all of its bus accesses." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: EARLY_RECV_INT + description: "This bit indicates that the DMA filled the first data buffer of the packet. This bit is cleared when the software writes 1 to this bit or when Bit[6] (RI) of this register is set (whichever occurs earlier)." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: ABN_INT_SUMM + description: "Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Interrupt Enable Register: Bit[1]: Transmit Process Stopped. Bit[3]: Transmit Jabber Timeout. Bit[4]: Receive FIFO Overflow. Bit[5]: Transmit Underflow. Bit[7]: Receive Buffer Unavailable. Bit[8]: Receive Process Stopped. Bit[9]: Receive Watchdog Timeout. Bit[10]: Early Transmit Interrupt. Bit[13]: Fatal Bus Error. Only unmasked bits affect the Abnormal Interrupt Summary bit. This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit which causes AIS to be set is cleared." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: NORM_INT_SUMM + description: "Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in Interrupt Enable Register: Bit[0]: Transmit Interrupt. Bit[2]: Transmit Buffer Unavailable. Bit[6]: Receive Interrupt. Bit[14]: Early Receive Interrupt. Only unmasked bits affect the Normal Interrupt Summary bit.This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit which causes NIS to be set is cleared." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RECV_PROC_STATE + description: "This field indicates the Receive DMA FSM state. This field does not generate an interrupt. 3'b000: Stopped. Reset or Stop Receive Command issued. 3'b001: Running. Fetching Receive Transfer Descriptor. 3'b010: Reserved for future use. 3'b011: Running. Waiting for RX packets. 3'b100: Suspended. Receive Descriptor Unavailable. 3'b101: Running. Closing Receive Descriptor. 3'b110: TIME_STAMP write state. 3'b111: Running. Transferring the TX packets data from receive buffer to host memory." + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: TRANS_PROC_STATE + description: "This field indicates the Transmit DMA FSM state. This field does not generate an interrupt. 3'b000: Stopped. Reset or Stop Transmit Command issued. 3'b001: Running. Fetching Transmit Transfer Descriptor. 3'b010: Reserved for future use. 3'b011: Running. Waiting for TX packets. 3'b100: Suspended. Receive Descriptor Unavailable. 3'b101: Running. Closing Transmit Descriptor. 3'b110: TIME_STAMP write state. 3'b111: Running. Transferring the TX packets data from transmit buffer to host memory." + bitOffset: 20 + bitWidth: 3 + access: read-write + - name: ERROR_BITS + description: "This field indicates the type of error that caused a Bus Error for example error response on the AHB interface. This field is valid only when Bit[13] (FBI) is set. This field does not generate an interrupt. 3'b000: Error during Rx DMA Write Data Transfer. 3'b011: Error during Tx DMA Read Data Transfer. 3'b100: Error during Rx DMA Descriptor Write Access. 3'b101: Error during Tx DMA Descriptor Write Access. 3'b110: Error during Rx DMA Descriptor Read Access. 3'b111: Error during Tx DMA Descriptor Read Access." + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: PMT_INT + description: "This bit indicates an interrupt event in the PMT module of the ETH_MAC. The software must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt and clear its source to reset this bit to 1'b0." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: TS_TRI_INT + description: "This bit indicates an interrupt event in the Timestamp Generator block of the ETH_MAC.The software must read the corresponding registers in the ETH_MAC to get the exact cause of the interrupt and clear its source to reset this bit to 1'b0." + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: DMAOPERATION_MODE + description: Receive and Transmit operating modes and command + addressOffset: 24 + size: 32 + fields: + - name: START_STOP_RX + description: When this bit is set the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames.When this bit is cleared the Rx DMA operation is stopped after the transfer of the current frame. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OPT_SECOND_FRAME + description: When this bit is set it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_THRESH_CTRL + description: "These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. 2'b00: 64， 2'b01: 32， 2'b10: 96， 2'b11: 128 ." + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: DROP_GFRM + description: When set the MAC drops the received giant frames in the Rx FIFO that is frames that are larger than the computed giant frame limit. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FWD_UNDER_GF + description: When set the Rx FIFO forwards Undersized frames (that is frames with no Error and length less than 64 bytes) including pad-bytes and CRC. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FWD_ERR_FRAME + description: When this bit is reset the Rx FIFO drops frames with error status (CRC error collision error giant frame watchdog timeout or overflow). + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: START_STOP_TRANSMISSION_COMMAND + description: When this bit is set transmission is placed in the Running state and the DMA checks the Transmit List at the current position for a frame to be transmitted.When this bit is reset the transmission process is placed in the Stopped state after completing the transmission of the current frame. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_THRESH_CTRL + description: "These bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition full frames with a length less than the threshold are also transmitted. These bits are used only when Tx_Str_fwd is reset. 3'b000: 64 3'b001: 128 3'b010: 192 3'b011: 256 3'b100: 40 3'b101: 32 3'b110: 24 3'b111: 16 ." + bitOffset: 14 + bitWidth: 3 + access: read-write + - name: FLUSH_TX_FIFO + description: When this bit is set the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is complete. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TX_STR_FWD + description: When this bit is set transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set the Tx_Thresh_Ctrl values specified in Tx_Thresh_Ctrl are ignored. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: DIS_FLUSH_RECV_FRAMES + description: When this bit is set the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: RX_STORE_FORWARD + description: When this bit is set the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: DIS_DROP_TCPIP_ERR_FRAM + description: When this bit is set the MAC does not drop the frames which only have errors detected by the Receive Checksum engine.When this bit is reset all error frames are dropped if the Fwd_Err_Frame bit is reset. + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: DMAIN_EN + addressOffset: 28 + size: 32 + fields: + - name: DMAIN_TIE + description: "When this bit is set with Normal Interrupt Summary Enable (Bit[16]) the Transmit Interrupt is enabled. When this bit is reset the Transmit Interrupt is disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DMAIN_TSE + description: "When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Transmission Stopped Interrupt is enabled. When this bit is reset the Transmission Stopped Interrupt is disabled." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DMAIN_TBUE + description: When this bit is set with Normal Interrupt Summary Enable (Bit 16) the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset the Transmit Buffer Unavailable Interrupt is Disabled. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DMAIN_TJTE + description: "When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset the Transmit Jabber Timeout Interrupt is disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DMAIN_OIE + description: "When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Receive Overflow Interrupt is enabled. When this bit is reset the Overflow Interrupt is disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DMAIN_UIE + description: "When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Transmit Underflow Interrupt is enabled. When this bit is reset the Underflow Interrupt is disabled." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DMAIN_RIE + description: "When this bit is set with Normal Interrupt Summary Enable (Bit[16]) the Receive Interrupt is enabled. When this bit is reset the Receive Interrupt is disabled." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: DMAIN_RBUE + description: "When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset the Receive Buffer Unavailable Interrupt is disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DMAIN_RSE + description: "When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Receive Stopped Interrupt is enabled. When this bit is reset the Receive Stopped Interrupt is disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DMAIN_RWTE + description: "When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset the Receive Watchdog Timeout Interrupt is disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DMAIN_ETIE + description: "When this bit is set with an Abnormal Interrupt Summary Enable (Bit[15]) the Early Transmit Interrupt is enabled. When this bit is reset the Early Transmit Interrupt is disabled." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DMAIN_FBEE + description: "When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]) the Fatal Bus Error Interrupt is enabled. When this bit is reset the Fatal Bus Error Enable Interrupt is disabled." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DMAIN_ERIE + description: "When this bit is set with Normal Interrupt Summary Enable (Bit[16]) the Early Receive Interrupt is enabled. When this bit is reset the Early Receive Interrupt is disabled." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DMAIN_AISE + description: "When this bit is set abnormal interrupt summary is enabled. When this bit is reset the abnormal interrupt summary is disabled. This bit enables the following interrupts in Status Register: Bit[1]: Transmit Process Stopped. Bit[3]: Transmit Jabber Timeout. Bit[4]: Receive Overflow. Bit[5]: Transmit Underflow. Bit[7]: Receive Buffer Unavailable. Bit[8]: Receive Process Stopped. Bit[9]: Receive Watchdog Timeout. Bit[10]: Early Transmit Interrupt. Bit[13]: Fatal Bus Error." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DMAIN_NISE + description: "When this bit is set normal interrupt summary is enabled. When this bit is reset normal interrupt summary is disabled. This bit enables the following interrupts in Status Register: Bit[0]: Transmit Interrupt. Bit[2]: Transmit Buffer Unavailable. Bit[6]: Receive Interrupt. Bit[14]: Early Receive Interrupt." + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: DMAMISSEDFR + description: Missed Frame and Buffer Overflow Counter Register + addressOffset: 32 + size: 32 + fields: + - name: MISSED_FC + description: This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: OVERFLOW_BMFC + description: "This bit is set every time Missed Frame Counter (Bits[15:0]) overflows that is the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: OVERFLOW_FC + description: This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read. + bitOffset: 17 + bitWidth: 11 + access: read-write + - name: OVERFLOW_BFOC + description: "This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows that is the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened." + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: DMARINTWDTIMER + description: Watchdog timer count on receive + addressOffset: 36 + size: 32 + fields: + - name: RIWTC + description: "This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI(RECV_INT) status bit is not set because of the setting in the corresponding descriptor RDES1[31]. When the watchdog timer runs out the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DMATXCURRDESC + description: The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation. + addressOffset: 72 + size: 32 + access: read-only + - register: + name: DMARXCURRDESC + description: The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation. + addressOffset: 76 + size: 32 + access: read-only + - register: + name: DMATXCURRADDR_BUF + description: The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation. + addressOffset: 80 + size: 32 + access: read-only + - register: + name: DMARXCURRADDR_BUF + description: The address of the current receive descriptor list. Cleared on Reset.Pointer updated by the DMA during operation. + addressOffset: 84 + size: 32 + access: read-only + - name: EMAC_EXT + description: "Ethernet Clock, PHY type, and SRAM configuration registers" + groupName: EMAC_EXT + baseAddress: 1073125376 + addressBlock: + - offset: 0 + size: 24 + usage: registers + registers: + - register: + name: EX_CLKOUT_CONF + description: RMII clock divider setting + addressOffset: 0 + size: 32 + fields: + - name: DIV_NUM + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: H_DIV_NUM + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: DLY_NUM + bitOffset: 8 + bitWidth: 2 + access: read-write + - register: + name: EX_OSCCLK_CONF + description: RMII clock half and whole divider settings + addressOffset: 4 + size: 32 + fields: + - name: DIV_NUM_10M + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: H_DIV_NUM_10M + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: DIV_NUM_100M + bitOffset: 12 + bitWidth: 6 + access: read-write + - name: H_DIV_NUM_100M + bitOffset: 18 + bitWidth: 6 + access: read-write + - name: CLK_SEL + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: EX_CLK_CTRL + description: Clock enable and external/internal clock selection + addressOffset: 8 + size: 32 + fields: + - name: EXT_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: INT_EN + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_125_CLK_EN + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MII_CLK_TX_EN + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MII_CLK_RX_EN + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CLK_EN + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: EX_PHYINF_CONF + description: Selection of MII/RMII phy + addressOffset: 12 + size: 32 + fields: + - name: INT_REVMII_RX_CLK_SEL + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EXT_REVMII_RX_CLK_SEL + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SBD_FLOWCTRL + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CORE_PHY_ADDR + bitOffset: 3 + bitWidth: 5 + access: read-write + - name: REVMII_PHY_ADDR + bitOffset: 8 + bitWidth: 5 + access: read-write + - name: PHY_INTF_SEL + bitOffset: 13 + bitWidth: 3 + access: read-write + - name: SS_MODE + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SBD_CLK_GATING_EN + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: PMT_CTRL_EN + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SCR_SMI_DLY_RX_SYNC + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: TX_ERR_OUT_EN + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: PD_SEL + description: Ethernet RAM power-down enable + addressOffset: 16 + size: 32 + fields: + - name: RAM_PD_EN + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: EX_DATE + addressOffset: 252 + size: 32 + - name: EMAC_MAC + description: Ethernet MAC configuration and control registers + groupName: EMAC_MAC + baseAddress: 1073127424 + addressBlock: + - offset: 0 + size: 120 + usage: registers + registers: + - register: + name: EMACCONFIG + description: MAC configuration + addressOffset: 0 + size: 32 + fields: + - name: PLTF + description: "These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.2'b00: 7 bytes of preamble. 2'b01: 5 bytes of preamble. 2'b10: 3 bytes of preamble." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: RX + description: When this bit is set the receiver state machine of the MAC is enabled for receiving frames from the MII. When this bit is reset the MAC receive state machine is disabled after the completion of the reception of the current frame and does not receive any further frames from the MII. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX + description: When this bit is set the transmit state machine of the MAC is enabled for transmission on the MII. When this bit is reset the MAC transmit state machine is disabled after the completion of the transmission of the current frame and does not transmit any further frames. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DEFERRALCHECK + description: Deferral Check. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: BACKOFFLIMIT + description: "The Back-Off limit determines the random integer number (r) of slot time delays (512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only in the half-duplex mode. 00: k= min (n 10). 01: k = min (n 8). 10: k = min (n 4). 11: k = min (n 1) n = retransmission attempt. The random integer r takes the value in the Range 0 ~ 2000." + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: PADCRCSTRIP + description: When this bit is set the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1 536 bytes. All received frames with length field greater than or equal to 1 536 bytes are passed to the application without stripping the Pad or FCS field. When this bit is reset the MAC passes all incoming frames without modifying them to the Host. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RETRY + description: "When this bit is set the MAC attempts only one transmission. When a collision occurs on the MII interface the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status. When this bit is reset the MAC attempts retries based on the settings of the BL field (Bits [6:5]). This bit is applicable only in the half-duplex Mode." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RXIPCOFFLOAD + description: "When this bit is set the MAC calculates the 16-bit one's complement of the one's complement sum of all received Ethernet frame payloads. It also checks whether the IPv4 Header checksum (assumed to be bytes 25/26 or 29/30 (VLAN-tagged) of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected). When this bit is reset this function is disabled." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DUPLEX + description: "When this bit is set the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. This bit is read only with default value of 1'b1 in the full-duplex-mode." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: LOOPBACK + description: When this bit is set the MAC operates in the loopback mode MII. The MII Receive clock input (CLK_RX) is required for the loopback to work properly because the transmit clock is not looped-back internally. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RXOWN + description: When this bit is set the MAC disables the reception of frames when the TX_EN is asserted in the half-duplex mode. When this bit is reset the MAC receives all packets that are given by the PHY while transmitting. This bit is not applicable if the MAC is operating in the full duplex mode. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FESPEED + description: "This bit selects the speed in the MII RMII interface. 0: 10 Mbps. 1: 100 Mbps." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: MII + description: This bit selects the Ethernet line speed. It should be set to 1 for 10 or 100 Mbps operations.In 10 or 100 Mbps operations this bit along with FES(EMACFESPEED) bit it selects the exact linespeed. In the 10/100 Mbps-only operations the bit is always 1. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DISABLECRS + description: When set high this bit makes the MAC transmitter ignore the MII CRS signal during frame transmission in the half-duplex mode. This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. When this bit is low the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: INTERFRAMEGAP + description: "These bits control the minimum IFG between frames during transmission. 3'b000: 96 bit times. 3'b001: 88 bit times. 3'b010: 80 bit times. 3'b111: 40 bit times. In the half-duplex mode the minimum IFG can be configured only for 64 bit times (IFG = 100). Lower values are not considered." + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: JUMBOFRAME + description: When this bit is set the MAC allows Jumbo frames of 9 018 bytes (9 022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: JABBER + description: When this bit is set the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16 383 bytes. When this bit is reset the MAC cuts off the transmitter if the application sends out more than 2 048 bytes of data (10 240 if JE is set high) during Transmission. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: WATCHDOG + description: When this bit is set the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16 383 bytes. When this bit is reset the MAC does not allow a receive frame which more than 2 048 bytes (10 240 if JE is set high) or the value programmed in Register (Watchdog Timeout Register). The MAC cuts off any bytes received after the watchdog limit number of bytes. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: ASS2KP + description: "When set the MAC considers all frames with up to 2 000 bytes length as normal packets.When Bit[20] (JE) is not set the MAC considers all received frames of size more than 2K bytes as Giant frames. When this bit is reset and Bit[20] (JE) is not set the MAC considers all received frames of size more than 1 518 bytes (1 522 bytes for tagged) as Giant frames. When Bit[20] is set setting this bit has no effect on Giant Frame status." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SAIRC + description: "This field controls the source address insertion or replacement for all transmitted frames.Bit[30] specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]: 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation. 2'b10: If Bit[30] is set to 0 the MAC inserts the content of the MAC Address 0 registers in the SA field of all transmitted frames. If Bit[30] is set to 1 the MAC inserts the content of the MAC Address 1 registers in the SA field of all transmitted frames. 2'b11: If Bit[30] is set to 0 the MAC replaces the content of the MAC Address 0 registers in the SA field of all transmitted frames. If Bit[30] is set to 1 the MAC replaces the content of the MAC Address 1 registers in the SA field of all transmitted frames." + bitOffset: 28 + bitWidth: 3 + access: read-write + - register: + name: EMACFF + description: Frame filter settings + addressOffset: 4 + size: 32 + fields: + - name: PMODE + description: When this bit is set the Address Filter module passes all incoming frames irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR(PRI_RATIO) is set. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DAIF + description: When this bit is set the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames. When reset normal filtering of frames is performed. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PAM + description: "When set this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DBF + description: When this bit is set the AFM(Address Filtering Module) module blocks all incoming broadcast frames. In addition it overrides all other filter settings. When this bit is reset the AFM module passes all received broadcast Frames. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: PCF + description: "These bits control the forwarding of all control frames (including unicast and multicast Pause frames). 2'b00: MAC filters all control frames from reaching the application. 2'b01: MAC forwards all control frames except Pause frames to application even if they fail the Address filter. 2'b10: MAC forwards all control frames to application even if they fail the Address Filter. 2'b11: MAC forwards control frames that pass the Address Filter.The following conditions should be true for the Pause frames processing: Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register (Flow Control Register) to 1. Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register(Flow Control Register) is set. Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: SAIF + description: When this bit is set the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter. When this bit is reset frames whose SA does not match the SA registers are marked as failing the SA Address filter. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SAFE + description: When this bit is set the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails the MAC drops the frame. When this bit is reset the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RECEIVE_ALL + description: When this bit is set the MAC Receiver module passes all received frames irrespective of whether they pass the address filter or not to the Application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset the Receiver module passes only those frames to the Application that pass the SA or DA address Filter. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EMACGMIIADDR + description: PHY configuration access + addressOffset: 16 + size: 32 + fields: + - name: MIIBUSY + description: "This bit should read logic 0 before writing to PHY Addr Register and PHY data Register.During a PHY register access the software sets this bit to 1'b1 to indicate that a Read or Write access is in progress. PHY data Register is invalid until this bit is cleared by the MAC. Therefore PHY data Register (MII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. Similarly for a read operation the contents of Register 5 are not valid until this bit is cleared. The subsequent read or write operation should happen only after the previous operation is complete. Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed there is no change in the functionality of this bit even when the PHY is not Present." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MIIWRITE + description: When set this bit indicates to the PHY that this is a Write operation using the MII Data register. If this bit is not set it indicates that this is a Read operation that is placing the data in the MII Data register. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MIICSRCLK + description: "CSR clock range: 1.0 MHz ~ 2.5 MHz. 4'b0000: When the APB clock frequency is 80 MHz the MDC clock frequency is APB CLK/42 4'b0011: When the APB clock frequency is 40 MHz the MDC clock frequency is APB CLK/26." + bitOffset: 2 + bitWidth: 4 + access: read-write + - name: MIIREG + description: These bits select the desired MII register in the selected PHY device. + bitOffset: 6 + bitWidth: 5 + access: read-write + - name: MIIDEV + description: This field indicates which of the 32 possible PHY devices are being accessed. + bitOffset: 11 + bitWidth: 5 + access: read-write + - register: + name: EMACMIIDATA + description: PHY data read write + addressOffset: 20 + size: 32 + fields: + - name: MII_DATA + description: This field contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: EMACFC + description: Frame flow control + addressOffset: 24 + size: 32 + fields: + - name: FCBBA + description: "This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFCE bit is set. In the full-duplex mode this bit should be read as 1'b0 before writing to the Flow Control register. To initiate a Pause frame the Application must set this bit to 1'b1. During a transfer of the Control Frame this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause frame transmission the MAC resets this bit to 1'b0. The Flow Control register should not be written to until this bit is cleared. In the half-duplex mode when this bit is set (and TFCE is set) then backpressure is asserted by the MAC. During backpressure when the MAC receives a new frame the transmitter starts sending a JAM pattern resulting in a collision. When the MAC is configured for the full-duplex mode the BPA(backpressure activate) is automatically disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TFCE + description: In the full-duplex mode when this bit is set the MAC enables the flow control operation to transmit Pause frames. When this bit is reset the flow control operation in the MAC is disabled and the MAC does not transmit any Pause frames. In the half-duplex mode when this bit is set the MAC enables the backpressure operation. When this bit is reset the backpressure feature is Disabled. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RFCE + description: When this bit is set the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset the decode function of the Pause frame is disabled. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: UPFD + description: A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. When this bit is set the MAC can also detect Pause frames with unicast address of the station. This unicast address should be as specified in the EMACADDR0 High Register and EMACADDR0 Low Register. When this bit is reset the MAC only detects Pause frames with unique multicast address. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PLT + description: "This field configures the threshold of the Pause timer automatic retransmission of the Pause frame.The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example if PT = 100H (256 slot-times) and PLT = 01 then a second Pause frame is automatically transmitted at 228 (256-28) slot times after the first Pause frame is transmitted. The following list provides the threshold values for different values: 2'b00: The threshold is Pause time minus 4 slot times (PT-4 slot times). 2'b01: The threshold is Pause time minus 28 slot times (PT-28 slot times). 2'b10: The threshold is Pause time minus 144 slot times (PT-144 slot times). 2'b11: The threshold is Pause time minus 256 slot times (PT-256 slot times). The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the MII interface." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DZPQ + description: When this bit is set it disables the automatic generation of the Zero-Quanta Pause frames on the de-assertion of the flow-control signal from the FIFO layer. When this bit is reset normal operation with automatic Zero-Quanta Pause frame generation is enabled. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: PAUSE_TIME + description: This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the MII clock domain then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: EMACDEBUG + description: Status debugging bits + addressOffset: 36 + size: 32 + access: read-only + fields: + - name: MACRPES + description: When high this bit indicates that the MAC MII receive protocol engine is actively receiving data and not in IDLE state. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MACRFFCS + description: "When high this field indicates the active state of the FIFO Read and Write controllers of the MAC Receive Frame Controller Module. MACRFFCS[1] represents the status of FIFO Read controller. MACRFFCS[0] represents the status of small FIFO Write controller." + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: MTLRFWCAS + description: When high this bit indicates that the MTL Rx FIFO Write Controller is active and is transferring a received frame to the FIFO. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MTLRFRCS + description: "This field gives the state of the Rx FIFO read Controller: 2'b00: IDLE state.2'b01: Reading frame data.2'b10: Reading frame status (or timestamp).2'b11: Flushing the frame data and status." + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: MTLRFFLS + description: "This field gives the status of the fill-level of the Rx FIFO: 2'b00: Rx FIFO Empty. 2'b01: Rx FIFO fill-level below flow-control deactivate threshold. 2'b10: Rx FIFO fill-level above flow-control activate threshold. 2'b11: Rx FIFO Full." + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: MACTPES + description: When high this bit indicates that the MAC MII transmit protocol engine is actively transmitting data and is not in the IDLE state. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: MACTFCS + description: "This field indicates the state of the MAC Transmit Frame Controller module: 2'b00: IDLE state. 2'b01: Waiting for status of previous frame or IFG or backoff period to be over. 2'b10: Generating and transmitting a Pause frame (in the full-duplex mode). 2'b11: Transferring input frame for transmission." + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MACTP + description: When high this bit indicates that the MAC transmitter is in the Pause condition (in the full-duplex-mode) and hence does not schedule any frame for transmission. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: MTLTFRCS + description: "This field indicates the state of the Tx FIFO Read Controller: 2'b00: IDLE state. 2'b01: READ state (transferring data to the MAC transmitter). 2'b10: Waiting for TxStatus from the MAC transmitter. 2'b11: Writing the received TxStatus or flushing the Tx FIFO." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: MTLTFWCS + description: When high this bit indicates that the MTL Tx FIFO Write Controller is active and is transferring data to the Tx FIFO. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: MTLTFNES + description: When high this bit indicates that the MTL Tx FIFO is not empty and some data is left for Transmission. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: MTLTSFFS + description: When high this bit indicates that the MTL TxStatus FIFO is full. Therefore the MTL cannot accept any more frames for transmission. + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: PMT_RWUFFR + description: "The MSB (31st bit) must be zero.Bit j[30:0] is the byte mask. If Bit 1/2/3/4 (byte number) of the byte mask is set the CRC block processes the Filter 1/2/3/4 Offset + j of the incoming packet(PWKPTR is 0/1/2/3).RWKPTR is 0:Filter 0 Byte Mask .RWKPTR is 1:Filter 1 Byte Mask RWKPTR is 2:Filter 2 Byte Mask RWKPTR is 3:Filter 3 Byte Mask RWKPTR is 4:Bit 3/11/19/27 specifies the address type defining the destination address type of the pattern.When the bit is set the pattern applies to only multicast packets" + addressOffset: 40 + size: 32 + access: read-only + - register: + name: PMT_CSR + description: PMT Control and Status + addressOffset: 44 + size: 32 + access: read-only + fields: + - name: PWRDWN + description: When set the MAC receiver drops all received frames until it receives the expected magic packet or remote wake-up frame.This bit must only be set when MGKPKTEN GLBLUCAST or RWKPKTEN bit is set high. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MGKPKTEN + description: When set enables generation of a power management event because of magic packet reception. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RWKPKTEN + description: When set enables generation of a power management event because of remote wake-up frame reception + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MGKPRCVD + description: When set this bit indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared by a Read into this register. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RWKPRCVD + description: When set this bit indicates the power management event is generated because of the reception of a remote wake-up frame. This bit is cleared by a Read into this register. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: GLBLUCAST + description: When set enables any unicast packet filtered by the MAC (DAFilter) address recognition to be a remote wake-up frame. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RWKPTR + description: The maximum value of the pointer is 7 the detail information please refer to PMT_RWUFFR. + bitOffset: 24 + bitWidth: 5 + access: read-write + - name: RWKFILTRST + description: When this bit is set it resets the RWKPTR register to 3’b000. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EMACLPI_CRS + description: LPI Control and Status + addressOffset: 48 + size: 32 + access: read-only + fields: + - name: TLPIEN + description: When set this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TLPIEX + description: When set this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI_TW_Timer has expired.This bit is cleared by a read into this register. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RLPIEN + description: When set this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RLPIEX + description: When set this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the MII interface exited the LPI state and resumed the normal reception. This bit is cleared by a read into this register. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TLPIST + description: When set this bit indicates that the MAC is transmitting the LPI pattern on the MII interface. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RLPIST + description: When set this bit indicates that the MAC is receiving the LPI pattern on the MII interface. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: LPIEN + description: When set this bit instructs the MAC Transmitter to enter the LPI state. When reset this bit instructs the MAC to exit the LPI state and resume normal transmission.This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PLS + description: This bit indicates the link status of the PHY.When set the link is considered to be okay (up) and when reset the link is considered to be down. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: LPITXA + description: This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side.If the LPITXA and LPIEN bits are set to 1 the MAC enters the LPI mode only after all outstanding frames and pending frames have been transmitted. The MAC comes out of the LPI mode when the application sends any frame.When this bit is 0 the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: EMACLPITIMERSCONTROL + description: LPI Timers Control + addressOffset: 52 + size: 32 + access: read-only + fields: + - name: LPI_TW_TIMER + description: This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: LPI_LS_TIMER + description: This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI_LS_Timer reaches the programmed terminal count. The default value of the LPI_LS_Timer is 1000 (1 sec) as defined in the IEEE standard. + bitOffset: 16 + bitWidth: 10 + access: read-write + - register: + name: EMACINTS + description: Interrupt status + addressOffset: 56 + size: 32 + access: read-only + fields: + - name: PMTINTS + description: "This bit is set when a magic packet or remote wake-up frame is received in the power-down mode (see Bit[5] and Bit[6] in the PMT Control and Status Register). This bit is cleared when both Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. This bit is valid only when you select the optional PMT module during core configuration." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: LPIIS + description: "When the Energy Efficient Ethernet feature is enabled this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared on reading Bit[0] of Register (LPI Control and Status Register)." + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: EMACINTMASK + description: Interrupt mask + addressOffset: 60 + size: 32 + fields: + - name: PMTINTMASK + description: When set this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register (Interrupt Status Register). + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: LPIINTMASK + description: When set this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register (Interrupt Status Register). + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: EMACADDR0HIGH + description: Upper 16 bits of the first 6-byte MAC address + addressOffset: 64 + size: 32 + fields: + - name: ADDRESS0_HI + description: "This field contains the upper 16 bits (47:32) of the first 6-byte MAC address.The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: ADDRESS_ENABLE0 + description: This bit is always set to 1. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EMACADDR0LOW + description: This field contains the lower 32 bits of the first 6-byte MAC address. This is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit Flow Control (Pause) Frames. + addressOffset: 68 + size: 32 + - register: + name: EMACADDR1HIGH + description: Upper 16 bits of the second 6-byte MAC address + addressOffset: 72 + size: 32 + fields: + - name: MAC_ADDRESS1_HI + description: "This field contains the upper 16 bits Bits[47:32] of the second 6-byte MAC Address." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MASK_BYTE_CONTROL + description: "These bits are mask control bits for comparison of each of the EMACADDR1 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR1 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR1 High [15:8]. Bit[28]: EMACADDR1 High [7:0]. Bit[27]: EMACADDR1 Low [31:24]. Bit[24]: EMACADDR1 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address." + bitOffset: 24 + bitWidth: 6 + access: read-write + - name: SOURCE_ADDRESS + description: "When this bit is set the EMACADDR1[47:0] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR1[47:0] is used to compare with the DA fields of the received frame." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: ADDRESS_ENABLE1 + description: When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EMACADDR1LOW + description: This field contains the lower 32 bits of the second 6-byte MAC address.The content of this field is undefined so the register needs to be configured after the initialization Process. + addressOffset: 76 + size: 32 + - register: + name: EMACADDR2HIGH + description: Upper 16 bits of the third 6-byte MAC address + addressOffset: 80 + size: 32 + fields: + - name: MAC_ADDRESS2_HI + description: "This field contains the upper 16 bits Bits[47:32] of the third 6-byte MAC address." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MASK_BYTE_CONTROL2 + description: "These bits are mask control bits for comparison of each of the EMACADDR2 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR2 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR2 High [15:8]. Bit[28]: EMACADDR2 High [7:0]. Bit[27]: EMACADDR2 Low [31:24]. Bit[24]: EMACADDR2 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address." + bitOffset: 24 + bitWidth: 6 + access: read-write + - name: SOURCE_ADDRESS2 + description: "When this bit is set the EMACADDR2[47:0] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR2[47:0] is used to compare with the DA fields of the received frame." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: ADDRESS_ENABLE2 + description: When this bit is set the address filter module uses the third MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EMACADDR2LOW + description: This field contains the lower 32 bits of the third 6-byte MAC address. The content of this field is undefined so the register needs to be configured after the initialization process. + addressOffset: 84 + size: 32 + - register: + name: EMACADDR3HIGH + description: Upper 16 bits of the fourth 6-byte MAC address + addressOffset: 88 + size: 32 + fields: + - name: MAC_ADDRESS3_HI + description: "This field contains the upper 16 bits Bits[47:32] of the fourth 6-byte MAC address." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MASK_BYTE_CONTROL3 + description: "These bits are mask control bits for comparison of each of the EMACADDR3 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR3 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR3 High [15:8]. Bit[28]: EMACADDR3 High [7:0]. Bit[27]: EMACADDR3 Low [31:24]. Bit[24]: EMACADDR3 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address." + bitOffset: 24 + bitWidth: 6 + access: read-write + - name: SOURCE_ADDRESS3 + description: "When this bit is set the EMACADDR3[47:0] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR3[47:0] is used to compare with the DA fields of the received frame." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: ADDRESS_ENABLE3 + description: When this bit is set the address filter module uses the fourth MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EMACADDR3LOW + description: This field contains the lower 32 bits of the fourth 6-byte MAC address.The content of this field is undefined so the register needs to be configured after the initialization Process. + addressOffset: 92 + size: 32 + - register: + name: EMACADDR4HIGH + description: Upper 16 bits of the fifth 6-byte MAC address + addressOffset: 96 + size: 32 + fields: + - name: MAC_ADDRESS4_HI + description: "This field contains the upper 16 bits Bits[47:32] of the fifth 6-byte MAC address." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MASK_BYTE_CONTROL4 + description: "These bits are mask control bits for comparison of each of the EMACADDR4 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR4 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR4 High [15:8]. Bit[28]: EMACADDR4 High [7:0]. Bit[27]: EMACADDR4 Low [31:24]. Bit[24]: EMACADDR4 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address." + bitOffset: 24 + bitWidth: 6 + access: read-write + - name: SOURCE_ADDRESS4 + description: "When this bit is set the EMACADDR4[47:0] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR4[47:0] is used to compare with the DA fields of the received frame." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: ADDRESS_ENABLE4 + description: When this bit is set the address filter module uses the fifth MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EMACADDR4LOW + description: This field contains the lower 32 bits of the fifth 6-byte MAC address. The content of this field is undefined so the register needs to be configured after the initialization process. + addressOffset: 100 + size: 32 + - register: + name: EMACADDR5HIGH + description: Upper 16 bits of the sixth 6-byte MAC address + addressOffset: 104 + size: 32 + fields: + - name: MAC_ADDRESS5_HI + description: "This field contains the upper 16 bits Bits[47:32] of the sixth 6-byte MAC address." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MASK_BYTE_CONTROL5 + description: "These bits are mask control bits for comparison of each of the EMACADDR5 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR5 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR5 High [15:8]. Bit[28]: EMACADDR5 High [7:0]. Bit[27]: EMACADDR5 Low [31:24]. Bit[24]: EMACADDR5 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address." + bitOffset: 24 + bitWidth: 6 + access: read-write + - name: SOURCE_ADDRESS5 + description: "When this bit is set the EMACADDR5[47:0] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR5[47:0] is used to compare with the DA fields of the received frame." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: ADDRESS_ENABLE5 + description: When this bit is set the address filter module uses the sixth MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EMACADDR5LOW + description: This field contains the lower 32 bits of the sixth 6-byte MAC address. The content of this field is undefined so the register needs to be configured after the initialization process. + addressOffset: 108 + size: 32 + - register: + name: EMACADDR6HIGH + description: Upper 16 bits of the seventh 6-byte MAC address + addressOffset: 112 + size: 32 + fields: + - name: MAC_ADDRESS6_HI + description: "This field contains the upper 16 bits Bits[47:32] of the seventh 6-byte MAC Address." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MASK_BYTE_CONTROL6 + description: "These bits are mask control bits for comparison of each of the EMACADDR6 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR6 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR6 High [15:8]. Bit[28]: EMACADDR6 High [7:0]. Bit[27]: EMACADDR6 Low [31:24]. Bit[24]: EMACADDR6 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address." + bitOffset: 24 + bitWidth: 6 + access: read-write + - name: SOURCE_ADDRESS6 + description: "When this bit is set the EMACADDR6[47:0] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR6[47:0] is used to compare with the DA fields of the received frame." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: ADDRESS_ENABLE6 + description: When this bit is set the address filter module uses the seventh MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EMACADDR6LOW + description: This field contains the lower 32 bits of the seventh 6-byte MAC address.The content of this field is undefined so the register needs to be configured after the initialization Process. + addressOffset: 116 + size: 32 + - register: + name: EMACADDR7HIGH + description: Upper 16 bits of the eighth 6-byte MAC address + addressOffset: 120 + size: 32 + fields: + - name: MAC_ADDRESS7_HI + description: "This field contains the upper 16 bits Bits[47:32] of the eighth 6-byte MAC Address." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MASK_BYTE_CONTROL7 + description: "These bits are mask control bits for comparison of each of the EMACADDR7 bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of EMACADDR7 registers. Each bit controls the masking of the bytes as follows: Bit[29]: EMACADDR7 High [15:8]. Bit[28]: EMACADDR7 High [7:0]. Bit[27]: EMACADDR7 Low [31:24]. Bit[24]: EMACADDR7 Low [7:0].You can filter a group of addresses (known as group address filtering) by masking one or more bytes of the address." + bitOffset: 24 + bitWidth: 6 + access: read-write + - name: SOURCE_ADDRESS7 + description: "When this bit is set the EMACADDR7[47:0] is used to compare with the SA fields of the received frame. When this bit is reset the EMACADDR7[47:0] is used to compare with the DA fields of the received frame." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: ADDRESS_ENABLE7 + description: When this bit is set the address filter module uses the eighth MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EMACADDR7LOW + description: This field contains the lower 32 bits of the eighth 6-byte MAC address.The content of this field is undefined so the register needs to be configured after the initialization Process. + addressOffset: 124 + size: 32 + - register: + name: EMACCSTATUS + description: Link communication status + addressOffset: 216 + size: 32 + access: read-only + fields: + - name: LINK_MODE + description: "This bit indicates the current mode of operation of the link: 1'b0: Half-duplex mode. 1'b1: Full-duplex mode." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LINK_SPEED + description: "This bit indicates the current speed of the link: 2'b00: 2.5 MHz. 2'b01: 25 MHz. 2'b10: 125 MHz." + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: JABBER_TIMEOUT + description: "This bit indicates whether there is jabber timeout error (1'b1) in the received Frame." + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: EMACWDOGTO + description: Watchdog timeout control + addressOffset: 220 + size: 32 + fields: + - name: WDOGTO + description: "When Bit[16] (PWE) is set and Bit[23] (WD) of EMACCONFIG_REG is reset this field is used as watchdog timeout for a received frame. If the length of a received frame exceeds the value of this field such frame is terminated and declared as an error frame." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: PWDOGEN + description: "When this bit is set and Bit[23] (WD) of EMACCONFIG_REG is reset the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. When this bit is cleared the watchdog timeout for a received frame is controlled by the setting of Bit[23] (WD) and Bit[20] (JE) in EMACCONFIG_REG." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FLASH_ENCRYPTION + description: FLASH_ENCRYPTION Peripheral + groupName: FLASH_ENCRYPTION + baseAddress: 1072979968 + addressBlock: + - offset: 0 + size: 44 + usage: registers + registers: + - register: + dim: 8 + dimIncrement: 4 + name: BUFFER_%s + addressOffset: 0 + size: 32 + fields: + - name: BUFFER + description: Data buffers for encryption. + bitOffset: 0 + bitWidth: 8 + access: write-only + - register: + name: START + addressOffset: 32 + size: 32 + fields: + - name: FLASH_START + description: Set this bit to start encryption operation on data buffer. + bitOffset: 0 + bitWidth: 8 + access: write-only + - register: + name: ADDRESS + addressOffset: 36 + size: 32 + fields: + - name: ADDRESS + description: The physical address on the off-chip flash must be 8-word boundary aligned. + bitOffset: 0 + bitWidth: 8 + access: write-only + - register: + name: DONE + addressOffset: 40 + size: 32 + fields: + - name: FLASH_DONE + description: Set this bit when encryption operation is complete. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: FRC_TIMER + description: FRC_TIMER Peripheral + groupName: FRC + baseAddress: 1072984064 + addressBlock: + - offset: 0 + size: 20 + usage: registers + registers: + - register: + name: TIMER_LOAD + addressOffset: 0 + size: 32 + fields: + - name: VALUE + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: TIMER_COUNT + addressOffset: 4 + size: 32 + fields: + - name: TIMER_COUNT + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: TIMER_CTRL + addressOffset: 8 + size: 32 + fields: + - name: TIMER_PRESCALER + bitOffset: 1 + bitWidth: 8 + access: read-write + - register: + name: TIMER_INT + addressOffset: 12 + size: 32 + fields: + - name: CLR + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: TIMER_ALARM + addressOffset: 16 + size: 32 + fields: + - name: TIMER_ALARM + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GPIO + description: General Purpose Input/Output + groupName: GPIO + baseAddress: 1072971776 + addressBlock: + - offset: 0 + size: 1484 + usage: registers + interrupt: + - name: GPIO + value: 22 + - name: GPIO_NMI + value: 23 + registers: + - register: + name: BT_SELECT + addressOffset: 0 + size: 32 + fields: + - name: BT_SEL + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: OUT + addressOffset: 4 + size: 32 + fields: + - name: DATA + description: GPIO0~31 output value + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: OUT_W1TS + addressOffset: 8 + size: 32 + fields: + - name: OUT_DATA_W1TS + description: GPIO0~31 output value write 1 to set + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: OUT_W1TC + addressOffset: 12 + size: 32 + fields: + - name: OUT_DATA_W1TC + description: GPIO0~31 output value write 1 to clear + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: OUT1 + addressOffset: 16 + size: 32 + fields: + - name: DATA + description: GPIO32~39 output value + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: OUT1_W1TS + addressOffset: 20 + size: 32 + fields: + - name: OUT1_DATA_W1TS + description: GPIO32~39 output value write 1 to set + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: OUT1_W1TC + addressOffset: 24 + size: 32 + fields: + - name: OUT1_DATA_W1TC + description: GPIO32~39 output value write 1 to clear + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: SDIO_SELECT + addressOffset: 28 + size: 32 + fields: + - name: SDIO_SEL + description: SDIO PADS on/off control from outside + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: ENABLE + addressOffset: 32 + size: 32 + fields: + - name: DATA + description: GPIO0~31 output enable + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ENABLE_W1TS + addressOffset: 36 + size: 32 + fields: + - name: ENABLE_DATA_W1TS + description: GPIO0~31 output enable write 1 to set + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ENABLE_W1TC + addressOffset: 40 + size: 32 + fields: + - name: ENABLE_DATA_W1TC + description: GPIO0~31 output enable write 1 to clear + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ENABLE1 + addressOffset: 44 + size: 32 + fields: + - name: DATA + description: GPIO32~39 output enable + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: ENABLE1_W1TS + addressOffset: 48 + size: 32 + fields: + - name: ENABLE1_DATA_W1TS + description: GPIO32~39 output enable write 1 to set + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: ENABLE1_W1TC + addressOffset: 52 + size: 32 + fields: + - name: ENABLE1_DATA_W1TC + description: GPIO32~39 output enable write 1 to clear + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: STRAP + addressOffset: 56 + size: 32 + fields: + - name: STRAPPING + description: "{10'b0, MTDI, GPIO0, GPIO2, GPIO4, MTDO, GPIO5}" + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: IN + addressOffset: 60 + size: 32 + fields: + - name: DATA_NEXT + description: GPIO0~31 input value + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: IN1 + addressOffset: 64 + size: 32 + fields: + - name: DATA_NEXT + description: GPIO32~39 input value + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: STATUS + addressOffset: 68 + size: 32 + fields: + - name: INT + description: GPIO0~31 interrupt status + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STATUS_W1TS + addressOffset: 72 + size: 32 + fields: + - name: STATUS_INT_W1TS + description: GPIO0~31 interrupt status write 1 to set + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STATUS_W1TC + addressOffset: 76 + size: 32 + fields: + - name: STATUS_INT_W1TC + description: GPIO0~31 interrupt status write 1 to clear + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STATUS1 + addressOffset: 80 + size: 32 + fields: + - name: INT + description: GPIO32~39 interrupt status + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: STATUS1_W1TS + addressOffset: 84 + size: 32 + fields: + - name: STATUS1_INT_W1TS + description: GPIO32~39 interrupt status write 1 to set + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: STATUS1_W1TC + addressOffset: 88 + size: 32 + fields: + - name: STATUS1_INT_W1TC + description: GPIO32~39 interrupt status write 1 to clear + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: ACPU_INT + addressOffset: 96 + size: 32 + fields: + - name: APPCPU_INT + description: GPIO0~31 APP CPU interrupt status + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: ACPU_NMI_INT + addressOffset: 100 + size: 32 + fields: + - name: APPCPU_NMI_INT + description: GPIO0~31 APP CPU non-maskable interrupt status + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PCPU_INT + addressOffset: 104 + size: 32 + fields: + - name: PROCPU_INT + description: GPIO0~31 PRO CPU interrupt status + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PCPU_NMI_INT + addressOffset: 108 + size: 32 + fields: + - name: PROCPU_NMI_INT + description: GPIO0~31 PRO CPU non-maskable interrupt status + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CPUSDIO_INT + addressOffset: 112 + size: 32 + fields: + - name: SDIO_INT + description: "SDIO's extent GPIO0~31 interrupt" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: ACPU_INT1 + addressOffset: 116 + size: 32 + fields: + - name: APPCPU_INT_H + description: GPIO32~39 APP CPU interrupt status + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: ACPU_NMI_INT1 + addressOffset: 120 + size: 32 + fields: + - name: APPCPU_NMI_INT_H + description: GPIO32~39 APP CPU non-maskable interrupt status + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: PCPU_INT1 + addressOffset: 124 + size: 32 + fields: + - name: PROCPU_INT_H + description: GPIO32~39 PRO CPU interrupt status + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: PCPU_NMI_INT1 + addressOffset: 128 + size: 32 + fields: + - name: PROCPU_NMI_INT_H + description: GPIO32~39 PRO CPU non-maskable interrupt status + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: CPUSDIO_INT1 + addressOffset: 132 + size: 32 + fields: + - name: SDIO_INT_H + description: "SDIO's extent GPIO32~39 interrupt" + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: PIN_PAD_DRIVER + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PIN_INT_TYPE + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: PIN_WAKEUP_ENABLE + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: PIN_CONFIG + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: PIN_INT_ENA + bitOffset: 13 + bitWidth: 5 + access: read-write + - register: + dim: 40 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39" + name: PIN%s + addressOffset: 136 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: GPIO wake up enable only available in light sleep + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CONFIG + description: NA + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: INT_ENA + description: "bit0: APP CPU interrupt enable bit1: APP CPU non-maskable interrupt enable bit3: PRO CPU interrupt enable bit4: PRO CPU non-maskable interrupt enable bit5: SDIO's extent interrupt enable" + bitOffset: 13 + bitWidth: 5 + access: read-write + - register: + name: cali_conf + addressOffset: 296 + size: 32 + fields: + - name: CALI_RTC_MAX + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: CALI_START + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: cali_data + addressOffset: 300 + size: 32 + fields: + - name: CALI_VALUE_SYNC2 + bitOffset: 0 + bitWidth: 20 + access: read-only + - name: CALI_RDY_REAL + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: CALI_RDY_SYNC2 + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + dim: 256 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255" + name: FUNC%s_IN_SEL_CFG + addressOffset: 304 + size: 32 + fields: + - name: IN_SEL + description: select one of the 256 inputs + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: IN_INV_SEL + description: revert the value of the input if you want to revert please set the value to 1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SEL + description: if the slow signal bypass the io matrix or not if you want setting the value to 1 + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + dim: 40 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39" + name: FUNC%s_OUT_SEL_CFG + addressOffset: 1328 + size: 32 + fields: + - name: OUT_SEL + description: select one of the 256 output to 40 GPIO + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: INV_SEL + description: invert the output value if you want to revert the output value setting the value to 1 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OEN_SEL + description: weather using the logical oen signal or not using the value setting by the register + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OEN_INV_SEL + description: invert the output enable value if you want to revert the output enable value setting the value to 1 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: GPIO_SD + description: Sigma-Delta Modulation + groupName: GPIO_SIGMADELTA + baseAddress: 1072975616 + addressBlock: + - offset: 0 + size: 44 + usage: registers + registers: + - register: + dim: 8 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7" + name: SIGMADELTA%s + addressOffset: 0 + size: 32 + resetValue: 65280 + fields: + - name: SD0_IN + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SD0_PRESCALE + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: CG + addressOffset: 32 + size: 32 + fields: + - name: SD_CLK_EN + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: MISC + addressOffset: 36 + size: 32 + fields: + - name: SPI_SWAP + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: VERSION + addressOffset: 40 + size: 32 + resetValue: 22045072 + fields: + - name: SD_DATE + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: HINF + description: HINF Peripheral + groupName: HINF + baseAddress: 1073000448 + addressBlock: + - offset: 0 + size: 52 + usage: registers + registers: + - register: + name: CFG_DATA0 + addressOffset: 0 + size: 32 + resetValue: 572679782 + fields: + - name: USER_ID_FN1 + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: DEVICE_ID_FN1 + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: CFG_DATA1 + addressOffset: 4 + size: 32 + resetValue: 17891345 + fields: + - name: SDIO_ENABLE + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SDIO_IOREADY1 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: HIGHSPEED_ENABLE + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: HIGHSPEED_MODE + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SDIO_CD_ENABLE + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SDIO_IOREADY2 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SDIO_INT_MASK + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: IOENABLE2 + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: CD_DISABLE + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: FUNC1_EPS + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: EMP + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: IOENABLE1 + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: SDIO20_CONF0 + bitOffset: 12 + bitWidth: 4 + access: read-write + - name: SDIO_VER + bitOffset: 16 + bitWidth: 12 + access: read-write + - name: FUNC2_EPS + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SDIO20_CONF1 + bitOffset: 29 + bitWidth: 3 + access: read-write + - register: + name: CFG_DATA7 + addressOffset: 28 + size: 32 + resetValue: 131072 + fields: + - name: PIN_STATE + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CHIP_STATE + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SDIO_RST + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SDIO_IOREADY0 + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: CIS_CONF0 + addressOffset: 32 + size: 32 + resetValue: 4294967295 + fields: + - name: CIS_CONF_W0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CIS_CONF1 + addressOffset: 36 + size: 32 + resetValue: 4294967295 + fields: + - name: CIS_CONF_W1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CIS_CONF2 + addressOffset: 40 + size: 32 + resetValue: 4294967295 + fields: + - name: CIS_CONF_W2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CIS_CONF3 + addressOffset: 44 + size: 32 + resetValue: 4294967295 + fields: + - name: CIS_CONF_W3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CIS_CONF4 + addressOffset: 48 + size: 32 + resetValue: 4294967295 + fields: + - name: CIS_CONF_W4 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CIS_CONF5 + addressOffset: 52 + size: 32 + resetValue: 4294967295 + fields: + - name: CIS_CONF_W5 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CIS_CONF6 + addressOffset: 56 + size: 32 + resetValue: 4294967295 + fields: + - name: CIS_CONF_W6 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CIS_CONF7 + addressOffset: 60 + size: 32 + resetValue: 4294967295 + fields: + - name: CIS_CONF_W7 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CFG_DATA16 + addressOffset: 64 + size: 32 + resetValue: 859006566 + fields: + - name: USER_ID_FN2 + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: DEVICE_ID_FN2 + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: DATE + addressOffset: 252 + size: 32 + resetValue: 352518656 + fields: + - name: SDIO_DATE + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: I2C0 + description: I2C (Inter-Integrated Circuit) Controller 0 + groupName: I2C + baseAddress: 1073033216 + addressBlock: + - offset: 0 + size: 156 + usage: registers + interrupt: + - name: I2C_EXT0 + value: 49 + registers: + - register: + name: SCL_LOW_PERIOD + addressOffset: 0 + size: 32 + fields: + - name: SCL_LOW_PERIOD + description: This register is used to configure the low level width of SCL clock. + bitOffset: 0 + bitWidth: 14 + access: read-write + - register: + name: CTR + addressOffset: 4 + size: 32 + resetValue: 3 + fields: + - name: SDA_FORCE_OUT + description: "1: normally ouput sda data 0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_FORCE_OUT + description: "1: normally ouput scl clock 0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl signal scl_oe is the enable bit for the internal output scl signal)" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SAMPLE_SCL_LEVEL + description: Set this bit to sample data in SCL low level. clear this bit to sample data in SCL high level. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MS_MODE + description: Set this bit to configure the module as i2c master clear this bit to configure the module as i2c slave. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TRANS_START + description: Set this bit to start sending data in txfifo. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TX_LSB_FIRST + description: "This bit is used to control the sending mode for data need to be send. 1: receive data from most significant bit 0: receive data from least significant bit" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_LSB_FIRST + description: "This bit is used to control the storage mode for received datas. 1: receive data from most significant bit 0: receive data from least significant bit" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: This is the clock gating control bit for reading or writing registers. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: SR + addressOffset: 8 + size: 32 + fields: + - name: ACK_REC + description: This register stores the value of ACK bit. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SLAVE_RW + description: "when in slave mode 1: master read slave 0: master write slave." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TIME_OUT + description: when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: ARB_LOST + description: when I2C lost control of SDA line this register changes to high level. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BUS_BUSY + description: "1:I2C bus is busy transferring data. 0:I2C bus is in idle state." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SLAVE_ADDRESSED + description: "when configured as i2c slave and the address send by master is equal to slave's address then this bit will be high level." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS + description: This register changes to high level when one byte is transferred. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: RXFIFO_CNT + description: This register represent the amount of data need to send. + bitOffset: 8 + bitWidth: 6 + access: read-only + - name: TXFIFO_CNT + description: This register stores the amount of received data in ram. + bitOffset: 18 + bitWidth: 6 + access: read-only + - name: SCL_MAIN_STATE_LAST + description: "This register stores the value of state machine for i2c module. 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK" + bitOffset: 24 + bitWidth: 3 + access: read-only + - name: SCL_STATE_LAST + description: "This register stores the value of state machine to produce SCL. 3'h0: SCL_IDLE 3'h1:SCL_START 3'h2:SCL_LOW_EDGE 3'h3: SCL_LOW 3'h4:SCL_HIGH_EDGE 3'h5:SCL_HIGH 3'h6:SCL_STOP" + bitOffset: 28 + bitWidth: 3 + access: read-only + - register: + name: TO + addressOffset: 12 + size: 32 + fields: + - name: TIME_OUT + description: This register is used to configure the max clock number of receiving a data. + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: SLAVE_ADDR + addressOffset: 16 + size: 32 + fields: + - name: SLAVE_ADDR + description: "when configured as i2c slave this register is used to configure slave's address." + bitOffset: 0 + bitWidth: 15 + access: read-write + - name: ADDR_10BIT_EN + description: This register is used to enable slave 10bit address mode. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RXFIFO_ST + addressOffset: 20 + size: 32 + fields: + - name: RXFIFO_START_ADDR + description: This is the offset address of the last receiving data as described in nonfifo_rx_thres_register. + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: RXFIFO_END_ADDR + description: This is the offset address of the first receiving data as described in nonfifo_rx_thres_register. + bitOffset: 5 + bitWidth: 5 + access: read-only + - name: TXFIFO_START_ADDR + description: This is the offset address of the first sending data as described in nonfifo_tx_thres register. + bitOffset: 10 + bitWidth: 5 + access: read-only + - name: TXFIFO_END_ADDR + description: This is the offset address of the last sending data as described in nonfifo_tx_thres register. + bitOffset: 15 + bitWidth: 5 + access: read-only + - register: + name: FIFO_CONF + addressOffset: 24 + size: 32 + resetValue: 22364299 + fields: + - name: RXFIFO_FULL_THRHD + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: TXFIFO_EMPTY_THRHD + description: Config txfifo empty threhd value when using apb fifo access + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: NONFIFO_EN + description: Set this bit to enble apb nonfifo access. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FIFO_ADDR_CFG_EN + description: "When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RX_FIFO_RST + description: Set this bit to reset rx fifo when using apb fifo access. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_FIFO_RST + description: Set this bit to reset tx fifo when using apb fifo access. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: NONFIFO_RX_THRES + description: when I2C receives more than nonfifo_rx_thres data it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data. + bitOffset: 14 + bitWidth: 6 + access: read-write + - name: NONFIFO_TX_THRES + description: when I2C sends more than nonfifo_tx_thres data it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data. + bitOffset: 20 + bitWidth: 6 + access: read-write + - register: + name: DATA + addressOffset: 28 + size: 32 + fields: + - name: FIFO_RDATA + description: The register represent the byte data read from rxfifo when use apb fifo access + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: INT_RAW + addressOffset: 32 + size: 32 + fields: + - name: RXFIFO_FULL_INT_RAW + description: The raw interrupt status bit for rxfifo full when use apb fifo access. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_EMPTY_INT_RAW + description: The raw interrupt status bit for txfifo empty when use apb fifo access. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_RAW + description: The raw interrupt status bit for receiving data overflow when use apb fifo access. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: END_DETECT_INT_RAW + description: The raw interrupt status bit for end_detect_int interrupt. when I2C deals with the END command it will produce end_detect_int interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SLAVE_TRAN_COMP_INT_RAW + description: The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detectsthe STOP bit it will produce slave_tran_comp_int interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_RAW + description: The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: MASTER_TRAN_COMP_INT_RAW + description: The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_RAW + description: The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command it will produce trans_complete_int interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_RAW + description: The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data it will produce time_out_int interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TRANS_START_INT_RAW + description: The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: ACK_ERR_INT_RAW + description: The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit it will produce ack_err_int interrupt.. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: RX_REC_FULL_INT_RAW + description: The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TX_SEND_EMPTY_INT_RAW + description: The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt.. + bitOffset: 12 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + addressOffset: 36 + size: 32 + fields: + - name: RXFIFO_FULL_INT_CLR + description: Set this bit to clear the rxfifo_full_int interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TXFIFO_EMPTY_INT_CLR + description: Set this bit to clear the txfifo_empty_int interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RXFIFO_OVF_INT_CLR + description: Set this bit to clear the rxfifo_ovf_int interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: END_DETECT_INT_CLR + description: Set this bit to clear the end_detect_int interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SLAVE_TRAN_COMP_INT_CLR + description: Set this bit to clear the slave_tran_comp_int interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: ARBITRATION_LOST_INT_CLR + description: Set this bit to clear the arbitration_lost_int interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: MASTER_TRAN_COMP_INT_CLR + description: Set this bit to clear the master_tran_comp interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TRANS_COMPLETE_INT_CLR + description: Set this bit to clear the trans_complete_int interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: TIME_OUT_INT_CLR + description: Set this bit to clear the time_out_int interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: TRANS_START_INT_CLR + description: Set this bit to clear the trans_start_int interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: ACK_ERR_INT_CLR + description: Set this bit to clear the ack_err_int interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: RX_REC_FULL_INT_CLR + description: Set this bit to clear the rx_rec_full_int interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TX_SEND_EMPTY_INT_CLR + description: Set this bit to clear the tx_send_empty_int interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + addressOffset: 40 + size: 32 + fields: + - name: RXFIFO_FULL_INT_ENA + description: The enable bit for rxfifo_full_int interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_EMPTY_INT_ENA + description: The enable bit for txfifo_empty_int interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_ENA + description: The enable bit for rxfifo_ovf_int interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: END_DETECT_INT_ENA + description: The enable bit for end_detect_int interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLAVE_TRAN_COMP_INT_ENA + description: The enable bit for slave_tran_comp_int interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ARBITRATION_LOST_INT_ENA + description: The enable bit for arbitration_lost_int interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: MASTER_TRAN_COMP_INT_ENA + description: The enable bit for master_tran_comp_int interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TRANS_COMPLETE_INT_ENA + description: The enable bit for trans_complete_int interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TIME_OUT_INT_ENA + description: The enable bit for time_out_int interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TRANS_START_INT_ENA + description: The enable bit for trans_start_int interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: ACK_ERR_INT_ENA + description: The enable bit for ack_err_int interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: RX_REC_FULL_INT_ENA + description: The enable bit for rx_rec_full_int interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_SEND_EMPTY_INT_ENA + description: The enable bit for tx_send_empty_int interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: INT_STATUS + addressOffset: 44 + size: 32 + fields: + - name: RXFIFO_FULL_INT_ST + description: The masked interrupt status for rxfifo_full_int interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_EMPTY_INT_ST + description: The masked interrupt status for txfifo_empty_int interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_ST + description: The masked interrupt status for rxfifo_ovf_int interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: END_DETECT_INT_ST + description: The masked interrupt status for end_detect_int interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SLAVE_TRAN_COMP_INT_ST + description: The masked interrupt status for slave_tran_comp_int interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_ST + description: The masked interrupt status for arbitration_lost_int interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: MASTER_TRAN_COMP_INT_ST + description: The masked interrupt status for master_tran_comp_int interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_ST + description: The masked interrupt status for trans_complete_int interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_ST + description: The masked interrupt status for time_out_int interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TRANS_START_INT_ST + description: The masked interrupt status for trans_start_int interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: ACK_ERR_INT_ST + description: The masked interrupt status for ack_err_int interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: RX_REC_FULL_INT_ST + description: The masked interrupt status for rx_rec_full_int interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TX_SEND_EMPTY_INT_ST + description: The masked interrupt status for tx_send_empty_int interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - register: + name: SDA_HOLD + addressOffset: 48 + size: 32 + fields: + - name: TIME + description: This register is used to configure the clock num I2C used to hold the data after the negedge of SCL. + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: SDA_SAMPLE + addressOffset: 52 + size: 32 + fields: + - name: TIME + description: This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: SCL_HIGH_PERIOD + addressOffset: 56 + size: 32 + fields: + - name: SCL_HIGH_PERIOD + description: This register is used to configure the clock num during SCL is low level. + bitOffset: 0 + bitWidth: 14 + access: read-write + - register: + name: SCL_START_HOLD + addressOffset: 64 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark. + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: SCL_RSTART_SETUP + addressOffset: 68 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark. + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: SCL_STOP_HOLD + addressOffset: 72 + size: 32 + fields: + - name: TIME + description: "This register is used to configure the clock num after the STOP bit's posedge." + bitOffset: 0 + bitWidth: 14 + access: read-write + - register: + name: SCL_STOP_SETUP + addressOffset: 76 + size: 32 + fields: + - name: TIME + description: This register is used to configure the clock num between the posedge of SCL and the posedge of SDA. + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: SCL_FILTER_CFG + addressOffset: 80 + size: 32 + resetValue: 8 + fields: + - name: SCL_FILTER_THRES + description: "When input SCL's pulse width is smaller than this register value I2C ignores this pulse." + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SCL_FILTER_EN + description: This is the filter enable bit for SCL. + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: SDA_FILTER_CFG + addressOffset: 84 + size: 32 + resetValue: 8 + fields: + - name: SDA_FILTER_THRES + description: "When input SCL's pulse width is smaller than this register value I2C ignores this pulse." + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SDA_FILTER_EN + description: This is the filter enable bit for SDA. + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + dim: 16 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" + name: COMD%s + addressOffset: 88 + size: 32 + fields: + - name: COMMAND + description: "This is the content of command0. It consists of three part. op_code is the command 0: RSTART 1: WRITE 2: READ 3: STOP . 4:END. Byte_num represent the number of data need to be send or data need to be received. ack_check_en ack_exp and ack value are used to control the ack bit." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND_DONE + description: When command0 is done in I2C Master mode this bit changes to high level. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DATE + addressOffset: 248 + size: 32 + resetValue: 369369088 + fields: + - name: DATE + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FIFO_START_ADDR + addressOffset: 256 + size: 32 + - name: I2C1 + description: I2C (Inter-Integrated Circuit) Controller 1 + baseAddress: 1073115136 + interrupt: + - name: I2C_EXT1 + value: 50 + derivedFrom: I2C0 + - name: I2S0 + description: I2S (Inter-IC Sound) Controller 0 + groupName: I2S + baseAddress: 1073016832 + addressBlock: + - offset: 0 + size: 180 + usage: registers + interrupt: + - name: I2S0 + value: 32 + registers: + - register: + name: CONF + addressOffset: 8 + size: 32 + resetValue: 197376 + fields: + - name: TX_RESET + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_RESET + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TX_FIFO_RESET + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_FIFO_RESET + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_START + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_START + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TX_SLAVE_MOD + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_SLAVE_MOD + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TX_RIGHT_FIRST + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RX_RIGHT_FIRST + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TX_MSB_SHIFT + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: RX_MSB_SHIFT + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_SHORT_SYNC + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RX_SHORT_SYNC + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_MONO + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RX_MONO + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TX_MSB_RIGHT + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RX_MSB_RIGHT + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SIG_LOOPBACK + bitOffset: 18 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + addressOffset: 12 + size: 32 + fields: + - name: RX_TAKE_DATA_INT_RAW + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_PUT_DATA_INT_RAW + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_WFULL_INT_RAW + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: RX_REMPTY_INT_RAW + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TX_WFULL_INT_RAW + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TX_REMPTY_INT_RAW + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_RAW + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_RAW + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IN_DONE_INT_RAW + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: IN_SUC_EOF_INT_RAW + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: IN_ERR_EOF_INT_RAW + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: OUT_DONE_INT_RAW + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: OUT_EOF_INT_RAW + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: IN_DSCR_ERR_INT_RAW + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: OUT_DSCR_ERR_INT_RAW + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: IN_DSCR_EMPTY_INT_RAW + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: OUT_TOTAL_EOF_INT_RAW + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + addressOffset: 16 + size: 32 + fields: + - name: RX_TAKE_DATA_INT_ST + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_PUT_DATA_INT_ST + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_WFULL_INT_ST + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: RX_REMPTY_INT_ST + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TX_WFULL_INT_ST + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TX_REMPTY_INT_ST + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_ST + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_ST + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IN_DONE_INT_ST + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: IN_SUC_EOF_INT_ST + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: IN_ERR_EOF_INT_ST + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: OUT_DONE_INT_ST + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: OUT_EOF_INT_ST + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: IN_DSCR_ERR_INT_ST + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: OUT_DSCR_ERR_INT_ST + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: IN_DSCR_EMPTY_INT_ST + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: OUT_TOTAL_EOF_INT_ST + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + addressOffset: 20 + size: 32 + fields: + - name: RX_TAKE_DATA_INT_ENA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_PUT_DATA_INT_ENA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_WFULL_INT_ENA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_REMPTY_INT_ENA + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_WFULL_INT_ENA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TX_REMPTY_INT_ENA + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RX_HUNG_INT_ENA + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_HUNG_INT_ENA + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IN_DONE_INT_ENA + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF_INT_ENA + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF_INT_ENA + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OUT_DONE_INT_ENA + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: OUT_EOF_INT_ENA + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR_INT_ENA + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR_INT_ENA + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY_INT_ENA + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF_INT_ENA + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + addressOffset: 24 + size: 32 + fields: + - name: TAKE_DATA_INT_CLR + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: PUT_DATA_INT_CLR + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_WFULL_INT_CLR + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: RX_REMPTY_INT_CLR + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TX_WFULL_INT_CLR + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: TX_REMPTY_INT_CLR + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: RX_HUNG_INT_CLR + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TX_HUNG_INT_CLR + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: IN_DONE_INT_CLR + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: IN_SUC_EOF_INT_CLR + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: IN_ERR_EOF_INT_CLR + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: OUT_DONE_INT_CLR + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: OUT_EOF_INT_CLR + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: IN_DSCR_ERR_INT_CLR + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: OUT_DSCR_ERR_INT_CLR + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: IN_DSCR_EMPTY_INT_CLR + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: OUT_TOTAL_EOF_INT_CLR + bitOffset: 16 + bitWidth: 1 + access: write-only + - register: + name: TIMING + addressOffset: 28 + size: 32 + fields: + - name: TX_BCK_IN_DELAY + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: TX_WS_IN_DELAY + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: RX_BCK_IN_DELAY + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: RX_WS_IN_DELAY + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: RX_SD_IN_DELAY + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: TX_BCK_OUT_DELAY + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: TX_WS_OUT_DELAY + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: TX_SD_OUT_DELAY + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: RX_WS_OUT_DELAY + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: RX_BCK_OUT_DELAY + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: TX_DSYNC_SW + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: RX_DSYNC_SW + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: DATA_ENABLE_DELAY + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: TX_BCK_IN_INV + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: FIFO_CONF + addressOffset: 32 + size: 32 + resetValue: 6176 + fields: + - name: RX_DATA_NUM + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: TX_DATA_NUM + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: DSCR_EN + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_FIFO_MOD + bitOffset: 13 + bitWidth: 3 + access: read-write + - name: RX_FIFO_MOD + bitOffset: 16 + bitWidth: 3 + access: read-write + - name: TX_FIFO_MOD_FORCE_EN + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RX_FIFO_MOD_FORCE_EN + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: RXEOF_NUM + addressOffset: 36 + size: 32 + resetValue: 64 + fields: + - name: RX_EOF_NUM + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CONF_SIGLE_DATA + addressOffset: 40 + size: 32 + fields: + - name: SIGLE_DATA + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CONF_CHAN + addressOffset: 44 + size: 32 + fields: + - name: TX_CHAN_MOD + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: RX_CHAN_MOD + bitOffset: 3 + bitWidth: 2 + access: read-write + - register: + name: OUT_LINK + addressOffset: 48 + size: 32 + fields: + - name: OUTLINK_ADDR + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: OUTLINK_STOP + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: OUTLINK_START + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: OUTLINK_RESTART + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: OUTLINK_PARK + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: IN_LINK + addressOffset: 52 + size: 32 + fields: + - name: INLINK_ADDR + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: INLINK_STOP + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: INLINK_START + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: INLINK_RESTART + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: INLINK_PARK + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: OUT_EOF_DES_ADDR + addressOffset: 56 + size: 32 + fields: + - name: OUT_EOF_DES_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_EOF_DES_ADDR + addressOffset: 60 + size: 32 + fields: + - name: IN_SUC_EOF_DES_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_EOF_BFR_DES_ADDR + addressOffset: 64 + size: 32 + fields: + - name: OUT_EOF_BFR_DES_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: AHB_TEST + addressOffset: 68 + size: 32 + fields: + - name: AHB_TESTMODE + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: AHB_TESTADDR + bitOffset: 4 + bitWidth: 2 + access: read-write + - register: + name: INLINK_DSCR + addressOffset: 72 + size: 32 + fields: + - name: INLINK_DSCR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INLINK_DSCR_BF0 + addressOffset: 76 + size: 32 + fields: + - name: INLINK_DSCR_BF0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INLINK_DSCR_BF1 + addressOffset: 80 + size: 32 + fields: + - name: INLINK_DSCR_BF1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUTLINK_DSCR + addressOffset: 84 + size: 32 + fields: + - name: OUTLINK_DSCR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUTLINK_DSCR_BF0 + addressOffset: 88 + size: 32 + fields: + - name: OUTLINK_DSCR_BF0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUTLINK_DSCR_BF1 + addressOffset: 92 + size: 32 + fields: + - name: OUTLINK_DSCR_BF1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: LC_CONF + addressOffset: 96 + size: 32 + resetValue: 256 + fields: + - name: IN_RST + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_RST + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AHBM_FIFO_RST + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: AHBM_RST + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUT_LOOP_TEST + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IN_LOOP_TEST + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUT_AUTO_WRBACK + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUT_NO_RESTART_CLR + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_EOF_MODE + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: OUTDSCR_BURST_EN + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: INDSCR_BURST_EN + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OUT_DATA_BURST_EN + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CHECK_OWNER + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: MEM_TRANS_EN + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: OUTFIFO_PUSH + addressOffset: 100 + size: 32 + fields: + - name: OUTFIFO_WDATA + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: OUTFIFO_PUSH + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: INFIFO_POP + addressOffset: 104 + size: 32 + fields: + - name: INFIFO_RDATA + bitOffset: 0 + bitWidth: 12 + access: read-only + - name: INFIFO_POP + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: LC_STATE0 + addressOffset: 108 + size: 32 + fields: + - name: LC_STATE0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: LC_STATE1 + addressOffset: 112 + size: 32 + fields: + - name: LC_STATE1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: LC_HUNG_CONF + addressOffset: 116 + size: 32 + resetValue: 2064 + fields: + - name: LC_FIFO_TIMEOUT + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: LC_FIFO_TIMEOUT_SHIFT + bitOffset: 8 + bitWidth: 3 + access: read-write + - name: LC_FIFO_TIMEOUT_ENA + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: CVSD_CONF0 + addressOffset: 128 + size: 32 + resetValue: 2147516415 + fields: + - name: CVSD_Y_MAX + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CVSD_Y_MIN + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: CVSD_CONF1 + addressOffset: 132 + size: 32 + resetValue: 656640 + fields: + - name: CVSD_SIGMA_MAX + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CVSD_SIGMA_MIN + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: CVSD_CONF2 + addressOffset: 136 + size: 32 + resetValue: 328356 + fields: + - name: CVSD_K + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: CVSD_J + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: CVSD_BETA + bitOffset: 6 + bitWidth: 10 + access: read-write + - name: CVSD_H + bitOffset: 16 + bitWidth: 3 + access: read-write + - register: + name: PLC_CONF0 + addressOffset: 140 + size: 32 + resetValue: 145228601 + fields: + - name: GOOD_PACK_MAX + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: N_ERR_SEG + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: SHIFT_RATE + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: MAX_SLIDE_SAMPLE + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: PACK_LEN_8K + bitOffset: 20 + bitWidth: 5 + access: read-write + - name: N_MIN_ERR + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: PLC_CONF1 + addressOffset: 144 + size: 32 + resetValue: 2685897221 + fields: + - name: BAD_CEF_ATTEN_PARA + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: BAD_CEF_ATTEN_PARA_SHIFT + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: BAD_OLA_WIN2_PARA_SHIFT + bitOffset: 12 + bitWidth: 4 + access: read-write + - name: BAD_OLA_WIN2_PARA + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SLIDE_WIN_LEN + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: PLC_CONF2 + addressOffset: 148 + size: 32 + resetValue: 40 + fields: + - name: CVSD_SEG_MOD + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: MIN_PERIOD + bitOffset: 2 + bitWidth: 5 + access: read-write + - register: + name: ESCO_CONF0 + addressOffset: 152 + size: 32 + fields: + - name: ESCO_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ESCO_CHAN_MOD + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ESCO_CVSD_DEC_PACK_ERR + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ESCO_CVSD_PACK_LEN_8K + bitOffset: 3 + bitWidth: 5 + access: read-write + - name: ESCO_CVSD_INF_EN + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CVSD_DEC_START + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CVSD_DEC_RESET + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: PLC_EN + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: PLC2DMA_EN + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: SCO_CONF0 + addressOffset: 156 + size: 32 + fields: + - name: SCO_WITH_I2S_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCO_NO_I2S_EN + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CVSD_ENC_START + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CVSD_ENC_RESET + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: CONF1 + addressOffset: 160 + size: 32 + resetValue: 137 + fields: + - name: TX_PCM_CONF + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: TX_PCM_BYPASS + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_PCM_CONF + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: RX_PCM_BYPASS + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TX_STOP_EN + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TX_ZEROS_RM_EN + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: PD_CONF + addressOffset: 164 + size: 32 + resetValue: 10 + fields: + - name: FIFO_FORCE_PD + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FIFO_FORCE_PU + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PLC_MEM_FORCE_PD + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PLC_MEM_FORCE_PU + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: CONF2 + addressOffset: 168 + size: 32 + fields: + - name: CAMERA_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LCD_TX_WRX2_EN + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: LCD_TX_SDX2_EN + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DATA_ENABLE_TEST_EN + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DATA_ENABLE + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: LCD_EN + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: EXT_ADC_START_EN + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: INTER_VALID_EN + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: CLKM_CONF + addressOffset: 172 + size: 32 + resetValue: 4 + fields: + - name: CLKM_DIV_NUM + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CLKM_DIV_B + bitOffset: 8 + bitWidth: 6 + access: read-write + - name: CLKM_DIV_A + bitOffset: 14 + bitWidth: 6 + access: read-write + - name: CLK_EN + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CLKA_ENA + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + name: SAMPLE_RATE_CONF + addressOffset: 176 + size: 32 + resetValue: 4260230 + fields: + - name: TX_BCK_DIV_NUM + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: RX_BCK_DIV_NUM + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: TX_BITS_MOD + bitOffset: 12 + bitWidth: 6 + access: read-write + - name: RX_BITS_MOD + bitOffset: 18 + bitWidth: 6 + access: read-write + - register: + name: PDM_CONF + addressOffset: 180 + size: 32 + resetValue: 22347808 + fields: + - name: TX_PDM_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_PDM_EN + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PCM2PDM_CONV_EN + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PDM2PCM_CONV_EN + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_PDM_SINC_OSR2 + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: TX_PDM_PRESCALE + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: TX_PDM_HP_IN_SHIFT + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: TX_PDM_LP_IN_SHIFT + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: TX_PDM_SINC_IN_SHIFT + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TX_PDM_SIGMADELTA_IN_SHIFT + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: RX_PDM_SINC_DSR_16_EN + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TX_PDM_HP_BYPASS + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: PDM_FREQ_CONF + addressOffset: 184 + size: 32 + resetValue: 983520 + fields: + - name: TX_PDM_FS + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: TX_PDM_FP + bitOffset: 10 + bitWidth: 10 + access: read-write + - register: + name: STATE + addressOffset: 188 + size: 32 + resetValue: 7 + fields: + - name: TX_IDLE + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_FIFO_RESET_BACK + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_FIFO_RESET_BACK + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: DATE + addressOffset: 252 + size: 32 + resetValue: 23085569 + fields: + - name: I2SDATE + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: I2S1 + description: I2S (Inter-IC Sound) Controller 1 + baseAddress: 1073139712 + interrupt: + - name: I2S1 + value: 33 + derivedFrom: I2S0 + - name: IO_MUX + description: Input/Output Multiplexer + groupName: IO_MUX + baseAddress: 1072992256 + addressBlock: + - offset: 0 + size: 148 + usage: registers + registers: + - register: + name: PIN_CTRL + addressOffset: 0 + size: 32 + fields: + - name: CLK1 + description: "If you want to output clock for I2S0 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0x0; CLK_OUT2, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[11:8] = 0x0. If you want to output clock for I2S1 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0xF; CLK_OUT2, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[11:8] = 0x0." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: CLK2 + description: "If you want to output clock for I2S0 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0x0; CLK_OUT2, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[11:8] = 0x0. If you want to output clock for I2S1 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0xF; CLK_OUT2, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[11:8] = 0x0." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: CLK3 + description: "If you want to output clock for I2S0 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0x0; CLK_OUT2, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0x0 and PIN_CTRL[11:8] = 0x0. If you want to output clock for I2S1 to: CLK_OUT1, then set PIN_CTRL[3:0] = 0xF; CLK_OUT2, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[7:4] = 0x0; CLK_OUT3, then set PIN_CTRL[3:0] = 0xF and PIN_CTRL[11:8] = 0x0." + bitOffset: 8 + bitWidth: 4 + access: read-write + - register: + name: GPIO36 + addressOffset: 4 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO37 + addressOffset: 8 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO38 + addressOffset: 12 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO39 + addressOffset: 16 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO34 + addressOffset: 20 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO35 + addressOffset: 24 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO32 + addressOffset: 28 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO33 + addressOffset: 32 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO25 + addressOffset: 36 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO26 + addressOffset: 40 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO27 + addressOffset: 44 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO14 + addressOffset: 48 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO12 + addressOffset: 52 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO13 + addressOffset: 56 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO15 + addressOffset: 60 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO2 + addressOffset: 64 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO0 + addressOffset: 68 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO4 + addressOffset: 72 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO16 + addressOffset: 76 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO17 + addressOffset: 80 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO9 + addressOffset: 84 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO10 + addressOffset: 88 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO11 + addressOffset: 92 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO6 + addressOffset: 96 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO7 + addressOffset: 100 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO8 + addressOffset: 104 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO5 + addressOffset: 108 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO18 + addressOffset: 112 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO19 + addressOffset: 116 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO20 + addressOffset: 120 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO21 + addressOffset: 124 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO22 + addressOffset: 128 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO3 + addressOffset: 132 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO1 + addressOffset: 136 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO23 + addressOffset: 140 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO24 + addressOffset: 144 + size: 32 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: enable output; 0: disable output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: Select the drive strength of the pad during sleep mode. A higher value corresponds with a higher strength. + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull-down circuitry, therefore, their FUN_WPD is always 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. GPIO pins 34-39 are input-only. These pins do not feature an output driver or internal pull- up/pull- down circuitry, therefore, their FUN_WPU is always 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. A higher value corresponds with a higher strength. For GPIO34-39, FUN_DRV is always 0. For detailed drive strength, please see note 8 in Table ”Notes on ESP32 Pin Lists”, in ESP32 Datasheet." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select the IO_MUX function for this signal. 0 selects Function 0, 1 selects Function 1, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: LEDC + description: LED Control PWM (Pulse Width Modulation) + groupName: LEDC + baseAddress: 1073057792 + addressBlock: + - offset: 0 + size: 408 + usage: registers + interrupt: + - name: LEDC + value: 43 + - name: TIMER1 + value: 56 + - name: TIMER2 + value: 57 + registers: + - register: + dim: 8 + dimIncrement: 20 + dimIndex: "0,1,2,3,4,5,6,7" + name: HSCH%s_CONF0 + addressOffset: 0 + size: 32 + fields: + - name: TIMER_SEL + description: "There are four high speed timers the two bits are used to select one of them for high speed channel0. 2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SIG_OUT_EN + description: This is the output enable control bit for high speed channel0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IDLE_LV + description: This bit is used to control the output value when high speed channel0 is off. + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + dim: 8 + dimIncrement: 20 + dimIndex: "0,1,2,3,4,5,6,7" + name: HSCH%s_HPOINT + addressOffset: 4 + size: 32 + fields: + - name: HPOINT + description: "The output value changes to high when htimerx(x=[0 3]) selected by high speed channel0 has reached reg_hpoint_hsch0[19:0]" + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + dim: 8 + dimIncrement: 20 + dimIndex: "0,1,2,3,4,5,6,7" + name: HSCH%s_DUTY + addressOffset: 8 + size: 32 + fields: + - name: DUTY + description: This register represents the current duty of the output signal for high speed channel0. + bitOffset: 0 + bitWidth: 25 + access: read-write + - register: + dim: 8 + dimIncrement: 20 + dimIndex: "0,1,2,3,4,5,6,7" + name: HSCH%s_CONF1 + addressOffset: 12 + size: 32 + resetValue: 1073741824 + fields: + - name: DUTY_SCALE + description: This register controls the increase or decrease step scale for high speed channel0. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: DUTY_CYCLE + description: This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel0. + bitOffset: 10 + bitWidth: 10 + access: read-write + - name: DUTY_NUM + description: This register is used to control the num of increased or decreased times for high speed channel0. + bitOffset: 20 + bitWidth: 10 + access: read-write + - name: DUTY_INC + description: This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel0. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DUTY_START + description: "When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + dim: 8 + dimIncrement: 20 + dimIndex: "0,1,2,3,4,5,6,7" + name: HSCH%s_DUTY_R + addressOffset: 16 + size: 32 + fields: + - name: DUTY_R + description: This register represents the current duty cycle of the output signal for high-speed channel %s + bitOffset: 0 + bitWidth: 25 + access: read-only + - register: + dim: 8 + dimIncrement: 20 + dimIndex: "0,1,2,3,4,5,6,7" + name: LSCH%s_CONF0 + addressOffset: 160 + size: 32 + fields: + - name: TIMER_SEL + description: "There are four low speed timers the two bits are used to select one of them for low speed channel0. 2'b00: seletc lstimer0. 2'b01: select lstimer1. 2'b10: select lstimer2. 2'b11: select lstimer3." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SIG_OUT_EN + description: This is the output enable control bit for low speed channel0. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IDLE_LV + description: This bit is used to control the output value when low speed channel0 is off. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PARA_UP + description: This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY for low speed channel0. + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + dim: 8 + dimIncrement: 20 + dimIndex: "0,1,2,3,4,5,6,7" + name: LSCH%s_HPOINT + addressOffset: 164 + size: 32 + fields: + - name: HPOINT + description: "The output value changes to high when lstimerx(x=[0 3]) selected by low speed channel0 has reached reg_hpoint_lsch0[19:0]" + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + dim: 8 + dimIncrement: 20 + dimIndex: "0,1,2,3,4,5,6,7" + name: LSCH%s_DUTY + addressOffset: 168 + size: 32 + access: read-write + fields: + - name: DUTY + description: This register represents the current duty of the output signal for low speed channel0. + bitOffset: 0 + bitWidth: 25 + access: read-write + - register: + dim: 8 + dimIncrement: 20 + dimIndex: "0,1,2,3,4,5,6,7" + name: LSCH%s_CONF1 + addressOffset: 172 + size: 32 + resetValue: 1073741824 + fields: + - name: DUTY_SCALE + description: This register controls the increase or decrease step scale for low speed channel0. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: DUTY_CYCLE + description: This register is used to increase or decrease the duty every reg_duty_cycle_lsch0 cycles for low speed channel0. + bitOffset: 10 + bitWidth: 10 + access: read-write + - name: DUTY_NUM + description: This register is used to control the num of increased or decreased times for low speed channel6. + bitOffset: 20 + bitWidth: 10 + access: read-write + - name: DUTY_INC + description: This register is used to increase the duty of output signal or decrease the duty of output signal for low speed channel6. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DUTY_START + description: "When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1 has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + dim: 8 + dimIncrement: 20 + dimIndex: "0,1,2,3,4,5,6,7" + name: LSCH%s_DUTY_R + addressOffset: 176 + size: 32 + fields: + - name: DUTY_R + description: This register represents the current duty cycle of the output signal for low-speed channel %s + bitOffset: 0 + bitWidth: 25 + access: read-only + - register: + dim: 4 + dimIncrement: 8 + dimIndex: "0,1,2,3" + name: HSTIMER%s_CONF + addressOffset: 320 + size: 32 + resetValue: 16777216 + fields: + - name: DUTY_RES + description: "This register controls the range of the counter in high speed timer0. the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20." + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: DIV_NUM + description: This register is used to configure parameter for divider in high speed timer0 the least significant eight bits represent the decimal part. + bitOffset: 5 + bitWidth: 18 + access: read-write + - name: PAUSE + description: This bit is used to pause the counter in high speed timer0 + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: RST + description: This bit is used to reset high speed timer0 the counter will be 0 after reset. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TICK_SEL + description: "This bit is used to choose apb_clk or ref_tick for high speed timer0. 1'b1:apb_clk 0:ref_tick" + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + dim: 4 + dimIncrement: 8 + dimIndex: "0,1,2,3" + name: HSTIMER%s_VALUE + addressOffset: 324 + size: 32 + fields: + - name: CNT + description: software can read this register to get the current counter value in high speed timer0 + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + dim: 4 + dimIncrement: 8 + dimIndex: "0,1,2,3" + name: LSTIMER%s_CONF + addressOffset: 352 + size: 32 + resetValue: 16777216 + fields: + - name: DUTY_RES + description: "This register controls the range of the counter in low speed timer0. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20." + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: DIV_NUM + description: This register is used to configure parameter for divider in low speed timer0 the least significant eight bits represent the decimal part. + bitOffset: 5 + bitWidth: 18 + access: read-write + - name: PAUSE + description: This bit is used to pause the counter in low speed timer0. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: RST + description: This bit is used to reset low speed timer0 the counter will be 0 after reset. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TICK_SEL + description: "This bit is used to choose slow_clk or ref_tick for low speed timer0. 1'b1:slow_clk 0:ref_tick" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PARA_UP + description: Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim. + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + dim: 4 + dimIncrement: 8 + dimIndex: "0,1,2,3" + name: LSTIMER%s_VALUE + addressOffset: 356 + size: 32 + fields: + - name: CNT + description: software can read this register to get the current counter value in low speed timer0. + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: INT_RAW + addressOffset: 384 + size: 32 + fields: + - name: HSTIMER0_OVF_INT_RAW + description: The interrupt raw bit for high speed channel0 counter overflow. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: HSTIMER1_OVF_INT_RAW + description: The interrupt raw bit for high speed channel1 counter overflow. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: HSTIMER2_OVF_INT_RAW + description: The interrupt raw bit for high speed channel2 counter overflow. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: HSTIMER3_OVF_INT_RAW + description: The interrupt raw bit for high speed channel3 counter overflow. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: LSTIMER0_OVF_INT_RAW + description: The interrupt raw bit for low speed channel0 counter overflow. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: LSTIMER1_OVF_INT_RAW + description: The interrupt raw bit for low speed channel1 counter overflow. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: LSTIMER2_OVF_INT_RAW + description: The interrupt raw bit for low speed channel2 counter overflow. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: LSTIMER3_OVF_INT_RAW + description: The interrupt raw bit for low speed channel3 counter overflow. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_HSCH0_INT_RAW + description: The interrupt raw bit for high speed channel 0 duty change done. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_HSCH1_INT_RAW + description: The interrupt raw bit for high speed channel 1 duty change done. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_HSCH2_INT_RAW + description: The interrupt raw bit for high speed channel 2 duty change done. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_HSCH3_INT_RAW + description: The interrupt raw bit for high speed channel 3 duty change done. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_HSCH4_INT_RAW + description: The interrupt raw bit for high speed channel 4 duty change done. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_HSCH5_INT_RAW + description: The interrupt raw bit for high speed channel 5 duty change done. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_HSCH6_INT_RAW + description: The interrupt raw bit for high speed channel 6 duty change done. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_HSCH7_INT_RAW + description: The interrupt raw bit for high speed channel 7 duty change done. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_LSCH0_INT_RAW + description: The interrupt raw bit for low speed channel 0 duty change done. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_LSCH1_INT_RAW + description: The interrupt raw bit for low speed channel 1 duty change done. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_LSCH2_INT_RAW + description: The interrupt raw bit for low speed channel 2 duty change done. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_LSCH3_INT_RAW + description: The interrupt raw bit for low speed channel 3 duty change done. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_LSCH4_INT_RAW + description: The interrupt raw bit for low speed channel 4 duty change done. + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_LSCH5_INT_RAW + description: The interrupt raw bit for low speed channel 5 duty change done. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_LSCH6_INT_RAW + description: The interrupt raw bit for low speed channel 6 duty change done. + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_LSCH7_INT_RAW + description: The interrupt raw bit for low speed channel 7 duty change done. + bitOffset: 23 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + addressOffset: 388 + size: 32 + fields: + - name: HSTIMER0_OVF_INT_ST + description: The interrupt status bit for high speed channel0 counter overflow event. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: HSTIMER1_OVF_INT_ST + description: The interrupt status bit for high speed channel1 counter overflow event. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: HSTIMER2_OVF_INT_ST + description: The interrupt status bit for high speed channel2 counter overflow event. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: HSTIMER3_OVF_INT_ST + description: The interrupt status bit for high speed channel3 counter overflow event. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: LSTIMER0_OVF_INT_ST + description: The interrupt status bit for low speed channel0 counter overflow event. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: LSTIMER1_OVF_INT_ST + description: The interrupt status bit for low speed channel1 counter overflow event. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: LSTIMER2_OVF_INT_ST + description: The interrupt status bit for low speed channel2 counter overflow event. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: LSTIMER3_OVF_INT_ST + description: The interrupt status bit for low speed channel3 counter overflow event. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_HSCH0_INT_ST + description: The interrupt status bit for high speed channel 0 duty change done event. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_HSCH1_INT_ST + description: The interrupt status bit for high speed channel 1 duty change done event. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_HSCH2_INT_ST + description: The interrupt status bit for high speed channel 2 duty change done event. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_HSCH3_INT_ST + description: The interrupt status bit for high speed channel 3 duty change done event. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_HSCH4_INT_ST + description: The interrupt status bit for high speed channel 4 duty change done event. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_HSCH5_INT_ST + description: The interrupt status bit for high speed channel 5 duty change done event. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_HSCH6_INT_ST + description: The interrupt status bit for high speed channel 6 duty change done event. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_HSCH7_INT_ST + description: The interrupt status bit for high speed channel 7 duty change done event. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_LSCH0_INT_ST + description: The interrupt status bit for low speed channel 0 duty change done event. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_LSCH1_INT_ST + description: The interrupt status bit for low speed channel 1 duty change done event. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_LSCH2_INT_ST + description: The interrupt status bit for low speed channel 2 duty change done event. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_LSCH3_INT_ST + description: The interrupt status bit for low speed channel 3 duty change done event. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_LSCH4_INT_ST + description: The interrupt status bit for low speed channel 4 duty change done event. + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_LSCH5_INT_ST + description: The interrupt status bit for low speed channel 5 duty change done event. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_LSCH6_INT_ST + description: The interrupt status bit for low speed channel 6 duty change done event. + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_LSCH7_INT_ST + description: The interrupt status bit for low speed channel 7 duty change done event + bitOffset: 23 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + addressOffset: 392 + size: 32 + fields: + - name: HSTIMER0_OVF_INT_ENA + description: The interrupt enable bit for high speed channel0 counter overflow interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: HSTIMER1_OVF_INT_ENA + description: The interrupt enable bit for high speed channel1 counter overflow interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: HSTIMER2_OVF_INT_ENA + description: The interrupt enable bit for high speed channel2 counter overflow interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: HSTIMER3_OVF_INT_ENA + description: The interrupt enable bit for high speed channel3 counter overflow interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: LSTIMER0_OVF_INT_ENA + description: The interrupt enable bit for low speed channel0 counter overflow interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: LSTIMER1_OVF_INT_ENA + description: The interrupt enable bit for low speed channel1 counter overflow interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: LSTIMER2_OVF_INT_ENA + description: The interrupt enable bit for low speed channel2 counter overflow interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: LSTIMER3_OVF_INT_ENA + description: The interrupt enable bit for low speed channel3 counter overflow interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_HSCH0_INT_ENA + description: The interrupt enable bit for high speed channel 0 duty change done interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_HSCH1_INT_ENA + description: The interrupt enable bit for high speed channel 1 duty change done interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_HSCH2_INT_ENA + description: The interrupt enable bit for high speed channel 2 duty change done interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_HSCH3_INT_ENA + description: The interrupt enable bit for high speed channel 3 duty change done interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_HSCH4_INT_ENA + description: The interrupt enable bit for high speed channel 4 duty change done interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_HSCH5_INT_ENA + description: The interrupt enable bit for high speed channel 5 duty change done interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_HSCH6_INT_ENA + description: The interrupt enable bit for high speed channel 6 duty change done interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_HSCH7_INT_ENA + description: The interrupt enable bit for high speed channel 7 duty change done interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_LSCH0_INT_ENA + description: The interrupt enable bit for low speed channel 0 duty change done interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_LSCH1_INT_ENA + description: The interrupt enable bit for low speed channel 1 duty change done interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_LSCH2_INT_ENA + description: The interrupt enable bit for low speed channel 2 duty change done interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_LSCH3_INT_ENA + description: The interrupt enable bit for low speed channel 3 duty change done interrupt. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_LSCH4_INT_ENA + description: The interrupt enable bit for low speed channel 4 duty change done interrupt. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_LSCH5_INT_ENA + description: The interrupt enable bit for low speed channel 5 duty change done interrupt. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_LSCH6_INT_ENA + description: The interrupt enable bit for low speed channel 6 duty change done interrupt. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_LSCH7_INT_ENA + description: The interrupt enable bit for low speed channel 7 duty change done interrupt. + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + addressOffset: 396 + size: 32 + fields: + - name: HSTIMER0_OVF_INT_CLR + description: Set this bit to clear high speed channel0 counter overflow interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: HSTIMER1_OVF_INT_CLR + description: Set this bit to clear high speed channel1 counter overflow interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: HSTIMER2_OVF_INT_CLR + description: Set this bit to clear high speed channel2 counter overflow interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: HSTIMER3_OVF_INT_CLR + description: Set this bit to clear high speed channel3 counter overflow interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: LSTIMER0_OVF_INT_CLR + description: Set this bit to clear low speed channel0 counter overflow interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: LSTIMER1_OVF_INT_CLR + description: Set this bit to clear low speed channel1 counter overflow interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: LSTIMER2_OVF_INT_CLR + description: Set this bit to clear low speed channel2 counter overflow interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: LSTIMER3_OVF_INT_CLR + description: Set this bit to clear low speed channel3 counter overflow interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_HSCH0_INT_CLR + description: Set this bit to clear high speed channel 0 duty change done interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_HSCH1_INT_CLR + description: Set this bit to clear high speed channel 1 duty change done interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_HSCH2_INT_CLR + description: Set this bit to clear high speed channel 2 duty change done interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_HSCH3_INT_CLR + description: Set this bit to clear high speed channel 3 duty change done interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_HSCH4_INT_CLR + description: Set this bit to clear high speed channel 4 duty change done interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_HSCH5_INT_CLR + description: Set this bit to clear high speed channel 5 duty change done interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_HSCH6_INT_CLR + description: Set this bit to clear high speed channel 6 duty change done interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_HSCH7_INT_CLR + description: Set this bit to clear high speed channel 7 duty change done interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_LSCH0_INT_CLR + description: Set this bit to clear low speed channel 0 duty change done interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_LSCH1_INT_CLR + description: Set this bit to clear low speed channel 1 duty change done interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_LSCH2_INT_CLR + description: Set this bit to clear low speed channel 2 duty change done interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_LSCH3_INT_CLR + description: Set this bit to clear low speed channel 3 duty change done interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_LSCH4_INT_CLR + description: Set this bit to clear low speed channel 4 duty change done interrupt. + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_LSCH5_INT_CLR + description: Set this bit to clear low speed channel 5 duty change done interrupt. + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_LSCH6_INT_CLR + description: Set this bit to clear low speed channel 6 duty change done interrupt. + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_LSCH7_INT_CLR + description: Set this bit to clear low speed channel 7 duty change done interrupt. + bitOffset: 23 + bitWidth: 1 + access: write-only + - register: + name: CONF + addressOffset: 400 + size: 32 + fields: + - name: APB_CLK_SEL + description: "This bit is used to set the frequency of slow_clk. 1'b1:80mhz 1'b0:8mhz" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + addressOffset: 508 + size: 32 + resetValue: 369301248 + fields: + - name: DATE + description: This register represents the version . + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: MCPWM0 + description: Motor Control Pulse-Width Modulation 0 + groupName: MCPWM + baseAddress: 1073078272 + addressBlock: + - offset: 0 + size: 296 + usage: registers + interrupt: + - name: MCPWM0 + value: 39 + - name: MCPWM1 + value: 40 + - name: MCPWM2 + value: 41 + - name: MCPWM3 + value: 42 + registers: + - register: + name: CLK_CFG + addressOffset: 0 + size: 32 + fields: + - name: CLK_PRESCALE + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: TIMER0_CFG0 + addressOffset: 4 + size: 32 + resetValue: 65280 + fields: + - name: TIMER0_PRESCALE + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TIMER0_PERIOD + bitOffset: 8 + bitWidth: 16 + access: read-write + - name: TIMER0_PERIOD_UPMETHOD + bitOffset: 24 + bitWidth: 2 + access: read-write + - register: + name: TIMER0_CFG1 + addressOffset: 8 + size: 32 + fields: + - name: TIMER0_START + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: TIMER0_MOD + bitOffset: 3 + bitWidth: 2 + access: read-write + - register: + name: TIMER0_SYNC + addressOffset: 12 + size: 32 + fields: + - name: TIMER0_SYNCI_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SW + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER0_SYNCO_SEL + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: TIMER0_PHASE + bitOffset: 4 + bitWidth: 16 + access: read-write + - name: TIMER0_PHASE_DIRECTION + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: TIMER0_STATUS + addressOffset: 16 + size: 32 + fields: + - name: TIMER0_VALUE + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: TIMER0_DIRECTION + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: TIMER1_CFG0 + addressOffset: 20 + size: 32 + resetValue: 65280 + fields: + - name: TIMER1_PRESCALE + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TIMER1_PERIOD + bitOffset: 8 + bitWidth: 16 + access: read-write + - name: TIMER1_PERIOD_UPMETHOD + bitOffset: 24 + bitWidth: 2 + access: read-write + - register: + name: TIMER1_CFG1 + addressOffset: 24 + size: 32 + fields: + - name: TIMER1_START + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: TIMER1_MOD + bitOffset: 3 + bitWidth: 2 + access: read-write + - register: + name: TIMER1_SYNC + addressOffset: 28 + size: 32 + fields: + - name: TIMER1_SYNCI_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SW + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER1_SYNCO_SEL + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: TIMER1_PHASE + bitOffset: 4 + bitWidth: 16 + access: read-write + - name: TIMER1_PHASE_DIRECTION + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: TIMER1_STATUS + addressOffset: 32 + size: 32 + fields: + - name: TIMER1_VALUE + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: TIMER1_DIRECTION + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: TIMER2_CFG0 + addressOffset: 36 + size: 32 + resetValue: 65280 + fields: + - name: TIMER2_PRESCALE + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TIMER2_PERIOD + bitOffset: 8 + bitWidth: 16 + access: read-write + - name: TIMER2_PERIOD_UPMETHOD + bitOffset: 24 + bitWidth: 2 + access: read-write + - register: + name: TIMER2_CFG1 + addressOffset: 40 + size: 32 + fields: + - name: TIMER2_START + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: TIMER2_MOD + bitOffset: 3 + bitWidth: 2 + access: read-write + - register: + name: TIMER2_SYNC + addressOffset: 44 + size: 32 + fields: + - name: TIMER2_SYNCI_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SW + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER2_SYNCO_SEL + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: TIMER2_PHASE + bitOffset: 4 + bitWidth: 16 + access: read-write + - name: TIMER2_PHASE_DIRECTION + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: TIMER2_STATUS + addressOffset: 48 + size: 32 + fields: + - name: TIMER2_VALUE + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: TIMER2_DIRECTION + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: TIMER_SYNCI_CFG + addressOffset: 52 + size: 32 + fields: + - name: TIMER0_SYNCISEL + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: TIMER1_SYNCISEL + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: TIMER2_SYNCISEL + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: EXTERNAL_SYNCI0_INVERT + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: EXTERNAL_SYNCI1_INVERT + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: EXTERNAL_SYNCI2_INVERT + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: OPERATOR_TIMERSEL + addressOffset: 56 + size: 32 + fields: + - name: OPERATOR0_TIMERSEL + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: OPERATOR1_TIMERSEL + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: OPERATOR2_TIMERSEL + bitOffset: 4 + bitWidth: 2 + access: read-write + - register: + name: GEN0_STMP_CFG + addressOffset: 60 + size: 32 + fields: + - name: GEN0_A_UPMETHOD + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: GEN0_B_UPMETHOD + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: GEN0_A_SHDW_FULL + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: GEN0_B_SHDW_FULL + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: GEN0_TSTMP_A + addressOffset: 64 + size: 32 + fields: + - name: GEN0_A + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: GEN0_TSTMP_B + addressOffset: 68 + size: 32 + fields: + - name: GEN0_B + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: GEN0_CFG0 + addressOffset: 72 + size: 32 + fields: + - name: GEN0_CFG_UPMETHOD + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: GEN0_T0_SEL + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: GEN0_T1_SEL + bitOffset: 7 + bitWidth: 3 + access: read-write + - register: + name: GEN0_FORCE + addressOffset: 76 + size: 32 + resetValue: 32 + fields: + - name: GEN0_CNTUFORCE_UPMETHOD + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: GEN0_A_CNTUFORCE_MODE + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: GEN0_B_CNTUFORCE_MODE + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: GEN0_A_NCIFORCE + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GEN0_A_NCIFORCE_MODE + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: GEN0_B_NCIFORCE + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: GEN0_B_NCIFORCE_MODE + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: GEN0_A + addressOffset: 80 + size: 32 + fields: + - name: UTEZ + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: GEN0_B + addressOffset: 84 + size: 32 + fields: + - name: UTEZ + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: DT0_CFG + addressOffset: 88 + size: 32 + resetValue: 98304 + fields: + - name: DT0_FED_UPMETHOD + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: DT0_RED_UPMETHOD + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: DT0_DEB_MODE + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DT0_A_OUTSWAP + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DT0_B_OUTSWAP + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DT0_RED_INSEL + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DT0_FED_INSEL + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DT0_RED_OUTINVERT + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DT0_FED_OUTINVERT + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DT0_A_OUTBYPASS + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DT0_B_OUTBYPASS + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DT0_CLK_SEL + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: DT0_FED_CFG + addressOffset: 92 + size: 32 + fields: + - name: DT0_FED + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: DT0_RED_CFG + addressOffset: 96 + size: 32 + fields: + - name: DT0_RED + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: CARRIER0_CFG + addressOffset: 100 + size: 32 + fields: + - name: CARRIER0_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CARRIER0_PRESCALE + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CARRIER0_DUTY + bitOffset: 5 + bitWidth: 3 + access: read-write + - name: CARRIER0_OSHTWTH + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: CARRIER0_OUT_INVERT + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CARRIER0_IN_INVERT + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: FH0_CFG0 + addressOffset: 104 + size: 32 + fields: + - name: FH0_SW_CBC + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FH0_F2_CBC + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FH0_F1_CBC + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FH0_F0_CBC + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FH0_SW_OST + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FH0_F2_OST + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FH0_F1_OST + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FH0_F0_OST + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FH0_A_CBC_D + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: FH0_A_CBC_U + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: FH0_A_OST_D + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: FH0_A_OST_U + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: FH0_B_CBC_D + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: FH0_B_CBC_U + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: FH0_B_OST_D + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: FH0_B_OST_U + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: FH0_CFG1 + addressOffset: 108 + size: 32 + fields: + - name: FH0_CLR_OST + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FH0_CBCPULSE + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: FH0_FORCE_CBC + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FH0_FORCE_OST + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: FH0_STATUS + addressOffset: 112 + size: 32 + fields: + - name: FH0_CBC_ON + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: FH0_OST_ON + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: GEN1_STMP_CFG + addressOffset: 116 + size: 32 + fields: + - name: GEN1_A_UPMETHOD + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: GEN1_B_UPMETHOD + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: GEN1_A_SHDW_FULL + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: GEN1_B_SHDW_FULL + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: GEN1_TSTMP_A + addressOffset: 120 + size: 32 + fields: + - name: GEN1_A + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: GEN1_TSTMP_B + addressOffset: 124 + size: 32 + fields: + - name: GEN1_B + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: GEN1_CFG0 + addressOffset: 128 + size: 32 + fields: + - name: GEN1_CFG_UPMETHOD + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: GEN1_T0_SEL + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: GEN1_T1_SEL + bitOffset: 7 + bitWidth: 3 + access: read-write + - register: + name: GEN1_FORCE + addressOffset: 132 + size: 32 + resetValue: 32 + fields: + - name: GEN1_CNTUFORCE_UPMETHOD + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: GEN1_A_CNTUFORCE_MODE + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: GEN1_B_CNTUFORCE_MODE + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: GEN1_A_NCIFORCE + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GEN1_A_NCIFORCE_MODE + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: GEN1_B_NCIFORCE + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: GEN1_B_NCIFORCE_MODE + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: GEN1_A + addressOffset: 136 + size: 32 + fields: + - name: UTEZ + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: GEN1_B + addressOffset: 140 + size: 32 + fields: + - name: UTEZ + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: DT1_CFG + addressOffset: 144 + size: 32 + resetValue: 98304 + fields: + - name: DT1_FED_UPMETHOD + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: DT1_RED_UPMETHOD + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: DT1_DEB_MODE + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DT1_A_OUTSWAP + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DT1_B_OUTSWAP + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DT1_RED_INSEL + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DT1_FED_INSEL + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DT1_RED_OUTINVERT + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DT1_FED_OUTINVERT + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DT1_A_OUTBYPASS + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DT1_B_OUTBYPASS + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DT1_CLK_SEL + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: DT1_FED_CFG + addressOffset: 148 + size: 32 + fields: + - name: DT1_FED + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: DT1_RED_CFG + addressOffset: 152 + size: 32 + fields: + - name: DT1_RED + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: CARRIER1_CFG + addressOffset: 156 + size: 32 + fields: + - name: CARRIER1_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CARRIER1_PRESCALE + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CARRIER1_DUTY + bitOffset: 5 + bitWidth: 3 + access: read-write + - name: CARRIER1_OSHTWTH + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: CARRIER1_OUT_INVERT + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CARRIER1_IN_INVERT + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: FH1_CFG0 + addressOffset: 160 + size: 32 + fields: + - name: FH1_SW_CBC + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FH1_F2_CBC + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FH1_F1_CBC + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FH1_F0_CBC + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FH1_SW_OST + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FH1_F2_OST + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FH1_F1_OST + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FH1_F0_OST + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FH1_A_CBC_D + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: FH1_A_CBC_U + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: FH1_A_OST_D + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: FH1_A_OST_U + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: FH1_B_CBC_D + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: FH1_B_CBC_U + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: FH1_B_OST_D + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: FH1_B_OST_U + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: FH1_CFG1 + addressOffset: 164 + size: 32 + fields: + - name: FH1_CLR_OST + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FH1_CBCPULSE + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: FH1_FORCE_CBC + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FH1_FORCE_OST + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: FH1_STATUS + addressOffset: 168 + size: 32 + fields: + - name: FH1_CBC_ON + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: FH1_OST_ON + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: GEN2_STMP_CFG + addressOffset: 172 + size: 32 + fields: + - name: GEN2_A_UPMETHOD + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: GEN2_B_UPMETHOD + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: GEN2_A_SHDW_FULL + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: GEN2_B_SHDW_FULL + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: GEN2_TSTMP_A + addressOffset: 176 + size: 32 + fields: + - name: GEN2_A + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: GEN2_TSTMP_B + addressOffset: 180 + size: 32 + fields: + - name: GEN2_B + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: GEN2_CFG0 + addressOffset: 184 + size: 32 + fields: + - name: GEN2_CFG_UPMETHOD + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: GEN2_T0_SEL + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: GEN2_T1_SEL + bitOffset: 7 + bitWidth: 3 + access: read-write + - register: + name: GEN2_FORCE + addressOffset: 188 + size: 32 + resetValue: 32 + fields: + - name: GEN2_CNTUFORCE_UPMETHOD + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: GEN2_A_CNTUFORCE_MODE + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: GEN2_B_CNTUFORCE_MODE + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: GEN2_A_NCIFORCE + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GEN2_A_NCIFORCE_MODE + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: GEN2_B_NCIFORCE + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: GEN2_B_NCIFORCE_MODE + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: GEN2_A + addressOffset: 192 + size: 32 + fields: + - name: UTEZ + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: GEN2_B + addressOffset: 196 + size: 32 + fields: + - name: UTEZ + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: DT2_CFG + addressOffset: 200 + size: 32 + resetValue: 98304 + fields: + - name: DT2_FED_UPMETHOD + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: DT2_RED_UPMETHOD + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: DT2_DEB_MODE + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DT2_A_OUTSWAP + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DT2_B_OUTSWAP + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DT2_RED_INSEL + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DT2_FED_INSEL + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DT2_RED_OUTINVERT + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DT2_FED_OUTINVERT + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DT2_A_OUTBYPASS + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DT2_B_OUTBYPASS + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DT2_CLK_SEL + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: DT2_FED_CFG + addressOffset: 204 + size: 32 + fields: + - name: DT2_FED + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: DT2_RED_CFG + addressOffset: 208 + size: 32 + fields: + - name: DT2_RED + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: CARRIER2_CFG + addressOffset: 212 + size: 32 + fields: + - name: CARRIER2_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CARRIER2_PRESCALE + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CARRIER2_DUTY + bitOffset: 5 + bitWidth: 3 + access: read-write + - name: CARRIER2_OSHTWTH + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: CARRIER2_OUT_INVERT + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CARRIER2_IN_INVERT + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: FH2_CFG0 + addressOffset: 216 + size: 32 + fields: + - name: FH2_SW_CBC + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FH2_F2_CBC + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FH2_F1_CBC + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FH2_F0_CBC + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FH2_SW_OST + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FH2_F2_OST + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FH2_F1_OST + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FH2_F0_OST + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FH2_A_CBC_D + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: FH2_A_CBC_U + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: FH2_A_OST_D + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: FH2_A_OST_U + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: FH2_B_CBC_D + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: FH2_B_CBC_U + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: FH2_B_OST_D + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: FH2_B_OST_U + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: FH2_CFG1 + addressOffset: 220 + size: 32 + fields: + - name: FH2_CLR_OST + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FH2_CBCPULSE + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: FH2_FORCE_CBC + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FH2_FORCE_OST + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: FH2_STATUS + addressOffset: 224 + size: 32 + fields: + - name: FH2_CBC_ON + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: FH2_OST_ON + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: FAULT_DETECT + addressOffset: 228 + size: 32 + fields: + - name: F0_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: F1_EN + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: F2_EN + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: F0_POLE + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: F1_POLE + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: F2_POLE + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: EVENT_F0 + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: EVENT_F1 + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: EVENT_F2 + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: CAP_TIMER_CFG + addressOffset: 232 + size: 32 + fields: + - name: CAP_TIMER_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CAP_SYNCI_EN + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CAP_SYNCI_SEL + bitOffset: 2 + bitWidth: 3 + access: read-write + - name: CAP_SYNC_SW + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: CAP_TIMER_PHASE + addressOffset: 236 + size: 32 + fields: + - name: CAP_TIMER_PHASE + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CAP_CH0_CFG + addressOffset: 240 + size: 32 + fields: + - name: CAP0_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CAP0_MODE + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: CAP0_PRESCALE + bitOffset: 3 + bitWidth: 8 + access: read-write + - name: CAP0_IN_INVERT + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CAP0_SW + bitOffset: 12 + bitWidth: 1 + access: write-only + - register: + name: CAP_CH1_CFG + addressOffset: 244 + size: 32 + fields: + - name: CAP1_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CAP1_MODE + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: CAP1_PRESCALE + bitOffset: 3 + bitWidth: 8 + access: read-write + - name: CAP1_IN_INVERT + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CAP1_SW + bitOffset: 12 + bitWidth: 1 + access: write-only + - register: + name: CAP_CH2_CFG + addressOffset: 248 + size: 32 + fields: + - name: CAP2_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CAP2_MODE + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: CAP2_PRESCALE + bitOffset: 3 + bitWidth: 8 + access: read-write + - name: CAP2_IN_INVERT + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CAP2_SW + bitOffset: 12 + bitWidth: 1 + access: write-only + - register: + name: CAP_CH0 + addressOffset: 252 + size: 32 + fields: + - name: CAP0_VALUE + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CAP_CH1 + addressOffset: 256 + size: 32 + fields: + - name: CAP1_VALUE + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CAP_CH2 + addressOffset: 260 + size: 32 + fields: + - name: CAP2_VALUE + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CAP_STATUS + addressOffset: 264 + size: 32 + fields: + - name: CAP0_EDGE + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CAP1_EDGE + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CAP2_EDGE + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: UPDATE_CFG + addressOffset: 268 + size: 32 + resetValue: 85 + fields: + - name: GLOBAL_UP_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: GLOBAL_FORCE_UP + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OP0_UP_EN + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OP0_FORCE_UP + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OP1_UP_EN + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OP1_FORCE_UP + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OP2_UP_EN + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OP2_FORCE_UP + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: INT_ENA + addressOffset: 272 + size: 32 + fields: + - name: TIMER0_STOP_INT_ENA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMER1_STOP_INT_ENA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER2_STOP_INT_ENA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TIMER0_TEZ_INT_ENA + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TIMER1_TEZ_INT_ENA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TIMER2_TEZ_INT_ENA + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TIMER0_TEP_INT_ENA + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TIMER1_TEP_INT_ENA + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TIMER2_TEP_INT_ENA + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FAULT0_INT_ENA + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FAULT1_INT_ENA + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FAULT2_INT_ENA + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FAULT0_CLR_INT_ENA + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FAULT1_CLR_INT_ENA + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FAULT2_CLR_INT_ENA + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: OP0_TEA_INT_ENA + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: OP1_TEA_INT_ENA + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: OP2_TEA_INT_ENA + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: OP0_TEB_INT_ENA + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: OP1_TEB_INT_ENA + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: OP2_TEB_INT_ENA + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: FH0_CBC_INT_ENA + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: FH1_CBC_INT_ENA + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: FH2_CBC_INT_ENA + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: FH0_OST_INT_ENA + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: FH1_OST_INT_ENA + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: FH2_OST_INT_ENA + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CAP0_INT_ENA + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: CAP1_INT_ENA + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CAP2_INT_ENA + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + addressOffset: 276 + size: 32 + fields: + - name: TIMER0_STOP_INT_RAW + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TIMER1_STOP_INT_RAW + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TIMER2_STOP_INT_RAW + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TIMER0_TEZ_INT_RAW + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TIMER1_TEZ_INT_RAW + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TIMER2_TEZ_INT_RAW + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: TIMER0_TEP_INT_RAW + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TIMER1_TEP_INT_RAW + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIMER2_TEP_INT_RAW + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: FAULT0_INT_RAW + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: FAULT1_INT_RAW + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: FAULT2_INT_RAW + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: FAULT0_CLR_INT_RAW + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: FAULT1_CLR_INT_RAW + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: FAULT2_CLR_INT_RAW + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: OP0_TEA_INT_RAW + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: OP1_TEA_INT_RAW + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: OP2_TEA_INT_RAW + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: OP0_TEB_INT_RAW + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: OP1_TEB_INT_RAW + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: OP2_TEB_INT_RAW + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: FH0_CBC_INT_RAW + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: FH1_CBC_INT_RAW + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: FH2_CBC_INT_RAW + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: FH0_OST_INT_RAW + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: FH1_OST_INT_RAW + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: FH2_OST_INT_RAW + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: CAP0_INT_RAW + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: CAP1_INT_RAW + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: CAP2_INT_RAW + bitOffset: 29 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + addressOffset: 280 + size: 32 + fields: + - name: TIMER0_STOP_INT_ST + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TIMER1_STOP_INT_ST + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TIMER2_STOP_INT_ST + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TIMER0_TEZ_INT_ST + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TIMER1_TEZ_INT_ST + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TIMER2_TEZ_INT_ST + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: TIMER0_TEP_INT_ST + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TIMER1_TEP_INT_ST + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIMER2_TEP_INT_ST + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: FAULT0_INT_ST + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: FAULT1_INT_ST + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: FAULT2_INT_ST + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: FAULT0_CLR_INT_ST + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: FAULT1_CLR_INT_ST + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: FAULT2_CLR_INT_ST + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: OP0_TEA_INT_ST + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: OP1_TEA_INT_ST + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: OP2_TEA_INT_ST + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: OP0_TEB_INT_ST + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: OP1_TEB_INT_ST + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: OP2_TEB_INT_ST + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: FH0_CBC_INT_ST + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: FH1_CBC_INT_ST + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: FH2_CBC_INT_ST + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: FH0_OST_INT_ST + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: FH1_OST_INT_ST + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: FH2_OST_INT_ST + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: CAP0_INT_ST + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: CAP1_INT_ST + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: CAP2_INT_ST + bitOffset: 29 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + addressOffset: 284 + size: 32 + fields: + - name: TIMER0_STOP_INT_CLR + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TIMER1_STOP_INT_CLR + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TIMER2_STOP_INT_CLR + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TIMER0_TEZ_INT_CLR + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TIMER1_TEZ_INT_CLR + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: TIMER2_TEZ_INT_CLR + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TIMER0_TEP_INT_CLR + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TIMER1_TEP_INT_CLR + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: TIMER2_TEP_INT_CLR + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: FAULT0_INT_CLR + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: FAULT1_INT_CLR + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: FAULT2_INT_CLR + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: FAULT0_CLR_INT_CLR + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: FAULT1_CLR_INT_CLR + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: FAULT2_CLR_INT_CLR + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: OP0_TEA_INT_CLR + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: OP1_TEA_INT_CLR + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: OP2_TEA_INT_CLR + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: OP0_TEB_INT_CLR + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: OP1_TEB_INT_CLR + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: OP2_TEB_INT_CLR + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: FH0_CBC_INT_CLR + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: FH1_CBC_INT_CLR + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: FH2_CBC_INT_CLR + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: FH0_OST_INT_CLR + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: FH1_OST_INT_CLR + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: FH2_OST_INT_CLR + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: CAP0_INT_CLR + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: CAP1_INT_CLR + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: CAP2_INT_CLR + bitOffset: 29 + bitWidth: 1 + access: write-only + - register: + name: CLK + addressOffset: 288 + size: 32 + fields: + - name: EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: VERSION + addressOffset: 292 + size: 32 + resetValue: 34632240 + fields: + - name: DATE + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: MCPWM1 + description: Motor Control Pulse-Width Modulation 1 + baseAddress: 1073135616 + derivedFrom: MCPWM0 + - name: NRX + description: NRX Peripheral + groupName: NRX + baseAddress: 1073073152 + addressBlock: + - offset: 0 + size: 4 + usage: registers + registers: + - register: + name: NRXPD_CTRL + description: WiFi RX control register + addressOffset: 212 + size: 32 + fields: + - name: DEMAP_FORCE_PD + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DEMAP_FORCE_PU + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: VIT_FORCE_PD + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: VIT_FORCE_PU + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_ROT_FORCE_PD + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_ROT_FORCE_PU + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CHAN_EST_FORCE_PD + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CHAN_EST_FORCE_PU + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: PCNT + description: Pulse Count Controller + groupName: PCNT + baseAddress: 1073049600 + addressBlock: + - offset: 0 + size: 184 + usage: registers + interrupt: + - name: PCNT + value: 48 + registers: + - register: + dim: 8 + dimIncrement: 12 + dimIndex: "0,1,2,3,4,5,6,7" + name: U%s_CONF0 + addressOffset: 0 + size: 32 + resetValue: 15376 + fields: + - name: FILTER_THRES + description: This register is used to filter pluse whose width is smaller than this value for unit0. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: FILTER_EN + description: This is the enable bit for filtering input signals for unit0. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: THR_ZERO_EN + description: "This is the enable bit for comparing unit0's count with 0 value." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: THR_H_LIM_EN + description: "This is the enable bit for comparing unit0's count with thr_h_lim value." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: THR_L_LIM_EN + description: "This is the enable bit for comparing unit0's count with thr_l_lim value." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: THR_THRES0_EN + description: "This is the enable bit for comparing unit0's count with thres0 value." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: THR_THRES1_EN + description: "This is the enable bit for comparing unit0's count with thres1 value ." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CH0_NEG_MODE + description: "This register is used to control the mode of channel0's input negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden" + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CH0_POS_MODE + description: "This register is used to control the mode of channel0's input posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden" + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: CH0_HCTRL_MODE + description: "This register is used to control the mode of channel0's high control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden" + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: CH0_LCTRL_MODE + description: "This register is used to control the mode of channel0's low control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden" + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CH1_NEG_MODE + description: "This register is used to control the mode of channel1's input negedge signal for unit0. 2'd1: increase at the negedge of input signal 2'd2:decrease at the negedge of input signal others:forbidden" + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CH1_POS_MODE + description: "This register is used to control the mode of channel1's input posedge signal for unit0. 2'd1: increase at the posedge of input signal 2'd2:decrease at the posedge of input signal others:forbidden" + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CH1_HCTRL_MODE + description: "This register is used to control the mode of channel1's high control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden" + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: CH1_LCTRL_MODE + description: "This register is used to control the mode of channel1's low control signal for unit0. 2'd0:increase when control signal is low 2'd1: decrease when control signal is high others:forbidden" + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + dim: 8 + dimIncrement: 12 + dimIndex: "0,1,2,3,4,5,6,7" + name: U%s_CONF1 + addressOffset: 4 + size: 32 + fields: + - name: CNT_THRES0 + description: This register is used to configure thres0 value for unit0. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CNT_THRES1 + description: This register is used to configure thres1 value for unit0. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + dim: 8 + dimIncrement: 12 + dimIndex: "0,1,2,3,4,5,6,7" + name: U%s_CONF2 + addressOffset: 8 + size: 32 + fields: + - name: CNT_H_LIM + description: This register is used to configure thr_h_lim value for unit0. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CNT_L_LIM + description: This register is used to confiugre thr_l_lim value for unit0. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7" + name: U%s_CNT + addressOffset: 96 + size: 32 + fields: + - name: CNT + description: This register stores the current pulse count value for unit0. + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: INT_RAW + addressOffset: 128 + size: 32 + fields: + - name: CNT_THR_EVENT_U0 + description: This is the interrupt raw bit for channel0 event. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U1 + description: This is the interrupt raw bit for channel1 event. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U2 + description: This is the interrupt raw bit for channel2 event. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U3 + description: This is the interrupt raw bit for channel3 event. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U4 + description: This is the interrupt raw bit for channel4 event. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U5 + description: This is the interrupt raw bit for channel5 event. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U6 + description: This is the interrupt raw bit for channel6 event. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U7 + description: This is the interrupt raw bit for channel7 event. + bitOffset: 7 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + addressOffset: 132 + size: 32 + fields: + - name: CNT_THR_EVENT_U0 + description: This is the interrupt status bit for channel0 event. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U1 + description: This is the interrupt status bit for channel1 event. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U2 + description: This is the interrupt status bit for channel2 event. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U3 + description: This is the interrupt status bit for channel3 event. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U4 + description: This is the interrupt status bit for channel4 event. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U5 + description: This is the interrupt status bit for channel5 event. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U6 + description: This is the interrupt status bit for channel6 event. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U7 + description: This is the interrupt status bit for channel7 event. + bitOffset: 7 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + addressOffset: 136 + size: 32 + fields: + - name: CNT_THR_EVENT_U0 + description: This is the interrupt enable bit for channel0 event. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U1 + description: This is the interrupt enable bit for channel1 event. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U2 + description: This is the interrupt enable bit for channel2 event. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U3 + description: This is the interrupt enable bit for channel3 event. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U4 + description: This is the interrupt enable bit for channel4 event. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U5 + description: This is the interrupt enable bit for channel5 event. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U6 + description: This is the interrupt enable bit for channel6 event. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U7 + description: This is the interrupt enable bit for channel7 event. + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + addressOffset: 140 + size: 32 + fields: + - name: CNT_THR_EVENT_U0 + description: Set this bit to clear channel0 event interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CNT_THR_EVENT_U1 + description: Set this bit to clear channel1 event interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CNT_THR_EVENT_U2 + description: Set this bit to clear channel2 event interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CNT_THR_EVENT_U3 + description: Set this bit to clear channel3 event interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: CNT_THR_EVENT_U4 + description: Set this bit to clear channel4 event interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: CNT_THR_EVENT_U5 + description: Set this bit to clear channel5 event interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CNT_THR_EVENT_U6 + description: Set this bit to clear channel6 event interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: CNT_THR_EVENT_U7 + description: Set this bit to clear channel7 event interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - register: + dim: 8 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7" + name: U%s_STATUS + addressOffset: 144 + size: 32 + fields: + - name: CORE_STATUS_U0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - name: ZERO_MODE + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: THRES1 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: THRES0 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: L_LIM + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_LIM + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: ZERO + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: CTRL + addressOffset: 176 + size: 32 + resetValue: 21845 + fields: + - name: CNT_RST_U0 + description: "Set this bit to clear unit0's counter." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U0 + description: "Set this bit to pause unit0's counter." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CNT_RST_U1 + description: "Set this bit to clear unit1's counter." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U1 + description: "Set this bit to pause unit1's counter." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CNT_RST_U2 + description: "Set this bit to clear unit2's counter." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U2 + description: "Set this bit to pause unit2's counter." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CNT_RST_U3 + description: "Set this bit to clear unit3's counter." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U3 + description: "Set this bit to pause unit3's counter." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CNT_RST_U4 + description: "Set this bit to clear unit4's counter." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U4 + description: "Set this bit to pause unit4's counter." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CNT_RST_U5 + description: "Set this bit to clear unit5's counter." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U5 + description: "Set this bit to pause unit5's counter." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CNT_RST_U6 + description: "Set this bit to clear unit6's counter." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U6 + description: "Set this bit to pause unit6's counter." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: CNT_RST_U7 + description: "Set this bit to clear unit7's counter." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U7 + description: "Set this bit to pause unit7's counter." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CLK_EN + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: DATE + addressOffset: 252 + size: 32 + resetValue: 336733696 + fields: + - name: DATE + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: RMT + description: Remote Control + groupName: RMT + baseAddress: 1073045504 + addressBlock: + - offset: 0 + size: 248 + usage: registers + interrupt: + - name: RMT + value: 47 + registers: + - register: + dim: 8 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7" + name: CH%sDATA + addressOffset: 0 + size: 32 + - register: + dim: 8 + dimIncrement: 8 + dimIndex: "0,1,2,3,4,5,6,7" + name: CH%sCONF0 + addressOffset: 32 + size: 32 + resetValue: 823132162 + fields: + - name: DIV_CNT + description: "This register is used to configure the frequency divider's factor in channel0." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: IDLE_THRES + description: In receive mode when no edge is detected on the input signal for longer than reg_idle_thres_ch0 then the receive process is done. + bitOffset: 8 + bitWidth: 16 + access: read-write + - name: MEM_SIZE + description: This register is used to configure the the amount of memory blocks allocated to channel0. + bitOffset: 24 + bitWidth: 4 + access: read-write + - name: CARRIER_EN + description: This is the carrier modulation enable control bit for channel0. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CARRIER_OUT_LV + description: "This bit is used to configure the way carrier wave is modulated for channel0.1'b1:transmit on low output level 1'b0:transmit on high output level." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: MEM_PD + description: "This bit is used to reduce power consumed by mem. 1:mem is in low power state." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: This bit is used to control clock.when software config RMT internal registers it controls the register clock. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + dim: 8 + dimIncrement: 8 + dimIndex: "0,1,2,3,4,5,6,7" + name: CH%sCONF1 + addressOffset: 36 + size: 32 + resetValue: 3872 + fields: + - name: TX_START + description: Set this bit to start sending data for channel0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_EN + description: Set this bit to enbale receving data for channel0. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MEM_WR_RST + description: Set this bit to reset write ram address for channel0 by receiver access. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MEM_RD_RST + description: Set this bit to reset read ram address for channel0 by transmitter access. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: APB_MEM_RST + description: Set this bit to reset W/R ram address for channel0 by apb fifo access + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MEM_OWNER + description: "This is the mark of channel0's ram usage right.1'b1：receiver uses the ram 0：transmitter uses the ram" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TX_CONTI_MODE + description: Set this bit to continue sending from the first data to the last data in channel0 again and again. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_FILTER_EN + description: This is the receive filter enable bit for channel0. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RX_FILTER_THRES + description: in receive mode channel0 ignore input pulse when the pulse width is smaller then this value. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: REF_CNT_RST + description: This bit is used to reset divider in channel0. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: REF_ALWAYS_ON + description: "This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: IDLE_OUT_LV + description: "This bit configures the output signal's level for channel0 in IDLE state." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: IDLE_OUT_EN + description: This is the output enable control bit for channel0 in IDLE state. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7" + name: CH%sSTATUS + addressOffset: 96 + size: 32 + fields: + - name: STATUS + description: The status for channel0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - name: MEM_WADDR_EX + description: The current memory read address of channel0. + bitOffset: 0 + bitWidth: 10 + access: read-only + - name: MEM_RADDR_EX + description: The current memory write address of channel0. + bitOffset: 12 + bitWidth: 10 + access: read-only + - name: STATE + description: "The channel0 state machine status register.3'h0 : idle, 3'h1 : send, 3'h2 : read memory, 3'h3 : receive, 3'h4 : wait." + bitOffset: 24 + bitWidth: 3 + access: read-only + - name: MEM_OWNER_ERR + description: "When channel0 is configured for receive mode, this bit will turn to high level if rmt_mem_owner register is not set to 1." + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: MEM_FULL + description: The memory full status bit for channel0 turns to high level when mem_waddr_ex is greater than or equal to the configuration range. + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: MEM_EMPTY + description: "The memory empty status bit for channel0. in acyclic mode, this bit turns to high level when mem_raddr_ex is greater than or equal to the configured range." + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: APB_MEM_WR_ERR + description: The apb write memory status bit for channel0 turns to high level when the apb write address exceeds the configuration range. + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: APB_MEM_RD_ERR + description: The apb read memory status bit for channel0 turns to high level when the apb read address exceeds the configuration range. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + dim: 8 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7" + name: CH%sADDR + addressOffset: 128 + size: 32 + fields: + - name: APB_MEM_ADDR + description: The ram relative address in channel0 by apb fifo access + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INT_RAW + addressOffset: 160 + size: 32 + fields: + - dim: 8 + dimIncrement: 3 + dimIndex: "0,1,2,3,4,5,6,7" + name: CH%s_TX_END + description: The interrupt raw bit for channel %s turns to high level when the transmit process is done. + bitOffset: 0 + bitWidth: 1 + access: read-only + - dim: 8 + dimIncrement: 3 + dimIndex: "0,1,2,3,4,5,6,7" + name: CH%s_RX_END + description: The interrupt raw bit for channel %s turns to high level when the receive process is done. + bitOffset: 1 + bitWidth: 1 + access: read-only + - dim: 8 + dimIncrement: 3 + dimIndex: "0,1,2,3,4,5,6,7" + name: CH%s_ERR + description: The interrupt raw bit for channel %s turns to high level when channle %s detects some errors. + bitOffset: 2 + bitWidth: 1 + access: read-only + - dim: 8 + dimIncrement: 1 + dimIndex: "0,1,2,3,4,5,6,7" + name: CH%s_TX_THR_EVENT + description: The interrupt raw bit for channel %s turns to high level when transmitter in channle%s have send datas more than reg_rmt_tx_lim_ch%s after detecting this interrupt software can updata the old datas with new datas. + bitOffset: 24 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + addressOffset: 164 + size: 32 + fields: + - dim: 8 + dimIncrement: 3 + dimIndex: "0,1,2,3,4,5,6,7" + name: CH%s_TX_END + description: "The interrupt state bit for channel %s's mt_ch%s_tx_end_int_raw when mt_ch%s_tx_end_int_ena is set to %s." + bitOffset: 0 + bitWidth: 1 + access: read-only + - dim: 8 + dimIncrement: 3 + dimIndex: "0,1,2,3,4,5,6,7" + name: CH%s_RX_END + description: "The interrupt state bit for channel %s's rmt_ch%s_rx_end_int_raw when rmt_ch%s_rx_end_int_ena is set to %s." + bitOffset: 1 + bitWidth: 1 + access: read-only + - dim: 8 + dimIncrement: 3 + dimIndex: "0,1,2,3,4,5,6,7" + name: CH%s_ERR + description: "The interrupt state bit for channel %s's rmt_ch%s_err_int_raw when rmt_ch%s_err_int_ena is set to %s." + bitOffset: 2 + bitWidth: 1 + access: read-only + - dim: 8 + dimIncrement: 1 + dimIndex: "0,1,2,3,4,5,6,7" + name: CH%s_TX_THR_EVENT + description: "The interrupt state bit for channel %s's rmt_ch%s_tx_thr_event_int_raw when mt_ch%s_tx_thr_event_int_ena is set to 1." + bitOffset: 24 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + addressOffset: 168 + size: 32 + fields: + - dim: 8 + dimIncrement: 3 + dimIndex: "0,1,2,3,4,5,6,7" + name: CH%s_TX_END + description: Set this bit to enable rmt_ch%s_tx_end_int_st. + bitOffset: 0 + bitWidth: 1 + access: read-write + - dim: 8 + dimIncrement: 3 + dimIndex: "0,1,2,3,4,5,6,7" + name: CH%s_RX_END + description: Set this bit to enable rmt_ch%s_rx_end_int_st. + bitOffset: 1 + bitWidth: 1 + access: read-write + - dim: 8 + dimIncrement: 3 + dimIndex: "0,1,2,3,4,5,6,7" + name: CH%s_ERR + description: Set this bit to enable rmt_ch%s_err_int_st. + bitOffset: 2 + bitWidth: 1 + access: read-write + - dim: 8 + dimIncrement: 1 + dimIndex: "0,1,2,3,4,5,6,7" + name: CH%s_TX_THR_EVENT + description: Set this bit to enable rmt_ch%s_tx_thr_event_int_st. + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + addressOffset: 172 + size: 32 + fields: + - dim: 8 + dimIncrement: 3 + dimIndex: "0,1,2,3,4,5,6,7" + name: CH%s_TX_END + description: Set this bit to clear the rmt_ch%s_rx_end_int_raw.. + bitOffset: 0 + bitWidth: 1 + access: write-only + - dim: 8 + dimIncrement: 3 + dimIndex: "0,1,2,3,4,5,6,7" + name: CH%s_RX_END + description: Set this bit to clear the rmt_ch%s_tx_end_int_raw. + bitOffset: 1 + bitWidth: 1 + access: write-only + - dim: 8 + dimIncrement: 3 + dimIndex: "0,1,2,3,4,5,6,7" + name: CH%s_ERR + description: Set this bit to clear the rmt_ch%s_err_int_raw. + bitOffset: 2 + bitWidth: 1 + access: write-only + - dim: 8 + dimIncrement: 1 + dimIndex: "0,1,2,3,4,5,6,7" + name: CH%s_TX_THR_EVENT + description: Set this bit to clear the rmt_ch%s_tx_thr_event_int_raw interrupt. + bitOffset: 24 + bitWidth: 1 + access: write-only + - register: + dim: 8 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7" + name: CH%sCARRIER_DUTY + addressOffset: 176 + size: 32 + resetValue: 4194368 + fields: + - name: CARRIER_LOW + description: "This register is used to configure carrier wave's low level value for channel0." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CARRIER_HIGH + description: "This register is used to configure carrier wave's high level value for channel0." + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7" + name: CH%s_TX_LIM + addressOffset: 208 + size: 32 + resetValue: 128 + fields: + - name: TX_LIM + description: When channel0 sends more than reg_rmt_tx_lim_ch0 datas then channel0 produce the relative interrupt. + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: APB_CONF + addressOffset: 240 + size: 32 + fields: + - name: APB_FIFO_MASK + description: Set this bit to disable apb fifo access + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_TX_WRAP_EN + description: "when datas need to be send is more than channel's mem can store then set this bit to enable reusage of mem this bit is used together with reg_rmt_tx_lim_chn." + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: DATE + addressOffset: 252 + size: 32 + resetValue: 369239552 + fields: + - name: DATE + description: This is the version register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: RNG + description: Hardware Random Number Generator + groupName: RNG + baseAddress: 1610829824 + addressBlock: + - offset: 0 + size: 4 + usage: registers + registers: + - register: + name: DATA + description: Random number data + addressOffset: 324 + size: 32 + access: read-only + - name: RSA + description: RSA (Rivest Shamir Adleman) Accelerator + groupName: RSA + baseAddress: 1072701440 + addressBlock: + - offset: 0 + size: 28 + usage: registers + interrupt: + - name: RSA + value: 51 + registers: + - register: + name: M_PRIME + addressOffset: 2048 + size: 32 + fields: + - name: M_PRIME + description: This register contains M’. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: MODEXP_MODE + addressOffset: 2052 + size: 32 + fields: + - name: MODEXP_MODE + description: This register contains the mode of modular exponentiation. + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: MODEXP_START + addressOffset: 2056 + size: 32 + fields: + - name: MODEXP_START + description: Write 1 to start modular exponentiation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: MULT_MODE + addressOffset: 2060 + size: 32 + fields: + - name: MULT_MODE + description: This register contains the mode of modular multiplication and multiplication. + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: MULT_START + addressOffset: 2064 + size: 32 + fields: + - name: MULT_START + description: Write 1 to start modular multiplication or multiplication. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: INTERRUPT + addressOffset: 2068 + size: 32 + fields: + - name: INTERRUPT + description: RSA interrupt status register. Will read 1 once an operation has completed. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CLEAN + addressOffset: 2072 + size: 32 + fields: + - name: CLEAN + description: This bit will read 1 once the memory initialization is completed. + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + dim: 32 + dimIncrement: 4 + name: "M_MEM[%s]" + description: Represents M + addressOffset: 0 + size: 32 + access: read-write + - register: + dim: 32 + dimIncrement: 4 + name: "Z_MEM[%s]" + description: Represents Z + addressOffset: 512 + size: 32 + access: read-write + - register: + dim: 32 + dimIncrement: 4 + name: "Y_MEM[%s]" + description: Represents Y + addressOffset: 1024 + size: 32 + access: read-write + - register: + dim: 32 + dimIncrement: 4 + name: "X_MEM[%s]" + description: Represents X + addressOffset: 1536 + size: 32 + access: read-write + - name: RTC_CNTL + description: Real-Time Clock Control + groupName: RTC_CNTL + baseAddress: 1072988160 + addressBlock: + - offset: 0 + size: 220 + usage: registers + interrupt: + - name: RTC_CORE + value: 46 + registers: + - register: + name: OPTIONS0 + addressOffset: 0 + size: 32 + resetValue: 474554368 + fields: + - name: SW_STALL_APPCPU_C0 + description: "{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SW_STALL_PROCPU_C0 + description: "{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: SW_APPCPU_RST + description: APP CPU SW reset + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SW_PROCPU_RST + description: PRO CPU SW reset + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: BB_I2C_FORCE_PD + description: BB_I2C force power down + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BB_I2C_FORCE_PU + description: BB_I2C force power up + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: BBPLL_I2C_FORCE_PD + description: BB_PLL _I2C force power down + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BBPLL_I2C_FORCE_PU + description: BB_PLL_I2C force power up + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: BBPLL_FORCE_PD + description: BB_PLL force power down + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: BBPLL_FORCE_PU + description: BB_PLL force power up + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: XTL_FORCE_PD + description: crystall force power down + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: XTL_FORCE_PU + description: crystall force power up + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: BIAS_SLEEP_FOLW_8M + description: BIAS_SLEEP follow CK8M + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: BIAS_FORCE_SLEEP + description: BIAS_SLEEP force sleep + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: BIAS_FORCE_NOSLEEP + description: BIAS_SLEEP force no sleep + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: BIAS_I2C_FOLW_8M + description: BIAS_I2C follow CK8M + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: BIAS_I2C_FORCE_PD + description: BIAS_I2C force power down + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: BIAS_I2C_FORCE_PU + description: BIAS_I2C force power up + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: BIAS_CORE_FOLW_8M + description: BIAS_CORE follow CK8M + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: BIAS_CORE_FORCE_PD + description: BIAS_CORE force power down + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: BIAS_CORE_FORCE_PU + description: BIAS_CORE force power up + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: XTL_FORCE_ISO + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: PLL_FORCE_ISO + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ANALOG_FORCE_ISO + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: XTL_FORCE_NOISO + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: PLL_FORCE_NOISO + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: ANALOG_FORCE_NOISO + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_RST + description: digital wrap force reset in deep sleep + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_NORST + description: digital core force no reset in deep sleep + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SW_SYS_RST + description: SW system reset + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SLP_TIMER0 + addressOffset: 4 + size: 32 + fields: + - name: SLP_VAL_LO + description: RTC sleep timer low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SLP_TIMER1 + addressOffset: 8 + size: 32 + fields: + - name: SLP_VAL_HI + description: RTC sleep timer high 16 bits + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MAIN_TIMER_ALARM_EN + description: timer alarm enable bit + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: TIME_UPDATE + addressOffset: 12 + size: 32 + fields: + - name: TIME_VALID + description: To indicate the register is updated + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: TIME_UPDATE + description: "Set 1: to update register with RTC timer" + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: TIME0 + addressOffset: 16 + size: 32 + fields: + - name: TIME_LO + description: RTC timer low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: TIME1 + addressOffset: 20 + size: 32 + fields: + - name: TIME_HI + description: RTC timer high 16 bits + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: STATE0 + addressOffset: 24 + size: 32 + resetValue: 3145728 + fields: + - name: TOUCH_WAKEUP_FORCE_EN + description: touch controller force wake up + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: ULP_CP_WAKEUP_FORCE_EN + description: ULP-coprocessor force wake up + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: APB2RTC_BRIDGE_SEL + description: "1: APB to RTC using bridge 0: APB to RTC using sync" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TOUCH_SLP_TIMER_EN + description: touch timer enable bit + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: ULP_CP_SLP_TIMER_EN + description: ULP-coprocessor timer enable bit + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SDIO_ACTIVE_IND + description: SDIO active indication + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SLP_WAKEUP + description: sleep wakeup bit + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SLP_REJECT + description: sleep reject bit + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SLEEP_EN + description: sleep enable bit + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TIMER1 + addressOffset: 28 + size: 32 + resetValue: 672400387 + fields: + - name: CPU_STALL_EN + description: CPU stall enable bit + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CPU_STALL_WAIT + description: CPU stall wait cycles in fast_clk_rtc + bitOffset: 1 + bitWidth: 5 + access: read-write + - name: CK8M_WAIT + description: CK8M wait cycles in slow_clk_rtc + bitOffset: 6 + bitWidth: 8 + access: read-write + - name: XTL_BUF_WAIT + description: XTAL wait cycles in slow_clk_rtc + bitOffset: 14 + bitWidth: 10 + access: read-write + - name: PLL_BUF_WAIT + description: PLL wait cycles in slow_clk_rtc + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: TIMER2 + addressOffset: 32 + size: 32 + resetValue: 17301504 + fields: + - name: ULPCP_TOUCH_START_WAIT + description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work + bitOffset: 15 + bitWidth: 9 + access: read-write + - name: MIN_TIME_CK8M_OFF + description: minimal cycles in slow_clk_rtc for CK8M in power down state + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: TIMER3 + addressOffset: 36 + size: 32 + resetValue: 336988680 + fields: + - name: WIFI_WAIT_TIMER + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: WIFI_POWERUP_TIMER + bitOffset: 9 + bitWidth: 7 + access: read-write + - name: ROM_RAM_WAIT_TIMER + bitOffset: 16 + bitWidth: 9 + access: read-write + - name: ROM_RAM_POWERUP_TIMER + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: TIMER4 + addressOffset: 40 + size: 32 + resetValue: 270535176 + fields: + - name: WAIT_TIMER + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: POWERUP_TIMER + bitOffset: 9 + bitWidth: 7 + access: read-write + - name: DG_WRAP_WAIT_TIMER + bitOffset: 16 + bitWidth: 9 + access: read-write + - name: DG_WRAP_POWERUP_TIMER + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: TIMER5 + addressOffset: 44 + size: 32 + resetValue: 303333377 + fields: + - name: ULP_CP_SUBTIMER_PREDIV + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: MIN_SLP_VAL + description: minimal sleep cycles in slow_clk_rtc + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: RTCMEM_WAIT_TIMER + bitOffset: 16 + bitWidth: 9 + access: read-write + - name: RTCMEM_POWERUP_TIMER + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: ANA_CONF + addressOffset: 48 + size: 32 + resetValue: 8388608 + fields: + - name: PLLA_FORCE_PD + description: PLLA force power down + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: PLLA_FORCE_PU + description: PLLA force power up + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: BBPLL_CAL_SLP_START + description: start BBPLL calibration during sleep + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PVTMON_PU + description: "1: PVTMON power up otherwise power down" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TXRF_I2C_PU + description: "1: TXRF_I2C power up otherwise power down" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RFRX_PBUS_PU + description: "1: RFRX_PBUS power up otherwise power down" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CKGEN_I2C_PU + description: "1: CKGEN_I2C power up otherwise power down" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: PLL_I2C_PU + description: "1: PLL_I2C power up otherwise power down" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RESET_STATE + addressOffset: 52 + size: 32 + resetValue: 12288 + fields: + - name: RESET_CAUSE_PROCPU + description: reset cause of PRO CPU + bitOffset: 0 + bitWidth: 6 + access: read-only + - name: RESET_CAUSE_APPCPU + description: reset cause of APP CPU + bitOffset: 6 + bitWidth: 6 + access: read-only + - name: APPCPU_STAT_VECTOR_SEL + description: APP CPU state vector sel + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PROCPU_STAT_VECTOR_SEL + description: PRO CPU state vector sel + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: WAKEUP_STATE + addressOffset: 56 + size: 32 + resetValue: 24576 + fields: + - name: WAKEUP_CAUSE + description: wakeup cause + bitOffset: 0 + bitWidth: 11 + access: read-only + - name: WAKEUP_ENA + description: wakeup enable bitmap + bitOffset: 11 + bitWidth: 11 + access: read-write + - name: GPIO_WAKEUP_FILTER + description: enable filter for gpio wakeup event + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: INT_ENA + addressOffset: 60 + size: 32 + fields: + - name: SLP_WAKEUP_INT_ENA + description: enable sleep wakeup interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_REJECT_INT_ENA + description: enable sleep reject interrupt + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SDIO_IDLE_INT_ENA + description: enable SDIO idle interrupt + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: WDT_INT_ENA + description: enable RTC WDT interrupt + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TIME_VALID_INT_ENA + description: enable RTC time valid interrupt + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ULP_CP_INT_ENA + description: enable ULP-coprocessor interrupt + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TOUCH_INT_ENA + description: enable touch interrupt + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_INT_ENA + description: enable brown out interrupt + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: MAIN_TIMER_INT_ENA + description: enable RTC main timer interrupt + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + addressOffset: 64 + size: 32 + fields: + - name: SLP_WAKEUP_INT_RAW + description: sleep wakeup interrupt raw + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SLP_REJECT_INT_RAW + description: sleep reject interrupt raw + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SDIO_IDLE_INT_RAW + description: SDIO idle interrupt raw + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: WDT_INT_RAW + description: RTC WDT interrupt raw + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TIME_VALID_INT_RAW + description: RTC time valid interrupt raw + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ULP_CP_INT_RAW + description: ULP-coprocessor interrupt raw + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: TOUCH_INT_RAW + description: touch interrupt raw + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BROWN_OUT_INT_RAW + description: brown out interrupt raw + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: MAIN_TIMER_INT_RAW + description: RTC main timer interrupt raw + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + addressOffset: 68 + size: 32 + fields: + - name: SLP_WAKEUP_INT_ST + description: sleep wakeup interrupt state + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SLP_REJECT_INT_ST + description: sleep reject interrupt state + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SDIO_IDLE_INT_ST + description: SDIO idle interrupt state + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: WDT_INT_ST + description: RTC WDT interrupt state + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TIME_VALID_INT_ST + description: RTC time valid interrupt state + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SAR_INT_ST + description: ULP-coprocessor interrupt state + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: TOUCH_INT_ST + description: touch interrupt state + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BROWN_OUT_INT_ST + description: brown out interrupt state + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: MAIN_TIMER_INT_ST + description: RTC main timer interrupt state + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + addressOffset: 72 + size: 32 + fields: + - name: SLP_WAKEUP_INT_CLR + description: Clear sleep wakeup interrupt state + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SLP_REJECT_INT_CLR + description: Clear sleep reject interrupt state + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SDIO_IDLE_INT_CLR + description: Clear SDIO idle interrupt state + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: WDT_INT_CLR + description: Clear RTC WDT interrupt state + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TIME_VALID_INT_CLR + description: Clear RTC time valid interrupt state + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SAR_INT_CLR + description: Clear ULP-coprocessor interrupt state + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TOUCH_INT_CLR + description: Clear touch interrupt state + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: BROWN_OUT_INT_CLR + description: Clear brown out interrupt state + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: MAIN_TIMER_INT_CLR + description: Clear RTC main timer interrupt state + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: STORE0 + addressOffset: 76 + size: 32 + fields: + - name: SCRATCH0 + description: 32-bit general purpose retention register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE1 + addressOffset: 80 + size: 32 + fields: + - name: SCRATCH1 + description: 32-bit general purpose retention register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE2 + addressOffset: 84 + size: 32 + fields: + - name: SCRATCH2 + description: 32-bit general purpose retention register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE3 + addressOffset: 88 + size: 32 + fields: + - name: SCRATCH3 + description: 32-bit general purpose retention register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: EXT_XTL_CONF + addressOffset: 92 + size: 32 + fields: + - name: XTL_EXT_CTR_LV + description: "0: power down XTAL at high level 1: power down XTAL at low level" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: XTL_EXT_CTR_EN + description: enable control XTAL by external pads + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EXT_WAKEUP_CONF + addressOffset: 96 + size: 32 + fields: + - name: EXT_WAKEUP0_LV + description: "0: external wakeup at low level 1: external wakeup at high level" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: EXT_WAKEUP1_LV + description: "0: external wakeup at low level 1: external wakeup at high level" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SLP_REJECT_CONF + addressOffset: 100 + size: 32 + fields: + - name: GPIO_REJECT_EN + description: enable GPIO reject + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SDIO_REJECT_EN + description: enable SDIO reject + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LIGHT_SLP_REJECT_EN + description: enable reject for light sleep + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: DEEP_SLP_REJECT_EN + description: enable reject for deep sleep + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: REJECT_CAUSE + description: sleep reject cause + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: CPU_PERIOD_CONF + addressOffset: 104 + size: 32 + fields: + - name: CPUSEL_CONF + description: CPU sel option + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CPUPERIOD_SEL + description: CPU period sel + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: SDIO_ACT_CONF + addressOffset: 108 + size: 32 + fields: + - name: SDIO_ACT_DNUM + bitOffset: 22 + bitWidth: 10 + access: read-write + - register: + name: CLK_CONF + addressOffset: 112 + size: 32 + resetValue: 8720 + fields: + - name: CK8M_DIV + description: "CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024." + bitOffset: 4 + bitWidth: 2 + access: read-write + enumeratedValues: + - name: CK8M_DIV + usage: read-write + values: + - name: DIV128 + description: DIV128 + value: 0 + - name: DIV256 + description: DIV256 + value: 1 + - name: DIV512 + description: DIV512 + value: 2 + - name: DIV1024 + description: DIV1024 + value: 3 + - name: ENB_CK8M + description: disable CK8M and CK8M_D256_OUT + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: ENB_CK8M_DIV + description: "1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256" + bitOffset: 7 + bitWidth: 1 + access: read-write + enumeratedValues: + - name: ENB_CK8M_DIV + usage: read-write + values: + - name: CK8M_DIV_256 + description: CK8M_DIV_256 + value: 0 + - name: CK8M + description: CK8M + value: 1 + - name: DIG_XTAL32K_EN + description: enable CK_XTAL_32K for digital core (no relationship with RTC core) + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DIG_CLK8M_D256_EN + description: enable CK8M_D256_OUT for digital core (no relationship with RTC core) + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DIG_CLK8M_EN + description: enable CK8M for digital core (no relationship with RTC core) + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CK8M_DFREQ_FORCE + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CK8M_DIV_SEL + description: divider = reg_ck8m_div_sel + 1 + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: XTAL_FORCE_NOGATING + description: XTAL force no gating during sleep + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CK8M_FORCE_NOGATING + description: CK8M force no gating during sleep + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CK8M_DFREQ + description: CK8M_DFREQ + bitOffset: 17 + bitWidth: 8 + access: read-write + - name: CK8M_FORCE_PD + description: CK8M force power down + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: CK8M_FORCE_PU + description: CK8M force power up + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SOC_CLK_SEL + description: "SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL" + bitOffset: 27 + bitWidth: 2 + access: read-write + enumeratedValues: + - name: SOC_CLK_SEL + usage: read-write + values: + - name: XTAL + description: XTAL + value: 0 + - name: PLL + description: PLL + value: 1 + - name: CK8M + description: CK8M + value: 2 + - name: APLL + description: APLL + value: 3 + - name: FAST_CLK_RTC_SEL + description: "fast_clk_rtc sel. 0: XTAL div 4 1: CK8M" + bitOffset: 29 + bitWidth: 1 + access: read-write + enumeratedValues: + - name: FAST_CLK_RTC_SEL + usage: read-write + values: + - name: XTAL_DIV_4 + description: XTAL_DIV_4 + value: 0 + - name: CK8M + description: CK8M + value: 1 + - name: ANA_CLK_RTC_SEL + description: "slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT" + bitOffset: 30 + bitWidth: 2 + access: read-write + enumeratedValues: + - name: ANA_CLK_RTC_SEL + usage: read-write + values: + - name: SLOW_CK + description: SLOW_CK + value: 0 + - name: CK_XTAL_32K + description: CK_XTAL_32K + value: 1 + - name: CK8M_D256_OUT + description: CK8M_D256_OUT + value: 2 + - register: + name: SDIO_CONF + addressOffset: 116 + size: 32 + resetValue: 44040192 + fields: + - name: SDIO_PD_EN + description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SDIO_FORCE + description: "1: use SW option to control SDIO_REG 0: use state machine" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SDIO_TIEH + description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1 + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: REG1P8_READY + description: read only register for REG1P8_READY + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: DREFL_SDIO + description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1 + bitOffset: 25 + bitWidth: 2 + access: read-write + - name: DREFM_SDIO + description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1 + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: DREFH_SDIO + description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1 + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: XPD_SDIO + description: SW option for XPD_SDIO_REG. Only active when reg_sdio_force = 1 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: BIAS_CONF + addressOffset: 120 + size: 32 + fields: + - name: DBG_ATTEN + description: DBG_ATTEN + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: ENB_SCK_XTAL + description: ENB_SCK_XTAL + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: INC_HEARTBEAT_REFRESH + description: INC_HEARTBEAT_REFRESH + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: DEC_HEARTBEAT_PERIOD + description: DEC_HEARTBEAT_PERIOD + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: INC_HEARTBEAT_PERIOD + description: INC_HEARTBEAT_PERIOD + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: DEC_HEARTBEAT_WIDTH + description: DEC_HEARTBEAT_WIDTH + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: RST_BIAS_I2C + description: RST_BIAS_I2C + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: REG + addressOffset: 124 + size: 32 + resetValue: 687875072 + fields: + - name: SCK_DCAP_FORCE + description: N/A + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DIG_DBIAS_SLP + description: DIG_REG_DBIAS during sleep + bitOffset: 8 + bitWidth: 3 + access: read-write + - name: DIG_DBIAS_WAK + description: DIG_REG_DBIAS during wakeup + bitOffset: 11 + bitWidth: 3 + access: read-write + - name: SCK_DCAP + description: SCK_DCAP + bitOffset: 14 + bitWidth: 8 + access: read-write + - name: DBIAS_SLP + description: RTC_DBIAS during sleep + bitOffset: 22 + bitWidth: 3 + access: read-write + - name: DBIAS_WAK + description: RTC_DBIAS during wakeup + bitOffset: 25 + bitWidth: 3 + access: read-write + - name: DBOOST_FORCE_PD + description: RTC_DBOOST force power down + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DBOOST_FORCE_PU + description: RTC_DBOOST force power up + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: FORCE_PD + description: RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower ) + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: FORCE_PU + description: RTC_REG force power up + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: PWC + addressOffset: 128 + size: 32 + resetValue: 76069 + fields: + - name: FASTMEM_FORCE_NOISO + description: Fast RTC memory force no ISO + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FASTMEM_FORCE_ISO + description: Fast RTC memory force ISO + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SLOWMEM_FORCE_NOISO + description: RTC memory force no ISO + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLOWMEM_FORCE_ISO + description: RTC memory force ISO + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FORCE_ISO + description: rtc_peri force ISO + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FORCE_NOISO + description: rtc_peri force no ISO + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FASTMEM_FOLW_CPU + description: "1: Fast RTC memory PD following CPU 0: fast RTC memory PD following RTC state machine" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FASTMEM_FORCE_LPD + description: Fast RTC memory force PD + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FASTMEM_FORCE_LPU + description: Fast RTC memory force no PD + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLOWMEM_FOLW_CPU + description: "1: RTC memory PD following CPU 0: RTC memory PD following RTC state machine" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLOWMEM_FORCE_LPD + description: RTC memory force PD + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLOWMEM_FORCE_LPU + description: RTC memory force no PD + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FASTMEM_FORCE_PD + description: Fast RTC memory force power down + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FASTMEM_FORCE_PU + description: Fast RTC memory force power up + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FASTMEM_PD_EN + description: enable power down fast RTC memory in sleep + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLOWMEM_FORCE_PD + description: RTC memory force power down + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLOWMEM_FORCE_PU + description: RTC memory force power up + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SLOWMEM_PD_EN + description: enable power down RTC memory in sleep + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: FORCE_PD + description: rtc_peri force power down + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: FORCE_PU + description: rtc_peri force power up + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PD_EN + description: enable power down rtc_peri in sleep + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: DIG_PWC + addressOffset: 132 + size: 32 + resetValue: 1398096 + fields: + - name: LSLP_MEM_FORCE_PD + description: memories in digital core force PD in sleep + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: LSLP_MEM_FORCE_PU + description: memories in digital core force no PD in sleep + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ROM0_FORCE_PD + description: ROM force power down + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: ROM0_FORCE_PU + description: ROM force power up + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: INTER_RAM0_FORCE_PD + description: internal SRAM 0 force power down + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: INTER_RAM0_FORCE_PU + description: internal SRAM 0 force power up + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: INTER_RAM1_FORCE_PD + description: internal SRAM 1 force power down + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: INTER_RAM1_FORCE_PU + description: internal SRAM 1 force power up + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: INTER_RAM2_FORCE_PD + description: internal SRAM 2 force power down + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: INTER_RAM2_FORCE_PU + description: internal SRAM 2 force power up + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: INTER_RAM3_FORCE_PD + description: internal SRAM 3 force power down + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: INTER_RAM3_FORCE_PU + description: internal SRAM 3 force power up + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: INTER_RAM4_FORCE_PD + description: internal SRAM 4 force power down + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: INTER_RAM4_FORCE_PU + description: internal SRAM 4 force power up + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: WIFI_FORCE_PD + description: wifi force power down + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: WIFI_FORCE_PU + description: wifi force power up + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_PD + description: digital core force power down + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_PU + description: digital core force power up + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: ROM0_PD_EN + description: enable power down ROM in sleep + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: INTER_RAM0_PD_EN + description: enable power down internal SRAM 0 in sleep + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: INTER_RAM1_PD_EN + description: enable power down internal SRAM 1 in sleep + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: INTER_RAM2_PD_EN + description: enable power down internal SRAM 2 in sleep + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: INTER_RAM3_PD_EN + description: enable power down internal SRAM 3 in sleep + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: INTER_RAM4_PD_EN + description: enable power down internal SRAM 4 in sleep + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: WIFI_PD_EN + description: enable power down wifi in sleep + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DG_WRAP_PD_EN + description: enable power down digital core in sleep + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DIG_ISO + addressOffset: 136 + size: 32 + resetValue: 2863288320 + fields: + - name: FORCE_OFF + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FORCE_ON + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DG_PAD_AUTOHOLD + description: read only register to indicate digital pad auto-hold status + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: CLR_DG_PAD_AUTOHOLD + description: wtite only register to clear digital pad auto-hold + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: DG_PAD_AUTOHOLD_EN + description: digital pad enable auto-hold + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DG_PAD_FORCE_NOISO + description: digital pad force no ISO + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DG_PAD_FORCE_ISO + description: digital pad force ISO + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DG_PAD_FORCE_UNHOLD + description: digital pad force un-hold + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DG_PAD_FORCE_HOLD + description: digital pad force hold + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: ROM0_FORCE_ISO + description: ROM force ISO + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ROM0_FORCE_NOISO + description: ROM force no ISO + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: INTER_RAM0_FORCE_ISO + description: internal SRAM 0 force ISO + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: INTER_RAM0_FORCE_NOISO + description: internal SRAM 0 force no ISO + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: INTER_RAM1_FORCE_ISO + description: internal SRAM 1 force ISO + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: INTER_RAM1_FORCE_NOISO + description: internal SRAM 1 force no ISO + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: INTER_RAM2_FORCE_ISO + description: internal SRAM 2 force ISO + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: INTER_RAM2_FORCE_NOISO + description: internal SRAM 2 force no ISO + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: INTER_RAM3_FORCE_ISO + description: internal SRAM 3 force ISO + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: INTER_RAM3_FORCE_NOISO + description: internal SRAM 3 force no ISO + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: INTER_RAM4_FORCE_ISO + description: internal SRAM 4 force ISO + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: INTER_RAM4_FORCE_NOISO + description: internal SRAM 4 force no ISO + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: WIFI_FORCE_ISO + description: wifi force ISO + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: WIFI_FORCE_NOISO + description: wifi force no ISO + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_ISO + description: digital core force ISO + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_NOISO + description: digital core force no ISO + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: WDTCONFIG0 + addressOffset: 140 + size: 32 + resetValue: 19584 + fields: + - name: WDT_PAUSE_IN_SLP + description: pause WDT in sleep + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: WDT_APPCPU_RESET_EN + description: enable WDT reset APP CPU + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: WDT_PROCPU_RESET_EN + description: enable WDT reset PRO CPU + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: WDT_FLASHBOOT_MOD_EN + description: enable WDT in flash boot + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: WDT_SYS_RESET_LENGTH + description: system reset counter length + bitOffset: 11 + bitWidth: 3 + access: read-write + - name: WDT_CPU_RESET_LENGTH + description: CPU reset counter length + bitOffset: 14 + bitWidth: 3 + access: read-write + - name: WDT_LEVEL_INT_EN + description: N/A + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: WDT_EDGE_INT_EN + description: N/A + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: WDT_STG3 + description: "1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en" + bitOffset: 19 + bitWidth: 3 + access: read-write + - name: WDT_STG2 + description: "1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en" + bitOffset: 22 + bitWidth: 3 + access: read-write + - name: WDT_STG1 + description: "1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en" + bitOffset: 25 + bitWidth: 3 + access: read-write + - name: WDT_STG0 + description: "1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en" + bitOffset: 28 + bitWidth: 3 + access: read-write + - name: WDT_EN + description: enable RTC WDT + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: WDTCONFIG1 + addressOffset: 144 + size: 32 + resetValue: 128000 + fields: + - name: WDT_STG0_HOLD + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG2 + addressOffset: 148 + size: 32 + resetValue: 80000 + fields: + - name: WDT_STG1_HOLD + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG3 + addressOffset: 152 + size: 32 + resetValue: 4095 + fields: + - name: WDT_STG2_HOLD + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG4 + addressOffset: 156 + size: 32 + resetValue: 4095 + fields: + - name: WDT_STG3_HOLD + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTFEED + addressOffset: 160 + size: 32 + fields: + - name: WDT_FEED + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: WDTWPROTECT + addressOffset: 164 + size: 32 + resetValue: 1356348065 + fields: + - name: WDT_WKEY + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEST_MUX + addressOffset: 168 + size: 32 + fields: + - name: ENT_RTC + description: ENT_RTC + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: DTEST_RTC + description: DTEST_RTC + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: SW_CPU_STALL + addressOffset: 172 + size: 32 + fields: + - name: SW_STALL_APPCPU_C1 + description: "{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU" + bitOffset: 20 + bitWidth: 6 + access: read-write + - name: SW_STALL_PROCPU_C1 + description: "{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU" + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: STORE4 + addressOffset: 176 + size: 32 + fields: + - name: SCRATCH4 + description: 32-bit general purpose retention register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE5 + addressOffset: 180 + size: 32 + fields: + - name: SCRATCH5 + description: 32-bit general purpose retention register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE6 + addressOffset: 184 + size: 32 + fields: + - name: SCRATCH6 + description: 32-bit general purpose retention register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE7 + addressOffset: 188 + size: 32 + fields: + - name: SCRATCH7 + description: 32-bit general purpose retention register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOW_POWER_ST + addressOffset: 192 + size: 32 + fields: + - name: LOW_POWER_DIAG0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - name: RDY_FOR_WAKEUP + description: "1 if RTC controller is ready to execute WAKE instruction, 0 otherwise" + bitOffset: 19 + bitWidth: 1 + access: read-only + - register: + name: DIAG1 + addressOffset: 196 + size: 32 + fields: + - name: LOW_POWER_DIAG1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HOLD_FORCE + addressOffset: 200 + size: 32 + fields: + - name: ADC1_HOLD_FORCE + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ADC2_HOLD_FORCE + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PDAC1_HOLD_FORCE + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PDAC2_HOLD_FORCE + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SENSE1_HOLD_FORCE + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SENSE2_HOLD_FORCE + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SENSE3_HOLD_FORCE + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SENSE4_HOLD_FORCE + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD0_HOLD_FORCE + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD1_HOLD_FORCE + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD2_HOLD_FORCE + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD3_HOLD_FORCE + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD4_HOLD_FORCE + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD5_HOLD_FORCE + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD6_HOLD_FORCE + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD7_HOLD_FORCE + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: X32P_HOLD_FORCE + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: X32N_HOLD_FORCE + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: EXT_WAKEUP1 + addressOffset: 204 + size: 32 + fields: + - name: SEL + description: Bitmap to select RTC pads for ext wakeup1 + bitOffset: 0 + bitWidth: 18 + access: read-write + - name: STATUS_CLR + description: clear ext wakeup1 status + bitOffset: 18 + bitWidth: 1 + access: write-only + - register: + name: EXT_WAKEUP1_STATUS + addressOffset: 208 + size: 32 + fields: + - name: EXT_WAKEUP1_STATUS + description: ext wakeup1 status + bitOffset: 0 + bitWidth: 18 + access: read-only + - register: + name: BROWN_OUT + addressOffset: 212 + size: 32 + resetValue: 335478784 + fields: + - name: RTC_MEM_PID_CONF + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: RTC_MEM_CRC_START + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RTC_MEM_CRC_ADDR + bitOffset: 9 + bitWidth: 11 + access: read-write + - name: CLOSE_FLASH_ENA + description: enable close flash when brown out happens + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PD_RF_ENA + description: enable power down RF when brown out happens + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RST_WAIT + description: brown out reset wait cycles + bitOffset: 16 + bitWidth: 10 + access: read-write + - name: RTC_MEM_CRC_LEN + bitOffset: 20 + bitWidth: 11 + access: read-write + - name: RST_ENA + description: enable brown out reset + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: DBROWN_OUT_THRES + description: brown out threshold + bitOffset: 27 + bitWidth: 3 + access: read-write + - name: ENA + description: enable brown out + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DET + description: brown out detect + bitOffset: 31 + bitWidth: 1 + access: read-only + - name: RTC_MEM_CRC_FINISH + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DATE + addressOffset: 316 + size: 32 + resetValue: 23085696 + fields: + - name: CNTL_DATE + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: RTC_IO + description: Low-power Input/Output + groupName: RTC_GPIO + baseAddress: 1072989184 + addressBlock: + - offset: 0 + size: 204 + usage: registers + registers: + - register: + name: OUT + addressOffset: 0 + size: 32 + fields: + - name: DATA + description: GPIO0~17 output value + bitOffset: 14 + bitWidth: 18 + access: read-write + - register: + name: OUT_W1TS + addressOffset: 4 + size: 32 + fields: + - name: OUT_DATA_W1TS + description: GPIO0~17 output value write 1 to set + bitOffset: 14 + bitWidth: 18 + access: write-only + - register: + name: OUT_W1TC + addressOffset: 8 + size: 32 + fields: + - name: OUT_DATA_W1TC + description: GPIO0~17 output value write 1 to clear + bitOffset: 14 + bitWidth: 18 + access: write-only + - register: + name: ENABLE + addressOffset: 12 + size: 32 + fields: + - name: ENABLE + description: GPIO0~17 output enable + bitOffset: 14 + bitWidth: 18 + access: read-write + - register: + name: ENABLE_W1TS + addressOffset: 16 + size: 32 + fields: + - name: ENABLE_W1TS + description: GPIO0~17 output enable write 1 to set + bitOffset: 14 + bitWidth: 18 + access: write-only + - register: + name: ENABLE_W1TC + addressOffset: 20 + size: 32 + fields: + - name: ENABLE_W1TC + description: GPIO0~17 output enable write 1 to clear + bitOffset: 14 + bitWidth: 18 + access: write-only + - register: + name: STATUS + addressOffset: 24 + size: 32 + fields: + - name: INT + description: GPIO0~17 interrupt status + bitOffset: 14 + bitWidth: 18 + access: read-write + - register: + name: STATUS_W1TS + addressOffset: 28 + size: 32 + fields: + - name: STATUS_INT_W1TS + description: GPIO0~17 interrupt status write 1 to set + bitOffset: 14 + bitWidth: 18 + access: write-only + - register: + name: STATUS_W1TC + addressOffset: 32 + size: 32 + fields: + - name: STATUS_INT_W1TC + description: GPIO0~17 interrupt status write 1 to clear + bitOffset: 14 + bitWidth: 18 + access: write-only + - register: + name: IN + addressOffset: 36 + size: 32 + fields: + - name: NEXT + description: GPIO0~17 input value + bitOffset: 14 + bitWidth: 18 + access: read-only + - register: + dim: 18 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17" + name: PIN%s + addressOffset: 40 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: GPIO wake up enable only available in light sleep + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: RTC_DEBUG_SEL + addressOffset: 112 + size: 32 + fields: + - name: DEBUG_SEL0 + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: DEBUG_SEL1 + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: DEBUG_SEL2 + bitOffset: 10 + bitWidth: 5 + access: read-write + - name: DEBUG_SEL3 + bitOffset: 15 + bitWidth: 5 + access: read-write + - name: DEBUG_SEL4 + bitOffset: 20 + bitWidth: 5 + access: read-write + - name: DEBUG_12M_NO_GATING + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: DIG_PAD_HOLD + addressOffset: 116 + size: 32 + fields: + - name: DIG_PAD_HOLD + description: select the digital pad hold value. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HALL_SENS + addressOffset: 120 + size: 32 + fields: + - name: HALL_PHASE + description: Reverse phase of hall sensor + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: XPD_HALL + description: Power on hall sensor and connect to VP and VN + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SENSOR_PADS + addressOffset: 124 + size: 32 + fields: + - name: SENSE4_FUN_IE + description: the input enable of the pad + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SENSE4_SLP_IE + description: the input enable of the pad in sleep status + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SENSE4_SLP_SEL + description: the sleep status selection signal of the pad + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SENSE4_FUN_SEL + description: the functional selection signal of the pad + bitOffset: 7 + bitWidth: 2 + access: read-write + - name: SENSE3_FUN_IE + description: the input enable of the pad + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SENSE3_SLP_IE + description: the input enable of the pad in sleep status + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SENSE3_SLP_SEL + description: the sleep status selection signal of the pad + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SENSE3_FUN_SEL + description: the functional selection signal of the pad + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: SENSE2_FUN_IE + description: the input enable of the pad + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SENSE2_SLP_IE + description: the input enable of the pad in sleep status + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SENSE2_SLP_SEL + description: the sleep status selection signal of the pad + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SENSE2_FUN_SEL + description: the functional selection signal of the pad + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: SENSE1_FUN_IE + description: the input enable of the pad + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SENSE1_SLP_IE + description: the input enable of the pad in sleep status + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SENSE1_SLP_SEL + description: the sleep status selection signal of the pad + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SENSE1_FUN_SEL + description: the functional selection signal of the pad + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: SENSE4_MUX_SEL + description: Ò1Ó select the digital function Ó0Óslection the rtc function + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SENSE3_MUX_SEL + description: Ò1Ó select the digital function Ó0Óslection the rtc function + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: SENSE2_MUX_SEL + description: Ò1Ó select the digital function Ó0Óslection the rtc function + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SENSE1_MUX_SEL + description: Ò1Ó select the digital function Ó0Óslection the rtc function + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SENSE4_HOLD + description: hold the current value of the output when setting the hold to Ò1Ó + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SENSE3_HOLD + description: hold the current value of the output when setting the hold to Ò1Ó + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SENSE2_HOLD + description: hold the current value of the output when setting the hold to Ò1Ó + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SENSE1_HOLD + description: hold the current value of the output when setting the hold to Ò1Ó + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: ADC_PAD + addressOffset: 128 + size: 32 + fields: + - name: ADC2_FUN_IE + description: the input enable of the pad + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: ADC2_SLP_IE + description: the input enable of the pad in sleep status + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: ADC2_SLP_SEL + description: the sleep status selection signal of the pad + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: ADC2_FUN_SEL + description: the functional selection signal of the pad + bitOffset: 21 + bitWidth: 2 + access: read-write + - name: ADC1_FUN_IE + description: the input enable of the pad + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: ADC1_SLP_IE + description: the input enable of the pad in sleep status + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ADC1_SLP_SEL + description: the sleep status selection signal of the pad + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: ADC1_FUN_SEL + description: the functional selection signal of the pad + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: ADC2_MUX_SEL + description: Ò1Ó select the digital function Ó0Óslection the rtc function + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: ADC1_MUX_SEL + description: Ò1Ó select the digital function Ó0Óslection the rtc function + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ADC2_HOLD + description: hold the current value of the output when setting the hold to Ò1Ó + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: ADC1_HOLD + description: hold the current value of the output when setting the hold to Ò1Ó + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: PAD_DAC1 + addressOffset: 132 + size: 32 + resetValue: 2147483648 + fields: + - name: PDAC1_DAC_XPD_FORCE + description: Power on DAC1. Usually we need to tristate PDAC1 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: PDAC1_FUN_IE + description: the input enable of the pad + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: PDAC1_SLP_OE + description: the output enable of the pad in sleep status + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PDAC1_SLP_IE + description: the input enable of the pad in sleep status + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: PDAC1_SLP_SEL + description: the sleep status selection signal of the pad + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PDAC1_FUN_SEL + description: the functional selection signal of the pad + bitOffset: 15 + bitWidth: 2 + access: read-write + - name: PDAC1_MUX_SEL + description: Ò1Ó select the digital function Ó0Óslection the rtc function + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: PDAC1_XPD_DAC + description: Power on DAC1. Usually we need to tristate PDAC1 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0 + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: PDAC1_DAC + description: PAD DAC1 control code. + bitOffset: 19 + bitWidth: 8 + access: read-write + - name: PDAC1_RUE + description: the pull up enable of the pad + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: PDAC1_RDE + description: the pull down enable of the pad + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: PDAC1_HOLD + description: hold the current value of the output when setting the hold to Ò1Ó + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: PDAC1_DRV + description: the driver strength of the pad + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: PAD_DAC2 + addressOffset: 136 + size: 32 + resetValue: 2147483648 + fields: + - name: PDAC2_DAC_XPD_FORCE + description: Power on DAC2. Usually we need to tristate PDAC2 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: PDAC2_FUN_IE + description: the input enable of the pad + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: PDAC2_SLP_OE + description: the output enable of the pad in sleep status + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PDAC2_SLP_IE + description: the input enable of the pad in sleep status + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: PDAC2_SLP_SEL + description: the sleep status selection signal of the pad + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PDAC2_FUN_SEL + description: the functional selection signal of the pad + bitOffset: 15 + bitWidth: 2 + access: read-write + - name: PDAC2_MUX_SEL + description: Ò1Ó select the digital function Ó0Óslection the rtc function + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: PDAC2_XPD_DAC + description: Power on DAC2. Usually we need to tristate PDAC1 if we power on the DAC i.e. IE=0 OE=0 RDE=0 RUE=0 + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: PDAC2_DAC + description: PAD DAC2 control code. + bitOffset: 19 + bitWidth: 8 + access: read-write + - name: PDAC2_RUE + description: the pull up enable of the pad + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: PDAC2_RDE + description: the pull down enable of the pad + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: PDAC2_HOLD + description: hold the current value of the output when setting the hold to Ò1Ó + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: PDAC2_DRV + description: the driver strength of the pad + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: XTAL_32K_PAD + addressOffset: 140 + size: 32 + resetValue: 2215641104 + fields: + - name: DBIAS_XTAL_32K + description: 32K XTAL self-bias reference control. + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: DRES_XTAL_32K + description: 32K XTAL resistor bias control. + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: X32P_FUN_IE + description: the input enable of the pad + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: X32P_SLP_OE + description: the output enable of the pad in sleep status + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: X32P_SLP_IE + description: the input enable of the pad in sleep status + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: X32P_SLP_SEL + description: the sleep status selection signal of the pad + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: X32P_FUN_SEL + description: the functional selection signal of the pad + bitOffset: 9 + bitWidth: 2 + access: read-write + - name: X32N_FUN_IE + description: the input enable of the pad + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: X32N_SLP_OE + description: the output enable of the pad in sleep status + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: X32N_SLP_IE + description: the input enable of the pad in sleep status + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: X32N_SLP_SEL + description: the sleep status selection signal of the pad + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: X32N_FUN_SEL + description: the functional selection signal of the pad + bitOffset: 15 + bitWidth: 2 + access: read-write + - name: X32P_MUX_SEL + description: Ò1Ó select the digital function Ó0Óslection the rtc function + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: X32N_MUX_SEL + description: Ò1Ó select the digital function Ó0Óslection the rtc function + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: XPD_XTAL_32K + description: Power up 32kHz crystal oscillator + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: DAC_XTAL_32K + description: 32K XTAL bias current DAC. + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: X32P_RUE + description: the pull up enable of the pad + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: X32P_RDE + description: the pull down enable of the pad + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: X32P_HOLD + description: hold the current value of the output when setting the hold to Ò1Ó + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: X32P_DRV + description: the driver strength of the pad + bitOffset: 25 + bitWidth: 2 + access: read-write + - name: X32N_RUE + description: the pull up enable of the pad + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: X32N_RDE + description: the pull down enable of the pad + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: X32N_HOLD + description: hold the current value of the output when setting the hold to Ò1Ó + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: X32N_DRV + description: the driver strength of the pad + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_CFG + addressOffset: 144 + size: 32 + resetValue: 1711276032 + fields: + - name: TOUCH_DCUR + description: touch sensor bias current. Should have option to tie with BIAS_SLEEP(When BIAS_SLEEP this setting is available + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: TOUCH_DRANGE + description: touch sensor saw wave voltage range. + bitOffset: 25 + bitWidth: 2 + access: read-write + - name: TOUCH_DREFL + description: touch sensor saw wave bottom voltage. + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: TOUCH_DREFH + description: touch sensor saw wave top voltage. + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: TOUCH_XPD_BIAS + description: touch sensor bias power on. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TOUCH_PAD0 + addressOffset: 148 + size: 32 + resetValue: 1375731712 + fields: + - name: TO_GPIO + description: connect the rtc pad input to digital pad input Ó0Ó is availbale GPIO4 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: the input enable of the pad + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: the output enable of the pad in sleep status + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: the input enable of the pad in sleep status + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: the sleep status selection signal of the pad + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: the functional selection signal of the pad + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: Ò1Ó select the digital function Ó0Óslection the rtc function + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: touch sensor power on. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: "default touch sensor tie option. 0: tie low 1: tie high." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: start touch sensor. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: DAC + description: touch sensor slope control. 3-bit for each touch panel default 100. + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: RUE + description: the pull up enable of the pad + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: the pull down enable of the pad + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: the driver strength of the pad + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: HOLD + description: hold the current value of the output when setting the hold to Ò1Ó + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TOUCH_PAD1 + addressOffset: 152 + size: 32 + resetValue: 1241513984 + fields: + - name: TO_GPIO + description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO0 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: the input enable of the pad + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: the output enable of the pad in sleep status + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: the input enable of the pad in sleep status + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: the sleep status selection signal of the pad + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: the functional selection signal of the pad + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: Ò1Ó select the digital function Ó0Óslection the rtc function + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: touch sensor power on. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: "default touch sensor tie option. 0: tie low 1: tie high." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: start touch sensor. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: DAC + description: touch sensor slope control. 3-bit for each touch panel default 100. + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: RUE + description: the pull up enable of the pad + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: the pull down enable of the pad + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: the driver strength of the pad + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: HOLD + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TOUCH_PAD2 + addressOffset: 156 + size: 32 + resetValue: 1375731712 + fields: + - name: TO_GPIO + description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO2 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: the input enable of the pad + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: the output enable of the pad in sleep status + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: the input enable of the pad in sleep status + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: the sleep status selection signal of the pad + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: the functional selection signal of the pad + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: Ò1Ó select the digital function Ó0Óslection the rtc function + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: touch sensor power on. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: "default touch sensor tie option. 0: tie low 1: tie high." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: start touch sensor. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: DAC + description: touch sensor slope control. 3-bit for each touch panel default 100. + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: RUE + description: the pull up enable of the pad + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: the pull down enable of the pad + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: the driver strength of the pad + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: HOLD + description: hold the current value of the output when setting the hold to Ò1Ó + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TOUCH_PAD3 + addressOffset: 160 + size: 32 + resetValue: 1241513984 + fields: + - name: TO_GPIO + description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDO + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: the input enable of the pad + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: the output enable of the pad in sleep status + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: the input enable of the pad in sleep status + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: the sleep status selection signal of the pad + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: the functional selection signal of the pad + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: Ò1Ó select the digital function Ó0Óslection the rtc function + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: touch sensor power on. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: "default touch sensor tie option. 0: tie low 1: tie high." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: start touch sensor. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: DAC + description: touch sensor slope control. 3-bit for each touch panel default 100. + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: RUE + description: the pull up enable of the pad + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: the pull down enable of the pad + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: the driver strength of the pad + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: HOLD + description: hold the current value of the output when setting the hold to Ò1Ó + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TOUCH_PAD4 + addressOffset: 164 + size: 32 + resetValue: 1375731712 + fields: + - name: TO_GPIO + description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTCK + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: the input enable of the pad + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: the output enable of the pad in sleep status + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: the input enable of the pad in sleep status + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: the sleep status selection signal of the pad + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: the functional selection signal of the pad + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: Ò1Ó select the digital function Ó0Óslection the rtc function + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: touch sensor power on. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: "default touch sensor tie option. 0: tie low 1: tie high." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: start touch sensor. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: DAC + description: touch sensor slope control. 3-bit for each touch panel default 100. + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: RUE + description: the pull up enable of the pad + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: the pull down enable of the pad + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: the driver strength of the pad + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: HOLD + description: hold the current value of the output when setting the hold to Ò1Ó + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TOUCH_PAD5 + addressOffset: 168 + size: 32 + resetValue: 1375731712 + fields: + - name: TO_GPIO + description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTDI + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: the input enable of the pad + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: the output enable of the pad in sleep status + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: the input enable of the pad in sleep status + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: the sleep status selection signal of the pad + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: the functional selection signal of the pad + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: Ò1Ó select the digital function Ó0Óslection the rtc function + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: touch sensor power on. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: "default touch sensor tie option. 0: tie low 1: tie high." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: start touch sensor. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: DAC + description: touch sensor slope control. 3-bit for each touch panel default 100. + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: RUE + description: the pull up enable of the pad + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: the pull down enable of the pad + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: the driver strength of the pad + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: HOLD + description: hold the current value of the output when setting the hold to Ò1Ó + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TOUCH_PAD6 + addressOffset: 172 + size: 32 + resetValue: 1241513984 + fields: + - name: TO_GPIO + description: connect the rtc pad input to digital pad input Ó0Ó is availbale.MTMS + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: the input enable of the pad + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: the output enable of the pad in sleep status + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: the input enable of the pad in sleep status + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: the sleep status selection signal of the pad + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: the functional selection signal of the pad + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: Ò1Ó select the digital function Ó0Óslection the rtc function + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: touch sensor power on. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: "default touch sensor tie option. 0: tie low 1: tie high." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: start touch sensor. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: DAC + description: touch sensor slope control. 3-bit for each touch panel default 100. + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: RUE + description: the pull up enable of the pad + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: the pull down enable of the pad + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: the driver strength of the pad + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: HOLD + description: hold the current value of the output when setting the hold to Ò1Ó + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TOUCH_PAD7 + addressOffset: 176 + size: 32 + resetValue: 1107296256 + fields: + - name: TO_GPIO + description: connect the rtc pad input to digital pad input Ó0Ó is availbale.GPIO27 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: the input enable of the pad + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: the output enable of the pad in sleep status + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: the input enable of the pad in sleep status + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: the sleep status selection signal of the pad + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: the functional selection signal of the pad + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: Ò1Ó select the digital function Ó0Óslection the rtc function + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: touch sensor power on. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: "default touch sensor tie option. 0: tie low 1: tie high." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: start touch sensor. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: DAC + description: touch sensor slope control. 3-bit for each touch panel default 100. + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: RUE + description: the pull up enable of the pad + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: the pull down enable of the pad + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: the driver strength of the pad + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: HOLD + description: hold the current value of the output when setting the hold to Ò1Ó + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TOUCH_PAD8 + addressOffset: 180 + size: 32 + resetValue: 33554432 + fields: + - name: TO_GPIO + description: connect the rtc pad input to digital pad input Ó0Ó is availbale + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: touch sensor power on. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: "default touch sensor tie option. 0: tie low 1: tie high." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: start touch sensor. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: DAC + description: touch sensor slope control. 3-bit for each touch panel default 100. + bitOffset: 23 + bitWidth: 3 + access: read-write + - register: + name: TOUCH_PAD9 + addressOffset: 184 + size: 32 + resetValue: 33554432 + fields: + - name: TO_GPIO + description: connect the rtc pad input to digital pad input Ó0Ó is availbale + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: touch sensor power on. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: "default touch sensor tie option. 0: tie low 1: tie high." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: start touch sensor. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: DAC + description: touch sensor slope control. 3-bit for each touch panel default 100. + bitOffset: 23 + bitWidth: 3 + access: read-write + - register: + name: EXT_WAKEUP0 + addressOffset: 188 + size: 32 + fields: + - name: SEL + description: select the wakeup source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17 + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: XTL_EXT_CTR + addressOffset: 192 + size: 32 + fields: + - name: SEL + description: select the external xtl power source Ó0Ó select GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17 + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: SAR_I2C_IO + addressOffset: 196 + size: 32 + fields: + - name: SAR_DEBUG_BIT_SEL + bitOffset: 23 + bitWidth: 5 + access: read-write + - name: SAR_I2C_SCL_SEL + description: "Ò0Ó using TOUCH_PAD[0] as i2c clk Ò1Ó using TOUCH_PAD[2] as i2c clk" + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: SAR_I2C_SDA_SEL + description: "Ò0Ó using TOUCH_PAD[1] as i2c sda Ò1Ó using TOUCH_PAD[3] as i2c sda" + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: DATE + addressOffset: 200 + size: 32 + resetValue: 23081312 + fields: + - name: IO_DATE + description: date + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: RTC_I2C + description: Low-power I2C (Inter-Integrated Circuit) Controller + groupName: RTC_I2C + baseAddress: 1072991232 + addressBlock: + - offset: 0 + size: 60 + usage: registers + registers: + - register: + name: SCL_LOW_PERIOD + addressOffset: 0 + size: 32 + fields: + - name: SCL_LOW_PERIOD + description: number of cycles that scl == 0 + bitOffset: 0 + bitWidth: 25 + access: read-write + - register: + name: CTRL + addressOffset: 4 + size: 32 + fields: + - name: SDA_FORCE_OUT + description: SDA is push-pull (1) or open-drain (0) + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_FORCE_OUT + description: SCL is push-pull (1) or open-drain (0) + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MS_MODE + description: Master (1) or slave (0) + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TRANS_START + description: Force to generate start condition + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TX_LSB_FIRST + description: Send LSB first + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_LSB_FIRST + description: Receive LSB first + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: DEBUG_STATUS + addressOffset: 8 + size: 32 + fields: + - name: ACK_VAL + description: The value of an acknowledge signal on the bus + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLAVE_RW + description: "When working as a slave, the value of R/W bit received" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMED_OUT + description: Transfer has timed out + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ARB_LOST + description: "When working as a master, lost control of I2C bus" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: BUS_BUSY + description: operation is in progress + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SLAVE_ADDR_MATCH + description: "When working as a slave, whether address was matched" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BYTE_TRANS + description: 8 bit transmit done + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: MAIN_STATE + description: state of the main state machine + bitOffset: 25 + bitWidth: 3 + access: read-write + - name: SCL_STATE + description: state of SCL state machine + bitOffset: 28 + bitWidth: 3 + access: read-write + - register: + name: TIMEOUT + addressOffset: 12 + size: 32 + fields: + - name: TIMEOUT + description: Maximum number of FAST_CLK cycles that the transmission can take + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: SLAVE_ADDR + addressOffset: 16 + size: 32 + fields: + - name: SLAVE_ADDR + description: local slave address + bitOffset: 0 + bitWidth: 15 + access: read-write + - name: _10BIT + description: Set if local slave address is 10-bit + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DATA + addressOffset: 28 + size: 32 + - register: + name: INT_RAW + addressOffset: 32 + size: 32 + fields: + - name: SLAVE_TRANS_COMPLETE_INT_RAW + description: Slave accepted 1 byte and address matched + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ARBITRATION_LOST_INT_RAW + description: Master lost arbitration + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MASTER_TRANS_COMPLETE_INT_RAW + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TRANS_COMPLETE_INT_RAW + description: Stop condition has been detected interrupt raw status + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TIME_OUT_INT_RAW + description: time out interrupt raw status + bitOffset: 7 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + addressOffset: 36 + size: 32 + fields: + - name: SLAVE_TRANS_COMPLETE_INT_CLR + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ARBITRATION_LOST_INT_CLR + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: MASTER_TRANS_COMPLETE_INT_CLR + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TRANS_COMPLETE_INT_CLR + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TIME_OUT_INT_CLR + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: INT_EN + addressOffset: 40 + size: 32 + - register: + name: INT_ST + addressOffset: 44 + size: 32 + - register: + name: SDA_DUTY + addressOffset: 48 + size: 32 + fields: + - name: SDA_DUTY + description: Number of FAST_CLK cycles SDA will switch after falling edge of SCL + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: SCL_HIGH_PERIOD + addressOffset: 56 + size: 32 + fields: + - name: SCL_HIGH_PERIOD + description: Number of FAST_CLK cycles for SCL to be high + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: SCL_START_PERIOD + addressOffset: 64 + size: 32 + fields: + - name: SCL_START_PERIOD + description: Number of FAST_CLK cycles to wait before generating start condition + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: SCL_STOP_PERIOD + addressOffset: 68 + size: 32 + fields: + - name: SCL_STOP_PERIOD + description: Number of FAST_CLK cycles to wait before generating stop condition + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: CMD + addressOffset: 72 + size: 32 + fields: + - name: VAL + description: Command content + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: DONE + description: Bit is set by HW when command is done + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: SDHOST + description: SD/MMC Host Controller + groupName: SDHOST + baseAddress: 1073119232 + addressBlock: + - offset: 0 + size: 164 + usage: registers + registers: + - register: + name: CTRL + description: Control register + addressOffset: 0 + size: 32 + fields: + - name: CONTROLLER_RESET + description: "To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FIFO_RESET + description: "To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation.\nNote: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DMA_RESET + description: "To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_ENABLE + description: "Global interrupt enable/disable bit. 0: Disable; 1: Enable." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: READ_WAIT + description: For sending read-wait to SDIO cards. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SEND_IRQ_RESPONSE + description: "Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: ABORT_READ_DATA + description: "After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SEND_CCSD + description: "When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. \nNOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SEND_AUTO_STOP_CCSD + description: "Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CEATA_DEVICE_INTERRUPT_STATUS + description: "Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit." + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: CLKDIV + description: Clock divider configuration register + addressOffset: 8 + size: 32 + fields: + - name: CLK_DIVIDER0 + description: "Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CLK_DIVIDER1 + description: "Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on." + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: CLK_DIVIDER2 + description: "Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on." + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: CLK_DIVIDER3 + description: "Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on." + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: CLKSRC + description: Clock source selection register + addressOffset: 12 + size: 32 + fields: + - name: CLKSRC + description: "Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for card 1. Card 0 maps and internally routes clock divider[0:3] outputs to cclk_out[1:0] pins, depending on bit value.\n00 : Clock divider 0;\n01 : Clock divider 1;\n10 : Clock divider 2;\n11 : Clock divider 3." + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CLKENA + description: Clock enable register + addressOffset: 16 + size: 32 + fields: + - name: CCLK_ENABLE + description: "Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card.\n0: Clock disabled;\n1: Clock enabled." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: LP_ENABLE + description: "Disable clock when the card is in IDLE state. One bit per card.\n0: clock disabled;\n1: clock enabled." + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: TMOUT + description: Data and response timeout configuration register + addressOffset: 20 + size: 32 + resetValue: 4294967104 + fields: + - name: RESPONSE_TIMEOUT + description: "Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: DATA_TIMEOUT + description: "Value for card data read timeout. This value is also used for data starvation by host timeout. The timeout counter is started only after the card clock is stopped. This value is specified in number of card output clocks, i.e. sdhost_cclk_out of the selected card.\nNOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled." + bitOffset: 8 + bitWidth: 24 + access: read-write + - register: + name: CTYPE + description: Card bus width configuration register + addressOffset: 24 + size: 32 + fields: + - name: CARD_WIDTH4 + description: "One bit per card indicates if card is 1-bit or 4-bit mode.\n0: 1-bit mode;\n1: 4-bit mode.\nBit[1:0] correspond to card[1:0] respectively." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CARD_WIDTH8 + description: "One bit per card indicates if card is in 8-bit mode.\n0: Non 8-bit mode;\n1: 8-bit mode.\nBit[17:16] correspond to card[1:0] respectively." + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: BLKSIZ + description: Card data block size configuration register + addressOffset: 28 + size: 32 + resetValue: 512 + fields: + - name: BLOCK_SIZE + description: Block size. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: BYTCNT + description: Data transfer length configuration register + addressOffset: 32 + size: 32 + resetValue: 512 + fields: + - name: BYTE_COUNT + description: "Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: INTMASK + description: SDIO interrupt mask register + addressOffset: 36 + size: 32 + fields: + - name: INT_MASK + description: "These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt.\nBit 15 (EBE): End-bit error/no CRC error;\nBit 14 (ACD): Auto command done;\nBit 13 (SBE/BCI): Rx Start Bit Error;\nBit 12 (HLE): Hardware locked write error;\nBit 11 (FRUN): FIFO underrun/overrun error;\nBit 10 (HTO): Data starvation-by-host timeout;\nBit 9 (DRTO): Data read timeout;\nBit 8 (RTO): Response timeout; \nBit 7 (DCRC): Data CRC error; \nBit 6 (RCRC): Response CRC error; \nBit 5 (RXDR): Receive FIFO data request; \nBit 4 (TXDR): Transmit FIFO data request; \nBit 3 (DTO): Data transfer over; \nBit 2 (CD): Command done; \nBit 1 (RE): Response error;\nBit 0 (CD): Card detect." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SDIO_INT_MASK + description: "SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0] respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt, and 1 enables an interrupt." + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: CMDARG + description: Command argument data register + addressOffset: 40 + size: 32 + fields: + - name: CMDARG + description: Value indicates command argument to be passed to the card. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CMD + description: Command and boot configuration register + addressOffset: 44 + size: 32 + resetValue: 536870912 + fields: + - name: INDEX + description: Command index. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: RESPONSE_EXPECT + description: "0: No response expected from card; 1: Response expected from card." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RESPONSE_LENGTH + description: "0: Short response expected from card; 1: Long response expected from card." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CHECK_RESPONSE_CRC + description: "0: Do not check; 1: Check response CRC.\nSome of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DATA_EXPECTED + description: "0: No data transfer expected; 1: Data transfer expected." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: READ_WRITE + description: "0: Read from card; 1: Write to card.\nDon't care if no data is expected from card." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TRANSFER_MODE + description: "Block data transfer command; 1: Stream data transfer command.\nDon't care if no data expected." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SEND_AUTO_STOP + description: "0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: WAIT_PRVDATA_COMPLETE + description: "0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command.\nThe SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: STOP_ABORT_CMD + description: "0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress.\nWhen open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SEND_INITIALIZATION + description: "0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command.\nAfter powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CARD_NUMBER + description: "Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported." + bitOffset: 16 + bitWidth: 5 + access: read-write + - name: UPDATE_CLOCK_REGISTERS_ONLY + description: "0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain.\nFollowing register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA.\nChanges card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: READ_CEATA_DEVICE + description: "Read access flag.\n0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device;\n1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device.\nSoftware should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: CCS_EXPECTED + description: "Expected Command Completion Signal (CCS) configuration.\n0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device;\n1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. \nIf the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: USE_HOLE + description: "Use Hold Register.\n0: CMD and DATA sent to card bypassing HOLD Register;\n1: CMD and DATA sent to card through the HOLD Register." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: START_CMD + description: "Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RESP0 + description: Response data register + addressOffset: 48 + size: 32 + fields: + - name: RESPONSE0 + description: "Bit[31:0] of response." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RESP1 + description: Long response data register + addressOffset: 52 + size: 32 + fields: + - name: RESPONSE1 + description: "Bit[63:32] of long response." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RESP2 + description: Long response data register + addressOffset: 56 + size: 32 + fields: + - name: RESPONSE2 + description: "Bit[95:64] of long response." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RESP3 + description: Long response data register + addressOffset: 60 + size: 32 + fields: + - name: RESPONSE3 + description: "Bit[127:96] of long response." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: MINTSTS + description: Masked interrupt status register + addressOffset: 64 + size: 32 + fields: + - name: INT_STATUS_MSK + description: "Interrupt enabled only if corresponding bit in interrupt mask register is set.\nBit 15 (EBE): End-bit error/no CRC error;\nBit 14 (ACD): Auto command done;\nBit 13 (SBE/BCI): RX Start Bit Error;\nBit 12 (HLE): Hardware locked write error; \nBit 11 (FRUN): FIFO underrun/overrun error;\nBit 10 (HTO): Data starvation by host timeout (HTO);\nBit 9 (DTRO): Data read timeout; \nBit 8 (RTO): Response timeout; \nBit 7 (DCRC): Data CRC error; \nBit 6 (RCRC): Response CRC error; \nBit 5 (RXDR): Receive FIFO data request; \nBit 4 (TXDR): Transmit FIFO data request;\nBit 3 (DTO): Data transfer over; \nBit 2 (CD): Command done; \nBit 1 (RE): Response error;\nBit 0 (CD): Card detect." + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: SDIO_INTERRUPT_MSK + description: "Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. SDIO interrupt for card is enabled only if corresponding sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit enables interrupt)." + bitOffset: 16 + bitWidth: 2 + access: read-only + - register: + name: RINTSTS + description: Raw interrupt status register + addressOffset: 68 + size: 32 + fields: + - name: INT_STATUS_RAW + description: "Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status.\nBit 15 (EBE): End-bit error/no CRC error;\nBit 14 (ACD): Auto command done;\nBit 13 (SBE/BCI): RX Start Bit Error;\nBit 12 (HLE): Hardware locked write error; \nBit 11 (FRUN): FIFO underrun/overrun error;\nBit 10 (HTO): Data starvation by host timeout (HTO);\nBit 9 (DTRO): Data read timeout; \nBit 8 (RTO): Response timeout; \nBit 7 (DCRC): Data CRC error; \nBit 6 (RCRC): Response CRC error; \nBit 5 (RXDR): Receive FIFO data request; \nBit 4 (TXDR): Transmit FIFO data request;\nBit 3 (DTO): Data transfer over; \nBit 2 (CD): Command done; \nBit 1 (RE): Response error;\nBit 0 (CD): Card detect." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SDIO_INTERRUPT_RAW + description: "Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has no effect.\n0: No SDIO interrupt from card;\n1: SDIO interrupt from card." + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: STATUS + description: SD/MMC status register + addressOffset: 72 + size: 32 + resetValue: 1814 + fields: + - name: FIFO_RX_WATERMARK + description: "FIFO reached Receive watermark level, not qualified with data transfer." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: FIFO_TX_WATERMARK + description: "FIFO reached Transmit watermark level, not qualified with data transfer." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: FIFO_EMPTY + description: FIFO is empty status. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FIFO_FULL + description: FIFO is full status. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: COMMAND_FSM_STATES + description: "Command FSM states.\n0: Idle;\n1: Send init sequence; \n2: Send cmd start bit; \n3: Send cmd tx bit;\n4: Send cmd index + arg;\n5: Send cmd crc7;\n6: Send cmd end bit;\n7: Receive resp start bit;\n8: Receive resp IRQ response;\n9: Receive resp tx bit;\n10: Receive resp cmd idx;\n11: Receive resp data;\n12: Receive resp crc7;\n13: Receive resp end bit;\n14: Cmd path wait NCC;\n15: Wait, cmd-to-response turnaround." + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: DATA_3_STATUS + description: "Raw selected sdhost_card_data[3], checks whether card is present.\n0: card not present;\n1: card present." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DATA_BUSY + description: "Inverted version of raw selected sdhost_card_data[0].\n0: Card data not busy;\n1: Card data busy." + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: DATA_STATE_MC_BUSY + description: Data transmit or receive state-machine is busy. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: RESPONSE_INDEX + description: "Index of previous response, including any auto-stop sent by core." + bitOffset: 11 + bitWidth: 6 + access: read-only + - name: FIFO_COUNT + description: "FIFO count, number of filled locations in FIFO." + bitOffset: 17 + bitWidth: 13 + access: read-only + - register: + name: FIFOTH + description: FIFO configuration register + addressOffset: 76 + size: 32 + fields: + - name: TX_WMARK + description: "FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred." + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: RX_WMARK + description: "FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set." + bitOffset: 16 + bitWidth: 11 + access: read-write + - name: DMA_MULTIPLE_TRANSACTION_SIZE + description: "Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE.\n000: 1-byte transfer; \n001: 4-byte transfer; \n010: 8-byte transfer; \n011: 16-byte transfer; \n100: 32-byte transfer; \n101: 64-byte transfer; \n110: 128-byte transfer; \n111: 256-byte transfer." + bitOffset: 28 + bitWidth: 3 + access: read-write + - register: + name: CDETECT + description: Card detect register + addressOffset: 80 + size: 32 + fields: + - name: CARD_DETECT_N + description: "Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0 represents presence of card. Only NUM_CARDS number of bits are implemented." + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: WRTPRT + description: Card write protection (WP) status register + addressOffset: 84 + size: 32 + fields: + - name: WRITE_PROTECT + description: Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write protection. Only NUM_CARDS number of bits are implemented. + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: TCBCNT + description: Transferred byte count register + addressOffset: 92 + size: 32 + fields: + - name: TCBCNT + description: Number of bytes transferred by CIU unit to card. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: TBBCNT + description: Transferred byte count register + addressOffset: 96 + size: 32 + fields: + - name: TBBCNT + description: Number of bytes transferred between Host/DMA memory and BIU FIFO. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEBNCE + description: Debounce filter time configuration register + addressOffset: 100 + size: 32 + fields: + - name: DEBOUNCE_COUNT + description: "Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \\verb+~+ 25 ms to prevent the card instability when the card is inserted or removed." + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: USRID + description: User ID (scratchpad) register + addressOffset: 104 + size: 32 + fields: + - name: USRID + description: "User identification register, value set by user. Can also be used as a scratchpad register by user." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: VERID + description: Version ID (scratchpad) register + addressOffset: 108 + size: 32 + resetValue: 1412572938 + fields: + - name: VERSIONID + description: Hardware version register. Can also be read by fireware. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HCON + description: Hardware feature register + addressOffset: 112 + size: 32 + resetValue: 54807747 + fields: + - name: CARD_TYPE + description: Hardware support SDIO and MMC. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CARD_NUM + description: Support card number is 2. + bitOffset: 1 + bitWidth: 5 + access: read-only + - name: BUS_TYPE + description: Register config is APB bus. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: DATA_WIDTH + description: Regisger data widht is 32. + bitOffset: 7 + bitWidth: 3 + access: read-only + - name: ADDR_WIDTH + description: Register address width is 32. + bitOffset: 10 + bitWidth: 6 + access: read-only + - name: DMA_WIDTH + description: DMA data witdth is 32. + bitOffset: 18 + bitWidth: 3 + access: read-only + - name: RAM_INDISE + description: Inside RAM in SDMMC module. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: HOLD + description: Have a hold regiser in data path . + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: NUM_CLK_DIV + description: Have 4 clk divider in design . + bitOffset: 24 + bitWidth: 2 + access: read-only + - register: + name: UHS + description: UHS-1 register + addressOffset: 116 + size: 32 + fields: + - name: DDR + description: "DDR mode selecton,1 bit for each card.\n0-Non-DDR mdoe.\n1-DDR mdoe." + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: RST_N + description: Card reset register + addressOffset: 120 + size: 32 + resetValue: 1 + fields: + - name: CARD_RESET + description: "Hardware reset.\n1: Active mode; \n0: Reset. \nThese bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET[0] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET[1] should be set to 1'b0 to reset card1." + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: BMOD + description: Burst mode transfer configuration register + addressOffset: 128 + size: 32 + fields: + - name: SWR + description: "Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FB + description: "Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DE + description: "IDMAC Enable. When set, the IDMAC is enabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: PBL + description: "Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows:\n000: 1-byte transfer; \n001: 4-byte transfer; \n010: 8-byte transfer; \n011: 16-byte transfer; \n100: 32-byte transfer; \n101: 64-byte transfer; \n110: 128-byte transfer; \n111: 256-byte transfer.\nPBL is a read-only value and is applicable only for data access, it does not apply to descriptor access." + bitOffset: 8 + bitWidth: 3 + access: read-write + - register: + name: PLDMND + description: Poll demand configuration register + addressOffset: 132 + size: 32 + fields: + - name: PD + description: "Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal descriptor fetch operation. This is a write only ." + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: DBADDR + description: Descriptor base address register + addressOffset: 136 + size: 32 + fields: + - name: DBADDR + description: "Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: IDSTS + description: IDMAC status register + addressOffset: 140 + size: 32 + fields: + - name: TI + description: Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RI + description: Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FBE + description: "Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DU + description: "Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0[31] = 0). Writing 1 clears this bit." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CES + description: "Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits:\nEBE : End Bit Error; \nRTO : Response Timeout/Boot Ack Timeout; \nRCRC : Response CRC; \nSBE : Start Bit Error; \nDRTO : Data Read Timeout/BDS timeout; \nDCRC : Data CRC for Receive; \nRE : Response Error.\nWriting 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: NIS + description: "Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit Interrupt, IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: AIS + description: "Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus Interrupt, IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FBE_CODE + description: "Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an interrupt.\n001: Host Abort received during transmission;\n010: Host Abort received during reception;\nOthers: Reserved." + bitOffset: 10 + bitWidth: 3 + access: read-write + - name: FSM + description: "DMAC FSM present state.\n0: DMA_IDLE (idle state); \n1: DMA_SUSPEND (suspend state); \n2: DESC_RD (descriptor reading state); \n3: DESC_CHK (descriptor checking state); \n4: DMA_RD_REQ_WAIT (read-data request waiting state);\n5: DMA_WR_REQ_WAIT (write-data request waiting state); \n6: DMA_RD (data-read state); \n7: DMA_WR (data-write state); \n8: DESC_CLOSE (descriptor close state)." + bitOffset: 13 + bitWidth: 4 + access: read-write + - register: + name: IDINTEN + description: IDMAC interrupt enable register + addressOffset: 144 + size: 32 + fields: + - name: TI + description: "Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RI + description: "Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FBE + description: "Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DU + description: "Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CES + description: "Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: NI + description: "Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits:\nIDINTEN[0]: Transmit Interrupt;\nIDINTEN[1]: Receive Interrupt." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: AI + description: "Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits:\nIDINTEN[2]: Fatal Bus Error Interrupt;\nIDINTEN[4]: DU Interrupt." + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: DSCADDR + description: Host descriptor address pointer + addressOffset: 148 + size: 32 + fields: + - name: DSCADDR + description: "Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the start address of the current descriptor read by the IDMAC." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BUFADDR + description: Host buffer address pointer register + addressOffset: 152 + size: 32 + fields: + - name: BUFADDR + description: "Host Buffer Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the current Data Buffer Address being accessed by the IDMAC." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CARDTHRCTL + description: Card Threshold Control register + addressOffset: 256 + size: 32 + fields: + - name: CARDRDTHREN + description: "Card read threshold enable.\n1'b0-Card read threshold disabled.\n1'b1-Card read threshold enabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CARDCLRINTEN + description: "Busy clear interrupt generation:\n1'b0-Busy clear interrypt disabled.\n1'b1-Busy clear interrypt enabled." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CARDWRTHREN + description: "Applicable when HS400 mode is enabled.\n1'b0-Card write Threshold disabled.\n1'b1-Card write Threshold enabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CARDTHRESHOLD + description: "The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG set to 1." + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: EMMCDDR + description: eMMC DDR register + addressOffset: 268 + size: 32 + fields: + - name: HALFSTARTBIT + description: "Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be:\n1'b0-Full cycle.\n1'b1-less than one full cycle." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: HS400_MODE + description: Set 1 to enable HS400 mode. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: ENSHIFT + description: Enable Phase Shift register + addressOffset: 272 + size: 32 + fields: + - name: ENABLE_SHIFT + description: "Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card.\n2'b00-Default phase shift.\n2'b01-Enables shifted to next immediate positive edge.\n2'b10-Enables shifted to next immediate negative edge.\n2'b11-Reserved." + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: BUFFIFO + description: CPU write and read transmit data by FIFO + addressOffset: 512 + size: 32 + fields: + - name: BUFFIFO + description: CPU write and read transmit data by FIFO. This register points to the current Data FIFO . + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CLK_EDGE_SEL + description: SDIO control register. + addressOffset: 2048 + size: 32 + resetValue: 8520192 + fields: + - name: CCLKIN_EDGE_DRV_SEL + description: "It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270." + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: CCLKIN_EDGE_SAM_SEL + description: "It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270." + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: CCLKIN_EDGE_SLF_SEL + description: "It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270." + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: CCLLKIN_EDGE_H + description: The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L. + bitOffset: 9 + bitWidth: 4 + access: read-write + - name: CCLLKIN_EDGE_L + description: The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H. + bitOffset: 13 + bitWidth: 4 + access: read-write + - name: CCLLKIN_EDGE_N + description: The value should be equal to CCLKIN_EDGE_L. + bitOffset: 17 + bitWidth: 4 + access: read-write + - name: ESDIO_MODE + description: Enable esdio mode. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: ESD_MODE + description: Enable esd mode. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: CCLK_EN + description: Sdio clock enable + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SENS + description: SENS Peripheral + groupName: SENS + baseAddress: 1072990208 + addressBlock: + - offset: 0 + size: 168 + usage: registers + registers: + - register: + name: SAR_READ_CTRL + addressOffset: 0 + size: 32 + resetValue: 461058 + fields: + - name: SAR1_CLK_DIV + description: clock divider + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SAR1_SAMPLE_CYCLE + description: sample cycles for SAR ADC1 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SAR1_SAMPLE_BIT + description: "00: for 9-bit width 01: for 10-bit width 10: for 11-bit width 11: for 12-bit width" + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: SAR1_CLK_GATED + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SAR1_SAMPLE_NUM + bitOffset: 19 + bitWidth: 8 + access: read-write + - name: SAR1_DIG_FORCE + description: "1: SAR ADC1 controlled by DIG ADC1 CTRL 0: SAR ADC1 controlled by RTC ADC1 CTRL" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SAR1_DATA_INV + description: Invert SAR ADC1 data + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: SAR_READ_STATUS1 + addressOffset: 4 + size: 32 + fields: + - name: SAR1_READER_STATUS + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SAR_MEAS_WAIT1 + addressOffset: 8 + size: 32 + resetValue: 655370 + fields: + - name: SAR_AMP_WAIT1 + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SAR_AMP_WAIT2 + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SAR_MEAS_WAIT2 + addressOffset: 12 + size: 32 + resetValue: 2097162 + fields: + - name: FORCE_XPD_SAR_SW + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SAR_AMP_WAIT3 + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: FORCE_XPD_AMP + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: FORCE_XPD_SAR + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: SAR2_RSTB_WAIT + bitOffset: 20 + bitWidth: 8 + access: read-write + - register: + name: SAR_MEAS_CTRL + addressOffset: 16 + size: 32 + resetValue: 117912463 + fields: + - name: XPD_SAR_AMP_FSM + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: AMP_RST_FB_FSM + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: AMP_SHORT_REF_FSM + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: AMP_SHORT_REF_GND_FSM + bitOffset: 12 + bitWidth: 4 + access: read-write + - name: XPD_SAR_FSM + bitOffset: 16 + bitWidth: 4 + access: read-write + - name: SAR_RSTB_FSM + bitOffset: 20 + bitWidth: 4 + access: read-write + - name: SAR2_XPD_WAIT + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: SAR_READ_STATUS2 + addressOffset: 20 + size: 32 + fields: + - name: SAR2_READER_STATUS + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: ULP_CP_SLEEP_CYC0 + addressOffset: 24 + size: 32 + resetValue: 200 + fields: + - name: SLEEP_CYCLES_S0 + description: sleep cycles for ULP-coprocessor timer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ULP_CP_SLEEP_CYC1 + addressOffset: 28 + size: 32 + resetValue: 100 + fields: + - name: SLEEP_CYCLES_S1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ULP_CP_SLEEP_CYC2 + addressOffset: 32 + size: 32 + resetValue: 50 + fields: + - name: SLEEP_CYCLES_S2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ULP_CP_SLEEP_CYC3 + addressOffset: 36 + size: 32 + resetValue: 40 + fields: + - name: SLEEP_CYCLES_S3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ULP_CP_SLEEP_CYC4 + addressOffset: 40 + size: 32 + resetValue: 20 + fields: + - name: SLEEP_CYCLES_S4 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SAR_START_FORCE + addressOffset: 44 + size: 32 + resetValue: 15 + fields: + - name: SAR1_BIT_WIDTH + description: "00: 9 bit 01: 10 bits 10: 11bits 11: 12bits" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SAR2_BIT_WIDTH + description: "00: 9 bit 01: 10 bits 10: 11bits 11: 12bits" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: SAR2_EN_TEST + description: SAR2_EN_TEST only active when reg_sar2_dig_force = 0 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SAR2_PWDET_CCT + description: SAR2_PWDET_CCT PA power detector capacitance tuning. + bitOffset: 5 + bitWidth: 3 + access: read-write + - name: ULP_CP_FORCE_START_TOP + description: "1: ULP-coprocessor is started by SW 0: ULP-coprocessor is started by timer" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ULP_CP_START_TOP + description: Write 1 to start ULP-coprocessor only active when reg_ulp_cp_force_start_top = 1 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SARCLK_EN + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: PC_INIT + description: initialized PC for ULP-coprocessor + bitOffset: 11 + bitWidth: 11 + access: read-write + - name: SAR2_STOP + description: stop SAR ADC2 conversion + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SAR1_STOP + description: stop SAR ADC1 conversion + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SAR2_PWDET_EN + description: N/A + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: SAR_MEM_WR_CTRL + addressOffset: 48 + size: 32 + resetValue: 1049088 + fields: + - name: MEM_WR_ADDR_INIT + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: MEM_WR_ADDR_SIZE + bitOffset: 11 + bitWidth: 11 + access: read-write + - name: RTC_MEM_WR_OFFST_CLR + bitOffset: 22 + bitWidth: 1 + access: write-only + - register: + name: SAR_ATTEN1 + addressOffset: 52 + size: 32 + resetValue: 4294967295 + fields: + - name: SAR1_ATTEN + description: "2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SAR_ATTEN2 + addressOffset: 56 + size: 32 + resetValue: 4294967295 + fields: + - name: SAR2_ATTEN + description: "2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SAR_SLAVE_ADDR1 + addressOffset: 60 + size: 32 + fields: + - name: I2C_SLAVE_ADDR1 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: I2C_SLAVE_ADDR0 + bitOffset: 11 + bitWidth: 11 + access: read-write + - name: MEAS_STATUS + bitOffset: 22 + bitWidth: 8 + access: read-only + - register: + name: SAR_SLAVE_ADDR2 + addressOffset: 64 + size: 32 + fields: + - name: I2C_SLAVE_ADDR3 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: I2C_SLAVE_ADDR2 + bitOffset: 11 + bitWidth: 11 + access: read-write + - register: + name: SAR_SLAVE_ADDR3 + addressOffset: 68 + size: 32 + fields: + - name: I2C_SLAVE_ADDR5 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: I2C_SLAVE_ADDR4 + bitOffset: 11 + bitWidth: 11 + access: read-write + - name: TSENS_OUT + description: temperature sensor data out + bitOffset: 22 + bitWidth: 8 + access: read-only + - name: TSENS_RDY_OUT + description: indicate temperature sensor out ready + bitOffset: 30 + bitWidth: 1 + access: read-only + - register: + name: SAR_SLAVE_ADDR4 + addressOffset: 72 + size: 32 + fields: + - name: I2C_SLAVE_ADDR7 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: I2C_SLAVE_ADDR6 + bitOffset: 11 + bitWidth: 11 + access: read-write + - name: I2C_RDATA + description: I2C read data + bitOffset: 22 + bitWidth: 8 + access: read-only + - name: I2C_DONE + description: indicate I2C done + bitOffset: 30 + bitWidth: 1 + access: read-only + - register: + name: SAR_TSENS_CTRL + addressOffset: 76 + size: 32 + resetValue: 417794 + fields: + - name: TSENS_XPD_WAIT + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: TSENS_XPD_FORCE + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TSENS_CLK_INV + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TSENS_CLK_GATED + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TSENS_IN_INV + description: invert temperature sensor data + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TSENS_CLK_DIV + description: temperature sensor clock divider + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: TSENS_POWER_UP + description: temperature sensor power up + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TSENS_POWER_UP_FORCE + description: "1: dump out & power up controlled by SW 0: by FSM" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TSENS_DUMP_OUT + description: temperature sensor dump out only active when reg_tsens_power_up_force = 1 + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: SAR_I2C_CTRL + addressOffset: 80 + size: 32 + fields: + - name: SAR_I2C_CTRL + description: I2C control data only active when reg_sar_i2c_start_force = 1 + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SAR_I2C_START + description: start I2C only active when reg_sar_i2c_start_force = 1 + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SAR_I2C_START_FORCE + description: "1: I2C started by SW 0: I2C started by FSM" + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: SAR_MEAS_START1 + addressOffset: 84 + size: 32 + fields: + - name: MEAS1_DATA_SAR + description: SAR ADC1 data + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: MEAS1_DONE_SAR + description: SAR ADC1 conversion done indication + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: MEAS1_START_SAR + description: SAR ADC1 controller (in RTC) starts conversion only active when reg_meas1_start_force = 1 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MEAS1_START_FORCE + description: "1: SAR ADC1 controller (in RTC) is started by SW 0: SAR ADC1 controller is started by ULP-coprocessor" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SAR1_EN_PAD + description: SAR ADC1 pad enable bitmap only active when reg_sar1_en_pad_force = 1 + bitOffset: 19 + bitWidth: 12 + access: read-write + - name: SAR1_EN_PAD_FORCE + description: "1: SAR ADC1 pad enable bitmap is controlled by SW 0: SAR ADC1 pad enable bitmap is controlled by ULP-coprocessor" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAR_TOUCH_CTRL1 + addressOffset: 88 + size: 32 + resetValue: 33820672 + fields: + - name: TOUCH_MEAS_DELAY + description: the meas length (in 8MHz) + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: TOUCH_XPD_WAIT + description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: TOUCH_OUT_SEL + description: "1: when the counter is greater then the threshold the touch pad is considered as \"touched\" 0: when the counter is less than the threshold the touch pad is considered as \"touched\"" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TOUCH_OUT_1EN + description: "1: wakeup interrupt is generated if SET1 is \"touched\" 0: wakeup interrupt is generated only if SET1 & SET2 is both \"touched\"" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: XPD_HALL_FORCE + description: "1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HALL_PHASE_FORCE + description: "1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor" + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: SAR_TOUCH_THRES1 + addressOffset: 92 + size: 32 + fields: + - name: TOUCH_OUT_TH1 + description: the threshold for touch pad 1 + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: TOUCH_OUT_TH0 + description: the threshold for touch pad 0 + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SAR_TOUCH_THRES2 + addressOffset: 96 + size: 32 + fields: + - name: TOUCH_OUT_TH3 + description: the threshold for touch pad 3 + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: TOUCH_OUT_TH2 + description: the threshold for touch pad 2 + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SAR_TOUCH_THRES3 + addressOffset: 100 + size: 32 + fields: + - name: TOUCH_OUT_TH5 + description: the threshold for touch pad 5 + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: TOUCH_OUT_TH4 + description: the threshold for touch pad 4 + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SAR_TOUCH_THRES4 + addressOffset: 104 + size: 32 + fields: + - name: TOUCH_OUT_TH7 + description: the threshold for touch pad 7 + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: TOUCH_OUT_TH6 + description: the threshold for touch pad 6 + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SAR_TOUCH_THRES5 + addressOffset: 108 + size: 32 + fields: + - name: TOUCH_OUT_TH9 + description: the threshold for touch pad 9 + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: TOUCH_OUT_TH8 + description: the threshold for touch pad 8 + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SAR_TOUCH_OUT1 + addressOffset: 112 + size: 32 + fields: + - name: TOUCH_MEAS_OUT1 + description: the counter for touch pad 1 + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: TOUCH_MEAS_OUT0 + description: the counter for touch pad 0 + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: SAR_TOUCH_OUT2 + addressOffset: 116 + size: 32 + fields: + - name: TOUCH_MEAS_OUT3 + description: the counter for touch pad 3 + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: TOUCH_MEAS_OUT2 + description: the counter for touch pad 2 + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: SAR_TOUCH_OUT3 + addressOffset: 120 + size: 32 + fields: + - name: TOUCH_MEAS_OUT5 + description: the counter for touch pad 5 + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: TOUCH_MEAS_OUT4 + description: the counter for touch pad 4 + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: SAR_TOUCH_OUT4 + addressOffset: 124 + size: 32 + fields: + - name: TOUCH_MEAS_OUT7 + description: the counter for touch pad 7 + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: TOUCH_MEAS_OUT6 + description: the counter for touch pad 6 + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: SAR_TOUCH_OUT5 + addressOffset: 128 + size: 32 + fields: + - name: TOUCH_MEAS_OUT9 + description: the counter for touch pad 9 + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: TOUCH_MEAS_OUT8 + description: the counter for touch pad 8 + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: SAR_TOUCH_CTRL2 + addressOffset: 132 + size: 32 + resetValue: 4196352 + fields: + - name: TOUCH_MEAS_EN + description: "10-bit register to indicate which pads are \"touched\"" + bitOffset: 0 + bitWidth: 10 + access: read-only + - name: TOUCH_MEAS_DONE + description: fsm set 1 to indicate touch touch meas is done + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: TOUCH_START_FSM_EN + description: "1: TOUCH_START & TOUCH_XPD is controlled by touch fsm 0: TOUCH_START & TOUCH_XPD is controlled by registers" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TOUCH_START_EN + description: "1: start touch fsm valid when reg_touch_start_force is set" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TOUCH_START_FORCE + description: "1: to start touch fsm by SW 0: to start touch fsm by timer" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TOUCH_SLEEP_CYCLES + description: sleep cycles for timer + bitOffset: 14 + bitWidth: 16 + access: read-write + - name: TOUCH_MEAS_EN_CLR + description: to clear reg_touch_meas_en + bitOffset: 30 + bitWidth: 1 + access: write-only + - register: + name: SAR_TOUCH_ENABLE + addressOffset: 140 + size: 32 + resetValue: 1073741823 + fields: + - name: TOUCH_PAD_WORKEN + description: Bitmap defining the working set during the measurement. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: TOUCH_PAD_OUTEN2 + description: "Bitmap defining SET2 for generating wakeup interrupt. SET2 is \"touched\" only if at least one of touch pad in SET2 is \"touched\"." + bitOffset: 10 + bitWidth: 10 + access: read-write + - name: TOUCH_PAD_OUTEN1 + description: "Bitmap defining SET1 for generating wakeup interrupt. SET1 is \"touched\" only if at least one of touch pad in SET1 is \"touched\"." + bitOffset: 20 + bitWidth: 10 + access: read-write + - register: + name: SAR_READ_CTRL2 + addressOffset: 144 + size: 32 + resetValue: 461058 + fields: + - name: SAR2_CLK_DIV + description: clock divider + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SAR2_SAMPLE_CYCLE + description: sample cycles for SAR ADC2 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SAR2_SAMPLE_BIT + description: "00: for 9-bit width 01: for 10-bit width 10: for 11-bit width 11: for 12-bit width" + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: SAR2_CLK_GATED + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SAR2_SAMPLE_NUM + bitOffset: 19 + bitWidth: 8 + access: read-write + - name: SAR2_PWDET_FORCE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SAR2_DIG_FORCE + description: "1: SAR ADC2 controlled by DIG ADC2 CTRL or PWDET CTRL 0: SAR ADC2 controlled by RTC ADC2 CTRL" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SAR2_DATA_INV + description: Invert SAR ADC2 data + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: SAR_MEAS_START2 + addressOffset: 148 + size: 32 + fields: + - name: MEAS2_DATA_SAR + description: SAR ADC2 data + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: MEAS2_DONE_SAR + description: SAR ADC2 conversion done indication + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: MEAS2_START_SAR + description: SAR ADC2 controller (in RTC) starts conversion only active when reg_meas2_start_force = 1 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MEAS2_START_FORCE + description: "1: SAR ADC2 controller (in RTC) is started by SW 0: SAR ADC2 controller is started by ULP-coprocessor" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SAR2_EN_PAD + description: SAR ADC2 pad enable bitmap only active when reg_sar2_en_pad_force = 1 + bitOffset: 19 + bitWidth: 12 + access: read-write + - name: SAR2_EN_PAD_FORCE + description: "1: SAR ADC2 pad enable bitmap is controlled by SW 0: SAR ADC2 pad enable bitmap is controlled by ULP-coprocessor" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAR_DAC_CTRL1 + addressOffset: 152 + size: 32 + fields: + - name: SW_FSTEP + description: frequency step for CW generator can be used to adjust the frequency + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SW_TONE_EN + description: "1: enable CW generator 0: disable CW generator" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DEBUG_BIT_SEL + bitOffset: 17 + bitWidth: 5 + access: read-write + - name: DAC_DIG_FORCE + description: "1: DAC1 & DAC2 use DMA 0: DAC1 & DAC2 do not use DMA" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: DAC_CLK_FORCE_LOW + description: "1: force PDAC_CLK to low" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: DAC_CLK_FORCE_HIGH + description: "1: force PDAC_CLK to high" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: DAC_CLK_INV + description: "1: invert PDAC_CLK" + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: SAR_DAC_CTRL2 + addressOffset: 156 + size: 32 + resetValue: 50331648 + fields: + - name: DAC_DC1 + description: DC offset for DAC1 CW generator + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: DAC_DC2 + description: DC offset for DAC2 CW generator + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: DAC_SCALE1 + description: "00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8" + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DAC_SCALE2 + description: "00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8" + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DAC_INV1 + description: "00: do not invert any bits 01: invert all bits 10: invert MSB 11: invert all bits except MSB" + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DAC_INV2 + description: "00: do not invert any bits 01: invert all bits 10: invert MSB 11: invert all bits except MSB" + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: DAC_CW_EN1 + description: "1: to select CW generator as source to PDAC1_DAC[7:0] 0: to select register reg_pdac1_dac[7:0] as source to PDAC1_DAC[7:0]" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: DAC_CW_EN2 + description: "1: to select CW generator as source to PDAC2_DAC[7:0] 0: to select register reg_pdac2_dac[7:0] as source to PDAC2_DAC[7:0]" + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: SAR_MEAS_CTRL2 + addressOffset: 160 + size: 32 + resetValue: 3 + fields: + - name: SAR1_DAC_XPD_FSM + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: SAR1_DAC_XPD_FSM_IDLE + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: XPD_SAR_AMP_FSM_IDLE + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: AMP_RST_FB_FSM_IDLE + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: AMP_SHORT_REF_FSM_IDLE + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: AMP_SHORT_REF_GND_FSM_IDLE + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: XPD_SAR_FSM_IDLE + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SAR_RSTB_FSM_IDLE + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SAR2_RSTB_FORCE + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: AMP_RST_FB_FORCE + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: AMP_SHORT_REF_FORCE + bitOffset: 15 + bitWidth: 2 + access: read-write + - name: AMP_SHORT_REF_GND_FORCE + bitOffset: 17 + bitWidth: 2 + access: read-write + - register: + name: SAR_NOUSE + addressOffset: 248 + size: 32 + fields: + - name: SAR_NOUSE + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SARDATE + addressOffset: 252 + size: 32 + resetValue: 23089536 + fields: + - name: SAR_DATE + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SHA + description: SHA (Secure Hash Algorithm) Accelerator + groupName: SHA + baseAddress: 1072705536 + addressBlock: + - offset: 0 + size: 192 + usage: registers + registers: + - register: + dim: 32 + dimIncrement: 4 + name: TEXT%s + addressOffset: 0 + size: 32 + fields: + - name: TEXT + description: SHA Message block and hash result register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SHA1_START + addressOffset: 128 + size: 32 + fields: + - name: SHA1_START + description: Write 1 to start an SHA-1 operation on the first message block. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SHA1_CONTINUE + addressOffset: 132 + size: 32 + fields: + - name: SHA1_CONTINUE + description: Write 1 to continue the SHA-1 operation with subsequent blocks. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SHA1_LOAD + addressOffset: 136 + size: 32 + fields: + - name: SHA1_LOAD + description: Write 1 to finish the SHA-1 operation to calculate the final message hash. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SHA1_BUSY + addressOffset: 140 + size: 32 + fields: + - name: SHA1_BUSY + description: "SHA-1 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: SHA256_START + addressOffset: 144 + size: 32 + fields: + - name: SHA256_START + description: Write 1 to start an SHA-256 operation on the first message block. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SHA256_LOAD + addressOffset: 152 + size: 32 + fields: + - name: SHA256_LOAD + description: Write 1 to finish the SHA-256 operation to calculate the final message hash. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SHA256_CONTINUE + addressOffset: 148 + size: 32 + fields: + - name: SHA256_CONTINUE + description: Write 1 to continue the SHA-256 operation with subsequent blocks. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SHA256_BUSY + addressOffset: 156 + size: 32 + fields: + - name: SHA256_BUSY + description: "SHA-256 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: SHA384_START + addressOffset: 160 + size: 32 + fields: + - name: SHA384_START + description: Write 1 to start an SHA-384 operation on the first message block. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SHA384_CONTINUE + addressOffset: 164 + size: 32 + fields: + - name: SHA384_CONTINUE + description: Write 1 to continue the SHA-384 operation with subsequent blocks. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SHA384_LOAD + addressOffset: 168 + size: 32 + fields: + - name: SHA384_LOAD + description: Write 1 to finish the SHA-384 operation to calculate the final message hash. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SHA384_BUSY + addressOffset: 172 + size: 32 + fields: + - name: SHA384_BUSY + description: "SHA-384 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: SHA512_START + addressOffset: 176 + size: 32 + fields: + - name: SHA512_START + description: Write 1 to start an SHA-512 operation on the first message block. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SHA512_CONTINUE + addressOffset: 180 + size: 32 + fields: + - name: SHA512_CONTINUE + description: Write 1 to continue the SHA-512 operation with subsequent blocks. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SHA512_LOAD + addressOffset: 184 + size: 32 + fields: + - name: SHA512_LOAD + description: Write 1 to finish the SHA-512 operation to calculate the final message hash. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SHA512_BUSY + addressOffset: 188 + size: 32 + fields: + - name: SHA512_BUSY + description: "SHA-512 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SLC + description: SLC Peripheral + groupName: SLC + baseAddress: 1073053696 + addressBlock: + - offset: 0 + size: 332 + usage: registers + registers: + - register: + name: CONF0 + addressOffset: 0 + size: 32 + resetValue: 4282187568 + fields: + - name: SLC0_TX_RST + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLC0_RX_RST + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AHBM_FIFO_RST + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: AHBM_RST + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLC0_TX_LOOP_TEST + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SLC0_RX_LOOP_TEST + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SLC0_RX_AUTO_WRBACK + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SLC0_RX_NO_RESTART_CLR + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SLC0_RXDSCR_BURST_EN + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLC0_RXDATA_BURST_EN + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLC0_RXLINK_AUTO_RET + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLC0_TXLINK_AUTO_RET + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SLC0_TXDSCR_BURST_EN + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SLC0_TXDATA_BURST_EN + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLC0_TOKEN_AUTO_CLR + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLC0_TOKEN_SEL + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLC1_TX_RST + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SLC1_RX_RST + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SLC0_WR_RETRY_MASK_EN + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SLC1_WR_RETRY_MASK_EN + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SLC1_TX_LOOP_TEST + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SLC1_RX_LOOP_TEST + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SLC1_RX_AUTO_WRBACK + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SLC1_RX_NO_RESTART_CLR + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SLC1_RXDSCR_BURST_EN + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SLC1_RXDATA_BURST_EN + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: SLC1_RXLINK_AUTO_RET + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SLC1_TXLINK_AUTO_RET + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SLC1_TXDSCR_BURST_EN + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SLC1_TXDATA_BURST_EN + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SLC1_TOKEN_AUTO_CLR + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SLC1_TOKEN_SEL + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: _0INT_RAW + addressOffset: 4 + size: 32 + fields: + - name: FRHOST_BIT0_INT_RAW + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT1_INT_RAW + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT2_INT_RAW + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT3_INT_RAW + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT4_INT_RAW + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT5_INT_RAW + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT6_INT_RAW + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT7_INT_RAW + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SLC0_RX_START_INT_RAW + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SLC0_TX_START_INT_RAW + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SLC0_RX_UDF_INT_RAW + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SLC0_TX_OVF_INT_RAW + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: SLC0_TOKEN0_1TO0_INT_RAW + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SLC0_TOKEN1_1TO0_INT_RAW + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SLC0_TX_DONE_INT_RAW + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SLC0_TX_SUC_EOF_INT_RAW + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLC0_RX_DONE_INT_RAW + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: SLC0_RX_EOF_INT_RAW + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: SLC0_TOHOST_INT_RAW + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: SLC0_TX_DSCR_ERR_INT_RAW + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: SLC0_RX_DSCR_ERR_INT_RAW + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SLC0_TX_DSCR_EMPTY_INT_RAW + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SLC0_HOST_RD_ACK_INT_RAW + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: SLC0_WR_RETRY_DONE_INT_RAW + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: SLC0_TX_ERR_EOF_INT_RAW + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: CMD_DTC_INT_RAW + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: SLC0_RX_QUICK_EOF_INT_RAW + bitOffset: 26 + bitWidth: 1 + access: read-only + - register: + name: _0INT_ST + addressOffset: 8 + size: 32 + fields: + - name: FRHOST_BIT0_INT_ST + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT1_INT_ST + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT2_INT_ST + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT3_INT_ST + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT4_INT_ST + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT5_INT_ST + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT6_INT_ST + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT7_INT_ST + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SLC0_RX_START_INT_ST + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SLC0_TX_START_INT_ST + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SLC0_RX_UDF_INT_ST + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SLC0_TX_OVF_INT_ST + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: SLC0_TOKEN0_1TO0_INT_ST + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SLC0_TOKEN1_1TO0_INT_ST + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SLC0_TX_DONE_INT_ST + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SLC0_TX_SUC_EOF_INT_ST + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLC0_RX_DONE_INT_ST + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: SLC0_RX_EOF_INT_ST + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: SLC0_TOHOST_INT_ST + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: SLC0_TX_DSCR_ERR_INT_ST + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: SLC0_RX_DSCR_ERR_INT_ST + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SLC0_TX_DSCR_EMPTY_INT_ST + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SLC0_HOST_RD_ACK_INT_ST + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: SLC0_WR_RETRY_DONE_INT_ST + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: SLC0_TX_ERR_EOF_INT_ST + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: CMD_DTC_INT_ST + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: SLC0_RX_QUICK_EOF_INT_ST + bitOffset: 26 + bitWidth: 1 + access: read-only + - register: + name: _0INT_ENA + addressOffset: 12 + size: 32 + fields: + - name: FRHOST_BIT0_INT_ENA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT1_INT_ENA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT2_INT_ENA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT3_INT_ENA + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT4_INT_ENA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT5_INT_ENA + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT6_INT_ENA + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT7_INT_ENA + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SLC0_RX_START_INT_ENA + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLC0_TX_START_INT_ENA + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLC0_RX_UDF_INT_ENA + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLC0_TX_OVF_INT_ENA + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SLC0_TOKEN0_1TO0_INT_ENA + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SLC0_TOKEN1_1TO0_INT_ENA + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLC0_TX_DONE_INT_ENA + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLC0_TX_SUC_EOF_INT_ENA + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLC0_RX_DONE_INT_ENA + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SLC0_RX_EOF_INT_ENA + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SLC0_TOHOST_INT_ENA + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SLC0_TX_DSCR_ERR_INT_ENA + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SLC0_RX_DSCR_ERR_INT_ENA + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SLC0_TX_DSCR_EMPTY_INT_ENA + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SLC0_HOST_RD_ACK_INT_ENA + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SLC0_WR_RETRY_DONE_INT_ENA + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SLC0_TX_ERR_EOF_INT_ENA + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: CMD_DTC_INT_ENA + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: SLC0_RX_QUICK_EOF_INT_ENA + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: _0INT_CLR + addressOffset: 16 + size: 32 + fields: + - name: FRHOST_BIT0_INT_CLR + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: FRHOST_BIT1_INT_CLR + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: FRHOST_BIT2_INT_CLR + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: FRHOST_BIT3_INT_CLR + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: FRHOST_BIT4_INT_CLR + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: FRHOST_BIT5_INT_CLR + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: FRHOST_BIT6_INT_CLR + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: FRHOST_BIT7_INT_CLR + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SLC0_RX_START_INT_CLR + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SLC0_TX_START_INT_CLR + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SLC0_RX_UDF_INT_CLR + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SLC0_TX_OVF_INT_CLR + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: SLC0_TOKEN0_1TO0_INT_CLR + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: SLC0_TOKEN1_1TO0_INT_CLR + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SLC0_TX_DONE_INT_CLR + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SLC0_TX_SUC_EOF_INT_CLR + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: SLC0_RX_DONE_INT_CLR + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: SLC0_RX_EOF_INT_CLR + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: SLC0_TOHOST_INT_CLR + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: SLC0_TX_DSCR_ERR_INT_CLR + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: SLC0_RX_DSCR_ERR_INT_CLR + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: SLC0_TX_DSCR_EMPTY_INT_CLR + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: SLC0_HOST_RD_ACK_INT_CLR + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: SLC0_WR_RETRY_DONE_INT_CLR + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: SLC0_TX_ERR_EOF_INT_CLR + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: CMD_DTC_INT_CLR + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: SLC0_RX_QUICK_EOF_INT_CLR + bitOffset: 26 + bitWidth: 1 + access: write-only + - register: + name: _1INT_RAW + addressOffset: 20 + size: 32 + fields: + - name: FRHOST_BIT8_INT_RAW + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT9_INT_RAW + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT10_INT_RAW + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT11_INT_RAW + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT12_INT_RAW + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT13_INT_RAW + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT14_INT_RAW + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT15_INT_RAW + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SLC1_RX_START_INT_RAW + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SLC1_TX_START_INT_RAW + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SLC1_RX_UDF_INT_RAW + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SLC1_TX_OVF_INT_RAW + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: SLC1_TOKEN0_1TO0_INT_RAW + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SLC1_TOKEN1_1TO0_INT_RAW + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SLC1_TX_DONE_INT_RAW + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SLC1_TX_SUC_EOF_INT_RAW + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLC1_RX_DONE_INT_RAW + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: SLC1_RX_EOF_INT_RAW + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: SLC1_TOHOST_INT_RAW + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: SLC1_TX_DSCR_ERR_INT_RAW + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: SLC1_RX_DSCR_ERR_INT_RAW + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SLC1_TX_DSCR_EMPTY_INT_RAW + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SLC1_HOST_RD_ACK_INT_RAW + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: SLC1_WR_RETRY_DONE_INT_RAW + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: SLC1_TX_ERR_EOF_INT_RAW + bitOffset: 24 + bitWidth: 1 + access: read-only + - register: + name: _1INT_ST + addressOffset: 24 + size: 32 + fields: + - name: FRHOST_BIT8_INT_ST + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT9_INT_ST + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT10_INT_ST + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT11_INT_ST + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT12_INT_ST + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT13_INT_ST + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT14_INT_ST + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT15_INT_ST + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SLC1_RX_START_INT_ST + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SLC1_TX_START_INT_ST + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SLC1_RX_UDF_INT_ST + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SLC1_TX_OVF_INT_ST + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: SLC1_TOKEN0_1TO0_INT_ST + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SLC1_TOKEN1_1TO0_INT_ST + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SLC1_TX_DONE_INT_ST + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SLC1_TX_SUC_EOF_INT_ST + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLC1_RX_DONE_INT_ST + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: SLC1_RX_EOF_INT_ST + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: SLC1_TOHOST_INT_ST + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: SLC1_TX_DSCR_ERR_INT_ST + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: SLC1_RX_DSCR_ERR_INT_ST + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SLC1_TX_DSCR_EMPTY_INT_ST + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SLC1_HOST_RD_ACK_INT_ST + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: SLC1_WR_RETRY_DONE_INT_ST + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: SLC1_TX_ERR_EOF_INT_ST + bitOffset: 24 + bitWidth: 1 + access: read-only + - register: + name: _1INT_ENA + addressOffset: 28 + size: 32 + fields: + - name: FRHOST_BIT8_INT_ENA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT9_INT_ENA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT10_INT_ENA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT11_INT_ENA + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT12_INT_ENA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT13_INT_ENA + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT14_INT_ENA + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT15_INT_ENA + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SLC1_RX_START_INT_ENA + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLC1_TX_START_INT_ENA + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLC1_RX_UDF_INT_ENA + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLC1_TX_OVF_INT_ENA + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SLC1_TOKEN0_1TO0_INT_ENA + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SLC1_TOKEN1_1TO0_INT_ENA + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLC1_TX_DONE_INT_ENA + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLC1_TX_SUC_EOF_INT_ENA + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLC1_RX_DONE_INT_ENA + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SLC1_RX_EOF_INT_ENA + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SLC1_TOHOST_INT_ENA + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SLC1_TX_DSCR_ERR_INT_ENA + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SLC1_RX_DSCR_ERR_INT_ENA + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SLC1_TX_DSCR_EMPTY_INT_ENA + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SLC1_HOST_RD_ACK_INT_ENA + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SLC1_WR_RETRY_DONE_INT_ENA + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SLC1_TX_ERR_EOF_INT_ENA + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: _1INT_CLR + addressOffset: 32 + size: 32 + fields: + - name: FRHOST_BIT8_INT_CLR + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: FRHOST_BIT9_INT_CLR + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: FRHOST_BIT10_INT_CLR + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: FRHOST_BIT11_INT_CLR + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: FRHOST_BIT12_INT_CLR + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: FRHOST_BIT13_INT_CLR + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: FRHOST_BIT14_INT_CLR + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: FRHOST_BIT15_INT_CLR + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SLC1_RX_START_INT_CLR + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SLC1_TX_START_INT_CLR + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SLC1_RX_UDF_INT_CLR + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SLC1_TX_OVF_INT_CLR + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: SLC1_TOKEN0_1TO0_INT_CLR + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: SLC1_TOKEN1_1TO0_INT_CLR + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SLC1_TX_DONE_INT_CLR + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SLC1_TX_SUC_EOF_INT_CLR + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: SLC1_RX_DONE_INT_CLR + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: SLC1_RX_EOF_INT_CLR + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: SLC1_TOHOST_INT_CLR + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: SLC1_TX_DSCR_ERR_INT_CLR + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: SLC1_RX_DSCR_ERR_INT_CLR + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: SLC1_TX_DSCR_EMPTY_INT_CLR + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: SLC1_HOST_RD_ACK_INT_CLR + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: SLC1_WR_RETRY_DONE_INT_CLR + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: SLC1_TX_ERR_EOF_INT_CLR + bitOffset: 24 + bitWidth: 1 + access: write-only + - register: + name: RX_STATUS + addressOffset: 36 + size: 32 + resetValue: 131074 + fields: + - name: SLC0_RX_FULL + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SLC0_RX_EMPTY + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SLC1_RX_FULL + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: SLC1_RX_EMPTY + bitOffset: 17 + bitWidth: 1 + access: read-only + - register: + name: _0RXFIFO_PUSH + addressOffset: 40 + size: 32 + fields: + - name: SLC0_RXFIFO_WDATA + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: SLC0_RXFIFO_PUSH + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: _1RXFIFO_PUSH + addressOffset: 44 + size: 32 + fields: + - name: SLC1_RXFIFO_WDATA + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: SLC1_RXFIFO_PUSH + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: TX_STATUS + addressOffset: 48 + size: 32 + resetValue: 131074 + fields: + - name: SLC0_TX_FULL + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SLC0_TX_EMPTY + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SLC1_TX_FULL + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: SLC1_TX_EMPTY + bitOffset: 17 + bitWidth: 1 + access: read-only + - register: + name: _0TXFIFO_POP + addressOffset: 52 + size: 32 + fields: + - name: SLC0_TXFIFO_RDATA + bitOffset: 0 + bitWidth: 11 + access: read-only + - name: SLC0_TXFIFO_POP + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: _1TXFIFO_POP + addressOffset: 56 + size: 32 + fields: + - name: SLC1_TXFIFO_RDATA + bitOffset: 0 + bitWidth: 11 + access: read-only + - name: SLC1_TXFIFO_POP + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: _0RX_LINK + addressOffset: 60 + size: 32 + fields: + - name: SLC0_RXLINK_ADDR + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: SLC0_RXLINK_STOP + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SLC0_RXLINK_START + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SLC0_RXLINK_RESTART + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SLC0_RXLINK_PARK + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: _0TX_LINK + addressOffset: 64 + size: 32 + fields: + - name: SLC0_TXLINK_ADDR + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: SLC0_TXLINK_STOP + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SLC0_TXLINK_START + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SLC0_TXLINK_RESTART + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SLC0_TXLINK_PARK + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: _1RX_LINK + addressOffset: 68 + size: 32 + resetValue: 1048576 + fields: + - name: SLC1_RXLINK_ADDR + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: SLC1_BT_PACKET + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SLC1_RXLINK_STOP + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SLC1_RXLINK_START + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SLC1_RXLINK_RESTART + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SLC1_RXLINK_PARK + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: _1TX_LINK + addressOffset: 72 + size: 32 + fields: + - name: SLC1_TXLINK_ADDR + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: SLC1_TXLINK_STOP + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SLC1_TXLINK_START + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SLC1_TXLINK_RESTART + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SLC1_TXLINK_PARK + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INTVEC_TOHOST + addressOffset: 76 + size: 32 + fields: + - name: SLC0_TOHOST_INTVEC + bitOffset: 0 + bitWidth: 8 + access: write-only + - name: SLC1_TOHOST_INTVEC + bitOffset: 16 + bitWidth: 8 + access: write-only + - register: + name: _0TOKEN0 + addressOffset: 80 + size: 32 + fields: + - name: SLC0_TOKEN0_WDATA + bitOffset: 0 + bitWidth: 12 + access: write-only + - name: SLC0_TOKEN0_WR + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: SLC0_TOKEN0_INC + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SLC0_TOKEN0_INC_MORE + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SLC0_TOKEN0 + bitOffset: 16 + bitWidth: 12 + access: read-only + - register: + name: _0TOKEN1 + addressOffset: 84 + size: 32 + fields: + - name: SLC0_TOKEN1_WDATA + bitOffset: 0 + bitWidth: 12 + access: write-only + - name: SLC0_TOKEN1_WR + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: SLC0_TOKEN1_INC + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SLC0_TOKEN1_INC_MORE + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SLC0_TOKEN1 + bitOffset: 16 + bitWidth: 12 + access: read-only + - register: + name: _1TOKEN0 + addressOffset: 88 + size: 32 + fields: + - name: SLC1_TOKEN0_WDATA + bitOffset: 0 + bitWidth: 12 + access: write-only + - name: SLC1_TOKEN0_WR + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: SLC1_TOKEN0_INC + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SLC1_TOKEN0_INC_MORE + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SLC1_TOKEN0 + bitOffset: 16 + bitWidth: 12 + access: read-only + - register: + name: _1TOKEN1 + addressOffset: 92 + size: 32 + fields: + - name: SLC1_TOKEN1_WDATA + bitOffset: 0 + bitWidth: 12 + access: write-only + - name: SLC1_TOKEN1_WR + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: SLC1_TOKEN1_INC + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SLC1_TOKEN1_INC_MORE + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SLC1_TOKEN1 + bitOffset: 16 + bitWidth: 12 + access: read-only + - register: + name: CONF1 + addressOffset: 96 + size: 32 + resetValue: 3145848 + fields: + - name: SLC0_CHECK_OWNER + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLC0_TX_CHECK_SUM_EN + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SLC0_RX_CHECK_SUM_EN + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CMD_HOLD_EN + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLC0_LEN_AUTO_CLR + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SLC0_TX_STITCH_EN + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SLC0_RX_STITCH_EN + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SLC1_CHECK_OWNER + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SLC1_TX_CHECK_SUM_EN + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SLC1_RX_CHECK_SUM_EN + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: HOST_INT_LEVEL_SEL + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SLC1_TX_STITCH_EN + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SLC1_RX_STITCH_EN + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CLK_EN + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: _0_STATE0 + addressOffset: 100 + size: 32 + fields: + - name: SLC0_STATE0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _0_STATE1 + addressOffset: 104 + size: 32 + fields: + - name: SLC0_STATE1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _1_STATE0 + addressOffset: 108 + size: 32 + fields: + - name: SLC1_STATE0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _1_STATE1 + addressOffset: 112 + size: 32 + fields: + - name: SLC1_STATE1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BRIDGE_CONF + addressOffset: 116 + size: 32 + resetValue: 685856 + fields: + - name: TXEOF_ENA + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: FIFO_MAP_ENA + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: SLC0_TX_DUMMY_MODE + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: HDA_MAP_128K + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLC1_TX_DUMMY_MODE + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TX_PUSH_IDLE_NUM + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: _0_TO_EOF_DES_ADDR + addressOffset: 120 + size: 32 + fields: + - name: SLC0_TO_EOF_DES_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _0_TX_EOF_DES_ADDR + addressOffset: 124 + size: 32 + fields: + - name: SLC0_TX_SUC_EOF_DES_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _0_TO_EOF_BFR_DES_ADDR + addressOffset: 128 + size: 32 + fields: + - name: SLC0_TO_EOF_BFR_DES_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _1_TO_EOF_DES_ADDR + addressOffset: 132 + size: 32 + fields: + - name: SLC1_TO_EOF_DES_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _1_TX_EOF_DES_ADDR + addressOffset: 136 + size: 32 + fields: + - name: SLC1_TX_SUC_EOF_DES_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _1_TO_EOF_BFR_DES_ADDR + addressOffset: 140 + size: 32 + fields: + - name: SLC1_TO_EOF_BFR_DES_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: AHB_TEST + addressOffset: 144 + size: 32 + fields: + - name: AHB_TESTMODE + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: AHB_TESTADDR + bitOffset: 4 + bitWidth: 2 + access: read-write + - register: + name: SDIO_ST + addressOffset: 148 + size: 32 + fields: + - name: CMD_ST + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: FUNC_ST + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: SDIO_WAKEUP + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: BUS_ST + bitOffset: 12 + bitWidth: 3 + access: read-only + - name: FUNC1_ACC_STATE + bitOffset: 16 + bitWidth: 5 + access: read-only + - name: FUNC2_ACC_STATE + bitOffset: 24 + bitWidth: 5 + access: read-only + - register: + name: RX_DSCR_CONF + addressOffset: 152 + size: 32 + resetValue: 270209050 + fields: + - name: SLC0_TOKEN_NO_REPLACE + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLC0_INFOR_NO_REPLACE + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SLC0_RX_FILL_MODE + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLC0_RX_EOF_MODE + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLC0_RX_FILL_EN + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SLC0_RD_RETRY_THRESHOLD + bitOffset: 5 + bitWidth: 11 + access: read-write + - name: SLC1_TOKEN_NO_REPLACE + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SLC1_INFOR_NO_REPLACE + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SLC1_RX_FILL_MODE + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SLC1_RX_EOF_MODE + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SLC1_RX_FILL_EN + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SLC1_RD_RETRY_THRESHOLD + bitOffset: 21 + bitWidth: 11 + access: read-write + - register: + name: _0_TXLINK_DSCR + addressOffset: 156 + size: 32 + fields: + - name: SLC0_TXLINK_DSCR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _0_TXLINK_DSCR_BF0 + addressOffset: 160 + size: 32 + fields: + - name: SLC0_TXLINK_DSCR_BF0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _0_TXLINK_DSCR_BF1 + addressOffset: 164 + size: 32 + fields: + - name: SLC0_TXLINK_DSCR_BF1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _0_RXLINK_DSCR + addressOffset: 168 + size: 32 + fields: + - name: SLC0_RXLINK_DSCR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _0_RXLINK_DSCR_BF0 + addressOffset: 172 + size: 32 + fields: + - name: SLC0_RXLINK_DSCR_BF0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _0_RXLINK_DSCR_BF1 + addressOffset: 176 + size: 32 + fields: + - name: SLC0_RXLINK_DSCR_BF1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _1_TXLINK_DSCR + addressOffset: 180 + size: 32 + fields: + - name: SLC1_TXLINK_DSCR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _1_TXLINK_DSCR_BF0 + addressOffset: 184 + size: 32 + fields: + - name: SLC1_TXLINK_DSCR_BF0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _1_TXLINK_DSCR_BF1 + addressOffset: 188 + size: 32 + fields: + - name: SLC1_TXLINK_DSCR_BF1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _1_RXLINK_DSCR + addressOffset: 192 + size: 32 + fields: + - name: SLC1_RXLINK_DSCR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _1_RXLINK_DSCR_BF0 + addressOffset: 196 + size: 32 + fields: + - name: SLC1_RXLINK_DSCR_BF0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _1_RXLINK_DSCR_BF1 + addressOffset: 200 + size: 32 + fields: + - name: SLC1_RXLINK_DSCR_BF1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _0_TX_ERREOF_DES_ADDR + addressOffset: 204 + size: 32 + fields: + - name: SLC0_TX_ERR_EOF_DES_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _1_TX_ERREOF_DES_ADDR + addressOffset: 208 + size: 32 + fields: + - name: SLC1_TX_ERR_EOF_DES_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: TOKEN_LAT + addressOffset: 212 + size: 32 + fields: + - name: SLC0_TOKEN + bitOffset: 0 + bitWidth: 12 + access: read-only + - name: SLC1_TOKEN + bitOffset: 16 + bitWidth: 12 + access: read-only + - register: + name: TX_DSCR_CONF + addressOffset: 216 + size: 32 + resetValue: 128 + fields: + - name: WR_RETRY_THRESHOLD + bitOffset: 0 + bitWidth: 11 + access: read-write + - register: + name: CMD_INFOR0 + addressOffset: 220 + size: 32 + fields: + - name: CMD_CONTENT0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CMD_INFOR1 + addressOffset: 224 + size: 32 + fields: + - name: CMD_CONTENT1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _0_LEN_CONF + addressOffset: 228 + size: 32 + fields: + - name: SLC0_LEN_WDATA + bitOffset: 0 + bitWidth: 20 + access: write-only + - name: SLC0_LEN_WR + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: SLC0_LEN_INC + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: SLC0_LEN_INC_MORE + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: SLC0_RX_PACKET_LOAD_EN + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SLC0_TX_PACKET_LOAD_EN + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SLC0_RX_GET_USED_DSCR + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: SLC0_TX_GET_USED_DSCR + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: SLC0_RX_NEW_PKT_IND + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: SLC0_TX_NEW_PKT_IND + bitOffset: 28 + bitWidth: 1 + access: read-only + - register: + name: _0_LENGTH + addressOffset: 232 + size: 32 + fields: + - name: SLC0_LEN + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: _0_TXPKT_H_DSCR + addressOffset: 236 + size: 32 + fields: + - name: SLC0_TX_PKT_H_DSCR_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: _0_TXPKT_E_DSCR + addressOffset: 240 + size: 32 + fields: + - name: SLC0_TX_PKT_E_DSCR_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: _0_RXPKT_H_DSCR + addressOffset: 244 + size: 32 + fields: + - name: SLC0_RX_PKT_H_DSCR_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: _0_RXPKT_E_DSCR + addressOffset: 248 + size: 32 + fields: + - name: SLC0_RX_PKT_E_DSCR_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: _0_TXPKTU_H_DSCR + addressOffset: 252 + size: 32 + fields: + - name: SLC0_TX_PKT_START_DSCR_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _0_TXPKTU_E_DSCR + addressOffset: 256 + size: 32 + fields: + - name: SLC0_TX_PKT_END_DSCR_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _0_RXPKTU_H_DSCR + addressOffset: 260 + size: 32 + fields: + - name: SLC0_RX_PKT_START_DSCR_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _0_RXPKTU_E_DSCR + addressOffset: 264 + size: 32 + fields: + - name: SLC0_RX_PKT_END_DSCR_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SEQ_POSITION + addressOffset: 276 + size: 32 + resetValue: 1289 + fields: + - name: SLC0_SEQ_POSITION + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SLC1_SEQ_POSITION + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: _0_DSCR_REC_CONF + addressOffset: 280 + size: 32 + resetValue: 1023 + fields: + - name: SLC0_RX_DSCR_REC_LIM + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: SDIO_CRC_ST0 + addressOffset: 284 + size: 32 + fields: + - name: DAT0_CRC_ERR_CNT + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: DAT1_CRC_ERR_CNT + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: DAT2_CRC_ERR_CNT + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: DAT3_CRC_ERR_CNT + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: SDIO_CRC_ST1 + addressOffset: 288 + size: 32 + fields: + - name: CMD_CRC_ERR_CNT + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: ERR_CNT_CLR + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: _0_EOF_START_DES + addressOffset: 292 + size: 32 + fields: + - name: SLC0_EOF_START_DES_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _0_PUSH_DSCR_ADDR + addressOffset: 296 + size: 32 + fields: + - name: SLC0_RX_PUSH_DSCR_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _0_DONE_DSCR_ADDR + addressOffset: 300 + size: 32 + fields: + - name: SLC0_RX_DONE_DSCR_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _0_SUB_START_DES + addressOffset: 304 + size: 32 + fields: + - name: SLC0_SUB_PAC_START_DSCR_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: _0_DSCR_CNT + addressOffset: 308 + size: 32 + fields: + - name: SLC0_RX_DSCR_CNT_LAT + bitOffset: 0 + bitWidth: 10 + access: read-only + - name: SLC0_RX_GET_EOF_OCC + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: _0_LEN_LIM_CONF + addressOffset: 312 + size: 32 + resetValue: 21504 + fields: + - name: SLC0_LEN_LIM + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: _0INT_ST1 + addressOffset: 316 + size: 32 + fields: + - name: FRHOST_BIT0_INT_ST1 + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT1_INT_ST1 + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT2_INT_ST1 + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT3_INT_ST1 + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT4_INT_ST1 + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT5_INT_ST1 + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT6_INT_ST1 + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT7_INT_ST1 + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SLC0_RX_START_INT_ST1 + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SLC0_TX_START_INT_ST1 + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SLC0_RX_UDF_INT_ST1 + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SLC0_TX_OVF_INT_ST1 + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: SLC0_TOKEN0_1TO0_INT_ST1 + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SLC0_TOKEN1_1TO0_INT_ST1 + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SLC0_TX_DONE_INT_ST1 + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SLC0_TX_SUC_EOF_INT_ST1 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLC0_RX_DONE_INT_ST1 + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: SLC0_RX_EOF_INT_ST1 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: SLC0_TOHOST_INT_ST1 + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: SLC0_TX_DSCR_ERR_INT_ST1 + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: SLC0_RX_DSCR_ERR_INT_ST1 + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SLC0_TX_DSCR_EMPTY_INT_ST1 + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SLC0_HOST_RD_ACK_INT_ST1 + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: SLC0_WR_RETRY_DONE_INT_ST1 + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: SLC0_TX_ERR_EOF_INT_ST1 + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: CMD_DTC_INT_ST1 + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: SLC0_RX_QUICK_EOF_INT_ST1 + bitOffset: 26 + bitWidth: 1 + access: read-only + - register: + name: _0INT_ENA1 + addressOffset: 320 + size: 32 + fields: + - name: FRHOST_BIT0_INT_ENA1 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT1_INT_ENA1 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT2_INT_ENA1 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT3_INT_ENA1 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT4_INT_ENA1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT5_INT_ENA1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT6_INT_ENA1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT7_INT_ENA1 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SLC0_RX_START_INT_ENA1 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLC0_TX_START_INT_ENA1 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLC0_RX_UDF_INT_ENA1 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLC0_TX_OVF_INT_ENA1 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SLC0_TOKEN0_1TO0_INT_ENA1 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SLC0_TOKEN1_1TO0_INT_ENA1 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLC0_TX_DONE_INT_ENA1 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLC0_TX_SUC_EOF_INT_ENA1 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLC0_RX_DONE_INT_ENA1 + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SLC0_RX_EOF_INT_ENA1 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SLC0_TOHOST_INT_ENA1 + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SLC0_TX_DSCR_ERR_INT_ENA1 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SLC0_RX_DSCR_ERR_INT_ENA1 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SLC0_TX_DSCR_EMPTY_INT_ENA1 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SLC0_HOST_RD_ACK_INT_ENA1 + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SLC0_WR_RETRY_DONE_INT_ENA1 + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SLC0_TX_ERR_EOF_INT_ENA1 + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: CMD_DTC_INT_ENA1 + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: SLC0_RX_QUICK_EOF_INT_ENA1 + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: _1INT_ST1 + addressOffset: 324 + size: 32 + fields: + - name: FRHOST_BIT8_INT_ST1 + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT9_INT_ST1 + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT10_INT_ST1 + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT11_INT_ST1 + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT12_INT_ST1 + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT13_INT_ST1 + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT14_INT_ST1 + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: FRHOST_BIT15_INT_ST1 + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SLC1_RX_START_INT_ST1 + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SLC1_TX_START_INT_ST1 + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SLC1_RX_UDF_INT_ST1 + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SLC1_TX_OVF_INT_ST1 + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: SLC1_TOKEN0_1TO0_INT_ST1 + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SLC1_TOKEN1_1TO0_INT_ST1 + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SLC1_TX_DONE_INT_ST1 + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SLC1_TX_SUC_EOF_INT_ST1 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLC1_RX_DONE_INT_ST1 + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: SLC1_RX_EOF_INT_ST1 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: SLC1_TOHOST_INT_ST1 + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: SLC1_TX_DSCR_ERR_INT_ST1 + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: SLC1_RX_DSCR_ERR_INT_ST1 + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SLC1_TX_DSCR_EMPTY_INT_ST1 + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SLC1_HOST_RD_ACK_INT_ST1 + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: SLC1_WR_RETRY_DONE_INT_ST1 + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: SLC1_TX_ERR_EOF_INT_ST1 + bitOffset: 24 + bitWidth: 1 + access: read-only + - register: + name: _1INT_ENA1 + addressOffset: 328 + size: 32 + fields: + - name: FRHOST_BIT8_INT_ENA1 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT9_INT_ENA1 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT10_INT_ENA1 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT11_INT_ENA1 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT12_INT_ENA1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT13_INT_ENA1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT14_INT_ENA1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FRHOST_BIT15_INT_ENA1 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SLC1_RX_START_INT_ENA1 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLC1_TX_START_INT_ENA1 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLC1_RX_UDF_INT_ENA1 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLC1_TX_OVF_INT_ENA1 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SLC1_TOKEN0_1TO0_INT_ENA1 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SLC1_TOKEN1_1TO0_INT_ENA1 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLC1_TX_DONE_INT_ENA1 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLC1_TX_SUC_EOF_INT_ENA1 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLC1_RX_DONE_INT_ENA1 + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SLC1_RX_EOF_INT_ENA1 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SLC1_TOHOST_INT_ENA1 + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SLC1_TX_DSCR_ERR_INT_ENA1 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SLC1_RX_DSCR_ERR_INT_ENA1 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SLC1_TX_DSCR_EMPTY_INT_ENA1 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SLC1_HOST_RD_ACK_INT_ENA1 + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SLC1_WR_RETRY_DONE_INT_ENA1 + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SLC1_TX_ERR_EOF_INT_ENA1 + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: DATE + addressOffset: 504 + size: 32 + resetValue: 369239296 + fields: + - name: DATE + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ID + addressOffset: 508 + size: 32 + resetValue: 256 + fields: + - name: ID + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: SLCHOST + description: SLCHOST Peripheral + groupName: SLCHOST + baseAddress: 1073041408 + addressBlock: + - offset: 0 + size: 260 + usage: registers + registers: + - register: + name: HOST_SLCHOST_FUNC2_0 + addressOffset: 16 + size: 32 + fields: + - name: HOST_SLC_FUNC2_INT + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: HOST_SLCHOST_FUNC2_1 + addressOffset: 20 + size: 32 + fields: + - name: HOST_SLC_FUNC2_INT_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: HOST_SLCHOST_FUNC2_2 + addressOffset: 32 + size: 32 + resetValue: 1 + fields: + - name: HOST_SLC_FUNC1_MDSTAT + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: HOST_SLCHOST_GPIO_STATUS0 + addressOffset: 52 + size: 32 + fields: + - name: HOST_GPIO_SDIO_INT0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HOST_SLCHOST_GPIO_STATUS1 + addressOffset: 56 + size: 32 + fields: + - name: HOST_GPIO_SDIO_INT1 + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: HOST_SLCHOST_GPIO_IN0 + addressOffset: 60 + size: 32 + fields: + - name: HOST_GPIO_SDIO_IN0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HOST_SLCHOST_GPIO_IN1 + addressOffset: 64 + size: 32 + fields: + - name: HOST_GPIO_SDIO_IN1 + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: HOST_SLC0HOST_TOKEN_RDATA + addressOffset: 68 + size: 32 + fields: + - name: HOST_SLC0_TOKEN0 + bitOffset: 0 + bitWidth: 12 + access: read-only + - name: HOST_SLC0_RX_PF_VALID + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: HOST_HOSTSLC0_TOKEN1 + bitOffset: 16 + bitWidth: 12 + access: read-only + - name: HOST_SLC0_RX_PF_EOF + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: HOST_SLC0_HOST_PF + addressOffset: 72 + size: 32 + fields: + - name: HOST_SLC0_PF_DATA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HOST_SLC1_HOST_PF + addressOffset: 76 + size: 32 + fields: + - name: HOST_SLC1_PF_DATA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HOST_SLC0HOST_INT_RAW + addressOffset: 80 + size: 32 + fields: + - name: HOST_SLC0_TOHOST_BIT0_INT_RAW + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_TOHOST_BIT1_INT_RAW + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_TOHOST_BIT2_INT_RAW + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_TOHOST_BIT3_INT_RAW + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_TOHOST_BIT4_INT_RAW + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_TOHOST_BIT5_INT_RAW + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_TOHOST_BIT6_INT_RAW + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_TOHOST_BIT7_INT_RAW + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_TOKEN0_1TO0_INT_RAW + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_TOKEN1_1TO0_INT_RAW + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_TOKEN0_0TO1_INT_RAW + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_TOKEN1_0TO1_INT_RAW + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: HOST_SLC0HOST_RX_SOF_INT_RAW + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: HOST_SLC0HOST_RX_EOF_INT_RAW + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: HOST_SLC0HOST_RX_START_INT_RAW + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: HOST_SLC0HOST_TX_START_INT_RAW + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_RX_UDF_INT_RAW + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_TX_OVF_INT_RAW + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_RX_PF_VALID_INT_RAW + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_EXT_BIT0_INT_RAW + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_EXT_BIT1_INT_RAW + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_EXT_BIT2_INT_RAW + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_EXT_BIT3_INT_RAW + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_RX_NEW_PACKET_INT_RAW + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_HOST_RD_RETRY_INT_RAW + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: HOST_GPIO_SDIO_INT_RAW + bitOffset: 25 + bitWidth: 1 + access: read-only + - register: + name: HOST_SLC1HOST_INT_RAW + addressOffset: 84 + size: 32 + fields: + - name: HOST_SLC1_TOHOST_BIT0_INT_RAW + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_TOHOST_BIT1_INT_RAW + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_TOHOST_BIT2_INT_RAW + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_TOHOST_BIT3_INT_RAW + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_TOHOST_BIT4_INT_RAW + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_TOHOST_BIT5_INT_RAW + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_TOHOST_BIT6_INT_RAW + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_TOHOST_BIT7_INT_RAW + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_TOKEN0_1TO0_INT_RAW + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_TOKEN1_1TO0_INT_RAW + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_TOKEN0_0TO1_INT_RAW + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_TOKEN1_0TO1_INT_RAW + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: HOST_SLC1HOST_RX_SOF_INT_RAW + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: HOST_SLC1HOST_RX_EOF_INT_RAW + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: HOST_SLC1HOST_RX_START_INT_RAW + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: HOST_SLC1HOST_TX_START_INT_RAW + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_RX_UDF_INT_RAW + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_TX_OVF_INT_RAW + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_RX_PF_VALID_INT_RAW + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_EXT_BIT0_INT_RAW + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_EXT_BIT1_INT_RAW + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_EXT_BIT2_INT_RAW + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_EXT_BIT3_INT_RAW + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_HOST_RD_RETRY_INT_RAW + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW + bitOffset: 25 + bitWidth: 1 + access: read-only + - register: + name: HOST_SLC0HOST_INT_ST + addressOffset: 88 + size: 32 + fields: + - name: HOST_SLC0_TOHOST_BIT0_INT_ST + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_TOHOST_BIT1_INT_ST + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_TOHOST_BIT2_INT_ST + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_TOHOST_BIT3_INT_ST + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_TOHOST_BIT4_INT_ST + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_TOHOST_BIT5_INT_ST + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_TOHOST_BIT6_INT_ST + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_TOHOST_BIT7_INT_ST + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_TOKEN0_1TO0_INT_ST + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_TOKEN1_1TO0_INT_ST + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_TOKEN0_0TO1_INT_ST + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_TOKEN1_0TO1_INT_ST + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: HOST_SLC0HOST_RX_SOF_INT_ST + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: HOST_SLC0HOST_RX_EOF_INT_ST + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: HOST_SLC0HOST_RX_START_INT_ST + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: HOST_SLC0HOST_TX_START_INT_ST + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_RX_UDF_INT_ST + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_TX_OVF_INT_ST + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_RX_PF_VALID_INT_ST + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_EXT_BIT0_INT_ST + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_EXT_BIT1_INT_ST + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_EXT_BIT2_INT_ST + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_EXT_BIT3_INT_ST + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_RX_NEW_PACKET_INT_ST + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: HOST_SLC0_HOST_RD_RETRY_INT_ST + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: HOST_GPIO_SDIO_INT_ST + bitOffset: 25 + bitWidth: 1 + access: read-only + - register: + name: HOST_SLC1HOST_INT_ST + addressOffset: 92 + size: 32 + fields: + - name: HOST_SLC1_TOHOST_BIT0_INT_ST + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_TOHOST_BIT1_INT_ST + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_TOHOST_BIT2_INT_ST + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_TOHOST_BIT3_INT_ST + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_TOHOST_BIT4_INT_ST + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_TOHOST_BIT5_INT_ST + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_TOHOST_BIT6_INT_ST + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_TOHOST_BIT7_INT_ST + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_TOKEN0_1TO0_INT_ST + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_TOKEN1_1TO0_INT_ST + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_TOKEN0_0TO1_INT_ST + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_TOKEN1_0TO1_INT_ST + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: HOST_SLC1HOST_RX_SOF_INT_ST + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: HOST_SLC1HOST_RX_EOF_INT_ST + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: HOST_SLC1HOST_RX_START_INT_ST + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: HOST_SLC1HOST_TX_START_INT_ST + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_RX_UDF_INT_ST + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_TX_OVF_INT_ST + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_RX_PF_VALID_INT_ST + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_EXT_BIT0_INT_ST + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_EXT_BIT1_INT_ST + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_EXT_BIT2_INT_ST + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_EXT_BIT3_INT_ST + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_HOST_RD_RETRY_INT_ST + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: HOST_SLC1_BT_RX_NEW_PACKET_INT_ST + bitOffset: 25 + bitWidth: 1 + access: read-only + - register: + name: HOST_SLCHOST_PKT_LEN + addressOffset: 96 + size: 32 + fields: + - name: HOST_HOSTSLC0_LEN + bitOffset: 0 + bitWidth: 20 + access: read-only + - name: HOST_HOSTSLC0_LEN_CHECK + bitOffset: 20 + bitWidth: 12 + access: read-only + - register: + name: HOST_SLCHOST_STATE_W0 + addressOffset: 100 + size: 32 + fields: + - name: HOST_SLCHOST_STATE0 + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: HOST_SLCHOST_STATE1 + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: HOST_SLCHOST_STATE2 + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: HOST_SLCHOST_STATE3 + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: HOST_SLCHOST_STATE_W1 + addressOffset: 104 + size: 32 + fields: + - name: HOST_SLCHOST_STATE4 + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: HOST_SLCHOST_STATE5 + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: HOST_SLCHOST_STATE6 + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: HOST_SLCHOST_STATE7 + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: HOST_SLCHOST_CONF_W0 + addressOffset: 108 + size: 32 + fields: + - name: HOST_SLCHOST_CONF0 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF1 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF2 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF3 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HOST_SLCHOST_CONF_W1 + addressOffset: 112 + size: 32 + fields: + - name: HOST_SLCHOST_CONF4 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF5 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF6 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF7 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HOST_SLCHOST_CONF_W2 + addressOffset: 116 + size: 32 + fields: + - name: HOST_SLCHOST_CONF8 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF9 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF10 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF11 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HOST_SLCHOST_CONF_W3 + addressOffset: 120 + size: 32 + resetValue: 192 + fields: + - name: HOST_SLCHOST_CONF12 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF13 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF14 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF15 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HOST_SLCHOST_CONF_W4 + addressOffset: 124 + size: 32 + resetValue: 511 + fields: + - name: HOST_SLCHOST_CONF16 + description: SLC timeout value + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF17 + description: SLC timeout enable + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF18 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF19 + description: Interrupt to target CPU + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HOST_SLCHOST_CONF_W5 + addressOffset: 128 + size: 32 + fields: + - name: HOST_SLCHOST_CONF20 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF21 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF22 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF23 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HOST_SLCHOST_WIN_CMD + addressOffset: 132 + size: 32 + - register: + name: HOST_SLCHOST_CONF_W6 + addressOffset: 136 + size: 32 + fields: + - name: HOST_SLCHOST_CONF24 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF25 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF26 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF27 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HOST_SLCHOST_CONF_W7 + addressOffset: 140 + size: 32 + fields: + - name: HOST_SLCHOST_CONF28 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF29 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF30 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF31 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HOST_SLCHOST_PKT_LEN0 + addressOffset: 144 + size: 32 + fields: + - name: HOST_HOSTSLC0_LEN0 + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: HOST_SLCHOST_PKT_LEN1 + addressOffset: 148 + size: 32 + fields: + - name: HOST_HOSTSLC0_LEN1 + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: HOST_SLCHOST_PKT_LEN2 + addressOffset: 152 + size: 32 + fields: + - name: HOST_HOSTSLC0_LEN2 + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: HOST_SLCHOST_CONF_W8 + addressOffset: 156 + size: 32 + fields: + - name: HOST_SLCHOST_CONF32 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF33 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF34 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF35 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HOST_SLCHOST_CONF_W9 + addressOffset: 160 + size: 32 + fields: + - name: HOST_SLCHOST_CONF36 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF37 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF38 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF39 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HOST_SLCHOST_CONF_W10 + addressOffset: 164 + size: 32 + fields: + - name: HOST_SLCHOST_CONF40 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF41 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF42 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF43 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HOST_SLCHOST_CONF_W11 + addressOffset: 168 + size: 32 + fields: + - name: HOST_SLCHOST_CONF44 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF45 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF46 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF47 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HOST_SLCHOST_CONF_W12 + addressOffset: 172 + size: 32 + fields: + - name: HOST_SLCHOST_CONF48 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF49 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF50 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF51 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HOST_SLCHOST_CONF_W13 + addressOffset: 176 + size: 32 + fields: + - name: HOST_SLCHOST_CONF52 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF53 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF54 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF55 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HOST_SLCHOST_CONF_W14 + addressOffset: 180 + size: 32 + fields: + - name: HOST_SLCHOST_CONF56 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF57 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF58 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF59 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HOST_SLCHOST_CONF_W15 + addressOffset: 184 + size: 32 + fields: + - name: HOST_SLCHOST_CONF60 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF61 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF62 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HOST_SLCHOST_CONF63 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HOST_SLCHOST_CHECK_SUM0 + addressOffset: 188 + size: 32 + fields: + - name: HOST_SLCHOST_CHECK_SUM0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HOST_SLCHOST_CHECK_SUM1 + addressOffset: 192 + size: 32 + fields: + - name: HOST_SLCHOST_CHECK_SUM1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HOST_SLC1HOST_TOKEN_RDATA + addressOffset: 196 + size: 32 + fields: + - name: HOST_SLC1_TOKEN0 + bitOffset: 0 + bitWidth: 12 + access: read-only + - name: HOST_SLC1_RX_PF_VALID + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: HOST_HOSTSLC1_TOKEN1 + bitOffset: 16 + bitWidth: 12 + access: read-only + - name: HOST_SLC1_RX_PF_EOF + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: HOST_SLC0HOST_TOKEN_WDATA + addressOffset: 200 + size: 32 + fields: + - name: HOST_SLC0HOST_TOKEN0_WD + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: HOST_SLC0HOST_TOKEN1_WD + bitOffset: 16 + bitWidth: 12 + access: read-write + - register: + name: HOST_SLC1HOST_TOKEN_WDATA + addressOffset: 204 + size: 32 + fields: + - name: HOST_SLC1HOST_TOKEN0_WD + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: HOST_SLC1HOST_TOKEN1_WD + bitOffset: 16 + bitWidth: 12 + access: read-write + - register: + name: HOST_SLCHOST_TOKEN_CON + addressOffset: 208 + size: 32 + fields: + - name: HOST_SLC0HOST_TOKEN0_DEC + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: HOST_SLC0HOST_TOKEN1_DEC + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: HOST_SLC0HOST_TOKEN0_WR + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: HOST_SLC0HOST_TOKEN1_WR + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: HOST_SLC1HOST_TOKEN0_DEC + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: HOST_SLC1HOST_TOKEN1_DEC + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: HOST_SLC1HOST_TOKEN0_WR + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: HOST_SLC1HOST_TOKEN1_WR + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: HOST_SLC0HOST_LEN_WR + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: HOST_SLC0HOST_INT_CLR + addressOffset: 212 + size: 32 + fields: + - name: HOST_SLC0_TOHOST_BIT0_INT_CLR + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: HOST_SLC0_TOHOST_BIT1_INT_CLR + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: HOST_SLC0_TOHOST_BIT2_INT_CLR + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: HOST_SLC0_TOHOST_BIT3_INT_CLR + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: HOST_SLC0_TOHOST_BIT4_INT_CLR + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: HOST_SLC0_TOHOST_BIT5_INT_CLR + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: HOST_SLC0_TOHOST_BIT6_INT_CLR + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: HOST_SLC0_TOHOST_BIT7_INT_CLR + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: HOST_SLC0_TOKEN0_1TO0_INT_CLR + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: HOST_SLC0_TOKEN1_1TO0_INT_CLR + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: HOST_SLC0_TOKEN0_0TO1_INT_CLR + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: HOST_SLC0_TOKEN1_0TO1_INT_CLR + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: HOST_SLC0HOST_RX_SOF_INT_CLR + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: HOST_SLC0HOST_RX_EOF_INT_CLR + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: HOST_SLC0HOST_RX_START_INT_CLR + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: HOST_SLC0HOST_TX_START_INT_CLR + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: HOST_SLC0_RX_UDF_INT_CLR + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: HOST_SLC0_TX_OVF_INT_CLR + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: HOST_SLC0_RX_PF_VALID_INT_CLR + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: HOST_SLC0_EXT_BIT0_INT_CLR + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: HOST_SLC0_EXT_BIT1_INT_CLR + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: HOST_SLC0_EXT_BIT2_INT_CLR + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: HOST_SLC0_EXT_BIT3_INT_CLR + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: HOST_SLC0_RX_NEW_PACKET_INT_CLR + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: HOST_SLC0_HOST_RD_RETRY_INT_CLR + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: HOST_GPIO_SDIO_INT_CLR + bitOffset: 25 + bitWidth: 1 + access: write-only + - register: + name: HOST_SLC1HOST_INT_CLR + addressOffset: 216 + size: 32 + fields: + - name: HOST_SLC1_TOHOST_BIT0_INT_CLR + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: HOST_SLC1_TOHOST_BIT1_INT_CLR + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: HOST_SLC1_TOHOST_BIT2_INT_CLR + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: HOST_SLC1_TOHOST_BIT3_INT_CLR + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: HOST_SLC1_TOHOST_BIT4_INT_CLR + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: HOST_SLC1_TOHOST_BIT5_INT_CLR + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: HOST_SLC1_TOHOST_BIT6_INT_CLR + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: HOST_SLC1_TOHOST_BIT7_INT_CLR + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: HOST_SLC1_TOKEN0_1TO0_INT_CLR + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: HOST_SLC1_TOKEN1_1TO0_INT_CLR + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: HOST_SLC1_TOKEN0_0TO1_INT_CLR + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: HOST_SLC1_TOKEN1_0TO1_INT_CLR + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: HOST_SLC1HOST_RX_SOF_INT_CLR + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: HOST_SLC1HOST_RX_EOF_INT_CLR + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: HOST_SLC1HOST_RX_START_INT_CLR + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: HOST_SLC1HOST_TX_START_INT_CLR + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: HOST_SLC1_RX_UDF_INT_CLR + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: HOST_SLC1_TX_OVF_INT_CLR + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: HOST_SLC1_RX_PF_VALID_INT_CLR + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: HOST_SLC1_EXT_BIT0_INT_CLR + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: HOST_SLC1_EXT_BIT1_INT_CLR + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: HOST_SLC1_EXT_BIT2_INT_CLR + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: HOST_SLC1_EXT_BIT3_INT_CLR + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: HOST_SLC1_HOST_RD_RETRY_INT_CLR + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR + bitOffset: 25 + bitWidth: 1 + access: write-only + - register: + name: HOST_SLC0HOST_FUNC1_INT_ENA + addressOffset: 220 + size: 32 + fields: + - name: HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC0HOST_RX_SOF_INT_ENA + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC0HOST_RX_EOF_INT_ENA + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC0HOST_RX_START_INT_ENA + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC0HOST_TX_START_INT_ENA + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC0_RX_UDF_INT_ENA + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC0_TX_OVF_INT_ENA + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC0_RX_PF_VALID_INT_ENA + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC0_EXT_BIT0_INT_ENA + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC0_EXT_BIT1_INT_ENA + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC0_EXT_BIT2_INT_ENA + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC0_EXT_BIT3_INT_ENA + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: HOST_FN1_GPIO_SDIO_INT_ENA + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: HOST_SLC1HOST_FUNC1_INT_ENA + addressOffset: 224 + size: 32 + fields: + - name: HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1HOST_RX_SOF_INT_ENA + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1HOST_RX_EOF_INT_ENA + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1HOST_RX_START_INT_ENA + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1HOST_TX_START_INT_ENA + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1_RX_UDF_INT_ENA + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1_TX_OVF_INT_ENA + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1_RX_PF_VALID_INT_ENA + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1_EXT_BIT0_INT_ENA + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1_EXT_BIT1_INT_ENA + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1_EXT_BIT2_INT_ENA + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1_EXT_BIT3_INT_ENA + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: HOST_SLC0HOST_FUNC2_INT_ENA + addressOffset: 228 + size: 32 + fields: + - name: HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC0HOST_RX_SOF_INT_ENA + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC0HOST_RX_EOF_INT_ENA + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC0HOST_RX_START_INT_ENA + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC0HOST_TX_START_INT_ENA + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC0_RX_UDF_INT_ENA + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC0_TX_OVF_INT_ENA + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC0_RX_PF_VALID_INT_ENA + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC0_EXT_BIT0_INT_ENA + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC0_EXT_BIT1_INT_ENA + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC0_EXT_BIT2_INT_ENA + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC0_EXT_BIT3_INT_ENA + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: HOST_FN2_GPIO_SDIO_INT_ENA + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: HOST_SLC1HOST_FUNC2_INT_ENA + addressOffset: 232 + size: 32 + fields: + - name: HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1HOST_RX_SOF_INT_ENA + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1HOST_RX_EOF_INT_ENA + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1HOST_RX_START_INT_ENA + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1HOST_TX_START_INT_ENA + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1_RX_UDF_INT_ENA + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1_TX_OVF_INT_ENA + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1_RX_PF_VALID_INT_ENA + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1_EXT_BIT0_INT_ENA + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1_EXT_BIT1_INT_ENA + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1_EXT_BIT2_INT_ENA + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1_EXT_BIT3_INT_ENA + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: HOST_SLC0HOST_INT_ENA + addressOffset: 236 + size: 32 + fields: + - name: HOST_SLC0_TOHOST_BIT0_INT_ENA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_TOHOST_BIT1_INT_ENA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_TOHOST_BIT2_INT_ENA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_TOHOST_BIT3_INT_ENA + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_TOHOST_BIT4_INT_ENA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_TOHOST_BIT5_INT_ENA + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_TOHOST_BIT6_INT_ENA + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_TOHOST_BIT7_INT_ENA + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_TOKEN0_1TO0_INT_ENA + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_TOKEN1_1TO0_INT_ENA + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_TOKEN0_0TO1_INT_ENA + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_TOKEN1_0TO1_INT_ENA + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: HOST_SLC0HOST_RX_SOF_INT_ENA + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: HOST_SLC0HOST_RX_EOF_INT_ENA + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: HOST_SLC0HOST_RX_START_INT_ENA + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: HOST_SLC0HOST_TX_START_INT_ENA + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_RX_UDF_INT_ENA + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_TX_OVF_INT_ENA + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_RX_PF_VALID_INT_ENA + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_EXT_BIT0_INT_ENA + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_EXT_BIT1_INT_ENA + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_EXT_BIT2_INT_ENA + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_EXT_BIT3_INT_ENA + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_RX_NEW_PACKET_INT_ENA + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_HOST_RD_RETRY_INT_ENA + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: HOST_GPIO_SDIO_INT_ENA + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: HOST_SLC1HOST_INT_ENA + addressOffset: 240 + size: 32 + fields: + - name: HOST_SLC1_TOHOST_BIT0_INT_ENA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_TOHOST_BIT1_INT_ENA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_TOHOST_BIT2_INT_ENA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_TOHOST_BIT3_INT_ENA + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_TOHOST_BIT4_INT_ENA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_TOHOST_BIT5_INT_ENA + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_TOHOST_BIT6_INT_ENA + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_TOHOST_BIT7_INT_ENA + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_TOKEN0_1TO0_INT_ENA + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_TOKEN1_1TO0_INT_ENA + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_TOKEN0_0TO1_INT_ENA + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_TOKEN1_0TO1_INT_ENA + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: HOST_SLC1HOST_RX_SOF_INT_ENA + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: HOST_SLC1HOST_RX_EOF_INT_ENA + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: HOST_SLC1HOST_RX_START_INT_ENA + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: HOST_SLC1HOST_TX_START_INT_ENA + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_RX_UDF_INT_ENA + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_TX_OVF_INT_ENA + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_RX_PF_VALID_INT_ENA + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_EXT_BIT0_INT_ENA + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_EXT_BIT1_INT_ENA + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_EXT_BIT2_INT_ENA + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_EXT_BIT3_INT_ENA + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_HOST_RD_RETRY_INT_ENA + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: HOST_SLC0HOST_RX_INFOR + addressOffset: 244 + size: 32 + fields: + - name: HOST_SLC0HOST_RX_INFOR + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: HOST_SLC1HOST_RX_INFOR + addressOffset: 248 + size: 32 + fields: + - name: HOST_SLC1HOST_RX_INFOR + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: HOST_SLC0HOST_LEN_WD + addressOffset: 252 + size: 32 + fields: + - name: HOST_SLC0HOST_LEN_WD + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HOST_SLC_APBWIN_WDATA + addressOffset: 256 + size: 32 + fields: + - name: HOST_SLC_APBWIN_WDATA + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HOST_SLC_APBWIN_CONF + addressOffset: 260 + size: 32 + fields: + - name: HOST_SLC_APBWIN_ADDR + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: HOST_SLC_APBWIN_WR + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HOST_SLC_APBWIN_START + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: HOST_SLC_APBWIN_RDATA + addressOffset: 264 + size: 32 + fields: + - name: HOST_SLC_APBWIN_RDATA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HOST_SLCHOST_RDCLR0 + addressOffset: 268 + size: 32 + resetValue: 245828 + fields: + - name: HOST_SLCHOST_SLC0_BIT7_CLRADDR + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: HOST_SLCHOST_SLC0_BIT6_CLRADDR + bitOffset: 9 + bitWidth: 9 + access: read-write + - register: + name: HOST_SLCHOST_RDCLR1 + addressOffset: 272 + size: 32 + resetValue: 246240 + fields: + - name: HOST_SLCHOST_SLC1_BIT7_CLRADDR + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: HOST_SLCHOST_SLC1_BIT6_CLRADDR + bitOffset: 9 + bitWidth: 9 + access: read-write + - register: + name: HOST_SLC0HOST_INT_ENA1 + addressOffset: 276 + size: 32 + fields: + - name: HOST_SLC0_TOHOST_BIT0_INT_ENA1 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_TOHOST_BIT1_INT_ENA1 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_TOHOST_BIT2_INT_ENA1 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_TOHOST_BIT3_INT_ENA1 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_TOHOST_BIT4_INT_ENA1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_TOHOST_BIT5_INT_ENA1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_TOHOST_BIT6_INT_ENA1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_TOHOST_BIT7_INT_ENA1 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_TOKEN0_1TO0_INT_ENA1 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_TOKEN1_1TO0_INT_ENA1 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_TOKEN0_0TO1_INT_ENA1 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_TOKEN1_0TO1_INT_ENA1 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: HOST_SLC0HOST_RX_SOF_INT_ENA1 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: HOST_SLC0HOST_RX_EOF_INT_ENA1 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: HOST_SLC0HOST_RX_START_INT_ENA1 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: HOST_SLC0HOST_TX_START_INT_ENA1 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_RX_UDF_INT_ENA1 + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_TX_OVF_INT_ENA1 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_RX_PF_VALID_INT_ENA1 + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_EXT_BIT0_INT_ENA1 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_EXT_BIT1_INT_ENA1 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_EXT_BIT2_INT_ENA1 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_EXT_BIT3_INT_ENA1 + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_RX_NEW_PACKET_INT_ENA1 + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: HOST_SLC0_HOST_RD_RETRY_INT_ENA1 + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: HOST_GPIO_SDIO_INT_ENA1 + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: HOST_SLC1HOST_INT_ENA1 + addressOffset: 280 + size: 32 + fields: + - name: HOST_SLC1_TOHOST_BIT0_INT_ENA1 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_TOHOST_BIT1_INT_ENA1 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_TOHOST_BIT2_INT_ENA1 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_TOHOST_BIT3_INT_ENA1 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_TOHOST_BIT4_INT_ENA1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_TOHOST_BIT5_INT_ENA1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_TOHOST_BIT6_INT_ENA1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_TOHOST_BIT7_INT_ENA1 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_TOKEN0_1TO0_INT_ENA1 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_TOKEN1_1TO0_INT_ENA1 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_TOKEN0_0TO1_INT_ENA1 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_TOKEN1_0TO1_INT_ENA1 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: HOST_SLC1HOST_RX_SOF_INT_ENA1 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: HOST_SLC1HOST_RX_EOF_INT_ENA1 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: HOST_SLC1HOST_RX_START_INT_ENA1 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: HOST_SLC1HOST_TX_START_INT_ENA1 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_RX_UDF_INT_ENA1 + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_TX_OVF_INT_ENA1 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_RX_PF_VALID_INT_ENA1 + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_EXT_BIT0_INT_ENA1 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_EXT_BIT1_INT_ENA1 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_EXT_BIT2_INT_ENA1 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_EXT_BIT3_INT_ENA1 + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_HOST_RD_RETRY_INT_ENA1 + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: HOST_SLCHOSTDATE + addressOffset: 376 + size: 32 + resetValue: 369239296 + fields: + - name: HOST_SLCHOST_DATE + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HOST_SLCHOSTID + addressOffset: 380 + size: 32 + resetValue: 1536 + fields: + - name: HOST_SLCHOST_ID + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HOST_SLCHOST_CONF + addressOffset: 496 + size: 32 + fields: + - name: HOST_FRC_SDIO11 + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: HOST_FRC_SDIO20 + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: HOST_FRC_NEG_SAMP + bitOffset: 10 + bitWidth: 5 + access: read-write + - name: HOST_FRC_POS_SAMP + bitOffset: 15 + bitWidth: 5 + access: read-write + - name: HOST_FRC_QUICK_IN + bitOffset: 20 + bitWidth: 5 + access: read-write + - name: HOST_SDIO20_INT_DELAY + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: HOST_SDIO_PAD_PULLUP + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HOST_HSPEED_CON_EN + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: HOST_SLCHOST_INF_ST + addressOffset: 500 + size: 32 + fields: + - name: HOST_SDIO20_MODE + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: HOST_SDIO_NEG_SAMP + bitOffset: 5 + bitWidth: 5 + access: read-only + - name: HOST_SDIO_QUICK_IN + bitOffset: 10 + bitWidth: 5 + access: read-only + - name: SPI0 + description: SPI (Serial Peripheral Interface) Controller 0 + groupName: SPI + baseAddress: 1072967680 + addressBlock: + - offset: 0 + size: 272 + usage: registers + interrupt: + - name: SPI0 + value: 28 + registers: + - register: + name: CMD + addressOffset: 0 + size: 32 + fields: + - name: FLASH_PER + description: "program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FLASH_PES + description: "program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: USR + description: "User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: FLASH_HPM + description: "Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: FLASH_RES + description: "This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: FLASH_DP + description: "Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: FLASH_CE + description: "Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: FLASH_BE + description: "Block erase enable. A 64KB block is erased via SPI command D8H. Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: FLASH_SE + description: "Sector erase enable. A 4KB sector is erased via SPI command 20H. Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: FLASH_PP + description: "Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: FLASH_WRSR + description: "Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: FLASH_RDSR + description: "Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: FLASH_RDID + description: "Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: FLASH_WRDI + description: "Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: FLASH_WREN + description: "Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: FLASH_READ + description: "Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: ADDR + addressOffset: 4 + size: 32 + - register: + name: CTRL + addressOffset: 8 + size: 32 + resetValue: 2139136 + fields: + - name: FCS_CRC_EN + description: For SPI1 initialize crc32 module before writing encrypted data to flash. Active low. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TX_CRC_EN + description: "For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: WAIT_FLASH_IDLE_EN + description: "wait flash idle when program flash or erase flash. 1: enable 0: disable." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FASTRD_MODE + description: "This bit enable the bits: spi_fread_qio spi_fread_dio spi_fread_qout and spi_fread_dout. 1: enable 0: disable." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FREAD_DUAL + description: "In the read operations read-data phase apply 2 signals. 1: enable 0: disable." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RESANDRES + description: "The Device ID is read out to SPI_RD_STATUS register, this bit combine with spi_flash_res bit. 1: enable 0: disable." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: FREAD_QUAD + description: "In the read operations read-data phase apply 4 signals. 1: enable 0: disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: WP + description: "Write protect signal output when SPI is idle. 1: output high 0: output low." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: WRSR_2B + description: "two bytes data will be written to status register when it is set. 1: enable 0: disable." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: FREAD_DIO + description: "In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: FREAD_QIO + description: "In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: RD_BIT_ORDER + description: "In read-data (MISO) phase 1: LSB first 0: MSB first" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: WR_BIT_ORDER + description: "In command address write-data (MOSI) phases 1: LSB firs 0: MSB first" + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: CTRL1 + addressOffset: 12 + size: 32 + resetValue: 1610547200 + fields: + - name: CS_HOLD_DELAY_RES + description: Delay cycles of resume Flash when resume Flash is enable by spi clock. + bitOffset: 16 + bitWidth: 12 + access: read-write + - name: CS_HOLD_DELAY + description: SPI cs signal is delayed by spi clock cycles + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: RD_STATUS + addressOffset: 16 + size: 32 + fields: + - name: STATUS + description: "In the slave mode, it is the status for master to read out." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: WB_MODE + description: "Mode bits in the flash fast read mode, it is combined with spi_fastrd_mode bit." + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: STATUS_EXT + description: "In the slave mode,it is the status for master to read out." + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: CTRL2 + addressOffset: 20 + size: 32 + resetValue: 17 + fields: + - name: SETUP_TIME + description: "(cycles-1) of ¡°prepare¡± phase by spi clock, this bits combined with spi_cs_setup bit." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: HOLD_TIME + description: "delay cycles of cs pin by spi clock, this bits combined with spi_cs_hold bit." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: CK_OUT_LOW_MODE + description: "modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_L bits." + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: CK_OUT_HIGH_MODE + description: "modify spi clock duty ratio when the value is lager than 8, the bits are combined with spi_clkcnt_N bits and spi_clkcnt_H bits." + bitOffset: 12 + bitWidth: 4 + access: read-write + - name: MISO_DELAY_MODE + description: "MISO signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle" + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: MISO_DELAY_NUM + description: MISO signals are delayed by system clock cycles + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: MOSI_DELAY_MODE + description: "MOSI signals are delayed by spi_clk. 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle" + bitOffset: 21 + bitWidth: 2 + access: read-write + - name: MOSI_DELAY_NUM + description: MOSI signals are delayed by system clock cycles + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: CS_DELAY_MODE + description: "spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle else delayed by half cycle 3: delayed one cycle" + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CS_DELAY_NUM + description: spi_cs signal is delayed by system clock cycles + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: CLOCK + addressOffset: 24 + size: 32 + resetValue: 2147496003 + fields: + - name: CLKCNT_L + description: In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: CLKCNT_H + description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: CLKCNT_N + description: In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1) + bitOffset: 12 + bitWidth: 6 + access: read-write + - name: CLKDIV_PRE + description: In the master mode it is pre-divider of spi_clk. + bitOffset: 18 + bitWidth: 13 + access: read-write + - name: CLK_EQU_SYSCLK + description: "In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USER + addressOffset: 28 + size: 32 + resetValue: 2147483712 + fields: + - name: DOUTDIN + description: "Set the bit to enable full duplex communication. 1: enable 0: disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CS_HOLD + description: "spi cs keep low when spi is in ¡°done¡± phase. 1: enable 0: disable." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CS_SETUP + description: "spi cs is enable when spi is in ¡°prepare¡± phase. 1: enable 0: disable." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CK_I_EDGE + description: In the slave mode the bit is same as spi_ck_out_edge in master mode. It is combined with spi_miso_delay_mode bits. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CK_OUT_EDGE + description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RD_BYTE_ORDER + description: "In read-data (MISO) phase 1: big-endian 0: little_endian" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: WR_BYTE_ORDER + description: "In command address write-data (MOSI) phases 1: big-endian 0: litte_endian" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FWRITE_DUAL + description: In the write operations read-data phase apply 2 signals + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FWRITE_QUAD + description: In the write operations read-data phase apply 4 signals + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FWRITE_DIO + description: In the write operations address phase and read-data phase apply 2 signals. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: FWRITE_QIO + description: In the write operations address phase and read-data phase apply 4 signals. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SIO + description: "Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: USR_HOLD_POL + description: "It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: USR_DOUT_HOLD + description: spi is hold at data out state the bit combined with spi_usr_hold_pol bit. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: USR_DIN_HOLD + description: spi is hold at data in state the bit combined with spi_usr_hold_pol bit. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: USR_DUMMY_HOLD + description: spi is hold at dummy state the bit combined with spi_usr_hold_pol bit. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: USR_ADDR_HOLD + description: spi is hold at address state the bit combined with spi_usr_hold_pol bit. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: USR_CMD_HOLD + description: spi is hold at command state the bit combined with spi_usr_hold_pol bit. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: USR_PREP_HOLD + description: spi is hold at prepare state the bit combined with spi_usr_hold_pol bit. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: USR_MISO_HIGHPART + description: "read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: USR_MOSI_HIGHPART + description: "write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: USR_DUMMY_IDLE + description: spi clock is disable in dummy phase when the bit is enable. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: USR_MOSI + description: This bit enable the write-data phase of an operation. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: USR_MISO + description: This bit enable the read-data phase of an operation. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: USR_DUMMY + description: This bit enable the dummy phase of an operation. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: USR_ADDR + description: This bit enable the address phase of an operation. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: USR_COMMAND + description: This bit enable the command phase of an operation. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USER1 + addressOffset: 32 + size: 32 + resetValue: 1543503879 + fields: + - name: USR_DUMMY_CYCLELEN + description: The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: USR_ADDR_BITLEN + description: The length in bits of address phase. The register value shall be (bit_num-1). + bitOffset: 26 + bitWidth: 6 + access: read-only + - register: + name: USER2 + addressOffset: 36 + size: 32 + resetValue: 1879048192 + fields: + - name: USR_COMMAND_VALUE + description: The value of command. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: USR_COMMAND_BITLEN + description: The length in bits of command phase. The register value shall be (bit_num-1) + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: MOSI_DLEN + addressOffset: 40 + size: 32 + fields: + - name: USR_MOSI_DBITLEN + description: The length in bits of write-data. The register value shall be (bit_num-1). + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: MISO_DLEN + addressOffset: 44 + size: 32 + fields: + - name: USR_MISO_DBITLEN + description: The length in bits of read-data. The register value shall be (bit_num-1). + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: SLV_WR_STATUS + addressOffset: 48 + size: 32 + fields: + - name: SLV_WR_ST + description: In the slave mode this register are the status register for the master to write into. In the master mode this register are the higher 32bits in the 64 bits address condition. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PIN + addressOffset: 52 + size: 32 + resetValue: 6 + fields: + - name: CS0_DIS + description: "SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CS1_DIS + description: "SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CS2_DIS + description: "SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CK_DIS + description: "1: spi clk out disable 0: spi clk out enable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: MASTER_CS_POL + description: In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol. + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: MASTER_CK_SEL + description: In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis. + bitOffset: 11 + bitWidth: 3 + access: read-write + - name: CK_IDLE_EDGE + description: "1: spi clk line is high when idle 0: spi clk line is low when idle" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CS_KEEP_ACTIVE + description: spi cs line keep low when the bit is set. + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: SLAVE + addressOffset: 56 + size: 32 + resetValue: 32 + fields: + - name: SLV_RD_BUF_DONE + description: The interrupt raw bit for the completion of read-buffer operation in the slave mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLV_WR_BUF_DONE + description: The interrupt raw bit for the completion of write-buffer operation in the slave mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SLV_RD_STA_DONE + description: The interrupt raw bit for the completion of read-status operation in the slave mode. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLV_WR_STA_DONE + description: The interrupt raw bit for the completion of write-status operation in the slave mode. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TRANS_DONE + description: The interrupt raw bit for the completion of any operation in both the master mode and the slave mode. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: INT_EN + description: Interrupt enable bits for the below 5 sources + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: CS_I_MODE + description: In the slave mode this bits used to synchronize the input spi cs signal and eliminate spi cs jitter. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: SLV_LAST_COMMAND + description: In the slave mode it is the value of command. + bitOffset: 17 + bitWidth: 3 + access: read-only + - name: SLV_LAST_STATE + description: In the slave mode it is the state of spi state machine. + bitOffset: 20 + bitWidth: 3 + access: read-only + - name: TRANS_CNT + description: "The operations counter in both the master mode and the slave mode. 4: read-status" + bitOffset: 23 + bitWidth: 4 + access: read-only + - name: SLV_CMD_DEFINE + description: "1: slave mode commands are defined in SPI_SLAVE3. 0: slave mode commands are fixed as: 1: write-status 2: write-buffer and 3: read-buffer." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SLV_WR_RD_STA_EN + description: write and read status enable in the slave mode + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SLV_WR_RD_BUF_EN + description: write and read buffer enable in the slave mode + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: MODE + description: "1: slave mode 0: master mode." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SYNC_RESET + description: "Software reset enable, reset the spi clock line cs line and data lines." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SLAVE1 + addressOffset: 60 + size: 32 + resetValue: 33554432 + fields: + - name: SLV_RDBUF_DUMMY_EN + description: In the slave mode it is the enable bit of dummy phase for read-buffer operations. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLV_WRBUF_DUMMY_EN + description: In the slave mode it is the enable bit of dummy phase for write-buffer operations. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SLV_RDSTA_DUMMY_EN + description: In the slave mode it is the enable bit of dummy phase for read-status operations. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLV_WRSTA_DUMMY_EN + description: In the slave mode it is the enable bit of dummy phase for write-status operations. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLV_WR_ADDR_BITLEN + description: In the slave mode it is the address length in bits for write-buffer operation. The register value shall be (bit_num-1). + bitOffset: 4 + bitWidth: 6 + access: read-write + - name: SLV_RD_ADDR_BITLEN + description: In the slave mode it is the address length in bits for read-buffer operation. The register value shall be (bit_num-1). + bitOffset: 10 + bitWidth: 6 + access: read-write + - name: SLV_STATUS_READBACK + description: "In the slave mode 1:read register of SPI_SLV_WR_STATUS 0: read register of SPI_RD_STATUS." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: SLV_STATUS_FAST_EN + description: In the slave mode enable fast read status. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SLV_STATUS_BITLEN + description: In the slave mode it is the length of status bit. + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: SLAVE2 + addressOffset: 64 + size: 32 + fields: + - name: SLV_RDSTA_DUMMY_CYCLELEN + description: In the slave mode it is the length in spi_clk cycles of dummy phase for read-status operations. The register value shall be (cycle_num-1). + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SLV_WRSTA_DUMMY_CYCLELEN + description: In the slave mode it is the length in spi_clk cycles of dummy phase for write-status operations. The register value shall be (cycle_num-1). + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SLV_RDBUF_DUMMY_CYCLELEN + description: In the slave mode it is the length in spi_clk cycles of dummy phase for read-buffer operations. The register value shall be (cycle_num-1). + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SLV_WRBUF_DUMMY_CYCLELEN + description: In the slave mode it is the length in spi_clk cycles of dummy phase for write-buffer operations. The register value shall be (cycle_num-1). + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: SLAVE3 + addressOffset: 68 + size: 32 + fields: + - name: SLV_RDBUF_CMD_VALUE + description: In the slave mode it is the value of read-buffer command. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SLV_WRBUF_CMD_VALUE + description: In the slave mode it is the value of write-buffer command. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SLV_RDSTA_CMD_VALUE + description: In the slave mode it is the value of read-status command. + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SLV_WRSTA_CMD_VALUE + description: In the slave mode it is the value of write-status command. + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: SLV_WRBUF_DLEN + addressOffset: 72 + size: 32 + fields: + - name: SLV_WRBUF_DBITLEN + description: In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1). + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: SLV_RDBUF_DLEN + addressOffset: 76 + size: 32 + fields: + - name: SLV_RDBUF_DBITLEN + description: In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1). + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: CACHE_FCTRL + addressOffset: 80 + size: 32 + fields: + - name: CACHE_REQ_EN + description: "For SPI0 Cache access enable 1: enable 0:disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CACHE_USR_CMD_4BYTE + description: "For SPI0 cache read flash with 4 bytes command 1: enable 0:disable." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CACHE_FLASH_USR_CMD + description: "For SPI0 cache read flash for user define command 1: enable 0:disable." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CACHE_FLASH_PES_EN + description: "For SPI0 spi1 send suspend command before cache read flash 1: enable 0:disable." + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: CACHE_SCTRL + addressOffset: 84 + size: 32 + resetValue: 364922928 + fields: + - name: USR_SRAM_DIO + description: "For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: USR_SRAM_QIO + description: "For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: USR_WR_SRAM_DUMMY + description: For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: USR_RD_SRAM_DUMMY + description: For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CACHE_SRAM_USR_RCMD + description: For SPI0 In the spi sram mode cache read sram for user define command. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SRAM_BYTES_LEN + description: For SPI0 In the sram mode it is the byte length of spi read sram data. + bitOffset: 6 + bitWidth: 8 + access: read-write + - name: SRAM_DUMMY_CYCLELEN + description: For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1). + bitOffset: 14 + bitWidth: 8 + access: read-write + - name: SRAM_ADDR_BITLEN + description: For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1). + bitOffset: 22 + bitWidth: 6 + access: read-write + - name: CACHE_SRAM_USR_WCMD + description: For SPI0 In the spi sram mode cache write sram for user define command + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: SRAM_CMD + addressOffset: 88 + size: 32 + fields: + - name: SRAM_DIO + description: For SPI0 SRAM DIO mode enable . SRAM DIO enable command will be send when the bit is set. The bit will be cleared once the operation done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SRAM_QIO + description: For SPI0 SRAM QIO mode enable . SRAM QIO enable command will be send when the bit is set. The bit will be cleared once the operation done. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SRAM_RSTIO + description: For SPI0 SRAM IO mode reset enable. SRAM IO mode reset operation will be triggered when the bit is set. The bit will be cleared once the operation done + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: SRAM_DRD_CMD + addressOffset: 92 + size: 32 + fields: + - name: CACHE_SRAM_USR_RD_CMD_VALUE + description: For SPI0 When cache mode is enable it is the read command value of command phase for SRAM. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CACHE_SRAM_USR_RD_CMD_BITLEN + description: For SPI0 When cache mode is enable it is the length in bits of command phase for SRAM. The register value shall be (bit_num-1). + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: SRAM_DWR_CMD + addressOffset: 96 + size: 32 + fields: + - name: CACHE_SRAM_USR_WR_CMD_VALUE + description: For SPI0 When cache mode is enable it is the write command value of command phase for SRAM. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CACHE_SRAM_USR_WR_CMD_BITLEN + description: For SPI0 When cache mode is enable it is the in bits of command phase for SRAM. The register value shall be (bit_num-1). + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: SLV_RD_BIT + addressOffset: 100 + size: 32 + fields: + - name: SLV_RDATA_BIT + description: In the slave mode it is the bit length of read data. The value is the length - 1. + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: W0 + addressOffset: 128 + size: 32 + fields: + - name: BUF0 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W1 + addressOffset: 132 + size: 32 + fields: + - name: BUF1 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W2 + addressOffset: 136 + size: 32 + fields: + - name: BUF2 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W3 + addressOffset: 140 + size: 32 + fields: + - name: BUF3 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W4 + addressOffset: 144 + size: 32 + fields: + - name: BUF4 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W5 + addressOffset: 148 + size: 32 + fields: + - name: BUF5 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W6 + addressOffset: 152 + size: 32 + fields: + - name: BUF6 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W7 + addressOffset: 156 + size: 32 + fields: + - name: BUF7 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W8 + addressOffset: 160 + size: 32 + fields: + - name: BUF8 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W9 + addressOffset: 164 + size: 32 + fields: + - name: BUF9 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W10 + addressOffset: 168 + size: 32 + fields: + - name: BUF10 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W11 + addressOffset: 172 + size: 32 + fields: + - name: BUF11 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W12 + addressOffset: 176 + size: 32 + fields: + - name: BUF12 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W13 + addressOffset: 180 + size: 32 + fields: + - name: BUF13 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W14 + addressOffset: 184 + size: 32 + fields: + - name: BUF14 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W15 + addressOffset: 188 + size: 32 + fields: + - name: BUF15 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TX_CRC + addressOffset: 192 + size: 32 + fields: + - name: DATA + description: For SPI1 the value of crc32 for 256 bits data. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: EXT0 + addressOffset: 240 + size: 32 + resetValue: 2148139088 + fields: + - name: T_PP_TIME + description: page program delay time by system clock. + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: T_PP_SHIFT + description: page program delay time shift . + bitOffset: 16 + bitWidth: 4 + access: read-write + - name: T_PP_ENA + description: page program delay enable. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EXT1 + addressOffset: 244 + size: 32 + resetValue: 2148466688 + fields: + - name: T_ERASE_TIME + description: erase flash delay time by system clock. + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: T_ERASE_SHIFT + description: erase flash delay time shift. + bitOffset: 16 + bitWidth: 4 + access: read-write + - name: T_ERASE_ENA + description: erase flash delay enable. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EXT2 + addressOffset: 248 + size: 32 + fields: + - name: ST + description: The status of spi state machine . + bitOffset: 0 + bitWidth: 3 + access: read-only + - register: + name: EXT3 + addressOffset: 252 + size: 32 + fields: + - name: INT_HOLD_ENA + description: "This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set if the other SPI is busy the SPI will be hold. 1(3): hold at ¡°idle¡± phase 2: hold at ¡°prepare¡± phase." + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: DMA_CONF + addressOffset: 256 + size: 32 + resetValue: 512 + fields: + - name: IN_RST + description: The bit is used to reset in dma fsm and in data fifo pointer. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_RST + description: The bit is used to reset out dma fsm and out data fifo pointer. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: AHBM_FIFO_RST + description: reset spi dma ahb master fifo pointer. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: AHBM_RST + description: reset spi dma ahb master. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: IN_LOOP_TEST + description: Set bit to test in link. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUT_LOOP_TEST + description: Set bit to test out link. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_AUTO_WRBACK + description: when the link is empty jump to next automatically. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: OUT_EOF_MODE + description: "out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OUTDSCR_BURST_EN + description: read descriptor use burst mode when read data for memory. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: INDSCR_BURST_EN + description: read descriptor use burst mode when write data to memory. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: OUT_DATA_BURST_EN + description: spi dma read data from memory in burst mode. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DMA_RX_STOP + description: spi dma read data stop when in continue tx/rx mode. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DMA_TX_STOP + description: spi dma write data stop when in continue tx/rx mode. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DMA_CONTINUE + description: spi dma continue tx/rx data. + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: DMA_OUT_LINK + addressOffset: 260 + size: 32 + fields: + - name: OUTLINK_ADDR + description: The address of the first outlink descriptor. + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: OUTLINK_STOP + description: Set the bit to stop to use outlink descriptor. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: OUTLINK_START + description: Set the bit to start to use outlink descriptor. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: OUTLINK_RESTART + description: Set the bit to mount on new outlink descriptors. + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: DMA_IN_LINK + addressOffset: 264 + size: 32 + fields: + - name: INLINK_ADDR + description: The address of the first inlink descriptor. + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: INLINK_AUTO_RET + description: when the bit is set inlink descriptor returns to the next descriptor while a packet is wrong + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: INLINK_STOP + description: Set the bit to stop to use inlink descriptor. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: INLINK_START + description: Set the bit to start to use inlink descriptor. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: INLINK_RESTART + description: Set the bit to mount on new inlink descriptors. + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: DMA_STATUS + addressOffset: 268 + size: 32 + fields: + - name: DMA_RX_EN + description: spi dma read data status bit. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DMA_TX_EN + description: spi dma write data status bit. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: DMA_INT_ENA + addressOffset: 272 + size: 32 + fields: + - name: INLINK_DSCR_EMPTY_INT_ENA + description: The enable bit for lack of enough inlink descriptors. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUTLINK_DSCR_ERROR_INT_ENA + description: The enable bit for outlink descriptor error. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: INLINK_DSCR_ERROR_INT_ENA + description: The enable bit for inlink descriptor error. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DONE_INT_ENA + description: The enable bit for completing usage of a inlink descriptor. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF_INT_ENA + description: The enable bit for receiving error. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF_INT_ENA + description: The enable bit for completing receiving all the packets from host. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUT_DONE_INT_ENA + description: The enable bit for completing usage of a outlink descriptor . + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUT_EOF_INT_ENA + description: The enable bit for sending a packet to host done. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF_INT_ENA + description: The enable bit for sending all the packets to host done. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: DMA_INT_RAW + addressOffset: 276 + size: 32 + fields: + - name: INLINK_DSCR_EMPTY_INT_RAW + description: The raw bit for lack of enough inlink descriptors. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUTLINK_DSCR_ERROR_INT_RAW + description: The raw bit for outlink descriptor error. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: INLINK_DSCR_ERROR_INT_RAW + description: The raw bit for inlink descriptor error. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: IN_DONE_INT_RAW + description: The raw bit for completing usage of a inlink descriptor. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: IN_ERR_EOF_INT_RAW + description: The raw bit for receiving error. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: IN_SUC_EOF_INT_RAW + description: The raw bit for completing receiving all the packets from host. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OUT_DONE_INT_RAW + description: The raw bit for completing usage of a outlink descriptor. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUT_EOF_INT_RAW + description: The raw bit for sending a packet to host done. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OUT_TOTAL_EOF_INT_RAW + description: The raw bit for sending all the packets to host done. + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: DMA_INT_ST + addressOffset: 280 + size: 32 + fields: + - name: INLINK_DSCR_EMPTY_INT_ST + description: The status bit for lack of enough inlink descriptors. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUTLINK_DSCR_ERROR_INT_ST + description: The status bit for outlink descriptor error. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: INLINK_DSCR_ERROR_INT_ST + description: The status bit for inlink descriptor error. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: IN_DONE_INT_ST + description: The status bit for completing usage of a inlink descriptor. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: IN_ERR_EOF_INT_ST + description: The status bit for receiving error. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: IN_SUC_EOF_INT_ST + description: The status bit for completing receiving all the packets from host. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OUT_DONE_INT_ST + description: The status bit for completing usage of a outlink descriptor. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUT_EOF_INT_ST + description: The status bit for sending a packet to host done. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OUT_TOTAL_EOF_INT_ST + description: The status bit for sending all the packets to host done. + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: DMA_INT_CLR + addressOffset: 284 + size: 32 + fields: + - name: INLINK_DSCR_EMPTY_INT_CLR + description: The clear bit for lack of enough inlink descriptors. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUTLINK_DSCR_ERROR_INT_CLR + description: The clear bit for outlink descriptor error. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: INLINK_DSCR_ERROR_INT_CLR + description: The clear bit for inlink descriptor error. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DONE_INT_CLR + description: The clear bit for completing usage of a inlink descriptor. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF_INT_CLR + description: The clear bit for receiving error. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF_INT_CLR + description: The clear bit for completing receiving all the packets from host. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUT_DONE_INT_CLR + description: The clear bit for completing usage of a outlink descriptor. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUT_EOF_INT_CLR + description: The clear bit for sending a packet to host done. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF_INT_CLR + description: The clear bit for sending all the packets to host done. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: IN_ERR_EOF_DES_ADDR + addressOffset: 288 + size: 32 + fields: + - name: DMA_IN_ERR_EOF_DES_ADDR + description: The inlink descriptor address when spi dma produce receiving error. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_SUC_EOF_DES_ADDR + addressOffset: 292 + size: 32 + fields: + - name: DMA_IN_SUC_EOF_DES_ADDR + description: The last inlink descriptor address when spi dma produce from_suc_eof. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INLINK_DSCR + addressOffset: 296 + size: 32 + fields: + - name: DMA_INLINK_DSCR + description: The content of current in descriptor pointer. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INLINK_DSCR_BF0 + addressOffset: 300 + size: 32 + fields: + - name: DMA_INLINK_DSCR_BF0 + description: The content of next in descriptor pointer. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INLINK_DSCR_BF1 + addressOffset: 304 + size: 32 + fields: + - name: DMA_INLINK_DSCR_BF1 + description: The content of current in descriptor data buffer pointer. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_EOF_BFR_DES_ADDR + addressOffset: 308 + size: 32 + fields: + - name: DMA_OUT_EOF_BFR_DES_ADDR + description: The address of buffer relative to the outlink descriptor that produce eof. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_EOF_DES_ADDR + addressOffset: 312 + size: 32 + fields: + - name: DMA_OUT_EOF_DES_ADDR + description: The last outlink descriptor address when spi dma produce to_eof. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUTLINK_DSCR + addressOffset: 316 + size: 32 + fields: + - name: DMA_OUTLINK_DSCR + description: The content of current out descriptor pointer. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUTLINK_DSCR_BF0 + addressOffset: 320 + size: 32 + fields: + - name: DMA_OUTLINK_DSCR_BF0 + description: The content of next out descriptor pointer. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUTLINK_DSCR_BF1 + addressOffset: 324 + size: 32 + fields: + - name: DMA_OUTLINK_DSCR_BF1 + description: The content of current out descriptor data buffer pointer. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DMA_RSTATUS + addressOffset: 328 + size: 32 + fields: + - name: DMA_OUT_STATUS + description: spi dma read data from memory status. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DMA_TSTATUS + addressOffset: 332 + size: 32 + fields: + - name: DMA_IN_STATUS + description: spi dma write data to memory status. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DATE + addressOffset: 1020 + size: 32 + resetValue: 23085680 + fields: + - name: DATE + description: SPI register version. + bitOffset: 0 + bitWidth: 28 + access: read-only + - name: SPI1 + description: SPI (Serial Peripheral Interface) Controller 1 + baseAddress: 1072963584 + interrupt: + - name: SPI1 + value: 29 + - name: SPI1_DMA + value: 52 + derivedFrom: SPI0 + - name: SPI2 + description: SPI (Serial Peripheral Interface) Controller 2 + baseAddress: 1073102848 + interrupt: + - name: SPI2 + value: 30 + - name: SPI2_DMA + value: 53 + derivedFrom: SPI0 + - name: SPI3 + description: SPI (Serial Peripheral Interface) Controller 3 + baseAddress: 1073106944 + interrupt: + - name: SPI3 + value: 31 + - name: SPI3_DMA + value: 54 + derivedFrom: SPI0 + - name: TIMG0 + description: Timer Group 0 + groupName: TIMG + baseAddress: 1073082368 + addressBlock: + - offset: 0 + size: 176 + usage: registers + interrupt: + - name: TG0_T0_LEVEL + value: 14 + - name: TG0_T1_LEVEL + value: 15 + - name: TG0_WDT_LEVEL + value: 16 + - name: TG0_LACT_LEVEL + value: 17 + - name: TG0_T0_EDGE + value: 58 + - name: TG0_T1_EDGE + value: 59 + - name: TG0_WDT_EDGE + value: 60 + - name: TG0_LACT_EDGE + value: 61 + registers: + - register: + name: T0CONFIG + addressOffset: 0 + size: 32 + resetValue: 1610620928 + fields: + - name: ALARM_EN + description: When set alarm is enabled + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: LEVEL_INT_EN + description: When set level type interrupt will be generated during alarm + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: EDGE_INT_EN + description: When set edge type interrupt will be generated during alarm + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DIVIDER + description: Timer 0 clock (T0_clk) prescale value. + bitOffset: 13 + bitWidth: 16 + access: read-write + - name: AUTORELOAD + description: When set timer 0 auto-reload at alarming is enabled + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: INCREASE + description: When set timer 0 time-base counter increment. When cleared timer 0 time-base counter decrement. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: EN + description: When set timer 0 time-base counter is enabled + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: T0LO + addressOffset: 4 + size: 32 + fields: + - name: LO + description: Register to store timer 0 time-base counter current value lower 32 bits. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: T0HI + addressOffset: 8 + size: 32 + fields: + - name: HI + description: Register to store timer 0 time-base counter current value higher 32 bits. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: T0UPDATE + addressOffset: 12 + size: 32 + fields: + - name: UPDATE + description: Write any value will trigger a timer 0 time-base counter value update (timer 0 current value will be stored in registers above) + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: T0ALARMLO + addressOffset: 16 + size: 32 + fields: + - name: ALARM_LO + description: Timer 0 time-base counter value lower 32 bits that will trigger the alarm + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: T0ALARMHI + addressOffset: 20 + size: 32 + fields: + - name: ALARM_HI + description: Timer 0 time-base counter value higher 32 bits that will trigger the alarm + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: T0LOADLO + addressOffset: 24 + size: 32 + fields: + - name: LOAD_LO + description: Lower 32 bits of the value that will load into timer 0 time-base counter + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: T0LOADHI + addressOffset: 28 + size: 32 + fields: + - name: LOAD_HI + description: higher 32 bits of the value that will load into timer 0 time-base counter + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: T0LOAD + addressOffset: 32 + size: 32 + fields: + - name: LOAD + description: Write any value will trigger timer 0 time-base counter reload + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: T1CONFIG + addressOffset: 36 + size: 32 + resetValue: 1610620928 + fields: + - name: ALARM_EN + description: When set alarm is enabled + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: LEVEL_INT_EN + description: When set level type interrupt will be generated during alarm + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: EDGE_INT_EN + description: When set edge type interrupt will be generated during alarm + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DIVIDER + description: Timer 1 clock (T1_clk) prescale value. + bitOffset: 13 + bitWidth: 16 + access: read-write + - name: AUTORELOAD + description: When set timer 1 auto-reload at alarming is enabled + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: INCREASE + description: When set timer 1 time-base counter increment. When cleared timer 1 time-base counter decrement. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: EN + description: When set timer 1 time-base counter is enabled + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: T1LO + addressOffset: 40 + size: 32 + fields: + - name: LO + description: Register to store timer 1 time-base counter current value lower 32 bits. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: T1HI + addressOffset: 44 + size: 32 + fields: + - name: HI + description: Register to store timer 1 time-base counter current value higher 32 bits. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: T1UPDATE + addressOffset: 48 + size: 32 + fields: + - name: UPDATE + description: Write any value will trigger a timer 1 time-base counter value update (timer 1 current value will be stored in registers above) + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: T1ALARMLO + addressOffset: 52 + size: 32 + fields: + - name: ALARM_LO + description: Timer 1 time-base counter value lower 32 bits that will trigger the alarm + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: T1ALARMHI + addressOffset: 56 + size: 32 + fields: + - name: ALARM_HI + description: Timer 1 time-base counter value higher 32 bits that will trigger the alarm + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: T1LOADLO + addressOffset: 60 + size: 32 + fields: + - name: LOAD_LO + description: Lower 32 bits of the value that will load into timer 1 time-base counter + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: T1LOADHI + addressOffset: 64 + size: 32 + fields: + - name: LOAD_HI + description: higher 32 bits of the value that will load into timer 1 time-base counter + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: T1LOAD + addressOffset: 68 + size: 32 + fields: + - name: LOAD + description: Write any value will trigger timer 1 time-base counter reload + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: WDTCONFIG0 + addressOffset: 72 + size: 32 + resetValue: 311296 + fields: + - name: WDT_FLASHBOOT_MOD_EN + description: When set flash boot protection is enabled + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: WDT_SYS_RESET_LENGTH + description: "length of system reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us" + bitOffset: 15 + bitWidth: 3 + access: read-write + enumeratedValues: + - name: WDT_SYS_RESET_LENGTH + usage: read-write + values: + - name: NS100 + description: 100ns + value: 0 + - name: NS200 + description: 200ns + value: 1 + - name: NS300 + description: 300ns + value: 2 + - name: NS400 + description: 400ns + value: 3 + - name: NS500 + description: 500ns + value: 4 + - name: NS800 + description: 800ns + value: 5 + - name: NS1600 + description: 1.6us + value: 6 + - name: NS3200 + description: 3.2us + value: 7 + - name: WDT_CPU_RESET_LENGTH + description: "length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us" + bitOffset: 18 + bitWidth: 3 + access: read-write + enumeratedValues: + - name: WDT_CPU_RESET_LENGTH + usage: read-write + values: + - name: NS100 + description: 100ns + value: 0 + - name: NS200 + description: 200ns + value: 1 + - name: NS300 + description: 300ns + value: 2 + - name: NS400 + description: 400ns + value: 3 + - name: NS500 + description: 500ns + value: 4 + - name: NS800 + description: 800ns + value: 5 + - name: NS1600 + description: 1.6us + value: 6 + - name: NS3200 + description: 3.2us + value: 7 + - name: WDT_LEVEL_INT_EN + description: When set level type interrupt generation is enabled + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: WDT_EDGE_INT_EN + description: When set edge type interrupt generation is enabled + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: WDT_STG3 + description: "Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system" + bitOffset: 23 + bitWidth: 2 + access: read-write + enumeratedValues: + - name: WDT_STG3 + usage: read-write + values: + - name: "OFF" + description: "Off" + value: 0 + - name: INTERRUPT + description: Interrupt + value: 1 + - name: RESET + description: Reset CPU + value: 2 + - name: RESET_SYS + description: Reset system + value: 3 + - name: WDT_STG2 + description: "Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system" + bitOffset: 25 + bitWidth: 2 + access: read-write + enumeratedValues: + - derived_from: WDT_STG3 + - name: WDT_STG1 + description: "Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system" + bitOffset: 27 + bitWidth: 2 + access: read-write + enumeratedValues: + - derived_from: WDT_STG3 + - name: WDT_STG0 + description: "Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system" + bitOffset: 29 + bitWidth: 2 + access: read-write + enumeratedValues: + - derived_from: WDT_STG3 + - name: WDT_EN + description: When set SWDT is enabled + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: WDTCONFIG1 + addressOffset: 76 + size: 32 + resetValue: 65536 + fields: + - name: WDT_CLK_PRESCALE + description: SWDT clock prescale value. Period = 12.5ns * value stored in this register + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: WDTCONFIG2 + addressOffset: 80 + size: 32 + resetValue: 26000000 + fields: + - name: WDT_STG0_HOLD + description: Stage 0 timeout value in SWDT clock cycles + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG3 + addressOffset: 84 + size: 32 + resetValue: 134217727 + fields: + - name: WDT_STG1_HOLD + description: Stage 1 timeout value in SWDT clock cycles + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG4 + addressOffset: 88 + size: 32 + resetValue: 1048575 + fields: + - name: WDT_STG2_HOLD + description: Stage 2 timeout value in SWDT clock cycles + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG5 + addressOffset: 92 + size: 32 + resetValue: 1048575 + fields: + - name: WDT_STG3_HOLD + description: Stage 3 timeout value in SWDT clock cycles + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTFEED + addressOffset: 96 + size: 32 + fields: + - name: WDT_FEED + description: Write any value will feed SWDT + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: WDTWPROTECT + addressOffset: 100 + size: 32 + resetValue: 1356348065 + fields: + - name: WDT_WKEY + description: If change its value from default then write protection is on. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RTCCALICFG + addressOffset: 104 + size: 32 + resetValue: 77824 + fields: + - name: RTC_CALI_START_CYCLING + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RTC_CALI_CLK_SEL + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: RTC_CALI_RDY + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: RTC_CALI_MAX + bitOffset: 16 + bitWidth: 15 + access: read-write + - name: RTC_CALI_START + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RTCCALICFG1 + addressOffset: 108 + size: 32 + fields: + - name: RTC_CALI_VALUE + bitOffset: 7 + bitWidth: 25 + access: read-only + - register: + name: LACTCONFIG + addressOffset: 112 + size: 32 + resetValue: 1610621696 + fields: + - name: LACT_RTC_ONLY + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: LACT_CPST_EN + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: LACT_LAC_EN + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: LACT_ALARM_EN + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: LACT_LEVEL_INT_EN + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: LACT_EDGE_INT_EN + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: LACT_DIVIDER + bitOffset: 13 + bitWidth: 16 + access: read-write + - name: LACT_AUTORELOAD + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LACT_INCREASE + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LACT_EN + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LACTRTC + addressOffset: 116 + size: 32 + fields: + - name: LACT_RTC_STEP_LEN + bitOffset: 6 + bitWidth: 26 + access: read-write + - register: + name: LACTLO + addressOffset: 120 + size: 32 + fields: + - name: LACT_LO + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: LACTHI + addressOffset: 124 + size: 32 + fields: + - name: LACT_HI + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: LACTUPDATE + addressOffset: 128 + size: 32 + fields: + - name: LACT_UPDATE + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: LACTALARMLO + addressOffset: 132 + size: 32 + fields: + - name: LACT_ALARM_LO + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LACTALARMHI + addressOffset: 136 + size: 32 + fields: + - name: LACT_ALARM_HI + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LACTLOADLO + addressOffset: 140 + size: 32 + fields: + - name: LACT_LOAD_LO + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LACTLOADHI + addressOffset: 144 + size: 32 + fields: + - name: LACT_LOAD_HI + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LACTLOAD + addressOffset: 148 + size: 32 + fields: + - name: LACT_LOAD + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: INT_ENA_TIMERS + addressOffset: 152 + size: 32 + fields: + - name: T0_INT_ENA + description: interrupt when timer0 alarm + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: T1_INT_ENA + description: interrupt when timer1 alarm + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: WDT_INT_ENA + description: Interrupt when an interrupt stage timeout + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: LACT_INT_ENA + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW_TIMERS + addressOffset: 156 + size: 32 + fields: + - name: T0_INT_RAW + description: interrupt when timer0 alarm + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: T1_INT_RAW + description: interrupt when timer1 alarm + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: WDT_INT_RAW + description: Interrupt when an interrupt stage timeout + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: LACT_INT_RAW + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_ST_TIMERS + addressOffset: 160 + size: 32 + fields: + - name: T0_INT_ST + description: interrupt when timer0 alarm + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: T1_INT_ST + description: interrupt when timer1 alarm + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: WDT_INT_ST + description: Interrupt when an interrupt stage timeout + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: LACT_INT_ST + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR_TIMERS + addressOffset: 164 + size: 32 + fields: + - name: T0_INT_CLR + description: interrupt when timer0 alarm + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: T1_INT_CLR + description: interrupt when timer1 alarm + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: WDT_INT_CLR + description: Interrupt when an interrupt stage timeout + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: LACT_INT_CLR + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: NTIMERS_DATE + addressOffset: 248 + size: 32 + resetValue: 23085712 + fields: + - name: NTIMERS_DATE + description: Version of this regfile + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + name: TIMGCLK + addressOffset: 252 + size: 32 + fields: + - name: CLK_EN + description: Force clock enable for this regfile + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: TIMG1 + description: Timer Group 1 + baseAddress: 1073086464 + interrupt: + - name: TG1_T0_LEVEL + value: 18 + - name: TG1_T1_LEVEL + value: 19 + - name: TG1_WDT_LEVEL + value: 20 + - name: TG1_LACT_LEVEL + value: 21 + - name: TG1_T0_EDGE + value: 62 + - name: TG1_T1_EDGE + value: 63 + - name: TG1_WDT_EDGE + value: 64 + - name: TG1_LACT_EDGE + value: 65 + derivedFrom: TIMG0 + - name: TWAI0 + description: Two-Wire Automotive Interface + groupName: TWAI + baseAddress: 1073131520 + addressBlock: + - offset: 0 + size: 108 + usage: registers + interrupt: + - name: TWAI0 + value: 45 + registers: + - register: + name: MODE + description: Mode Register + addressOffset: 0 + size: 32 + resetValue: 1 + fields: + - name: RESET_MODE + description: "This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LISTEN_ONLY_MODE + description: "1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SELF_TEST_MODE + description: "1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_FILTER_MODE + description: "This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode." + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: CMD + description: Command Register + addressOffset: 4 + size: 32 + fields: + - name: TX_REQ + description: Set the bit to 1 to allow the driving nodes start transmission. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ABORT_TX + description: Set the bit to 1 to cancel a pending transmission request. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RELEASE_BUF + description: Set the bit to 1 to release the RX buffer. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CLR_OVERRUN + description: Set the bit to 1 to clear the data overrun status bit. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SELF_RX_REQ + description: Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously. + bitOffset: 4 + bitWidth: 1 + access: write-only + - register: + name: STATUS + description: Status register + addressOffset: 8 + size: 32 + fields: + - name: RX_BUF_ST + description: "1: The data in the RX buffer is not empty, with at least one received data packet." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OVERRUN_ST + description: "1: The RX FIFO is full and data overrun has occurred." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TX_BUF_ST + description: "1: The TX buffer is empty, the CPU may write a message into it." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_COMPLETE + description: "1: The TWAI controller has successfully received a packet from the bus." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: RX_ST + description: "1: The TWAI Controller is receiving a message from the bus." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TX_ST + description: "1: The TWAI Controller is transmitting a message to the bus." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ERR_ST + description: "1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG." + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BUS_OFF_ST + description: "1: In bus-off status, the TWAI Controller is no longer involved in bus activities." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: MISS_ST + description: "This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete" + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INT_RAW + description: Interrupt Register + addressOffset: 12 + size: 32 + fields: + - name: RX_INT_ST + description: "Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_INT_ST + description: "Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ERR_WARN_INT_ST + description: "Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0)." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: OVERRUN_INT_ST + description: "Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: ERR_PASSIVE_INT_ST + description: "Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ARB_LOST_INT_ST + description: "Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated." + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BUS_ERR_INT_ST + description: "Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus." + bitOffset: 7 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt Enable Register + addressOffset: 16 + size: 32 + fields: + - name: RX_INT_ENA + description: Set this bit to 1 to enable receive interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_INT_ENA + description: Set this bit to 1 to enable transmit interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ERR_WARN_INT_ENA + description: Set this bit to 1 to enable error warning interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OVERRUN_INT_ENA + description: Set this bit to 1 to enable data overrun interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ERR_PASSIVE_INT_ENA + description: Set this bit to 1 to enable error passive interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: ARB_LOST_INT_ENA + description: Set this bit to 1 to enable arbitration lost interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BUS_ERR_INT_ENA + description: Set this bit to 1 to enable error interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: BUS_TIMING_0 + description: Bus Timing Register 0 + addressOffset: 24 + size: 32 + fields: + - name: BAUD_PRESC + description: "Baud Rate Prescaler, determines the frequency dividing ratio." + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: SYNC_JUMP_WIDTH + description: "Synchronization Jump Width (SJW), 1 \\verb+~+ 14 Tq wide." + bitOffset: 6 + bitWidth: 2 + access: read-write + - register: + name: BUS_TIMING_1 + description: Bus Timing Register 1 + addressOffset: 28 + size: 32 + fields: + - name: TIME_SEG1 + description: The width of PBS1. + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: TIME_SEG2 + description: The width of PBS2. + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: TIME_SAMP + description: "The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times" + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: ARB_LOST_CAP + description: Arbitration Lost Capture Register + addressOffset: 44 + size: 32 + fields: + - name: ARB_LOST_CAP + description: This register contains information about the bit position of lost arbitration. + bitOffset: 0 + bitWidth: 5 + access: read-only + - register: + name: ERR_CODE_CAP + description: Error Code Capture Register + addressOffset: 48 + size: 32 + fields: + - name: ECC_SEGMENT + description: "This register contains information about the location of errors, see Table 181 for details." + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: ECC_DIRECTION + description: "This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ECC_TYPE + description: "This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error" + bitOffset: 6 + bitWidth: 2 + access: read-only + - register: + name: ERR_WARNING_LIMIT + description: Error Warning Limit Register + addressOffset: 52 + size: 32 + resetValue: 96 + fields: + - name: ERR_WARNING_LIMIT + description: "Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid)." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: RX_ERR_CNT + description: Receive Error Counter Register + addressOffset: 56 + size: 32 + fields: + - name: RX_ERR_CNT + description: "The RX error counter register, reflects value changes under reception status." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: TX_ERR_CNT + description: Transmit Error Counter Register + addressOffset: 60 + size: 32 + fields: + - name: TX_ERR_CNT + description: "The TX error counter register, reflects value changes under transmission status." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_0 + description: Data register 0 + addressOffset: 64 + size: 32 + fields: + - name: TX_BYTE_0 + description: "In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_1 + description: Data register 1 + addressOffset: 68 + size: 32 + fields: + - name: TX_BYTE_1 + description: "In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_2 + description: Data register 2 + addressOffset: 72 + size: 32 + fields: + - name: TX_BYTE_2 + description: "In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_3 + description: Data register 3 + addressOffset: 76 + size: 32 + fields: + - name: TX_BYTE_3 + description: "In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_4 + description: Data register 4 + addressOffset: 80 + size: 32 + fields: + - name: TX_BYTE_4 + description: "In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_5 + description: Data register 5 + addressOffset: 84 + size: 32 + fields: + - name: TX_BYTE_5 + description: "In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_6 + description: Data register 6 + addressOffset: 88 + size: 32 + fields: + - name: TX_BYTE_6 + description: "In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_7 + description: Data register 7 + addressOffset: 92 + size: 32 + fields: + - name: TX_BYTE_7 + description: "In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_8 + description: Data register 8 + addressOffset: 96 + size: 32 + fields: + - name: TX_BYTE_8 + description: Stored the 8th byte information of the data to be transmitted under operating mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_9 + description: Data register 9 + addressOffset: 100 + size: 32 + fields: + - name: TX_BYTE_9 + description: Stored the 9th byte information of the data to be transmitted under operating mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_10 + description: Data register 10 + addressOffset: 104 + size: 32 + fields: + - name: TX_BYTE_10 + description: Stored the 10th byte information of the data to be transmitted under operating mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_11 + description: Data register 11 + addressOffset: 108 + size: 32 + fields: + - name: TX_BYTE_11 + description: Stored the 11th byte information of the data to be transmitted under operating mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_12 + description: Data register 12 + addressOffset: 112 + size: 32 + fields: + - name: TX_BYTE_12 + description: Stored the 12th byte information of the data to be transmitted under operating mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: RX_MESSAGE_CNT + description: Receive Message Counter Register + addressOffset: 116 + size: 32 + fields: + - name: RX_MESSAGE_COUNTER + description: This register reflects the number of messages available within the RX FIFO. + bitOffset: 0 + bitWidth: 7 + access: read-only + - register: + name: CLOCK_DIVIDER + description: Clock Divider register + addressOffset: 124 + size: 32 + fields: + - name: CD + description: These bits are used to configure frequency dividing coefficients of the external CLKOUT pin. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CLOCK_OFF + description: "This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: UART0 + description: UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + groupName: UART + baseAddress: 1072955392 + addressBlock: + - offset: 0 + size: 124 + usage: registers + interrupt: + - name: UART0 + value: 34 + registers: + - register: + name: FIFO + addressOffset: 0 + size: 32 + fields: + - name: RXFIFO_RD_BYTE + description: This register stores one byte data read by rx fifo. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: INT_RAW + addressOffset: 4 + size: 32 + fields: + - name: RXFIFO_FULL_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd). + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_EMPTY_INT_RAW + description: "This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) ." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: PARITY_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the parity error of data. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FRM_ERR_INT_RAW + description: "This interrupt raw bit turns to high level when receiver detects data's frame error ." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives more data than the fifo can store. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DSR_CHG_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CTS_CHG_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BRK_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: RXFIFO_TOUT_INT_RAW + description: This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SW_XON_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SW_XOFF_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: GLITCH_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the start bit. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TX_BRK_DONE_INT_RAW + description: "This interrupt raw bit turns to high level when transmitter completes sendding 0 after all the datas in transmitter's fifo are send." + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: TX_BRK_IDLE_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the last data has been send. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter has send all the data in fifo. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: RS485_PARITY_ERR_INT_RAW + description: This interrupt raw bit turns to high level when rs485 detects the parity error. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: RS485_FRM_ERR_INT_RAW + description: This interrupt raw bit turns to high level when rs485 detects the data frame error. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: RS485_CLASH_INT_RAW + description: This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: AT_CMD_CHAR_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars. + bitOffset: 18 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + addressOffset: 8 + size: 32 + fields: + - name: RXFIFO_FULL_INT_ST + description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_EMPTY_INT_ST + description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: PARITY_ERR_INT_ST + description: This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FRM_ERR_INT_ST + description: This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_ST + description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DSR_CHG_INT_ST + description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CTS_CHG_INT_ST + description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BRK_DET_INT_ST + description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: RXFIFO_TOUT_INT_ST + description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SW_XON_INT_ST + description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SW_XOFF_INT_ST + description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: GLITCH_DET_INT_ST + description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TX_BRK_DONE_INT_ST + description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: TX_BRK_IDLE_DONE_INT_ST + description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_ST + description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: RS485_PARITY_ERR_INT_ST + description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: RS485_FRM_ERR_INT_ST + description: This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: RS485_CLASH_INT_ST + description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: AT_CMD_CHAR_DET_INT_ST + description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + bitOffset: 18 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + addressOffset: 12 + size: 32 + fields: + - name: RXFIFO_FULL_INT_ENA + description: This is the enable bit for rxfifo_full_int_st register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_EMPTY_INT_ENA + description: This is the enable bit for rxfifo_full_int_st register. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PARITY_ERR_INT_ENA + description: This is the enable bit for parity_err_int_st register. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FRM_ERR_INT_ENA + description: This is the enable bit for frm_err_int_st register. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_ENA + description: This is the enable bit for rxfifo_ovf_int_st register. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DSR_CHG_INT_ENA + description: This is the enable bit for dsr_chg_int_st register. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CTS_CHG_INT_ENA + description: This is the enable bit for cts_chg_int_st register. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BRK_DET_INT_ENA + description: This is the enable bit for brk_det_int_st register. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RXFIFO_TOUT_INT_ENA + description: This is the enable bit for rxfifo_tout_int_st register. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SW_XON_INT_ENA + description: This is the enable bit for sw_xon_int_st register. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SW_XOFF_INT_ENA + description: This is the enable bit for sw_xoff_int_st register. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GLITCH_DET_INT_ENA + description: This is the enable bit for glitch_det_int_st register. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_BRK_DONE_INT_ENA + description: This is the enable bit for tx_brk_done_int_st register. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_BRK_IDLE_DONE_INT_ENA + description: This is the enable bit for tx_brk_idle_done_int_st register. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_ENA + description: This is the enable bit for tx_done_int_st register. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RS485_PARITY_ERR_INT_ENA + description: This is the enable bit for rs485_parity_err_int_st register. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RS485_FRM_ERR_INT_ENA + description: This is the enable bit for rs485_parity_err_int_st register. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RS485_CLASH_INT_ENA + description: This is the enable bit for rs485_clash_int_st register. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: AT_CMD_CHAR_DET_INT_ENA + description: This is the enable bit for at_cmd_char_det_int_st register. + bitOffset: 18 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + addressOffset: 16 + size: 32 + fields: + - name: RXFIFO_FULL_INT_CLR + description: Set this bit to clear the rxfifo_full_int_raw interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TXFIFO_EMPTY_INT_CLR + description: Set this bit to clear txfifo_empty_int_raw interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: PARITY_ERR_INT_CLR + description: Set this bit to clear parity_err_int_raw interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: FRM_ERR_INT_CLR + description: Set this bit to clear frm_err_int_raw interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: RXFIFO_OVF_INT_CLR + description: Set this bit to clear rxfifo_ovf_int_raw interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: DSR_CHG_INT_CLR + description: Set this bit to clear the dsr_chg_int_raw interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CTS_CHG_INT_CLR + description: Set this bit to clear the cts_chg_int_raw interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: BRK_DET_INT_CLR + description: Set this bit to clear the brk_det_int_raw interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: RXFIFO_TOUT_INT_CLR + description: Set this bit to clear the rxfifo_tout_int_raw interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SW_XON_INT_CLR + description: Set this bit to clear the sw_xon_int_raw interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SW_XOFF_INT_CLR + description: Set this bit to clear the sw_xon_int_raw interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: GLITCH_DET_INT_CLR + description: Set this bit to clear the glitch_det_int_raw interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TX_BRK_DONE_INT_CLR + description: Set this bit to clear the tx_brk_done_int_raw interrupt.. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: TX_BRK_IDLE_DONE_INT_CLR + description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: TX_DONE_INT_CLR + description: Set this bit to clear the tx_done_int_raw interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: RS485_PARITY_ERR_INT_CLR + description: Set this bit to clear the rs485_parity_err_int_raw interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: RS485_FRM_ERR_INT_CLR + description: Set this bit to clear the rs485_frm_err_int_raw interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: RS485_CLASH_INT_CLR + description: Set this bit to clear the rs485_clash_int_raw interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: AT_CMD_CHAR_DET_INT_CLR + description: Set this bit to clear the at_cmd_char_det_int_raw interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - register: + name: CLKDIV + addressOffset: 20 + size: 32 + resetValue: 694 + fields: + - name: CLKDIV + description: "The register value is the integer part of the frequency divider's factor." + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: FRAG + description: "The register value is the decimal part of the frequency divider's factor." + bitOffset: 20 + bitWidth: 4 + access: read-write + - register: + name: AUTOBAUD + addressOffset: 24 + size: 32 + resetValue: 4096 + fields: + - name: EN + description: This is the enable bit for detecting baudrate. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: GLITCH_FILT + description: when input pulse width is lower then this value igore this pulse.this register is used in autobaud detect process. + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: STATUS + addressOffset: 28 + size: 32 + fields: + - name: RXFIFO_CNT + description: "(rx_mem_cnt rxfifo_cnt) stores the byte num of valid datas in receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits." + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: ST_URX_OUT + description: "This register stores the value of receiver's finite state machine. 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1" + bitOffset: 8 + bitWidth: 4 + access: read-only + - name: DSRN + description: This register stores the level value of the internal uart dsr signal. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: CTSN + description: This register stores the level value of the internal uart cts signal. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: RXD + description: This register stores the level value of the internal uart rxd signal. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TXFIFO_CNT + description: "(tx_mem_cnt txfifo_cnt) stores the byte num of valid datas in transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits." + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: ST_UTX_OUT + description: "This register stores the value of transmitter's finite state machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1" + bitOffset: 24 + bitWidth: 4 + access: read-only + - name: DTRN + description: The register represent the level value of the internal uart dsr signal. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: RTSN + description: This register represent the level value of the internal uart cts signal. + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: TXD + description: This register represent the level value of the internal uart rxd signal. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CONF0 + addressOffset: 32 + size: 32 + resetValue: 134217756 + fields: + - name: PARITY + description: "This register is used to configure the parity check mode. 0:even 1:odd" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PARITY_EN + description: Set this bit to enable uart parity check. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BIT_NUM + description: "This registe is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: STOP_BIT_NUM + description: "This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: SW_RTS + description: This register is used to configure the software rts signal which is used in software flow control. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SW_DTR + description: This register is used to configure the software dtr signal which is used in software flow control.. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TXD_BRK + description: Set this bit to enbale transmitter to send 0 when the process of sending data is done. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: IRDA_DPLX + description: Set this bit to enable irda loopback mode. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: IRDA_TX_EN + description: This is the start enable bit for irda transmitter. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: IRDA_WCTL + description: "1.the irda transmitter's 11th bit is the same to the 10th bit. 0.set irda transmitter's 11th bit to 0." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: IRDA_TX_INV + description: "Set this bit to inverse the level value of irda transmitter's level." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: IRDA_RX_INV + description: "Set this bit to inverse the level value of irda receiver's level." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: LOOPBACK + description: Set this bit to enable uart loopback test mode. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TX_FLOW_EN + description: "Set this bit to enable transmitter's flow control function." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: IRDA_EN + description: Set this bit to enable irda protocol. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RXFIFO_RST + description: "Set this bit to reset uart receiver's fifo." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: TXFIFO_RST + description: "Set this bit to reset uart transmitter's fifo." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RXD_INV + description: Set this bit to inverse the level value of uart rxd signal. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: CTS_INV + description: Set this bit to inverse the level value of uart cts signal. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: DSR_INV + description: Set this bit to inverse the level value of uart dsr signal. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: TXD_INV + description: Set this bit to inverse the level value of uart txd signal. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RTS_INV + description: Set this bit to inverse the level value of uart rts signal. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: DTR_INV + description: Set this bit to inverse the level value of uart dtr signal. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: 1.force clock on for registers.support clock only when write registers + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: ERR_WR_MASK + description: 1.receiver stops storing data int fifo when data is wrong. 0.receiver stores the data even if the received data is wrong. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TICK_REF_ALWAYS_ON + description: "This register is used to select the clock.1.apb clock 0:ref_tick" + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: CONF1 + addressOffset: 36 + size: 32 + resetValue: 24672 + fields: + - name: RXFIFO_FULL_THRHD + description: When receiver receives more data than its threshold value.receiver will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd). + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: TXFIFO_EMPTY_THRHD + description: when the data amount in transmitter fifo is less than its threshold value. it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd) + bitOffset: 8 + bitWidth: 7 + access: read-write + - name: RX_FLOW_THRHD + description: when receiver receives more data than its threshold value. receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd). + bitOffset: 16 + bitWidth: 7 + access: read-write + - name: RX_FLOW_EN + description: "This is the flow enable bit for uart receiver. 1:choose software flow control with configuring sw_rts signal" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: RX_TOUT_THRHD + description: This register is used to configure the timeout value for uart receiver receiving a byte. + bitOffset: 24 + bitWidth: 7 + access: read-write + - name: RX_TOUT_EN + description: "This is the enble bit for uart receiver's timeout function." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LOWPULSE + addressOffset: 40 + size: 32 + resetValue: 1048575 + fields: + - name: MIN_CNT + description: This register stores the value of the minimum duration time for the low level pulse. it is used in baudrate-detect process. + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: HIGHPULSE + addressOffset: 44 + size: 32 + resetValue: 1048575 + fields: + - name: MIN_CNT + description: This register stores the value of the maxinum duration time for the high level pulse. it is used in baudrate-detect process. + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: RXD_CNT + addressOffset: 48 + size: 32 + fields: + - name: RXD_EDGE_CNT + description: This register stores the count of rxd edge change. it is used in baudrate-detect process. + bitOffset: 0 + bitWidth: 10 + access: read-only + - register: + name: FLOW_CONF + addressOffset: 52 + size: 32 + fields: + - name: SW_FLOW_CON_EN + description: Set this bit to enable software flow control. it is used with register sw_xon or sw_xoff . + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: XONOFF_DEL + description: Set this bit to remove flow control char from the received data. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FORCE_XON + description: Set this bit to clear ctsn to stop the transmitter from sending data. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FORCE_XOFF + description: Set this bit to set ctsn to enable the transmitter to go on sending data. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SEND_XON + description: Set this bit to send xon char. it is cleared by hardware automatically. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SEND_XOFF + description: Set this bit to send xoff char. it is cleared by hardware automatically. + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: SLEEP_CONF + addressOffset: 56 + size: 32 + resetValue: 240 + fields: + - name: ACTIVE_THRESHOLD + description: When the input rxd edge changes more than this register value. the uart is active from light sleeping mode. + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: SWFC_CONF + addressOffset: 60 + size: 32 + resetValue: 319938560 + fields: + - name: XON_THRESHOLD + description: "when the data amount in receiver's fifo is more than this register value. it will send a xoff char with uart_sw_flow_con_en set to 1." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: XOFF_THRESHOLD + description: "When the data amount in receiver's fifo is less than this register value. it will send a xon char with uart_sw_flow_con_en set to 1." + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: XON_CHAR + description: This register stores the xon flow control char. + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: XOFF_CHAR + description: This register stores the xoff flow control char. + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: IDLE_CONF + addressOffset: 64 + size: 32 + resetValue: 10748160 + fields: + - name: RX_IDLE_THRHD + description: when receiver takes more time than this register value to receive a byte data. it will produce frame end signal for uhci to stop receiving data. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: TX_IDLE_NUM + description: This register is used to configure the duration time between transfers. + bitOffset: 10 + bitWidth: 10 + access: read-write + - name: TX_BRK_NUM + description: This register is used to configure the num of 0 send after the process of sending data is done. it is active when txd_brk is set to 1. + bitOffset: 20 + bitWidth: 8 + access: read-write + - register: + name: RS485_CONF + addressOffset: 68 + size: 32 + fields: + - name: RS485_EN + description: Set this bit to choose rs485 mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DL0_EN + description: Set this bit to delay the stop bit by 1 bit. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DL1_EN + description: Set this bit to delay the stop bit by 1 bit. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RS485TX_RX_EN + description: "Set this bit to enable loopback transmitter's output data signal to receiver's input data signal." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RS485RXBY_TX_EN + description: "1: enable rs485's transmitter to send data when rs485's receiver is busy. 0:rs485's transmitter should not send data when its receiver is busy." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RS485_RX_DLY_NUM + description: "This register is used to delay the receiver's internal data signal." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RS485_TX_DLY_NUM + description: "This register is used to delay the transmitter's internal data signal." + bitOffset: 6 + bitWidth: 4 + access: read-write + - register: + name: AT_CMD_PRECNT + addressOffset: 72 + size: 32 + resetValue: 1600000 + fields: + - name: PRE_IDLE_NUM + description: This register is used to configure the idle duration time before the first at_cmd is received by receiver. when the the duration is less than this register value it will not take the next data received as at_cmd char. + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: AT_CMD_POSTCNT + addressOffset: 76 + size: 32 + resetValue: 1600000 + fields: + - name: POST_IDLE_NUM + description: This register is used to configure the duration time between the last at_cmd and the next data. when the duration is less than this register value it will not take the previous data as at_cmd char. + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: AT_CMD_GAPTOUT + addressOffset: 80 + size: 32 + resetValue: 7680 + fields: + - name: RX_GAP_TOUT + description: This register is used to configure the duration time between the at_cmd chars. when the duration time is less than this register value it will not take the datas as continous at_cmd chars. + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: AT_CMD_CHAR + addressOffset: 84 + size: 32 + resetValue: 811 + fields: + - name: AT_CMD_CHAR + description: This register is used to configure the content of at_cmd char. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CHAR_NUM + description: This register is used to configure the num of continous at_cmd chars received by receiver. + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: MEM_CONF + addressOffset: 88 + size: 32 + resetValue: 136 + fields: + - name: MEM_PD + description: Set this bit to power down mem.when reg_mem_pd registers in the 3 uarts are all set to 1 mem will enter low power mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_SIZE + description: "This register is used to configure the amount of mem allocated to receiver's fifo. the default byte num is 128." + bitOffset: 3 + bitWidth: 4 + access: read-write + - name: TX_SIZE + description: "This register is used to configure the amount of mem allocated to transmitter's fifo.the default byte num is 128." + bitOffset: 7 + bitWidth: 4 + access: read-write + - name: RX_FLOW_THRHD_H3 + description: "Refer to the rx_flow_thrhd's description." + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: RX_TOUT_THRHD_H3 + description: "Refer to the rx_tout_thrhd's description." + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: XON_THRESHOLD_H2 + description: "Refer to the uart_xon_threshold's description." + bitOffset: 21 + bitWidth: 2 + access: read-write + - name: XOFF_THRESHOLD_H2 + description: "Refer to the uart_xoff_threshold's description." + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: RX_MEM_FULL_THRHD + description: "Refer to the rxfifo_full_thrhd's description." + bitOffset: 25 + bitWidth: 3 + access: read-write + - name: TX_MEM_EMPTY_THRHD + description: "Refer to txfifo_empty_thrhd's description." + bitOffset: 28 + bitWidth: 3 + access: read-write + - register: + name: MEM_TX_STATUS + addressOffset: 92 + size: 32 + fields: + - name: MEM_TX_STATUS + bitOffset: 0 + bitWidth: 24 + access: read-only + - register: + name: MEM_RX_STATUS + addressOffset: 96 + size: 32 + fields: + - name: MEM_RX_STATUS + description: This register stores the current uart rx mem read address and rx mem write address + bitOffset: 0 + bitWidth: 24 + access: read-only + - name: MEM_RX_RD_ADDR + description: This register stores the rx mem read address + bitOffset: 2 + bitWidth: 11 + access: read-only + - name: MEM_RX_WR_ADDR + description: This register stores the rx mem write address + bitOffset: 13 + bitWidth: 11 + access: read-only + - register: + name: MEM_CNT_STATUS + addressOffset: 100 + size: 32 + fields: + - name: RX_MEM_CNT + description: "Refer to the rxfifo_cnt's description." + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: TX_MEM_CNT + description: "Refer to the txfifo_cnt's description." + bitOffset: 3 + bitWidth: 3 + access: read-only + - register: + name: POSPULSE + addressOffset: 104 + size: 32 + resetValue: 1048575 + fields: + - name: POSEDGE_MIN_CNT + description: This register stores the count of rxd posedge edge. it is used in boudrate-detect process. + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: NEGPULSE + addressOffset: 108 + size: 32 + resetValue: 1048575 + fields: + - name: NEGEDGE_MIN_CNT + description: This register stores the count of rxd negedge edge. it is used in boudrate-detect process. + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: DATE + addressOffset: 120 + size: 32 + resetValue: 353510656 + fields: + - name: DATE + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ID + addressOffset: 124 + size: 32 + resetValue: 1280 + fields: + - name: ID + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: UART1 + description: UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + baseAddress: 1073020928 + interrupt: + - name: UART1 + value: 35 + derivedFrom: UART0 + - name: UART2 + description: UART (Universal Asynchronous Receiver-Transmitter) Controller 2 + baseAddress: 1073143808 + interrupt: + - name: UART2 + value: 36 + derivedFrom: UART0 + - name: UHCI0 + description: Universal Host Controller Interface 0 + groupName: UHCI + baseAddress: 1073037312 + addressBlock: + - offset: 0 + size: 200 + usage: registers + interrupt: + - name: UHCI0 + value: 12 + registers: + - register: + name: CONF0 + addressOffset: 0 + size: 32 + resetValue: 3604736 + fields: + - name: IN_RST + description: Set this bit to reset in link operations. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_RST + description: Set this bit to reset out link operations. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AHBM_FIFO_RST + description: Set this bit to reset dma ahb fifo. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: AHBM_RST + description: Set this bit to reset dma ahb interface. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: IN_LOOP_TEST + description: Set this bit to enable loop test for in links. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUT_LOOP_TEST + description: Set this bit to enable loop test for out links. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUT_AUTO_WRBACK + description: "when in link's length is 0 go on to use the next in link automatically." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUT_NO_RESTART_CLR + description: "don't use" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_EOF_MODE + description: Set this bit to produce eof after DMA pops all data clear this bit to produce eof after DMA pushes all data + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: UART0_CE + description: Set this bit to use UART to transmit or receive data. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: UART1_CE + description: Set this bit to use UART1 to transmit or receive data. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: UART2_CE + description: Set this bit to use UART2 to transmit or receive data. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: OUTDSCR_BURST_EN + description: Set this bit to enable DMA in links to use burst mode. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: INDSCR_BURST_EN + description: Set this bit to enable DMA out links to use burst mode. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: OUT_DATA_BURST_EN + description: Set this bit to enable DMA burst MODE + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: MEM_TRANS_EN + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SEPER_EN + description: Set this bit to use special char to separate the data frame. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: HEAD_EN + description: Set this bit to enable to use head packet before the data frame. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: CRC_REC_EN + description: "Set this bit to enable receiver''s ability of crc calculation when crc_en bit in head packet is 1 then there will be crc bytes after data_frame" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: UART_IDLE_EOF_EN + description: Set this bit to enable to use idle time when the idle time after data frame is satisfied this means the end of a data frame. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: LEN_EOF_EN + description: Set this bit to enable to use packet_len in packet head when the received data is equal to packet_len this means the end of a data frame. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: ENCODE_CRC_EN + description: Set this bit to enable crc calculation for data frame when bit6 in the head packet is 1. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: Set this bit to enable clock-gating for read or write registers. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: UART_RX_BRK_EOF_EN + description: Set this bit to enable to use brk char as the end of a data frame. + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + addressOffset: 4 + size: 32 + fields: + - name: RX_START_INT_RAW + description: when a separator char has been send it will produce uhci_rx_start_int interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_START_INT_RAW + description: when DMA detects a separator char it will produce uhci_tx_start_int interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_RAW + description: when DMA takes a lot of time to receive a data it will produce uhci_rx_hung_int interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_RAW + description: when DMA takes a lot of time to read a data from RAM it will produce uhci_tx_hung_int interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: IN_DONE_INT_RAW + description: when a in link descriptor has been completed it will produce uhci_in_done_int interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: IN_SUC_EOF_INT_RAW + description: when a data packet has been received it will produce uhci_in_suc_eof_int interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: IN_ERR_EOF_INT_RAW + description: when there are some errors about eof in in link descriptor it will produce uhci_in_err_eof_int interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUT_DONE_INT_RAW + description: when a out link descriptor is completed it will produce uhci_out_done_int interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OUT_EOF_INT_RAW + description: "when the current descriptor's eof bit is 1 it will produce uhci_out_eof_int interrupt." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: IN_DSCR_ERR_INT_RAW + description: when there are some errors about the out link descriptor it will produce uhci_in_dscr_err_int interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: OUT_DSCR_ERR_INT_RAW + description: when there are some errors about the in link descriptor it will produce uhci_out_dscr_err_int interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: IN_DSCR_EMPTY_INT_RAW + description: when there are not enough in links for DMA it will produce uhci_in_dscr_err_int interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: OUTLINK_EOF_ERR_INT_RAW + description: when there are some errors about eof in outlink descriptor it will produce uhci_outlink_eof_err_int interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: OUT_TOTAL_EOF_INT_RAW + description: When all data have been send it will produce uhci_out_total_eof_int interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SEND_S_Q_INT_RAW + description: When use single send registers to send a short packets it will produce this interrupt when dma has send the short packet. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SEND_A_Q_INT_RAW + description: When use always_send registers to send a series of short packets it will produce this interrupt when dma has send the short packet. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: DMA_INFIFO_FULL_WM_INT_RAW + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + addressOffset: 8 + size: 32 + fields: + - name: RX_START_INT_ST + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_START_INT_ST + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_ST + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_ST + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: IN_DONE_INT_ST + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: IN_SUC_EOF_INT_ST + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: IN_ERR_EOF_INT_ST + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUT_DONE_INT_ST + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OUT_EOF_INT_ST + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: IN_DSCR_ERR_INT_ST + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: OUT_DSCR_ERR_INT_ST + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: IN_DSCR_EMPTY_INT_ST + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: OUTLINK_EOF_ERR_INT_ST + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: OUT_TOTAL_EOF_INT_ST + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SEND_S_Q_INT_ST + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SEND_A_Q_INT_ST + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: DMA_INFIFO_FULL_WM_INT_ST + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + addressOffset: 12 + size: 32 + fields: + - name: RX_START_INT_ENA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_START_INT_ENA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_HUNG_INT_ENA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_HUNG_INT_ENA + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: IN_DONE_INT_ENA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF_INT_ENA + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF_INT_ENA + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUT_DONE_INT_ENA + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_EOF_INT_ENA + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR_INT_ENA + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR_INT_ENA + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY_INT_ENA + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: OUTLINK_EOF_ERR_INT_ENA + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF_INT_ENA + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SEND_S_Q_INT_ENA + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SEND_A_Q_INT_ENA + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DMA_INFIFO_FULL_WM_INT_ENA + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + addressOffset: 16 + size: 32 + fields: + - name: RX_START_INT_CLR + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TX_START_INT_CLR + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_HUNG_INT_CLR + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TX_HUNG_INT_CLR + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: IN_DONE_INT_CLR + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: IN_SUC_EOF_INT_CLR + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: IN_ERR_EOF_INT_CLR + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: OUT_DONE_INT_CLR + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: OUT_EOF_INT_CLR + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: IN_DSCR_ERR_INT_CLR + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: OUT_DSCR_ERR_INT_CLR + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: IN_DSCR_EMPTY_INT_CLR + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: OUTLINK_EOF_ERR_INT_CLR + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: OUT_TOTAL_EOF_INT_CLR + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SEND_S_Q_INT_CLR + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SEND_A_Q_INT_CLR + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: DMA_INFIFO_FULL_WM_INT_CLR + bitOffset: 16 + bitWidth: 1 + access: write-only + - register: + name: DMA_OUT_STATUS + addressOffset: 20 + size: 32 + resetValue: 2 + fields: + - name: OUT_FULL + description: "1:DMA out link descriptor's fifo is full." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUT_EMPTY + description: "1:DMA in link descriptor's fifo is empty." + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: DMA_OUT_PUSH + addressOffset: 24 + size: 32 + fields: + - name: OUTFIFO_WDATA + description: "This is the data need to be pushed into out link descriptor's fifo." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: OUTFIFO_PUSH + description: "Set this bit to push data in out link descriptor's fifo." + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: DMA_IN_STATUS + addressOffset: 28 + size: 32 + resetValue: 2 + fields: + - name: IN_FULL + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: IN_EMPTY + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_ERR_CAUSE + description: "This register stores the errors caused in out link descriptor's data packet." + bitOffset: 4 + bitWidth: 3 + access: read-only + - register: + name: DMA_IN_POP + addressOffset: 32 + size: 32 + fields: + - name: INFIFO_RDATA + description: "This register stores the data pop from in link descriptor's fifo." + bitOffset: 0 + bitWidth: 12 + access: read-only + - name: INFIFO_POP + description: "Set this bit to pop data in in link descriptor's fifo." + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: DMA_OUT_LINK + addressOffset: 36 + size: 32 + fields: + - name: OUTLINK_ADDR + description: "This register stores the least 20 bits of the first out link descriptor's address." + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: OUTLINK_STOP + description: Set this bit to stop dealing with the out link descriptors. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: OUTLINK_START + description: Set this bit to start dealing with the out link descriptors. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: OUTLINK_RESTART + description: Set this bit to mount on new out link descriptors + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: OUTLINK_PARK + description: "1£º the out link descriptor's fsm is in idle state. 0:the out link descriptor's fsm is working." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: DMA_IN_LINK + addressOffset: 40 + size: 32 + resetValue: 1048576 + fields: + - name: INLINK_ADDR + description: "This register stores the least 20 bits of the first in link descriptor's address." + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: INLINK_AUTO_RET + description: "1:when a packet is wrong in link descriptor returns to the descriptor which is lately used." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: INLINK_STOP + description: Set this bit to stop dealing with the in link descriptors. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: INLINK_START + description: Set this bit to start dealing with the in link descriptors. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: INLINK_RESTART + description: Set this bit to mount on new in link descriptors + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: INLINK_PARK + description: "1:the in link descriptor's fsm is in idle state. 0:the in link descriptor's fsm is working" + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CONF1 + addressOffset: 44 + size: 32 + resetValue: 51 + fields: + - name: CHECK_SUM_EN + description: Set this bit to enable decoder to check check_sum in packet header. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CHECK_SEQ_EN + description: Set this bit to enable decoder to check seq num in packet header. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CRC_DISABLE + description: Set this bit to disable crc calculation. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SAVE_HEAD + description: Set this bit to save packet header . + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_CHECK_SUM_RE + description: Set this bit to enable hardware replace check_sum in packet header automatically. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TX_ACK_NUM_RE + description: Set this bit to enable hardware replace ack num in packet header automatically. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CHECK_OWNER + description: Set this bit to check the owner bit in link descriptor. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: WAIT_SW_START + description: Set this bit to enable software way to add packet header. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SW_START + description: Set this bit to start inserting the packet header. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DMA_INFIFO_FULL_THRS + description: "when data amount in link descriptor's fifo is more than this register value it will produce uhci_dma_infifo_full_wm_int interrupt." + bitOffset: 9 + bitWidth: 12 + access: read-write + - register: + name: STATE0 + addressOffset: 48 + size: 32 + fields: + - name: STATE0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: STATE1 + addressOffset: 52 + size: 32 + fields: + - name: STATE1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DMA_OUT_EOF_DES_ADDR + addressOffset: 56 + size: 32 + fields: + - name: OUT_EOF_DES_ADDR + description: This register stores the address of out link descriptoir when eof bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DMA_IN_SUC_EOF_DES_ADDR + addressOffset: 60 + size: 32 + fields: + - name: IN_SUC_EOF_DES_ADDR + description: This register stores the address of in link descriptor when eof bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DMA_IN_ERR_EOF_DES_ADDR + addressOffset: 64 + size: 32 + fields: + - name: IN_ERR_EOF_DES_ADDR + description: This register stores the address of in link descriptor when there are some errors in this descriptor. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DMA_OUT_EOF_BFR_DES_ADDR + addressOffset: 68 + size: 32 + fields: + - name: OUT_EOF_BFR_DES_ADDR + description: This register stores the address of out link descriptor when there are some errors in this descriptor. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: AHB_TEST + addressOffset: 72 + size: 32 + fields: + - name: AHB_TESTMODE + description: "bit2 is ahb bus test enable ,bit1 is used to choose wrtie(1) or read(0) mode. bit0 is used to choose test only once(1) or continue(0)" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: AHB_TESTADDR + description: "The two bits represent ahb bus address bit[20:19]" + bitOffset: 4 + bitWidth: 2 + access: read-write + - register: + name: DMA_IN_DSCR + addressOffset: 76 + size: 32 + fields: + - name: INLINK_DSCR + description: "The content of current in link descriptor's third dword" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DMA_IN_DSCR_BF0 + addressOffset: 80 + size: 32 + fields: + - name: INLINK_DSCR_BF0 + description: "The content of current in link descriptor's first dword" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DMA_IN_DSCR_BF1 + addressOffset: 84 + size: 32 + fields: + - name: INLINK_DSCR_BF1 + description: "The content of current in link descriptor's second dword" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DMA_OUT_DSCR + addressOffset: 88 + size: 32 + fields: + - name: OUTLINK_DSCR + description: "The content of current out link descriptor's third dword" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DMA_OUT_DSCR_BF0 + addressOffset: 92 + size: 32 + fields: + - name: OUTLINK_DSCR_BF0 + description: "The content of current out link descriptor's first dword" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DMA_OUT_DSCR_BF1 + addressOffset: 96 + size: 32 + fields: + - name: OUTLINK_DSCR_BF1 + description: "The content of current out link descriptor's second dword" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: ESCAPE_CONF + addressOffset: 100 + size: 32 + resetValue: 51 + fields: + - name: TX_C0_ESC_EN + description: Set this bit to enable 0xc0 char decode when DMA receives data. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_DB_ESC_EN + description: Set this bit to enable 0xdb char decode when DMA receives data. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TX_11_ESC_EN + description: Set this bit to enable flow control char 0x11 decode when DMA receives data. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_13_ESC_EN + description: Set this bit to enable flow control char 0x13 decode when DMA receives data. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_C0_ESC_EN + description: Set this bit to enable 0xc0 char replace when DMA sends data. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_DB_ESC_EN + description: Set this bit to enable 0xdb char replace when DMA sends data. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RX_11_ESC_EN + description: Set this bit to enable flow control char 0x11 replace when DMA sends data. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_13_ESC_EN + description: Set this bit to enable flow control char 0x13 replace when DMA sends data. + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: HUNG_CONF + addressOffset: 104 + size: 32 + resetValue: 8456208 + fields: + - name: TXFIFO_TIMEOUT + description: This register stores the timeout value.when DMA takes more time than this register value to receive a data it will produce uhci_tx_hung_int interrupt. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TXFIFO_TIMEOUT_SHIFT + description: "The tick count is cleared when its value >=(17'd8000>>reg_txfifo_timeout_shift)" + bitOffset: 8 + bitWidth: 3 + access: read-write + - name: TXFIFO_TIMEOUT_ENA + description: The enable bit for txfifo receive data timeout + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RXFIFO_TIMEOUT + description: This register stores the timeout value.when DMA takes more time than this register value to read a data from RAM it will produce uhci_rx_hung_int interrupt. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: RXFIFO_TIMEOUT_SHIFT + description: "The tick count is cleared when its value >=(17'd8000>>reg_rxfifo_timeout_shift)" + bitOffset: 20 + bitWidth: 3 + access: read-write + - name: RXFIFO_TIMEOUT_ENA + description: This is the enable bit for DMA send data timeout + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: ACK_NUM + addressOffset: 108 + size: 32 + - register: + name: RX_HEAD + addressOffset: 112 + size: 32 + fields: + - name: RX_HEAD + description: This register stores the packet header received by DMA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: QUICK_SENT + addressOffset: 116 + size: 32 + fields: + - name: SINGLE_SEND_NUM + description: The bits are used to choose which short packet + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SINGLE_SEND_EN + description: Set this bit to enable send a short packet + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ALWAYS_SEND_NUM + description: The bits are used to choose which short packet + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: ALWAYS_SEND_EN + description: Set this bit to enable continuously send the same short packet + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: Q0_WORD0 + addressOffset: 120 + size: 32 + fields: + - name: SEND_Q0_WORD0 + description: "This register stores the content of short packet's first dword" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q0_WORD1 + addressOffset: 124 + size: 32 + fields: + - name: SEND_Q0_WORD1 + description: "This register stores the content of short packet's second dword" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q1_WORD0 + addressOffset: 128 + size: 32 + fields: + - name: SEND_Q1_WORD0 + description: "This register stores the content of short packet's first dword" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q1_WORD1 + addressOffset: 132 + size: 32 + fields: + - name: SEND_Q1_WORD1 + description: "This register stores the content of short packet's second dword" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q2_WORD0 + addressOffset: 136 + size: 32 + fields: + - name: SEND_Q2_WORD0 + description: "This register stores the content of short packet's first dword" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q2_WORD1 + addressOffset: 140 + size: 32 + fields: + - name: SEND_Q2_WORD1 + description: "This register stores the content of short packet's second dword" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q3_WORD0 + addressOffset: 144 + size: 32 + fields: + - name: SEND_Q3_WORD0 + description: "This register stores the content of short packet's first dword" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q3_WORD1 + addressOffset: 148 + size: 32 + fields: + - name: SEND_Q3_WORD1 + description: "This register stores the content of short packet's second dword" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q4_WORD0 + addressOffset: 152 + size: 32 + fields: + - name: SEND_Q4_WORD0 + description: "This register stores the content of short packet's first dword" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q4_WORD1 + addressOffset: 156 + size: 32 + fields: + - name: SEND_Q4_WORD1 + description: "This register stores the content of short packet's second dword" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q5_WORD0 + addressOffset: 160 + size: 32 + fields: + - name: SEND_Q5_WORD0 + description: "This register stores the content of short packet's first dword" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q5_WORD1 + addressOffset: 164 + size: 32 + fields: + - name: SEND_Q5_WORD1 + description: "This register stores the content of short packet's second dword" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q6_WORD0 + addressOffset: 168 + size: 32 + fields: + - name: SEND_Q6_WORD0 + description: "This register stores the content of short packet's first dword" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q6_WORD1 + addressOffset: 172 + size: 32 + fields: + - name: SEND_Q6_WORD1 + description: "This register stores the content of short packet's second dword" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ESC_CONF0 + addressOffset: 176 + size: 32 + resetValue: 14474176 + fields: + - name: SEPER_CHAR + description: This register stores the seperator char seperator char is used to seperate the data frame. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SEPER_ESC_CHAR0 + description: This register stores thee first char used to replace seperator char in data. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SEPER_ESC_CHAR1 + description: This register stores the second char used to replace seperator char in data . 0xdc 0xdb replace 0xc0 by default. + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: ESC_CONF1 + addressOffset: 180 + size: 32 + resetValue: 14539739 + fields: + - name: ESC_SEQ0 + description: This register stores the first substitute char used to replace the seperator char. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: ESC_SEQ0_CHAR0 + description: This register stores the first char used to replace reg_esc_seq0 in data. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: ESC_SEQ0_CHAR1 + description: This register stores the second char used to replace the reg_esc_seq0 in data + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: ESC_CONF2 + addressOffset: 184 + size: 32 + resetValue: 14605073 + fields: + - name: ESC_SEQ1 + description: This register stores the flow control char to turn on the flow_control + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: ESC_SEQ1_CHAR0 + description: This register stores the first char used to replace the reg_esc_seq1 in data. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: ESC_SEQ1_CHAR1 + description: This register stores the second char used to replace the reg_esc_seq1 in data. + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: ESC_CONF3 + addressOffset: 188 + size: 32 + resetValue: 14670611 + fields: + - name: ESC_SEQ2 + description: This register stores the flow_control char to turn off the flow_control + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: ESC_SEQ2_CHAR0 + description: This register stores the first char used to replace the reg_esc_seq2 in data. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: ESC_SEQ2_CHAR1 + description: This register stores the second char used to replace the reg_esc_seq2 in data. + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: PKT_THRES + addressOffset: 192 + size: 32 + resetValue: 128 + fields: + - name: PKT_THRS + description: when the amount of packet payload is greater than this value the process of receiving data is done. + bitOffset: 0 + bitWidth: 13 + access: read-write + - register: + name: DATE + addressOffset: 252 + size: 32 + resetValue: 369364993 + fields: + - name: DATE + description: version information + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: UHCI1 + description: Universal Host Controller Interface 1 + baseAddress: 1073004544 + interrupt: + - name: UHCI1 + value: 13 + derivedFrom: UHCI0 diff --git a/esp32c2/svd/esp32c2.svd.yaml b/esp32c2/svd/esp32c2.svd.yaml new file mode 100644 index 0000000000..a0f1cdb30c --- /dev/null +++ b/esp32c2/svd/esp32c2.svd.yaml @@ -0,0 +1,15269 @@ +--- +vendor: "ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD." +vendorID: ESPRESSIF +name: ESP32-C2 +series: ESP32 C-Series +version: "10" +description: 32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE) +licenseText: "Copyright 2024 Espressif Systems (Shanghai) PTE LTD\n\n Licensed under the Apache License, Version 2.0 (the \"License\");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an \"AS IS\" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License." +cpu: + name: RV32IMC + revision: r0p0 + endian: little + mpuPresent: false + fpuPresent: false + nvicPrioBits: 0 + vendorSystickConfig: false +addressUnitBits: 32 +width: 32 +resetValue: 0 +resetMask: 4294967295 +peripherals: + - name: APB_CTRL + description: APB (Advanced Peripheral Bus) Controller + groupName: APB_CTRL + baseAddress: 1610768384 + addressBlock: + - offset: 0 + size: 160 + usage: registers + interrupt: + - name: APB_CTRL + value: 12 + registers: + - register: + name: SYSCLK_CONF + description: APB_CTRL_SYSCLK_CONF_REG + addressOffset: 0 + size: 32 + resetValue: 1 + fields: + - name: PRE_DIV_CNT + description: reg_pre_div_cnt + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: CLK_320M_EN + description: reg_clk_320m_en + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: reg_clk_en + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RST_TICK_CNT + description: reg_rst_tick_cnt + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: TICK_CONF + description: APB_CTRL_TICK_CONF_REG + addressOffset: 4 + size: 32 + resetValue: 67367 + fields: + - name: XTAL_TICK_NUM + description: reg_xtal_tick_num + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CK8M_TICK_NUM + description: reg_ck8m_tick_num + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: TICK_ENABLE + description: reg_tick_enable + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: CLK_OUT_EN + description: APB_CTRL_CLK_OUT_EN_REG + addressOffset: 8 + size: 32 + resetValue: 2047 + fields: + - name: CLK20_OEN + description: reg_clk20_oen + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CLK22_OEN + description: reg_clk22_oen + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CLK44_OEN + description: reg_clk44_oen + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CLK_BB_OEN + description: reg_clk_bb_oen + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CLK80_OEN + description: reg_clk80_oen + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CLK160_OEN + description: reg_clk160_oen + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CLK_320M_OEN + description: reg_clk_320m_oen + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CLK_ADC_INF_OEN + description: reg_clk_adc_inf_oen + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_DAC_CPU_OEN + description: reg_clk_dac_cpu_oen + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CLK40X_BB_OEN + description: reg_clk40x_bb_oen + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CLK_XTAL_OEN + description: reg_clk_xtal_oen + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: WIFI_BB_CFG + description: APB_CTRL_WIFI_BB_CFG_REG + addressOffset: 12 + size: 32 + fields: + - name: WIFI_BB_CFG + description: reg_wifi_bb_cfg + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WIFI_BB_CFG_2 + description: APB_CTRL_WIFI_BB_CFG_2_REG + addressOffset: 16 + size: 32 + fields: + - name: WIFI_BB_CFG_2 + description: reg_wifi_bb_cfg_2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WIFI_CLK_EN + description: APB_CTRL_WIFI_CLK_EN_REG + addressOffset: 20 + size: 32 + resetValue: 4294762544 + fields: + - name: WIFI_CLK_EN + description: reg_wifi_clk_en + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WIFI_RST_EN + description: APB_CTRL_WIFI_RST_EN_REG + addressOffset: 24 + size: 32 + fields: + - name: WIFI_RST + description: reg_wifi_rst + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HOST_INF_SEL + description: APB_CTRL_HOST_INF_SEL_REG + addressOffset: 28 + size: 32 + fields: + - name: PERI_IO_SWAP + description: reg_peri_io_swap + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: EXT_MEM_PMS_LOCK + description: APB_CTRL_EXT_MEM_PMS_LOCK_REG + addressOffset: 32 + size: 32 + fields: + - name: EXT_MEM_PMS_LOCK + description: reg_ext_mem_pms_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: FLASH_ACE0_ATTR + description: APB_CTRL_FLASH_ACE0_ATTR_REG + addressOffset: 40 + size: 32 + resetValue: 3 + fields: + - name: FLASH_ACE0_ATTR + description: reg_flash_ace0_attr + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: FLASH_ACE1_ATTR + description: APB_CTRL_FLASH_ACE1_ATTR_REG + addressOffset: 44 + size: 32 + resetValue: 3 + fields: + - name: FLASH_ACE1_ATTR + description: reg_flash_ace1_attr + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: FLASH_ACE2_ATTR + description: APB_CTRL_FLASH_ACE2_ATTR_REG + addressOffset: 48 + size: 32 + resetValue: 3 + fields: + - name: FLASH_ACE2_ATTR + description: reg_flash_ace2_attr + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: FLASH_ACE3_ATTR + description: APB_CTRL_FLASH_ACE3_ATTR_REG + addressOffset: 52 + size: 32 + resetValue: 3 + fields: + - name: FLASH_ACE3_ATTR + description: reg_flash_ace3_attr + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: FLASH_ACE0_ADDR + description: APB_CTRL_FLASH_ACE0_ADDR_REG + addressOffset: 56 + size: 32 + fields: + - name: S + description: reg_flash_ace0_addr_s + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FLASH_ACE1_ADDR + description: APB_CTRL_FLASH_ACE1_ADDR_REG + addressOffset: 60 + size: 32 + resetValue: 4194304 + fields: + - name: S + description: reg_flash_ace1_addr_s + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FLASH_ACE2_ADDR + description: APB_CTRL_FLASH_ACE2_ADDR_REG + addressOffset: 64 + size: 32 + resetValue: 8388608 + fields: + - name: S + description: reg_flash_ace2_addr_s + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FLASH_ACE3_ADDR + description: APB_CTRL_FLASH_ACE3_ADDR_REG + addressOffset: 68 + size: 32 + resetValue: 12582912 + fields: + - name: S + description: reg_flash_ace3_addr_s + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FLASH_ACE0_SIZE + description: APB_CTRL_FLASH_ACE0_SIZE_REG + addressOffset: 72 + size: 32 + resetValue: 1024 + fields: + - name: FLASH_ACE0_SIZE + description: reg_flash_ace0_size + bitOffset: 0 + bitWidth: 13 + access: read-write + - register: + name: FLASH_ACE1_SIZE + description: APB_CTRL_FLASH_ACE1_SIZE_REG + addressOffset: 76 + size: 32 + resetValue: 1024 + fields: + - name: FLASH_ACE1_SIZE + description: reg_flash_ace1_size + bitOffset: 0 + bitWidth: 13 + access: read-write + - register: + name: FLASH_ACE2_SIZE + description: APB_CTRL_FLASH_ACE2_SIZE_REG + addressOffset: 80 + size: 32 + resetValue: 1024 + fields: + - name: FLASH_ACE2_SIZE + description: reg_flash_ace2_size + bitOffset: 0 + bitWidth: 13 + access: read-write + - register: + name: FLASH_ACE3_SIZE + description: APB_CTRL_FLASH_ACE3_SIZE_REG + addressOffset: 84 + size: 32 + resetValue: 1024 + fields: + - name: FLASH_ACE3_SIZE + description: reg_flash_ace3_size + bitOffset: 0 + bitWidth: 13 + access: read-write + - register: + name: SPI_MEM_PMS_CTRL + description: APB_CTRL_SPI_MEM_PMS_CTRL_REG + addressOffset: 136 + size: 32 + fields: + - name: SPI_MEM_REJECT_INT + description: reg_spi_mem_reject_int + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_MEM_REJECT_CLR + description: reg_spi_mem_reject_clr + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SPI_MEM_REJECT_CDE + description: reg_spi_mem_reject_cde + bitOffset: 2 + bitWidth: 5 + access: read-only + - register: + name: SPI_MEM_REJECT_ADDR + description: APB_CTRL_SPI_MEM_REJECT_ADDR_REG + addressOffset: 140 + size: 32 + fields: + - name: SPI_MEM_REJECT_ADDR + description: reg_spi_mem_reject_addr + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SDIO_CTRL + description: APB_CTRL_SDIO_CTRL_REG + addressOffset: 144 + size: 32 + fields: + - name: SDIO_WIN_ACCESS_EN + description: reg_sdio_win_access_en + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: REDCY_SIG0 + description: APB_CTRL_REDCY_SIG0_REG_REG + addressOffset: 148 + size: 32 + fields: + - name: REDCY_SIG0 + description: reg_redcy_sig0 + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: REDCY_ANDOR + description: reg_redcy_andor + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: REDCY_SIG1 + description: APB_CTRL_REDCY_SIG1_REG_REG + addressOffset: 152 + size: 32 + fields: + - name: REDCY_SIG1 + description: reg_redcy_sig1 + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: REDCY_NANDOR + description: reg_redcy_nandor + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: FRONT_END_MEM_PD + description: APB_CTRL_FRONT_END_MEM_PD_REG + addressOffset: 156 + size: 32 + resetValue: 85 + fields: + - name: AGC_MEM_FORCE_PU + description: reg_agc_mem_force_pu + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: AGC_MEM_FORCE_PD + description: reg_agc_mem_force_pd + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PBUS_MEM_FORCE_PU + description: reg_pbus_mem_force_pu + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PBUS_MEM_FORCE_PD + description: reg_pbus_mem_force_pd + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DC_MEM_FORCE_PU + description: reg_dc_mem_force_pu + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DC_MEM_FORCE_PD + description: reg_dc_mem_force_pd + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FREQ_MEM_FORCE_PU + description: reg_freq_mem_force_pu + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FREQ_MEM_FORCE_PD + description: reg_freq_mem_force_pd + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: RETENTION_CTRL + description: APB_CTRL_RETENTION_CTRL_REG + addressOffset: 160 + size: 32 + fields: + - name: RETENTION_LINK_ADDR + description: reg_retention_link_addr + bitOffset: 0 + bitWidth: 27 + access: read-write + - name: NOBYPASS_CPU_ISO_RST + description: reg_nobypass_cpu_iso_rst + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: CLKGATE_FORCE_ON + description: Memory power configuration registers + addressOffset: 164 + size: 32 + resetValue: 127 + fields: + - name: ROM_CLKGATE_FORCE_ON + description: "Set the bit to 1 to force rom always have clock, for low power can clear to 0 then only when have access the rom have clock" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SRAM_CLKGATE_FORCE_ON + description: "Set the bit to 1 to force sram always have clock, for low power can clear to 0 then only when have access the sram have clock" + bitOffset: 3 + bitWidth: 4 + access: read-write + - register: + name: MEM_POWER_DOWN + description: Memory power configuration registers + addressOffset: 168 + size: 32 + resetValue: 127 + fields: + - name: ROM_POWER_DOWN + description: Set 1 to let rom power down + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SRAM_POWER_DOWN + description: Set 1 to let sram power down + bitOffset: 3 + bitWidth: 4 + access: read-write + - register: + name: MEM_POWER_UP + description: Memory power configuration registers + addressOffset: 172 + size: 32 + resetValue: 127 + fields: + - name: ROM_POWER_UP + description: Set 1 to let rom power up + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SRAM_POWER_UP + description: Set 1 to let sram power up + bitOffset: 3 + bitWidth: 4 + access: read-write + - register: + name: RND_DATA + description: APB_CTRL_RND_DATA_REG + addressOffset: 176 + size: 32 + fields: + - name: RND_DATA + description: reg_rnd_data + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PERI_BACKUP_CONFIG + description: APB_CTRL_PERI_BACKUP_CONFIG_REG_REG + addressOffset: 180 + size: 32 + resetValue: 25728 + fields: + - name: PERI_BACKUP_FLOW_ERR + description: reg_peri_backup_flow_err + bitOffset: 1 + bitWidth: 2 + access: read-only + - name: PERI_BACKUP_BURST_LIMIT + description: reg_peri_backup_burst_limit + bitOffset: 4 + bitWidth: 5 + access: read-write + - name: PERI_BACKUP_TOUT_THRES + description: reg_peri_backup_tout_thres + bitOffset: 9 + bitWidth: 10 + access: read-write + - name: PERI_BACKUP_SIZE + description: reg_peri_backup_size + bitOffset: 19 + bitWidth: 10 + access: read-write + - name: PERI_BACKUP_START + description: reg_peri_backup_start + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: PERI_BACKUP_TO_MEM + description: reg_peri_backup_to_mem + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: PERI_BACKUP_ENA + description: reg_peri_backup_ena + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: PERI_BACKUP_APB_ADDR + description: APB_CTRL_PERI_BACKUP_APB_ADDR_REG_REG + addressOffset: 184 + size: 32 + fields: + - name: BACKUP_APB_START_ADDR + description: reg_backup_apb_start_addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PERI_BACKUP_MEM_ADDR + description: APB_CTRL_PERI_BACKUP_MEM_ADDR_REG_REG + addressOffset: 188 + size: 32 + fields: + - name: BACKUP_MEM_START_ADDR + description: reg_backup_mem_start_addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PERI_BACKUP_INT_RAW + description: APB_CTRL_PERI_BACKUP_INT_RAW_REG + addressOffset: 192 + size: 32 + fields: + - name: PERI_BACKUP_DONE_INT_RAW + description: reg_peri_backup_done_int_raw + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PERI_BACKUP_ERR_INT_RAW + description: reg_peri_backup_err_int_raw + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: PERI_BACKUP_INT_ST + description: APB_CTRL_PERI_BACKUP_INT_ST_REG + addressOffset: 196 + size: 32 + fields: + - name: PERI_BACKUP_DONE_INT_ST + description: reg_peri_backup_done_int_st + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PERI_BACKUP_ERR_INT_ST + description: reg_peri_backup_err_int_st + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: PERI_BACKUP_INT_ENA + description: APB_CTRL_PERI_BACKUP_INT_ENA_REG + addressOffset: 200 + size: 32 + fields: + - name: PERI_BACKUP_DONE_INT_ENA + description: reg_peri_backup_done_int_ena + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PERI_BACKUP_ERR_INT_ENA + description: reg_peri_backup_err_int_ena + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: PERI_BACKUP_INT_CLR + description: APB_CTRL_PERI_BACKUP_INT_CLR_REG + addressOffset: 208 + size: 32 + fields: + - name: PERI_BACKUP_DONE_INT_CLR + description: reg_peri_backup_done_int_clr + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: PERI_BACKUP_ERR_INT_CLR + description: reg_peri_backup_err_int_clr + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: DATE + description: APB_CTRL_DATE_REG + addressOffset: 1020 + size: 32 + resetValue: 34627712 + fields: + - name: DATE + description: reg_dateVersion control + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: APB_SARADC + description: SAR (Successive Approximation Register) Analog-to-Digital Converter + groupName: APB_SARADC + baseAddress: 1610874880 + addressBlock: + - offset: 0 + size: 104 + usage: registers + interrupt: + - name: APB_ADC + value: 32 + registers: + - register: + name: CTRL + description: register description + addressOffset: 0 + size: 32 + resetValue: 1073971776 + fields: + - name: SARADC_START_FORCE + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SARADC_START + description: Need add description + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SARADC_SAR_CLK_GATED + description: Need add description + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SARADC_SAR_CLK_DIV + description: SAR clock divider + bitOffset: 7 + bitWidth: 8 + access: read-write + - name: SARADC_SAR_PATT_LEN + description: 0 ~ 15 means length 1 ~ 16 + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: SARADC_SAR_PATT_P_CLEAR + description: clear the pointer of pattern table for DIG ADC1 CTRL + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SARADC_XPD_SAR_FORCE + description: force option to xpd sar blocks + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: SARADC_WAIT_ARB_CYCLE + description: wait arbit signal stable after sar_done + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CTRL2 + description: register description + addressOffset: 4 + size: 32 + resetValue: 41470 + fields: + - name: SARADC_MEAS_NUM_LIMIT + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SARADC_MAX_MEAS_NUM + description: max conversion number + bitOffset: 1 + bitWidth: 8 + access: read-write + - name: SARADC_SAR1_INV + description: "1: data to DIG ADC1 CTRL is inverted, otherwise not" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SARADC_SAR2_INV + description: "1: data to DIG ADC2 CTRL is inverted, otherwise not" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SARADC_TIMER_TARGET + description: to set saradc timer target + bitOffset: 12 + bitWidth: 12 + access: read-write + - name: SARADC_TIMER_EN + description: to enable saradc timer trigger + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: FILTER_CTRL1 + description: register description + addressOffset: 8 + size: 32 + fields: + - name: FILTER_FACTOR1 + description: Need add description + bitOffset: 26 + bitWidth: 3 + access: read-write + - name: FILTER_FACTOR0 + description: Need add description + bitOffset: 29 + bitWidth: 3 + access: read-write + - register: + name: FSM_WAIT + description: register description + addressOffset: 12 + size: 32 + resetValue: 16713736 + fields: + - name: SARADC_XPD_WAIT + description: Need add description + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SARADC_RSTB_WAIT + description: Need add description + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SARADC_STANDBY_WAIT + description: Need add description + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: SAR1_STATUS + description: register description + addressOffset: 16 + size: 32 + fields: + - name: SARADC_SAR1_STATUS + description: Need add description + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SAR2_STATUS + description: register description + addressOffset: 20 + size: 32 + fields: + - name: SARADC_SAR2_STATUS + description: Need add description + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SAR_PATT_TAB1 + description: register description + addressOffset: 24 + size: 32 + resetValue: 16777215 + fields: + - name: SARADC_SAR_PATT_TAB1 + description: item 0 ~ 3 for pattern table 1 (each item one byte) + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: SAR_PATT_TAB2 + description: register description + addressOffset: 28 + size: 32 + resetValue: 16777215 + fields: + - name: SARADC_SAR_PATT_TAB2 + description: Item 4 ~ 7 for pattern table 1 (each item one byte) + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: ONETIME_SAMPLE + description: register description + addressOffset: 32 + size: 32 + resetValue: 436207616 + fields: + - name: SARADC_ONETIME_ATTEN + description: Need add description + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: SARADC_ONETIME_CHANNEL + description: Need add description + bitOffset: 25 + bitWidth: 4 + access: read-write + - name: SARADC_ONETIME_START + description: Need add description + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SARADC2_ONETIME_SAMPLE + description: Need add description + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SARADC1_ONETIME_SAMPLE + description: Need add description + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: APB_ADC_ARB_CTRL + description: register description + addressOffset: 36 + size: 32 + resetValue: 2304 + fields: + - name: ADC_ARB_APB_FORCE + description: adc2 arbiter force to enableapb controller + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ADC_ARB_RTC_FORCE + description: adc2 arbiter force to enable rtc controller + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ADC_ARB_WIFI_FORCE + description: adc2 arbiter force to enable wifi controller + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ADC_ARB_GRANT_FORCE + description: adc2 arbiter force grant + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: ADC_ARB_APB_PRIORITY + description: Set adc2 arbiterapb priority + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: ADC_ARB_RTC_PRIORITY + description: Set adc2 arbiter rtc priority + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: ADC_ARB_WIFI_PRIORITY + description: Set adc2 arbiter wifi priority + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: ADC_ARB_FIX_PRIORITY + description: adc2 arbiter uses fixed priority + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: FILTER_CTRL0 + description: register description + addressOffset: 40 + size: 32 + resetValue: 57933824 + fields: + - name: FILTER_CHANNEL1 + description: Need add description + bitOffset: 18 + bitWidth: 4 + access: read-write + - name: FILTER_CHANNEL0 + description: apb_adc1_filter_factor + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: FILTER_RESET + description: enable apb_adc1_filter + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAR1DATA_STATUS + description: register description + addressOffset: 44 + size: 32 + fields: + - name: APB_SARADC1_DATA + description: Need add description + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: SAR2DATA_STATUS + description: register description + addressOffset: 48 + size: 32 + fields: + - name: APB_SARADC2_DATA + description: Need add description + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: THRES0_CTRL + description: register description + addressOffset: 52 + size: 32 + resetValue: 262125 + fields: + - name: THRES0_CHANNEL + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: THRES0_HIGH + description: "saradc1's thres0 monitor thres" + bitOffset: 5 + bitWidth: 13 + access: read-write + - name: THRES0_LOW + description: "saradc1's thres0 monitor thres" + bitOffset: 18 + bitWidth: 13 + access: read-write + - register: + name: THRES1_CTRL + description: register description + addressOffset: 56 + size: 32 + resetValue: 262125 + fields: + - name: THRES1_CHANNEL + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: THRES1_HIGH + description: "saradc1's thres0 monitor thres" + bitOffset: 5 + bitWidth: 13 + access: read-write + - name: THRES1_LOW + description: "saradc1's thres0 monitor thres" + bitOffset: 18 + bitWidth: 13 + access: read-write + - register: + name: THRES_CTRL + description: register description + addressOffset: 60 + size: 32 + fields: + - name: THRES_ALL_EN + description: Need add description + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: THRES3_EN + description: Need add description + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: THRES2_EN + description: Need add description + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: THRES1_EN + description: Need add description + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: THRES0_EN + description: Need add description + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_ENA + description: register description + addressOffset: 64 + size: 32 + fields: + - name: THRES1_LOW_INT_ENA + description: Need add description + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: THRES0_LOW_INT_ENA + description: Need add description + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: THRES1_HIGH_INT_ENA + description: Need add description + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: THRES0_HIGH_INT_ENA + description: Need add description + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: APB_SARADC2_DONE_INT_ENA + description: Need add description + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: APB_SARADC1_DONE_INT_ENA + description: Need add description + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: register description + addressOffset: 68 + size: 32 + fields: + - name: THRES1_LOW_INT_RAW + description: Need add description + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: THRES0_LOW_INT_RAW + description: Need add description + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: THRES1_HIGH_INT_RAW + description: Need add description + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: THRES0_HIGH_INT_RAW + description: Need add description + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: APB_SARADC2_DONE_INT_RAW + description: Need add description + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: APB_SARADC1_DONE_INT_RAW + description: Need add description + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: register description + addressOffset: 72 + size: 32 + fields: + - name: THRES1_LOW_INT_ST + description: Need add description + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: THRES0_LOW_INT_ST + description: Need add description + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: THRES1_HIGH_INT_ST + description: Need add description + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: THRES0_HIGH_INT_ST + description: Need add description + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: APB_SARADC2_DONE_INT_ST + description: Need add description + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: APB_SARADC1_DONE_INT_ST + description: Need add description + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: register description + addressOffset: 76 + size: 32 + fields: + - name: THRES1_LOW_INT_CLR + description: Need add description + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: THRES0_LOW_INT_CLR + description: Need add description + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: THRES1_HIGH_INT_CLR + description: Need add description + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: THRES0_HIGH_INT_CLR + description: Need add description + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: APB_SARADC2_DONE_INT_CLR + description: Need add description + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: APB_SARADC1_DONE_INT_CLR + description: Need add description + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: DMA_CONF + description: register description + addressOffset: 80 + size: 32 + resetValue: 255 + fields: + - name: APB_ADC_EOF_NUM + description: the dma_in_suc_eof gen when sample cnt = spi_eof_num + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: APB_ADC_RESET_FSM + description: reset_apb_adc_state + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: APB_ADC_TRANS + description: enable apb_adc use spi_dma + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: APB_ADC_CLKM_CONF + description: register description + addressOffset: 84 + size: 32 + resetValue: 4 + fields: + - name: REG_CLKM_DIV_NUM + description: Integral I2S clock divider value + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: REG_CLKM_DIV_B + description: Fractional clock divider numerator value + bitOffset: 8 + bitWidth: 6 + access: read-write + - name: REG_CLKM_DIV_A + description: Fractional clock divider denominator value + bitOffset: 14 + bitWidth: 6 + access: read-write + - name: CLK_EN + description: Need add description + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: REG_CLK_SEL + description: Set this bit to enable clk_apll + bitOffset: 21 + bitWidth: 2 + access: read-write + - register: + name: APB_TSENS_CTRL + description: register description + addressOffset: 88 + size: 32 + resetValue: 98304 + fields: + - name: REG_TSENS_OUT + description: Need add description + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: REG_TSENS_IN_INV + description: Need add description + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: REG_TSENS_CLK_DIV + description: Need add description + bitOffset: 14 + bitWidth: 8 + access: read-write + - name: REG_TSENS_PU + description: Need add description + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: APB_TSENS_CTRL2 + description: register description + addressOffset: 92 + size: 32 + resetValue: 16386 + fields: + - name: REG_TSENS_XPD_WAIT + description: Need add description + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: REG_TSENS_XPD_FORCE + description: Need add description + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: REG_TSENS_CLK_INV + description: Need add description + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TSENS_CLK_SEL + description: Need add description + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: CALI + description: register description + addressOffset: 96 + size: 32 + resetValue: 32768 + fields: + - name: CFG + description: Need add description + bitOffset: 0 + bitWidth: 17 + access: read-write + - register: + name: APB_CTRL_DATE + description: register description + addressOffset: 1020 + size: 32 + resetValue: 34632208 + fields: + - name: DATE + description: Need add description + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: ASSIST_DEBUG + description: Debug Assist + groupName: ASSIST_DEBUG + baseAddress: 1611456512 + addressBlock: + - offset: 0 + size: 56 + usage: registers + interrupt: + - name: ASSIST_DEBUG + description: Assist debug interrupt + value: 40 + registers: + - register: + name: CORE_0_MONTR_ENA + description: core0 monitor enable configuration register + addressOffset: 0 + size: 32 + fields: + - name: CORE_0_SP_SPILL_MIN_ENA + description: enbale sp underlow monitor + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_SP_SPILL_MAX_ENA + description: enbale sp overflow monitor + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_INTR_RAW + description: core0 monitor interrupt status register + addressOffset: 4 + size: 32 + fields: + - name: CORE_0_SP_SPILL_MIN_RAW + description: sp underlow monitor interrupt status register + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_0_SP_SPILL_MAX_RAW + description: sp overflow monitor interupt status register + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: CORE_0_INTR_ENA + description: core0 monitor interrupt enable register + addressOffset: 8 + size: 32 + fields: + - name: CORE_0_SP_SPILL_MIN_INTR_ENA + description: enbale sp underlow monitor interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_SP_SPILL_MAX_INTR_ENA + description: enbale sp overflow monitor interrupt + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_INTR_CLR + description: core0 monitor interrupt clr register + addressOffset: 12 + size: 32 + fields: + - name: CORE_0_SP_SPILL_MIN_CLR + description: clr sp underlow monitor interrupt + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CORE_0_SP_SPILL_MAX_CLR + description: clr sp overflow monitor interrupt + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: CORE_0_SP_MIN + description: stack min value + addressOffset: 16 + size: 32 + fields: + - name: CORE_0_SP_MIN + description: core0 sp region configuration regsiter + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_SP_MAX + description: stack max value + addressOffset: 20 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_SP_MAX + description: core0 sp pc status register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_SP_PC + description: stack monitor pc status register + addressOffset: 24 + size: 32 + fields: + - name: CORE_0_SP_PC + description: This regsiter stores the PC when trigger stack monitor. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_RCD_EN + description: record enable configuration register + addressOffset: 28 + size: 32 + fields: + - name: CORE_0_RCD_RECORDEN + description: Set 1 to enable record PC + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_RCD_PDEBUGEN + description: "Set 1 to enable cpu pdebug function, must set this bit can get cpu PC" + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_RCD_PDEBUGPC + description: record status regsiter + addressOffset: 32 + size: 32 + fields: + - name: CORE_0_RCD_PDEBUGPC + description: recorded PC + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_RCD_PDEBUGSP + description: record status regsiter + addressOffset: 36 + size: 32 + fields: + - name: CORE_0_RCD_PDEBUGSP + description: recorded sp + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_LASTPC_BEFORE_EXCEPTION + description: cpu status register + addressOffset: 40 + size: 32 + fields: + - name: CORE_0_LASTPC_BEFORE_EXC + description: "cpu's lastpc before exception" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_DEBUG_MODE + description: cpu status register + addressOffset: 44 + size: 32 + fields: + - name: CORE_0_DEBUG_MODE + description: "cpu debug mode status, 1 means cpu enter debug mode." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_0_DEBUG_MODULE_ACTIVE + description: cpu debug_module active status + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: CLOCK_GATE + description: clock gate register + addressOffset: 48 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: clock gate register + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: version register + addressOffset: 508 + size: 32 + resetValue: 34627616 + fields: + - name: DATE + description: version register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: BB + description: BB Peripheral + groupName: BB + baseAddress: 1610731520 + addressBlock: + - offset: 0 + size: 4 + usage: registers + registers: + - register: + name: BBPD_CTRL + description: Baseband control register + addressOffset: 84 + size: 32 + fields: + - name: DC_EST_FORCE_PD + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DC_EST_FORCE_PU + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FFT_FORCE_PD + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FFT_FORCE_PU + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DMA + description: DMA (Direct Memory Access) Controller + groupName: DMA + baseAddress: 1610870784 + addressBlock: + - offset: 0 + size: 132 + usage: registers + interrupt: + - name: DMA_CH0 + value: 33 + registers: + - cluster: + dim: 1 + dimIncrement: 16 + dimIndex: "0" + name: INT_CH%s + description: "Cluster INT_CH%s, containing INT_RAW_CH?, INT_ST_CH?, INT_ENA_CH?, INT_CLR_CH?" + addressOffset: 0 + children: + - register: + name: RAW + description: DMA_INT_RAW_CH0_REG. + addressOffset: 0 + size: 32 + fields: + - name: IN_DONE + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF + description: "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF + description: "The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_DONE + description: The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUT_EOF + description: The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR + description: "The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR + description: "The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY + description: "The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF + description: The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF + description: This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF + description: This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF + description: This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF + description: This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: ST + description: DMA_INT_ST_CH0_REG. + addressOffset: 4 + size: 32 + fields: + - name: IN_DONE + description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: IN_SUC_EOF + description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: IN_ERR_EOF + description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: OUT_DONE + description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: OUT_EOF + description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: IN_DSCR_ERR + description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OUT_DSCR_ERR + description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: IN_DSCR_EMPTY + description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OUT_TOTAL_EOF + description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: INFIFO_OVF + description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: INFIFO_UDF + description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: OUTFIFO_OVF + description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: OUTFIFO_UDF + description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - register: + name: ENA + description: DMA_INT_ENA_CH0_REG. + addressOffset: 8 + size: 32 + fields: + - name: IN_DONE + description: The interrupt enable bit for the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF + description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF + description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_DONE + description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUT_EOF + description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR + description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR + description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY + description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF + description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF + description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF + description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF + description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF + description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: CLR + description: DMA_INT_CLR_CH0_REG. + addressOffset: 12 + size: 32 + fields: + - name: IN_DONE + description: Set this bit to clear the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: IN_SUC_EOF + description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: IN_ERR_EOF + description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: OUT_DONE + description: Set this bit to clear the OUT_DONE_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: OUT_EOF + description: Set this bit to clear the OUT_EOF_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: IN_DSCR_ERR + description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: OUT_DSCR_ERR + description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: IN_DSCR_EMPTY + description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: OUT_TOTAL_EOF + description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: INFIFO_OVF + description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: INFIFO_UDF + description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: OUTFIFO_OVF + description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: OUTFIFO_UDF + description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - register: + name: AHB_TEST + description: DMA_AHB_TEST_REG. + addressOffset: 64 + size: 32 + fields: + - name: AHB_TESTMODE + description: reserved + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: AHB_TESTADDR + description: reserved + bitOffset: 4 + bitWidth: 2 + access: read-write + - register: + name: MISC_CONF + description: DMA_MISC_CONF_REG. + addressOffset: 68 + size: 32 + fields: + - name: AHBM_RST_INTER + description: "Set this bit, then clear this bit to reset the internal ahb FSM." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ARB_PRI_DIS + description: Set this bit to disable priority arbitration function. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: reg_clk_en + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: DMA_DATE_REG. + addressOffset: 72 + size: 32 + resetValue: 34624128 + fields: + - name: DATE + description: register version. + bitOffset: 0 + bitWidth: 32 + access: read-write + - cluster: + dim: 1 + dimIncrement: 192 + dimIndex: "0" + name: CH%s + description: "Cluster CH%s, containing IN_CONF0_CH?, IN_CONF1_CH?, INFIFO_STATUS_CH?, IN_POP_CH?, IN_LINK_CH?, IN_STATE_CH?, IN_SUC_EOF_DES_ADDR_CH?, IN_ERR_EOF_DES_ADDR_CH?, IN_DSCR_CH?, IN_DSCR_BF0_CH?, IN_DSCR_BF1_CH?, IN_PRI_CH?, IN_PERI_SEL_CH?, OUT_CONF0_CH?, OUT_CONF1_CH?, OUTFIFO_STATUS_CH?, OUT_PUSH_CH?, OUT_LINK_CH?, OUT_STATE_CH?, OUT_EOF_DES_ADDR_CH?, OUT_EOF_BFR_DES_ADDR_CH?, OUT_DSCR_CH?, OUT_DSCR_BF0_CH?, OUT_DSCR_BF1_CH?, OUT_PRI_CH?, OUT_PERI_SEL_CH?" + addressOffset: 112 + children: + - register: + name: IN_CONF0 + description: DMA_IN_CONF0_CH0_REG. + addressOffset: 0 + size: 32 + fields: + - name: IN_RST + description: This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_LOOP_TEST + description: reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: INDSCR_BURST_EN + description: Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DATA_BURST_EN + description: Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MEM_TRANS_EN + description: Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: IN_CONF1 + description: DMA_IN_CONF1_CH0_REG. + addressOffset: 4 + size: 32 + fields: + - name: IN_CHECK_OWNER + description: Set this bit to enable checking the owner attribute of the link descriptor. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: INFIFO_STATUS + description: DMA_INFIFO_STATUS_CH0_REG. + addressOffset: 8 + size: 32 + resetValue: 125829123 + fields: + - name: INFIFO_FULL + description: L1 Rx FIFO full signal for Rx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: INFIFO_EMPTY + description: L1 Rx FIFO empty signal for Rx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: INFIFO_CNT + description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + bitOffset: 2 + bitWidth: 6 + access: read-only + - name: IN_REMAIN_UNDER_1B + description: reserved + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: IN_REMAIN_UNDER_2B + description: reserved + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: IN_REMAIN_UNDER_3B + description: reserved + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: IN_REMAIN_UNDER_4B + description: reserved + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: IN_BUF_HUNGRY + description: reserved + bitOffset: 27 + bitWidth: 1 + access: read-only + - register: + name: IN_POP + description: DMA_IN_POP_CH0_REG. + addressOffset: 12 + size: 32 + resetValue: 2048 + fields: + - name: INFIFO_RDATA + description: This register stores the data popping from DMA FIFO. + bitOffset: 0 + bitWidth: 12 + access: read-only + - name: INFIFO_POP + description: Set this bit to pop data from DMA FIFO. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: IN_LINK + description: DMA_IN_LINK_CH0_REG. + addressOffset: 16 + size: 32 + resetValue: 17825792 + fields: + - name: INLINK_ADDR + description: "This register stores the 20 least significant bits of the first inlink descriptor's address." + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: INLINK_AUTO_RET + description: "Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: INLINK_STOP + description: Set this bit to stop dealing with the inlink descriptors. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: INLINK_START + description: Set this bit to start dealing with the inlink descriptors. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: INLINK_RESTART + description: Set this bit to mount a new inlink descriptor. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: INLINK_PARK + description: "1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working." + bitOffset: 24 + bitWidth: 1 + access: read-only + - register: + name: IN_STATE + description: DMA_IN_STATE_CH0_REG. + addressOffset: 20 + size: 32 + fields: + - name: INLINK_DSCR_ADDR + description: "This register stores the current inlink descriptor's address." + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: IN_DSCR_STATE + description: reserved + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: IN_STATE + description: reserved + bitOffset: 20 + bitWidth: 3 + access: read-only + - register: + name: IN_SUC_EOF_DES_ADDR + description: DMA_IN_SUC_EOF_DES_ADDR_CH0_REG. + addressOffset: 24 + size: 32 + fields: + - name: IN_SUC_EOF_DES_ADDR + description: This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_ERR_EOF_DES_ADDR + description: DMA_IN_ERR_EOF_DES_ADDR_CH0_REG. + addressOffset: 28 + size: 32 + fields: + - name: IN_ERR_EOF_DES_ADDR + description: This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR + description: DMA_IN_DSCR_CH0_REG. + addressOffset: 32 + size: 32 + fields: + - name: INLINK_DSCR + description: The address of the current inlink descriptor x. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_BF0 + description: DMA_IN_DSCR_BF0_CH0_REG. + addressOffset: 36 + size: 32 + fields: + - name: INLINK_DSCR_BF0 + description: The address of the last inlink descriptor x-1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_BF1 + description: DMA_IN_DSCR_BF1_CH0_REG. + addressOffset: 40 + size: 32 + fields: + - name: INLINK_DSCR_BF1 + description: The address of the second-to-last inlink descriptor x-2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_PRI + description: DMA_IN_PRI_CH0_REG. + addressOffset: 44 + size: 32 + fields: + - name: RX_PRI + description: "The priority of Rx channel 0. The larger of the value, the higher of the priority." + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: IN_PERI_SEL + description: DMA_IN_PERI_SEL_CH0_REG. + addressOffset: 48 + size: 32 + resetValue: 63 + fields: + - name: PERI_IN_SEL + description: "This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC." + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: OUT_CONF0 + description: DMA_OUT_CONF0_CH0_REG. + addressOffset: 96 + size: 32 + resetValue: 8 + fields: + - name: OUT_RST + description: This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_LOOP_TEST + description: reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_AUTO_WRBACK + description: Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_EOF_MODE + description: "EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTDSCR_BURST_EN + description: Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUT_DATA_BURST_EN + description: Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: OUT_CONF1 + description: DMA_OUT_CONF1_CH0_REG. + addressOffset: 100 + size: 32 + fields: + - name: OUT_CHECK_OWNER + description: Set this bit to enable checking the owner attribute of the link descriptor. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: OUTFIFO_STATUS + description: DMA_OUTFIFO_STATUS_CH0_REG. + addressOffset: 104 + size: 32 + resetValue: 125829122 + fields: + - name: OUTFIFO_FULL + description: L1 Tx FIFO full signal for Tx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY + description: L1 Tx FIFO empty signal for Tx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: OUTFIFO_CNT + description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + bitOffset: 2 + bitWidth: 6 + access: read-only + - name: OUT_REMAIN_UNDER_1B + description: reserved + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: OUT_REMAIN_UNDER_2B + description: reserved + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: OUT_REMAIN_UNDER_3B + description: reserved + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: OUT_REMAIN_UNDER_4B + description: reserved + bitOffset: 26 + bitWidth: 1 + access: read-only + - register: + name: OUT_PUSH + description: DMA_OUT_PUSH_CH0_REG. + addressOffset: 108 + size: 32 + fields: + - name: OUTFIFO_WDATA + description: This register stores the data that need to be pushed into DMA FIFO. + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: OUTFIFO_PUSH + description: Set this bit to push data into DMA FIFO. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: OUT_LINK + description: DMA_OUT_LINK_CH0_REG. + addressOffset: 112 + size: 32 + resetValue: 8388608 + fields: + - name: OUTLINK_ADDR + description: "This register stores the 20 least significant bits of the first outlink descriptor's address." + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: OUTLINK_STOP + description: Set this bit to stop dealing with the outlink descriptors. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: OUTLINK_START + description: Set this bit to start dealing with the outlink descriptors. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: OUTLINK_RESTART + description: Set this bit to restart a new outlink from the last address. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: OUTLINK_PARK + description: "1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working." + bitOffset: 23 + bitWidth: 1 + access: read-only + - register: + name: OUT_STATE + description: DMA_OUT_STATE_CH0_REG. + addressOffset: 116 + size: 32 + fields: + - name: OUTLINK_DSCR_ADDR + description: "This register stores the current outlink descriptor's address." + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: OUT_DSCR_STATE + description: reserved + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: OUT_STATE + description: reserved + bitOffset: 20 + bitWidth: 3 + access: read-only + - register: + name: OUT_EOF_DES_ADDR + description: DMA_OUT_EOF_DES_ADDR_CH0_REG. + addressOffset: 120 + size: 32 + fields: + - name: OUT_EOF_DES_ADDR + description: This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_EOF_BFR_DES_ADDR + description: DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG. + addressOffset: 124 + size: 32 + fields: + - name: OUT_EOF_BFR_DES_ADDR + description: This register stores the address of the outlink descriptor before the last outlink descriptor. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR + description: DMA_OUT_DSCR_CH0_REG. + addressOffset: 128 + size: 32 + fields: + - name: OUTLINK_DSCR + description: The address of the current outlink descriptor y. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_BF0 + description: DMA_OUT_DSCR_BF0_CH0_REG. + addressOffset: 132 + size: 32 + fields: + - name: OUTLINK_DSCR_BF0 + description: The address of the last outlink descriptor y-1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_BF1 + description: DMA_OUT_DSCR_BF1_CH0_REG. + addressOffset: 136 + size: 32 + fields: + - name: OUTLINK_DSCR_BF1 + description: The address of the second-to-last inlink descriptor x-2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_PRI + description: DMA_OUT_PRI_CH0_REG. + addressOffset: 140 + size: 32 + fields: + - name: TX_PRI + description: "The priority of Tx channel 0. The larger of the value, the higher of the priority." + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: OUT_PERI_SEL + description: DMA_OUT_PERI_SEL_CH0_REG. + addressOffset: 144 + size: 32 + resetValue: 63 + fields: + - name: PERI_OUT_SEL + description: "This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC." + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: ECC + description: ECC (ECC Hardware Accelerator) + groupName: ECC + baseAddress: 1610866688 + addressBlock: + - offset: 0 + size: 24 + usage: registers + registers: + - register: + name: MULT_INT_RAW + description: "I2S interrupt raw register, valid in level." + addressOffset: 12 + size: 32 + fields: + - name: CALC_DONE_INT_RAW + description: The raw interrupt status bit for the i2s_tx_hung_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: MULT_INT_ST + description: I2S interrupt status register. + addressOffset: 16 + size: 32 + fields: + - name: CALC_DONE_INT_ST + description: The masked interrupt status bit for the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: MULT_INT_ENA + description: I2S interrupt enable register. + addressOffset: 20 + size: 32 + fields: + - name: CALC_DONE_INT_ENA + description: The interrupt enable bit for the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: MULT_INT_CLR + description: I2S interrupt clear register. + addressOffset: 24 + size: 32 + fields: + - name: CALC_DONE_INT_CLR + description: Set this bit to clear the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: MULT_CONF + description: I2S RX configure register + addressOffset: 28 + size: 32 + fields: + - name: START + description: Set this bit to reset receiver + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RESET + description: Set this bit to reset Rx AFIFO + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: KEY_LENGTH + description: Set this bit to start receiving data + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SECURITY_MODE + description: Set this bit to enable slave receiver mode + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: clk gate + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: WORK_MODE + description: Reserved + bitOffset: 5 + bitWidth: 3 + access: read-write + - name: VERIFICATION_RESULT + description: Reserve + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: MULT_DATE + description: Version control register + addressOffset: 252 + size: 32 + resetValue: 33628720 + fields: + - name: DATE + description: ECC mult version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + name: "K_MEM[%s]" + description: The memory that stores k. + addressOffset: 256 + size: 32 + - register: + dim: 8 + dimIncrement: 4 + name: "PX_MEM[%s]" + description: The memory that stores Px. + addressOffset: 288 + size: 32 + - register: + dim: 8 + dimIncrement: 4 + name: "PY_MEM[%s]" + description: The memory that stores Py. + addressOffset: 320 + size: 32 + - name: EFUSE + description: eFuse Controller + groupName: EFUSE + baseAddress: 1610647552 + addressBlock: + - offset: 0 + size: 192 + usage: registers + interrupt: + - name: EFUSE + value: 20 + registers: + - register: + name: PGM_DATA0 + description: Register 0 that stores data to be programmed. + addressOffset: 0 + size: 32 + fields: + - name: PGM_DATA_0 + description: The content of the 0th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA1 + description: Register 1 that stores data to be programmed. + addressOffset: 4 + size: 32 + fields: + - name: PGM_DATA_1 + description: The content of the 1st 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA2 + description: Register 2 that stores data to be programmed. + addressOffset: 8 + size: 32 + fields: + - name: PGM_DATA_2 + description: The content of the 2nd 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA3 + description: Register 3 that stores data to be programmed. + addressOffset: 12 + size: 32 + fields: + - name: PGM_DATA_3 + description: The content of the 3rd 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA4 + description: Register 4 that stores data to be programmed. + addressOffset: 16 + size: 32 + fields: + - name: PGM_DATA_4 + description: The content of the 4th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA5 + description: Register 5 that stores data to be programmed. + addressOffset: 20 + size: 32 + fields: + - name: PGM_DATA_5 + description: The content of the 5th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA6 + description: Register 6 that stores data to be programmed. + addressOffset: 24 + size: 32 + fields: + - name: PGM_DATA_6 + description: The content of the 6th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA7 + description: Register 7 that stores data to be programmed. + addressOffset: 28 + size: 32 + fields: + - name: PGM_DATA_7 + description: The content of the 7th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_CHECK_VALUE0 + description: Register 0 that stores the RS code to be programmed. + addressOffset: 32 + size: 32 + fields: + - name: PGM_RS_DATA_0 + description: The content of the 0th 32-bit RS code to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_CHECK_VALUE1 + description: Register 1 that stores the RS code to be programmed. + addressOffset: 36 + size: 32 + fields: + - name: PGM_RS_DATA_1 + description: The content of the 1st 32-bit RS code to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_CHECK_VALUE2 + description: Register 2 that stores the RS code to be programmed. + addressOffset: 40 + size: 32 + fields: + - name: PGM_RS_DATA_2 + description: The content of the 2nd 32-bit RS code to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RD_WR_DIS + description: BLOCK0 data register 0. + addressOffset: 44 + size: 32 + fields: + - name: WR_DIS + description: Disable programming of individual eFuses. + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: RD_REPEAT_DATA0 + description: BLOCK0 data register 1. + addressOffset: 48 + size: 32 + fields: + - name: RD_DIS + description: The bit be set to disable software read high/low 128-bit of BLK3. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: WDT_DELAY_SEL + description: "Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000." + bitOffset: 2 + bitWidth: 2 + access: read-only + - name: DIS_PAD_JTAG + description: Set this bit to disable pad jtag. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_ICACHE + description: The bit be set to disable icache in download mode. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_MANUAL_ENCRYPT + description: The bit be set to disable manual encryption. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SPI_BOOT_ENCRYPT_DECRYPT_CNT + description: "These bits be set to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable." + bitOffset: 7 + bitWidth: 3 + access: read-only + - name: XTS_KEY_LENGTH_256 + description: "The bit be set means XTS_AES use the whole 256-bit efuse data in BLOCK3. Otherwise, XTS_AES use 128-bit eFuse data in BLOCK3." + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: UART_PRINT_CONTROL + description: Set this bit to disable usb printing. + bitOffset: 11 + bitWidth: 2 + access: read-only + - name: FORCE_SEND_RESUME + description: Set this bit to force ROM code to send a resume command during SPI boot. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_MODE + description: "Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 4, 5, 6, 7)." + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DIS_DIRECT_BOOT + description: This bit set means disable direct_boot mode. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: ENABLE_SECURITY_DOWNLOAD + description: Set this bit to enable secure UART download mode. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: FLASH_TPUW + description: "Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value. Otherwise, the waiting time is twice the configurable value." + bitOffset: 17 + bitWidth: 4 + access: read-only + - name: SECURE_BOOT_EN + description: The bit be set to enable secure boot. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED + description: Reserved (used for four backups method). + bitOffset: 22 + bitWidth: 10 + access: read-only + - register: + name: RD_BLK1_DATA0 + description: BLOCK1 data register 0. + addressOffset: 52 + size: 32 + fields: + - name: SYSTEM_DATA0 + description: "Stores the bits [0:31] of system data." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_BLK1_DATA1 + description: BLOCK1 data register 1. + addressOffset: 56 + size: 32 + fields: + - name: SYSTEM_DATA1 + description: "Stores the bits [32:63] of system data." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_BLK1_DATA2 + description: BLOCK1 data register 2. + addressOffset: 60 + size: 32 + fields: + - name: SYSTEM_DATA2 + description: "Stores the bits [64:87] of system data." + bitOffset: 0 + bitWidth: 24 + access: read-only + - register: + name: RD_BLK2_DATA0 + description: Register 0 of BLOCK2. + addressOffset: 64 + size: 32 + fields: + - name: BLK2_DATA0 + description: "Store the bit [0:31] of MAC." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_BLK2_DATA1 + description: Register 1 of BLOCK2. + addressOffset: 68 + size: 32 + fields: + - name: MAC_ID_HIGH + description: "Store the bit [31:47] of MAC." + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: WAFER_VERSION + description: Store wafer version. + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: PKG_VERSION + description: Store package version. + bitOffset: 19 + bitWidth: 3 + access: read-only + - name: BLK2_EFUSE_VERSION + description: Store efuse version. + bitOffset: 22 + bitWidth: 3 + access: read-only + - name: RF_REF_I_BIAS_CONFIG + description: Store rf configuration parameters. + bitOffset: 25 + bitWidth: 4 + access: read-only + - name: LDO_VOL_BIAS_CONFIG_LOW + description: "Store the bit [0:2] of ido configuration parameters." + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: RD_BLK2_DATA2 + description: Register 2 of BLOCK2. + addressOffset: 72 + size: 32 + fields: + - name: LDO_VOL_BIAS_CONFIG_HIGH + description: "Store the bit [3:29] of ido configuration parameters." + bitOffset: 0 + bitWidth: 27 + access: read-only + - name: PVT_LOW + description: "Store the bit [0:4] of pvt." + bitOffset: 27 + bitWidth: 5 + access: read-only + - register: + name: RD_BLK2_DATA3 + description: Register 3 of BLOCK2. + addressOffset: 76 + size: 32 + fields: + - name: PVT_HIGH + description: "Store the bit [5:14] of pvt." + bitOffset: 0 + bitWidth: 10 + access: read-only + - name: ADC_CALIBRATION_0 + description: "Store the bit [0:21] of ADC calibration data." + bitOffset: 10 + bitWidth: 22 + access: read-only + - register: + name: RD_BLK2_DATA4 + description: Register 4 of BLOCK2. + addressOffset: 80 + size: 32 + fields: + - name: ADC_CALIBRATION_1 + description: "Store the bit [22:53] of ADC calibration data." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_BLK2_DATA5 + description: Register 5 of BLOCK2. + addressOffset: 84 + size: 32 + fields: + - name: ADC_CALIBRATION_2 + description: "Store the bit [54:85] of ADC calibration data." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_BLK2_DATA6 + description: Register 6 of BLOCK2. + addressOffset: 88 + size: 32 + fields: + - name: ADC_CALIBRATION_3 + description: "Store the bit [86:96] of ADC calibration data." + bitOffset: 0 + bitWidth: 11 + access: read-only + - name: BLK2_RESERVED_DATA_0 + description: "Store the bit [0:20] of block2 reserved data." + bitOffset: 11 + bitWidth: 21 + access: read-only + - register: + name: RD_BLK2_DATA7 + description: Register 7 of BLOCK2. + addressOffset: 92 + size: 32 + fields: + - name: BLK2_RESERVED_DATA_1 + description: "Store the bit [21:52] of block2 reserved data." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_BLK3_DATA0 + description: Register 0 of BLOCK3. + addressOffset: 96 + size: 32 + fields: + - name: BLK3_DATA0 + description: Store the first 32-bit of Block3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_BLK3_DATA1 + description: Register 1 of BLOCK3. + addressOffset: 100 + size: 32 + fields: + - name: BLK3_DATA1 + description: Store the second 32-bit of Block3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_BLK3_DATA2 + description: Register 2 of BLOCK3. + addressOffset: 104 + size: 32 + fields: + - name: BLK3_DATA2 + description: Store the third 32-bit of Block3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_BLK3_DATA3 + description: Register 3 of BLOCK3. + addressOffset: 108 + size: 32 + fields: + - name: BLK3_DATA3 + description: Store the fourth 32-bit of Block3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_BLK3_DATA4 + description: Register 4 of BLOCK3. + addressOffset: 112 + size: 32 + fields: + - name: BLK3_DATA4 + description: Store the fifth 32-bit of Block3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_BLK3_DATA5 + description: Register 5 of BLOCK3. + addressOffset: 116 + size: 32 + fields: + - name: BLK3_DATA5 + description: Store the sixth 32-bit of Block3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_BLK3_DATA6 + description: Register 6 of BLOCK3. + addressOffset: 120 + size: 32 + fields: + - name: BLK3_DATA6 + description: Store the seventh 32-bit of Block3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_BLK3_DATA7 + description: Register 7 of BLOCK3. + addressOffset: 124 + size: 32 + fields: + - name: BLK3_DATA7 + description: Store the eighth 32-bit of Block3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_REPEAT_ERR + description: Programming error record register 0 of BLOCK0. + addressOffset: 128 + size: 32 + fields: + - name: RD_DIS_ERR + description: "If any bit in RD_DIS is 1, then it indicates a programming error." + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: WDT_DELAY_SEL_ERR + description: "If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error." + bitOffset: 2 + bitWidth: 2 + access: read-only + - name: DIS_PAD_JTAG_ERR + description: "If any bit in DIS_PAD_JTAG is 1, then it indicates a programming error." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_ICACHE_ERR + description: "If any bit in this filed is 1, then it indicates a programming error." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR + description: "If any bit in DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error." + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SPI_BOOT_ENCRYPT_DECRYPT_CNT_ERR + description: "If any bit in SPI_BOOT_ENCRYPT_DECRYPT_CNT is 1, then it indicates a programming error." + bitOffset: 7 + bitWidth: 3 + access: read-only + - name: XTS_KEY_LENGTH_256_ERR + description: "If any bit in XTS_KEY_LENGTH_256 is 1, then it indicates a programming error." + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: UART_PRINT_CONTROL_ERR + description: "If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error." + bitOffset: 11 + bitWidth: 2 + access: read-only + - name: FORCE_SEND_RESUME_ERR + description: "If any bit in FORCE_SEND_RESUME is 1, then it indicates a programming error." + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_MODE_ERR + description: "If any bit in this filed is 1, then it indicates a programming error." + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DIS_DIRECT_BOOT_ERR + description: "If any bit in this filed is 1, then it indicates a programming error." + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: ENABLE_SECURITY_DOWNLOAD_ERR + description: "If any bit in this filed is 1, then it indicates a programming error." + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: FLASH_TPUW_ERR + description: "If any bit in this filed is 1, then it indicates a programming error." + bitOffset: 17 + bitWidth: 4 + access: read-only + - name: SECURE_BOOT_EN_ERR + description: "If any bit in this filed is 1, then it indicates a programming error." + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED_ERR + description: Reserved. + bitOffset: 22 + bitWidth: 10 + access: read-only + - register: + name: RD_RS_ERR + description: Programming error record register 0 of BLOCK1-10. + addressOffset: 132 + size: 32 + fields: + - name: BLK1_ERR_NUM + description: The value of this signal means the number of error bytes in block1. + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: BLK1_FAIL + description: "0: Means no failure and that the data of block1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BLK2_ERR_NUM + description: The value of this signal means the number of error bytes in block2. + bitOffset: 4 + bitWidth: 3 + access: read-only + - name: BLK2_FAIL + description: "0: Means no failure and that the data of block2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: BLK3_ERR_NUM + description: The value of this signal means the number of error bytes in block3. + bitOffset: 8 + bitWidth: 3 + access: read-only + - name: BLK3_FAIL + description: "0: Means no failure and that the block3 data is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 11 + bitWidth: 1 + access: read-only + - register: + name: CLK + description: eFuse clcok configuration register. + addressOffset: 136 + size: 32 + resetValue: 2 + fields: + - name: EFUSE_MEM_FORCE_PD + description: Set this bit to force eFuse SRAM into power-saving mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_CLK_FORCE_ON + description: Set this bit and force to activate clock signal of eFuse SRAM. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EFUSE_MEM_FORCE_PU + description: Set this bit to force eFuse SRAM into working mode. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EN + description: Set this bit and force to enable clock signal of eFuse memory. + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: CONF + description: eFuse operation mode configuraiton register + addressOffset: 140 + size: 32 + fields: + - name: OP_CODE + description: "0x5A5A: Operate programming command 0x5AA5: Operate read command." + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: STATUS + description: eFuse status register. + addressOffset: 144 + size: 32 + fields: + - name: STATE + description: Indicates the state of the eFuse state machine. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: OTP_LOAD_SW + description: The value of OTP_LOAD_SW. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: OTP_VDDQ_C_SYNC2 + description: The value of OTP_VDDQ_C_SYNC2. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OTP_STROBE_SW + description: The value of OTP_STROBE_SW. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OTP_CSB_SW + description: The value of OTP_CSB_SW. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OTP_PGENB_SW + description: The value of OTP_PGENB_SW. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: OTP_VDDQ_IS_SW + description: The value of OTP_VDDQ_IS_SW. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: BLK0_VALID_BIT_CNT + description: "Record the number of bit '1' in BLOCK0." + bitOffset: 10 + bitWidth: 6 + access: read-only + - register: + name: CMD + description: eFuse command register. + addressOffset: 148 + size: 32 + fields: + - name: READ_CMD + description: Set this bit to send read command. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PGM_CMD + description: Set this bit to send programming command. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BLK_NUM + description: "The serial number of the block to be programmed. Value 0-3 corresponds to block number 0-3, respectively." + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: INT_RAW + description: eFuse raw interrupt register. + addressOffset: 152 + size: 32 + fields: + - name: READ_DONE_INT_RAW + description: The raw bit signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PGM_DONE_INT_RAW + description: The raw bit signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: eFuse interrupt status register. + addressOffset: 156 + size: 32 + fields: + - name: READ_DONE_INT_ST + description: The status signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PGM_DONE_INT_ST + description: The status signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: eFuse interrupt enable register. + addressOffset: 256 + size: 32 + fields: + - name: READ_DONE_INT_ENA + description: The enable signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PGM_DONE_INT_ENA + description: The enable signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: eFuse interrupt clear register. + addressOffset: 260 + size: 32 + fields: + - name: READ_DONE_INT_CLR + description: The clear signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: PGM_DONE_INT_CLR + description: The clear signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: DAC_CONF + description: Controls the eFuse programming voltage. + addressOffset: 264 + size: 32 + resetValue: 130588 + fields: + - name: DAC_CLK_DIV + description: Controls the division factor of the rising clock of the programming voltage. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: DAC_CLK_PAD_SEL + description: "Don't care." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DAC_NUM + description: Controls the rising period of the programming voltage. + bitOffset: 9 + bitWidth: 8 + access: read-write + - name: OE_CLR + description: Reduces the power supply of the programming voltage. + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: RD_TIM_CONF + description: Configures read timing parameters. + addressOffset: 268 + size: 32 + resetValue: 302055937 + fields: + - name: THR_A + description: Configures hold time for efuse read. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TRD + description: Configures pulse time for efuse read. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: TSUR_A + description: Configures setup time for efuse read. + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: READ_INIT_NUM + description: Configures the initial read time of eFuse. + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: WR_TIM_CONF0 + description: Configurarion register 0 of eFuse programming timing parameters. + addressOffset: 272 + size: 32 + resetValue: 13107457 + fields: + - name: THP_A + description: Configures hold time for efuse program. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TPGM_INACTIVE + description: "Configures pulse time for burning '0' bit." + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: TPGM + description: "Configures pulse time for burning '1' bit." + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: WR_TIM_CONF1 + description: Configurarion register 1 of eFuse programming timing parameters. + addressOffset: 276 + size: 32 + resetValue: 3145729 + fields: + - name: TSUP_A + description: Configures setup time for efuse program. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: PWR_ON_NUM + description: Configures the power up time for VDDQ. + bitOffset: 8 + bitWidth: 16 + access: read-write + - register: + name: WR_TIM_CONF2 + description: Configurarion register 2 of eFuse programming timing parameters. + addressOffset: 280 + size: 32 + resetValue: 400 + fields: + - name: PWR_OFF_NUM + description: Configures the power outage time for VDDQ. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: DATE + description: eFuse version register. + addressOffset: 508 + size: 32 + resetValue: 34636176 + fields: + - name: DATE + description: Stores eFuse version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: EXTMEM + description: External Memory + groupName: EXTMEM + baseAddress: 1611415552 + addressBlock: + - offset: 0 + size: 148 + usage: registers + registers: + - register: + name: ICACHE_CTRL + description: This description will be updated in the near future. + addressOffset: 0 + size: 32 + fields: + - name: ICACHE_ENABLE + description: "The bit is used to activate the data cache. 0: disable, 1: enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: ICACHE_CTRL1 + description: This description will be updated in the near future. + addressOffset: 4 + size: 32 + resetValue: 3 + fields: + - name: ICACHE_SHUT_IBUS + description: "The bit is used to disable core0 ibus, 0: enable, 1: disable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ICACHE_SHUT_DBUS + description: "The bit is used to disable core1 ibus, 0: enable, 1: disable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: ICACHE_TAG_POWER_CTRL + description: This description will be updated in the near future. + addressOffset: 8 + size: 32 + resetValue: 5 + fields: + - name: ICACHE_TAG_MEM_FORCE_ON + description: "The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ICACHE_TAG_MEM_FORCE_PD + description: "The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ICACHE_TAG_MEM_FORCE_PU + description: "The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up" + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: ICACHE_SYNC_CTRL + description: This description will be updated in the near future. + addressOffset: 40 + size: 32 + resetValue: 1 + fields: + - name: ICACHE_INVALIDATE_ENA + description: The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ICACHE_SYNC_DONE + description: The bit is used to indicate invalidate operation is finished. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: ICACHE_SYNC_ADDR + description: This description will be updated in the near future. + addressOffset: 44 + size: 32 + fields: + - name: ICACHE_SYNC_ADDR + description: The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ICACHE_SYNC_SIZE + description: This description will be updated in the near future. + addressOffset: 48 + size: 32 + fields: + - name: ICACHE_SYNC_SIZE + description: The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG. + bitOffset: 0 + bitWidth: 23 + access: read-write + - register: + name: IBUS_TO_FLASH_START_VADDR + description: This description will be updated in the near future. + addressOffset: 84 + size: 32 + resetValue: 1107296256 + fields: + - name: IBUS_TO_FLASH_START_VADDR + description: The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: IBUS_TO_FLASH_END_VADDR + description: This description will be updated in the near future. + addressOffset: 88 + size: 32 + resetValue: 1111490559 + fields: + - name: IBUS_TO_FLASH_END_VADDR + description: The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DBUS_TO_FLASH_START_VADDR + description: This description will be updated in the near future. + addressOffset: 92 + size: 32 + resetValue: 1006632960 + fields: + - name: DBUS_TO_FLASH_START_VADDR + description: The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DBUS_TO_FLASH_END_VADDR + description: This description will be updated in the near future. + addressOffset: 96 + size: 32 + resetValue: 1010827263 + fields: + - name: DBUS_TO_FLASH_END_VADDR + description: The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CACHE_ACS_CNT_CLR + description: This description will be updated in the near future. + addressOffset: 100 + size: 32 + fields: + - name: IBUS_ACS_CNT_CLR + description: The bit is used to clear ibus counter. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: DBUS_ACS_CNT_CLR + description: The bit is used to clear dbus counter. + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: CACHE_ILG_INT_ENA + description: This description will be updated in the near future. + addressOffset: 120 + size: 32 + fields: + - name: ICACHE_SYNC_OP_FAULT_INT_ENA + description: The bit is used to enable interrupt by sync configurations fault. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ICACHE_PRELOAD_OP_FAULT_INT_ENA + description: The bit is used to enable interrupt by preload configurations fault. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MMU_ENTRY_FAULT_INT_ENA + description: The bit is used to enable interrupt by mmu entry fault. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: IBUS_CNT_OVF_INT_ENA + description: The bit is used to enable interrupt by ibus counter overflow. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DBUS_CNT_OVF_INT_ENA + description: The bit is used to enable interrupt by dbus counter overflow. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: CACHE_ILG_INT_CLR + description: This description will be updated in the near future. + addressOffset: 124 + size: 32 + fields: + - name: ICACHE_SYNC_OP_FAULT_INT_CLR + description: The bit is used to clear interrupt by sync configurations fault. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ICACHE_PRELOAD_OP_FAULT_INT_CLR + description: The bit is used to clear interrupt by preload configurations fault. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: MMU_ENTRY_FAULT_INT_CLR + description: The bit is used to clear interrupt by mmu entry fault. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: IBUS_CNT_OVF_INT_CLR + description: The bit is used to clear interrupt by ibus counter overflow. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: DBUS_CNT_OVF_INT_CLR + description: The bit is used to clear interrupt by dbus counter overflow. + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: CACHE_ILG_INT_ST + description: This description will be updated in the near future. + addressOffset: 128 + size: 32 + fields: + - name: ICACHE_SYNC_OP_FAULT_ST + description: The bit is used to indicate interrupt by sync configurations fault. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ICACHE_PRELOAD_OP_FAULT_ST + description: The bit is used to indicate interrupt by preload configurations fault. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: MMU_ENTRY_FAULT_ST + description: The bit is used to indicate interrupt by mmu entry fault. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: IBUS_ACS_CNT_OVF_ST + description: The bit is used to indicate interrupt by ibus access flash/spiram counter overflow. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IBUS_ACS_MISS_CNT_OVF_ST + description: The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DBUS_ACS_CNT_OVF_ST + description: The bit is used to indicate interrupt by dbus access flash/spiram counter overflow. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: DBUS_ACS_FLASH_MISS_CNT_OVF_ST + description: The bit is used to indicate interrupt by dbus access flash miss counter overflow. + bitOffset: 10 + bitWidth: 1 + access: read-only + - register: + name: CORE0_ACS_CACHE_INT_ENA + description: This description will be updated in the near future. + addressOffset: 132 + size: 32 + fields: + - name: CORE0_IBUS_ACS_MSK_IC_INT_ENA + description: The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE0_IBUS_WR_IC_INT_ENA + description: The bit is used to enable interrupt by ibus trying to write icache + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CORE0_IBUS_REJECT_INT_ENA + description: The bit is used to enable interrupt by authentication fail. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CORE0_DBUS_ACS_MSK_IC_INT_ENA + description: The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CORE0_DBUS_REJECT_INT_ENA + description: The bit is used to enable interrupt by authentication fail. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CORE0_DBUS_WR_IC_INT_ENA + description: The bit is used to enable interrupt by dbus trying to write icache + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: CORE0_ACS_CACHE_INT_CLR + description: This description will be updated in the near future. + addressOffset: 136 + size: 32 + fields: + - name: CORE0_IBUS_ACS_MSK_IC_INT_CLR + description: The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CORE0_IBUS_WR_IC_INT_CLR + description: The bit is used to clear interrupt by ibus trying to write icache + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CORE0_IBUS_REJECT_INT_CLR + description: The bit is used to clear interrupt by authentication fail. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CORE0_DBUS_ACS_MSK_IC_INT_CLR + description: The bit is used to clear interrupt by cpu access icache while the corresponding dbus is disabled or icache is disabled which include speculative access. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: CORE0_DBUS_REJECT_INT_CLR + description: The bit is used to clear interrupt by authentication fail. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: CORE0_DBUS_WR_IC_INT_CLR + description: The bit is used to clear interrupt by dbus trying to write icache + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: CORE0_ACS_CACHE_INT_ST + description: This description will be updated in the near future. + addressOffset: 140 + size: 32 + fields: + - name: CORE0_IBUS_ACS_MSK_ICACHE_ST + description: The bit is used to indicate interrupt by cpu access icache while the core0_ibus is disabled or icache is disabled which include speculative access. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE0_IBUS_WR_ICACHE_ST + description: The bit is used to indicate interrupt by ibus trying to write icache + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CORE0_IBUS_REJECT_ST + description: The bit is used to indicate interrupt by authentication fail. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CORE0_DBUS_ACS_MSK_ICACHE_ST + description: The bit is used to indicate interrupt by cpu access icache while the core0_dbus is disabled or icache is disabled which include speculative access. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: CORE0_DBUS_REJECT_ST + description: The bit is used to indicate interrupt by authentication fail. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: CORE0_DBUS_WR_ICACHE_ST + description: The bit is used to indicate interrupt by dbus trying to write icache + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: CORE0_DBUS_REJECT_ST + description: This description will be updated in the near future. + addressOffset: 144 + size: 32 + fields: + - name: CORE0_DBUS_ATTR + description: "The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able." + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: CORE0_DBUS_WORLD + description: "The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1" + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: CORE0_DBUS_REJECT_VADDR + description: This description will be updated in the near future. + addressOffset: 148 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE0_DBUS_VADDR + description: The bits are used to indicate the virtual address of CPU access dbus when authentication fail. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE0_IBUS_REJECT_ST + description: This description will be updated in the near future. + addressOffset: 152 + size: 32 + fields: + - name: CORE0_IBUS_ATTR + description: "The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able" + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: CORE0_IBUS_WORLD + description: "The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1" + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: CORE0_IBUS_REJECT_VADDR + description: This description will be updated in the near future. + addressOffset: 156 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE0_IBUS_VADDR + description: The bits are used to indicate the virtual address of CPU access ibus when authentication fail. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CACHE_MMU_FAULT_CONTENT + description: This description will be updated in the near future. + addressOffset: 160 + size: 32 + fields: + - name: CACHE_MMU_FAULT_CONTENT + description: The bits are used to indicate the content of mmu entry which cause mmu fault.. + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: CACHE_MMU_FAULT_CODE + description: "The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache." + bitOffset: 10 + bitWidth: 4 + access: read-only + - register: + name: CACHE_MMU_FAULT_VADDR + description: This description will be updated in the near future. + addressOffset: 164 + size: 32 + fields: + - name: CACHE_MMU_FAULT_VADDR + description: The bits are used to indicate the virtual address which cause mmu fault.. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CACHE_WRAP_AROUND_CTRL + description: This description will be updated in the near future. + addressOffset: 168 + size: 32 + fields: + - name: CACHE_FLASH_WRAP_AROUND + description: The bit is used to enable wrap around mode when read data from flash. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CACHE_MMU_POWER_CTRL + description: This description will be updated in the near future. + addressOffset: 172 + size: 32 + resetValue: 5 + fields: + - name: CACHE_MMU_MEM_FORCE_ON + description: "The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CACHE_MMU_MEM_FORCE_PD + description: "The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CACHE_MMU_MEM_FORCE_PU + description: "The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up" + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: CACHE_STATE + description: This description will be updated in the near future. + addressOffset: 176 + size: 32 + resetValue: 1 + fields: + - name: ICACHE_STATE + description: "The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state" + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE + description: This description will be updated in the near future. + addressOffset: 180 + size: 32 + fields: + - name: RECORD_DISABLE_DB_ENCRYPT + description: Reserved. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RECORD_DISABLE_G0CB_DECRYPT + description: Reserved. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON + description: This description will be updated in the near future. + addressOffset: 184 + size: 32 + resetValue: 7 + fields: + - name: CLK_FORCE_ON_MANUAL_CRYPT + description: "The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CLK_FORCE_ON_AUTO_CRYPT + description: "The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CLK_FORCE_ON_CRYPT + description: "The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: CACHE_PRELOAD_INT_CTRL + description: This description will be updated in the near future. + addressOffset: 188 + size: 32 + fields: + - name: ICACHE_PRELOAD_INT_ST + description: The bit is used to indicate the interrupt by icache pre-load done. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ICACHE_PRELOAD_INT_ENA + description: The bit is used to enable the interrupt by icache pre-load done. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ICACHE_PRELOAD_INT_CLR + description: The bit is used to clear the interrupt by icache pre-load done. + bitOffset: 2 + bitWidth: 1 + access: write-only + - register: + name: CACHE_SYNC_INT_CTRL + description: This description will be updated in the near future. + addressOffset: 192 + size: 32 + fields: + - name: ICACHE_SYNC_INT_ST + description: The bit is used to indicate the interrupt by icache sync done. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ICACHE_SYNC_INT_ENA + description: The bit is used to enable the interrupt by icache sync done. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ICACHE_SYNC_INT_CLR + description: The bit is used to clear the interrupt by icache sync done. + bitOffset: 2 + bitWidth: 1 + access: write-only + - register: + name: CACHE_MMU_OWNER + description: This description will be updated in the near future. + addressOffset: 196 + size: 32 + fields: + - name: CACHE_MMU_OWNER + description: "The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus" + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CACHE_CONF_MISC + description: This description will be updated in the near future. + addressOffset: 200 + size: 32 + resetValue: 7 + fields: + - name: CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT + description: The bit is used to disable checking mmu entry fault by preload operation. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT + description: The bit is used to disable checking mmu entry fault by sync operation. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CACHE_TRACE_ENA + description: The bit is used to enable cache trace function. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CACHE_MMU_PAGE_SIZE + description: "This bit is used to choose mmu page size. 2:64KB. 1. 32KB. 0: 16KB" + bitOffset: 3 + bitWidth: 2 + access: read-write + - register: + name: ICACHE_FREEZE + description: This description will be updated in the near future. + addressOffset: 204 + size: 32 + fields: + - name: ENA + description: The bit is used to enable icache freeze mode + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MODE + description: "The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DONE + description: The bit is used to indicate icache freeze success + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: ICACHE_ATOMIC_OPERATE_ENA + description: This description will be updated in the near future. + addressOffset: 208 + size: 32 + resetValue: 1 + fields: + - name: ICACHE_ATOMIC_OPERATE_ENA + description: "The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CACHE_REQUEST + description: This description will be updated in the near future. + addressOffset: 212 + size: 32 + fields: + - name: BYPASS + description: The bit is used to disable request recording which could cause performance issue + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CLOCK_GATE + description: This description will be updated in the near future. + addressOffset: 256 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: clock gate enable. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: REG_DATE + description: This description will be updated in the near future. + addressOffset: 1020 + size: 32 + resetValue: 34631760 + fields: + - name: DATE + description: version information + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: GPIO + description: General Purpose Input/Output + groupName: GPIO + baseAddress: 1610629120 + addressBlock: + - offset: 0 + size: 788 + usage: registers + interrupt: + - name: GPIO + value: 13 + - name: GPIO_NMI + value: 14 + registers: + - register: + name: BT_SELECT + description: GPIO bit select register + addressOffset: 0 + size: 32 + fields: + - name: BT_SEL + description: GPIO bit select register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: OUT + description: GPIO output register + addressOffset: 4 + size: 32 + fields: + - name: DATA_ORIG + description: GPIO output register for GPIO0-24 + bitOffset: 0 + bitWidth: 25 + access: read-write + - register: + name: OUT_W1TS + description: GPIO output set register + addressOffset: 8 + size: 32 + fields: + - name: OUT_W1TS + description: GPIO output set register for GPIO0-24 + bitOffset: 0 + bitWidth: 25 + access: write-only + - register: + name: OUT_W1TC + description: GPIO output clear register + addressOffset: 12 + size: 32 + fields: + - name: OUT_W1TC + description: GPIO output clear register for GPIO0-24 + bitOffset: 0 + bitWidth: 25 + access: write-only + - register: + name: SDIO_SELECT + description: GPIO sdio select register + addressOffset: 28 + size: 32 + fields: + - name: SDIO_SEL + description: GPIO sdio select register + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: ENABLE + description: GPIO output enable register + addressOffset: 32 + size: 32 + fields: + - name: DATA + description: GPIO output enable register for GPIO0-24 + bitOffset: 0 + bitWidth: 25 + access: read-write + - register: + name: ENABLE_W1TS + description: GPIO output enable set register + addressOffset: 36 + size: 32 + fields: + - name: ENABLE_W1TS + description: GPIO output enable set register for GPIO0-24 + bitOffset: 0 + bitWidth: 25 + access: write-only + - register: + name: ENABLE_W1TC + description: GPIO output enable clear register + addressOffset: 40 + size: 32 + fields: + - name: ENABLE_W1TC + description: GPIO output enable clear register for GPIO0-24 + bitOffset: 0 + bitWidth: 25 + access: write-only + - register: + name: STRAP + description: pad strapping register + addressOffset: 56 + size: 32 + fields: + - name: STRAPPING + description: pad strapping register + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: IN + description: GPIO input register + addressOffset: 60 + size: 32 + fields: + - name: DATA_NEXT + description: GPIO input register for GPIO0-24 + bitOffset: 0 + bitWidth: 25 + access: read-only + - register: + name: STATUS + description: GPIO interrupt status register + addressOffset: 68 + size: 32 + fields: + - name: INTERRUPT + description: GPIO interrupt status register for GPIO0-24 + bitOffset: 0 + bitWidth: 25 + access: read-write + - register: + name: STATUS_W1TS + description: GPIO interrupt status set register + addressOffset: 72 + size: 32 + fields: + - name: STATUS_W1TS + description: GPIO interrupt status set register for GPIO0-24 + bitOffset: 0 + bitWidth: 25 + access: write-only + - register: + name: STATUS_W1TC + description: GPIO interrupt status clear register + addressOffset: 76 + size: 32 + fields: + - name: STATUS_W1TC + description: GPIO interrupt status clear register for GPIO0-24 + bitOffset: 0 + bitWidth: 25 + access: write-only + - register: + name: PCPU_INT + description: GPIO PRO_CPU interrupt status register + addressOffset: 92 + size: 32 + fields: + - name: PROCPU_INT + description: GPIO PRO_CPU interrupt status register for GPIO0-24 + bitOffset: 0 + bitWidth: 25 + access: read-only + - register: + name: PCPU_NMI_INT + description: GPIO PRO_CPU(not shielded) interrupt status register + addressOffset: 96 + size: 32 + fields: + - name: PROCPU_NMI_INT + description: GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-24 + bitOffset: 0 + bitWidth: 25 + access: read-only + - register: + name: CPUSDIO_INT + description: GPIO CPUSDIO interrupt status register + addressOffset: 100 + size: 32 + fields: + - name: SDIO_INT + description: GPIO CPUSDIO interrupt status register for GPIO0-24 + bitOffset: 0 + bitWidth: 25 + access: read-only + - register: + dim: 25 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24" + name: PIN%s + description: GPIO pin configuration register + addressOffset: 116 + size: 32 + fields: + - name: SYNC2_BYPASS + description: "set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: PAD_DRIVER + description: "set this bit to select pad driver. 1:open-drain. 0:normal." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SYNC1_BYPASS + description: "set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge." + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: INT_TYPE + description: "set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CONFIG + description: reserved + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: INT_ENA + description: set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. + bitOffset: 13 + bitWidth: 5 + access: read-write + - register: + name: STATUS_NEXT + description: GPIO interrupt source register + addressOffset: 332 + size: 32 + fields: + - name: STATUS_INTERRUPT_NEXT + description: GPIO interrupt source register for GPIO0-24 + bitOffset: 0 + bitWidth: 26 + access: read-only + - register: + dim: 128 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" + name: FUNC%s_IN_SEL_CFG + description: GPIO input function configuration register + addressOffset: 340 + size: 32 + fields: + - name: IN_SEL + description: "set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level." + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: IN_INV_SEL + description: "set this bit to invert input signal. 1:invert. 0:not invert." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SEL + description: "set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO." + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + dim: 25 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24" + name: FUNC%s_OUT_SEL_CFG + description: GPIO output function select register + addressOffset: 1364 + size: 32 + resetValue: 128 + fields: + - name: OUT_SEL + description: "The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n]." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: INV_SEL + description: "set this bit to invert output signal.1:invert.0:not invert." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: OEN_SEL + description: "set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OEN_INV_SEL + description: "set this bit to invert output enable signal.1:invert.0:not invert." + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: CLOCK_GATE + description: GPIO clock gate register + addressOffset: 1580 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: set this bit to enable GPIO clock gate + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: REG_DATE + description: GPIO version register + addressOffset: 1788 + size: 32 + resetValue: 34627984 + fields: + - name: REG_DATE + description: version register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: I2C0 + description: I2C (Inter-Integrated Circuit) Controller 0 + groupName: I2C + baseAddress: 1610690560 + addressBlock: + - offset: 0 + size: 136 + usage: registers + interrupt: + - name: I2C_MST + value: 11 + - name: I2C_EXT0 + value: 22 + registers: + - register: + name: SCL_LOW_PERIOD + description: "Configures the low level width of the SCL\nClock" + addressOffset: 0 + size: 32 + fields: + - name: SCL_LOW_PERIOD + description: "This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: CTR + description: Transmission setting + addressOffset: 4 + size: 32 + resetValue: 523 + fields: + - name: SDA_FORCE_OUT + description: "0: direct output, 1: open drain output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_FORCE_OUT + description: "0: direct output, 1: open drain output." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SAMPLE_SCL_LEVEL + description: "This register is used to select the sample mode.\n1: sample SDA data on the SCL low level.\n0: sample SDA data on the SCL high level." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_FULL_ACK_LEVEL + description: This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MS_MODE + description: "Set this bit to configure the module as an I2C Master. Clear this bit to configure the\nmodule as an I2C Slave." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TRANS_START + description: Set this bit to start sending the data in txfifo. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TX_LSB_FIRST + description: "This bit is used to control the sending mode for data needing to be sent. \n1: send data from the least significant bit,\n0: send data from the most significant bit." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_LSB_FIRST + description: "This bit is used to control the storage mode for received data.\n1: receive data from the least significant bit,\n0: receive data from the most significant bit." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ARBITRATION_EN + description: This is the enable bit for arbitration_lost. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FSM_RST + description: This register is used to reset the scl FMS. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: CONF_UPGATE + description: synchronization bit + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: SLV_TX_AUTO_START_EN + description: This is the enable bit for slave to send data automatically + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: SR + description: Describe I2C work status. + addressOffset: 8 + size: 32 + fields: + - name: RESP_REC + description: "The received ACK value in master mode or slave mode. 0: ACK, 1: NACK." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ARB_LOST + description: "When the I2C controller loses control of SCL line, this register changes to 1." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BUS_BUSY + description: "1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: RXFIFO_CNT + description: This field represents the amount of data needed to be sent. + bitOffset: 8 + bitWidth: 5 + access: read-only + - name: TXFIFO_CNT + description: This field stores the amount of received data in RAM. + bitOffset: 18 + bitWidth: 5 + access: read-only + - name: SCL_MAIN_STATE_LAST + description: "This field indicates the states of the I2C module state machine. \n0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK" + bitOffset: 24 + bitWidth: 3 + access: read-only + - name: SCL_STATE_LAST + description: "This field indicates the states of the state machine used to produce SCL.\n0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop" + bitOffset: 28 + bitWidth: 3 + access: read-only + - register: + name: TO + description: Setting time out control for receiving data. + addressOffset: 12 + size: 32 + resetValue: 16 + fields: + - name: TIME_OUT_VALUE + description: "This register is used to configure the timeout for receiving a data bit in APB\nclock cycles." + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: TIME_OUT_EN + description: This is the enable bit for time out control. + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: FIFO_ST + description: FIFO status register. + addressOffset: 20 + size: 32 + fields: + - name: RXFIFO_RADDR + description: This is the offset address of the APB reading from rxfifo + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: RXFIFO_WADDR + description: This is the offset address of i2c module receiving data and writing to rxfifo. + bitOffset: 5 + bitWidth: 4 + access: read-only + - name: TXFIFO_RADDR + description: This is the offset address of i2c module reading from txfifo. + bitOffset: 10 + bitWidth: 4 + access: read-only + - name: TXFIFO_WADDR + description: This is the offset address of APB bus writing to txfifo. + bitOffset: 15 + bitWidth: 4 + access: read-only + - register: + name: FIFO_CONF + description: FIFO configuration register. + addressOffset: 24 + size: 32 + resetValue: 16454 + fields: + - name: RXFIFO_WM_THRHD + description: "The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: TXFIFO_WM_THRHD + description: "The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid." + bitOffset: 5 + bitWidth: 4 + access: read-write + - name: NONFIFO_EN + description: Set this bit to enable APB nonfifo access. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: RX_FIFO_RST + description: Set this bit to reset rx-fifo. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_FIFO_RST + description: Set this bit to reset tx-fifo. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FIFO_PRT_EN + description: "The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty." + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DATA + description: Rx FIFO read data. + addressOffset: 28 + size: 32 + fields: + - name: FIFO_RDATA + description: The value of rx FIFO read data. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 32 + size: 32 + resetValue: 2 + fields: + - name: RXFIFO_WM_INT_RAW + description: The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_WM_INT_RAW + description: The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_RAW + description: The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: END_DETECT_INT_RAW + description: The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS_DONE_INT_RAW + description: The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_RAW + description: The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: MST_TXFIFO_UDF_INT_RAW + description: The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_RAW + description: The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_RAW + description: The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TRANS_START_INT_RAW + description: The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: NACK_INT_RAW + description: The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: TXFIFO_OVF_INT_RAW + description: The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: RXFIFO_UDF_INT_RAW + description: The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SCL_ST_TO_INT_RAW + description: The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SCL_MAIN_ST_TO_INT_RAW + description: The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DET_START_INT_RAW + description: The raw interrupt bit for I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 36 + size: 32 + fields: + - name: RXFIFO_WM_INT_CLR + description: Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TXFIFO_WM_INT_CLR + description: Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RXFIFO_OVF_INT_CLR + description: Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: END_DETECT_INT_CLR + description: Set this bit to clear the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: BYTE_TRANS_DONE_INT_CLR + description: Set this bit to clear the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: ARBITRATION_LOST_INT_CLR + description: Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: MST_TXFIFO_UDF_INT_CLR + description: Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TRANS_COMPLETE_INT_CLR + description: Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: TIME_OUT_INT_CLR + description: Set this bit to clear the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: TRANS_START_INT_CLR + description: Set this bit to clear the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: NACK_INT_CLR + description: Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: TXFIFO_OVF_INT_CLR + description: Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: RXFIFO_UDF_INT_CLR + description: Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: SCL_ST_TO_INT_CLR + description: Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SCL_MAIN_ST_TO_INT_CLR + description: Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: DET_START_INT_CLR + description: Set this bit to clear I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 40 + size: 32 + fields: + - name: RXFIFO_WM_INT_ENA + description: The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_WM_INT_ENA + description: The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_ENA + description: The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: END_DETECT_INT_ENA + description: The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: BYTE_TRANS_DONE_INT_ENA + description: The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ARBITRATION_LOST_INT_ENA + description: The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: MST_TXFIFO_UDF_INT_ENA + description: The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TRANS_COMPLETE_INT_ENA + description: The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TIME_OUT_INT_ENA + description: The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TRANS_START_INT_ENA + description: The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: NACK_INT_ENA + description: The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TXFIFO_OVF_INT_ENA + description: The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RXFIFO_UDF_INT_ENA + description: The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SCL_ST_TO_INT_ENA + description: The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SCL_MAIN_ST_TO_INT_ENA + description: The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DET_START_INT_ENA + description: The interrupt enable bit for I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: INT_STATUS + description: Status of captured I2C communication events + addressOffset: 44 + size: 32 + fields: + - name: RXFIFO_WM_INT_ST + description: The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_WM_INT_ST + description: The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_ST + description: The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: END_DETECT_INT_ST + description: The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS_DONE_INT_ST + description: The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_ST + description: The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: MST_TXFIFO_UDF_INT_ST + description: The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_ST + description: The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_ST + description: The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TRANS_START_INT_ST + description: The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: NACK_INT_ST + description: The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: TXFIFO_OVF_INT_ST + description: The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: RXFIFO_UDF_INT_ST + description: The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SCL_ST_TO_INT_ST + description: The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SCL_MAIN_ST_TO_INT_ST + description: The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DET_START_INT_ST + description: The masked interrupt status bit for I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - register: + name: SDA_HOLD + description: Configures the hold time after a negative SCL edge. + addressOffset: 48 + size: 32 + fields: + - name: TIME + description: "This register is used to configure the time to hold the data after the negative\nedge of SCL, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SDA_SAMPLE + description: Configures the sample time after a positive SCL edge. + addressOffset: 52 + size: 32 + fields: + - name: TIME + description: "This register is used to configure for how long SDA is sampled, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_HIGH_PERIOD + description: Configures the high level width of SCL + addressOffset: 56 + size: 32 + fields: + - name: SCL_HIGH_PERIOD + description: "This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: SCL_WAIT_HIGH_PERIOD + description: "This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles." + bitOffset: 9 + bitWidth: 7 + access: read-write + - register: + name: SCL_START_HOLD + description: Configures the delay between the SDA and SCL negative edge for a start condition + addressOffset: 64 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the time between the negative edge\nof SDA and the negative edge of SCL for a START condition, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_RSTART_SETUP + description: "Configures the delay between the positive\nedge of SCL and the negative edge of SDA" + addressOffset: 68 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the time between the positive\nedge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_STOP_HOLD + description: "Configures the delay after the SCL clock\nedge for a stop condition" + addressOffset: 72 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the delay after the STOP condition,\nin I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_STOP_SETUP + description: "Configures the delay between the SDA and\nSCL positive edge for a stop condition" + addressOffset: 76 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the time between the positive edge\nof SCL and the positive edge of SDA, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: FILTER_CFG + description: SCL and SDA filter configuration register + addressOffset: 80 + size: 32 + resetValue: 768 + fields: + - name: SCL_FILTER_THRES + description: "When a pulse on the SCL input has smaller width than this register value\nin I2C module clock cycles, the I2C controller will ignore that pulse." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: SDA_FILTER_THRES + description: "When a pulse on the SDA input has smaller width than this register value\nin I2C module clock cycles, the I2C controller will ignore that pulse." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: SCL_FILTER_EN + description: This is the filter enable bit for SCL. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SDA_FILTER_EN + description: This is the filter enable bit for SDA. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: CLK_CONF + description: I2C CLK configuration register + addressOffset: 84 + size: 32 + resetValue: 2097152 + fields: + - name: SCLK_DIV_NUM + description: the integral part of the fractional divisor for i2c module + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SCLK_DIV_A + description: the numerator of the fractional part of the fractional divisor for i2c module + bitOffset: 8 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_B + description: the denominator of the fractional part of the fractional divisor for i2c module + bitOffset: 14 + bitWidth: 6 + access: read-write + - name: SCLK_SEL + description: "The clock selection for i2c module:0-XTAL,1-CLK_8MHz." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SCLK_ACTIVE + description: The clock switch for i2c module + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7" + name: COMD%s + description: I2C command register %s + addressOffset: 88 + size: 32 + fields: + - name: COMMAND + description: "This is the content of command 0. It consists of three parts: \nop_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.\nByte_num represents the number of bytes that need to be sent or received.\nack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more\nInformation." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND_DONE + description: "When command 0 is done in I2C Master mode, this bit changes to high\nlevel." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SCL_ST_TIME_OUT + description: SCL status time out register + addressOffset: 120 + size: 32 + resetValue: 16 + fields: + - name: SCL_ST_TO_I2C + description: The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SCL_MAIN_ST_TIME_OUT + description: SCL main status time out register + addressOffset: 124 + size: 32 + resetValue: 16 + fields: + - name: SCL_MAIN_ST_TO_I2C + description: The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23 + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SCL_SP_CONF + description: Power configuration register + addressOffset: 128 + size: 32 + fields: + - name: SCL_RST_SLV_EN + description: "When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_RST_SLV_NUM + description: Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. + bitOffset: 1 + bitWidth: 5 + access: read-write + - name: SCL_PD_EN + description: "The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SDA_PD_EN + description: "The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low." + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version register + addressOffset: 248 + size: 32 + resetValue: 34628163 + fields: + - name: DATE + description: This is the the version register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TXFIFO_START_ADDR + description: I2C TXFIFO base address register + addressOffset: 256 + size: 32 + fields: + - name: TXFIFO_START_ADDR + description: This is the I2C txfifo first address. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RXFIFO_START_ADDR + description: I2C RXFIFO base address register + addressOffset: 384 + size: 32 + fields: + - name: RXFIFO_START_ADDR + description: This is the I2C rxfifo first address. + bitOffset: 0 + bitWidth: 32 + access: read-only + - name: INTERRUPT_CORE0 + description: Interrupt Controller (Core 0) + groupName: INTERRUPT_CORE0 + baseAddress: 1611407360 + addressBlock: + - offset: 0 + size: 336 + usage: registers + interrupt: + - name: WIFI_MAC + value: 0 + - name: WIFI_MAC_NMI + value: 1 + - name: WIFI_PWR + value: 2 + - name: WIFI_BB + value: 3 + - name: BT_MAC + value: 4 + - name: BT_BB + value: 5 + - name: BT_BB_NMI + value: 6 + - name: LP_TIMER + value: 7 + - name: COEX + value: 8 + - name: BLE_TIMER + value: 9 + - name: BLE_SEC + value: 10 + - name: CACHE_IA + value: 25 + - name: ICACHE_PRELOAD0 + value: 30 + - name: ICACHE_SYNC0 + value: 31 + - name: ECC + value: 35 + - name: FROM_CPU_INTR0 + value: 36 + - name: FROM_CPU_INTR1 + value: 37 + - name: FROM_CPU_INTR2 + value: 38 + - name: FROM_CPU_INTR3 + value: 39 + - name: ETS_CORE0_PIF_PMS_SIZE + value: 41 + registers: + - register: + name: MAC_INTR_MAP + description: register description + addressOffset: 0 + size: 32 + fields: + - name: WIFI_MAC_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: WIFI_MAC_NMI_MAP + description: register description + addressOffset: 4 + size: 32 + fields: + - name: WIFI_MAC_NMI_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: WIFI_PWR_INT_MAP + description: register description + addressOffset: 8 + size: 32 + fields: + - name: WIFI_PWR_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: WIFI_BB_INT_MAP + description: register description + addressOffset: 12 + size: 32 + fields: + - name: WIFI_BB_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BT_MAC_INT_MAP + description: register description + addressOffset: 16 + size: 32 + fields: + - name: BT_MAC_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BT_BB_INT_MAP + description: register description + addressOffset: 20 + size: 32 + fields: + - name: BT_BB_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BT_BB_NMI_MAP + description: register description + addressOffset: 24 + size: 32 + fields: + - name: BT_BB_NMI_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: LP_TIMER_INT_MAP + description: register description + addressOffset: 28 + size: 32 + fields: + - name: LP_TIMER_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: COEX_INT_MAP + description: register description + addressOffset: 32 + size: 32 + fields: + - name: COEX_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BLE_TIMER_INT_MAP + description: register description + addressOffset: 36 + size: 32 + fields: + - name: BLE_TIMER_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BLE_SEC_INT_MAP + description: register description + addressOffset: 40 + size: 32 + fields: + - name: BLE_SEC_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: I2C_MST_INT_MAP + description: register description + addressOffset: 44 + size: 32 + fields: + - name: I2C_MST_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APB_CTRL_INTR_MAP + description: register description + addressOffset: 48 + size: 32 + fields: + - name: APB_CTRL_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: GPIO_INTERRUPT_PRO_MAP + description: register description + addressOffset: 52 + size: 32 + fields: + - name: GPIO_INTERRUPT_PRO_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: GPIO_INTERRUPT_PRO_NMI_MAP + description: register description + addressOffset: 56 + size: 32 + fields: + - name: GPIO_INTERRUPT_PRO_NMI_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SPI_INTR_1_MAP + description: register description + addressOffset: 60 + size: 32 + fields: + - name: SPI_INTR_1_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SPI_INTR_2_MAP + description: register description + addressOffset: 64 + size: 32 + fields: + - name: SPI_INTR_2_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: UART_INTR_MAP + description: register description + addressOffset: 68 + size: 32 + fields: + - name: UART_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: UART1_INTR_MAP + description: register description + addressOffset: 72 + size: 32 + fields: + - name: UART1_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: LEDC_INT_MAP + description: register description + addressOffset: 76 + size: 32 + fields: + - name: LEDC_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: EFUSE_INT_MAP + description: register description + addressOffset: 80 + size: 32 + fields: + - name: EFUSE_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RTC_CORE_INTR_MAP + description: register description + addressOffset: 84 + size: 32 + fields: + - name: RTC_CORE_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: I2C_EXT0_INTR_MAP + description: register description + addressOffset: 88 + size: 32 + fields: + - name: I2C_EXT0_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG_T0_INT_MAP + description: register description + addressOffset: 92 + size: 32 + fields: + - name: TG_T0_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG_WDT_INT_MAP + description: register description + addressOffset: 96 + size: 32 + fields: + - name: TG_WDT_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CACHE_IA_INT_MAP + description: register description + addressOffset: 100 + size: 32 + fields: + - name: CACHE_IA_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SYSTIMER_TARGET0_INT_MAP + description: register description + addressOffset: 104 + size: 32 + fields: + - name: SYSTIMER_TARGET0_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SYSTIMER_TARGET1_INT_MAP + description: register description + addressOffset: 108 + size: 32 + fields: + - name: SYSTIMER_TARGET1_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SYSTIMER_TARGET2_INT_MAP + description: register description + addressOffset: 112 + size: 32 + fields: + - name: SYSTIMER_TARGET2_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SPI_MEM_REJECT_INTR_MAP + description: register description + addressOffset: 116 + size: 32 + fields: + - name: SPI_MEM_REJECT_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: ICACHE_PRELOAD_INT_MAP + description: register description + addressOffset: 120 + size: 32 + fields: + - name: ICACHE_PRELOAD_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: ICACHE_SYNC_INT_MAP + description: register description + addressOffset: 124 + size: 32 + fields: + - name: ICACHE_SYNC_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APB_ADC_INT_MAP + description: register description + addressOffset: 128 + size: 32 + fields: + - name: APB_ADC_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_CH0_INT_MAP + description: register description + addressOffset: 132 + size: 32 + fields: + - name: DMA_CH0_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SHA_INT_MAP + description: register description + addressOffset: 136 + size: 32 + fields: + - name: SHA_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: ECC_INT_MAP + description: register description + addressOffset: 140 + size: 32 + fields: + - name: ECC_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_0_MAP + description: register description + addressOffset: 144 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_0_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_1_MAP + description: register description + addressOffset: 148 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_1_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_2_MAP + description: register description + addressOffset: 152 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_2_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_3_MAP + description: register description + addressOffset: 156 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_3_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: ASSIST_DEBUG_INTR_MAP + description: register description + addressOffset: 160 + size: 32 + fields: + - name: ASSIST_DEBUG_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + description: register description + addressOffset: 164 + size: 32 + fields: + - name: CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CACHE_CORE0_ACS_INT_MAP + description: register description + addressOffset: 168 + size: 32 + fields: + - name: CACHE_CORE0_ACS_INT_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: INTR_STATUS_REG_0 + description: register description + addressOffset: 172 + size: 32 + fields: + - name: INTR_STATUS_0 + description: Need add description + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INTR_STATUS_REG_1 + description: register description + addressOffset: 176 + size: 32 + fields: + - name: INTR_STATUS_1 + description: Need add description + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CLOCK_GATE + description: register description + addressOffset: 180 + size: 32 + resetValue: 1 + fields: + - name: REG_CLK_EN + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INT_ENABLE + description: register description + addressOffset: 184 + size: 32 + fields: + - name: CPU_INT_ENABLE + description: Need add description + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CPU_INT_TYPE + description: register description + addressOffset: 188 + size: 32 + fields: + - name: CPU_INT_TYPE + description: Need add description + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CPU_INT_CLEAR + description: register description + addressOffset: 192 + size: 32 + fields: + - name: CPU_INT_CLEAR + description: Need add description + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CPU_INT_EIP_STATUS + description: register description + addressOffset: 196 + size: 32 + fields: + - name: CPU_INT_EIP_STATUS + description: Need add description + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CPU_INT_PRI_0 + description: register description + addressOffset: 200 + size: 32 + fields: + - name: CPU_PRI_0_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_1 + description: register description + addressOffset: 204 + size: 32 + fields: + - name: CPU_PRI_1_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_2 + description: register description + addressOffset: 208 + size: 32 + fields: + - name: CPU_PRI_2_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_3 + description: register description + addressOffset: 212 + size: 32 + fields: + - name: CPU_PRI_3_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_4 + description: register description + addressOffset: 216 + size: 32 + fields: + - name: CPU_PRI_4_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_5 + description: register description + addressOffset: 220 + size: 32 + fields: + - name: CPU_PRI_5_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_6 + description: register description + addressOffset: 224 + size: 32 + fields: + - name: CPU_PRI_6_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_7 + description: register description + addressOffset: 228 + size: 32 + fields: + - name: CPU_PRI_7_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_8 + description: register description + addressOffset: 232 + size: 32 + fields: + - name: CPU_PRI_8_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_9 + description: register description + addressOffset: 236 + size: 32 + fields: + - name: CPU_PRI_9_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_10 + description: register description + addressOffset: 240 + size: 32 + fields: + - name: CPU_PRI_10_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_11 + description: register description + addressOffset: 244 + size: 32 + fields: + - name: CPU_PRI_11_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_12 + description: register description + addressOffset: 248 + size: 32 + fields: + - name: CPU_PRI_12_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_13 + description: register description + addressOffset: 252 + size: 32 + fields: + - name: CPU_PRI_13_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_14 + description: register description + addressOffset: 256 + size: 32 + fields: + - name: CPU_PRI_14_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_15 + description: register description + addressOffset: 260 + size: 32 + fields: + - name: CPU_PRI_15_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_16 + description: register description + addressOffset: 264 + size: 32 + fields: + - name: CPU_PRI_16_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_17 + description: register description + addressOffset: 268 + size: 32 + fields: + - name: CPU_PRI_17_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_18 + description: register description + addressOffset: 272 + size: 32 + fields: + - name: CPU_PRI_18_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_19 + description: register description + addressOffset: 276 + size: 32 + fields: + - name: CPU_PRI_19_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_20 + description: register description + addressOffset: 280 + size: 32 + fields: + - name: CPU_PRI_20_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_21 + description: register description + addressOffset: 284 + size: 32 + fields: + - name: CPU_PRI_21_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_22 + description: register description + addressOffset: 288 + size: 32 + fields: + - name: CPU_PRI_22_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_23 + description: register description + addressOffset: 292 + size: 32 + fields: + - name: CPU_PRI_23_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_24 + description: register description + addressOffset: 296 + size: 32 + fields: + - name: CPU_PRI_24_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_25 + description: register description + addressOffset: 300 + size: 32 + fields: + - name: CPU_PRI_25_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_26 + description: register description + addressOffset: 304 + size: 32 + fields: + - name: CPU_PRI_26_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_27 + description: register description + addressOffset: 308 + size: 32 + fields: + - name: CPU_PRI_27_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_28 + description: register description + addressOffset: 312 + size: 32 + fields: + - name: CPU_PRI_28_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_29 + description: register description + addressOffset: 316 + size: 32 + fields: + - name: CPU_PRI_29_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_30 + description: register description + addressOffset: 320 + size: 32 + fields: + - name: CPU_PRI_30_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_31 + description: register description + addressOffset: 324 + size: 32 + fields: + - name: CPU_PRI_31_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_THRESH + description: register description + addressOffset: 328 + size: 32 + fields: + - name: CPU_INT_THRESH + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: INTERRUPT_REG_DATE + description: register description + addressOffset: 2044 + size: 32 + resetValue: 34636176 + fields: + - name: INTERRUPT_REG_DATE + description: Need add description + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: IO_MUX + description: Input/Output Multiplexer + groupName: IO_MUX + baseAddress: 1610649600 + addressBlock: + - offset: 0 + size: 92 + usage: registers + registers: + - register: + name: PIN_CTRL + description: Clock Output Configuration Register + addressOffset: 0 + size: 32 + resetValue: 2047 + fields: + - name: CLK_OUT1 + description: "If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: CLK_OUT2 + description: "If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: CLK_OUT3 + description: "If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals." + bitOffset: 8 + bitWidth: 4 + access: read-write + - register: + dim: 21 + dimIncrement: 4 + name: GPIO%s + description: IO MUX Configure Register for pad XTAL_32K_P + addressOffset: 4 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: IO MUX Version Control Register + addressOffset: 252 + size: 32 + resetValue: 34627984 + fields: + - name: REG_DATE + description: Version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: LEDC + description: LED Control PWM (Pulse Width Modulation) + groupName: LEDC + baseAddress: 1610715136 + addressBlock: + - offset: 0 + size: 176 + usage: registers + interrupt: + - name: LEDC + value: 19 + registers: + - register: + dim: 6 + dimIncrement: 20 + name: CH%s_CONF0 + description: Configuration register 0 for channel %s + addressOffset: 0 + size: 32 + fields: + - name: TIMER_SEL + description: "This field is used to select one of timers for channel %s.\n\n0: select timer0; 1: select timer1; 2: select timer2; 3: select timer3" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SIG_OUT_EN + description: Set this bit to enable signal output on channel %s. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IDLE_LV + description: This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0). + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PARA_UP + description: "This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware." + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: OVF_NUM + description: "This register is used to configure the maximum times of overflow minus 1.\n\nThe LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times." + bitOffset: 5 + bitWidth: 10 + access: read-write + - name: OVF_CNT_EN + description: This bit is used to enable the ovf_cnt of channel %s. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: OVF_CNT_RESET + description: Set this bit to reset the ovf_cnt of channel %s. + bitOffset: 16 + bitWidth: 1 + access: write-only + - register: + dim: 6 + dimIncrement: 20 + name: CH%s_HPOINT + description: High point register for channel %s + addressOffset: 4 + size: 32 + fields: + - name: HPOINT + description: The output value changes to high when the selected timers has reached the value specified by this register. + bitOffset: 0 + bitWidth: 14 + access: read-write + - register: + dim: 6 + dimIncrement: 20 + name: CH%s_DUTY + description: Initial duty cycle for channel %s + addressOffset: 8 + size: 32 + fields: + - name: DUTY + description: "This register is used to change the output duty by controlling the Lpoint.\n\nThe output value turns to low when the selected timers has reached the Lpoint." + bitOffset: 0 + bitWidth: 19 + access: read-write + - register: + dim: 6 + dimIncrement: 20 + name: CH%s_CONF1 + description: Configuration register 1 for channel %s + addressOffset: 12 + size: 32 + resetValue: 1073741824 + fields: + - name: DUTY_SCALE + description: This register is used to configure the changing step scale of duty on channel %s. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: DUTY_CYCLE + description: The duty will change every LEDC_DUTY_CYCLE_CH%s on channel %s. + bitOffset: 10 + bitWidth: 10 + access: read-write + - name: DUTY_NUM + description: This register is used to control the number of times the duty cycle will be changed. + bitOffset: 20 + bitWidth: 10 + access: read-write + - name: DUTY_INC + description: "This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase; 0: Decrease." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DUTY_START + description: Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + dim: 6 + dimIncrement: 20 + name: CH%s_DUTY_R + description: Current duty cycle for channel %s + addressOffset: 16 + size: 32 + fields: + - name: DUTY_CH0_R + description: This register stores the current duty of output signal on channel %s. + bitOffset: 0 + bitWidth: 19 + access: read-only + - register: + dim: 4 + dimIncrement: 8 + name: TIMER%s_CONF + description: Timer %s configuration + addressOffset: 160 + size: 32 + resetValue: 8388608 + fields: + - name: DUTY_RES + description: This register is used to control the range of the counter in timer %s. + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: CLK_DIV + description: "This register is used to configure the divisor for the divider in timer %s.\n\nThe least significant eight bits represent the fractional part." + bitOffset: 4 + bitWidth: 18 + access: read-write + - name: PAUSE + description: This bit is used to suspend the counter in timer %s. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RST + description: This bit is used to reset timer %s. The counter will show 0 after reset. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TICK_SEL + description: "This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate.\n\n1'h0: SLOW_CLK 1'h1: REF_TICK" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PARA_UP + description: Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES. + bitOffset: 25 + bitWidth: 1 + access: write-only + - register: + dim: 4 + dimIncrement: 8 + name: TIMER%s_VALUE + description: Timer %s current counter value + addressOffset: 164 + size: 32 + fields: + - name: CNT + description: This register stores the current counter value of timer %s. + bitOffset: 0 + bitWidth: 14 + access: read-only + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 192 + size: 32 + fields: + - name: OVF_INT_RAW + description: Triggered when the timer0 has reached its maximum counter value. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMER1_OVF_INT_RAW + description: Triggered when the timer1 has reached its maximum counter value. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER2_OVF_INT_RAW + description: Triggered when the timer2 has reached its maximum counter value. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TIMER3_OVF_INT_RAW + description: Triggered when the timer3 has reached its maximum counter value. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH0_INT_RAW + description: Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH1_INT_RAW + description: Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH2_INT_RAW + description: Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH3_INT_RAW + description: Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH4_INT_RAW + description: Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH5_INT_RAW + description: Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH0_INT_RAW + description: Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH1_INT_RAW + description: Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH2_INT_RAW + description: Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH3_INT_RAW + description: Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH4_INT_RAW + description: Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH5_INT_RAW + description: Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 196 + size: 32 + fields: + - name: OVF_INT_ST + description: This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TIMER1_OVF_INT_ST + description: This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TIMER2_OVF_INT_ST + description: This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TIMER3_OVF_INT_ST + description: This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH0_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENAIS set to 1. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH1_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENAIS set to 1. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH2_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENAIS set to 1. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH3_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENAIS set to 1. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH4_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENAIS set to 1. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH5_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENAIS set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH0_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH1_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH2_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH3_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH4_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH5_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + bitOffset: 15 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 200 + size: 32 + fields: + - name: OVF_INT_ENA + description: The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMER1_OVF_INT_ENA + description: The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER2_OVF_INT_ENA + description: The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TIMER3_OVF_INT_ENA + description: The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH0_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH1_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH2_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH3_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH4_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH5_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH0_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH1_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH2_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH3_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH4_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH5_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 204 + size: 32 + fields: + - name: OVF_INT_CLR + description: Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TIMER1_OVF_INT_CLR + description: Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TIMER2_OVF_INT_CLR + description: Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TIMER3_OVF_INT_CLR + description: Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH0_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH1_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH2_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH3_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH4_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH5_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH0_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH1_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH2_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH3_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH4_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH5_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - register: + name: CONF + description: Global ledc configuration register + addressOffset: 208 + size: 32 + fields: + - name: APB_CLK_SEL + description: "This bit is used to select clock source for the 4 timers .\n\n2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CLK_EN + description: "This bit is used to control clock.\n\n1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 252 + size: 32 + resetValue: 419829504 + fields: + - name: LEDC_DATE + description: This is the version control register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: MODEM_CLKRST + description: MODEM_CLKRST Peripheral + groupName: MODEM_CLKRST + baseAddress: 1610930176 + addressBlock: + - offset: 0 + size: 24 + usage: registers + registers: + - register: + name: CLK_CONF + addressOffset: 0 + size: 32 + fields: + - name: CLK_EN + description: "." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: MODEM_LP_TIMER_CONF + addressOffset: 4 + size: 32 + fields: + - name: LP_TIMER_SEL_RTC_SLOW + description: "." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LP_TIMER_SEL_8M + description: "." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: LP_TIMER_SEL_XTAL + description: "." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: LP_TIMER_SEL_XTAL32K + description: "." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: LP_TIMER_CLK_DIV_NUM + description: "." + bitOffset: 4 + bitWidth: 8 + access: read-write + - register: + name: COEX_LP_CLK_CONF + addressOffset: 8 + size: 32 + fields: + - name: COEX_LPCLK_SEL_RTC_SLOW + description: "." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: COEX_LPCLK_SEL_8M + description: "." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: COEX_LPCLK_SEL_XTAL + description: "." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: COEX_LPCLK_SEL_XTAL32K + description: "." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: COEX_LPCLK_DIV_NUM + description: "." + bitOffset: 4 + bitWidth: 8 + access: read-write + - register: + name: BLE_TIMER_CLK_CONF + addressOffset: 12 + size: 32 + resetValue: 3 + fields: + - name: BLETIMER_USE_XTAL + description: "." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: BLETIMER_CLK_IS_ACTIVE + description: "." + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: DATE + addressOffset: 12 + size: 32 + resetValue: 34632304 + fields: + - name: DATE + description: "." + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + name: ETM_CLK_CONF + addressOffset: 16 + size: 32 + fields: + - name: ETM_CLK_SEL + description: "." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_CLK_ACTIVE + description: "." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RNG + description: Hardware Random Number Generator + groupName: RNG + baseAddress: 1610768384 + addressBlock: + - offset: 0 + size: 4 + usage: registers + registers: + - register: + name: DATA + description: Random number data + addressOffset: 176 + size: 32 + access: read-only + - name: RTC_CNTL + description: Real-Time Clock Control + groupName: RTC_CNTL + baseAddress: 1610645504 + addressBlock: + - offset: 0 + size: 276 + usage: registers + interrupt: + - name: RTC_CORE + value: 21 + registers: + - register: + name: OPTIONS0 + description: register description + addressOffset: 0 + size: 32 + resetValue: 268476416 + fields: + - name: SW_STALL_PROCPU_C0 + description: "{reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: SW_PROCPU_RST + description: PRO CPU SW reset + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BB_I2C_FORCE_PD + description: BB_I2C force power down + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BB_I2C_FORCE_PU + description: BB_I2C force power up + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: BBPLL_I2C_FORCE_PD + description: BB_PLL _I2C force power down + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BBPLL_I2C_FORCE_PU + description: BB_PLL_I2C force power up + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: BBPLL_FORCE_PD + description: BB_PLL force power down + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: BBPLL_FORCE_PU + description: BB_PLL force power up + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: XTL_FORCE_PD + description: crystall force power down + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: XTL_FORCE_PU + description: crystall force power up + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: XTL_EN_WAIT + description: wait bias_sleep and current source wakeup + bitOffset: 14 + bitWidth: 4 + access: read-write + - name: XTL_EXT_CTR_SEL + description: Need add desc + bitOffset: 20 + bitWidth: 3 + access: read-write + - name: ANALOG_FORCE_ISO + description: Need add desc + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: ANALOG_FORCE_NOISO + description: Need add desc + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_RST + description: digital wrap force reset in deep sleep + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_NORST + description: digital core force no reset in deep sleep + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SW_SYS_RST + description: SW system reset + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SLP_TIMER0 + description: register description + addressOffset: 4 + size: 32 + fields: + - name: SLP_VAL_LO + description: Need add desc + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SLP_TIMER1 + description: register description + addressOffset: 8 + size: 32 + fields: + - name: SLP_VAL_HI + description: RTC sleep timer high 16 bits + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MAIN_TIMER_ALARM_EN + description: timer alarm enable bit + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: TIME_UPDATE + description: register description + addressOffset: 12 + size: 32 + fields: + - name: TIMER_SYS_STALL + description: Enable to record system stall time + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: TIMER_XTL_OFF + description: Enable to record 40M XTAL OFF time + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: TIMER_SYS_RST + description: enable to record system reset time + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TIME_UPDATE + description: "Set 1: to update register with RTC timer" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TIME_LOW0 + description: register description + addressOffset: 16 + size: 32 + fields: + - name: TIMER_VALUE0_LOW + description: RTC timer low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TIME_HIGH0 + description: register description + addressOffset: 20 + size: 32 + fields: + - name: TIMER_VALUE0_HIGH + description: RTC timer high 16 bits + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: STATE0 + description: register description + addressOffset: 24 + size: 32 + fields: + - name: SW_CPU_INT + description: rtc software interrupt to main cpu + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_REJECT_CAUSE_CLR + description: clear rtc sleep reject cause + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: APB2RTC_BRIDGE_SEL + description: "1: APB to RTC using bridge" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SDIO_ACTIVE_IND + description: SDIO active indication + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SLP_WAKEUP + description: leep wakeup bit + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SLP_REJECT + description: leep reject bit + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SLEEP_EN + description: sleep enable bit + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TIMER1 + description: register description + addressOffset: 28 + size: 32 + resetValue: 672400387 + fields: + - name: CPU_STALL_EN + description: CPU stall enable bit + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CPU_STALL_WAIT + description: CPU stall wait cycles in fast_clk_rtc + bitOffset: 1 + bitWidth: 5 + access: read-write + - name: CK8M_WAIT + description: CK8M wait cycles in slow_clk_rtc + bitOffset: 6 + bitWidth: 8 + access: read-write + - name: XTL_BUF_WAIT + description: XTAL wait cycles in slow_clk_rtc + bitOffset: 14 + bitWidth: 10 + access: read-write + - name: PLL_BUF_WAIT + description: PLL wait cycles in slow_clk_rtc + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: TIMER2 + description: register description + addressOffset: 32 + size: 32 + resetValue: 16777216 + fields: + - name: MIN_TIME_CK8M_OFF + description: minimal cycles in slow_clk_rtc for CK8M in power down state + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: TIMER4 + description: register description + addressOffset: 36 + size: 32 + resetValue: 270532608 + fields: + - name: DG_WRAP_WAIT_TIMER + description: Need add desc + bitOffset: 16 + bitWidth: 9 + access: read-write + - name: DG_WRAP_POWERUP_TIMER + description: Need add desc + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: TIMER5 + description: register description + addressOffset: 40 + size: 32 + resetValue: 32768 + fields: + - name: MIN_SLP_VAL + description: minimal sleep cycles in slow_clk_rtc + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: ANA_CONF + description: register description + addressOffset: 44 + size: 32 + resetValue: 4456448 + fields: + - name: I2C_RESET_POR_FORCE_PD + description: Need add desc + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: I2C_RESET_POR_FORCE_PU + description: Need add desc + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SAR_I2C_PU + description: PLLA force power up + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: BBPLL_CAL_SLP_START + description: start BBPLL calibration during sleep + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TXRF_I2C_PU + description: "1: TXRF_I2C power up" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RFRX_PBUS_PU + description: "1: RFRX_PBUS power up" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CKGEN_I2C_PU + description: "1: CKGEN_I2C power up" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: PLL_I2C_PU + description: Need add desc + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: PLLA_FORCE_PD + description: PLLA force power down + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: PLLA_FORCE_PU + description: PLLA force power up + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: RESET_STATE + description: register description + addressOffset: 48 + size: 32 + resetValue: 8192 + fields: + - name: RESET_CAUSE_PROCPU + description: reset cause of PRO CPU + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: STAT_VECTOR_SEL_PROCPU + description: PRO CPU state vector sel + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: OCD_HALT_ON_RESET_PROCPU + description: PROCPU OcdHaltOnReset + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: DRESET_MASK_PROCPU + description: Need add desc + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: WAKEUP_STATE + description: register description + addressOffset: 52 + size: 32 + resetValue: 393216 + fields: + - name: WAKEUP_ENA + description: wakeup enable bitmap + bitOffset: 15 + bitWidth: 17 + access: read-write + - register: + name: INT_ENA_RTC + description: register description + addressOffset: 56 + size: 32 + fields: + - name: SLP_WAKEUP_INT_ENA + description: enable sleep wakeup interrupt + bitOffset: 0 + bitWidth: 1 + - name: SLP_REJECT_INT_ENA + description: enable sleep reject interrupt + bitOffset: 1 + bitWidth: 1 + - name: WDT_INT_ENA + description: enable RTC WDT interrupt + bitOffset: 3 + bitWidth: 1 + - name: BROWN_OUT_INT_ENA + description: enable brown out interrupt + bitOffset: 9 + bitWidth: 1 + - name: MAIN_TIMER_INT_ENA + description: enable RTC main timer interrupt + bitOffset: 10 + bitWidth: 1 + - name: SWD_INT_ENA + description: enable super watch dog interrupt + bitOffset: 15 + bitWidth: 1 + - name: BBPLL_CAL_INT_ENA + description: Need add desc + bitOffset: 20 + bitWidth: 1 + - register: + name: INT_RAW_RTC + description: register description + addressOffset: 60 + size: 32 + fields: + - name: SLP_WAKEUP_INT_RAW + description: sleep wakeup interrupt raw + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_REJECT_INT_RAW + description: sleep reject interrupt raw + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: WDT_INT_RAW + description: RTC WDT interrupt raw + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_INT_RAW + description: brown out interrupt raw + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: MAIN_TIMER_INT_RAW + description: RTC main timer interrupt raw + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SWD_INT_RAW + description: super watch dog interrupt raw + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: BBPLL_CAL_INT_RAW + description: Need add desc + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: INT_ST_RTC + description: register description + addressOffset: 64 + size: 32 + fields: + - name: SLP_WAKEUP_INT_ST + description: sleep wakeup interrupt state + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_REJECT_INT_ST + description: sleep reject interrupt state + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: WDT_INT_ST + description: RTC WDT interrupt state + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_INT_ST + description: brown out interrupt state + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: MAIN_TIMER_INT_ST + description: RTC main timer interrupt state + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SWD_INT_ST + description: super watch dog interrupt state + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: BBPLL_CAL_INT_ST + description: Need add desc + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR_RTC + description: register description + addressOffset: 68 + size: 32 + fields: + - name: SLP_WAKEUP_INT_CLR + description: Clear sleep wakeup interrupt state + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_REJECT_INT_CLR + description: Clear sleep reject interrupt state + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: WDT_INT_CLR + description: Clear RTC WDT interrupt state + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_INT_CLR + description: Clear brown out interrupt state + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: MAIN_TIMER_INT_CLR + description: Clear RTC main timer interrupt state + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SWD_INT_CLR + description: Clear super watch dog interrupt state + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: BBPLL_CAL_INT_CLR + description: Need add desc + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: STORE0 + description: register description + addressOffset: 72 + size: 32 + fields: + - name: SCRATCH0 + description: Need add desc + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE1 + description: register description + addressOffset: 76 + size: 32 + fields: + - name: SCRATCH1 + description: Need add desc + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE2 + description: register description + addressOffset: 80 + size: 32 + fields: + - name: SCRATCH2 + description: Need add desc + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE3 + description: register description + addressOffset: 84 + size: 32 + fields: + - name: SCRATCH3 + description: Need add desc + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: EXT_XTL_CONF + description: register description + addressOffset: 88 + size: 32 + fields: + - name: XTL_EXT_CTR_LV + description: "0: power down XTAL at high level" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: XTL_EXT_CTR_EN + description: Need add desc + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EXT_WAKEUP_CONF + description: register description + addressOffset: 92 + size: 32 + fields: + - name: GPIO_WAKEUP_FILTER + description: enable filter for gpio wakeup event + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SLP_REJECT_CONF + description: register description + addressOffset: 96 + size: 32 + fields: + - name: SLEEP_REJECT_ENA + description: sleep reject enable + bitOffset: 12 + bitWidth: 18 + access: read-write + - name: LIGHT_SLP_REJECT_EN + description: enable reject for light sleep + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DEEP_SLP_REJECT_EN + description: enable reject for deep sleep + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CPU_PERIOD_CONF + description: register description + addressOffset: 100 + size: 32 + fields: + - name: CPUSEL_CONF + description: CPU sel option + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CPUPERIOD_SEL + description: Need add desc + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CLK_CONF + description: register description + addressOffset: 104 + size: 32 + resetValue: 290992664 + fields: + - name: EFUSE_CLK_FORCE_GATING + description: Need add desc + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EFUSE_CLK_FORCE_NOGATING + description: Need add desc + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CK8M_DIV_SEL_VLD + description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CK8M_DIV + description: "CK8M_D256_OUT divider. 00: div128" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: ENB_CK8M + description: disable CK8M and CK8M_D256_OUT + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: ENB_CK8M_DIV + description: "1: CK8M_D256_OUT is actually CK8M" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DIG_XTAL32K_EN + description: enable CK_XTAL_32K for digital core (no relationship with RTC core) + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DIG_CLK8M_D256_EN + description: enable CK8M_D256_OUT for digital core (no relationship with RTC core) + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DIG_CLK8M_EN + description: enable CK8M for digital core (no relationship with RTC core) + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CK8M_DIV_SEL + description: divider = reg_ck8m_div_sel + 1 + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: XTAL_FORCE_NOGATING + description: XTAL force no gating during sleep + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CK8M_FORCE_NOGATING + description: CK8M force no gating during sleep + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CK8M_DFREQ + description: CK8M_DFREQ + bitOffset: 17 + bitWidth: 8 + access: read-write + - name: CK8M_FORCE_PD + description: CK8M force power down + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: CK8M_FORCE_PU + description: CK8M force power up + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: XTAL_GLOBAL_FORCE_GATING + description: Need add desc + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: XTAL_GLOBAL_FORCE_NOGATING + description: Need add desc + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: FAST_CLK_RTC_SEL + description: "fast_clk_rtc sel. 0: XTAL div 4" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ANA_CLK_RTC_SEL + description: Need add desc + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: SLOW_CLK_CONF + description: register description + addressOffset: 108 + size: 32 + resetValue: 4194304 + fields: + - name: ANA_CLK_DIV_VLD + description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: ANA_CLK_DIV + description: Need add desc + bitOffset: 23 + bitWidth: 8 + access: read-write + - name: SLOW_CLK_NEXT_EDGE + description: Need add desc + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: BIAS_CONF + description: register description + addressOffset: 112 + size: 32 + resetValue: 67584 + fields: + - name: DG_VDD_DRV_B_SLP + description: Need add desc + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: DG_VDD_DRV_B_SLP_EN + description: Need add desc + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BIAS_BUF_IDLE + description: Need add desc + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: BIAS_BUF_WAKE + description: Need add desc + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: BIAS_BUF_DEEP_SLP + description: Need add desc + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: BIAS_BUF_MONITOR + description: Need add desc + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: PD_CUR_DEEP_SLP + description: xpd cur when rtc in sleep_state + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PD_CUR_MONITOR + description: xpd cur when rtc in monitor state + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: BIAS_SLEEP_DEEP_SLP + description: bias_sleep when rtc in sleep_state + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: BIAS_SLEEP_MONITOR + description: bias_sleep when rtc in monitor state + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: DBG_ATTEN_DEEP_SLP + description: DBG_ATTEN when rtc in sleep state + bitOffset: 18 + bitWidth: 4 + access: read-write + - name: DBG_ATTEN_MONITOR + description: DBG_ATTEN when rtc in active state + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: DBG_ATTEN_ACTIVE + description: Need add desc + bitOffset: 26 + bitWidth: 4 + access: read-write + - register: + name: RTC_CNTL + description: register description + addressOffset: 116 + size: 32 + resetValue: 2147483648 + fields: + - name: DIG_REG_CAL_EN + description: Need add desc + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SCK_DCAP + description: SCK_DCAP + bitOffset: 14 + bitWidth: 8 + access: read-write + - name: REGULATOR_FORCE_PD + description: RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower ) + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: REGULATOR_FORCE_PU + description: Need add desc + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: PWC + description: register description + addressOffset: 120 + size: 32 + fields: + - name: PAD_FORCE_HOLD + description: rtc pad force hold + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + name: DIG_PWC + description: register description + addressOffset: 124 + size: 32 + resetValue: 1048608 + fields: + - name: VDD_SPI_PWR_DRV + description: Need add desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: VDD_SPI_PWR_FORCE + description: Need add desc + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: VDD_SPI_PD_EN + description: Need add desc + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: LSLP_MEM_FORCE_PD + description: memories in digital core force PD in sleep + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: LSLP_MEM_FORCE_PU + description: memories in digital core force no PD in sleep + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_PD + description: digital core force power down + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_PU + description: digital core force power up + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: DG_WRAP_PD_EN + description: Need add desc + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DIG_ISO + description: register description + addressOffset: 128 + size: 32 + resetValue: 2147504256 + fields: + - name: FORCE_OFF + description: Need add desc + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FORCE_ON + description: Need add desc + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DG_PAD_AUTOHOLD + description: read only register to indicate digital pad auto-hold status + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CLR_DG_PAD_AUTOHOLD + description: wtite only register to clear digital pad auto-hold + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DG_PAD_AUTOHOLD_EN + description: digital pad enable auto-hold + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DG_PAD_FORCE_NOISO + description: digital pad force no ISO + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DG_PAD_FORCE_ISO + description: digital pad force ISO + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DG_PAD_FORCE_UNHOLD + description: digital pad force un-hold + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DG_PAD_FORCE_HOLD + description: digital pad force hold + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_ISO + description: digital core force ISO + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_NOISO + description: Need add desc + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: WDTCONFIG0 + description: register description + addressOffset: 132 + size: 32 + resetValue: 78356 + fields: + - name: WDT_CHIP_RESET_WIDTH + description: chip reset siginal pulse width + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: WDT_CHIP_RESET_EN + description: wdt reset whole chip enable + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: WDT_PAUSE_IN_SLP + description: pause WDT in sleep + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: WDT_PROCPU_RESET_EN + description: enable WDT reset PRO CPU + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: WDT_FLASHBOOT_MOD_EN + description: enable WDT in flash boot + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: WDT_SYS_RESET_LENGTH + description: system reset counter length + bitOffset: 13 + bitWidth: 3 + access: read-write + - name: WDT_CPU_RESET_LENGTH + description: CPU reset counter length + bitOffset: 16 + bitWidth: 3 + access: read-write + - name: WDT_STG3 + description: "1: interrupt stage en" + bitOffset: 19 + bitWidth: 3 + access: read-write + - name: WDT_STG2 + description: "1: interrupt stage en" + bitOffset: 22 + bitWidth: 3 + access: read-write + - name: WDT_STG1 + description: "1: interrupt stage en" + bitOffset: 25 + bitWidth: 3 + access: read-write + - name: WDT_STG0 + description: "1: interrupt stage en" + bitOffset: 28 + bitWidth: 3 + access: read-write + - name: WDT_EN + description: Need add desc + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: WDTCONFIG1 + description: register description + addressOffset: 136 + size: 32 + resetValue: 200000 + fields: + - name: WDT_STG0_HOLD + description: Need add desc + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG2 + description: register description + addressOffset: 140 + size: 32 + resetValue: 80000 + fields: + - name: WDT_STG1_HOLD + description: Need add desc + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG3 + description: register description + addressOffset: 144 + size: 32 + resetValue: 4095 + fields: + - name: WDT_STG2_HOLD + description: Need add desc + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG4 + description: register description + addressOffset: 148 + size: 32 + resetValue: 4095 + fields: + - name: WDT_STG3_HOLD + description: Need add desc + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTFEED + description: register description + addressOffset: 152 + size: 32 + fields: + - name: WDT_FEED + description: Need add desc + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: WDTWPROTECT + description: register description + addressOffset: 156 + size: 32 + fields: + - name: WDT_WKEY + description: Need add desc + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SWD_CONF + description: register description + addressOffset: 160 + size: 32 + resetValue: 78643200 + fields: + - name: SWD_RESET_FLAG + description: swd reset flag + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SWD_FEED_INT + description: swd interrupt for feeding + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SWD_BYPASS_RST + description: Need add desc + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SWD_SIGNAL_WIDTH + description: adjust signal width send to swd + bitOffset: 18 + bitWidth: 10 + access: read-write + - name: SWD_RST_FLAG_CLR + description: reset swd reset flag + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SWD_FEED + description: Sw feed swd + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SWD_DISABLE + description: disabel SWD + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SWD_AUTO_FEED_EN + description: automatically feed swd when int comes + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SWD_WPROTECT + description: register description + addressOffset: 164 + size: 32 + fields: + - name: SWD_WKEY + description: Need add desc + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SW_CPU_STALL + description: register description + addressOffset: 168 + size: 32 + fields: + - name: SW_STALL_PROCPU_C1 + description: Need add desc + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: STORE4 + description: register description + addressOffset: 172 + size: 32 + fields: + - name: SCRATCH4 + description: Need add desc + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE5 + description: register description + addressOffset: 176 + size: 32 + fields: + - name: SCRATCH5 + description: Need add desc + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE6 + description: register description + addressOffset: 180 + size: 32 + fields: + - name: SCRATCH6 + description: Need add desc + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE7 + description: register description + addressOffset: 184 + size: 32 + fields: + - name: SCRATCH7 + description: Need add desc + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOW_POWER_ST + description: register description + addressOffset: 188 + size: 32 + fields: + - name: XPD_DIG + description: digital wrap power down + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TOUCH_STATE_START + description: touch should start to work + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TOUCH_STATE_SWITCH + description: touch is about to working. Switch rtc main state + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TOUCH_STATE_SLP + description: touch is in sleep state + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TOUCH_STATE_DONE + description: touch is done + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: COCPU_STATE_START + description: ulp/cocpu should start to work + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: COCPU_STATE_SWITCH + description: ulp/cocpu is about to working. Switch rtc main state + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: COCPU_STATE_SLP + description: ulp/cocpu is in sleep state + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: COCPU_STATE_DONE + description: ulp/cocpu is done + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: MAIN_STATE_XTAL_ISO + description: no use any more + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MAIN_STATE_PLL_ON + description: rtc main state machine is in states that pll should be running + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RDY_FOR_WAKEUP + description: rtc is ready to receive wake up trigger from wake up source + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: MAIN_STATE_WAIT_END + description: rtc main state machine has been waited for some cycles + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: IN_WAKEUP_STATE + description: rtc main state machine is in the states of wakeup process + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: IN_LOW_POWER_STATE + description: rtc main state machine is in the states of low power + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: MAIN_STATE_IN_WAIT_8M + description: rtc main state machine is in wait 8m state + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: MAIN_STATE_IN_WAIT_PLL + description: rtc main state machine is in wait pll state + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: MAIN_STATE_IN_WAIT_XTL + description: rtc main state machine is in wait xtal state + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: MAIN_STATE_IN_SLP + description: rtc main state machine is in sleep state + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: MAIN_STATE_IN_IDLE + description: rtc main state machine is in idle state + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: MAIN_STATE + description: rtc main state machine status + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: DIAG0 + description: register description + addressOffset: 192 + size: 32 + fields: + - name: LOW_POWER_DIAG1 + description: Need add desc + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PAD_HOLD + description: register description + addressOffset: 196 + size: 32 + fields: + - name: GPIO_PIN0_HOLD + description: Need add desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: GPIO_PIN1_HOLD + description: Need add desc + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: GPIO_PIN2_HOLD + description: Need add desc + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: GPIO_PIN3_HOLD + description: Need add desc + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: GPIO_PIN4_HOLD + description: Need add desc + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: GPIO_PIN5_HOLD + description: Need add desc + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: DIG_PAD_HOLD + description: register description + addressOffset: 200 + size: 32 + fields: + - name: DIG_PAD_HOLD + description: Need add desc + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BROWN_OUT + description: register description + addressOffset: 204 + size: 32 + resetValue: 1140785168 + fields: + - name: BROWN_OUT_INT_WAIT + description: brown out interrupt wait cycles + bitOffset: 4 + bitWidth: 10 + access: read-write + - name: BROWN_OUT_CLOSE_FLASH_ENA + description: enable close flash when brown out happens + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_PD_RF_ENA + description: enable power down RF when brown out happens + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_RST_WAIT + description: brown out reset wait cycles + bitOffset: 16 + bitWidth: 10 + access: read-write + - name: BROWN_OUT_RST_ENA + description: enable brown out reset + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_RST_SEL + description: "1: 4-pos reset" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_ANA_RST_EN + description: Need add desc + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_CNT_CLR + description: clear brown out counter + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_ENA + description: enable brown out + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DET + description: Need add desc + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TIME_LOW1 + description: register description + addressOffset: 208 + size: 32 + fields: + - name: TIMER_VALUE1_LOW + description: RTC timer low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TIME_HIGH1 + description: register description + addressOffset: 212 + size: 32 + fields: + - name: TIMER_VALUE1_HIGH + description: RTC timer high 16 bits + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: USB_CONF + description: register description + addressOffset: 216 + size: 32 + fields: + - name: IO_MUX_RESET_DISABLE + description: Need add desc + bitOffset: 18 + bitWidth: 1 + access: read-write + - register: + name: SLP_REJECT_CAUSE + description: register description + addressOffset: 220 + size: 32 + fields: + - name: REJECT_CAUSE + description: sleep reject cause + bitOffset: 0 + bitWidth: 18 + access: read-write + - register: + name: OPTION1 + description: register description + addressOffset: 224 + size: 32 + fields: + - name: FORCE_DOWNLOAD_BOOT + description: Need add desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SLP_WAKEUP_CAUSE + description: register description + addressOffset: 228 + size: 32 + fields: + - name: WAKEUP_CAUSE + description: sleep wakeup cause + bitOffset: 0 + bitWidth: 17 + access: read-write + - register: + name: ULP_CP_TIMER_1 + description: register description + addressOffset: 232 + size: 32 + resetValue: 51200 + fields: + - name: ULP_CP_TIMER_SLP_CYCLE + description: sleep cycles for ULP-coprocessor timer + bitOffset: 8 + bitWidth: 24 + access: read-write + - register: + name: INT_ENA_RTC_W1TS + description: register description + addressOffset: 236 + size: 32 + fields: + - name: SLP_WAKEUP_INT_ENA_W1TS + description: enable sleep wakeup interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_REJECT_INT_ENA_W1TS + description: enable sleep reject interrupt + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: WDT_INT_ENA_W1TS + description: enable RTC WDT interrupt + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_INT_ENA_W1TS + description: enable brown out interrupt + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: MAIN_TIMER_INT_ENA_W1TS + description: enable RTC main timer interrupt + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SWD_INT_ENA_W1TS + description: enable super watch dog interrupt + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: BBPLL_CAL_INT_ENA_W1TS + description: Need add desc + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: INT_ENA_RTC_W1TC + description: register description + addressOffset: 240 + size: 32 + fields: + - name: SLP_WAKEUP_INT_ENA_W1TC + description: enable sleep wakeup interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_REJECT_INT_ENA_W1TC + description: enable sleep reject interrupt + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: WDT_INT_ENA_W1TC + description: enable RTC WDT interrupt + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_INT_ENA_W1TC + description: enable brown out interrupt + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: MAIN_TIMER_INT_ENA_W1TC + description: enable RTC main timer interrupt + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SWD_INT_ENA_W1TC + description: enable super watch dog interrupt + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: BBPLL_CAL_INT_ENA_W1TC + description: Need add desc + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: CNTL_RETENTION_CTRL + description: register description + addressOffset: 244 + size: 32 + resetValue: 2697986048 + fields: + - name: RETENTION_CLK_SEL + description: Need add desc + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RETENTION_DONE_WAIT + description: Need add desc + bitOffset: 19 + bitWidth: 3 + access: read-write + - name: RETENTION_CLKOFF_WAIT + description: Need add desc + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: RETENTION_EN + description: Need add desc + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RETENTION_WAIT + description: wait cycles for rention operation + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: FIB_SEL + description: register description + addressOffset: 248 + size: 32 + resetValue: 7 + fields: + - name: FIB_SEL + description: select use analog fib signal + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: CNTL_GPIO_WAKEUP + description: register description + addressOffset: 252 + size: 32 + fields: + - name: GPIO_WAKEUP_STATUS + description: Need add desc + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: GPIO_WAKEUP_STATUS_CLR + description: Need add desc + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: GPIO_PIN_CLK_GATE + description: Need add desc + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: GPIO_PIN5_INT_TYPE + description: Need add desc + bitOffset: 8 + bitWidth: 3 + access: read-write + - name: GPIO_PIN4_INT_TYPE + description: Need add desc + bitOffset: 11 + bitWidth: 3 + access: read-write + - name: GPIO_PIN3_INT_TYPE + description: Need add desc + bitOffset: 14 + bitWidth: 3 + access: read-write + - name: GPIO_PIN2_INT_TYPE + description: Need add desc + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: GPIO_PIN1_INT_TYPE + description: Need add desc + bitOffset: 20 + bitWidth: 3 + access: read-write + - name: GPIO_PIN0_INT_TYPE + description: Need add desc + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: GPIO_PIN5_WAKEUP_ENABLE + description: Need add desc + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: GPIO_PIN4_WAKEUP_ENABLE + description: Need add desc + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: GPIO_PIN3_WAKEUP_ENABLE + description: Need add desc + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: GPIO_PIN2_WAKEUP_ENABLE + description: Need add desc + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: GPIO_PIN1_WAKEUP_ENABLE + description: Need add desc + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: GPIO_PIN0_WAKEUP_ENABLE + description: Need add desc + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CNTL_DBG_SEL + description: register description + addressOffset: 256 + size: 32 + fields: + - name: DEBUG_12M_NO_GATING + description: Need add desc + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DEBUG_BIT_SEL + description: Need add desc + bitOffset: 2 + bitWidth: 5 + access: read-write + - name: DEBUG_SEL0 + description: Need add desc + bitOffset: 7 + bitWidth: 5 + access: read-write + - name: DEBUG_SEL1 + description: Need add desc + bitOffset: 12 + bitWidth: 5 + access: read-write + - name: DEBUG_SEL2 + description: Need add desc + bitOffset: 17 + bitWidth: 5 + access: read-write + - name: DEBUG_SEL3 + description: Need add desc + bitOffset: 22 + bitWidth: 5 + access: read-write + - name: DEBUG_SEL4 + description: Need add desc + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: CNTL_DBG_MAP + description: register description + addressOffset: 260 + size: 32 + fields: + - name: GPIO_PIN5_MUX_SEL + description: Need add desc + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: GPIO_PIN4_MUX_SEL + description: Need add desc + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: GPIO_PIN3_MUX_SEL + description: Need add desc + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: GPIO_PIN2_MUX_SEL + description: Need add desc + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: GPIO_PIN1_MUX_SEL + description: Need add desc + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: GPIO_PIN0_MUX_SEL + description: Need add desc + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: GPIO_PIN5_FUN_SEL + description: Need add desc + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: GPIO_PIN4_FUN_SEL + description: Need add desc + bitOffset: 12 + bitWidth: 4 + access: read-write + - name: GPIO_PIN3_FUN_SEL + description: Need add desc + bitOffset: 16 + bitWidth: 4 + access: read-write + - name: GPIO_PIN2_FUN_SEL + description: Need add desc + bitOffset: 20 + bitWidth: 4 + access: read-write + - name: GPIO_PIN1_FUN_SEL + description: Need add desc + bitOffset: 24 + bitWidth: 4 + access: read-write + - name: GPIO_PIN0_FUN_SEL + description: Need add desc + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: CNTL_SENSOR_CTRL + description: register description + addressOffset: 264 + size: 32 + fields: + - name: SAR2_PWDET_CCT + description: Need add desc + bitOffset: 27 + bitWidth: 3 + access: read-write + - name: FORCE_XPD_SAR + description: Need add desc + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CNTL_DBG_SAR_SEL + description: register description + addressOffset: 268 + size: 32 + fields: + - name: SAR_DEBUG_SEL + description: Need add desc + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: CNTL_DATE + description: register description + addressOffset: 508 + size: 32 + resetValue: 34632080 + fields: + - name: CNTL_DATE + description: Need add desc + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SENSITIVE + description: SENSITIVE Peripheral + groupName: SENSITIVE + baseAddress: 1611403264 + addressBlock: + - offset: 0 + size: 72 + usage: registers + registers: + - register: + name: ROM_TABLE_LOCK + description: register description + addressOffset: 0 + size: 32 + fields: + - name: ROM_TABLE_LOCK + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: ROM_TABLE + description: register description + addressOffset: 4 + size: 32 + fields: + - name: ROM_TABLE + description: Need add description + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: APB_PERIPHERAL_ACCESS_0 + description: register description + addressOffset: 8 + size: 32 + fields: + - name: APB_PERIPHERAL_ACCESS_LOCK + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: APB_PERIPHERAL_ACCESS_1 + description: register description + addressOffset: 12 + size: 32 + resetValue: 1 + fields: + - name: APB_PERIPHERAL_ACCESS_SPLIT_BURST + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: INTERNAL_SRAM_USAGE_0 + description: register description + addressOffset: 16 + size: 32 + fields: + - name: INTERNAL_SRAM_USAGE_LOCK + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: INTERNAL_SRAM_USAGE_1 + description: register description + addressOffset: 20 + size: 32 + resetValue: 15 + fields: + - name: INTERNAL_SRAM_USAGE_CPU_CACHE + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: INTERNAL_SRAM_USAGE_CPU_SRAM + description: Need add description + bitOffset: 1 + bitWidth: 3 + access: read-write + - register: + name: INTERNAL_SRAM_USAGE_3 + description: register description + addressOffset: 24 + size: 32 + fields: + - name: INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM + description: Need add description + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: INTERNAL_SRAM_ALLOC_MAC_DUMP + description: Need add description + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: CACHE_TAG_ACCESS_0 + description: register description + addressOffset: 28 + size: 32 + fields: + - name: CACHE_TAG_ACCESS_LOCK + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CACHE_TAG_ACCESS_1 + description: register description + addressOffset: 32 + size: 32 + resetValue: 15 + fields: + - name: PRO_I_TAG_RD_ACS + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_I_TAG_WR_ACS + description: Need add description + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PRO_D_TAG_RD_ACS + description: Need add description + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PRO_D_TAG_WR_ACS + description: Need add description + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: CACHE_MMU_ACCESS_0 + description: register description + addressOffset: 36 + size: 32 + fields: + - name: CACHE_MMU_ACCESS_LOCK + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CACHE_MMU_ACCESS_1 + description: register description + addressOffset: 40 + size: 32 + resetValue: 3 + fields: + - name: PRO_MMU_RD_ACS + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_MMU_WR_ACS + description: Need add description + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: PIF_ACCESS_MONITOR_0 + description: register description + addressOffset: 44 + size: 32 + fields: + - name: PIF_ACCESS_MONITOR_LOCK + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: PIF_ACCESS_MONITOR_1 + description: register description + addressOffset: 48 + size: 32 + resetValue: 3 + fields: + - name: PIF_ACCESS_MONITOR_NONWORD_VIOLATE_CLR + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PIF_ACCESS_MONITOR_NONWORD_VIOLATE_EN + description: Need add description + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: PIF_ACCESS_MONITOR_2 + description: register description + addressOffset: 52 + size: 32 + fields: + - name: PIF_ACCESS_MONITOR_NONWORD_VIOLATE_INTR + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE + description: Need add description + bitOffset: 1 + bitWidth: 2 + access: read-only + - register: + name: PIF_ACCESS_MONITOR_3 + description: register description + addressOffset: 56 + size: 32 + fields: + - name: PIF_ACCESS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR + description: Need add description + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: XTS_AES_KEY_UPDATE + description: register description + addressOffset: 60 + size: 32 + fields: + - name: XTS_AES_KEY_UPDATE + description: Set this bit to update xts_aes key + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CLOCK_GATE + description: register description + addressOffset: 64 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SENSITIVE_REG_DATE + description: register description + addressOffset: 4092 + size: 32 + resetValue: 34628353 + fields: + - name: SENSITIVE_REG_DATE + description: Need add description + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SHA + description: SHA (Secure Hash Algorithm) Accelerator + groupName: SHA + baseAddress: 1610854400 + addressBlock: + - offset: 0 + size: 176 + usage: registers + interrupt: + - name: SHA + value: 34 + registers: + - register: + name: MODE + description: Initial configuration register. + addressOffset: 0 + size: 32 + fields: + - name: MODE + description: Sha mode. + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: T_STRING + description: SHA 512/t configuration register 0. + addressOffset: 4 + size: 32 + fields: + - name: T_STRING + description: Sha t_string (used if and only if mode == SHA_512/t). + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: T_LENGTH + description: SHA 512/t configuration register 1. + addressOffset: 8 + size: 32 + fields: + - name: T_LENGTH + description: Sha t_length (used if and only if mode == SHA_512/t). + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: DMA_BLOCK_NUM + description: DMA configuration register 0. + addressOffset: 12 + size: 32 + fields: + - name: DMA_BLOCK_NUM + description: Dma-sha block number. + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: START + description: Typical SHA configuration register 0. + addressOffset: 16 + size: 32 + fields: + - name: START + description: Reserved. + bitOffset: 1 + bitWidth: 31 + access: write-only + - register: + name: CONTINUE + description: Typical SHA configuration register 1. + addressOffset: 20 + size: 32 + fields: + - name: CONTINUE + description: Reserved. + bitOffset: 1 + bitWidth: 31 + access: write-only + - register: + name: BUSY + description: Busy register. + addressOffset: 24 + size: 32 + fields: + - name: STATE + description: "Sha busy state. 1'b0: idle. 1'b1: busy." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: DMA_START + description: DMA configuration register 1. + addressOffset: 28 + size: 32 + fields: + - name: DMA_START + description: Start dma-sha. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: DMA_CONTINUE + description: DMA configuration register 2. + addressOffset: 32 + size: 32 + fields: + - name: DMA_CONTINUE + description: Continue dma-sha. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: CLEAR_IRQ + description: Interrupt clear register. + addressOffset: 36 + size: 32 + fields: + - name: CLEAR_INTERRUPT + description: Clear sha interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: IRQ_ENA + description: Interrupt enable register. + addressOffset: 40 + size: 32 + fields: + - name: INTERRUPT_ENA + description: "Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Date register. + addressOffset: 44 + size: 32 + resetValue: 538969622 + fields: + - name: DATE + description: Sha date information/ sha version information. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + name: "H_MEM[%s]" + description: Sha H memory which contains intermediate hash or finial hash. + addressOffset: 64 + size: 32 + - register: + dim: 16 + dimIncrement: 4 + name: "M_MEM[%s]" + description: Sha M memory which contains message. + addressOffset: 128 + size: 32 + - name: SPI0 + description: SPI (Serial Peripheral Interface) Controller 0 + groupName: SPI0 + baseAddress: 1610625024 + addressBlock: + - offset: 0 + size: 72 + usage: registers + interrupt: + - name: SPI_MEM_REJECT_CACHE + value: 29 + registers: + - register: + name: CTRL + description: SPI0 control register. + addressOffset: 8 + size: 32 + resetValue: 2891776 + fields: + - name: FDUMMY_OUT + description: In the dummy phase the signal level of spi is output by the spi controller. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FCMD_DUAL + description: "Apply 2 signals during command phase 1:enable 0: disable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FCMD_QUAD + description: "Apply 4 signals during command phase 1:enable 0: disable" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FASTRD_MODE + description: "This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT AND SPI_MEM_FREAD_DOUT. 1: enable 0: disable." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FREAD_DUAL + description: "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: Q_POL + description: "The bit is used to set MISO line polarity, 1: high 0, low" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: D_POL + description: "The bit is used to set MOSI line polarity, 1: high 0, low" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: FREAD_QUAD + description: "In the read operations read-data phase apply 4 signals. 1: enable 0: disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: WP + description: "Write protect signal output when SPI is idle. 1: output high, 0: output low." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: FREAD_DIO + description: "In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: FREAD_QIO + description: "In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: CTRL1 + description: SPI0 control1 register. + addressOffset: 12 + size: 32 + fields: + - name: CLK_MODE + description: "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: RXFIFO_RST + description: SPI0 RX FIFO reset signal. + bitOffset: 30 + bitWidth: 1 + access: write-only + - register: + name: CTRL2 + description: SPI0 control2 register. + addressOffset: 16 + size: 32 + resetValue: 33 + fields: + - name: CS_SETUP_TIME + description: (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit. + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: CS_HOLD_TIME + description: Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit. + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: CS_HOLD_DELAY + description: "These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles." + bitOffset: 25 + bitWidth: 6 + access: read-write + - name: SYNC_RESET + description: The FSM will be reset. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: CLOCK + description: SPI clock division control register. + addressOffset: 20 + size: 32 + resetValue: 196867 + fields: + - name: CLKCNT_L + description: In the master mode it must be equal to spi_mem_clkcnt_N. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CLKCNT_H + description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: CLKCNT_N + description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: CLK_EQU_SYSCLK + description: Set this bit in 1-division mode. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USER + description: SPI0 user register. + addressOffset: 24 + size: 32 + fields: + - name: CS_HOLD + description: "spi cs keep low when spi is in done phase. 1: enable 0: disable." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CS_SETUP + description: "spi cs is enable when spi is in prepare phase. 1: enable 0: disable." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CK_OUT_EDGE + description: the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: USR_DUMMY_IDLE + description: spi clock is disable in dummy phase when the bit is enable. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: USR_DUMMY + description: This bit enable the dummy phase of an operation. + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: USER1 + description: SPI0 user1 register. + addressOffset: 28 + size: 32 + resetValue: 1543503879 + fields: + - name: USR_DUMMY_CYCLELEN + description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: USR_ADDR_BITLEN + description: The length in bits of address phase. The register value shall be (bit_num-1). + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: USER2 + description: SPI0 user2 register. + addressOffset: 32 + size: 32 + resetValue: 1879048192 + fields: + - name: USR_COMMAND_VALUE + description: The value of command. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: USR_COMMAND_BITLEN + description: The length in bits of command phase. The register value shall be (bit_num-1) + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: RD_STATUS + description: SPI0 read control register. + addressOffset: 44 + size: 32 + fields: + - name: WB_MODE + description: Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: MISC + description: SPI0 misc register + addressOffset: 52 + size: 32 + fields: + - name: TRANS_END + description: The bit is used to indicate the spi0_mst_st controlled transmitting is done. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TRANS_END_INT_ENA + description: The bit is used to enable the interrupt of spi0_mst_st controlled transmitting is done. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CSPI_ST_TRANS_END + description: The bit is used to indicate the spi0_slv_st controlled transmitting is done. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CSPI_ST_TRANS_END_INT_ENA + description: The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CK_IDLE_EDGE + description: "1: spi clk line is high when idle 0: spi clk line is low when idle" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CS_KEEP_ACTIVE + description: spi cs line keep low when the bit is set. + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: CACHE_FCTRL + description: SPI0 bit mode control register. + addressOffset: 60 + size: 32 + fields: + - name: CACHE_REQ_EN + description: "For SPI0, Cache access enable, 1: enable, 0:disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CACHE_USR_ADDR_4BYTE + description: "For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CACHE_FLASH_USR_CMD + description: "For SPI0, cache read flash for user define command, 1: enable, 0:disable." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FDIN_DUAL + description: "For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FDOUT_DUAL + description: "For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FADDR_DUAL + description: "For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FDIN_QUAD + description: "For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FDOUT_QUAD + description: "For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FADDR_QUAD + description: "For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: FSM + description: SPI0 FSM status register + addressOffset: 84 + size: 32 + resetValue: 512 + fields: + - name: CSPI_ST + description: "The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state." + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: EM_ST + description: "The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state." + bitOffset: 4 + bitWidth: 3 + access: read-only + - name: CSPI_LOCK_DELAY_TIME + description: "The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1." + bitOffset: 7 + bitWidth: 5 + access: read-write + - register: + name: TIMING_CALI + description: SPI0 timing calibration register + addressOffset: 168 + size: 32 + fields: + - name: TIMING_CLK_ENA + description: The bit is used to enable timing adjust clock for all reading operations. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TIMING_CALI + description: The bit is used to enable timing auto-calibration for all reading operations. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: EXTRA_DUMMY_CYCLELEN + description: add extra dummy spi clock cycle length for spi clock calibration. + bitOffset: 2 + bitWidth: 3 + access: read-only + - register: + name: DIN_MODE + description: SPI0 input delay mode control register + addressOffset: 172 + size: 32 + fields: + - name: DIN0_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: DIN1_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 2 + bitWidth: 2 + access: read-only + - name: DIN2_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 4 + bitWidth: 2 + access: read-only + - name: DIN3_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 6 + bitWidth: 2 + access: read-only + - register: + name: DIN_NUM + description: SPI0 input delay number control register + addressOffset: 176 + size: 32 + fields: + - name: DIN0_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DIN1_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: DIN2_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: DIN3_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: DOUT_MODE + description: SPI0 output delay mode control register + addressOffset: 180 + size: 32 + fields: + - name: DOUT0_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DOUT1_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: DOUT2_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: DOUT3_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: CLOCK_GATE + description: SPI0 clk_gate register + addressOffset: 220 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: "Register clock gate enable signal. 1: Enable. 0: Disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_CLK_SEL + description: SPI0 module clock select register + addressOffset: 224 + size: 32 + fields: + - name: SPI01_CLK_SEL + description: "When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used." + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 1020 + size: 32 + resetValue: 34627985 + fields: + - name: DATE + description: SPI register version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SPI1 + description: SPI (Serial Peripheral Interface) Controller 1 + groupName: SPI1 + baseAddress: 1610620928 + addressBlock: + - offset: 0 + size: 168 + usage: registers + registers: + - register: + name: CMD + description: SPI1 memory command register + addressOffset: 0 + size: 32 + fields: + - name: SPI1_MST_ST + description: The current status of SPI1 master FSM. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: MSPI_ST + description: "The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state." + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: FLASH_PE + description: "In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: USR + description: "User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: FLASH_HPM + description: "Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: FLASH_RES + description: "This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: FLASH_DP + description: "Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: FLASH_CE + description: "Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: FLASH_BE + description: "Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: FLASH_SE + description: "Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: FLASH_PP + description: "Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: FLASH_WRSR + description: "Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: FLASH_RDSR + description: "Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: FLASH_RDID + description: "Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: FLASH_WRDI + description: "Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: FLASH_WREN + description: "Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: FLASH_READ + description: "Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: ADDR + description: SPI1 address register + addressOffset: 4 + size: 32 + fields: + - name: USR_ADDR_VALUE + description: "In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CTRL + description: SPI1 control register. + addressOffset: 8 + size: 32 + resetValue: 2924544 + fields: + - name: FDUMMY_OUT + description: In the dummy phase the signal level of spi is output by the spi controller. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FCMD_DUAL + description: "Apply 2 signals during command phase 1:enable 0: disable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FCMD_QUAD + description: "Apply 4 signals during command phase 1:enable 0: disable" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FCS_CRC_EN + description: "For SPI1, initialize crc32 module before writing encrypted data to flash. Active low." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TX_CRC_EN + description: "For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FASTRD_MODE + description: "This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FREAD_DUAL + description: "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RESANDRES + description: "The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: Q_POL + description: "The bit is used to set MISO line polarity, 1: high 0, low" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: D_POL + description: "The bit is used to set MOSI line polarity, 1: high 0, low" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: FREAD_QUAD + description: "In the read operations read-data phase apply 4 signals. 1: enable 0: disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: WP + description: "Write protect signal output when SPI is idle. 1: output high, 0: output low." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: WRSR_2B + description: "two bytes data will be written to status register when it is set. 1: enable 0: disable." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: FREAD_DIO + description: "In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: FREAD_QIO + description: "In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: CTRL1 + description: SPI1 control1 register. + addressOffset: 12 + size: 32 + resetValue: 4092 + fields: + - name: CLK_MODE + description: "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CS_HOLD_DLY_RES + description: "After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles." + bitOffset: 2 + bitWidth: 10 + access: read-write + - register: + name: CTRL2 + description: SPI1 control2 register. + addressOffset: 16 + size: 32 + fields: + - name: SYNC_RESET + description: The FSM will be reset. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: CLOCK + description: SPI1 clock division control register. + addressOffset: 20 + size: 32 + resetValue: 196867 + fields: + - name: CLKCNT_L + description: In the master mode it must be equal to spi_mem_clkcnt_N. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CLKCNT_H + description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: CLKCNT_N + description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: CLK_EQU_SYSCLK + description: reserved + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USER + description: SPI1 user register. + addressOffset: 24 + size: 32 + resetValue: 2147483648 + fields: + - name: CK_OUT_EDGE + description: the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FWRITE_DUAL + description: In the write operations read-data phase apply 2 signals + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FWRITE_QUAD + description: In the write operations read-data phase apply 4 signals + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FWRITE_DIO + description: In the write operations address phase and read-data phase apply 2 signals. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: FWRITE_QIO + description: In the write operations address phase and read-data phase apply 4 signals. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: USR_MISO_HIGHPART + description: "read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: USR_MOSI_HIGHPART + description: "write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: USR_DUMMY_IDLE + description: SPI clock is disable in dummy phase when the bit is enable. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: USR_MOSI + description: This bit enable the write-data phase of an operation. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: USR_MISO + description: This bit enable the read-data phase of an operation. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: USR_DUMMY + description: This bit enable the dummy phase of an operation. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: USR_ADDR + description: This bit enable the address phase of an operation. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: USR_COMMAND + description: This bit enable the command phase of an operation. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USER1 + description: SPI1 user1 register. + addressOffset: 28 + size: 32 + resetValue: 1543503879 + fields: + - name: USR_DUMMY_CYCLELEN + description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: USR_ADDR_BITLEN + description: The length in bits of address phase. The register value shall be (bit_num-1). + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: USER2 + description: SPI1 user2 register. + addressOffset: 32 + size: 32 + resetValue: 1879048192 + fields: + - name: USR_COMMAND_VALUE + description: The value of command. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: USR_COMMAND_BITLEN + description: The length in bits of command phase. The register value shall be (bit_num-1) + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: MOSI_DLEN + description: SPI1 send data bit length control register. + addressOffset: 36 + size: 32 + fields: + - name: USR_MOSI_DBITLEN + description: The length in bits of write-data. The register value shall be (bit_num-1). + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: MISO_DLEN + description: SPI1 receive data bit length control register. + addressOffset: 40 + size: 32 + fields: + - name: USR_MISO_DBITLEN + description: The length in bits of read-data. The register value shall be (bit_num-1). + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: RD_STATUS + description: SPI1 status register. + addressOffset: 44 + size: 32 + fields: + - name: STATUS + description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: WB_MODE + description: Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: MISC + description: SPI1 misc register + addressOffset: 52 + size: 32 + resetValue: 2 + fields: + - name: CS0_DIS + description: "SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CS1_DIS + description: "SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CK_IDLE_EDGE + description: "1: spi clk line is high when idle 0: spi clk line is low when idle" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CS_KEEP_ACTIVE + description: spi cs line keep low when the bit is set. + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: TX_CRC + description: SPI1 TX CRC data register. + addressOffset: 56 + size: 32 + resetValue: 4294967295 + fields: + - name: DATA + description: "For SPI1, the value of crc32." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CACHE_FCTRL + description: SPI1 bit mode control register. + addressOffset: 60 + size: 32 + fields: + - name: CACHE_USR_ADDR_4BYTE + description: "For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FDIN_DUAL + description: "For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FDOUT_DUAL + description: "For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FADDR_DUAL + description: "For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FDIN_QUAD + description: "For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FDOUT_QUAD + description: "For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FADDR_QUAD + description: "For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: W0 + description: SPI1 memory data buffer0 + addressOffset: 88 + size: 32 + fields: + - name: BUF0 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W1 + description: SPI1 memory data buffer1 + addressOffset: 92 + size: 32 + fields: + - name: BUF1 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W2 + description: SPI1 memory data buffer2 + addressOffset: 96 + size: 32 + fields: + - name: BUF2 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W3 + description: SPI1 memory data buffer3 + addressOffset: 100 + size: 32 + fields: + - name: BUF3 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W4 + description: SPI1 memory data buffer4 + addressOffset: 104 + size: 32 + fields: + - name: BUF4 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W5 + description: SPI1 memory data buffer5 + addressOffset: 108 + size: 32 + fields: + - name: BUF5 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W6 + description: SPI1 memory data buffer6 + addressOffset: 112 + size: 32 + fields: + - name: BUF6 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W7 + description: SPI1 memory data buffer7 + addressOffset: 116 + size: 32 + fields: + - name: BUF7 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W8 + description: SPI1 memory data buffer8 + addressOffset: 120 + size: 32 + fields: + - name: BUF8 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W9 + description: SPI1 memory data buffer9 + addressOffset: 124 + size: 32 + fields: + - name: BUF9 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W10 + description: SPI1 memory data buffer10 + addressOffset: 128 + size: 32 + fields: + - name: BUF10 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W11 + description: SPI1 memory data buffer11 + addressOffset: 132 + size: 32 + fields: + - name: BUF11 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W12 + description: SPI1 memory data buffer12 + addressOffset: 136 + size: 32 + fields: + - name: BUF12 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W13 + description: SPI1 memory data buffer13 + addressOffset: 140 + size: 32 + fields: + - name: BUF13 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W14 + description: SPI1 memory data buffer14 + addressOffset: 144 + size: 32 + fields: + - name: BUF14 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W15 + description: SPI1 memory data buffer15 + addressOffset: 148 + size: 32 + fields: + - name: BUF15 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FLASH_WAITI_CTRL + description: SPI1 wait idle control register + addressOffset: 152 + size: 32 + resetValue: 20 + fields: + - name: WAITI_DUMMY + description: The dummy phase enable when wait flash idle (RDSR) + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: WAITI_CMD + description: The command to wait flash idle(RDSR). + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: WAITI_DUMMY_CYCLELEN + description: The dummy cycle length when wait flash idle(RDSR). + bitOffset: 10 + bitWidth: 6 + access: read-write + - register: + name: FLASH_SUS_CTRL + description: SPI1 flash suspend control register + addressOffset: 156 + size: 32 + resetValue: 134225920 + fields: + - name: FLASH_PER + description: "program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FLASH_PES + description: "program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FLASH_PER_WAIT_EN + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FLASH_PES_WAIT_EN + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PES_PER_EN + description: "Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FLASH_PES_EN + description: Set this bit to enable Auto-suspending function. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: PESR_END_MSK + description: "The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]." + bitOffset: 6 + bitWidth: 16 + access: read-write + - name: SPI_FMEM_RD_SUS_2B + description: "1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: PER_END_EN + description: "1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: PES_END_EN + description: "1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SUS_TIMEOUT_CNT + description: "When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass." + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: FLASH_SUS_CMD + description: SPI1 flash suspend command register + addressOffset: 160 + size: 32 + resetValue: 357754 + fields: + - name: FLASH_PER_COMMAND + description: Program/Erase resume command. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: FLASH_PES_COMMAND + description: Program/Erase suspend command. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: WAIT_PESR_COMMAND + description: Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SUS_STATUS + description: SPI1 flash suspend status register + addressOffset: 164 + size: 32 + fields: + - name: FLASH_SUS + description: "The status of flash suspend, only used in SPI1." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: WAIT_PESR_CMD_2B + description: "1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FLASH_HPM_DLY_128 + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FLASH_RES_DLY_128 + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FLASH_DP_DLY_128 + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FLASH_PER_DLY_128 + description: "Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FLASH_PES_DLY_128 + description: "Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI0_LOCK_EN + description: "1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it." + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: TIMING_CALI + description: SPI1 timing control register + addressOffset: 168 + size: 32 + fields: + - name: TIMING_CALI + description: The bit is used to enable timing auto-calibration for all reading operations. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: EXTRA_DUMMY_CYCLELEN + description: add extra dummy spi clock cycle length for spi clock calibration. + bitOffset: 2 + bitWidth: 3 + access: read-only + - register: + name: INT_ENA + description: SPI1 interrupt enable register + addressOffset: 192 + size: 32 + fields: + - name: PER_END_INT_ENA + description: The enable bit for SPI_MEM_PER_END_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PES_END_INT_ENA + description: The enable bit for SPI_MEM_PES_END_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: WPE_END_INT_ENA + description: The enable bit for SPI_MEM_WPE_END_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLV_ST_END_INT_ENA + description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MST_ST_END_INT_ENA + description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_INT_ENA + description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: SPI1 interrupt clear register + addressOffset: 196 + size: 32 + fields: + - name: PER_END_INT_CLR + description: The clear bit for SPI_MEM_PER_END_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: PES_END_INT_CLR + description: The clear bit for SPI_MEM_PES_END_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: WPE_END_INT_CLR + description: The clear bit for SPI_MEM_WPE_END_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SLV_ST_END_INT_CLR + description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: MST_ST_END_INT_CLR + description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: BROWN_OUT_INT_CLR + description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: INT_RAW + description: SPI1 interrupt raw register + addressOffset: 200 + size: 32 + fields: + - name: PER_END_INT_RAW + description: "The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PES_END_INT_RAW + description: "The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: WPE_END_INT_RAW + description: "The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLV_ST_END_INT_RAW + description: "The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MST_ST_END_INT_RAW + description: "The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_INT_RAW + description: "The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others." + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: SPI1 interrupt status register + addressOffset: 204 + size: 32 + fields: + - name: PER_END_INT_ST + description: The status bit for SPI_MEM_PER_END_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PES_END_INT_ST + description: The status bit for SPI_MEM_PES_END_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: WPE_END_INT_ST + description: The status bit for SPI_MEM_WPE_END_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SLV_ST_END_INT_ST + description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: MST_ST_END_INT_ST + description: The status bit for SPI_MEM_MST_ST_END_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: BROWN_OUT_INT_ST + description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: CLOCK_GATE + description: SPI1 clk_gate register + addressOffset: 220 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: "Register clock gate enable signal. 1: Enable. 0: Disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 1020 + size: 32 + resetValue: 34631699 + fields: + - name: DATE + description: Version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SPI2 + description: SPI (Serial Peripheral Interface) Controller 2 + groupName: SPI2 + baseAddress: 1610760192 + addressBlock: + - offset: 0 + size: 152 + usage: registers + interrupt: + - name: SPI1 + value: 15 + - name: SPI2 + value: 16 + registers: + - register: + name: CMD + description: Command control register + addressOffset: 0 + size: 32 + fields: + - name: CONF_BITLEN + description: Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 18 + access: read-write + - name: UPDATE + description: "Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: USR + description: "User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf." + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: ADDR + description: Address value register + addressOffset: 4 + size: 32 + fields: + - name: USR_ADDR_VALUE + description: Address to slave. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CTRL + description: SPI control register + addressOffset: 8 + size: 32 + resetValue: 3932160 + fields: + - name: DUMMY_OUT + description: "0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FADDR_DUAL + description: "Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FADDR_QUAD + description: "Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FADDR_OCT + description: "Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: FCMD_DUAL + description: "Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FCMD_QUAD + description: "Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FCMD_OCT + description: "Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: FREAD_DUAL + description: "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: FREAD_QUAD + description: "In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: FREAD_OCT + description: "In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: Q_POL + description: "The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: D_POL + description: "The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: HOLD_POL + description: "SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: WP_POL + description: "Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: RD_BIT_ORDER + description: "In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state." + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: WR_BIT_ORDER + description: "In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state." + bitOffset: 25 + bitWidth: 2 + access: read-write + - register: + name: CLOCK + description: SPI clock control register + addressOffset: 12 + size: 32 + resetValue: 2147496003 + fields: + - name: CLKCNT_L + description: In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: CLKCNT_H + description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: CLKCNT_N + description: In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + bitOffset: 12 + bitWidth: 6 + access: read-write + - name: CLKDIV_PRE + description: In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + bitOffset: 18 + bitWidth: 4 + access: read-write + - name: CLK_EQU_SYSCLK + description: "In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USER + description: SPI USER control register + addressOffset: 16 + size: 32 + resetValue: 2147483840 + fields: + - name: DOUTDIN + description: "Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: QPI_MODE + description: "Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OPI_MODE + description: "Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TSCK_I_EDGE + description: "In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CS_HOLD + description: "spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CS_SETUP + description: "spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RSCK_I_EDGE + description: "In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CK_OUT_EDGE + description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FWRITE_DUAL + description: In the write operations read-data phase apply 2 signals. Can be configured in CONF state. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FWRITE_QUAD + description: In the write operations read-data phase apply 4 signals. Can be configured in CONF state. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FWRITE_OCT + description: In the write operations read-data phase apply 8 signals. Can be configured in CONF state. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: USR_CONF_NXT + description: "1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SIO + description: "Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: USR_MISO_HIGHPART + description: "read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: USR_MOSI_HIGHPART + description: "write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: USR_DUMMY_IDLE + description: spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: USR_MOSI + description: This bit enable the write-data phase of an operation. Can be configured in CONF state. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: USR_MISO + description: This bit enable the read-data phase of an operation. Can be configured in CONF state. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: USR_DUMMY + description: This bit enable the dummy phase of an operation. Can be configured in CONF state. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: USR_ADDR + description: This bit enable the address phase of an operation. Can be configured in CONF state. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: USR_COMMAND + description: This bit enable the command phase of an operation. Can be configured in CONF state. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USER1 + description: SPI USER control register 1 + addressOffset: 20 + size: 32 + resetValue: 3091267591 + fields: + - name: USR_DUMMY_CYCLELEN + description: The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: MST_WFULL_ERR_END_EN + description: "1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CS_SETUP_TIME + description: (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. + bitOffset: 17 + bitWidth: 5 + access: read-write + - name: CS_HOLD_TIME + description: delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. + bitOffset: 22 + bitWidth: 5 + access: read-write + - name: USR_ADDR_BITLEN + description: The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: USER2 + description: SPI USER control register 2 + addressOffset: 24 + size: 32 + resetValue: 2013265920 + fields: + - name: USR_COMMAND_VALUE + description: The value of command. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MST_REMPTY_ERR_END_EN + description: "1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: USR_COMMAND_BITLEN + description: The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: MS_DLEN + description: SPI data bit length control register + addressOffset: 28 + size: 32 + fields: + - name: MS_DATA_BITLEN + description: The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 0 + bitWidth: 18 + access: read-write + - register: + name: MISC + description: SPI misc register + addressOffset: 32 + size: 32 + resetValue: 62 + fields: + - name: CS0_DIS + description: "SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CS1_DIS + description: "SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CS2_DIS + description: "SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CS3_DIS + description: "SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CS4_DIS + description: "SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CS5_DIS + description: "SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CK_DIS + description: "1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: MASTER_CS_POL + description: "In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: CLK_DATA_DTR_EN + description: "1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19." + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: DATA_DTR_EN + description: "1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state." + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: ADDR_DTR_EN + description: "1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state." + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: CMD_DTR_EN + description: "1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state." + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: SLAVE_CS_POL + description: "spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: DQS_IDLE_EDGE + description: The default value of spi_dqs. Can be configured in CONF state. + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: CK_IDLE_EDGE + description: "1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CS_KEEP_ACTIVE + description: spi cs line keep low when the bit is set. Can be configured in CONF state. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: QUAD_DIN_PIN_SWAP + description: "1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DIN_MODE + description: SPI input delay mode configuration + addressOffset: 36 + size: 32 + fields: + - name: DIN0_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: DIN1_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 2 + bitWidth: 2 + access: read-only + - name: DIN2_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 2 + access: read-only + - name: DIN3_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: DIN4_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 8 + bitWidth: 2 + access: read-only + - name: DIN5_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 10 + bitWidth: 2 + access: read-only + - name: DIN6_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 12 + bitWidth: 2 + access: read-only + - name: DIN7_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 14 + bitWidth: 2 + access: read-only + - name: TIMING_HCLK_ACTIVE + description: "1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state." + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: DIN_NUM + description: SPI input delay number configuration + addressOffset: 40 + size: 32 + fields: + - name: DIN0_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: DIN1_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 2 + bitWidth: 2 + access: read-only + - name: DIN2_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 4 + bitWidth: 2 + access: read-only + - name: DIN3_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: DIN4_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 8 + bitWidth: 2 + access: read-only + - name: DIN5_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 10 + bitWidth: 2 + access: read-only + - name: DIN6_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 12 + bitWidth: 2 + access: read-only + - name: DIN7_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 14 + bitWidth: 2 + access: read-only + - register: + name: DOUT_MODE + description: SPI output delay mode configuration + addressOffset: 44 + size: 32 + fields: + - name: DOUT0_MODE + description: "The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DOUT1_MODE + description: "The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: DOUT2_MODE + description: "The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: DOUT3_MODE + description: "The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DOUT4_MODE + description: "The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DOUT5_MODE + description: "The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: DOUT6_MODE + description: "The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: DOUT7_MODE + description: "The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: D_DQS_MODE + description: "The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: DMA_CONF + description: SPI DMA control register + addressOffset: 48 + size: 32 + resetValue: 3 + fields: + - name: DMA_OUTFIFO_EMPTY + description: "Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DMA_INFIFO_FULL + description: "Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: DMA_SLV_SEG_TRANS_EN + description: "Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SLV_RX_SEG_TRANS_CLR_EN + description: "1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SLV_TX_SEG_TRANS_CLR_EN + description: "1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: RX_EOF_EN + description: "1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: DMA_RX_ENA + description: Set this bit to enable SPI DMA controlled receive data mode. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: DMA_TX_ENA + description: Set this bit to enable SPI DMA controlled send data mode. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: RX_AFIFO_RST + description: "Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer." + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: BUF_AFIFO_RST + description: "Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer." + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: DMA_AFIFO_RST + description: "Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer." + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: DMA_INT_ENA + description: SPI interrupt enable register + addressOffset: 52 + size: 32 + fields: + - name: DMA_INFIFO_FULL_ERR_INT_ENA + description: The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DMA_OUTFIFO_EMPTY_ERR_INT_ENA + description: The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SLV_EX_QPI_INT_ENA + description: The enable bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLV_EN_QPI_INT_ENA + description: The enable bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLV_CMD7_INT_ENA + description: The enable bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SLV_CMD8_INT_ENA + description: The enable bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SLV_CMD9_INT_ENA + description: The enable bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SLV_CMDA_INT_ENA + description: The enable bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SLV_RD_DMA_DONE_INT_ENA + description: The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLV_WR_DMA_DONE_INT_ENA + description: The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLV_RD_BUF_DONE_INT_ENA + description: The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLV_WR_BUF_DONE_INT_ENA + description: The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TRANS_DONE_INT_ENA + description: The enable bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DMA_SEG_TRANS_DONE_INT_ENA + description: The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SEG_MAGIC_ERR_INT_ENA + description: The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLV_BUF_ADDR_ERR_INT_ENA + description: The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLV_CMD_ERR_INT_ENA + description: The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: MST_RX_AFIFO_WFULL_ERR_INT_ENA + description: The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MST_TX_AFIFO_REMPTY_ERR_INT_ENA + description: The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: APP2_INT_ENA + description: The enable bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: APP1_INT_ENA + description: The enable bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: DMA_INT_CLR + description: SPI interrupt clear register + addressOffset: 56 + size: 32 + fields: + - name: DMA_INFIFO_FULL_ERR_INT_CLR + description: The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: DMA_OUTFIFO_EMPTY_ERR_INT_CLR + description: The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SLV_EX_QPI_INT_CLR + description: The clear bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SLV_EN_QPI_INT_CLR + description: The clear bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SLV_CMD7_INT_CLR + description: The clear bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SLV_CMD8_INT_CLR + description: The clear bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: SLV_CMD9_INT_CLR + description: The clear bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: SLV_CMDA_INT_CLR + description: The clear bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SLV_RD_DMA_DONE_INT_CLR + description: The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SLV_WR_DMA_DONE_INT_CLR + description: The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SLV_RD_BUF_DONE_INT_CLR + description: The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SLV_WR_BUF_DONE_INT_CLR + description: The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TRANS_DONE_INT_CLR + description: The clear bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: DMA_SEG_TRANS_DONE_INT_CLR + description: The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SEG_MAGIC_ERR_INT_CLR + description: The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SLV_BUF_ADDR_ERR_INT_CLR + description: The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: SLV_CMD_ERR_INT_CLR + description: The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: MST_RX_AFIFO_WFULL_ERR_INT_CLR + description: The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: MST_TX_AFIFO_REMPTY_ERR_INT_CLR + description: The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: APP2_INT_CLR + description: The clear bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: APP1_INT_CLR + description: The clear bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: write-only + - register: + name: DMA_INT_RAW + description: SPI interrupt raw register + addressOffset: 60 + size: 32 + fields: + - name: DMA_INFIFO_FULL_ERR_INT_RAW + description: "1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DMA_OUTFIFO_EMPTY_ERR_INT_RAW + description: "1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SLV_EX_QPI_INT_RAW + description: "The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLV_EN_QPI_INT_RAW + description: "The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLV_CMD7_INT_RAW + description: "The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SLV_CMD8_INT_RAW + description: "The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SLV_CMD9_INT_RAW + description: "The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SLV_CMDA_INT_RAW + description: "The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SLV_RD_DMA_DONE_INT_RAW + description: "The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLV_WR_DMA_DONE_INT_RAW + description: "The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLV_RD_BUF_DONE_INT_RAW + description: "The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLV_WR_BUF_DONE_INT_RAW + description: "The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TRANS_DONE_INT_RAW + description: "The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DMA_SEG_TRANS_DONE_INT_RAW + description: "The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SEG_MAGIC_ERR_INT_RAW + description: "The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLV_BUF_ADDR_ERR_INT_RAW + description: "The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLV_CMD_ERR_INT_RAW + description: "The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: MST_RX_AFIFO_WFULL_ERR_INT_RAW + description: "The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MST_TX_AFIFO_REMPTY_ERR_INT_RAW + description: "The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: APP2_INT_RAW + description: The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: APP1_INT_RAW + description: The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: DMA_INT_ST + description: SPI interrupt status register + addressOffset: 64 + size: 32 + fields: + - name: DMA_INFIFO_FULL_ERR_INT_ST + description: The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DMA_OUTFIFO_EMPTY_ERR_INT_ST + description: The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SLV_EX_QPI_INT_ST + description: The status bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SLV_EN_QPI_INT_ST + description: The status bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SLV_CMD7_INT_ST + description: The status bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SLV_CMD8_INT_ST + description: The status bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SLV_CMD9_INT_ST + description: The status bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SLV_CMDA_INT_ST + description: The status bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SLV_RD_DMA_DONE_INT_ST + description: The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SLV_WR_DMA_DONE_INT_ST + description: The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SLV_RD_BUF_DONE_INT_ST + description: The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SLV_WR_BUF_DONE_INT_ST + description: The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TRANS_DONE_INT_ST + description: The status bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: DMA_SEG_TRANS_DONE_INT_ST + description: The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SEG_MAGIC_ERR_INT_ST + description: The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SLV_BUF_ADDR_ERR_INT_ST + description: The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLV_CMD_ERR_INT_ST + description: The status bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: MST_RX_AFIFO_WFULL_ERR_INT_ST + description: The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: MST_TX_AFIFO_REMPTY_ERR_INT_ST + description: The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: APP2_INT_ST + description: The status bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: APP1_INT_ST + description: The status bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: read-only + - register: + name: DMA_INT_SET + description: SPI interrupt software set register + addressOffset: 68 + size: 32 + fields: + - name: DMA_INFIFO_FULL_ERR_INT_SET + description: The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: DMA_OUTFIFO_EMPTY_ERR_INT_SET + description: The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SLV_EX_QPI_INT_SET + description: The software set bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SLV_EN_QPI_INT_SET + description: The software set bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SLV_CMD7_INT_SET + description: The software set bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SLV_CMD8_INT_SET + description: The software set bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: SLV_CMD9_INT_SET + description: The software set bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: SLV_CMDA_INT_SET + description: The software set bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SLV_RD_DMA_DONE_INT_SET + description: The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SLV_WR_DMA_DONE_INT_SET + description: The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SLV_RD_BUF_DONE_INT_SET + description: The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SLV_WR_BUF_DONE_INT_SET + description: The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TRANS_DONE_INT_SET + description: The software set bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: DMA_SEG_TRANS_DONE_INT_SET + description: The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SEG_MAGIC_ERR_INT_SET + description: The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SLV_BUF_ADDR_ERR_INT_SET + description: The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: SLV_CMD_ERR_INT_SET + description: The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: MST_RX_AFIFO_WFULL_ERR_INT_SET + description: The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: MST_TX_AFIFO_REMPTY_ERR_INT_SET + description: The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: APP2_INT_SET + description: The software set bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: APP1_INT_SET + description: The software set bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: write-only + - register: + name: W0 + description: SPI CPU-controlled buffer0 + addressOffset: 152 + size: 32 + fields: + - name: BUF0 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W1 + description: SPI CPU-controlled buffer1 + addressOffset: 156 + size: 32 + fields: + - name: BUF1 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W2 + description: SPI CPU-controlled buffer2 + addressOffset: 160 + size: 32 + fields: + - name: BUF2 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W3 + description: SPI CPU-controlled buffer3 + addressOffset: 164 + size: 32 + fields: + - name: BUF3 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W4 + description: SPI CPU-controlled buffer4 + addressOffset: 168 + size: 32 + fields: + - name: BUF4 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W5 + description: SPI CPU-controlled buffer5 + addressOffset: 172 + size: 32 + fields: + - name: BUF5 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W6 + description: SPI CPU-controlled buffer6 + addressOffset: 176 + size: 32 + fields: + - name: BUF6 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W7 + description: SPI CPU-controlled buffer7 + addressOffset: 180 + size: 32 + fields: + - name: BUF7 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W8 + description: SPI CPU-controlled buffer8 + addressOffset: 184 + size: 32 + fields: + - name: BUF8 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W9 + description: SPI CPU-controlled buffer9 + addressOffset: 188 + size: 32 + fields: + - name: BUF9 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W10 + description: SPI CPU-controlled buffer10 + addressOffset: 192 + size: 32 + fields: + - name: BUF10 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W11 + description: SPI CPU-controlled buffer11 + addressOffset: 196 + size: 32 + fields: + - name: BUF11 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W12 + description: SPI CPU-controlled buffer12 + addressOffset: 200 + size: 32 + fields: + - name: BUF12 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W13 + description: SPI CPU-controlled buffer13 + addressOffset: 204 + size: 32 + fields: + - name: BUF13 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W14 + description: SPI CPU-controlled buffer14 + addressOffset: 208 + size: 32 + fields: + - name: BUF14 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W15 + description: SPI CPU-controlled buffer15 + addressOffset: 212 + size: 32 + fields: + - name: BUF15 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SLAVE + description: SPI slave control register + addressOffset: 224 + size: 32 + resetValue: 41943040 + fields: + - name: CLK_MODE + description: "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CLK_MODE_13 + description: "{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RSCK_DATA_OUT + description: "It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLV_RDDMA_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLV_WRDMA_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLV_RDBUF_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLV_WRBUF_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DMA_SEG_MAGIC_VALUE + description: The magic value of BM table in master DMA seg-trans. + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: MODE + description: "Set SPI work mode. 1: slave mode 0: master mode." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SOFT_RESET + description: "Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state." + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: USR_CONF + description: "1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode." + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: SLAVE1 + description: SPI slave control register 1 + addressOffset: 228 + size: 32 + fields: + - name: SLV_DATA_BITLEN + description: The transferred data bit length in SPI slave FD and HD mode. + bitOffset: 0 + bitWidth: 18 + access: read-write + - name: SLV_LAST_COMMAND + description: In the slave mode it is the value of command. + bitOffset: 18 + bitWidth: 8 + access: read-write + - name: SLV_LAST_ADDR + description: In the slave mode it is the value of address. + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: CLK_GATE + description: SPI module clock and register clock control + addressOffset: 232 + size: 32 + fields: + - name: CLK_EN + description: Set this bit to enable clk gate + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MST_CLK_ACTIVE + description: Set this bit to power on the SPI module clock. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MST_CLK_SEL + description: "This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control + addressOffset: 240 + size: 32 + resetValue: 34627696 + fields: + - name: DATE + description: SPI register version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SYSTEM + description: System Configuration Registers + groupName: SYSTEM + baseAddress: 1611399168 + addressBlock: + - offset: 0 + size: 160 + usage: registers + registers: + - register: + name: CPU_PERI_CLK_EN + description: cpu_peripheral clock gating register + addressOffset: 0 + size: 32 + fields: + - name: CLK_EN_ASSIST_DEBUG + description: Set 1 to open assist_debug module clock + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CLK_EN_DEDICATED_GPIO + description: Set 1 to open dedicated_gpio module clk + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: CPU_PERI_RST_EN + description: cpu_peripheral reset register + addressOffset: 4 + size: 32 + resetValue: 192 + fields: + - name: RST_EN_ASSIST_DEBUG + description: Set 1 to let assist_debug module reset + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RST_EN_DEDICATED_GPIO + description: Set 1 to let dedicated_gpio module reset + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: CPU_PER_CONF + description: cpu clock config register + addressOffset: 8 + size: 32 + resetValue: 12 + fields: + - name: CPUPERIOD_SEL + description: This field used to sel cpu clock frequent. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: PLL_FREQ_SEL + description: This field used to sel pll frequent. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CPU_WAIT_MODE_FORCE_ON + description: Set 1 to force cpu_waiti_clk enable. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CPU_WAITI_DELAY_NUM + description: "This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close" + bitOffset: 4 + bitWidth: 4 + access: read-write + - register: + name: MEM_PD_MASK + description: memory power down mask register + addressOffset: 12 + size: 32 + resetValue: 1 + fields: + - name: LSLP_MEM_PD_MASK + description: Set 1 to mask memory power down. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: PERIP_CLK_EN0 + description: peripheral clock gating register + addressOffset: 16 + size: 32 + resetValue: 1895833702 + fields: + - name: SPI01_CLK_EN + description: Set 1 to enable SPI01 clock + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UART_CLK_EN + description: Set 1 to enable UART clock + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: UART1_CLK_EN + description: Set 1 to enable UART1 clock + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI2_CLK_EN + description: Set 1 to enable SPI2 clock + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: I2C_EXT0_CLK_EN + description: Set 1 to enable I2C_EXT0 clock + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: LEDC_CLK_EN + description: Set 1 to enable LEDC clock + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TIMERGROUP_CLK_EN + description: Set 1 to enable TIMERGROUP clock + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: UART_MEM_CLK_EN + description: Set 1 to enable UART_MEM clock + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: APB_SARADC_CLK_EN + description: Set 1 to enable APB_SARADC clock + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SYSTIMER_CLK_EN + description: Set 1 to enable SYSTEMTIMER clock + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ADC2_ARB_CLK_EN + description: Set 1 to enable ADC2_ARB clock + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: PERIP_CLK_EN1 + description: peripheral clock gating register + addressOffset: 20 + size: 32 + fields: + - name: CRYPTO_ECC_CLK_EN + description: Set 1 to enable ECC clock + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CRYPTO_SHA_CLK_EN + description: Set 1 to enable SHA clock + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DMA_CLK_EN + description: Set 1 to enable DMA clock + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TSENS_CLK_EN + description: Set 1 to enable TSENS clock + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PERIP_RST_EN0 + description: reserved + addressOffset: 24 + size: 32 + fields: + - name: SPI01_RST + description: Set 1 to let SPI01 reset + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UART_RST + description: Set 1 to let UART reset + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: UART1_RST + description: Set 1 to let UART1 reset + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI2_RST + description: Set 1 to let SPI2 reset + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: I2C_EXT0_RST + description: Set 1 to let I2C_EXT0 reset + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: LEDC_RST + description: Set 1 to let LEDC reset + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TIMERGROUP_RST + description: Set 1 to let TIMERGROUP reset + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: UART_MEM_RST + description: Set 1 to let UART_MEM reset + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: APB_SARADC_RST + description: Set 1 to let APB_SARADC reset + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SYSTIMER_RST + description: Set 1 to let SYSTIMER reset + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ADC2_ARB_RST + description: Set 1 to let ADC2_ARB reset + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: PERIP_RST_EN1 + description: peripheral reset register + addressOffset: 28 + size: 32 + resetValue: 70 + fields: + - name: CRYPTO_ECC_RST + description: Set 1 to let CRYPTO_ECC reset + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CRYPTO_SHA_RST + description: Set 1 to let CRYPTO_SHA reset + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DMA_RST + description: Set 1 to let DMA reset + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TSENS_RST + description: Set 1 to let TSENS reset + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: BT_LPCK_DIV_INT + description: clock config register + addressOffset: 32 + size: 32 + resetValue: 255 + fields: + - name: BT_LPCK_DIV_NUM + description: This field is lower power clock frequent division factor + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: BT_LPCK_DIV_FRAC + description: low power clock configuration register + addressOffset: 36 + size: 32 + resetValue: 33558529 + fields: + - name: BT_LPCK_DIV_B + description: This field is lower power clock frequent division factor b + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: BT_LPCK_DIV_A + description: This field is lower power clock frequent division factor a + bitOffset: 12 + bitWidth: 12 + access: read-write + - name: LPCLK_SEL_RTC_SLOW + description: Set 1 to select rtc-slow clock as rtc low power clock + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: LPCLK_SEL_8M + description: Set 1 to select 8m clock as rtc low power clock + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LPCLK_SEL_XTAL + description: Set 1 to select xtal clock as rtc low power clock + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LPCLK_SEL_XTAL32K + description: Set 1 to select xtal32k clock as low power clock + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LPCLK_RTC_EN + description: Set 1 to enable RTC low power clock + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_0 + description: interrupt generate register + addressOffset: 40 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_0 + description: Set 1 to generate cpu interrupt 0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_1 + description: interrupt generate register + addressOffset: 44 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_1 + description: Set 1 to generate cpu interrupt 1 + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_2 + description: interrupt generate register + addressOffset: 48 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_2 + description: Set 1 to generate cpu interrupt 2 + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_3 + description: interrupt generate register + addressOffset: 52 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_3 + description: Set 1 to generate cpu interrupt 3 + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: RSA_PD_CTRL + description: rsa memory power control register + addressOffset: 56 + size: 32 + resetValue: 1 + fields: + - name: RSA_MEM_PD + description: Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Signature occupies the RSA. This bit is invalid. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RSA_MEM_FORCE_PU + description: Set 1 to force power up RSA memory. This bit has the second highest priority. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RSA_MEM_FORCE_PD + description: Set 1 to force power down RSA memory. This bit has the highest priority. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: EDMA_CTRL + description: edma clcok and reset register + addressOffset: 60 + size: 32 + resetValue: 1 + fields: + - name: EDMA_CLK_ON + description: Set 1 to enable EDMA clock. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EDMA_RESET + description: Set 1 to let EDMA reset + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CACHE_CONTROL + description: cache control register + addressOffset: 64 + size: 32 + resetValue: 5 + fields: + - name: ICACHE_CLK_ON + description: Set 1 to enable icache clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ICACHE_RESET + description: Set 1 to let icache reset + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DCACHE_CLK_ON + description: Set 1 to enable dcache clock + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DCACHE_RESET + description: Set 1 to let dcache reset + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL + description: SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG + addressOffset: 68 + size: 32 + fields: + - name: ENABLE_SPI_MANUAL_ENCRYPT + description: Set 1 to enable the SPI manual encrypt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ENABLE_DOWNLOAD_DB_ENCRYPT + description: Set 1 to enable download DB encrypt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ENABLE_DOWNLOAD_G0CB_DECRYPT + description: Set 1 to enable download G0CB decrypt + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ENABLE_DOWNLOAD_MANUAL_ENCRYPT + description: Set 1 to enable download manual encrypt + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: RTC_FASTMEM_CONFIG + description: fast memory config register + addressOffset: 72 + size: 32 + resetValue: 2146435072 + fields: + - name: RTC_MEM_CRC_START + description: Set 1 to start the CRC of RTC memory + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RTC_MEM_CRC_ADDR + description: This field is used to set address of RTC memory for CRC. + bitOffset: 9 + bitWidth: 11 + access: read-write + - name: RTC_MEM_CRC_LEN + description: This field is used to set length of RTC memory for CRC based on start address. + bitOffset: 20 + bitWidth: 11 + access: read-write + - name: RTC_MEM_CRC_FINISH + description: This bit stores the status of RTC memory CRC.1 means finished. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: RTC_FASTMEM_CRC + description: reserved + addressOffset: 76 + size: 32 + fields: + - name: RTC_MEM_CRC_RES + description: This field stores the CRC result of RTC memory. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: REDUNDANT_ECO_CTRL + description: eco register + addressOffset: 80 + size: 32 + fields: + - name: REDUNDANT_ECO_DRIVE + description: reg_redundant_eco_drive + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REDUNDANT_ECO_RESULT + description: reg_redundant_eco_result + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: CLOCK_GATE + description: clock gating register + addressOffset: 84 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: reg_clk_en + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SYSCLK_CONF + description: system clock config register + addressOffset: 88 + size: 32 + resetValue: 1 + fields: + - name: PRE_DIV_CNT + description: This field is used to set the count of prescaler of XTAL_CLK. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: SOC_CLK_SEL + description: This field is used to select soc clock. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CLK_XTAL_FREQ + description: This field is used to read xtal frequency in MHz. + bitOffset: 12 + bitWidth: 7 + access: read-only + - name: CLK_DIV_EN + description: reg_clk_div_en + bitOffset: 19 + bitWidth: 1 + access: read-only + - register: + name: MEM_PVT + description: mem pvt register + addressOffset: 92 + size: 32 + resetValue: 3 + fields: + - name: MEM_PATH_LEN + description: reg_mem_path_len + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: MEM_ERR_CNT_CLR + description: reg_mem_err_cnt_clr + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: MONITOR_EN + description: reg_mem_pvt_monitor_en + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: MEM_TIMING_ERR_CNT + description: reg_mem_timing_err_cnt + bitOffset: 6 + bitWidth: 16 + access: read-only + - name: MEM_VT_SEL + description: reg_mem_vt_sel + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: COMB_PVT_LVT_CONF + description: mem pvt register + addressOffset: 96 + size: 32 + resetValue: 3 + fields: + - name: COMB_PATH_LEN_LVT + description: reg_comb_path_len_lvt + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: COMB_ERR_CNT_CLR_LVT + description: reg_comb_err_cnt_clr_lvt + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: COMB_PVT_MONITOR_EN_LVT + description: reg_comb_pvt_monitor_en_lvt + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: COMB_PVT_NVT_CONF + description: mem pvt register + addressOffset: 100 + size: 32 + resetValue: 3 + fields: + - name: COMB_PATH_LEN_NVT + description: reg_comb_path_len_nvt + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: COMB_ERR_CNT_CLR_NVT + description: reg_comb_err_cnt_clr_nvt + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: COMB_PVT_MONITOR_EN_NVT + description: reg_comb_pvt_monitor_en_nvt + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: COMB_PVT_HVT_CONF + description: mem pvt register + addressOffset: 104 + size: 32 + resetValue: 3 + fields: + - name: COMB_PATH_LEN_HVT + description: reg_comb_path_len_hvt + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: COMB_ERR_CNT_CLR_HVT + description: reg_comb_err_cnt_clr_hvt + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: COMB_PVT_MONITOR_EN_HVT + description: reg_comb_pvt_monitor_en_hvt + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: COMB_PVT_ERR_LVT_SITE0 + description: mem pvt register + addressOffset: 108 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_LVT_SITE0 + description: reg_comb_timing_err_cnt_lvt_site0 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_NVT_SITE0 + description: mem pvt register + addressOffset: 112 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_NVT_SITE0 + description: reg_comb_timing_err_cnt_nvt_site0 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_HVT_SITE0 + description: mem pvt register + addressOffset: 116 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_HVT_SITE0 + description: reg_comb_timing_err_cnt_hvt_site0 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_LVT_SITE1 + description: mem pvt register + addressOffset: 120 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_LVT_SITE1 + description: reg_comb_timing_err_cnt_lvt_site1 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_NVT_SITE1 + description: mem pvt register + addressOffset: 124 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_NVT_SITE1 + description: reg_comb_timing_err_cnt_nvt_site1 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_HVT_SITE1 + description: mem pvt register + addressOffset: 128 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_HVT_SITE1 + description: reg_comb_timing_err_cnt_hvt_site1 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_LVT_SITE2 + description: mem pvt register + addressOffset: 132 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_LVT_SITE2 + description: reg_comb_timing_err_cnt_lvt_site2 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_NVT_SITE2 + description: mem pvt register + addressOffset: 136 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_NVT_SITE2 + description: reg_comb_timing_err_cnt_nvt_site2 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_HVT_SITE2 + description: mem pvt register + addressOffset: 140 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_HVT_SITE2 + description: reg_comb_timing_err_cnt_hvt_site2 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_LVT_SITE3 + description: mem pvt register + addressOffset: 144 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_LVT_SITE3 + description: reg_comb_timing_err_cnt_lvt_site3 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_NVT_SITE3 + description: mem pvt register + addressOffset: 148 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_NVT_SITE3 + description: reg_comb_timing_err_cnt_nvt_site3 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_HVT_SITE3 + description: mem pvt register + addressOffset: 152 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_HVT_SITE3 + description: reg_comb_timing_err_cnt_hvt_site3 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: REG_DATE + description: Version register + addressOffset: 4092 + size: 32 + resetValue: 34636176 + fields: + - name: SYSTEM_REG_DATE + description: reg_system_reg_date + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SYSTIMER + description: System Timer + groupName: SYSTIMER + baseAddress: 1610756096 + addressBlock: + - offset: 0 + size: 120 + usage: registers + interrupt: + - name: SYSTIMER_TARGET0 + value: 26 + - name: SYSTIMER_TARGET1 + value: 27 + - name: SYSTIMER_TARGET2 + value: 28 + registers: + - register: + name: CONF + description: Configure system timer clock + addressOffset: 0 + size: 32 + resetValue: 1174405120 + fields: + - name: SYSTIMER_CLK_FO + description: systimer clock force on + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TARGET2_WORK_EN + description: target2 work enable + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TARGET1_WORK_EN + description: target1 work enable + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TARGET0_WORK_EN + description: target0 work enable + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT1_CORE1_STALL_EN + description: If timer unit1 is stalled when core1 stalled + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT1_CORE0_STALL_EN + description: If timer unit1 is stalled when core0 stalled + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT0_CORE1_STALL_EN + description: If timer unit0 is stalled when core1 stalled + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT0_CORE0_STALL_EN + description: If timer unit0 is stalled when core0 stalled + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT1_WORK_EN + description: timer unit1 work enable + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT0_WORK_EN + description: timer unit0 work enable + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: register file clk gating + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: UNIT0_OP + description: system timer unit0 value update register + addressOffset: 4 + size: 32 + fields: + - name: TIMER_UNIT0_VALUE_VALID + description: timer value is sync and valid + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: TIMER_UNIT0_UPDATE + description: update timer_unit0 + bitOffset: 30 + bitWidth: 1 + access: write-only + - register: + name: UNIT1_OP + description: system timer unit1 value update register + addressOffset: 8 + size: 32 + fields: + - name: TIMER_UNIT1_VALUE_VALID + description: timer value is sync and valid + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: TIMER_UNIT1_UPDATE + description: update timer unit1 + bitOffset: 30 + bitWidth: 1 + access: write-only + - register: + name: UNIT0_LOAD_HI + description: system timer unit0 value high load register + addressOffset: 12 + size: 32 + fields: + - name: TIMER_UNIT0_LOAD_HI + description: timer unit0 load high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: UNIT0_LOAD_LO + description: system timer unit0 value low load register + addressOffset: 16 + size: 32 + fields: + - name: TIMER_UNIT0_LOAD_LO + description: timer unit0 load low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: UNIT1_LOAD_HI + description: system timer unit1 value high load register + addressOffset: 20 + size: 32 + fields: + - name: TIMER_UNIT1_LOAD_HI + description: timer unit1 load high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: UNIT1_LOAD_LO + description: system timer unit1 value low load register + addressOffset: 24 + size: 32 + fields: + - name: TIMER_UNIT1_LOAD_LO + description: timer unit1 load low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET0_HI + description: system timer comp0 value high register + addressOffset: 28 + size: 32 + fields: + - name: TIMER_TARGET0_HI + description: timer taget0 high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: TARGET0_LO + description: system timer comp0 value low register + addressOffset: 32 + size: 32 + fields: + - name: TIMER_TARGET0_LO + description: timer taget0 low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET1_HI + description: system timer comp1 value high register + addressOffset: 36 + size: 32 + fields: + - name: TIMER_TARGET1_HI + description: timer taget1 high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: TARGET1_LO + description: system timer comp1 value low register + addressOffset: 40 + size: 32 + fields: + - name: TIMER_TARGET1_LO + description: timer taget1 low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET2_HI + description: system timer comp2 value high register + addressOffset: 44 + size: 32 + fields: + - name: TIMER_TARGET2_HI + description: timer taget2 high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: TARGET2_LO + description: system timer comp2 value low register + addressOffset: 48 + size: 32 + fields: + - name: TIMER_TARGET2_LO + description: timer taget2 low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET0_CONF + description: system timer comp0 target mode register + addressOffset: 52 + size: 32 + fields: + - name: TARGET0_PERIOD + description: target0 period + bitOffset: 0 + bitWidth: 26 + access: read-write + - name: TARGET0_PERIOD_MODE + description: Set target0 to period mode + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TARGET0_TIMER_UNIT_SEL + description: select which unit to compare + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TARGET1_CONF + description: system timer comp1 target mode register + addressOffset: 56 + size: 32 + fields: + - name: TARGET1_PERIOD + description: target1 period + bitOffset: 0 + bitWidth: 26 + access: read-write + - name: TARGET1_PERIOD_MODE + description: Set target1 to period mode + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TARGET1_TIMER_UNIT_SEL + description: select which unit to compare + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TARGET2_CONF + description: system timer comp2 target mode register + addressOffset: 60 + size: 32 + fields: + - name: TARGET2_PERIOD + description: target2 period + bitOffset: 0 + bitWidth: 26 + access: read-write + - name: TARGET2_PERIOD_MODE + description: Set target2 to period mode + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TARGET2_TIMER_UNIT_SEL + description: select which unit to compare + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: UNIT0_VALUE_HI + description: system timer unit0 value high register + addressOffset: 64 + size: 32 + fields: + - name: TIMER_UNIT0_VALUE_HI + description: timer read value high 20bits + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: UNIT0_VALUE_LO + description: system timer unit0 value low register + addressOffset: 68 + size: 32 + fields: + - name: TIMER_UNIT0_VALUE_LO + description: timer read value low 32bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: UNIT1_VALUE_HI + description: system timer unit1 value high register + addressOffset: 72 + size: 32 + fields: + - name: TIMER_UNIT1_VALUE_HI + description: timer read value high 20bits + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: UNIT1_VALUE_LO + description: system timer unit1 value low register + addressOffset: 76 + size: 32 + fields: + - name: TIMER_UNIT1_VALUE_LO + description: timer read value low 32bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: COMP0_LOAD + description: system timer comp0 conf sync register + addressOffset: 80 + size: 32 + fields: + - name: TIMER_COMP0_LOAD + description: timer comp0 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: COMP1_LOAD + description: system timer comp1 conf sync register + addressOffset: 84 + size: 32 + fields: + - name: TIMER_COMP1_LOAD + description: timer comp1 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: COMP2_LOAD + description: system timer comp2 conf sync register + addressOffset: 88 + size: 32 + fields: + - name: TIMER_COMP2_LOAD + description: timer comp2 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: UNIT0_LOAD + description: system timer unit0 conf sync register + addressOffset: 92 + size: 32 + fields: + - name: TIMER_UNIT0_LOAD + description: timer unit0 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: UNIT1_LOAD + description: system timer unit1 conf sync register + addressOffset: 96 + size: 32 + fields: + - name: TIMER_UNIT1_LOAD + description: timer unit1 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + description: systimer interrupt enable register + addressOffset: 100 + size: 32 + fields: + - name: TARGET0_INT_ENA + description: interupt0 enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TARGET1_INT_ENA + description: interupt1 enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TARGET2_INT_ENA + description: interupt2 enable + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: systimer interrupt raw register + addressOffset: 104 + size: 32 + fields: + - name: TARGET0_INT_RAW + description: interupt0 raw + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TARGET1_INT_RAW + description: interupt1 raw + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TARGET2_INT_RAW + description: interupt2 raw + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: systimer interrupt clear register + addressOffset: 108 + size: 32 + fields: + - name: TARGET0_INT_CLR + description: interupt0 clear + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TARGET1_INT_CLR + description: interupt1 clear + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TARGET2_INT_CLR + description: interupt2 clear + bitOffset: 2 + bitWidth: 1 + access: write-only + - register: + name: INT_ST + description: systimer interrupt status register + addressOffset: 112 + size: 32 + fields: + - name: TARGET0_INT_ST + description: interupt0 status + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TARGET1_INT_ST + description: interupt1 status + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TARGET2_INT_ST + description: interupt2 status + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: system timer version control register + addressOffset: 252 + size: 32 + resetValue: 33628753 + fields: + - name: DATE + description: systimer register version + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: TIMG0 + description: Timer Group 0 + groupName: TIMG + baseAddress: 1610739712 + addressBlock: + - offset: 0 + size: 104 + usage: registers + interrupt: + - name: TG0_T0_LEVEL + value: 23 + - name: TG0_WDT_LEVEL + value: 24 + registers: + - register: + name: T0CONFIG + description: Timer %s configuration register + addressOffset: 0 + size: 32 + resetValue: 1610620928 + fields: + - name: USE_XTAL + description: "1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: ALARM_EN + description: "When set, the alarm is enabled. This bit is automatically cleared once an\nalarm occurs." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DIVCNT_RST + description: "When set, Timer %s 's clock divider counter will be reset." + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: DIVIDER + description: Timer %s clock (T%s_clk) prescaler value. + bitOffset: 13 + bitWidth: 16 + access: read-write + - name: AUTORELOAD + description: "When set, timer %s auto-reload at alarm is enabled." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: INCREASE + description: "When set, the timer %s time-base counter will increment every clock tick. When\ncleared, the timer %s time-base counter will decrement." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: EN + description: "When set, the timer %s time-base counter is enabled." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: T0LO + description: "Timer %s current value, low 32 bits" + addressOffset: 4 + size: 32 + fields: + - name: LO + description: "After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter\nof timer %s can be read here." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: T0HI + description: "Timer %s current value, high 22 bits" + addressOffset: 8 + size: 32 + fields: + - name: T0_HI + description: "After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter\nof timer %s can be read here." + bitOffset: 0 + bitWidth: 22 + access: read-only + - register: + name: T0UPDATE + description: Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG + addressOffset: 12 + size: 32 + fields: + - name: UPDATE + description: "After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: T0ALARMLO + description: "Timer %s alarm value, low 32 bits" + addressOffset: 16 + size: 32 + fields: + - name: ALARM_LO + description: "Timer %s alarm trigger time-base counter value, low 32 bits." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: T0ALARMHI + description: "Timer %s alarm value, high bits" + addressOffset: 20 + size: 32 + fields: + - name: ALARM_HI + description: "Timer %s alarm trigger time-base counter value, high 22 bits." + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: T0LOADLO + description: "Timer %s reload value, low 32 bits" + addressOffset: 24 + size: 32 + fields: + - name: LOAD_LO + description: "Low 32 bits of the value that a reload will load onto timer %s time-base\nCounter." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: T0LOADHI + description: "Timer %s reload value, high 22 bits" + addressOffset: 28 + size: 32 + fields: + - name: LOAD_HI + description: "High 22 bits of the value that a reload will load onto timer %s time-base\ncounter." + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: T0LOAD + description: Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG + addressOffset: 32 + size: 32 + fields: + - name: LOAD + description: Write any value to trigger a timer %s time-base counter reload. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: WDTCONFIG0 + description: Watchdog timer configuration register + addressOffset: 72 + size: 32 + resetValue: 311296 + fields: + - name: WDT_APPCPU_RESET_EN + description: WDT reset CPU enable. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: WDT_PROCPU_RESET_EN + description: WDT reset CPU enable. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: WDT_FLASHBOOT_MOD_EN + description: "When set, Flash boot protection is enabled." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: WDT_SYS_RESET_LENGTH + description: "System reset signal length selection. 0: 100 ns, 1: 200 ns,\n2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us." + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: WDT_CPU_RESET_LENGTH + description: "CPU reset signal length selection. 0: 100 ns, 1: 200 ns,\n2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us." + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: WDT_USE_XTAL + description: "choose WDT clock:0-apb_clk; 1-xtal_clk." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: WDT_CONF_UPDATE_EN + description: update the WDT configuration registers + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: WDT_STG3 + description: "Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system." + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: WDT_STG2 + description: "Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system." + bitOffset: 25 + bitWidth: 2 + access: read-write + - name: WDT_STG1 + description: "Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system." + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: WDT_STG0 + description: "Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system." + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: WDT_EN + description: "When set, MWDT is enabled." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: WDTCONFIG1 + description: Watchdog timer prescaler register + addressOffset: 76 + size: 32 + resetValue: 65536 + fields: + - name: WDT_DIVCNT_RST + description: "When set, WDT 's clock divider counter will be reset." + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: WDT_CLK_PRESCALE + description: "MWDT clock prescaler value. MWDT clock period = 12.5 ns *\nTIMG_WDT_CLK_PRESCALE." + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: WDTCONFIG2 + description: Watchdog timer stage 0 timeout value + addressOffset: 80 + size: 32 + resetValue: 26000000 + fields: + - name: WDT_STG0_HOLD + description: "Stage 0 timeout value, in MWDT clock cycles." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG3 + description: Watchdog timer stage 1 timeout value + addressOffset: 84 + size: 32 + resetValue: 134217727 + fields: + - name: WDT_STG1_HOLD + description: "Stage 1 timeout value, in MWDT clock cycles." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG4 + description: Watchdog timer stage 2 timeout value + addressOffset: 88 + size: 32 + resetValue: 1048575 + fields: + - name: WDT_STG2_HOLD + description: "Stage 2 timeout value, in MWDT clock cycles." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG5 + description: Watchdog timer stage 3 timeout value + addressOffset: 92 + size: 32 + resetValue: 1048575 + fields: + - name: WDT_STG3_HOLD + description: "Stage 3 timeout value, in MWDT clock cycles." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTFEED + description: Write to feed the watchdog timer + addressOffset: 96 + size: 32 + fields: + - name: WDT_FEED + description: Write any value to feed the MWDT. (WO) + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: WDTWPROTECT + description: Watchdog write protect register + addressOffset: 100 + size: 32 + resetValue: 1356348065 + fields: + - name: WDT_WKEY + description: "If the register contains a different value than its reset value, write\nprotection is enabled." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RTCCALICFG + description: RTC calibration configure register + addressOffset: 104 + size: 32 + resetValue: 77824 + fields: + - name: RTC_CALI_START_CYCLING + description: Reserved + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RTC_CALI_CLK_SEL + description: "0:rtc slow clock. 1:clk_8m, 2:xtal_32k." + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: RTC_CALI_RDY + description: Reserved + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: RTC_CALI_MAX + description: Reserved + bitOffset: 16 + bitWidth: 15 + access: read-write + - name: RTC_CALI_START + description: Reserved + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RTCCALICFG1 + description: RTC calibration configure1 register + addressOffset: 108 + size: 32 + fields: + - name: RTC_CALI_CYCLING_DATA_VLD + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RTC_CALI_VALUE + description: Reserved + bitOffset: 7 + bitWidth: 25 + access: read-only + - register: + name: INT_ENA_TIMERS + description: Interrupt enable bits + addressOffset: 112 + size: 32 + fields: + - name: T0_INT_ENA + description: The interrupt enable bit for the TIMG_T0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: WDT_INT_ENA + description: The interrupt enable bit for the TIMG_WDT_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW_TIMERS + description: Raw interrupt status + addressOffset: 116 + size: 32 + fields: + - name: T0_INT_RAW + description: The raw interrupt status bit for the TIMG_T0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: WDT_INT_RAW + description: The raw interrupt status bit for the TIMG_WDT_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_ST_TIMERS + description: Masked interrupt status + addressOffset: 120 + size: 32 + fields: + - name: T0_INT_ST + description: The masked interrupt status bit for the TIMG_T0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: WDT_INT_ST + description: The masked interrupt status bit for the TIMG_WDT_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR_TIMERS + description: Interrupt clear bits + addressOffset: 124 + size: 32 + fields: + - name: T0_INT_CLR + description: Set this bit to clear the TIMG_T0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: WDT_INT_CLR + description: Set this bit to clear the TIMG_WDT_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: RTCCALICFG2 + description: Timer group calibration register + addressOffset: 128 + size: 32 + resetValue: 4294967192 + fields: + - name: RTC_CALI_TIMEOUT + description: RTC calibration timeout indicator + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RTC_CALI_TIMEOUT_RST_CNT + description: Cycles that release calibration timeout reset + bitOffset: 3 + bitWidth: 4 + access: read-write + - name: RTC_CALI_TIMEOUT_THRES + description: "Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered." + bitOffset: 7 + bitWidth: 25 + access: read-write + - register: + name: NTIMERS_DATE + description: Timer version control register + addressOffset: 248 + size: 32 + resetValue: 33579409 + fields: + - name: NTIMGS_DATE + description: Timer version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + name: REGCLK + description: Timer group clock gate register + addressOffset: 252 + size: 32 + resetValue: 1610612736 + fields: + - name: WDT_CLK_IS_ACTIVE + description: "enable WDT's clock" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TIMER_CLK_IS_ACTIVE + description: "enable Timer 30's clock" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software." + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: UART0 + description: UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + groupName: UART + baseAddress: 1610612736 + addressBlock: + - offset: 0 + size: 132 + usage: registers + interrupt: + - name: UART0 + value: 17 + registers: + - register: + name: FIFO + description: FIFO data register + addressOffset: 0 + size: 32 + fields: + - name: RXFIFO_RD_BYTE + description: UART 0 accesses FIFO via this register. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 4 + size: 32 + resetValue: 2 + fields: + - name: RXFIFO_FULL_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_EMPTY_INT_RAW + description: This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PARITY_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a parity error in the data. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FRM_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a data frame error . + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DSR_CHG_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CTS_CHG_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BRK_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RXFIFO_TOUT_INT_RAW + description: This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SW_XON_INT_RAW + description: This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SW_XOFF_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GLITCH_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_BRK_DONE_INT_RAW + description: "This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_BRK_IDLE_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RS485_PARITY_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RS485_FRM_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RS485_CLASH_INT_RAW + description: This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: AT_CMD_CHAR_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: WAKEUP_INT_RAW + description: This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 8 + size: 32 + fields: + - name: RXFIFO_FULL_INT_ST + description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_EMPTY_INT_ST + description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: PARITY_ERR_INT_ST + description: This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FRM_ERR_INT_ST + description: This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_ST + description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DSR_CHG_INT_ST + description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CTS_CHG_INT_ST + description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BRK_DET_INT_ST + description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: RXFIFO_TOUT_INT_ST + description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SW_XON_INT_ST + description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SW_XOFF_INT_ST + description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: GLITCH_DET_INT_ST + description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TX_BRK_DONE_INT_ST + description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: TX_BRK_IDLE_DONE_INT_ST + description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_ST + description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: RS485_PARITY_ERR_INT_ST + description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: RS485_FRM_ERR_INT_ST + description: This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: RS485_CLASH_INT_ST + description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: AT_CMD_CHAR_DET_INT_ST + description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: WAKEUP_INT_ST + description: This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + bitOffset: 19 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 12 + size: 32 + fields: + - name: RXFIFO_FULL_INT_ENA + description: This is the enable bit for rxfifo_full_int_st register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_EMPTY_INT_ENA + description: This is the enable bit for txfifo_empty_int_st register. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PARITY_ERR_INT_ENA + description: This is the enable bit for parity_err_int_st register. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FRM_ERR_INT_ENA + description: This is the enable bit for frm_err_int_st register. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_ENA + description: This is the enable bit for rxfifo_ovf_int_st register. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DSR_CHG_INT_ENA + description: This is the enable bit for dsr_chg_int_st register. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CTS_CHG_INT_ENA + description: This is the enable bit for cts_chg_int_st register. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BRK_DET_INT_ENA + description: This is the enable bit for brk_det_int_st register. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RXFIFO_TOUT_INT_ENA + description: This is the enable bit for rxfifo_tout_int_st register. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SW_XON_INT_ENA + description: This is the enable bit for sw_xon_int_st register. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SW_XOFF_INT_ENA + description: This is the enable bit for sw_xoff_int_st register. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GLITCH_DET_INT_ENA + description: This is the enable bit for glitch_det_int_st register. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_BRK_DONE_INT_ENA + description: This is the enable bit for tx_brk_done_int_st register. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_BRK_IDLE_DONE_INT_ENA + description: This is the enable bit for tx_brk_idle_done_int_st register. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_ENA + description: This is the enable bit for tx_done_int_st register. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RS485_PARITY_ERR_INT_ENA + description: This is the enable bit for rs485_parity_err_int_st register. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RS485_FRM_ERR_INT_ENA + description: This is the enable bit for rs485_parity_err_int_st register. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RS485_CLASH_INT_ENA + description: This is the enable bit for rs485_clash_int_st register. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: AT_CMD_CHAR_DET_INT_ENA + description: This is the enable bit for at_cmd_char_det_int_st register. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: WAKEUP_INT_ENA + description: This is the enable bit for uart_wakeup_int_st register. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 16 + size: 32 + fields: + - name: RXFIFO_FULL_INT_CLR + description: Set this bit to clear the rxfifo_full_int_raw interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TXFIFO_EMPTY_INT_CLR + description: Set this bit to clear txfifo_empty_int_raw interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: PARITY_ERR_INT_CLR + description: Set this bit to clear parity_err_int_raw interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: FRM_ERR_INT_CLR + description: Set this bit to clear frm_err_int_raw interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: RXFIFO_OVF_INT_CLR + description: Set this bit to clear rxfifo_ovf_int_raw interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: DSR_CHG_INT_CLR + description: Set this bit to clear the dsr_chg_int_raw interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CTS_CHG_INT_CLR + description: Set this bit to clear the cts_chg_int_raw interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: BRK_DET_INT_CLR + description: Set this bit to clear the brk_det_int_raw interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: RXFIFO_TOUT_INT_CLR + description: Set this bit to clear the rxfifo_tout_int_raw interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SW_XON_INT_CLR + description: Set this bit to clear the sw_xon_int_raw interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SW_XOFF_INT_CLR + description: Set this bit to clear the sw_xoff_int_raw interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: GLITCH_DET_INT_CLR + description: Set this bit to clear the glitch_det_int_raw interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TX_BRK_DONE_INT_CLR + description: Set this bit to clear the tx_brk_done_int_raw interrupt.. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: TX_BRK_IDLE_DONE_INT_CLR + description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: TX_DONE_INT_CLR + description: Set this bit to clear the tx_done_int_raw interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: RS485_PARITY_ERR_INT_CLR + description: Set this bit to clear the rs485_parity_err_int_raw interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: RS485_FRM_ERR_INT_CLR + description: Set this bit to clear the rs485_frm_err_int_raw interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: RS485_CLASH_INT_CLR + description: Set this bit to clear the rs485_clash_int_raw interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: AT_CMD_CHAR_DET_INT_CLR + description: Set this bit to clear the at_cmd_char_det_int_raw interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: WAKEUP_INT_CLR + description: Set this bit to clear the uart_wakeup_int_raw interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - register: + name: CLKDIV + description: Clock divider configuration + addressOffset: 20 + size: 32 + resetValue: 694 + fields: + - name: CLKDIV + description: The integral part of the frequency divider factor. + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: FRAG + description: The decimal part of the frequency divider factor. + bitOffset: 20 + bitWidth: 4 + access: read-write + - register: + name: RX_FILT + description: Rx Filter configuration + addressOffset: 24 + size: 32 + resetValue: 8 + fields: + - name: GLITCH_FILT + description: "when input pulse width is lower than this value, the pulse is ignored." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GLITCH_FILT_EN + description: Set this bit to enable Rx signal filter. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: STATUS + description: UART status register + addressOffset: 28 + size: 32 + resetValue: 3758145536 + fields: + - name: RXFIFO_CNT + description: Stores the byte number of valid data in Rx-FIFO. + bitOffset: 0 + bitWidth: 10 + access: read-only + - name: DSRN + description: The register represent the level value of the internal uart dsr signal. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: CTSN + description: This register represent the level value of the internal uart cts signal. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: RXD + description: This register represent the level value of the internal uart rxd signal. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TXFIFO_CNT + description: Stores the byte number of data in Tx-FIFO. + bitOffset: 16 + bitWidth: 10 + access: read-only + - name: DTRN + description: This bit represents the level of the internal uart dtr signal. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: RTSN + description: This bit represents the level of the internal uart rts signal. + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: TXD + description: This bit represents the level of the internal uart txd signal. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CONF0 + description: a + addressOffset: 32 + size: 32 + resetValue: 268435484 + fields: + - name: PARITY + description: This register is used to configure the parity check mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PARITY_EN + description: Set this bit to enable uart parity check. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BIT_NUM + description: This register is used to set the length of data. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: STOP_BIT_NUM + description: This register is used to set the length of stop bit. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: SW_RTS + description: This register is used to configure the software rts signal which is used in software flow control. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SW_DTR + description: This register is used to configure the software dtr signal which is used in software flow control. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TXD_BRK + description: Set this bit to enbale transmitter to send NULL when the process of sending data is done. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: IRDA_DPLX + description: Set this bit to enable IrDA loopback mode. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: IRDA_TX_EN + description: This is the start enable bit for IrDA transmitter. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: IRDA_WCTL + description: "1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: IRDA_TX_INV + description: Set this bit to invert the level of IrDA transmitter. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: IRDA_RX_INV + description: Set this bit to invert the level of IrDA receiver. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: LOOPBACK + description: Set this bit to enable uart loopback test mode. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TX_FLOW_EN + description: Set this bit to enable flow control function for transmitter. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: IRDA_EN + description: Set this bit to enable IrDA protocol. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RXFIFO_RST + description: Set this bit to reset the uart receive-FIFO. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: TXFIFO_RST + description: Set this bit to reset the uart transmit-FIFO. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RXD_INV + description: Set this bit to inverse the level value of uart rxd signal. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: CTS_INV + description: Set this bit to inverse the level value of uart cts signal. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: DSR_INV + description: Set this bit to inverse the level value of uart dsr signal. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: TXD_INV + description: Set this bit to inverse the level value of uart txd signal. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RTS_INV + description: Set this bit to inverse the level value of uart rts signal. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: DTR_INV + description: Set this bit to inverse the level value of uart dtr signal. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: ERR_WR_MASK + description: "1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: AUTOBAUD_EN + description: This is the enable bit for detecting baudrate. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: MEM_CLK_EN + description: UART memory clock gate enable signal. + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: CONF1 + description: Configuration register 1 + addressOffset: 36 + size: 32 + resetValue: 49248 + fields: + - name: RXFIFO_FULL_THRHD + description: It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: TXFIFO_EMPTY_THRHD + description: It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + bitOffset: 9 + bitWidth: 9 + access: read-write + - name: DIS_RX_DAT_OVF + description: Disable UART Rx data overflow detect. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RX_TOUT_FLOW_DIS + description: Set this bit to stop accumulating idle_cnt when hardware flow control works. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RX_FLOW_EN + description: This is the flow enable bit for UART receiver. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: RX_TOUT_EN + description: "This is the enble bit for uart receiver's timeout function." + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + name: LOWPULSE + description: Autobaud minimum low pulse duration register + addressOffset: 40 + size: 32 + resetValue: 4095 + fields: + - name: MIN_CNT + description: This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process. + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: HIGHPULSE + description: Autobaud minimum high pulse duration register + addressOffset: 44 + size: 32 + resetValue: 4095 + fields: + - name: MIN_CNT + description: This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process. + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: RXD_CNT + description: Autobaud edge change count register + addressOffset: 48 + size: 32 + fields: + - name: RXD_EDGE_CNT + description: This register stores the count of rxd edge change. It is used in baud rate-detect process. + bitOffset: 0 + bitWidth: 10 + access: read-only + - register: + name: FLOW_CONF + description: Software flow-control configuration + addressOffset: 52 + size: 32 + fields: + - name: SW_FLOW_CON_EN + description: Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: XONOFF_DEL + description: Set this bit to remove flow control char from the received data. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FORCE_XON + description: Set this bit to enable the transmitter to go on sending data. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FORCE_XOFF + description: Set this bit to stop the transmitter from sending data. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SEND_XON + description: Set this bit to send Xon char. It is cleared by hardware automatically. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SEND_XOFF + description: Set this bit to send Xoff char. It is cleared by hardware automatically. + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: SLEEP_CONF + description: Sleep-mode configuration + addressOffset: 56 + size: 32 + resetValue: 240 + fields: + - name: ACTIVE_THRESHOLD + description: The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: SWFC_CONF0 + description: Software flow-control character configuration + addressOffset: 60 + size: 32 + resetValue: 9952 + fields: + - name: XOFF_THRESHOLD + description: "When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: XOFF_CHAR + description: This register stores the Xoff flow control char. + bitOffset: 9 + bitWidth: 8 + access: read-write + - register: + name: SWFC_CONF1 + description: Software flow-control character configuration + addressOffset: 64 + size: 32 + resetValue: 8704 + fields: + - name: XON_THRESHOLD + description: "When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: XON_CHAR + description: This register stores the Xon flow control char. + bitOffset: 9 + bitWidth: 8 + access: read-write + - register: + name: TXBRK_CONF + description: Tx Break character configuration + addressOffset: 68 + size: 32 + resetValue: 10 + fields: + - name: TX_BRK_NUM + description: This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: IDLE_CONF + description: Frame-end idle configuration + addressOffset: 72 + size: 32 + resetValue: 262400 + fields: + - name: RX_IDLE_THRHD + description: It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: TX_IDLE_NUM + description: This register is used to configure the duration time between transfers. + bitOffset: 10 + bitWidth: 10 + access: read-write + - register: + name: RS485_CONF + description: RS485 mode configuration + addressOffset: 76 + size: 32 + fields: + - name: RS485_EN + description: Set this bit to choose the rs485 mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DL0_EN + description: Set this bit to delay the stop bit by 1 bit. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DL1_EN + description: Set this bit to delay the stop bit by 1 bit. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RS485TX_RX_EN + description: Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RS485RXBY_TX_EN + description: "1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RS485_RX_DLY_NUM + description: "This register is used to delay the receiver's internal data signal." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RS485_TX_DLY_NUM + description: "This register is used to delay the transmitter's internal data signal." + bitOffset: 6 + bitWidth: 4 + access: read-write + - register: + name: AT_CMD_PRECNT + description: Pre-sequence timing configuration + addressOffset: 80 + size: 32 + resetValue: 2305 + fields: + - name: PRE_IDLE_NUM + description: This register is used to configure the idle duration time before the first at_cmd is received by receiver. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_POSTCNT + description: Post-sequence timing configuration + addressOffset: 84 + size: 32 + resetValue: 2305 + fields: + - name: POST_IDLE_NUM + description: This register is used to configure the duration time between the last at_cmd and the next data. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_GAPTOUT + description: Timeout configuration + addressOffset: 88 + size: 32 + resetValue: 11 + fields: + - name: RX_GAP_TOUT + description: This register is used to configure the duration time between the at_cmd chars. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_CHAR + description: AT escape sequence detection configuration + addressOffset: 92 + size: 32 + resetValue: 811 + fields: + - name: AT_CMD_CHAR + description: This register is used to configure the content of at_cmd char. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CHAR_NUM + description: This register is used to configure the num of continuous at_cmd chars received by receiver. + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: MEM_CONF + description: UART threshold and allocation configuration + addressOffset: 96 + size: 32 + resetValue: 655378 + fields: + - name: RX_SIZE + description: This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: TX_SIZE + description: This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes. + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: RX_FLOW_THRHD + description: This register is used to configure the maximum amount of data that can be received when hardware flow control works. + bitOffset: 7 + bitWidth: 9 + access: read-write + - name: RX_TOUT_THRHD + description: This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + bitOffset: 16 + bitWidth: 10 + access: read-write + - name: MEM_FORCE_PD + description: Set this bit to force power down UART memory. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PU + description: Set this bit to force power up UART memory. + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: MEM_TX_STATUS + description: Tx-FIFO write and read offset address. + addressOffset: 100 + size: 32 + fields: + - name: APB_TX_WADDR + description: This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB. + bitOffset: 0 + bitWidth: 10 + access: read-only + - name: TX_RADDR + description: This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl. + bitOffset: 11 + bitWidth: 10 + access: read-only + - register: + name: MEM_RX_STATUS + description: Rx-FIFO write and read offset address. + addressOffset: 104 + size: 32 + resetValue: 524544 + fields: + - name: APB_RX_RADDR + description: "This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180." + bitOffset: 0 + bitWidth: 10 + access: read-only + - name: RX_WADDR + description: "This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180." + bitOffset: 11 + bitWidth: 10 + access: read-only + - register: + name: FSM_STATUS + description: UART transmit and receive status. + addressOffset: 108 + size: 32 + fields: + - name: ST_URX_OUT + description: This is the status register of receiver. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: ST_UTX_OUT + description: This is the status register of transmitter. + bitOffset: 4 + bitWidth: 4 + access: read-only + - register: + name: POSPULSE + description: Autobaud high pulse register + addressOffset: 112 + size: 32 + resetValue: 4095 + fields: + - name: POSEDGE_MIN_CNT + description: This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process. + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: NEGPULSE + description: Autobaud low pulse register + addressOffset: 116 + size: 32 + resetValue: 4095 + fields: + - name: NEGEDGE_MIN_CNT + description: This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process. + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: CLK_CONF + description: UART core clock configuration + addressOffset: 120 + size: 32 + resetValue: 57675776 + fields: + - name: SCLK_DIV_B + description: The denominator of the frequency divider factor. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_A + description: The numerator of the frequency divider factor. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_NUM + description: The integral part of the frequency divider factor. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: SCLK_SEL + description: "UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: SCLK_EN + description: Set this bit to enable UART Tx/Rx clock. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RST_CORE + description: "Write 1 then write 0 to this bit, reset UART Tx/Rx." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TX_SCLK_EN + description: Set this bit to enable UART Tx clock. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: RX_SCLK_EN + description: Set this bit to enable UART Rx clock. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TX_RST_CORE + description: "Write 1 then write 0 to this bit, reset UART Tx." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RX_RST_CORE + description: "Write 1 then write 0 to this bit, reset UART Rx." + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: UART Version register + addressOffset: 124 + size: 32 + resetValue: 33587824 + fields: + - name: DATE + description: This is the version register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ID + description: UART ID register + addressOffset: 128 + size: 32 + resetValue: 1073743104 + fields: + - name: ID + description: This register is used to configure the uart_id. + bitOffset: 0 + bitWidth: 30 + access: read-write + - name: HIGH_SPEED + description: "This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: REG_UPDATE + description: Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: UART1 + description: UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + baseAddress: 1610678272 + interrupt: + - name: UART1 + value: 18 + derivedFrom: UART0 + - name: XTS_AES + description: XTS-AES-128 Flash Encryption + groupName: XTS_AES + baseAddress: 1611448320 + addressBlock: + - offset: 0 + size: 48 + usage: registers + registers: + - register: + dim: 4 + dimIncrement: 4 + name: "PLAIN_MEM[%s]" + description: The memory that stores plaintext + addressOffset: 0 + size: 32 + - register: + name: LINESIZE + description: XTS-AES line-size register + addressOffset: 64 + size: 32 + fields: + - name: LINESIZE + description: "This bit stores the line size parameter. 0: 16Byte, 1: 32Byte." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DESTINATION + description: XTS-AES destination register + addressOffset: 68 + size: 32 + fields: + - name: DESTINATION + description: "This bit stores the destination. 0: flash(default). 1: reserved." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: PHYSICAL_ADDRESS + description: XTS-AES physical address register + addressOffset: 72 + size: 32 + fields: + - name: PHYSICAL_ADDRESS + description: "Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes." + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: TRIGGER + description: XTS-AES trigger register + addressOffset: 76 + size: 32 + fields: + - name: TRIGGER + description: Set this bit to start manual encryption calculation + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: RELEASE + description: XTS-AES release register + addressOffset: 80 + size: 32 + fields: + - name: RELEASE + description: "Set this bit to release the manual encrypted result, after that the result will be visible to spi" + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: DESTROY + description: XTS-AES destroy register + addressOffset: 84 + size: 32 + fields: + - name: DESTROY + description: Set this bit to destroy XTS-AES result. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: STATE + description: XTS-AES status register + addressOffset: 88 + size: 32 + fields: + - name: STATE + description: "Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means the encrypted result is generated but not visible to mspi. USE means that the encrypted result is visible to mspi." + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: DATE + description: XTS-AES version control register + addressOffset: 92 + size: 32 + resetValue: 538969635 + fields: + - name: DATE + description: Those bits stores the version information of XTS-AES. + bitOffset: 0 + bitWidth: 30 + access: read-write diff --git a/esp32c3/svd/esp32c3.svd.yaml b/esp32c3/svd/esp32c3.svd.yaml new file mode 100644 index 0000000000..777257e0c2 --- /dev/null +++ b/esp32c3/svd/esp32c3.svd.yaml @@ -0,0 +1,24629 @@ +--- +vendor: "ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD." +vendorID: ESPRESSIF +name: ESP32-C3 +series: ESP32 C-Series +version: "18" +description: 32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE) +licenseText: "Copyright 2024 Espressif Systems (Shanghai) PTE LTD\n\n Licensed under the Apache License, Version 2.0 (the \"License\");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an \"AS IS\" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License." +cpu: + name: RV32IMC + revision: r0p0 + endian: little + mpuPresent: false + fpuPresent: false + nvicPrioBits: 0 + vendorSystickConfig: false +addressUnitBits: 32 +width: 32 +resetValue: 0 +resetMask: 4294967295 +peripherals: + - name: AES + description: AES (Advanced Encryption Standard) Accelerator + groupName: AES + baseAddress: 1610850304 + addressBlock: + - offset: 0 + size: 188 + usage: registers + interrupt: + - name: AES + value: 48 + registers: + - register: + name: KEY_0 + description: Key material key_0 configure register + addressOffset: 0 + size: 32 + fields: + - name: KEY_0 + description: This bits stores key_0 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_1 + description: Key material key_1 configure register + addressOffset: 4 + size: 32 + fields: + - name: KEY_1 + description: This bits stores key_1 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_2 + description: Key material key_2 configure register + addressOffset: 8 + size: 32 + fields: + - name: KEY_2 + description: This bits stores key_2 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_3 + description: Key material key_3 configure register + addressOffset: 12 + size: 32 + fields: + - name: KEY_3 + description: This bits stores key_3 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_4 + description: Key material key_4 configure register + addressOffset: 16 + size: 32 + fields: + - name: KEY_4 + description: This bits stores key_4 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_5 + description: Key material key_5 configure register + addressOffset: 20 + size: 32 + fields: + - name: KEY_5 + description: This bits stores key_5 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_6 + description: Key material key_6 configure register + addressOffset: 24 + size: 32 + fields: + - name: KEY_6 + description: This bits stores key_6 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_7 + description: Key material key_7 configure register + addressOffset: 28 + size: 32 + fields: + - name: KEY_7 + description: This bits stores key_7 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_IN_0 + description: source text material text_in_0 configure register + addressOffset: 32 + size: 32 + fields: + - name: TEXT_IN_0 + description: This bits stores text_in_0 that is a part of source text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_IN_1 + description: source text material text_in_1 configure register + addressOffset: 36 + size: 32 + fields: + - name: TEXT_IN_1 + description: This bits stores text_in_1 that is a part of source text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_IN_2 + description: source text material text_in_2 configure register + addressOffset: 40 + size: 32 + fields: + - name: TEXT_IN_2 + description: This bits stores text_in_2 that is a part of source text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_IN_3 + description: source text material text_in_3 configure register + addressOffset: 44 + size: 32 + fields: + - name: TEXT_IN_3 + description: This bits stores text_in_3 that is a part of source text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_OUT_0 + description: result text material text_out_0 configure register + addressOffset: 48 + size: 32 + fields: + - name: TEXT_OUT_0 + description: This bits stores text_out_0 that is a part of result text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_OUT_1 + description: result text material text_out_1 configure register + addressOffset: 52 + size: 32 + fields: + - name: TEXT_OUT_1 + description: This bits stores text_out_1 that is a part of result text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_OUT_2 + description: result text material text_out_2 configure register + addressOffset: 56 + size: 32 + fields: + - name: TEXT_OUT_2 + description: This bits stores text_out_2 that is a part of result text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_OUT_3 + description: result text material text_out_3 configure register + addressOffset: 60 + size: 32 + fields: + - name: TEXT_OUT_3 + description: This bits stores text_out_3 that is a part of result text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: MODE + description: AES Mode register + addressOffset: 64 + size: 32 + fields: + - name: MODE + description: "This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256." + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: ENDIAN + description: AES Endian configure register + addressOffset: 68 + size: 32 + fields: + - name: ENDIAN + description: "endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out endian or out_stream endian" + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: TRIGGER + description: AES trigger register + addressOffset: 72 + size: 32 + fields: + - name: TRIGGER + description: Set this bit to start AES calculation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: STATE + description: AES state register + addressOffset: 76 + size: 32 + fields: + - name: STATE + description: "Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done." + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + dim: 4 + dimIncrement: 4 + name: "IV_MEM[%s]" + description: The memory that stores initialization vector + addressOffset: 80 + size: 32 + - register: + dim: 4 + dimIncrement: 4 + name: "H_MEM[%s]" + description: The memory that stores GCM hash subkey + addressOffset: 96 + size: 32 + - register: + dim: 4 + dimIncrement: 4 + name: "J0_MEM[%s]" + description: The memory that stores J0 + addressOffset: 112 + size: 32 + - register: + dim: 4 + dimIncrement: 4 + name: "T0_MEM[%s]" + description: The memory that stores T0 + addressOffset: 128 + size: 32 + - register: + name: DMA_ENABLE + description: DMA-AES working mode register + addressOffset: 144 + size: 32 + fields: + - name: DMA_ENABLE + description: "1'b0: typical AES working mode, 1'b1: DMA-AES working mode." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: BLOCK_MODE + description: AES cipher block mode register + addressOffset: 148 + size: 32 + fields: + - name: BLOCK_MODE + description: "Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved." + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: BLOCK_NUM + description: AES block number register + addressOffset: 152 + size: 32 + fields: + - name: BLOCK_NUM + description: Those bits stores the number of Plaintext/ciphertext block. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: INC_SEL + description: Standard incrementing function configure register + addressOffset: 156 + size: 32 + fields: + - name: INC_SEL + description: "This bit decides the standard incrementing function. 0: INC32. 1: INC128." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: AAD_BLOCK_NUM + description: Additional Authential Data block number register + addressOffset: 160 + size: 32 + fields: + - name: AAD_BLOCK_NUM + description: Those bits stores the number of AAD block. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REMAINDER_BIT_NUM + description: AES remainder bit number register + addressOffset: 164 + size: 32 + fields: + - name: REMAINDER_BIT_NUM + description: Those bits stores the number of remainder bit. + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: CONTINUE + description: AES continue register + addressOffset: 168 + size: 32 + fields: + - name: CONTINUE + description: Set this bit to continue GCM operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: INT_CLEAR + description: AES Interrupt clear register + addressOffset: 172 + size: 32 + fields: + - name: INT_CLEAR + description: Set this bit to clear the AES interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + description: AES Interrupt enable register + addressOffset: 176 + size: 32 + fields: + - name: INT_ENA + description: Set this bit to enable interrupt that occurs when DMA-AES calculation is done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: AES version control register + addressOffset: 180 + size: 32 + resetValue: 538513936 + fields: + - name: DATE + description: This bits stores the version information of AES. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: DMA_EXIT + description: AES-DMA exit config + addressOffset: 184 + size: 32 + fields: + - name: DMA_EXIT + description: "Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer." + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: APB_CTRL + description: APB (Advanced Peripheral Bus) Controller + groupName: APB_CTRL + baseAddress: 1610768384 + addressBlock: + - offset: 0 + size: 160 + usage: registers + interrupt: + - name: APB_CTRL + value: 14 + registers: + - register: + name: SYSCLK_CONF + description: APB_CTRL_SYSCLK_CONF_REG + addressOffset: 0 + size: 32 + resetValue: 1 + fields: + - name: PRE_DIV_CNT + description: reg_pre_div_cnt + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: CLK_320M_EN + description: reg_clk_320m_en + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: reg_clk_en + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RST_TICK_CNT + description: reg_rst_tick_cnt + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: TICK_CONF + description: APB_CTRL_TICK_CONF_REG + addressOffset: 4 + size: 32 + resetValue: 67367 + fields: + - name: XTAL_TICK_NUM + description: reg_xtal_tick_num + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CK8M_TICK_NUM + description: reg_ck8m_tick_num + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: TICK_ENABLE + description: reg_tick_enable + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: CLK_OUT_EN + description: APB_CTRL_CLK_OUT_EN_REG + addressOffset: 8 + size: 32 + resetValue: 2047 + fields: + - name: CLK20_OEN + description: reg_clk20_oen + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CLK22_OEN + description: reg_clk22_oen + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CLK44_OEN + description: reg_clk44_oen + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CLK_BB_OEN + description: reg_clk_bb_oen + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CLK80_OEN + description: reg_clk80_oen + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CLK160_OEN + description: reg_clk160_oen + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CLK_320M_OEN + description: reg_clk_320m_oen + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CLK_ADC_INF_OEN + description: reg_clk_adc_inf_oen + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_DAC_CPU_OEN + description: reg_clk_dac_cpu_oen + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CLK40X_BB_OEN + description: reg_clk40x_bb_oen + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CLK_XTAL_OEN + description: reg_clk_xtal_oen + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: WIFI_BB_CFG + description: APB_CTRL_WIFI_BB_CFG_REG + addressOffset: 12 + size: 32 + fields: + - name: WIFI_BB_CFG + description: reg_wifi_bb_cfg + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WIFI_BB_CFG_2 + description: APB_CTRL_WIFI_BB_CFG_2_REG + addressOffset: 16 + size: 32 + fields: + - name: WIFI_BB_CFG_2 + description: reg_wifi_bb_cfg_2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WIFI_CLK_EN + description: APB_CTRL_WIFI_CLK_EN_REG + addressOffset: 20 + size: 32 + resetValue: 4294762544 + fields: + - name: WIFI_CLK_EN + description: reg_wifi_clk_en + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WIFI_RST_EN + description: APB_CTRL_WIFI_RST_EN_REG + addressOffset: 24 + size: 32 + fields: + - name: WIFI_RST + description: reg_wifi_rst + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HOST_INF_SEL + description: APB_CTRL_HOST_INF_SEL_REG + addressOffset: 28 + size: 32 + fields: + - name: PERI_IO_SWAP + description: reg_peri_io_swap + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: EXT_MEM_PMS_LOCK + description: APB_CTRL_EXT_MEM_PMS_LOCK_REG + addressOffset: 32 + size: 32 + fields: + - name: EXT_MEM_PMS_LOCK + description: reg_ext_mem_pms_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: FLASH_ACE0_ATTR + description: APB_CTRL_FLASH_ACE0_ATTR_REG + addressOffset: 40 + size: 32 + resetValue: 3 + fields: + - name: FLASH_ACE0_ATTR + description: reg_flash_ace0_attr + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: FLASH_ACE1_ATTR + description: APB_CTRL_FLASH_ACE1_ATTR_REG + addressOffset: 44 + size: 32 + resetValue: 3 + fields: + - name: FLASH_ACE1_ATTR + description: reg_flash_ace1_attr + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: FLASH_ACE2_ATTR + description: APB_CTRL_FLASH_ACE2_ATTR_REG + addressOffset: 48 + size: 32 + resetValue: 3 + fields: + - name: FLASH_ACE2_ATTR + description: reg_flash_ace2_attr + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: FLASH_ACE3_ATTR + description: APB_CTRL_FLASH_ACE3_ATTR_REG + addressOffset: 52 + size: 32 + resetValue: 3 + fields: + - name: FLASH_ACE3_ATTR + description: reg_flash_ace3_attr + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: FLASH_ACE0_ADDR + description: APB_CTRL_FLASH_ACE0_ADDR_REG + addressOffset: 56 + size: 32 + fields: + - name: S + description: reg_flash_ace0_addr_s + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FLASH_ACE1_ADDR + description: APB_CTRL_FLASH_ACE1_ADDR_REG + addressOffset: 60 + size: 32 + resetValue: 4194304 + fields: + - name: S + description: reg_flash_ace1_addr_s + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FLASH_ACE2_ADDR + description: APB_CTRL_FLASH_ACE2_ADDR_REG + addressOffset: 64 + size: 32 + resetValue: 8388608 + fields: + - name: S + description: reg_flash_ace2_addr_s + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FLASH_ACE3_ADDR + description: APB_CTRL_FLASH_ACE3_ADDR_REG + addressOffset: 68 + size: 32 + resetValue: 12582912 + fields: + - name: S + description: reg_flash_ace3_addr_s + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FLASH_ACE0_SIZE + description: APB_CTRL_FLASH_ACE0_SIZE_REG + addressOffset: 72 + size: 32 + resetValue: 1024 + fields: + - name: FLASH_ACE0_SIZE + description: reg_flash_ace0_size + bitOffset: 0 + bitWidth: 13 + access: read-write + - register: + name: FLASH_ACE1_SIZE + description: APB_CTRL_FLASH_ACE1_SIZE_REG + addressOffset: 76 + size: 32 + resetValue: 1024 + fields: + - name: FLASH_ACE1_SIZE + description: reg_flash_ace1_size + bitOffset: 0 + bitWidth: 13 + access: read-write + - register: + name: FLASH_ACE2_SIZE + description: APB_CTRL_FLASH_ACE2_SIZE_REG + addressOffset: 80 + size: 32 + resetValue: 1024 + fields: + - name: FLASH_ACE2_SIZE + description: reg_flash_ace2_size + bitOffset: 0 + bitWidth: 13 + access: read-write + - register: + name: FLASH_ACE3_SIZE + description: APB_CTRL_FLASH_ACE3_SIZE_REG + addressOffset: 84 + size: 32 + resetValue: 1024 + fields: + - name: FLASH_ACE3_SIZE + description: reg_flash_ace3_size + bitOffset: 0 + bitWidth: 13 + access: read-write + - register: + name: SPI_MEM_PMS_CTRL + description: APB_CTRL_SPI_MEM_PMS_CTRL_REG + addressOffset: 136 + size: 32 + fields: + - name: SPI_MEM_REJECT_INT + description: reg_spi_mem_reject_int + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_MEM_REJECT_CLR + description: reg_spi_mem_reject_clr + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SPI_MEM_REJECT_CDE + description: reg_spi_mem_reject_cde + bitOffset: 2 + bitWidth: 5 + access: read-only + - register: + name: SPI_MEM_REJECT_ADDR + description: APB_CTRL_SPI_MEM_REJECT_ADDR_REG + addressOffset: 140 + size: 32 + fields: + - name: SPI_MEM_REJECT_ADDR + description: reg_spi_mem_reject_addr + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SDIO_CTRL + description: APB_CTRL_SDIO_CTRL_REG + addressOffset: 144 + size: 32 + fields: + - name: SDIO_WIN_ACCESS_EN + description: reg_sdio_win_access_en + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: REDCY_SIG0 + description: APB_CTRL_REDCY_SIG0_REG_REG + addressOffset: 148 + size: 32 + fields: + - name: REDCY_SIG0 + description: reg_redcy_sig0 + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: REDCY_ANDOR + description: reg_redcy_andor + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: REDCY_SIG1 + description: APB_CTRL_REDCY_SIG1_REG_REG + addressOffset: 152 + size: 32 + fields: + - name: REDCY_SIG1 + description: reg_redcy_sig1 + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: REDCY_NANDOR + description: reg_redcy_nandor + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: FRONT_END_MEM_PD + description: APB_CTRL_FRONT_END_MEM_PD_REG + addressOffset: 156 + size: 32 + resetValue: 21 + fields: + - name: AGC_MEM_FORCE_PU + description: reg_agc_mem_force_pu + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: AGC_MEM_FORCE_PD + description: reg_agc_mem_force_pd + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PBUS_MEM_FORCE_PU + description: reg_pbus_mem_force_pu + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PBUS_MEM_FORCE_PD + description: reg_pbus_mem_force_pd + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DC_MEM_FORCE_PU + description: reg_dc_mem_force_pu + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DC_MEM_FORCE_PD + description: reg_dc_mem_force_pd + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: RETENTION_CTRL + description: APB_CTRL_RETENTION_CTRL_REG + addressOffset: 160 + size: 32 + fields: + - name: RETENTION_LINK_ADDR + description: reg_retention_link_addr + bitOffset: 0 + bitWidth: 27 + access: read-write + - name: NOBYPASS_CPU_ISO_RST + description: reg_nobypass_cpu_iso_rst + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: CLKGATE_FORCE_ON + description: APB_CTRL_CLKGATE_FORCE_ON_REG + addressOffset: 164 + size: 32 + resetValue: 63 + fields: + - name: ROM_CLKGATE_FORCE_ON + description: reg_rom_clkgate_force_on + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SRAM_CLKGATE_FORCE_ON + description: reg_sram_clkgate_force_on + bitOffset: 2 + bitWidth: 4 + access: read-write + - register: + name: MEM_POWER_DOWN + description: APB_CTRL_MEM_POWER_DOWN_REG + addressOffset: 168 + size: 32 + fields: + - name: ROM_POWER_DOWN + description: reg_rom_power_down + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SRAM_POWER_DOWN + description: reg_sram_power_down + bitOffset: 2 + bitWidth: 4 + access: read-write + - register: + name: MEM_POWER_UP + description: APB_CTRL_MEM_POWER_UP_REG + addressOffset: 172 + size: 32 + resetValue: 63 + fields: + - name: ROM_POWER_UP + description: reg_rom_power_up + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SRAM_POWER_UP + description: reg_sram_power_up + bitOffset: 2 + bitWidth: 4 + access: read-write + - register: + name: RND_DATA + description: APB_CTRL_RND_DATA_REG + addressOffset: 176 + size: 32 + fields: + - name: RND_DATA + description: reg_rnd_data + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PERI_BACKUP_CONFIG + description: APB_CTRL_PERI_BACKUP_CONFIG_REG_REG + addressOffset: 180 + size: 32 + resetValue: 25728 + fields: + - name: PERI_BACKUP_FLOW_ERR + description: reg_peri_backup_flow_err + bitOffset: 1 + bitWidth: 2 + access: read-only + - name: PERI_BACKUP_BURST_LIMIT + description: reg_peri_backup_burst_limit + bitOffset: 4 + bitWidth: 5 + access: read-write + - name: PERI_BACKUP_TOUT_THRES + description: reg_peri_backup_tout_thres + bitOffset: 9 + bitWidth: 10 + access: read-write + - name: PERI_BACKUP_SIZE + description: reg_peri_backup_size + bitOffset: 19 + bitWidth: 10 + access: read-write + - name: PERI_BACKUP_START + description: reg_peri_backup_start + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: PERI_BACKUP_TO_MEM + description: reg_peri_backup_to_mem + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: PERI_BACKUP_ENA + description: reg_peri_backup_ena + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: PERI_BACKUP_APB_ADDR + description: APB_CTRL_PERI_BACKUP_APB_ADDR_REG_REG + addressOffset: 184 + size: 32 + fields: + - name: BACKUP_APB_START_ADDR + description: reg_backup_apb_start_addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PERI_BACKUP_MEM_ADDR + description: APB_CTRL_PERI_BACKUP_MEM_ADDR_REG_REG + addressOffset: 188 + size: 32 + fields: + - name: BACKUP_MEM_START_ADDR + description: reg_backup_mem_start_addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PERI_BACKUP_INT_RAW + description: APB_CTRL_PERI_BACKUP_INT_RAW_REG + addressOffset: 192 + size: 32 + fields: + - name: PERI_BACKUP_DONE_INT_RAW + description: reg_peri_backup_done_int_raw + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PERI_BACKUP_ERR_INT_RAW + description: reg_peri_backup_err_int_raw + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: PERI_BACKUP_INT_ST + description: APB_CTRL_PERI_BACKUP_INT_ST_REG + addressOffset: 196 + size: 32 + fields: + - name: PERI_BACKUP_DONE_INT_ST + description: reg_peri_backup_done_int_st + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PERI_BACKUP_ERR_INT_ST + description: reg_peri_backup_err_int_st + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: PERI_BACKUP_INT_ENA + description: APB_CTRL_PERI_BACKUP_INT_ENA_REG + addressOffset: 200 + size: 32 + fields: + - name: PERI_BACKUP_DONE_INT_ENA + description: reg_peri_backup_done_int_ena + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PERI_BACKUP_ERR_INT_ENA + description: reg_peri_backup_err_int_ena + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: PERI_BACKUP_INT_CLR + description: APB_CTRL_PERI_BACKUP_INT_CLR_REG + addressOffset: 208 + size: 32 + fields: + - name: PERI_BACKUP_DONE_INT_CLR + description: reg_peri_backup_done_int_clr + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: PERI_BACKUP_ERR_INT_CLR + description: reg_peri_backup_err_int_clr + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: DATE + description: APB_CTRL_DATE_REG + addressOffset: 1020 + size: 32 + resetValue: 33583632 + fields: + - name: DATE + description: reg_dateVersion control + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: APB_SARADC + description: SAR (Successive Approximation Register) Analog-to-Digital Converter + groupName: APB_SARADC + baseAddress: 1610874880 + addressBlock: + - offset: 0 + size: 104 + usage: registers + interrupt: + - name: APB_ADC + value: 43 + registers: + - register: + name: CTRL + description: digital saradc configure register + addressOffset: 0 + size: 32 + resetValue: 1073971776 + fields: + - name: SARADC_START_FORCE + description: select software enable saradc sample + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SARADC_START + description: software enable saradc sample + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SARADC_SAR_CLK_GATED + description: SAR clock gated + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SARADC_SAR_CLK_DIV + description: SAR clock divider + bitOffset: 7 + bitWidth: 8 + access: read-write + - name: SARADC_SAR_PATT_LEN + description: 0 ~ 15 means length 1 ~ 16 + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: SARADC_SAR_PATT_P_CLEAR + description: clear the pointer of pattern table for DIG ADC1 CTRL + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SARADC_XPD_SAR_FORCE + description: force option to xpd sar blocks + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: SARADC_WAIT_ARB_CYCLE + description: wait arbit signal stable after sar_done + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CTRL2 + description: digital saradc configure register + addressOffset: 4 + size: 32 + resetValue: 41470 + fields: + - name: SARADC_MEAS_NUM_LIMIT + description: enable max meas num + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SARADC_MAX_MEAS_NUM + description: max conversion number + bitOffset: 1 + bitWidth: 8 + access: read-write + - name: SARADC_SAR1_INV + description: "1: data to DIG ADC1 CTRL is inverted, otherwise not" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SARADC_SAR2_INV + description: "1: data to DIG ADC2 CTRL is inverted, otherwise not" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SARADC_TIMER_TARGET + description: to set saradc timer target + bitOffset: 12 + bitWidth: 12 + access: read-write + - name: SARADC_TIMER_EN + description: to enable saradc timer trigger + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: FILTER_CTRL1 + description: digital saradc configure register + addressOffset: 8 + size: 32 + fields: + - name: APB_SARADC_FILTER_FACTOR1 + description: Factor of saradc filter1 + bitOffset: 26 + bitWidth: 3 + access: read-write + - name: APB_SARADC_FILTER_FACTOR0 + description: Factor of saradc filter0 + bitOffset: 29 + bitWidth: 3 + access: read-write + - register: + name: FSM_WAIT + description: digital saradc configure register + addressOffset: 12 + size: 32 + resetValue: 16713736 + fields: + - name: SARADC_XPD_WAIT + description: saradc_xpd_wait + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SARADC_RSTB_WAIT + description: saradc_rstb_wait + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SARADC_STANDBY_WAIT + description: saradc_standby_wait + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: SAR1_STATUS + description: digital saradc configure register + addressOffset: 16 + size: 32 + fields: + - name: SARADC_SAR1_STATUS + description: saradc1 status about data and channel + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SAR2_STATUS + description: digital saradc configure register + addressOffset: 20 + size: 32 + fields: + - name: SARADC_SAR2_STATUS + description: saradc2 status about data and channel + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SAR_PATT_TAB1 + description: digital saradc configure register + addressOffset: 24 + size: 32 + fields: + - name: SARADC_SAR_PATT_TAB1 + description: item 0 ~ 3 for pattern table 1 (each item one byte) + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: SAR_PATT_TAB2 + description: digital saradc configure register + addressOffset: 28 + size: 32 + fields: + - name: SARADC_SAR_PATT_TAB2 + description: Item 4 ~ 7 for pattern table 1 (each item one byte) + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: ONETIME_SAMPLE + description: digital saradc configure register + addressOffset: 32 + size: 32 + resetValue: 436207616 + fields: + - name: SARADC_ONETIME_ATTEN + description: configure onetime atten + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: SARADC_ONETIME_CHANNEL + description: configure onetime channel + bitOffset: 25 + bitWidth: 4 + access: read-write + - name: SARADC_ONETIME_START + description: trigger adc onetime sample + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SARADC2_ONETIME_SAMPLE + description: enable adc2 onetime sample + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SARADC1_ONETIME_SAMPLE + description: enable adc1 onetime sample + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: ARB_CTRL + description: digital saradc configure register + addressOffset: 36 + size: 32 + resetValue: 2304 + fields: + - name: ADC_ARB_APB_FORCE + description: adc2 arbiter force to enableapb controller + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ADC_ARB_RTC_FORCE + description: adc2 arbiter force to enable rtc controller + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ADC_ARB_WIFI_FORCE + description: adc2 arbiter force to enable wifi controller + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ADC_ARB_GRANT_FORCE + description: adc2 arbiter force grant + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: ADC_ARB_APB_PRIORITY + description: Set adc2 arbiterapb priority + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: ADC_ARB_RTC_PRIORITY + description: Set adc2 arbiter rtc priority + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: ADC_ARB_WIFI_PRIORITY + description: Set adc2 arbiter wifi priority + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: ADC_ARB_FIX_PRIORITY + description: adc2 arbiter uses fixed priority + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: FILTER_CTRL0 + description: digital saradc configure register + addressOffset: 40 + size: 32 + resetValue: 57933824 + fields: + - name: APB_SARADC_FILTER_CHANNEL1 + description: configure filter1 to adc channel + bitOffset: 18 + bitWidth: 4 + access: read-write + - name: APB_SARADC_FILTER_CHANNEL0 + description: configure filter0 to adc channel + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: APB_SARADC_FILTER_RESET + description: enable apb_adc1_filter + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAR1DATA_STATUS + description: digital saradc configure register + addressOffset: 44 + size: 32 + fields: + - name: APB_SARADC1_DATA + description: saradc1 data + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: SAR2DATA_STATUS + description: digital saradc configure register + addressOffset: 48 + size: 32 + fields: + - name: APB_SARADC2_DATA + description: saradc2 data + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: THRES0_CTRL + description: digital saradc configure register + addressOffset: 52 + size: 32 + resetValue: 262125 + fields: + - name: APB_SARADC_THRES0_CHANNEL + description: configure thres0 to adc channel + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: APB_SARADC_THRES0_HIGH + description: saradc thres0 monitor thres + bitOffset: 5 + bitWidth: 13 + access: read-write + - name: APB_SARADC_THRES0_LOW + description: saradc thres0 monitor thres + bitOffset: 18 + bitWidth: 13 + access: read-write + - register: + name: THRES1_CTRL + description: digital saradc configure register + addressOffset: 56 + size: 32 + resetValue: 262125 + fields: + - name: APB_SARADC_THRES1_CHANNEL + description: configure thres1 to adc channel + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: APB_SARADC_THRES1_HIGH + description: saradc thres1 monitor thres + bitOffset: 5 + bitWidth: 13 + access: read-write + - name: APB_SARADC_THRES1_LOW + description: saradc thres1 monitor thres + bitOffset: 18 + bitWidth: 13 + access: read-write + - register: + name: THRES_CTRL + description: digital saradc configure register + addressOffset: 60 + size: 32 + fields: + - name: APB_SARADC_THRES_ALL_EN + description: enable thres to all channel + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES1_EN + description: enable thres1 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES0_EN + description: enable thres0 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_ENA + description: digital saradc int register + addressOffset: 64 + size: 32 + fields: + - name: APB_SARADC_THRES1_LOW_INT_ENA + description: saradc thres1 low interrupt enable + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES0_LOW_INT_ENA + description: saradc thres0 low interrupt enable + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES1_HIGH_INT_ENA + description: saradc thres1 high interrupt enable + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES0_HIGH_INT_ENA + description: saradc thres0 high interrupt enable + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: APB_SARADC2_DONE_INT_ENA + description: saradc2 done interrupt enable + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: APB_SARADC1_DONE_INT_ENA + description: saradc1 done interrupt enable + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: digital saradc int register + addressOffset: 68 + size: 32 + fields: + - name: APB_SARADC_THRES1_LOW_INT_RAW + description: saradc thres1 low interrupt raw + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: APB_SARADC_THRES0_LOW_INT_RAW + description: saradc thres0 low interrupt raw + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: APB_SARADC_THRES1_HIGH_INT_RAW + description: saradc thres1 high interrupt raw + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: APB_SARADC_THRES0_HIGH_INT_RAW + description: saradc thres0 high interrupt raw + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: APB_SARADC2_DONE_INT_RAW + description: saradc2 done interrupt raw + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: APB_SARADC1_DONE_INT_RAW + description: saradc1 done interrupt raw + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: digital saradc int register + addressOffset: 72 + size: 32 + fields: + - name: APB_SARADC_THRES1_LOW_INT_ST + description: saradc thres1 low interrupt state + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: APB_SARADC_THRES0_LOW_INT_ST + description: saradc thres0 low interrupt state + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: APB_SARADC_THRES1_HIGH_INT_ST + description: saradc thres1 high interrupt state + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: APB_SARADC_THRES0_HIGH_INT_ST + description: saradc thres0 high interrupt state + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: APB_SARADC2_DONE_INT_ST + description: saradc2 done interrupt state + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: APB_SARADC1_DONE_INT_ST + description: saradc1 done interrupt state + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: digital saradc int register + addressOffset: 76 + size: 32 + fields: + - name: APB_SARADC_THRES1_LOW_INT_CLR + description: saradc thres1 low interrupt clear + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: APB_SARADC_THRES0_LOW_INT_CLR + description: saradc thres0 low interrupt clear + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: APB_SARADC_THRES1_HIGH_INT_CLR + description: saradc thres1 high interrupt clear + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: APB_SARADC_THRES0_HIGH_INT_CLR + description: saradc thres0 high interrupt clear + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: APB_SARADC2_DONE_INT_CLR + description: saradc2 done interrupt clear + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: APB_SARADC1_DONE_INT_CLR + description: saradc1 done interrupt clear + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: DMA_CONF + description: digital saradc configure register + addressOffset: 80 + size: 32 + resetValue: 255 + fields: + - name: APB_ADC_EOF_NUM + description: the dma_in_suc_eof gen when sample cnt = spi_eof_num + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: APB_ADC_RESET_FSM + description: reset_apb_adc_state + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: APB_ADC_TRANS + description: enable apb_adc use spi_dma + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CLKM_CONF + description: digital saradc configure register + addressOffset: 84 + size: 32 + resetValue: 4 + fields: + - name: CLKM_DIV_NUM + description: Integral I2S clock divider value + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CLKM_DIV_B + description: Fractional clock divider numerator value + bitOffset: 8 + bitWidth: 6 + access: read-write + - name: CLKM_DIV_A + description: Fractional clock divider denominator value + bitOffset: 14 + bitWidth: 6 + access: read-write + - name: CLK_EN + description: reg clk en + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CLK_SEL + description: Set this bit to enable clk_apll + bitOffset: 21 + bitWidth: 2 + access: read-write + - register: + name: APB_TSENS_CTRL + description: digital tsens configure register + addressOffset: 88 + size: 32 + resetValue: 98304 + fields: + - name: TSENS_OUT + description: temperature sensor data out + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: TSENS_IN_INV + description: invert temperature sensor data + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TSENS_CLK_DIV + description: temperature sensor clock divider + bitOffset: 14 + bitWidth: 8 + access: read-write + - name: TSENS_PU + description: temperature sensor power up + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: TSENS_CTRL2 + description: digital tsens configure register + addressOffset: 92 + size: 32 + resetValue: 16386 + fields: + - name: TSENS_XPD_WAIT + description: the time that power up tsens need wait + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: TSENS_XPD_FORCE + description: force power up tsens + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: TSENS_CLK_INV + description: inv tsens clk + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TSENS_CLK_SEL + description: tsens clk select + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: CALI + description: digital saradc configure register + addressOffset: 96 + size: 32 + resetValue: 32768 + fields: + - name: APB_SARADC_CALI_CFG + description: saradc cali factor + bitOffset: 0 + bitWidth: 17 + access: read-write + - register: + name: CTRL_DATE + description: version + addressOffset: 1020 + size: 32 + resetValue: 33583473 + fields: + - name: DATE + description: version + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: ASSIST_DEBUG + description: Debug Assist + groupName: ASSIST_DEBUG + baseAddress: 1611456512 + addressBlock: + - offset: 0 + size: 160 + usage: registers + interrupt: + - name: ASSIST_DEBUG + value: 54 + registers: + - register: + name: CORE_0_MONTR_ENA + description: ASSIST_DEBUG_C0RE_0_MONTR_ENA_REG + addressOffset: 0 + size: 32 + fields: + - name: CORE_0_AREA_DRAM0_0_RD_ENA + description: reg_core_0_area_dram0_0_rd_ena + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_0_WR_ENA + description: reg_core_0_area_dram0_0_wr_ena + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_1_RD_ENA + description: reg_core_0_area_dram0_1_rd_ena + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_1_WR_ENA + description: reg_core_0_area_dram0_1_wr_ena + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_0_RD_ENA + description: reg_core_0_area_pif_0_rd_ena + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_0_WR_ENA + description: reg_core_0_area_pif_0_wr_ena + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_1_RD_ENA + description: reg_core_0_area_pif_1_rd_ena + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_1_WR_ENA + description: reg_core_0_area_pif_1_wr_ena + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CORE_0_SP_SPILL_MIN_ENA + description: reg_core_0_sp_spill_min_ena + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CORE_0_SP_SPILL_MAX_ENA + description: reg_core_0_sp_spill_max_ena + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CORE_0_IRAM0_EXCEPTION_MONITOR_ENA + description: reg_core_0_iram0_exception_monitor_ena + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CORE_0_DRAM0_EXCEPTION_MONITOR_ENA + description: reg_core_0_dram0_exception_monitor_ena + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_INTR_RAW + description: ASSIST_DEBUG_CORE_0_INTR_RAW_REG + addressOffset: 4 + size: 32 + fields: + - name: CORE_0_AREA_DRAM0_0_RD_RAW + description: reg_core_0_area_dram0_0_rd_raw + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_DRAM0_0_WR_RAW + description: reg_core_0_area_dram0_0_wr_raw + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_DRAM0_1_RD_RAW + description: reg_core_0_area_dram0_1_rd_raw + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_DRAM0_1_WR_RAW + description: reg_core_0_area_dram0_1_wr_raw + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_PIF_0_RD_RAW + description: reg_core_0_area_pif_0_rd_raw + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_PIF_0_WR_RAW + description: reg_core_0_area_pif_0_wr_raw + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_PIF_1_RD_RAW + description: reg_core_0_area_pif_1_rd_raw + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_PIF_1_WR_RAW + description: reg_core_0_area_pif_1_wr_raw + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: CORE_0_SP_SPILL_MIN_RAW + description: reg_core_0_sp_spill_min_raw + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: CORE_0_SP_SPILL_MAX_RAW + description: reg_core_0_sp_spill_max_raw + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: CORE_0_IRAM0_EXCEPTION_MONITOR_RAW + description: reg_core_0_iram0_exception_monitor_raw + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: CORE_0_DRAM0_EXCEPTION_MONITOR_RAW + description: reg_core_0_dram0_exception_monitor_raw + bitOffset: 11 + bitWidth: 1 + access: read-only + - register: + name: CORE_0_INTR_ENA + description: ASSIST_DEBUG_CORE_0_INTR_ENA_REG + addressOffset: 8 + size: 32 + fields: + - name: CORE_0_AREA_DRAM0_0_RD_INTR_ENA + description: reg_core_0_area_dram0_0_rd_intr_ena + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_0_WR_INTR_ENA + description: reg_core_0_area_dram0_0_wr_intr_ena + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_1_RD_INTR_ENA + description: reg_core_0_area_dram0_1_rd_intr_ena + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_1_WR_INTR_ENA + description: reg_core_0_area_dram0_1_wr_intr_ena + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_0_RD_INTR_ENA + description: reg_core_0_area_pif_0_rd_intr_ena + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_0_WR_INTR_ENA + description: reg_core_0_area_pif_0_wr_intr_ena + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_1_RD_INTR_ENA + description: reg_core_0_area_pif_1_rd_intr_ena + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_1_WR_INTR_ENA + description: reg_core_0_area_pif_1_wr_intr_ena + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CORE_0_SP_SPILL_MIN_INTR_ENA + description: reg_core_0_sp_spill_min_intr_ena + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CORE_0_SP_SPILL_MAX_INTR_ENA + description: reg_core_0_sp_spill_max_intr_ena + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CORE_0_IRAM0_EXCEPTION_MONITOR_RLS + description: reg_core_0_iram0_exception_monitor_ena + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CORE_0_DRAM0_EXCEPTION_MONITOR_RLS + description: reg_core_0_dram0_exception_monitor_ena + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_INTR_CLR + description: ASSIST_DEBUG_CORE_0_INTR_CLR_REG + addressOffset: 12 + size: 32 + fields: + - name: CORE_0_AREA_DRAM0_0_RD_CLR + description: reg_core_0_area_dram0_0_rd_clr + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_0_WR_CLR + description: reg_core_0_area_dram0_0_wr_clr + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_1_RD_CLR + description: reg_core_0_area_dram0_1_rd_clr + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_1_WR_CLR + description: reg_core_0_area_dram0_1_wr_clr + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_0_RD_CLR + description: reg_core_0_area_pif_0_rd_clr + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_0_WR_CLR + description: reg_core_0_area_pif_0_wr_clr + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_1_RD_CLR + description: reg_core_0_area_pif_1_rd_clr + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_1_WR_CLR + description: reg_core_0_area_pif_1_wr_clr + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CORE_0_SP_SPILL_MIN_CLR + description: reg_core_0_sp_spill_min_clr + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CORE_0_SP_SPILL_MAX_CLR + description: reg_core_0_sp_spill_max_clr + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CORE_0_IRAM0_EXCEPTION_MONITOR_CLR + description: reg_core_0_iram0_exception_monitor_clr + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CORE_0_DRAM0_EXCEPTION_MONITOR_CLR + description: reg_core_0_dram0_exception_monitor_clr + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_AREA_DRAM0_0_MIN + description: ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG + addressOffset: 16 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_AREA_DRAM0_0_MIN + description: reg_core_0_area_dram0_0_min + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_DRAM0_0_MAX + description: ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG + addressOffset: 20 + size: 32 + fields: + - name: CORE_0_AREA_DRAM0_0_MAX + description: reg_core_0_area_dram0_0_max + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_DRAM0_1_MIN + description: ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG + addressOffset: 24 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_AREA_DRAM0_1_MIN + description: reg_core_0_area_dram0_1_min + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_DRAM0_1_MAX + description: ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG + addressOffset: 28 + size: 32 + fields: + - name: CORE_0_AREA_DRAM0_1_MAX + description: reg_core_0_area_dram0_1_max + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_PIF_0_MIN + description: ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG + addressOffset: 32 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_AREA_PIF_0_MIN + description: reg_core_0_area_pif_0_min + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_PIF_0_MAX + description: ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG + addressOffset: 36 + size: 32 + fields: + - name: CORE_0_AREA_PIF_0_MAX + description: reg_core_0_area_pif_0_max + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_PIF_1_MIN + description: ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG + addressOffset: 40 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_AREA_PIF_1_MIN + description: reg_core_0_area_pif_1_min + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_PIF_1_MAX + description: ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG + addressOffset: 44 + size: 32 + fields: + - name: CORE_0_AREA_PIF_1_MAX + description: reg_core_0_area_pif_1_max + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_PC + description: ASSIST_DEBUG_CORE_0_AREA_PC_REG + addressOffset: 48 + size: 32 + fields: + - name: CORE_0_AREA_PC + description: reg_core_0_area_pc + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_AREA_SP + description: ASSIST_DEBUG_CORE_0_AREA_SP_REG + addressOffset: 52 + size: 32 + fields: + - name: CORE_0_AREA_SP + description: reg_core_0_area_sp + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_SP_MIN + description: ASSIST_DEBUG_CORE_0_SP_MIN_REG + addressOffset: 56 + size: 32 + fields: + - name: CORE_0_SP_MIN + description: reg_core_0_sp_min + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_SP_MAX + description: ASSIST_DEBUG_CORE_0_SP_MAX_REG + addressOffset: 60 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_SP_MAX + description: reg_core_0_sp_max + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_SP_PC + description: ASSIST_DEBUG_CORE_0_SP_PC_REG + addressOffset: 64 + size: 32 + fields: + - name: CORE_0_SP_PC + description: reg_core_0_sp_pc + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_RCD_EN + description: ASSIST_DEBUG_CORE_0_RCD_EN_REG + addressOffset: 68 + size: 32 + fields: + - name: CORE_0_RCD_RECORDEN + description: reg_core_0_rcd_recorden + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_RCD_PDEBUGEN + description: reg_core_0_rcd_pdebugen + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_RCD_PDEBUGPC + description: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG + addressOffset: 72 + size: 32 + fields: + - name: CORE_0_RCD_PDEBUGPC + description: reg_core_0_rcd_pdebugpc + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_RCD_PDEBUGSP + description: ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG + addressOffset: 76 + size: 32 + fields: + - name: CORE_0_RCD_PDEBUGSP + description: reg_core_0_rcd_pdebugsp + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_IRAM0_EXCEPTION_MONITOR_0 + description: ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG + addressOffset: 80 + size: 32 + fields: + - name: CORE_0_IRAM0_RECORDING_ADDR_0 + description: reg_core_0_iram0_recording_addr_0 + bitOffset: 0 + bitWidth: 24 + access: read-only + - name: CORE_0_IRAM0_RECORDING_WR_0 + description: reg_core_0_iram0_recording_wr_0 + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: CORE_0_IRAM0_RECORDING_LOADSTORE_0 + description: reg_core_0_iram0_recording_loadstore_0 + bitOffset: 25 + bitWidth: 1 + access: read-only + - register: + name: CORE_0_IRAM0_EXCEPTION_MONITOR_1 + description: ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG + addressOffset: 84 + size: 32 + fields: + - name: CORE_0_IRAM0_RECORDING_ADDR_1 + description: reg_core_0_iram0_recording_addr_1 + bitOffset: 0 + bitWidth: 24 + access: read-only + - name: CORE_0_IRAM0_RECORDING_WR_1 + description: reg_core_0_iram0_recording_wr_1 + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: CORE_0_IRAM0_RECORDING_LOADSTORE_1 + description: reg_core_0_iram0_recording_loadstore_1 + bitOffset: 25 + bitWidth: 1 + access: read-only + - register: + name: CORE_0_DRAM0_EXCEPTION_MONITOR_0 + description: ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG + addressOffset: 88 + size: 32 + fields: + - name: CORE_0_DRAM0_RECORDING_ADDR_0 + description: reg_core_0_dram0_recording_addr_0 + bitOffset: 0 + bitWidth: 24 + access: read-only + - name: CORE_0_DRAM0_RECORDING_WR_0 + description: reg_core_0_dram0_recording_wr_0 + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: CORE_0_DRAM0_RECORDING_BYTEEN_0 + description: reg_core_0_dram0_recording_byteen_0 + bitOffset: 25 + bitWidth: 4 + access: read-only + - register: + name: CORE_0_DRAM0_EXCEPTION_MONITOR_1 + description: ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG + addressOffset: 92 + size: 32 + fields: + - name: CORE_0_DRAM0_RECORDING_PC_0 + description: reg_core_0_dram0_recording_pc_0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_DRAM0_EXCEPTION_MONITOR_2 + description: ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG + addressOffset: 96 + size: 32 + fields: + - name: CORE_0_DRAM0_RECORDING_ADDR_1 + description: reg_core_0_dram0_recording_addr_1 + bitOffset: 0 + bitWidth: 24 + access: read-only + - name: CORE_0_DRAM0_RECORDING_WR_1 + description: reg_core_0_dram0_recording_wr_1 + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: CORE_0_DRAM0_RECORDING_BYTEEN_1 + description: reg_core_0_dram0_recording_byteen_1 + bitOffset: 25 + bitWidth: 4 + access: read-only + - register: + name: CORE_0_DRAM0_EXCEPTION_MONITOR_3 + description: ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG + addressOffset: 100 + size: 32 + fields: + - name: CORE_0_DRAM0_RECORDING_PC_1 + description: reg_core_0_dram0_recording_pc_1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 + description: ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG + addressOffset: 104 + size: 32 + fields: + - name: CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 + description: reg_core_x_iram0_dram0_limit_cycle_0 + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 + description: ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG + addressOffset: 108 + size: 32 + fields: + - name: CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 + description: reg_core_x_iram0_dram0_limit_cycle_1 + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: LOG_SETTING + description: ASSIST_DEBUG_LOG_SETTING + addressOffset: 112 + size: 32 + resetValue: 128 + fields: + - name: LOG_ENA + description: reg_log_ena + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: LOG_MODE + description: reg_log_mode + bitOffset: 3 + bitWidth: 4 + access: read-write + - name: LOG_MEM_LOOP_ENABLE + description: reg_log_mem_loop_enable + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: LOG_DATA_0 + description: ASSIST_DEBUG_LOG_DATA_0_REG + addressOffset: 116 + size: 32 + fields: + - name: LOG_DATA_0 + description: reg_log_data_0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOG_DATA_MASK + description: ASSIST_DEBUG_LOG_DATA_MASK_REG + addressOffset: 120 + size: 32 + fields: + - name: LOG_DATA_SIZE + description: reg_log_data_size + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: LOG_MIN + description: ASSIST_DEBUG_LOG_MIN_REG + addressOffset: 124 + size: 32 + fields: + - name: LOG_MIN + description: reg_log_min + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOG_MAX + description: ASSIST_DEBUG_LOG_MAX_REG + addressOffset: 128 + size: 32 + fields: + - name: LOG_MAX + description: reg_log_max + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOG_MEM_START + description: ASSIST_DEBUG_LOG_MEM_START_REG + addressOffset: 132 + size: 32 + fields: + - name: LOG_MEM_START + description: reg_log_mem_start + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOG_MEM_END + description: ASSIST_DEBUG_LOG_MEM_END_REG + addressOffset: 136 + size: 32 + fields: + - name: LOG_MEM_END + description: reg_log_mem_end + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOG_MEM_WRITING_ADDR + description: ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG + addressOffset: 140 + size: 32 + fields: + - name: LOG_MEM_WRITING_ADDR + description: reg_log_mem_writing_addr + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: LOG_MEM_FULL_FLAG + description: ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG + addressOffset: 144 + size: 32 + fields: + - name: LOG_MEM_FULL_FLAG + description: reg_log_mem_full_flag + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CLR_LOG_MEM_FULL_FLAG + description: reg_clr_log_mem_full_flag + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: C0RE_0_LASTPC_BEFORE_EXCEPTION + description: ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION + addressOffset: 148 + size: 32 + fields: + - name: CORE_0_LASTPC_BEFORE_EXC + description: reg_core_0_lastpc_before_exc + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: C0RE_0_DEBUG_MODE + description: ASSIST_DEBUG_C0RE_0_DEBUG_MODE + addressOffset: 152 + size: 32 + fields: + - name: CORE_0_DEBUG_MODE + description: reg_core_0_debug_mode + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_0_DEBUG_MODULE_ACTIVE + description: reg_core_0_debug_module_active + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: ASSIST_DEBUG_DATE_REG + addressOffset: 508 + size: 32 + resetValue: 33587216 + fields: + - name: ASSIST_DEBUG_DATE + description: reg_assist_debug_date + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: BB + description: BB Peripheral + groupName: BB + baseAddress: 1610731520 + addressBlock: + - offset: 0 + size: 4 + usage: registers + registers: + - register: + name: BBPD_CTRL + description: Baseband control register + addressOffset: 84 + size: 32 + fields: + - name: DC_EST_FORCE_PD + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DC_EST_FORCE_PU + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FFT_FORCE_PD + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FFT_FORCE_PU + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DMA + description: DMA (Direct Memory Access) Controller + groupName: DMA + baseAddress: 1610870784 + addressBlock: + - offset: 0 + size: 372 + usage: registers + interrupt: + - name: DMA_CH0 + value: 44 + - name: DMA_CH1 + value: 45 + - name: DMA_CH2 + value: 46 + - name: DMA_APBPERI_PMS + value: 55 + registers: + - cluster: + dim: 3 + dimIncrement: 16 + dimIndex: "0,1,2" + name: INT_CH%s + description: "Cluster INT_CH%s, containing INT_RAW_CH?, INT_ST_CH?, INT_ENA_CH?, INT_CLR_CH?" + addressOffset: 0 + children: + - register: + name: RAW + description: DMA_INT_RAW_CH0_REG. + addressOffset: 0 + size: 32 + fields: + - name: IN_DONE + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF + description: "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF + description: "The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_DONE + description: The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUT_EOF + description: The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR + description: "The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR + description: "The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY + description: "The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF + description: The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF + description: This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF + description: This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF + description: This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF + description: This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: ST + description: DMA_INT_ST_CH0_REG. + addressOffset: 4 + size: 32 + fields: + - name: IN_DONE + description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: IN_SUC_EOF + description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: IN_ERR_EOF + description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: OUT_DONE + description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: OUT_EOF + description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: IN_DSCR_ERR + description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OUT_DSCR_ERR + description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: IN_DSCR_EMPTY + description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OUT_TOTAL_EOF + description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: INFIFO_OVF + description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: INFIFO_UDF + description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: OUTFIFO_OVF + description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: OUTFIFO_UDF + description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - register: + name: ENA + description: DMA_INT_ENA_CH0_REG. + addressOffset: 8 + size: 32 + fields: + - name: IN_DONE + description: The interrupt enable bit for the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF + description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF + description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_DONE + description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUT_EOF + description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR + description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR + description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY + description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF + description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF + description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF + description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF + description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF + description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: CLR + description: DMA_INT_CLR_CH0_REG. + addressOffset: 12 + size: 32 + fields: + - name: IN_DONE + description: Set this bit to clear the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: IN_SUC_EOF + description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: IN_ERR_EOF + description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: OUT_DONE + description: Set this bit to clear the OUT_DONE_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: OUT_EOF + description: Set this bit to clear the OUT_EOF_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: IN_DSCR_ERR + description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: OUT_DSCR_ERR + description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: IN_DSCR_EMPTY + description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: OUT_TOTAL_EOF + description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: INFIFO_OVF + description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: INFIFO_UDF + description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: OUTFIFO_OVF + description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: OUTFIFO_UDF + description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - register: + name: AHB_TEST + description: DMA_AHB_TEST_REG. + addressOffset: 64 + size: 32 + fields: + - name: AHB_TESTMODE + description: reserved + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: AHB_TESTADDR + description: reserved + bitOffset: 4 + bitWidth: 2 + access: read-write + - register: + name: MISC_CONF + description: DMA_MISC_CONF_REG. + addressOffset: 68 + size: 32 + fields: + - name: AHBM_RST_INTER + description: "Set this bit, then clear this bit to reset the internal ahb FSM." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ARB_PRI_DIS + description: Set this bit to disable priority arbitration function. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: reg_clk_en + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: DMA_DATE_REG. + addressOffset: 72 + size: 32 + resetValue: 33587792 + fields: + - name: DATE + description: register version. + bitOffset: 0 + bitWidth: 32 + access: read-write + - cluster: + dim: 3 + dimIncrement: 192 + dimIndex: "0,1,2" + name: CH%s + description: "Cluster CH%s, containing IN_CONF0_CH?, IN_CONF1_CH?, INFIFO_STATUS_CH?, IN_POP_CH?, IN_LINK_CH?, IN_STATE_CH?, IN_SUC_EOF_DES_ADDR_CH?, IN_ERR_EOF_DES_ADDR_CH?, IN_DSCR_CH?, IN_DSCR_BF0_CH?, IN_DSCR_BF1_CH?, IN_PRI_CH?, IN_PERI_SEL_CH?, OUT_CONF0_CH?, OUT_CONF1_CH?, OUTFIFO_STATUS_CH?, OUT_PUSH_CH?, OUT_LINK_CH?, OUT_STATE_CH?, OUT_EOF_DES_ADDR_CH?, OUT_EOF_BFR_DES_ADDR_CH?, OUT_DSCR_CH?, OUT_DSCR_BF0_CH?, OUT_DSCR_BF1_CH?, OUT_PRI_CH?, OUT_PERI_SEL_CH?" + addressOffset: 112 + children: + - register: + name: IN_CONF0 + description: DMA_IN_CONF0_CH0_REG. + addressOffset: 0 + size: 32 + fields: + - name: IN_RST + description: This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_LOOP_TEST + description: reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: INDSCR_BURST_EN + description: Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DATA_BURST_EN + description: Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MEM_TRANS_EN + description: Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: IN_CONF1 + description: DMA_IN_CONF1_CH0_REG. + addressOffset: 4 + size: 32 + fields: + - name: IN_CHECK_OWNER + description: Set this bit to enable checking the owner attribute of the link descriptor. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: INFIFO_STATUS + description: DMA_INFIFO_STATUS_CH0_REG. + addressOffset: 8 + size: 32 + resetValue: 125829123 + fields: + - name: INFIFO_FULL + description: L1 Rx FIFO full signal for Rx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: INFIFO_EMPTY + description: L1 Rx FIFO empty signal for Rx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: INFIFO_CNT + description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + bitOffset: 2 + bitWidth: 6 + access: read-only + - name: IN_REMAIN_UNDER_1B + description: reserved + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: IN_REMAIN_UNDER_2B + description: reserved + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: IN_REMAIN_UNDER_3B + description: reserved + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: IN_REMAIN_UNDER_4B + description: reserved + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: IN_BUF_HUNGRY + description: reserved + bitOffset: 27 + bitWidth: 1 + access: read-only + - register: + name: IN_POP + description: DMA_IN_POP_CH0_REG. + addressOffset: 12 + size: 32 + resetValue: 2048 + fields: + - name: INFIFO_RDATA + description: This register stores the data popping from DMA FIFO. + bitOffset: 0 + bitWidth: 12 + access: read-only + - name: INFIFO_POP + description: Set this bit to pop data from DMA FIFO. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: IN_LINK + description: DMA_IN_LINK_CH0_REG. + addressOffset: 16 + size: 32 + resetValue: 17825792 + fields: + - name: INLINK_ADDR + description: "This register stores the 20 least significant bits of the first inlink descriptor's address." + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: INLINK_AUTO_RET + description: "Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: INLINK_STOP + description: Set this bit to stop dealing with the inlink descriptors. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: INLINK_START + description: Set this bit to start dealing with the inlink descriptors. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: INLINK_RESTART + description: Set this bit to mount a new inlink descriptor. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: INLINK_PARK + description: "1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working." + bitOffset: 24 + bitWidth: 1 + access: read-only + - register: + name: IN_STATE + description: DMA_IN_STATE_CH0_REG. + addressOffset: 20 + size: 32 + fields: + - name: INLINK_DSCR_ADDR + description: "This register stores the current inlink descriptor's address." + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: IN_DSCR_STATE + description: reserved + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: IN_STATE + description: reserved + bitOffset: 20 + bitWidth: 3 + access: read-only + - register: + name: IN_SUC_EOF_DES_ADDR + description: DMA_IN_SUC_EOF_DES_ADDR_CH0_REG. + addressOffset: 24 + size: 32 + fields: + - name: IN_SUC_EOF_DES_ADDR + description: This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_ERR_EOF_DES_ADDR + description: DMA_IN_ERR_EOF_DES_ADDR_CH0_REG. + addressOffset: 28 + size: 32 + fields: + - name: IN_ERR_EOF_DES_ADDR + description: This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR + description: DMA_IN_DSCR_CH0_REG. + addressOffset: 32 + size: 32 + fields: + - name: INLINK_DSCR + description: The address of the current inlink descriptor x. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_BF0 + description: DMA_IN_DSCR_BF0_CH0_REG. + addressOffset: 36 + size: 32 + fields: + - name: INLINK_DSCR_BF0 + description: The address of the last inlink descriptor x-1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_BF1 + description: DMA_IN_DSCR_BF1_CH0_REG. + addressOffset: 40 + size: 32 + fields: + - name: INLINK_DSCR_BF1 + description: The address of the second-to-last inlink descriptor x-2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_PRI + description: DMA_IN_PRI_CH0_REG. + addressOffset: 44 + size: 32 + fields: + - name: RX_PRI + description: "The priority of Rx channel 0. The larger of the value, the higher of the priority." + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: IN_PERI_SEL + description: DMA_IN_PERI_SEL_CH0_REG. + addressOffset: 48 + size: 32 + resetValue: 63 + fields: + - name: PERI_IN_SEL + description: "This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC." + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: OUT_CONF0 + description: DMA_OUT_CONF0_CH0_REG. + addressOffset: 96 + size: 32 + resetValue: 8 + fields: + - name: OUT_RST + description: This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_LOOP_TEST + description: reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_AUTO_WRBACK + description: Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_EOF_MODE + description: "EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTDSCR_BURST_EN + description: Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUT_DATA_BURST_EN + description: Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: OUT_CONF1 + description: DMA_OUT_CONF1_CH0_REG. + addressOffset: 100 + size: 32 + fields: + - name: OUT_CHECK_OWNER + description: Set this bit to enable checking the owner attribute of the link descriptor. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: OUTFIFO_STATUS + description: DMA_OUTFIFO_STATUS_CH0_REG. + addressOffset: 104 + size: 32 + resetValue: 125829122 + fields: + - name: OUTFIFO_FULL + description: L1 Tx FIFO full signal for Tx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY + description: L1 Tx FIFO empty signal for Tx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: OUTFIFO_CNT + description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + bitOffset: 2 + bitWidth: 6 + access: read-only + - name: OUT_REMAIN_UNDER_1B + description: reserved + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: OUT_REMAIN_UNDER_2B + description: reserved + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: OUT_REMAIN_UNDER_3B + description: reserved + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: OUT_REMAIN_UNDER_4B + description: reserved + bitOffset: 26 + bitWidth: 1 + access: read-only + - register: + name: OUT_PUSH + description: DMA_OUT_PUSH_CH0_REG. + addressOffset: 108 + size: 32 + fields: + - name: OUTFIFO_WDATA + description: This register stores the data that need to be pushed into DMA FIFO. + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: OUTFIFO_PUSH + description: Set this bit to push data into DMA FIFO. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: OUT_LINK + description: DMA_OUT_LINK_CH0_REG. + addressOffset: 112 + size: 32 + resetValue: 8388608 + fields: + - name: OUTLINK_ADDR + description: "This register stores the 20 least significant bits of the first outlink descriptor's address." + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: OUTLINK_STOP + description: Set this bit to stop dealing with the outlink descriptors. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: OUTLINK_START + description: Set this bit to start dealing with the outlink descriptors. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: OUTLINK_RESTART + description: Set this bit to restart a new outlink from the last address. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: OUTLINK_PARK + description: "1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working." + bitOffset: 23 + bitWidth: 1 + access: read-only + - register: + name: OUT_STATE + description: DMA_OUT_STATE_CH0_REG. + addressOffset: 116 + size: 32 + fields: + - name: OUTLINK_DSCR_ADDR + description: "This register stores the current outlink descriptor's address." + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: OUT_DSCR_STATE + description: reserved + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: OUT_STATE + description: reserved + bitOffset: 20 + bitWidth: 3 + access: read-only + - register: + name: OUT_EOF_DES_ADDR + description: DMA_OUT_EOF_DES_ADDR_CH0_REG. + addressOffset: 120 + size: 32 + fields: + - name: OUT_EOF_DES_ADDR + description: This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_EOF_BFR_DES_ADDR + description: DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG. + addressOffset: 124 + size: 32 + fields: + - name: OUT_EOF_BFR_DES_ADDR + description: This register stores the address of the outlink descriptor before the last outlink descriptor. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR + description: DMA_OUT_DSCR_CH0_REG. + addressOffset: 128 + size: 32 + fields: + - name: OUTLINK_DSCR + description: The address of the current outlink descriptor y. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_BF0 + description: DMA_OUT_DSCR_BF0_CH0_REG. + addressOffset: 132 + size: 32 + fields: + - name: OUTLINK_DSCR_BF0 + description: The address of the last outlink descriptor y-1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_BF1 + description: DMA_OUT_DSCR_BF1_CH0_REG. + addressOffset: 136 + size: 32 + fields: + - name: OUTLINK_DSCR_BF1 + description: The address of the second-to-last inlink descriptor x-2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_PRI + description: DMA_OUT_PRI_CH0_REG. + addressOffset: 140 + size: 32 + fields: + - name: TX_PRI + description: "The priority of Tx channel 0. The larger of the value, the higher of the priority." + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: OUT_PERI_SEL + description: DMA_OUT_PERI_SEL_CH0_REG. + addressOffset: 144 + size: 32 + resetValue: 63 + fields: + - name: PERI_OUT_SEL + description: "This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC." + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: DS + description: Digital Signature + groupName: DS + baseAddress: 1610862592 + addressBlock: + - offset: 0 + size: 4236 + usage: registers + registers: + - register: + dim: 128 + dimIncrement: 4 + name: "Y_MEM[%s]" + description: memory that stores Y + addressOffset: 0 + size: 32 + - register: + dim: 128 + dimIncrement: 4 + name: "M_MEM[%s]" + description: memory that stores M + addressOffset: 512 + size: 32 + - register: + dim: 128 + dimIncrement: 4 + name: "RB_MEM[%s]" + description: memory that stores Rb + addressOffset: 1024 + size: 32 + - register: + dim: 12 + dimIncrement: 4 + name: "BOX_MEM[%s]" + description: memory that stores BOX + addressOffset: 1536 + size: 32 + - register: + dim: 128 + dimIncrement: 4 + name: "X_MEM[%s]" + description: memory that stores X + addressOffset: 2048 + size: 32 + - register: + dim: 128 + dimIncrement: 4 + name: "Z_MEM[%s]" + description: memory that stores Z + addressOffset: 2560 + size: 32 + - register: + name: SET_START + description: DS start control register + addressOffset: 3584 + size: 32 + fields: + - name: SET_START + description: set this bit to start DS operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_CONTINUE + description: DS continue control register + addressOffset: 3588 + size: 32 + fields: + - name: SET_CONTINUE + description: set this bit to continue DS operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_FINISH + description: DS finish control register + addressOffset: 3592 + size: 32 + fields: + - name: SET_FINISH + description: Set this bit to finish DS process. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: QUERY_BUSY + description: DS query busy register + addressOffset: 3596 + size: 32 + fields: + - name: QUERY_BUSY + description: "digital signature state. 1'b0: idle, 1'b1: busy" + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: QUERY_KEY_WRONG + description: DS query key-wrong counter register + addressOffset: 3600 + size: 32 + fields: + - name: QUERY_KEY_WRONG + description: digital signature key wrong counter + bitOffset: 0 + bitWidth: 4 + access: read-only + - register: + name: QUERY_CHECK + description: DS query check result register + addressOffset: 3604 + size: 32 + fields: + - name: MD_ERROR + description: "MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PADDING_BAD + description: "padding checkout result. 1'b0: a good padding, 1'b1: a bad padding" + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: DS version control register + addressOffset: 3616 + size: 32 + resetValue: 538969624 + fields: + - name: DATE + description: ds version information + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: IV_MEM%s + description: IV block data + addressOffset: 1584 + size: 32 + - name: EFUSE + description: eFuse Controller + groupName: EFUSE + baseAddress: 1610647552 + addressBlock: + - offset: 0 + size: 460 + usage: registers + interrupt: + - name: EFUSE + value: 24 + registers: + - register: + name: PGM_DATA0 + description: Register 0 that stores data to be programmed. + addressOffset: 0 + size: 32 + fields: + - name: PGM_DATA_0 + description: The content of the 0th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA1 + description: Register 1 that stores data to be programmed. + addressOffset: 4 + size: 32 + fields: + - name: PGM_DATA_1 + description: The content of the 1st 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA2 + description: Register 2 that stores data to be programmed. + addressOffset: 8 + size: 32 + fields: + - name: PGM_DATA_2 + description: The content of the 2nd 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA3 + description: Register 3 that stores data to be programmed. + addressOffset: 12 + size: 32 + fields: + - name: PGM_DATA_3 + description: The content of the 3rd 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA4 + description: Register 4 that stores data to be programmed. + addressOffset: 16 + size: 32 + fields: + - name: PGM_DATA_4 + description: The content of the 4th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA5 + description: Register 5 that stores data to be programmed. + addressOffset: 20 + size: 32 + fields: + - name: PGM_DATA_5 + description: The content of the 5th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA6 + description: Register 6 that stores data to be programmed. + addressOffset: 24 + size: 32 + fields: + - name: PGM_DATA_6 + description: The content of the 6th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA7 + description: Register 7 that stores data to be programmed. + addressOffset: 28 + size: 32 + fields: + - name: PGM_DATA_7 + description: The content of the 7th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_CHECK_VALUE0 + description: Register 0 that stores the RS code to be programmed. + addressOffset: 32 + size: 32 + fields: + - name: PGM_RS_DATA_0 + description: The content of the 0th 32-bit RS code to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_CHECK_VALUE1 + description: Register 1 that stores the RS code to be programmed. + addressOffset: 36 + size: 32 + fields: + - name: PGM_RS_DATA_1 + description: The content of the 1st 32-bit RS code to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_CHECK_VALUE2 + description: Register 2 that stores the RS code to be programmed. + addressOffset: 40 + size: 32 + fields: + - name: PGM_RS_DATA_2 + description: The content of the 2nd 32-bit RS code to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RD_WR_DIS + description: BLOCK0 data register 0. + addressOffset: 44 + size: 32 + fields: + - name: WR_DIS + description: Disable programming of individual eFuses. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_REPEAT_DATA0 + description: BLOCK0 data register 1. + addressOffset: 48 + size: 32 + fields: + - name: RD_DIS + description: Set this bit to disable reading from BlOCK4-10. + bitOffset: 0 + bitWidth: 7 + access: read-only + - name: DIS_RTC_RAM_BOOT + description: Set this bit to disable boot from RTC RAM. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DIS_ICACHE + description: Set this bit to disable Icache. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DIS_USB_JTAG + description: Set this bit to disable function of usb switch to jtag in module of usb device. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_ICACHE + description: "Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7)." + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: DIS_USB_DEVICE + description: Set this bit to disable usb device. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: DIS_FORCE_DOWNLOAD + description: Set this bit to disable the function that forces chip into download mode. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED6 + description: Reserved (used for four backups method). + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: DIS_CAN + description: Set this bit to disable CAN function. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: JTAG_SEL_ENABLE + description: Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SOFT_DIS_JTAG + description: Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module. + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: DIS_PAD_JTAG + description: Set this bit to disable JTAG in the hard way. JTAG is disabled permanently. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_MANUAL_ENCRYPT + description: Set this bit to disable flash encryption when in download boot modes. + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: USB_DREFH + description: "Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse." + bitOffset: 21 + bitWidth: 2 + access: read-only + - name: USB_DREFL + description: "Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse." + bitOffset: 23 + bitWidth: 2 + access: read-only + - name: USB_EXCHG_PINS + description: Set this bit to exchange USB D+ and D- pins. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: VDD_SPI_AS_GPIO + description: Set this bit to vdd spi pin function as gpio. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: BTLC_GPIO_ENABLE + description: Enable btlc gpio. + bitOffset: 27 + bitWidth: 2 + access: read-only + - name: POWERGLITCH_EN + description: Set this bit to enable power glitch function. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: POWER_GLITCH_DSENSE + description: Sample delay configuration of power glitch. + bitOffset: 30 + bitWidth: 2 + access: read-only + - register: + name: RD_REPEAT_DATA1 + description: BLOCK0 data register 2. + addressOffset: 52 + size: 32 + fields: + - name: RPT4_RESERVED2 + description: Reserved (used for four backups method). + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: WDT_DELAY_SEL + description: "Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000." + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: SPI_BOOT_CRYPT_CNT + description: "Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable." + bitOffset: 18 + bitWidth: 3 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE0 + description: Set this bit to enable revoking first secure boot key. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE1 + description: Set this bit to enable revoking second secure boot key. + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE2 + description: Set this bit to enable revoking third secure boot key. + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: KEY_PURPOSE_0 + description: Purpose of Key0. + bitOffset: 24 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_1 + description: Purpose of Key1. + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_REPEAT_DATA2 + description: BLOCK0 data register 3. + addressOffset: 56 + size: 32 + fields: + - name: KEY_PURPOSE_2 + description: Purpose of Key2. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_3 + description: Purpose of Key3. + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_4 + description: Purpose of Key4. + bitOffset: 8 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_5 + description: Purpose of Key5. + bitOffset: 12 + bitWidth: 4 + access: read-only + - name: RPT4_RESERVED3 + description: Reserved (used for four backups method). + bitOffset: 16 + bitWidth: 4 + access: read-only + - name: SECURE_BOOT_EN + description: Set this bit to enable secure boot. + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_AGGRESSIVE_REVOKE + description: Set this bit to enable revoking aggressive secure boot. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED0 + description: Reserved (used for four backups method). + bitOffset: 22 + bitWidth: 6 + access: read-only + - name: FLASH_TPUW + description: "Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value; Otherwise, the waiting time is twice the configurable value." + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_REPEAT_DATA3 + description: BLOCK0 data register 4. + addressOffset: 60 + size: 32 + fields: + - name: DIS_DOWNLOAD_MODE + description: "Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7)." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DIS_LEGACY_SPI_BOOT + description: "Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4)." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: UART_PRINT_CHANNEL + description: "Selectes the default UART print channel. 0: UART0. 1: UART1." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FLASH_ECC_MODE + description: "Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DIS_USB_DOWNLOAD_MODE + description: Set this bit to disable UART download mode through USB. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ENABLE_SECURITY_DOWNLOAD + description: Set this bit to enable secure UART download mode. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: UART_PRINT_CONTROL + description: "Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled." + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: PIN_POWER_SELECTION + description: "GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: FLASH_TYPE + description: "Set the maximum lines of SPI flash. 0: four lines. 1: eight lines." + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: FLASH_PAGE_SIZE + description: Set Flash page size. + bitOffset: 10 + bitWidth: 2 + access: read-only + - name: FLASH_ECC_EN + description: Set 1 to enable ECC for flash boot. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: FORCE_SEND_RESUME + description: Set this bit to force ROM code to send a resume command during SPI boot. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SECURE_VERSION + description: Secure version (used by ESP-IDF anti-rollback feature). + bitOffset: 14 + bitWidth: 16 + access: read-only + - name: RPT4_RESERVED1 + description: Reserved (used for four backups method). + bitOffset: 30 + bitWidth: 2 + access: read-only + - register: + name: RD_REPEAT_DATA4 + description: BLOCK0 data register 5. + addressOffset: 64 + size: 32 + fields: + - name: RPT4_RESERVED4 + description: Reserved (used for four backups method). + bitOffset: 0 + bitWidth: 24 + access: read-only + - register: + name: RD_MAC_SPI_SYS_0 + description: BLOCK1 data register 0. + addressOffset: 68 + size: 32 + fields: + - name: MAC_0 + description: Stores the low 32 bits of MAC address. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_MAC_SPI_SYS_1 + description: BLOCK1 data register 1. + addressOffset: 72 + size: 32 + fields: + - name: MAC_1 + description: Stores the high 16 bits of MAC address. + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: SPI_PAD_CONF_0 + description: Stores the zeroth part of SPI_PAD_CONF. + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: RD_MAC_SPI_SYS_2 + description: BLOCK1 data register 2. + addressOffset: 76 + size: 32 + fields: + - name: SPI_PAD_CONF_1 + description: Stores the first part of SPI_PAD_CONF. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_MAC_SPI_SYS_3 + description: BLOCK1 data register 3. + addressOffset: 80 + size: 32 + fields: + - name: SPI_PAD_CONF_2 + description: Stores the second part of SPI_PAD_CONF. + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: SYS_DATA_PART0_0 + description: Stores the fist 14 bits of the zeroth part of system data. + bitOffset: 18 + bitWidth: 14 + access: read-only + - register: + name: RD_MAC_SPI_SYS_4 + description: BLOCK1 data register 4. + addressOffset: 84 + size: 32 + fields: + - name: SYS_DATA_PART0_1 + description: Stores the fist 32 bits of the zeroth part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_MAC_SPI_SYS_5 + description: BLOCK1 data register 5. + addressOffset: 88 + size: 32 + fields: + - name: SYS_DATA_PART0_2 + description: Stores the second 32 bits of the zeroth part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA0 + description: Register 0 of BLOCK2 (system). + addressOffset: 92 + size: 32 + fields: + - name: SYS_DATA_PART1_0 + description: Stores the zeroth 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA1 + description: Register 1 of BLOCK2 (system). + addressOffset: 96 + size: 32 + fields: + - name: SYS_DATA_PART1_1 + description: Stores the first 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA2 + description: Register 2 of BLOCK2 (system). + addressOffset: 100 + size: 32 + fields: + - name: SYS_DATA_PART1_2 + description: Stores the second 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA3 + description: Register 3 of BLOCK2 (system). + addressOffset: 104 + size: 32 + fields: + - name: SYS_DATA_PART1_3 + description: Stores the third 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA4 + description: Register 4 of BLOCK2 (system). + addressOffset: 108 + size: 32 + fields: + - name: SYS_DATA_PART1_4 + description: Stores the fourth 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA5 + description: Register 5 of BLOCK2 (system). + addressOffset: 112 + size: 32 + fields: + - name: SYS_DATA_PART1_5 + description: Stores the fifth 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA6 + description: Register 6 of BLOCK2 (system). + addressOffset: 116 + size: 32 + fields: + - name: SYS_DATA_PART1_6 + description: Stores the sixth 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA7 + description: Register 7 of BLOCK2 (system). + addressOffset: 120 + size: 32 + fields: + - name: SYS_DATA_PART1_7 + description: Stores the seventh 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA0 + description: Register 0 of BLOCK3 (user). + addressOffset: 124 + size: 32 + fields: + - name: USR_DATA0 + description: Stores the zeroth 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA1 + description: Register 1 of BLOCK3 (user). + addressOffset: 128 + size: 32 + fields: + - name: USR_DATA1 + description: Stores the first 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA2 + description: Register 2 of BLOCK3 (user). + addressOffset: 132 + size: 32 + fields: + - name: USR_DATA2 + description: Stores the second 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA3 + description: Register 3 of BLOCK3 (user). + addressOffset: 136 + size: 32 + fields: + - name: USR_DATA3 + description: Stores the third 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA4 + description: Register 4 of BLOCK3 (user). + addressOffset: 140 + size: 32 + fields: + - name: USR_DATA4 + description: Stores the fourth 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA5 + description: Register 5 of BLOCK3 (user). + addressOffset: 144 + size: 32 + fields: + - name: USR_DATA5 + description: Stores the fifth 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA6 + description: Register 6 of BLOCK3 (user). + addressOffset: 148 + size: 32 + fields: + - name: USR_DATA6 + description: Stores the sixth 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA7 + description: Register 7 of BLOCK3 (user). + addressOffset: 152 + size: 32 + fields: + - name: USR_DATA7 + description: Stores the seventh 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA0 + description: Register 0 of BLOCK4 (KEY0). + addressOffset: 156 + size: 32 + fields: + - name: KEY0_DATA0 + description: Stores the zeroth 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA1 + description: Register 1 of BLOCK4 (KEY0). + addressOffset: 160 + size: 32 + fields: + - name: KEY0_DATA1 + description: Stores the first 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA2 + description: Register 2 of BLOCK4 (KEY0). + addressOffset: 164 + size: 32 + fields: + - name: KEY0_DATA2 + description: Stores the second 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA3 + description: Register 3 of BLOCK4 (KEY0). + addressOffset: 168 + size: 32 + fields: + - name: KEY0_DATA3 + description: Stores the third 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA4 + description: Register 4 of BLOCK4 (KEY0). + addressOffset: 172 + size: 32 + fields: + - name: KEY0_DATA4 + description: Stores the fourth 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA5 + description: Register 5 of BLOCK4 (KEY0). + addressOffset: 176 + size: 32 + fields: + - name: KEY0_DATA5 + description: Stores the fifth 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA6 + description: Register 6 of BLOCK4 (KEY0). + addressOffset: 180 + size: 32 + fields: + - name: KEY0_DATA6 + description: Stores the sixth 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA7 + description: Register 7 of BLOCK4 (KEY0). + addressOffset: 184 + size: 32 + fields: + - name: KEY0_DATA7 + description: Stores the seventh 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA0 + description: Register 0 of BLOCK5 (KEY1). + addressOffset: 188 + size: 32 + fields: + - name: KEY1_DATA0 + description: Stores the zeroth 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA1 + description: Register 1 of BLOCK5 (KEY1). + addressOffset: 192 + size: 32 + fields: + - name: KEY1_DATA1 + description: Stores the first 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA2 + description: Register 2 of BLOCK5 (KEY1). + addressOffset: 196 + size: 32 + fields: + - name: KEY1_DATA2 + description: Stores the second 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA3 + description: Register 3 of BLOCK5 (KEY1). + addressOffset: 200 + size: 32 + fields: + - name: KEY1_DATA3 + description: Stores the third 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA4 + description: Register 4 of BLOCK5 (KEY1). + addressOffset: 204 + size: 32 + fields: + - name: KEY1_DATA4 + description: Stores the fourth 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA5 + description: Register 5 of BLOCK5 (KEY1). + addressOffset: 208 + size: 32 + fields: + - name: KEY1_DATA5 + description: Stores the fifth 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA6 + description: Register 6 of BLOCK5 (KEY1). + addressOffset: 212 + size: 32 + fields: + - name: KEY1_DATA6 + description: Stores the sixth 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA7 + description: Register 7 of BLOCK5 (KEY1). + addressOffset: 216 + size: 32 + fields: + - name: KEY1_DATA7 + description: Stores the seventh 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA0 + description: Register 0 of BLOCK6 (KEY2). + addressOffset: 220 + size: 32 + fields: + - name: KEY2_DATA0 + description: Stores the zeroth 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA1 + description: Register 1 of BLOCK6 (KEY2). + addressOffset: 224 + size: 32 + fields: + - name: KEY2_DATA1 + description: Stores the first 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA2 + description: Register 2 of BLOCK6 (KEY2). + addressOffset: 228 + size: 32 + fields: + - name: KEY2_DATA2 + description: Stores the second 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA3 + description: Register 3 of BLOCK6 (KEY2). + addressOffset: 232 + size: 32 + fields: + - name: KEY2_DATA3 + description: Stores the third 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA4 + description: Register 4 of BLOCK6 (KEY2). + addressOffset: 236 + size: 32 + fields: + - name: KEY2_DATA4 + description: Stores the fourth 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA5 + description: Register 5 of BLOCK6 (KEY2). + addressOffset: 240 + size: 32 + fields: + - name: KEY2_DATA5 + description: Stores the fifth 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA6 + description: Register 6 of BLOCK6 (KEY2). + addressOffset: 244 + size: 32 + fields: + - name: KEY2_DATA6 + description: Stores the sixth 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA7 + description: Register 7 of BLOCK6 (KEY2). + addressOffset: 248 + size: 32 + fields: + - name: KEY2_DATA7 + description: Stores the seventh 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA0 + description: Register 0 of BLOCK7 (KEY3). + addressOffset: 252 + size: 32 + fields: + - name: KEY3_DATA0 + description: Stores the zeroth 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA1 + description: Register 1 of BLOCK7 (KEY3). + addressOffset: 256 + size: 32 + fields: + - name: KEY3_DATA1 + description: Stores the first 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA2 + description: Register 2 of BLOCK7 (KEY3). + addressOffset: 260 + size: 32 + fields: + - name: KEY3_DATA2 + description: Stores the second 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA3 + description: Register 3 of BLOCK7 (KEY3). + addressOffset: 264 + size: 32 + fields: + - name: KEY3_DATA3 + description: Stores the third 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA4 + description: Register 4 of BLOCK7 (KEY3). + addressOffset: 268 + size: 32 + fields: + - name: KEY3_DATA4 + description: Stores the fourth 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA5 + description: Register 5 of BLOCK7 (KEY3). + addressOffset: 272 + size: 32 + fields: + - name: KEY3_DATA5 + description: Stores the fifth 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA6 + description: Register 6 of BLOCK7 (KEY3). + addressOffset: 276 + size: 32 + fields: + - name: KEY3_DATA6 + description: Stores the sixth 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA7 + description: Register 7 of BLOCK7 (KEY3). + addressOffset: 280 + size: 32 + fields: + - name: KEY3_DATA7 + description: Stores the seventh 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA0 + description: Register 0 of BLOCK8 (KEY4). + addressOffset: 284 + size: 32 + fields: + - name: KEY4_DATA0 + description: Stores the zeroth 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA1 + description: Register 1 of BLOCK8 (KEY4). + addressOffset: 288 + size: 32 + fields: + - name: KEY4_DATA1 + description: Stores the first 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA2 + description: Register 2 of BLOCK8 (KEY4). + addressOffset: 292 + size: 32 + fields: + - name: KEY4_DATA2 + description: Stores the second 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA3 + description: Register 3 of BLOCK8 (KEY4). + addressOffset: 296 + size: 32 + fields: + - name: KEY4_DATA3 + description: Stores the third 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA4 + description: Register 4 of BLOCK8 (KEY4). + addressOffset: 300 + size: 32 + fields: + - name: KEY4_DATA4 + description: Stores the fourth 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA5 + description: Register 5 of BLOCK8 (KEY4). + addressOffset: 304 + size: 32 + fields: + - name: KEY4_DATA5 + description: Stores the fifth 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA6 + description: Register 6 of BLOCK8 (KEY4). + addressOffset: 308 + size: 32 + fields: + - name: KEY4_DATA6 + description: Stores the sixth 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA7 + description: Register 7 of BLOCK8 (KEY4). + addressOffset: 312 + size: 32 + fields: + - name: KEY4_DATA7 + description: Stores the seventh 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA0 + description: Register 0 of BLOCK9 (KEY5). + addressOffset: 316 + size: 32 + fields: + - name: KEY5_DATA0 + description: Stores the zeroth 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA1 + description: Register 1 of BLOCK9 (KEY5). + addressOffset: 320 + size: 32 + fields: + - name: KEY5_DATA1 + description: Stores the first 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA2 + description: Register 2 of BLOCK9 (KEY5). + addressOffset: 324 + size: 32 + fields: + - name: KEY5_DATA2 + description: Stores the second 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA3 + description: Register 3 of BLOCK9 (KEY5). + addressOffset: 328 + size: 32 + fields: + - name: KEY5_DATA3 + description: Stores the third 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA4 + description: Register 4 of BLOCK9 (KEY5). + addressOffset: 332 + size: 32 + fields: + - name: KEY5_DATA4 + description: Stores the fourth 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA5 + description: Register 5 of BLOCK9 (KEY5). + addressOffset: 336 + size: 32 + fields: + - name: KEY5_DATA5 + description: Stores the fifth 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA6 + description: Register 6 of BLOCK9 (KEY5). + addressOffset: 340 + size: 32 + fields: + - name: KEY5_DATA6 + description: Stores the sixth 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA7 + description: Register 7 of BLOCK9 (KEY5). + addressOffset: 344 + size: 32 + fields: + - name: KEY5_DATA7 + description: Stores the seventh 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA0 + description: Register 0 of BLOCK10 (system). + addressOffset: 348 + size: 32 + fields: + - name: SYS_DATA_PART2_0 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA1 + description: Register 1 of BLOCK9 (KEY5). + addressOffset: 352 + size: 32 + fields: + - name: SYS_DATA_PART2_1 + description: Stores the 1st 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA2 + description: Register 2 of BLOCK10 (system). + addressOffset: 356 + size: 32 + fields: + - name: SYS_DATA_PART2_2 + description: Stores the 2nd 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA3 + description: Register 3 of BLOCK10 (system). + addressOffset: 360 + size: 32 + fields: + - name: SYS_DATA_PART2_3 + description: Stores the 3rd 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA4 + description: Register 4 of BLOCK10 (system). + addressOffset: 364 + size: 32 + fields: + - name: SYS_DATA_PART2_4 + description: Stores the 4th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA5 + description: Register 5 of BLOCK10 (system). + addressOffset: 368 + size: 32 + fields: + - name: SYS_DATA_PART2_5 + description: Stores the 5th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA6 + description: Register 6 of BLOCK10 (system). + addressOffset: 372 + size: 32 + fields: + - name: SYS_DATA_PART2_6 + description: Stores the 6th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA7 + description: Register 7 of BLOCK10 (system). + addressOffset: 376 + size: 32 + fields: + - name: SYS_DATA_PART2_7 + description: Stores the 7th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_REPEAT_ERR0 + description: Programming error record register 0 of BLOCK0. + addressOffset: 380 + size: 32 + fields: + - name: RD_DIS_ERR + description: "If any bit in RD_DIS is 1, then it indicates a programming error." + bitOffset: 0 + bitWidth: 7 + access: read-only + - name: DIS_RTC_RAM_BOOT_ERR + description: "If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DIS_ICACHE_ERR + description: "If DIS_ICACHE is 1, then it indicates a programming error." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DIS_USB_JTAG_ERR + description: "If DIS_USB_JTAG is 1, then it indicates a programming error." + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_ICACHE_ERR + description: "If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error." + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: DIS_USB_DEVICE_ERR + description: "If DIS_USB_DEVICE is 1, then it indicates a programming error." + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: DIS_FORCE_DOWNLOAD_ERR + description: "If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error." + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED6_ERR + description: Reserved. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: DIS_CAN_ERR + description: "If DIS_CAN is 1, then it indicates a programming error." + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: JTAG_SEL_ENABLE_ERR + description: "If JTAG_SEL_ENABLE is 1, then it indicates a programming error." + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SOFT_DIS_JTAG_ERR + description: "If SOFT_DIS_JTAG is 1, then it indicates a programming error." + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: DIS_PAD_JTAG_ERR + description: "If DIS_PAD_JTAG is 1, then it indicates a programming error." + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR + description: "If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error." + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: USB_DREFH_ERR + description: "If any bit in USB_DREFH is 1, then it indicates a programming error." + bitOffset: 21 + bitWidth: 2 + access: read-only + - name: USB_DREFL_ERR + description: "If any bit in USB_DREFL is 1, then it indicates a programming error." + bitOffset: 23 + bitWidth: 2 + access: read-only + - name: USB_EXCHG_PINS_ERR + description: "If USB_EXCHG_PINS is 1, then it indicates a programming error." + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: VDD_SPI_AS_GPIO_ERR + description: "If VDD_SPI_AS_GPIO is 1, then it indicates a programming error." + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: BTLC_GPIO_ENABLE_ERR + description: "If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error." + bitOffset: 27 + bitWidth: 2 + access: read-only + - name: POWERGLITCH_EN_ERR + description: "If POWERGLITCH_EN is 1, then it indicates a programming error." + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: POWER_GLITCH_DSENSE_ERR + description: "If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error." + bitOffset: 30 + bitWidth: 2 + access: read-only + - register: + name: RD_REPEAT_ERR1 + description: Programming error record register 1 of BLOCK0. + addressOffset: 384 + size: 32 + fields: + - name: RPT4_RESERVED2_ERR + description: Reserved. + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: WDT_DELAY_SEL_ERR + description: "If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error." + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: SPI_BOOT_CRYPT_CNT_ERR + description: "If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error." + bitOffset: 18 + bitWidth: 3 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE0_ERR + description: "If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error." + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE1_ERR + description: "If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error." + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE2_ERR + description: "If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error." + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: KEY_PURPOSE_0_ERR + description: "If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error." + bitOffset: 24 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_1_ERR + description: "If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error." + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_REPEAT_ERR2 + description: Programming error record register 2 of BLOCK0. + addressOffset: 388 + size: 32 + fields: + - name: KEY_PURPOSE_2_ERR + description: "If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error." + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_3_ERR + description: "If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error." + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_4_ERR + description: "If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error." + bitOffset: 8 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_5_ERR + description: "If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error." + bitOffset: 12 + bitWidth: 4 + access: read-only + - name: RPT4_RESERVED3_ERR + description: Reserved. + bitOffset: 16 + bitWidth: 4 + access: read-only + - name: SECURE_BOOT_EN_ERR + description: "If SECURE_BOOT_EN is 1, then it indicates a programming error." + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_AGGRESSIVE_REVOKE_ERR + description: "If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error." + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED0_ERR + description: Reserved. + bitOffset: 22 + bitWidth: 6 + access: read-only + - name: FLASH_TPUW_ERR + description: "If any bit in FLASH_TPUM is 1, then it indicates a programming error." + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_REPEAT_ERR3 + description: Programming error record register 3 of BLOCK0. + addressOffset: 392 + size: 32 + fields: + - name: DIS_DOWNLOAD_MODE_ERR + description: "If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DIS_LEGACY_SPI_BOOT_ERR + description: "If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: UART_PRINT_CHANNEL_ERR + description: "If UART_PRINT_CHANNEL is 1, then it indicates a programming error." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FLASH_ECC_MODE_ERR + description: "If FLASH_ECC_MODE is 1, then it indicates a programming error." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DIS_USB_DOWNLOAD_MODE_ERR + description: "If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ENABLE_SECURITY_DOWNLOAD_ERR + description: "If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: UART_PRINT_CONTROL_ERR + description: "If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error." + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: PIN_POWER_SELECTION_ERR + description: "If PIN_POWER_SELECTION is 1, then it indicates a programming error." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: FLASH_TYPE_ERR + description: "If FLASH_TYPE is 1, then it indicates a programming error." + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: FLASH_PAGE_SIZE_ERR + description: "If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error." + bitOffset: 10 + bitWidth: 2 + access: read-only + - name: FLASH_ECC_EN_ERR + description: "If FLASH_ECC_EN_ERR is 1, then it indicates a programming error." + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: FORCE_SEND_RESUME_ERR + description: "If FORCE_SEND_RESUME is 1, then it indicates a programming error." + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SECURE_VERSION_ERR + description: "If any bit in SECURE_VERSION is 1, then it indicates a programming error." + bitOffset: 14 + bitWidth: 16 + access: read-only + - name: RPT4_RESERVED1_ERR + description: Reserved. + bitOffset: 30 + bitWidth: 2 + access: read-only + - register: + name: RD_REPEAT_ERR4 + description: Programming error record register 4 of BLOCK0. + addressOffset: 400 + size: 32 + fields: + - name: RPT4_RESERVED4_ERR + description: Reserved. + bitOffset: 0 + bitWidth: 24 + access: read-only + - register: + name: RD_RS_ERR0 + description: Programming error record register 0 of BLOCK1-10. + addressOffset: 448 + size: 32 + fields: + - name: MAC_SPI_8M_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: MAC_SPI_8M_FAIL + description: "0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SYS_PART1_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 4 + bitWidth: 3 + access: read-only + - name: SYS_PART1_FAIL + description: "0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: USR_DATA_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 8 + bitWidth: 3 + access: read-only + - name: USR_DATA_FAIL + description: "0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: KEY0_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 12 + bitWidth: 3 + access: read-only + - name: KEY0_FAIL + description: "0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6." + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: KEY1_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: KEY1_FAIL + description: "0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6." + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: KEY2_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 20 + bitWidth: 3 + access: read-only + - name: KEY2_FAIL + description: "0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6." + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: KEY3_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 24 + bitWidth: 3 + access: read-only + - name: KEY3_FAIL + description: "0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6." + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: KEY4_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 28 + bitWidth: 3 + access: read-only + - name: KEY4_FAIL + description: "0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: RD_RS_ERR1 + description: Programming error record register 1 of BLOCK1-10. + addressOffset: 452 + size: 32 + fields: + - name: KEY5_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: KEY5_FAIL + description: "0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SYS_PART2_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 4 + bitWidth: 3 + access: read-only + - name: SYS_PART2_FAIL + description: "0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 7 + bitWidth: 1 + access: read-only + - register: + name: CLK + description: eFuse clock configuration register. + addressOffset: 456 + size: 32 + resetValue: 2 + fields: + - name: EFUSE_MEM_FORCE_PD + description: Set this bit to force eFuse SRAM into power-saving mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_CLK_FORCE_ON + description: Set this bit and force to activate clock signal of eFuse SRAM. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EFUSE_MEM_FORCE_PU + description: Set this bit to force eFuse SRAM into working mode. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EN + description: Set this bit and force to enable clock signal of eFuse memory. + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: CONF + description: eFuse operation mode configuration register. + addressOffset: 460 + size: 32 + fields: + - name: OP_CODE + description: "0x5A5A: Operate programming command 0x5AA5: Operate read command." + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: STATUS + description: eFuse status register. + addressOffset: 464 + size: 32 + fields: + - name: STATE + description: Indicates the state of the eFuse state machine. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: OTP_LOAD_SW + description: The value of OTP_LOAD_SW. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: OTP_VDDQ_C_SYNC2 + description: The value of OTP_VDDQ_C_SYNC2. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OTP_STROBE_SW + description: The value of OTP_STROBE_SW. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OTP_CSB_SW + description: The value of OTP_CSB_SW. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OTP_PGENB_SW + description: The value of OTP_PGENB_SW. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: OTP_VDDQ_IS_SW + description: The value of OTP_VDDQ_IS_SW. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: REPEAT_ERR_CNT + description: Indicates the number of error bits during programming BLOCK0. + bitOffset: 10 + bitWidth: 8 + access: read-only + - register: + name: CMD + description: eFuse command register. + addressOffset: 468 + size: 32 + fields: + - name: READ_CMD + description: Set this bit to send read command. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PGM_CMD + description: Set this bit to send programming command. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BLK_NUM + description: "The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively." + bitOffset: 2 + bitWidth: 4 + access: read-write + - register: + name: INT_RAW + description: eFuse raw interrupt register. + addressOffset: 472 + size: 32 + fields: + - name: READ_DONE_INT_RAW + description: The raw bit signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PGM_DONE_INT_RAW + description: The raw bit signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: eFuse interrupt status register. + addressOffset: 476 + size: 32 + fields: + - name: READ_DONE_INT_ST + description: The status signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PGM_DONE_INT_ST + description: The status signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: eFuse interrupt enable register. + addressOffset: 480 + size: 32 + fields: + - name: READ_DONE_INT_ENA + description: The enable signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PGM_DONE_INT_ENA + description: The enable signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: eFuse interrupt clear register. + addressOffset: 484 + size: 32 + fields: + - name: READ_DONE_INT_CLR + description: The clear signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: PGM_DONE_INT_CLR + description: The clear signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: DAC_CONF + description: Controls the eFuse programming voltage. + addressOffset: 488 + size: 32 + resetValue: 130588 + fields: + - name: DAC_CLK_DIV + description: Controls the division factor of the rising clock of the programming voltage. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: DAC_CLK_PAD_SEL + description: "Don't care." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DAC_NUM + description: Controls the rising period of the programming voltage. + bitOffset: 9 + bitWidth: 8 + access: read-write + - name: OE_CLR + description: Reduces the power supply of the programming voltage. + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: RD_TIM_CONF + description: Configures read timing parameters. + addressOffset: 492 + size: 32 + resetValue: 301989888 + fields: + - name: READ_INIT_NUM + description: Configures the initial read time of eFuse. + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: WR_TIM_CONF1 + description: Configuration register 1 of eFuse programming timing parameters. + addressOffset: 496 + size: 32 + resetValue: 2654208 + fields: + - name: PWR_ON_NUM + description: Configures the power up time for VDDQ. + bitOffset: 8 + bitWidth: 16 + access: read-write + - register: + name: WR_TIM_CONF2 + description: Configuration register 2 of eFuse programming timing parameters. + addressOffset: 500 + size: 32 + resetValue: 400 + fields: + - name: PWR_OFF_NUM + description: Configures the power outage time for VDDQ. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: DATE + description: eFuse version register. + addressOffset: 508 + size: 32 + resetValue: 33583616 + fields: + - name: DATE + description: Stores eFuse version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: EXTMEM + description: External Memory + groupName: EXTMEM + baseAddress: 1611415552 + addressBlock: + - offset: 0 + size: 264 + usage: registers + registers: + - register: + name: ICACHE_CTRL + description: This description will be updated in the near future. + addressOffset: 0 + size: 32 + fields: + - name: ICACHE_ENABLE + description: "The bit is used to activate the data cache. 0: disable, 1: enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: ICACHE_CTRL1 + description: This description will be updated in the near future. + addressOffset: 4 + size: 32 + resetValue: 3 + fields: + - name: ICACHE_SHUT_IBUS + description: "The bit is used to disable core0 ibus, 0: enable, 1: disable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ICACHE_SHUT_DBUS + description: "The bit is used to disable core1 ibus, 0: enable, 1: disable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: ICACHE_TAG_POWER_CTRL + description: This description will be updated in the near future. + addressOffset: 8 + size: 32 + resetValue: 5 + fields: + - name: ICACHE_TAG_MEM_FORCE_ON + description: "The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ICACHE_TAG_MEM_FORCE_PD + description: "The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ICACHE_TAG_MEM_FORCE_PU + description: "The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up" + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: ICACHE_PRELOCK_CTRL + description: This description will be updated in the near future. + addressOffset: 12 + size: 32 + fields: + - name: ICACHE_PRELOCK_SCT0_EN + description: The bit is used to enable the first section of prelock function. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ICACHE_PRELOCK_SCT1_EN + description: The bit is used to enable the second section of prelock function. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: ICACHE_PRELOCK_SCT0_ADDR + description: This description will be updated in the near future. + addressOffset: 16 + size: 32 + fields: + - name: ICACHE_PRELOCK_SCT0_ADDR + description: "The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ICACHE_PRELOCK_SCT1_ADDR + description: This description will be updated in the near future. + addressOffset: 20 + size: 32 + fields: + - name: ICACHE_PRELOCK_SCT1_ADDR + description: "The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ICACHE_PRELOCK_SCT_SIZE + description: This description will be updated in the near future. + addressOffset: 24 + size: 32 + fields: + - name: ICACHE_PRELOCK_SCT1_SIZE + description: "The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG" + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: ICACHE_PRELOCK_SCT0_SIZE + description: "The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG" + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: ICACHE_LOCK_CTRL + description: This description will be updated in the near future. + addressOffset: 28 + size: 32 + resetValue: 4 + fields: + - name: ICACHE_LOCK_ENA + description: The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ICACHE_UNLOCK_ENA + description: The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ICACHE_LOCK_DONE + description: The bit is used to indicate unlock/lock operation is finished. + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: ICACHE_LOCK_ADDR + description: This description will be updated in the near future. + addressOffset: 32 + size: 32 + fields: + - name: ICACHE_LOCK_ADDR + description: The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ICACHE_LOCK_SIZE + description: This description will be updated in the near future. + addressOffset: 36 + size: 32 + fields: + - name: ICACHE_LOCK_SIZE + description: The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: ICACHE_SYNC_CTRL + description: This description will be updated in the near future. + addressOffset: 40 + size: 32 + resetValue: 1 + fields: + - name: ICACHE_INVALIDATE_ENA + description: The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ICACHE_SYNC_DONE + description: The bit is used to indicate invalidate operation is finished. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: ICACHE_SYNC_ADDR + description: This description will be updated in the near future. + addressOffset: 44 + size: 32 + fields: + - name: ICACHE_SYNC_ADDR + description: The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ICACHE_SYNC_SIZE + description: This description will be updated in the near future. + addressOffset: 48 + size: 32 + fields: + - name: ICACHE_SYNC_SIZE + description: The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG. + bitOffset: 0 + bitWidth: 23 + access: read-write + - register: + name: ICACHE_PRELOAD_CTRL + description: This description will be updated in the near future. + addressOffset: 52 + size: 32 + resetValue: 2 + fields: + - name: ICACHE_PRELOAD_ENA + description: The bit is used to enable preload operation. It will be cleared by hardware after preload operation done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ICACHE_PRELOAD_DONE + description: The bit is used to indicate preload operation is finished. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ICACHE_PRELOAD_ORDER + description: "The bit is used to configure the direction of preload operation. 1: descending, 0: ascending." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: ICACHE_PRELOAD_ADDR + description: This description will be updated in the near future. + addressOffset: 56 + size: 32 + fields: + - name: ICACHE_PRELOAD_ADDR + description: The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ICACHE_PRELOAD_SIZE + description: This description will be updated in the near future. + addressOffset: 60 + size: 32 + fields: + - name: ICACHE_PRELOAD_SIZE + description: The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG.. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: ICACHE_AUTOLOAD_CTRL + description: This description will be updated in the near future. + addressOffset: 64 + size: 32 + resetValue: 8 + fields: + - name: ICACHE_AUTOLOAD_SCT0_ENA + description: The bits are used to enable the first section for autoload operation. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ICACHE_AUTOLOAD_SCT1_ENA + description: The bits are used to enable the second section for autoload operation. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ICACHE_AUTOLOAD_ENA + description: "The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ICACHE_AUTOLOAD_DONE + description: The bit is used to indicate autoload operation is finished. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: ICACHE_AUTOLOAD_ORDER + description: "The bits are used to configure the direction of autoload. 1: descending, 0: ascending." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ICACHE_AUTOLOAD_RQST + description: "The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit." + bitOffset: 5 + bitWidth: 2 + access: read-write + - register: + name: ICACHE_AUTOLOAD_SCT0_ADDR + description: This description will be updated in the near future. + addressOffset: 68 + size: 32 + fields: + - name: ICACHE_AUTOLOAD_SCT0_ADDR + description: The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ICACHE_AUTOLOAD_SCT0_SIZE + description: This description will be updated in the near future. + addressOffset: 72 + size: 32 + fields: + - name: ICACHE_AUTOLOAD_SCT0_SIZE + description: The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena. + bitOffset: 0 + bitWidth: 27 + access: read-write + - register: + name: ICACHE_AUTOLOAD_SCT1_ADDR + description: This description will be updated in the near future. + addressOffset: 76 + size: 32 + fields: + - name: ICACHE_AUTOLOAD_SCT1_ADDR + description: The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ICACHE_AUTOLOAD_SCT1_SIZE + description: This description will be updated in the near future. + addressOffset: 80 + size: 32 + fields: + - name: ICACHE_AUTOLOAD_SCT1_SIZE + description: The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena. + bitOffset: 0 + bitWidth: 27 + access: read-write + - register: + name: IBUS_TO_FLASH_START_VADDR + description: This description will be updated in the near future. + addressOffset: 84 + size: 32 + resetValue: 1107296256 + fields: + - name: IBUS_TO_FLASH_START_VADDR + description: The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: IBUS_TO_FLASH_END_VADDR + description: This description will be updated in the near future. + addressOffset: 88 + size: 32 + resetValue: 1115684863 + fields: + - name: IBUS_TO_FLASH_END_VADDR + description: The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DBUS_TO_FLASH_START_VADDR + description: This description will be updated in the near future. + addressOffset: 92 + size: 32 + resetValue: 1006632960 + fields: + - name: DBUS_TO_FLASH_START_VADDR + description: The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DBUS_TO_FLASH_END_VADDR + description: This description will be updated in the near future. + addressOffset: 96 + size: 32 + resetValue: 1015021567 + fields: + - name: DBUS_TO_FLASH_END_VADDR + description: The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CACHE_ACS_CNT_CLR + description: This description will be updated in the near future. + addressOffset: 100 + size: 32 + fields: + - name: IBUS_ACS_CNT_CLR + description: The bit is used to clear ibus counter. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: DBUS_ACS_CNT_CLR + description: The bit is used to clear dbus counter. + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: IBUS_ACS_MISS_CNT + description: This description will be updated in the near future. + addressOffset: 104 + size: 32 + fields: + - name: IBUS_ACS_MISS_CNT + description: The bits are used to count the number of the cache miss caused by ibus access flash. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IBUS_ACS_CNT + description: This description will be updated in the near future. + addressOffset: 108 + size: 32 + fields: + - name: IBUS_ACS_CNT + description: The bits are used to count the number of ibus access flash through icache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DBUS_ACS_FLASH_MISS_CNT + description: This description will be updated in the near future. + addressOffset: 112 + size: 32 + fields: + - name: DBUS_ACS_FLASH_MISS_CNT + description: The bits are used to count the number of the cache miss caused by dbus access flash. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DBUS_ACS_CNT + description: This description will be updated in the near future. + addressOffset: 116 + size: 32 + fields: + - name: DBUS_ACS_CNT + description: The bits are used to count the number of dbus access flash through icache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CACHE_ILG_INT_ENA + description: This description will be updated in the near future. + addressOffset: 120 + size: 32 + fields: + - name: ICACHE_SYNC_OP_FAULT_INT_ENA + description: The bit is used to enable interrupt by sync configurations fault. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ICACHE_PRELOAD_OP_FAULT_INT_ENA + description: The bit is used to enable interrupt by preload configurations fault. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MMU_ENTRY_FAULT_INT_ENA + description: The bit is used to enable interrupt by mmu entry fault. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: IBUS_CNT_OVF_INT_ENA + description: The bit is used to enable interrupt by ibus counter overflow. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DBUS_CNT_OVF_INT_ENA + description: The bit is used to enable interrupt by dbus counter overflow. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: CACHE_ILG_INT_CLR + description: This description will be updated in the near future. + addressOffset: 124 + size: 32 + fields: + - name: ICACHE_SYNC_OP_FAULT_INT_CLR + description: The bit is used to clear interrupt by sync configurations fault. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ICACHE_PRELOAD_OP_FAULT_INT_CLR + description: The bit is used to clear interrupt by preload configurations fault. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: MMU_ENTRY_FAULT_INT_CLR + description: The bit is used to clear interrupt by mmu entry fault. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: IBUS_CNT_OVF_INT_CLR + description: The bit is used to clear interrupt by ibus counter overflow. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: DBUS_CNT_OVF_INT_CLR + description: The bit is used to clear interrupt by dbus counter overflow. + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: CACHE_ILG_INT_ST + description: This description will be updated in the near future. + addressOffset: 128 + size: 32 + fields: + - name: ICACHE_SYNC_OP_FAULT_ST + description: The bit is used to indicate interrupt by sync configurations fault. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ICACHE_PRELOAD_OP_FAULT_ST + description: The bit is used to indicate interrupt by preload configurations fault. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: MMU_ENTRY_FAULT_ST + description: The bit is used to indicate interrupt by mmu entry fault. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: IBUS_ACS_CNT_OVF_ST + description: The bit is used to indicate interrupt by ibus access flash/spiram counter overflow. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IBUS_ACS_MISS_CNT_OVF_ST + description: The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DBUS_ACS_CNT_OVF_ST + description: The bit is used to indicate interrupt by dbus access flash/spiram counter overflow. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: DBUS_ACS_FLASH_MISS_CNT_OVF_ST + description: The bit is used to indicate interrupt by dbus access flash miss counter overflow. + bitOffset: 10 + bitWidth: 1 + access: read-only + - register: + name: CORE0_ACS_CACHE_INT_ENA + description: This description will be updated in the near future. + addressOffset: 132 + size: 32 + fields: + - name: CORE0_IBUS_ACS_MSK_IC_INT_ENA + description: The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE0_IBUS_WR_IC_INT_ENA + description: The bit is used to enable interrupt by ibus trying to write icache + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CORE0_IBUS_REJECT_INT_ENA + description: The bit is used to enable interrupt by authentication fail. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CORE0_DBUS_ACS_MSK_IC_INT_ENA + description: The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CORE0_DBUS_REJECT_INT_ENA + description: The bit is used to enable interrupt by authentication fail. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CORE0_DBUS_WR_IC_INT_ENA + description: The bit is used to enable interrupt by dbus trying to write icache + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: CORE0_ACS_CACHE_INT_CLR + description: This description will be updated in the near future. + addressOffset: 136 + size: 32 + fields: + - name: CORE0_IBUS_ACS_MSK_IC_INT_CLR + description: The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CORE0_IBUS_WR_IC_INT_CLR + description: The bit is used to clear interrupt by ibus trying to write icache + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CORE0_IBUS_REJECT_INT_CLR + description: The bit is used to clear interrupt by authentication fail. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CORE0_DBUS_ACS_MSK_IC_INT_CLR + description: The bit is used to clear interrupt by cpu access icache while the corresponding dbus is disabled or icache is disabled which include speculative access. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: CORE0_DBUS_REJECT_INT_CLR + description: The bit is used to clear interrupt by authentication fail. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: CORE0_DBUS_WR_IC_INT_CLR + description: The bit is used to clear interrupt by dbus trying to write icache + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: CORE0_ACS_CACHE_INT_ST + description: This description will be updated in the near future. + addressOffset: 140 + size: 32 + fields: + - name: CORE0_IBUS_ACS_MSK_ICACHE_ST + description: The bit is used to indicate interrupt by cpu access icache while the core0_ibus is disabled or icache is disabled which include speculative access. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE0_IBUS_WR_ICACHE_ST + description: The bit is used to indicate interrupt by ibus trying to write icache + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CORE0_IBUS_REJECT_ST + description: The bit is used to indicate interrupt by authentication fail. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CORE0_DBUS_ACS_MSK_ICACHE_ST + description: The bit is used to indicate interrupt by cpu access icache while the core0_dbus is disabled or icache is disabled which include speculative access. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: CORE0_DBUS_REJECT_ST + description: The bit is used to indicate interrupt by authentication fail. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: CORE0_DBUS_WR_ICACHE_ST + description: The bit is used to indicate interrupt by dbus trying to write icache + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: CORE0_DBUS_REJECT_ST + description: This description will be updated in the near future. + addressOffset: 144 + size: 32 + fields: + - name: CORE0_DBUS_ATTR + description: "The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able." + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: CORE0_DBUS_WORLD + description: "The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1" + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: CORE0_DBUS_REJECT_VADDR + description: This description will be updated in the near future. + addressOffset: 148 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE0_DBUS_VADDR + description: The bits are used to indicate the virtual address of CPU access dbus when authentication fail. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE0_IBUS_REJECT_ST + description: This description will be updated in the near future. + addressOffset: 152 + size: 32 + fields: + - name: CORE0_IBUS_ATTR + description: "The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able" + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: CORE0_IBUS_WORLD + description: "The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1" + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: CORE0_IBUS_REJECT_VADDR + description: This description will be updated in the near future. + addressOffset: 156 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE0_IBUS_VADDR + description: The bits are used to indicate the virtual address of CPU access ibus when authentication fail. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CACHE_MMU_FAULT_CONTENT + description: This description will be updated in the near future. + addressOffset: 160 + size: 32 + fields: + - name: CACHE_MMU_FAULT_CONTENT + description: The bits are used to indicate the content of mmu entry which cause mmu fault.. + bitOffset: 0 + bitWidth: 10 + access: read-only + - name: CACHE_MMU_FAULT_CODE + description: "The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache." + bitOffset: 10 + bitWidth: 4 + access: read-only + - register: + name: CACHE_MMU_FAULT_VADDR + description: This description will be updated in the near future. + addressOffset: 164 + size: 32 + fields: + - name: CACHE_MMU_FAULT_VADDR + description: The bits are used to indicate the virtual address which cause mmu fault.. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CACHE_WRAP_AROUND_CTRL + description: This description will be updated in the near future. + addressOffset: 168 + size: 32 + fields: + - name: CACHE_FLASH_WRAP_AROUND + description: The bit is used to enable wrap around mode when read data from flash. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CACHE_MMU_POWER_CTRL + description: This description will be updated in the near future. + addressOffset: 172 + size: 32 + resetValue: 5 + fields: + - name: CACHE_MMU_MEM_FORCE_ON + description: "The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CACHE_MMU_MEM_FORCE_PD + description: "The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CACHE_MMU_MEM_FORCE_PU + description: "The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up" + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: CACHE_STATE + description: This description will be updated in the near future. + addressOffset: 176 + size: 32 + resetValue: 1 + fields: + - name: ICACHE_STATE + description: "The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state" + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE + description: This description will be updated in the near future. + addressOffset: 180 + size: 32 + fields: + - name: RECORD_DISABLE_DB_ENCRYPT + description: Reserved. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RECORD_DISABLE_G0CB_DECRYPT + description: Reserved. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON + description: This description will be updated in the near future. + addressOffset: 184 + size: 32 + resetValue: 7 + fields: + - name: CLK_FORCE_ON_MANUAL_CRYPT + description: "The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CLK_FORCE_ON_AUTO_CRYPT + description: "The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CLK_FORCE_ON_CRYPT + description: "The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: CACHE_PRELOAD_INT_CTRL + description: This description will be updated in the near future. + addressOffset: 188 + size: 32 + fields: + - name: ICACHE_PRELOAD_INT_ST + description: The bit is used to indicate the interrupt by icache pre-load done. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ICACHE_PRELOAD_INT_ENA + description: The bit is used to enable the interrupt by icache pre-load done. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ICACHE_PRELOAD_INT_CLR + description: The bit is used to clear the interrupt by icache pre-load done. + bitOffset: 2 + bitWidth: 1 + access: write-only + - register: + name: CACHE_SYNC_INT_CTRL + description: This description will be updated in the near future. + addressOffset: 192 + size: 32 + fields: + - name: ICACHE_SYNC_INT_ST + description: The bit is used to indicate the interrupt by icache sync done. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ICACHE_SYNC_INT_ENA + description: The bit is used to enable the interrupt by icache sync done. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ICACHE_SYNC_INT_CLR + description: The bit is used to clear the interrupt by icache sync done. + bitOffset: 2 + bitWidth: 1 + access: write-only + - register: + name: CACHE_MMU_OWNER + description: This description will be updated in the near future. + addressOffset: 196 + size: 32 + fields: + - name: CACHE_MMU_OWNER + description: "The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus" + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CACHE_CONF_MISC + description: This description will be updated in the near future. + addressOffset: 200 + size: 32 + resetValue: 7 + fields: + - name: CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT + description: The bit is used to disable checking mmu entry fault by preload operation. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT + description: The bit is used to disable checking mmu entry fault by sync operation. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CACHE_TRACE_ENA + description: The bit is used to enable cache trace function. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: ICACHE_FREEZE + description: This description will be updated in the near future. + addressOffset: 204 + size: 32 + fields: + - name: ENA + description: The bit is used to enable icache freeze mode + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MODE + description: "The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DONE + description: The bit is used to indicate icache freeze success + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: ICACHE_ATOMIC_OPERATE_ENA + description: This description will be updated in the near future. + addressOffset: 208 + size: 32 + resetValue: 1 + fields: + - name: ICACHE_ATOMIC_OPERATE_ENA + description: "The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CACHE_REQUEST + description: This description will be updated in the near future. + addressOffset: 212 + size: 32 + fields: + - name: BYPASS + description: The bit is used to disable request recording which could cause performance issue + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: IBUS_PMS_TBL_LOCK + description: This description will be updated in the near future. + addressOffset: 216 + size: 32 + fields: + - name: IBUS_PMS_LOCK + description: The bit is used to configure the ibus permission control section boundary0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: IBUS_PMS_TBL_BOUNDARY0 + description: This description will be updated in the near future. + addressOffset: 220 + size: 32 + fields: + - name: IBUS_PMS_BOUNDARY0 + description: The bit is used to configure the ibus permission control section boundary0 + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: IBUS_PMS_TBL_BOUNDARY1 + description: This description will be updated in the near future. + addressOffset: 224 + size: 32 + resetValue: 2048 + fields: + - name: IBUS_PMS_BOUNDARY1 + description: The bit is used to configure the ibus permission control section boundary1 + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: IBUS_PMS_TBL_BOUNDARY2 + description: This description will be updated in the near future. + addressOffset: 228 + size: 32 + resetValue: 2048 + fields: + - name: IBUS_PMS_BOUNDARY2 + description: The bit is used to configure the ibus permission control section boundary2 + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: IBUS_PMS_TBL_ATTR + description: This description will be updated in the near future. + addressOffset: 232 + size: 32 + resetValue: 255 + fields: + - name: IBUS_PMS_SCT1_ATTR + description: "The bit is used to configure attribute of the ibus permission control section1, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1" + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: IBUS_PMS_SCT2_ATTR + description: "The bit is used to configure attribute of the ibus permission control section2, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1" + bitOffset: 4 + bitWidth: 4 + access: read-write + - register: + name: DBUS_PMS_TBL_LOCK + description: This description will be updated in the near future. + addressOffset: 236 + size: 32 + fields: + - name: DBUS_PMS_LOCK + description: The bit is used to configure the ibus permission control section boundary0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DBUS_PMS_TBL_BOUNDARY0 + description: This description will be updated in the near future. + addressOffset: 240 + size: 32 + fields: + - name: DBUS_PMS_BOUNDARY0 + description: The bit is used to configure the dbus permission control section boundary0 + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: DBUS_PMS_TBL_BOUNDARY1 + description: This description will be updated in the near future. + addressOffset: 244 + size: 32 + resetValue: 2048 + fields: + - name: DBUS_PMS_BOUNDARY1 + description: The bit is used to configure the dbus permission control section boundary1 + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: DBUS_PMS_TBL_BOUNDARY2 + description: This description will be updated in the near future. + addressOffset: 248 + size: 32 + resetValue: 2048 + fields: + - name: DBUS_PMS_BOUNDARY2 + description: The bit is used to configure the dbus permission control section boundary2 + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: DBUS_PMS_TBL_ATTR + description: This description will be updated in the near future. + addressOffset: 252 + size: 32 + resetValue: 15 + fields: + - name: DBUS_PMS_SCT1_ATTR + description: "The bit is used to configure attribute of the dbus permission control section1, bit0: load in world0, bit2: load in world1" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DBUS_PMS_SCT2_ATTR + description: "The bit is used to configure attribute of the dbus permission control section2, bit0: load in world0, bit2: load in world1" + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: CLOCK_GATE + description: This description will be updated in the near future. + addressOffset: 256 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: clock gate enable. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: REG_DATE + description: This description will be updated in the near future. + addressOffset: 1020 + size: 32 + resetValue: 33583456 + fields: + - name: DATE + description: version information + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: GPIO + description: General Purpose Input/Output + groupName: GPIO + baseAddress: 1610629120 + addressBlock: + - offset: 0 + size: 796 + usage: registers + interrupt: + - name: GPIO + value: 16 + - name: GPIO_NMI + value: 17 + registers: + - register: + name: BT_SELECT + description: GPIO bit select register + addressOffset: 0 + size: 32 + fields: + - name: BT_SEL + description: GPIO bit select register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: OUT + description: GPIO output register + addressOffset: 4 + size: 32 + fields: + - name: DATA_ORIG + description: GPIO output register for GPIO0-25 + bitOffset: 0 + bitWidth: 26 + access: read-write + - register: + name: OUT_W1TS + description: GPIO output set register + addressOffset: 8 + size: 32 + fields: + - name: OUT_W1TS + description: GPIO output set register for GPIO0-25 + bitOffset: 0 + bitWidth: 26 + access: write-only + - register: + name: OUT_W1TC + description: GPIO output clear register + addressOffset: 12 + size: 32 + fields: + - name: OUT_W1TC + description: GPIO output clear register for GPIO0-25 + bitOffset: 0 + bitWidth: 26 + access: write-only + - register: + name: SDIO_SELECT + description: GPIO sdio select register + addressOffset: 28 + size: 32 + fields: + - name: SDIO_SEL + description: GPIO sdio select register + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: ENABLE + description: GPIO output enable register + addressOffset: 32 + size: 32 + fields: + - name: DATA + description: GPIO output enable register for GPIO0-25 + bitOffset: 0 + bitWidth: 26 + access: read-write + - register: + name: ENABLE_W1TS + description: GPIO output enable set register + addressOffset: 36 + size: 32 + fields: + - name: ENABLE_W1TS + description: GPIO output enable set register for GPIO0-25 + bitOffset: 0 + bitWidth: 26 + access: write-only + - register: + name: ENABLE_W1TC + description: GPIO output enable clear register + addressOffset: 40 + size: 32 + fields: + - name: ENABLE_W1TC + description: GPIO output enable clear register for GPIO0-25 + bitOffset: 0 + bitWidth: 26 + access: write-only + - register: + name: STRAP + description: pad strapping register + addressOffset: 56 + size: 32 + fields: + - name: STRAPPING + description: pad strapping register + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: IN + description: GPIO input register + addressOffset: 60 + size: 32 + fields: + - name: DATA_NEXT + description: GPIO input register for GPIO0-25 + bitOffset: 0 + bitWidth: 26 + access: read-only + - register: + name: STATUS + description: GPIO interrupt status register + addressOffset: 68 + size: 32 + fields: + - name: INTERRUPT + description: GPIO interrupt status register for GPIO0-25 + bitOffset: 0 + bitWidth: 26 + access: read-write + - register: + name: STATUS_W1TS + description: GPIO interrupt status set register + addressOffset: 72 + size: 32 + fields: + - name: STATUS_W1TS + description: GPIO interrupt status set register for GPIO0-25 + bitOffset: 0 + bitWidth: 26 + access: write-only + - register: + name: STATUS_W1TC + description: GPIO interrupt status clear register + addressOffset: 76 + size: 32 + fields: + - name: STATUS_W1TC + description: GPIO interrupt status clear register for GPIO0-25 + bitOffset: 0 + bitWidth: 26 + access: write-only + - register: + name: PCPU_INT + description: GPIO PRO_CPU interrupt status register + addressOffset: 92 + size: 32 + fields: + - name: PROCPU_INT + description: GPIO PRO_CPU interrupt status register for GPIO0-25 + bitOffset: 0 + bitWidth: 26 + access: read-only + - register: + name: PCPU_NMI_INT + description: GPIO PRO_CPU(not shielded) interrupt status register + addressOffset: 96 + size: 32 + fields: + - name: PROCPU_NMI_INT + description: GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-25 + bitOffset: 0 + bitWidth: 26 + access: read-only + - register: + name: CPUSDIO_INT + description: GPIO CPUSDIO interrupt status register + addressOffset: 100 + size: 32 + fields: + - name: SDIO_INT + description: GPIO CPUSDIO interrupt status register for GPIO0-25 + bitOffset: 0 + bitWidth: 26 + access: read-only + - register: + dim: 26 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25" + name: PIN%s + description: GPIO pin configuration register + addressOffset: 116 + size: 32 + fields: + - name: SYNC2_BYPASS + description: "set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: PAD_DRIVER + description: "set this bit to select pad driver. 1:open-drain. 0:normal." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SYNC1_BYPASS + description: "set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge." + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: INT_TYPE + description: "set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CONFIG + description: reserved + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: INT_ENA + description: set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. + bitOffset: 13 + bitWidth: 5 + access: read-write + - register: + name: STATUS_NEXT + description: GPIO interrupt source register + addressOffset: 332 + size: 32 + fields: + - name: STATUS_INTERRUPT_NEXT + description: GPIO interrupt source register for GPIO0-25 + bitOffset: 0 + bitWidth: 26 + access: read-only + - register: + dim: 128 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" + name: FUNC%s_IN_SEL_CFG + description: GPIO input function configuration register + addressOffset: 340 + size: 32 + fields: + - name: IN_SEL + description: "set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level." + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: IN_INV_SEL + description: "set this bit to invert input signal. 1:invert. 0:not invert." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SEL + description: "set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO." + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + dim: 26 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25" + name: FUNC%s_OUT_SEL_CFG + description: GPIO output function select register + addressOffset: 1364 + size: 32 + resetValue: 128 + fields: + - name: OUT_SEL + description: "The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n]." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: INV_SEL + description: "set this bit to invert output signal.1:invert.0:not invert." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: OEN_SEL + description: "set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OEN_INV_SEL + description: "set this bit to invert output enable signal.1:invert.0:not invert." + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: CLOCK_GATE + description: GPIO clock gate register + addressOffset: 1580 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: set this bit to enable GPIO clock gate + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: REG_DATE + description: GPIO version register + addressOffset: 1788 + size: 32 + resetValue: 33579312 + fields: + - name: REG_DATE + description: version register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: GPIO_SD + description: Sigma-Delta Modulation + groupName: GPIOSD + baseAddress: 1610632960 + addressBlock: + - offset: 0 + size: 28 + usage: registers + registers: + - register: + dim: 4 + dimIncrement: 4 + name: SIGMADELTA%s + description: Duty Cycle Configure Register of SDM%s + addressOffset: 0 + size: 32 + resetValue: 65280 + fields: + - name: SD0_IN + description: This field is used to configure the duty cycle of sigma delta modulation output. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SD0_PRESCALE + description: This field is used to set a divider value to divide APB clock. + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: SIGMADELTA_CG + description: Clock Gating Configure Register + addressOffset: 32 + size: 32 + fields: + - name: CLK_EN + description: Clock enable bit of configuration registers for sigma delta modulation. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SIGMADELTA_MISC + description: MISC Register + addressOffset: 36 + size: 32 + fields: + - name: FUNCTION_CLK_EN + description: Clock enable bit of sigma delta modulation. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI_SWAP + description: Reserved. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SIGMADELTA_VERSION + description: Version Control Register + addressOffset: 40 + size: 32 + resetValue: 33579568 + fields: + - name: GPIO_SD_DATE + description: Version control register. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: HMAC + description: HMAC (Hash-based Message Authentication Code) Accelerator + groupName: HMAC + baseAddress: 1610866688 + addressBlock: + - offset: 0 + size: 164 + usage: registers + registers: + - register: + name: SET_START + description: Process control register 0. + addressOffset: 64 + size: 32 + fields: + - name: SET_START + description: Start hmac operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_PARA_PURPOSE + description: Configure purpose. + addressOffset: 68 + size: 32 + fields: + - name: PURPOSE_SET + description: Set hmac parameter purpose. + bitOffset: 0 + bitWidth: 4 + access: write-only + - register: + name: SET_PARA_KEY + description: Configure key. + addressOffset: 72 + size: 32 + fields: + - name: KEY_SET + description: Set hmac parameter key. + bitOffset: 0 + bitWidth: 3 + access: write-only + - register: + name: SET_PARA_FINISH + description: Finish initial configuration. + addressOffset: 76 + size: 32 + fields: + - name: SET_PARA_END + description: Finish hmac configuration. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_MESSAGE_ONE + description: Process control register 1. + addressOffset: 80 + size: 32 + fields: + - name: SET_TEXT_ONE + description: Call SHA to calculate one message block. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_MESSAGE_ING + description: Process control register 2. + addressOffset: 84 + size: 32 + fields: + - name: SET_TEXT_ING + description: Continue typical hmac. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_MESSAGE_END + description: Process control register 3. + addressOffset: 88 + size: 32 + fields: + - name: SET_TEXT_END + description: Start hardware padding. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_RESULT_FINISH + description: Process control register 4. + addressOffset: 92 + size: 32 + fields: + - name: SET_RESULT_END + description: "After read result from upstream, then let hmac back to idle." + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_INVALIDATE_JTAG + description: Invalidate register 0. + addressOffset: 96 + size: 32 + fields: + - name: SET_INVALIDATE_JTAG + description: Clear result from hmac downstream JTAG. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_INVALIDATE_DS + description: Invalidate register 1. + addressOffset: 100 + size: 32 + fields: + - name: SET_INVALIDATE_DS + description: Clear result from hmac downstream DS. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: QUERY_ERROR + description: Error register. + addressOffset: 104 + size: 32 + fields: + - name: QUERY_CHECK + description: "Hmac configuration state. 0: key are agree with purpose. 1: error" + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: QUERY_BUSY + description: Busy register. + addressOffset: 108 + size: 32 + fields: + - name: BUSY_STATE + description: "Hmac state. 1'b0: idle. 1'b1: busy" + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + dim: 16 + dimIncrement: 4 + name: "WR_MESSAGE_MEM[%s]" + description: Message block memory. + addressOffset: 128 + size: 32 + - register: + dim: 8 + dimIncrement: 4 + name: "RD_RESULT_MEM[%s]" + description: Result from upstream. + addressOffset: 192 + size: 32 + - register: + name: SET_MESSAGE_PAD + description: Process control register 5. + addressOffset: 240 + size: 32 + fields: + - name: SET_TEXT_PAD + description: Start software padding. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: ONE_BLOCK + description: Process control register 6. + addressOffset: 244 + size: 32 + fields: + - name: SET_ONE_BLOCK + description: "Don't have to do padding." + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SOFT_JTAG_CTRL + description: Jtag register 0. + addressOffset: 248 + size: 32 + fields: + - name: SOFT_JTAG_CTRL + description: Turn on JTAG verification. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: WR_JTAG + description: Jtag register 1. + addressOffset: 252 + size: 32 + fields: + - name: WR_JTAG + description: 32-bit of key to be compared. + bitOffset: 0 + bitWidth: 32 + access: write-only + - name: I2C0 + description: I2C (Inter-Integrated Circuit) Controller 0 + groupName: I2C + baseAddress: 1610690560 + addressBlock: + - offset: 0 + size: 144 + usage: registers + interrupt: + - name: I2C_MASTER + value: 11 + - name: I2C_EXT0 + value: 29 + registers: + - register: + name: SCL_LOW_PERIOD + description: I2C_SCL_LOW_PERIOD_REG + addressOffset: 0 + size: 32 + fields: + - name: SCL_LOW_PERIOD + description: reg_scl_low_period + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: CTR + description: I2C_CTR_REG + addressOffset: 4 + size: 32 + resetValue: 523 + fields: + - name: SDA_FORCE_OUT + description: reg_sda_force_out + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_FORCE_OUT + description: reg_scl_force_out + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SAMPLE_SCL_LEVEL + description: reg_sample_scl_level + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_FULL_ACK_LEVEL + description: reg_rx_full_ack_level + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MS_MODE + description: reg_ms_mode + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TRANS_START + description: reg_trans_start + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TX_LSB_FIRST + description: reg_tx_lsb_first + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_LSB_FIRST + description: reg_rx_lsb_first + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: reg_clk_en + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ARBITRATION_EN + description: reg_arbitration_en + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FSM_RST + description: reg_fsm_rst + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: CONF_UPGATE + description: reg_conf_upgate + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: SLV_TX_AUTO_START_EN + description: reg_slv_tx_auto_start_en + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: ADDR_10BIT_RW_CHECK_EN + description: reg_addr_10bit_rw_check_en + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: ADDR_BROADCASTING_EN + description: reg_addr_broadcasting_en + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: SR + description: I2C_SR_REG + addressOffset: 8 + size: 32 + resetValue: 49152 + fields: + - name: RESP_REC + description: reg_resp_rec + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SLAVE_RW + description: reg_slave_rw + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ARB_LOST + description: reg_arb_lost + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BUS_BUSY + description: reg_bus_busy + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SLAVE_ADDRESSED + description: reg_slave_addressed + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: RXFIFO_CNT + description: reg_rxfifo_cnt + bitOffset: 8 + bitWidth: 6 + access: read-only + - name: STRETCH_CAUSE + description: reg_stretch_cause + bitOffset: 14 + bitWidth: 2 + access: read-only + - name: TXFIFO_CNT + description: reg_txfifo_cnt + bitOffset: 18 + bitWidth: 6 + access: read-only + - name: SCL_MAIN_STATE_LAST + description: reg_scl_main_state_last + bitOffset: 24 + bitWidth: 3 + access: read-only + - name: SCL_STATE_LAST + description: reg_scl_state_last + bitOffset: 28 + bitWidth: 3 + access: read-only + - register: + name: TO + description: I2C_TO_REG + addressOffset: 12 + size: 32 + resetValue: 16 + fields: + - name: TIME_OUT_VALUE + description: reg_time_out_value + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: TIME_OUT_EN + description: reg_time_out_en + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: SLAVE_ADDR + description: I2C_SLAVE_ADDR_REG + addressOffset: 16 + size: 32 + fields: + - name: SLAVE_ADDR + description: reg_slave_addr + bitOffset: 0 + bitWidth: 15 + access: read-write + - name: ADDR_10BIT_EN + description: reg_addr_10bit_en + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: FIFO_ST + description: I2C_FIFO_ST_REG + addressOffset: 20 + size: 32 + fields: + - name: RXFIFO_RADDR + description: reg_rxfifo_raddr + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: RXFIFO_WADDR + description: reg_rxfifo_waddr + bitOffset: 5 + bitWidth: 5 + access: read-only + - name: TXFIFO_RADDR + description: reg_txfifo_raddr + bitOffset: 10 + bitWidth: 5 + access: read-only + - name: TXFIFO_WADDR + description: reg_txfifo_waddr + bitOffset: 15 + bitWidth: 5 + access: read-only + - name: SLAVE_RW_POINT + description: reg_slave_rw_point + bitOffset: 22 + bitWidth: 8 + access: read-only + - register: + name: FIFO_CONF + description: I2C_FIFO_CONF_REG + addressOffset: 24 + size: 32 + resetValue: 16523 + fields: + - name: RXFIFO_WM_THRHD + description: reg_rxfifo_wm_thrhd + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: TXFIFO_WM_THRHD + description: reg_txfifo_wm_thrhd + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: NONFIFO_EN + description: reg_nonfifo_en + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FIFO_ADDR_CFG_EN + description: reg_fifo_addr_cfg_en + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RX_FIFO_RST + description: reg_rx_fifo_rst + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_FIFO_RST + description: reg_tx_fifo_rst + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FIFO_PRT_EN + description: reg_fifo_prt_en + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DATA + description: I2C_FIFO_DATA_REG + addressOffset: 28 + size: 32 + fields: + - name: FIFO_RDATA + description: reg_fifo_rdata + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: INT_RAW + description: I2C_INT_RAW_REG + addressOffset: 32 + size: 32 + resetValue: 2 + fields: + - name: RXFIFO_WM_INT_RAW + description: reg_rxfifo_wm_int_raw + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_WM_INT_RAW + description: reg_txfifo_wm_int_raw + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_RAW + description: reg_rxfifo_ovf_int_raw + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: END_DETECT_INT_RAW + description: reg_end_detect_int_raw + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS_DONE_INT_RAW + description: reg_byte_trans_done_int_raw + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_RAW + description: reg_arbitration_lost_int_raw + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: MST_TXFIFO_UDF_INT_RAW + description: reg_mst_txfifo_udf_int_raw + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_RAW + description: reg_trans_complete_int_raw + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_RAW + description: reg_time_out_int_raw + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TRANS_START_INT_RAW + description: reg_trans_start_int_raw + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: NACK_INT_RAW + description: reg_nack_int_raw + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: TXFIFO_OVF_INT_RAW + description: reg_txfifo_ovf_int_raw + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: RXFIFO_UDF_INT_RAW + description: reg_rxfifo_udf_int_raw + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SCL_ST_TO_INT_RAW + description: reg_scl_st_to_int_raw + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SCL_MAIN_ST_TO_INT_RAW + description: reg_scl_main_st_to_int_raw + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DET_START_INT_RAW + description: reg_det_start_int_raw + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLAVE_STRETCH_INT_RAW + description: reg_slave_stretch_int_raw + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: GENERAL_CALL_INT_RAW + description: reg_general_call_int_raw + bitOffset: 17 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: I2C_INT_CLR_REG + addressOffset: 36 + size: 32 + fields: + - name: RXFIFO_WM_INT_CLR + description: reg_rxfifo_wm_int_clr + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TXFIFO_WM_INT_CLR + description: reg_txfifo_wm_int_clr + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RXFIFO_OVF_INT_CLR + description: reg_rxfifo_ovf_int_clr + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: END_DETECT_INT_CLR + description: reg_end_detect_int_clr + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: BYTE_TRANS_DONE_INT_CLR + description: reg_byte_trans_done_int_clr + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: ARBITRATION_LOST_INT_CLR + description: reg_arbitration_lost_int_clr + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: MST_TXFIFO_UDF_INT_CLR + description: reg_mst_txfifo_udf_int_clr + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TRANS_COMPLETE_INT_CLR + description: reg_trans_complete_int_clr + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: TIME_OUT_INT_CLR + description: reg_time_out_int_clr + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: TRANS_START_INT_CLR + description: reg_trans_start_int_clr + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: NACK_INT_CLR + description: reg_nack_int_clr + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: TXFIFO_OVF_INT_CLR + description: reg_txfifo_ovf_int_clr + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: RXFIFO_UDF_INT_CLR + description: reg_rxfifo_udf_int_clr + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: SCL_ST_TO_INT_CLR + description: reg_scl_st_to_int_clr + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SCL_MAIN_ST_TO_INT_CLR + description: reg_scl_main_st_to_int_clr + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: DET_START_INT_CLR + description: reg_det_start_int_clr + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: SLAVE_STRETCH_INT_CLR + description: reg_slave_stretch_int_clr + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: GENERAL_CALL_INT_CLR + description: reg_general_call_int_clr + bitOffset: 17 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + description: I2C_INT_ENA_REG + addressOffset: 40 + size: 32 + fields: + - name: RXFIFO_WM_INT_ENA + description: reg_rxfifo_wm_int_ena + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_WM_INT_ENA + description: reg_txfifo_wm_int_ena + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_ENA + description: reg_rxfifo_ovf_int_ena + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: END_DETECT_INT_ENA + description: reg_end_detect_int_ena + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: BYTE_TRANS_DONE_INT_ENA + description: reg_byte_trans_done_int_ena + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ARBITRATION_LOST_INT_ENA + description: reg_arbitration_lost_int_ena + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: MST_TXFIFO_UDF_INT_ENA + description: reg_mst_txfifo_udf_int_ena + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TRANS_COMPLETE_INT_ENA + description: reg_trans_complete_int_ena + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TIME_OUT_INT_ENA + description: reg_time_out_int_ena + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TRANS_START_INT_ENA + description: reg_trans_start_int_ena + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: NACK_INT_ENA + description: reg_nack_int_ena + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TXFIFO_OVF_INT_ENA + description: reg_txfifo_ovf_int_ena + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RXFIFO_UDF_INT_ENA + description: reg_rxfifo_udf_int_ena + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SCL_ST_TO_INT_ENA + description: reg_scl_st_to_int_ena + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SCL_MAIN_ST_TO_INT_ENA + description: reg_scl_main_st_to_int_ena + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DET_START_INT_ENA + description: reg_det_start_int_ena + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLAVE_STRETCH_INT_ENA + description: reg_slave_stretch_int_ena + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: GENERAL_CALL_INT_ENA + description: reg_general_call_int_ena + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: INT_STATUS + description: I2C_INT_STATUS_REG + addressOffset: 44 + size: 32 + fields: + - name: RXFIFO_WM_INT_ST + description: reg_rxfifo_wm_int_st + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_WM_INT_ST + description: reg_txfifo_wm_int_st + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_ST + description: reg_rxfifo_ovf_int_st + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: END_DETECT_INT_ST + description: reg_end_detect_int_st + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS_DONE_INT_ST + description: reg_byte_trans_done_int_st + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_ST + description: reg_arbitration_lost_int_st + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: MST_TXFIFO_UDF_INT_ST + description: reg_mst_txfifo_udf_int_st + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_ST + description: reg_trans_complete_int_st + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_ST + description: reg_time_out_int_st + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TRANS_START_INT_ST + description: reg_trans_start_int_st + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: NACK_INT_ST + description: reg_nack_int_st + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: TXFIFO_OVF_INT_ST + description: reg_txfifo_ovf_int_st + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: RXFIFO_UDF_INT_ST + description: reg_rxfifo_udf_int_st + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SCL_ST_TO_INT_ST + description: reg_scl_st_to_int_st + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SCL_MAIN_ST_TO_INT_ST + description: reg_scl_main_st_to_int_st + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DET_START_INT_ST + description: reg_det_start_int_st + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLAVE_STRETCH_INT_ST + description: reg_slave_stretch_int_st + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: GENERAL_CALL_INT_ST + description: reg_general_call_int_st + bitOffset: 17 + bitWidth: 1 + access: read-only + - register: + name: SDA_HOLD + description: I2C_SDA_HOLD_REG + addressOffset: 48 + size: 32 + fields: + - name: TIME + description: reg_sda_hold_time + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SDA_SAMPLE + description: I2C_SDA_SAMPLE_REG + addressOffset: 52 + size: 32 + fields: + - name: TIME + description: reg_sda_sample_time + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_HIGH_PERIOD + description: I2C_SCL_HIGH_PERIOD_REG + addressOffset: 56 + size: 32 + fields: + - name: SCL_HIGH_PERIOD + description: reg_scl_high_period + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: SCL_WAIT_HIGH_PERIOD + description: reg_scl_wait_high_period + bitOffset: 9 + bitWidth: 7 + access: read-write + - register: + name: SCL_START_HOLD + description: I2C_SCL_START_HOLD_REG + addressOffset: 64 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: reg_scl_start_hold_time + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_RSTART_SETUP + description: I2C_SCL_RSTART_SETUP_REG + addressOffset: 68 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: reg_scl_rstart_setup_time + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_STOP_HOLD + description: I2C_SCL_STOP_HOLD_REG + addressOffset: 72 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: reg_scl_stop_hold_time + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_STOP_SETUP + description: I2C_SCL_STOP_SETUP_REG + addressOffset: 76 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: reg_scl_stop_setup_time + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: FILTER_CFG + description: I2C_FILTER_CFG_REG + addressOffset: 80 + size: 32 + resetValue: 768 + fields: + - name: SCL_FILTER_THRES + description: reg_scl_filter_thres + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: SDA_FILTER_THRES + description: reg_sda_filter_thres + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: SCL_FILTER_EN + description: reg_scl_filter_en + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SDA_FILTER_EN + description: reg_sda_filter_en + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: CLK_CONF + description: I2C_CLK_CONF_REG + addressOffset: 84 + size: 32 + resetValue: 2097152 + fields: + - name: SCLK_DIV_NUM + description: reg_sclk_div_num + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SCLK_DIV_A + description: reg_sclk_div_a + bitOffset: 8 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_B + description: reg_sclk_div_b + bitOffset: 14 + bitWidth: 6 + access: read-write + - name: SCLK_SEL + description: reg_sclk_sel + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SCLK_ACTIVE + description: reg_sclk_active + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7" + name: COMD%s + description: I2C_COMD%s_REG + addressOffset: 88 + size: 32 + fields: + - name: COMMAND + description: reg_command + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND_DONE + description: reg_command_done + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SCL_ST_TIME_OUT + description: I2C_SCL_ST_TIME_OUT_REG + addressOffset: 120 + size: 32 + resetValue: 16 + fields: + - name: SCL_ST_TO_I2C + description: reg_scl_st_to_regno more than 23 + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SCL_MAIN_ST_TIME_OUT + description: I2C_SCL_MAIN_ST_TIME_OUT_REG + addressOffset: 124 + size: 32 + resetValue: 16 + fields: + - name: SCL_MAIN_ST_TO_I2C + description: reg_scl_main_st_to_regno more than 23 + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SCL_SP_CONF + description: I2C_SCL_SP_CONF_REG + addressOffset: 128 + size: 32 + fields: + - name: SCL_RST_SLV_EN + description: reg_scl_rst_slv_en + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_RST_SLV_NUM + description: reg_scl_rst_slv_num + bitOffset: 1 + bitWidth: 5 + access: read-write + - name: SCL_PD_EN + description: reg_scl_pd_en + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SDA_PD_EN + description: reg_sda_pd_en + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: SCL_STRETCH_CONF + description: I2C_SCL_STRETCH_CONF_REG + addressOffset: 132 + size: 32 + fields: + - name: STRETCH_PROTECT_NUM + description: reg_stretch_protect_num + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: SLAVE_SCL_STRETCH_EN + description: reg_slave_scl_stretch_en + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLAVE_SCL_STRETCH_CLR + description: reg_slave_scl_stretch_clr + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: SLAVE_BYTE_ACK_CTL_EN + description: reg_slave_byte_ack_ctl_en + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SLAVE_BYTE_ACK_LVL + description: reg_slave_byte_ack_lvl + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: I2C_DATE_REG + addressOffset: 248 + size: 32 + resetValue: 537330177 + fields: + - name: DATE + description: reg_date + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TXFIFO_START_ADDR + description: I2C_TXFIFO_START_ADDR_REG + addressOffset: 256 + size: 32 + fields: + - name: TXFIFO_START_ADDR + description: reg_txfifo_start_addr. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RXFIFO_START_ADDR + description: I2C_RXFIFO_START_ADDR_REG + addressOffset: 384 + size: 32 + fields: + - name: RXFIFO_START_ADDR + description: reg_rxfifo_start_addr. + bitOffset: 0 + bitWidth: 32 + access: read-only + - name: I2S0 + description: I2S (Inter-IC Sound) Controller 0 + groupName: I2S + baseAddress: 1610797056 + addressBlock: + - offset: 0 + size: 92 + usage: registers + interrupt: + - name: I2S0 + value: 20 + registers: + - register: + name: INT_RAW + description: "I2S interrupt raw register, valid in level." + addressOffset: 12 + size: 32 + fields: + - name: RX_DONE_INT_RAW + description: The raw interrupt status bit for the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_RAW + description: The raw interrupt status bit for the i2s_tx_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_RAW + description: The raw interrupt status bit for the i2s_rx_hung_int interrupt + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_RAW + description: The raw interrupt status bit for the i2s_tx_hung_int interrupt + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: I2S interrupt status register. + addressOffset: 16 + size: 32 + fields: + - name: RX_DONE_INT_ST + description: The masked interrupt status bit for the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_ST + description: The masked interrupt status bit for the i2s_tx_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_ST + description: The masked interrupt status bit for the i2s_rx_hung_int interrupt + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_ST + description: The masked interrupt status bit for the i2s_tx_hung_int interrupt + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: I2S interrupt enable register. + addressOffset: 20 + size: 32 + fields: + - name: RX_DONE_INT_ENA + description: The interrupt enable bit for the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_ENA + description: The interrupt enable bit for the i2s_tx_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_HUNG_INT_ENA + description: The interrupt enable bit for the i2s_rx_hung_int interrupt + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_HUNG_INT_ENA + description: The interrupt enable bit for the i2s_tx_hung_int interrupt + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: I2S interrupt clear register. + addressOffset: 24 + size: 32 + fields: + - name: RX_DONE_INT_CLR + description: Set this bit to clear the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TX_DONE_INT_CLR + description: Set this bit to clear the i2s_tx_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_HUNG_INT_CLR + description: Set this bit to clear the i2s_rx_hung_int interrupt + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TX_HUNG_INT_CLR + description: Set this bit to clear the i2s_tx_hung_int interrupt + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: RX_CONF + description: I2S RX configure register + addressOffset: 32 + size: 32 + resetValue: 38400 + fields: + - name: RX_RESET + description: Set this bit to reset receiver + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: RX_FIFO_RESET + description: Set this bit to reset Rx AFIFO + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_START + description: Set this bit to start receiving data + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_SLAVE_MOD + description: Set this bit to enable slave receiver mode + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_MONO + description: Set this bit to enable receiver in mono mode + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RX_BIG_ENDIAN + description: "I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RX_UPDATE + description: Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RX_MONO_FST_VLD + description: "1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RX_PCM_CONF + description: "I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: RX_PCM_BYPASS + description: Set this bit to bypass Compress/Decompress module for received data. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RX_STOP_MODE + description: "0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full." + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: RX_LEFT_ALIGN + description: "1: I2S RX left alignment mode. 0: I2S RX right alignment mode." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RX_24_FILL_EN + description: "1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RX_WS_IDLE_POL + description: "0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: RX_BIT_ORDER + description: "I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RX_TDM_EN + description: "1: Enable I2S TDM Rx mode . 0: Disable." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RX_PDM_EN + description: "1: Enable I2S PDM Rx mode . 0: Disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: TX_CONF + description: I2S TX configure register + addressOffset: 36 + size: 32 + resetValue: 45568 + fields: + - name: TX_RESET + description: Set this bit to reset transmitter + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TX_FIFO_RESET + description: Set this bit to reset Tx AFIFO + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TX_START + description: Set this bit to start transmitting data + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_SLAVE_MOD + description: Set this bit to enable slave transmitter mode + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_MONO + description: Set this bit to enable transmitter in mono mode + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TX_CHAN_EQUAL + description: "1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_BIG_ENDIAN + description: "I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TX_UPDATE + description: Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TX_MONO_FST_VLD + description: "1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TX_PCM_CONF + description: "I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: TX_PCM_BYPASS + description: Set this bit to bypass Compress/Decompress module for transmitted data. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_STOP_EN + description: Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_LEFT_ALIGN + description: "1: I2S TX left alignment mode. 0: I2S TX right alignment mode." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TX_24_FILL_EN + description: "1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: TX_WS_IDLE_POL + description: "0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: TX_BIT_ORDER + description: "I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TX_TDM_EN + description: "1: Enable I2S TDM Tx mode . 0: Disable." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: TX_PDM_EN + description: "1: Enable I2S PDM Tx mode . 0: Disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TX_CHAN_MOD + description: I2S transmitter channel mode configuration bits. + bitOffset: 24 + bitWidth: 3 + access: read-write + - name: SIG_LOOPBACK + description: Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: RX_CONF1 + description: I2S RX configure register 1 + addressOffset: 40 + size: 32 + resetValue: 792584960 + fields: + - name: RX_TDM_WS_WIDTH + description: "The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck" + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: RX_BCK_DIV_NUM + description: Bit clock configuration bits in receiver mode. + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: RX_BITS_MOD + description: "Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode." + bitOffset: 13 + bitWidth: 5 + access: read-write + - name: RX_HALF_SAMPLE_BITS + description: I2S Rx half sample bits -1. + bitOffset: 18 + bitWidth: 6 + access: read-write + - name: RX_TDM_CHAN_BITS + description: The Rx bit number for each channel minus 1in TDM mode. + bitOffset: 24 + bitWidth: 5 + access: read-write + - name: RX_MSB_SHIFT + description: Set this bit to enable receiver in Phillips standard mode + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: TX_CONF1 + description: I2S TX configure register 1 + addressOffset: 44 + size: 32 + resetValue: 1866326784 + fields: + - name: TX_TDM_WS_WIDTH + description: "The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck" + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: TX_BCK_DIV_NUM + description: Bit clock configuration bits in transmitter mode. + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: TX_BITS_MOD + description: "Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode." + bitOffset: 13 + bitWidth: 5 + access: read-write + - name: TX_HALF_SAMPLE_BITS + description: I2S Tx half sample bits -1. + bitOffset: 18 + bitWidth: 6 + access: read-write + - name: TX_TDM_CHAN_BITS + description: The Tx bit number for each channel minus 1in TDM mode. + bitOffset: 24 + bitWidth: 5 + access: read-write + - name: TX_MSB_SHIFT + description: Set this bit to enable transmitter in Phillips standard mode + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TX_BCK_NO_DLY + description: "1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode." + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: RX_CLKM_CONF + description: I2S RX clock configure register + addressOffset: 48 + size: 32 + resetValue: 2 + fields: + - name: RX_CLKM_DIV_NUM + description: Integral I2S clock divider value + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: RX_CLK_ACTIVE + description: I2S Rx module clock enable signal. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RX_CLK_SEL + description: "Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in." + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: MCLK_SEL + description: "0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT." + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: TX_CLKM_CONF + description: I2S TX clock configure register + addressOffset: 52 + size: 32 + resetValue: 2 + fields: + - name: TX_CLKM_DIV_NUM + description: "Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TX_CLK_ACTIVE + description: I2S Tx module clock enable signal. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TX_CLK_SEL + description: "Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in." + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: CLK_EN + description: Set this bit to enable clk gate + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: RX_CLKM_DIV_CONF + description: I2S RX module clock divider configure register + addressOffset: 56 + size: 32 + resetValue: 512 + fields: + - name: RX_CLKM_DIV_Z + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: RX_CLKM_DIV_Y + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))." + bitOffset: 9 + bitWidth: 9 + access: read-write + - name: RX_CLKM_DIV_X + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1." + bitOffset: 18 + bitWidth: 9 + access: read-write + - name: RX_CLKM_DIV_YN1 + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1." + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: TX_CLKM_DIV_CONF + description: I2S TX module clock divider configure register + addressOffset: 60 + size: 32 + resetValue: 512 + fields: + - name: TX_CLKM_DIV_Z + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: TX_CLKM_DIV_Y + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))." + bitOffset: 9 + bitWidth: 9 + access: read-write + - name: TX_CLKM_DIV_X + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1." + bitOffset: 18 + bitWidth: 9 + access: read-write + - name: TX_CLKM_DIV_YN1 + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1." + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: TX_PCM2PDM_CONF + description: I2S TX PCM2PDM configuration register + addressOffset: 64 + size: 32 + resetValue: 4890628 + fields: + - name: TX_PDM_HP_BYPASS + description: I2S TX PDM bypass hp filter or not. The option has been removed. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_PDM_SINC_OSR2 + description: I2S TX PDM OSR2 value + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: TX_PDM_PRESCALE + description: I2S TX PDM prescale for sigmadelta + bitOffset: 5 + bitWidth: 8 + access: read-write + - name: TX_PDM_HP_IN_SHIFT + description: "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4" + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: TX_PDM_LP_IN_SHIFT + description: "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4" + bitOffset: 15 + bitWidth: 2 + access: read-write + - name: TX_PDM_SINC_IN_SHIFT + description: "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4" + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: TX_PDM_SIGMADELTA_IN_SHIFT + description: "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4" + bitOffset: 19 + bitWidth: 2 + access: read-write + - name: TX_PDM_SIGMADELTA_DITHER2 + description: I2S TX PDM sigmadelta dither2 value + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: TX_PDM_SIGMADELTA_DITHER + description: I2S TX PDM sigmadelta dither value + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TX_PDM_DAC_2OUT_EN + description: I2S TX PDM dac mode enable + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TX_PDM_DAC_MODE_EN + description: I2S TX PDM dac 2channel enable + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PCM2PDM_CONV_EN + description: I2S TX PDM Converter enable + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: TX_PCM2PDM_CONF1 + description: I2S TX PCM2PDM configuration register + addressOffset: 68 + size: 32 + resetValue: 66552768 + fields: + - name: TX_PDM_FP + description: I2S TX PDM Fp + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: TX_PDM_FS + description: I2S TX PDM Fs + bitOffset: 10 + bitWidth: 10 + access: read-write + - name: TX_IIR_HP_MULT12_5 + description: "The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])" + bitOffset: 20 + bitWidth: 3 + access: read-write + - name: TX_IIR_HP_MULT12_0 + description: "The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])" + bitOffset: 23 + bitWidth: 3 + access: read-write + - register: + name: RX_TDM_CTRL + description: I2S TX TDM mode control register + addressOffset: 80 + size: 32 + resetValue: 65535 + fields: + - name: RX_TDM_PDM_CHAN0_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN1_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN2_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN3_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN4_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN5_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN6_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN7_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN8_EN + description: "1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN9_EN + description: "1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN10_EN + description: "1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN11_EN + description: "1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN12_EN + description: "1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN13_EN + description: "1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN14_EN + description: "1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN15_EN + description: "1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RX_TDM_TOT_CHAN_NUM + description: The total channel number of I2S TX TDM mode. + bitOffset: 16 + bitWidth: 4 + access: read-write + - register: + name: TX_TDM_CTRL + description: I2S TX TDM mode control register + addressOffset: 84 + size: 32 + resetValue: 65535 + fields: + - name: TX_TDM_CHAN0_EN + description: "1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN1_EN + description: "1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN2_EN + description: "1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN3_EN + description: "1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN4_EN + description: "1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN5_EN + description: "1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN6_EN + description: "1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN7_EN + description: "1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN8_EN + description: "1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN9_EN + description: "1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN10_EN + description: "1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN11_EN + description: "1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN12_EN + description: "1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN13_EN + description: "1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN14_EN + description: "1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN15_EN + description: "1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TX_TDM_TOT_CHAN_NUM + description: The total channel number of I2S TX TDM mode. + bitOffset: 16 + bitWidth: 4 + access: read-write + - name: TX_TDM_SKIP_MSK_EN + description: "When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels." + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: RX_TIMING + description: I2S RX timing control register + addressOffset: 88 + size: 32 + fields: + - name: RX_SD_IN_DM + description: "The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: RX_WS_OUT_DM + description: "The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: RX_BCK_OUT_DM + description: "The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: RX_WS_IN_DM + description: "The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: RX_BCK_IN_DM + description: "The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 28 + bitWidth: 2 + access: read-write + - register: + name: TX_TIMING + description: I2S TX timing control register + addressOffset: 92 + size: 32 + fields: + - name: TX_SD_OUT_DM + description: "The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: TX_SD1_OUT_DM + description: "The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: TX_WS_OUT_DM + description: "The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: TX_BCK_OUT_DM + description: "The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TX_WS_IN_DM + description: "The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: TX_BCK_IN_DM + description: "The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 28 + bitWidth: 2 + access: read-write + - register: + name: LC_HUNG_CONF + description: I2S HUNG configure register. + addressOffset: 96 + size: 32 + resetValue: 2064 + fields: + - name: LC_FIFO_TIMEOUT + description: the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: LC_FIFO_TIMEOUT_SHIFT + description: The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + bitOffset: 8 + bitWidth: 3 + access: read-write + - name: LC_FIFO_TIMEOUT_ENA + description: The enable bit for FIFO timeout + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: RXEOF_NUM + description: I2S RX data number control register. + addressOffset: 100 + size: 32 + resetValue: 64 + fields: + - name: RX_EOF_NUM + description: "The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel." + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: CONF_SIGLE_DATA + description: I2S signal data register + addressOffset: 104 + size: 32 + fields: + - name: SINGLE_DATA + description: The configured constant channel data to be sent out. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STATE + description: I2S TX status register + addressOffset: 108 + size: 32 + resetValue: 1 + fields: + - name: TX_IDLE + description: "1: i2s_tx is idle state. 0: i2s_tx is working." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: Version control register + addressOffset: 128 + size: 32 + resetValue: 33583648 + fields: + - name: DATE + description: I2S version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: INTERRUPT_CORE0 + description: Interrupt Controller (Core 0) + groupName: INTERRUPT_CORE0 + baseAddress: 1611407360 + addressBlock: + - offset: 0 + size: 412 + usage: registers + interrupt: + - name: WIFI_MAC + value: 0 + - name: WIFI_MAC_NMI + value: 1 + - name: WIFI_PWR + value: 2 + - name: WIFI_BB + value: 3 + - name: BT_MAC + value: 4 + - name: BT_BB + value: 5 + - name: BT_BB_NMI + value: 6 + - name: RWBT + value: 7 + - name: RWBLE + value: 8 + - name: RWBT_NMI + value: 9 + - name: RWBLE_NMI + value: 10 + - name: SLC0 + value: 12 + - name: SLC1 + value: 13 + - name: CACHE_IA + value: 36 + - name: ICACHE_PRELOAD0 + value: 41 + - name: ICACHE_SYNC0 + value: 42 + - name: FROM_CPU_INTR0 + value: 50 + - name: FROM_CPU_INTR1 + value: 51 + - name: FROM_CPU_INTR2 + value: 52 + - name: FROM_CPU_INTR3 + value: 53 + - name: CORE0_IRAM0_PMS + value: 56 + - name: CORE0_DRAM0_PMS + value: 57 + - name: CORE0_PIF_PMS + value: 58 + - name: CORE0_PIF_PMS_SIZE + value: 59 + - name: BAK_PMS_VIOLATE + value: 60 + - name: CACHE_CORE0_ACS + value: 61 + registers: + - register: + name: MAC_INTR_MAP + description: mac intr map register + addressOffset: 0 + size: 32 + fields: + - name: MAC_INTR_MAP + description: core0_mac_intr_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: MAC_NMI_MAP + description: mac nmi_intr map register + addressOffset: 4 + size: 32 + fields: + - name: MAC_NMI_MAP + description: reg_core0_mac_nmi_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PWR_INTR_MAP + description: pwr intr map register + addressOffset: 8 + size: 32 + fields: + - name: PWR_INTR_MAP + description: reg_core0_pwr_intr_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BB_INT_MAP + description: bb intr map register + addressOffset: 12 + size: 32 + fields: + - name: BB_INT_MAP + description: reg_core0_bb_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BT_MAC_INT_MAP + description: bt intr map register + addressOffset: 16 + size: 32 + fields: + - name: BT_MAC_INT_MAP + description: reg_core0_bt_mac_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BT_BB_INT_MAP + description: bb_bt intr map register + addressOffset: 20 + size: 32 + fields: + - name: BT_BB_INT_MAP + description: reg_core0_bt_bb_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BT_BB_NMI_MAP + description: bb_bt_nmi intr map register + addressOffset: 24 + size: 32 + fields: + - name: BT_BB_NMI_MAP + description: reg_core0_bt_bb_nmi_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RWBT_IRQ_MAP + description: rwbt intr map register + addressOffset: 28 + size: 32 + fields: + - name: RWBT_IRQ_MAP + description: reg_core0_rwbt_irq_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RWBLE_IRQ_MAP + description: rwble intr map register + addressOffset: 32 + size: 32 + fields: + - name: RWBLE_IRQ_MAP + description: reg_core0_rwble_irq_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RWBT_NMI_MAP + description: rwbt_nmi intr map register + addressOffset: 36 + size: 32 + fields: + - name: RWBT_NMI_MAP + description: reg_core0_rwbt_nmi_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RWBLE_NMI_MAP + description: rwble_nmi intr map register + addressOffset: 40 + size: 32 + fields: + - name: RWBLE_NMI_MAP + description: reg_core0_rwble_nmi_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: I2C_MST_INT_MAP + description: i2c intr map register + addressOffset: 44 + size: 32 + fields: + - name: I2C_MST_INT_MAP + description: reg_core0_i2c_mst_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SLC0_INTR_MAP + description: slc0 intr map register + addressOffset: 48 + size: 32 + fields: + - name: SLC0_INTR_MAP + description: reg_core0_slc0_intr_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SLC1_INTR_MAP + description: slc1 intr map register + addressOffset: 52 + size: 32 + fields: + - name: SLC1_INTR_MAP + description: reg_core0_slc1_intr_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APB_CTRL_INTR_MAP + description: apb_ctrl intr map register + addressOffset: 56 + size: 32 + fields: + - name: APB_CTRL_INTR_MAP + description: reg_core0_apb_ctrl_intr_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: UHCI0_INTR_MAP + description: uchi0 intr map register + addressOffset: 60 + size: 32 + fields: + - name: UHCI0_INTR_MAP + description: reg_core0_uhci0_intr_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: GPIO_INTERRUPT_PRO_MAP + description: gpio intr map register + addressOffset: 64 + size: 32 + fields: + - name: GPIO_INTERRUPT_PRO_MAP + description: reg_core0_gpio_interrupt_pro_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: GPIO_INTERRUPT_PRO_NMI_MAP + description: gpio_pro intr map register + addressOffset: 68 + size: 32 + fields: + - name: GPIO_INTERRUPT_PRO_NMI_MAP + description: reg_core0_gpio_interrupt_pro_nmi_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SPI_INTR_1_MAP + description: gpio_pro_nmi intr map register + addressOffset: 72 + size: 32 + fields: + - name: SPI_INTR_1_MAP + description: reg_core0_spi_intr_1_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SPI_INTR_2_MAP + description: spi1 intr map register + addressOffset: 76 + size: 32 + fields: + - name: SPI_INTR_2_MAP + description: reg_core0_spi_intr_2_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: I2S1_INT_MAP + description: spi2 intr map register + addressOffset: 80 + size: 32 + fields: + - name: I2S1_INT_MAP + description: reg_core0_i2s1_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: UART_INTR_MAP + description: i2s1 intr map register + addressOffset: 84 + size: 32 + fields: + - name: UART_INTR_MAP + description: reg_core0_uart_intr_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: UART1_INTR_MAP + description: uart1 intr map register + addressOffset: 88 + size: 32 + fields: + - name: UART1_INTR_MAP + description: reg_core0_uart1_intr_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: LEDC_INT_MAP + description: ledc intr map register + addressOffset: 92 + size: 32 + fields: + - name: LEDC_INT_MAP + description: reg_core0_ledc_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: EFUSE_INT_MAP + description: efuse intr map register + addressOffset: 96 + size: 32 + fields: + - name: EFUSE_INT_MAP + description: reg_core0_efuse_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CAN_INT_MAP + description: can intr map register + addressOffset: 100 + size: 32 + fields: + - name: CAN_INT_MAP + description: reg_core0_can_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: USB_INTR_MAP + description: usb intr map register + addressOffset: 104 + size: 32 + fields: + - name: USB_INTR_MAP + description: reg_core0_usb_intr_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RTC_CORE_INTR_MAP + description: rtc intr map register + addressOffset: 108 + size: 32 + fields: + - name: RTC_CORE_INTR_MAP + description: reg_core0_rtc_core_intr_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RMT_INTR_MAP + description: rmt intr map register + addressOffset: 112 + size: 32 + fields: + - name: RMT_INTR_MAP + description: reg_core0_rmt_intr_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: I2C_EXT0_INTR_MAP + description: i2c intr map register + addressOffset: 116 + size: 32 + fields: + - name: I2C_EXT0_INTR_MAP + description: reg_core0_i2c_ext0_intr_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TIMER_INT1_MAP + description: timer1 intr map register + addressOffset: 120 + size: 32 + fields: + - name: TIMER_INT1_MAP + description: reg_core0_timer_int1_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TIMER_INT2_MAP + description: timer2 intr map register + addressOffset: 124 + size: 32 + fields: + - name: TIMER_INT2_MAP + description: reg_core0_timer_int2_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG_T0_INT_MAP + description: tg to intr map register + addressOffset: 128 + size: 32 + fields: + - name: TG_T0_INT_MAP + description: reg_core0_tg_t0_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG_WDT_INT_MAP + description: tg wdt intr map register + addressOffset: 132 + size: 32 + fields: + - name: TG_WDT_INT_MAP + description: reg_core0_tg_wdt_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG1_T0_INT_MAP + description: tg1 to intr map register + addressOffset: 136 + size: 32 + fields: + - name: TG1_T0_INT_MAP + description: reg_core0_tg1_t0_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG1_WDT_INT_MAP + description: tg1 wdt intr map register + addressOffset: 140 + size: 32 + fields: + - name: TG1_WDT_INT_MAP + description: reg_core0_tg1_wdt_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CACHE_IA_INT_MAP + description: cache ia intr map register + addressOffset: 144 + size: 32 + fields: + - name: CACHE_IA_INT_MAP + description: reg_core0_cache_ia_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SYSTIMER_TARGET0_INT_MAP + description: systimer intr map register + addressOffset: 148 + size: 32 + fields: + - name: SYSTIMER_TARGET0_INT_MAP + description: reg_core0_systimer_target0_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SYSTIMER_TARGET1_INT_MAP + description: systimer target1 intr map register + addressOffset: 152 + size: 32 + fields: + - name: SYSTIMER_TARGET1_INT_MAP + description: reg_core0_systimer_target1_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SYSTIMER_TARGET2_INT_MAP + description: systimer target2 intr map register + addressOffset: 156 + size: 32 + fields: + - name: SYSTIMER_TARGET2_INT_MAP + description: reg_core0_systimer_target2_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SPI_MEM_REJECT_INTR_MAP + description: spi mem reject intr map register + addressOffset: 160 + size: 32 + fields: + - name: SPI_MEM_REJECT_INTR_MAP + description: reg_core0_spi_mem_reject_intr_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: ICACHE_PRELOAD_INT_MAP + description: icache perload intr map register + addressOffset: 164 + size: 32 + fields: + - name: ICACHE_PRELOAD_INT_MAP + description: reg_core0_icache_preload_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: ICACHE_SYNC_INT_MAP + description: icache sync intr map register + addressOffset: 168 + size: 32 + fields: + - name: ICACHE_SYNC_INT_MAP + description: reg_core0_icache_sync_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APB_ADC_INT_MAP + description: adc intr map register + addressOffset: 172 + size: 32 + fields: + - name: APB_ADC_INT_MAP + description: reg_core0_apb_adc_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_CH0_INT_MAP + description: dma ch0 intr map register + addressOffset: 176 + size: 32 + fields: + - name: DMA_CH0_INT_MAP + description: reg_core0_dma_ch0_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_CH1_INT_MAP + description: dma ch1 intr map register + addressOffset: 180 + size: 32 + fields: + - name: DMA_CH1_INT_MAP + description: reg_core0_dma_ch1_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_CH2_INT_MAP + description: dma ch2 intr map register + addressOffset: 184 + size: 32 + fields: + - name: DMA_CH2_INT_MAP + description: reg_core0_dma_ch2_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RSA_INT_MAP + description: rsa intr map register + addressOffset: 188 + size: 32 + fields: + - name: RSA_INT_MAP + description: reg_core0_rsa_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: AES_INT_MAP + description: aes intr map register + addressOffset: 192 + size: 32 + fields: + - name: AES_INT_MAP + description: reg_core0_aes_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SHA_INT_MAP + description: sha intr map register + addressOffset: 196 + size: 32 + fields: + - name: SHA_INT_MAP + description: reg_core0_sha_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_0_MAP + description: cpu from cpu 0 intr map register + addressOffset: 200 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_0_MAP + description: reg_core0_cpu_intr_from_cpu_0_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_1_MAP + description: cpu from cpu 0 intr map register + addressOffset: 204 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_1_MAP + description: reg_core0_cpu_intr_from_cpu_1_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_2_MAP + description: cpu from cpu 1 intr map register + addressOffset: 208 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_2_MAP + description: reg_core0_cpu_intr_from_cpu_2_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_3_MAP + description: cpu from cpu 3 intr map register + addressOffset: 212 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_3_MAP + description: reg_core0_cpu_intr_from_cpu_3_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: ASSIST_DEBUG_INTR_MAP + description: assist debug intr map register + addressOffset: 216 + size: 32 + fields: + - name: ASSIST_DEBUG_INTR_MAP + description: reg_core0_assist_debug_intr_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP + description: dma pms violatile intr map register + addressOffset: 220 + size: 32 + fields: + - name: DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP + description: reg_core0_dma_apbperi_pms_monitor_violate_intr_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + description: iram0 pms violatile intr map register + addressOffset: 224 + size: 32 + fields: + - name: CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + description: reg_core0_core_0_iram0_pms_monitor_violate_intr_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + description: mac intr map register + addressOffset: 228 + size: 32 + fields: + - name: CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + description: reg_core0_core_0_dram0_pms_monitor_violate_intr_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + description: mac intr map register + addressOffset: 232 + size: 32 + fields: + - name: CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + description: reg_core0_core_0_pif_pms_monitor_violate_intr_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + description: mac intr map register + addressOffset: 236 + size: 32 + fields: + - name: CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + description: reg_core0_core_0_pif_pms_monitor_violate_size_intr_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BACKUP_PMS_VIOLATE_INTR_MAP + description: mac intr map register + addressOffset: 240 + size: 32 + fields: + - name: BACKUP_PMS_VIOLATE_INTR_MAP + description: reg_core0_backup_pms_violate_intr_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CACHE_CORE0_ACS_INT_MAP + description: mac intr map register + addressOffset: 244 + size: 32 + fields: + - name: CACHE_CORE0_ACS_INT_MAP + description: reg_core0_cache_core0_acs_int_map + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: INTR_STATUS_REG_0 + description: mac intr map register + addressOffset: 248 + size: 32 + fields: + - name: INTR_STATUS_0 + description: reg_core0_intr_status_0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INTR_STATUS_REG_1 + description: mac intr map register + addressOffset: 252 + size: 32 + fields: + - name: INTR_STATUS_1 + description: reg_core0_intr_status_1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CLOCK_GATE + description: mac intr map register + addressOffset: 256 + size: 32 + resetValue: 1 + fields: + - name: REG_CLK_EN + description: reg_core0_reg_clk_en + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INT_ENABLE + description: mac intr map register + addressOffset: 260 + size: 32 + fields: + - name: CPU_INT_ENABLE + description: reg_core0_cpu_int_enable + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CPU_INT_TYPE + description: mac intr map register + addressOffset: 264 + size: 32 + fields: + - name: CPU_INT_TYPE + description: reg_core0_cpu_int_type + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CPU_INT_CLEAR + description: mac intr map register + addressOffset: 268 + size: 32 + fields: + - name: CPU_INT_CLEAR + description: reg_core0_cpu_int_clear + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CPU_INT_EIP_STATUS + description: mac intr map register + addressOffset: 272 + size: 32 + fields: + - name: CPU_INT_EIP_STATUS + description: reg_core0_cpu_int_eip_status + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CPU_INT_PRI_0 + description: mac intr map register + addressOffset: 276 + size: 32 + fields: + - name: CPU_PRI_0_MAP + description: reg_core0_cpu_pri_0_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_1 + description: mac intr map register + addressOffset: 280 + size: 32 + fields: + - name: CPU_PRI_1_MAP + description: reg_core0_cpu_pri_1_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_2 + description: mac intr map register + addressOffset: 284 + size: 32 + fields: + - name: CPU_PRI_2_MAP + description: reg_core0_cpu_pri_2_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_3 + description: mac intr map register + addressOffset: 288 + size: 32 + fields: + - name: CPU_PRI_3_MAP + description: reg_core0_cpu_pri_3_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_4 + description: mac intr map register + addressOffset: 292 + size: 32 + fields: + - name: CPU_PRI_4_MAP + description: reg_core0_cpu_pri_4_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_5 + description: mac intr map register + addressOffset: 296 + size: 32 + fields: + - name: CPU_PRI_5_MAP + description: reg_core0_cpu_pri_5_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_6 + description: mac intr map register + addressOffset: 300 + size: 32 + fields: + - name: CPU_PRI_6_MAP + description: reg_core0_cpu_pri_6_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_7 + description: mac intr map register + addressOffset: 304 + size: 32 + fields: + - name: CPU_PRI_7_MAP + description: reg_core0_cpu_pri_7_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_8 + description: mac intr map register + addressOffset: 308 + size: 32 + fields: + - name: CPU_PRI_8_MAP + description: reg_core0_cpu_pri_8_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_9 + description: mac intr map register + addressOffset: 312 + size: 32 + fields: + - name: CPU_PRI_9_MAP + description: reg_core0_cpu_pri_9_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_10 + description: mac intr map register + addressOffset: 316 + size: 32 + fields: + - name: CPU_PRI_10_MAP + description: reg_core0_cpu_pri_10_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_11 + description: mac intr map register + addressOffset: 320 + size: 32 + fields: + - name: CPU_PRI_11_MAP + description: reg_core0_cpu_pri_11_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_12 + description: mac intr map register + addressOffset: 324 + size: 32 + fields: + - name: CPU_PRI_12_MAP + description: reg_core0_cpu_pri_12_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_13 + description: mac intr map register + addressOffset: 328 + size: 32 + fields: + - name: CPU_PRI_13_MAP + description: reg_core0_cpu_pri_13_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_14 + description: mac intr map register + addressOffset: 332 + size: 32 + fields: + - name: CPU_PRI_14_MAP + description: reg_core0_cpu_pri_14_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_15 + description: mac intr map register + addressOffset: 336 + size: 32 + fields: + - name: CPU_PRI_15_MAP + description: reg_core0_cpu_pri_15_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_16 + description: mac intr map register + addressOffset: 340 + size: 32 + fields: + - name: CPU_PRI_16_MAP + description: reg_core0_cpu_pri_16_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_17 + description: mac intr map register + addressOffset: 344 + size: 32 + fields: + - name: CPU_PRI_17_MAP + description: reg_core0_cpu_pri_17_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_18 + description: mac intr map register + addressOffset: 348 + size: 32 + fields: + - name: CPU_PRI_18_MAP + description: reg_core0_cpu_pri_18_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_19 + description: mac intr map register + addressOffset: 352 + size: 32 + fields: + - name: CPU_PRI_19_MAP + description: reg_core0_cpu_pri_19_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_20 + description: mac intr map register + addressOffset: 356 + size: 32 + fields: + - name: CPU_PRI_20_MAP + description: reg_core0_cpu_pri_20_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_21 + description: mac intr map register + addressOffset: 360 + size: 32 + fields: + - name: CPU_PRI_21_MAP + description: reg_core0_cpu_pri_21_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_22 + description: mac intr map register + addressOffset: 364 + size: 32 + fields: + - name: CPU_PRI_22_MAP + description: reg_core0_cpu_pri_22_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_23 + description: mac intr map register + addressOffset: 368 + size: 32 + fields: + - name: CPU_PRI_23_MAP + description: reg_core0_cpu_pri_23_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_24 + description: mac intr map register + addressOffset: 372 + size: 32 + fields: + - name: CPU_PRI_24_MAP + description: reg_core0_cpu_pri_24_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_25 + description: mac intr map register + addressOffset: 376 + size: 32 + fields: + - name: CPU_PRI_25_MAP + description: reg_core0_cpu_pri_25_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_26 + description: mac intr map register + addressOffset: 380 + size: 32 + fields: + - name: CPU_PRI_26_MAP + description: reg_core0_cpu_pri_26_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_27 + description: mac intr map register + addressOffset: 384 + size: 32 + fields: + - name: CPU_PRI_27_MAP + description: reg_core0_cpu_pri_27_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_28 + description: mac intr map register + addressOffset: 388 + size: 32 + fields: + - name: CPU_PRI_28_MAP + description: reg_core0_cpu_pri_28_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_29 + description: mac intr map register + addressOffset: 392 + size: 32 + fields: + - name: CPU_PRI_29_MAP + description: reg_core0_cpu_pri_29_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_30 + description: mac intr map register + addressOffset: 396 + size: 32 + fields: + - name: CPU_PRI_30_MAP + description: reg_core0_cpu_pri_30_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_31 + description: mac intr map register + addressOffset: 400 + size: 32 + fields: + - name: CPU_PRI_31_MAP + description: reg_core0_cpu_pri_31_map + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_THRESH + description: mac intr map register + addressOffset: 404 + size: 32 + fields: + - name: CPU_INT_THRESH + description: reg_core0_cpu_int_thresh + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: INTERRUPT_REG_DATE + description: mac intr map register + addressOffset: 2044 + size: 32 + resetValue: 33583632 + fields: + - name: INTERRUPT_REG_DATE + description: reg_core0_interrupt_reg_date + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: IO_MUX + description: Input/Output Multiplexer + groupName: IO_MUX + baseAddress: 1610649600 + addressBlock: + - offset: 0 + size: 96 + usage: registers + registers: + - register: + name: PIN_CTRL + description: Clock Output Configuration Register + addressOffset: 0 + size: 32 + resetValue: 2047 + fields: + - name: CLK_OUT1 + description: "If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: CLK_OUT2 + description: "If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: CLK_OUT3 + description: "If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals." + bitOffset: 8 + bitWidth: 4 + access: read-write + - register: + dim: 22 + dimIncrement: 4 + name: GPIO%s + description: IO MUX Configure Register for pad XTAL_32K_P + addressOffset: 4 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: IO MUX Version Control Register + addressOffset: 252 + size: 32 + resetValue: 33579088 + fields: + - name: REG_DATE + description: Version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: LEDC + description: LED Control PWM (Pulse Width Modulation) + groupName: LEDC + baseAddress: 1610715136 + addressBlock: + - offset: 0 + size: 176 + usage: registers + interrupt: + - name: LEDC + value: 23 + - name: TIMER1 + value: 30 + - name: TIMER2 + value: 31 + registers: + - register: + dim: 6 + dimIncrement: 20 + dimIndex: "0,1,2,3,4,5" + name: CH%s_CONF0 + description: LEDC_LSCH%s_CONF%s. + addressOffset: 0 + size: 32 + fields: + - name: TIMER_SEL + description: reg_timer_sel_lsch0. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SIG_OUT_EN + description: reg_sig_out_en_lsch0. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IDLE_LV + description: reg_idle_lv_lsch0. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PARA_UP + description: reg_para_up_lsch0. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: OVF_NUM + description: reg_ovf_num_lsch0. + bitOffset: 5 + bitWidth: 10 + access: read-write + - name: OVF_CNT_EN + description: reg_ovf_cnt_en_lsch0. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: OVF_CNT_RESET + description: reg_ovf_cnt_reset_lsch0. + bitOffset: 16 + bitWidth: 1 + access: write-only + - register: + dim: 6 + dimIncrement: 20 + dimIndex: "0,1,2,3,4,5" + name: CH%s_HPOINT + description: LEDC_LSCH%s_HPOINT. + addressOffset: 4 + size: 32 + fields: + - name: HPOINT + description: reg_hpoint_lsch0. + bitOffset: 0 + bitWidth: 14 + access: read-write + - register: + dim: 6 + dimIncrement: 20 + dimIndex: "0,1,2,3,4,5" + name: CH%s_DUTY + description: LEDC_LSCH%s_DUTY. + addressOffset: 8 + size: 32 + fields: + - name: DUTY + description: reg_duty_lsch0. + bitOffset: 0 + bitWidth: 19 + access: read-write + - register: + dim: 6 + dimIncrement: 20 + dimIndex: "0,1,2,3,4,5" + name: CH%s_CONF1 + description: LEDC_LSCH%s_CONF1. + addressOffset: 12 + size: 32 + resetValue: 1073741824 + fields: + - name: DUTY_SCALE + description: reg_duty_scale_lsch0. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: DUTY_CYCLE + description: reg_duty_cycle_lsch0. + bitOffset: 10 + bitWidth: 10 + access: read-write + - name: DUTY_NUM + description: reg_duty_num_lsch0. + bitOffset: 20 + bitWidth: 10 + access: read-write + - name: DUTY_INC + description: reg_duty_inc_lsch0. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DUTY_START + description: reg_duty_start_lsch0. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + dim: 6 + dimIncrement: 20 + dimIndex: "0,1,2,3,4,5" + name: CH%s_DUTY_R + description: LEDC_LSCH%s_DUTY_R. + addressOffset: 16 + size: 32 + fields: + - name: DUTY_R + description: reg_duty_lsch0_r. + bitOffset: 0 + bitWidth: 19 + access: read-only + - register: + dim: 4 + dimIncrement: 8 + dimIndex: "0,1,2,3" + name: TIMER%s_CONF + description: LEDC_LSTIMER%s_CONF. + addressOffset: 160 + size: 32 + resetValue: 8388608 + fields: + - name: DUTY_RES + description: reg_lstimer0_duty_res. + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: CLK_DIV + description: reg_clk_div_lstimer0. + bitOffset: 4 + bitWidth: 18 + access: read-write + - name: PAUSE + description: reg_lstimer0_pause. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RST + description: reg_lstimer0_rst. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TICK_SEL + description: reg_tick_sel_lstimer0. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PARA_UP + description: reg_lstimer0_para_up. + bitOffset: 25 + bitWidth: 1 + access: write-only + - register: + dim: 4 + dimIncrement: 8 + dimIndex: "0,1,2,3" + name: TIMER%s_VALUE + description: LEDC_LSTIMER%s_VALUE. + addressOffset: 164 + size: 32 + fields: + - name: CNT + description: reg_lstimer0_cnt. + bitOffset: 0 + bitWidth: 14 + access: read-only + - register: + name: INT_RAW + description: LEDC_INT_RAW. + addressOffset: 192 + size: 32 + fields: + - name: LSTIMER0_OVF_INT_RAW + description: reg_lstimer0_ovf_int_raw. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LSTIMER1_OVF_INT_RAW + description: reg_lstimer1_ovf_int_raw. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: LSTIMER2_OVF_INT_RAW + description: reg_lstimer2_ovf_int_raw. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: LSTIMER3_OVF_INT_RAW + description: reg_lstimer3_ovf_int_raw. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_LSCH0_INT_RAW + description: reg_duty_chng_end_lsch0_int_raw. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_LSCH1_INT_RAW + description: reg_duty_chng_end_lsch1_int_raw. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_LSCH2_INT_RAW + description: reg_duty_chng_end_lsch2_int_raw. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_LSCH3_INT_RAW + description: reg_duty_chng_end_lsch3_int_raw. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_LSCH4_INT_RAW + description: reg_duty_chng_end_lsch4_int_raw. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_LSCH5_INT_RAW + description: reg_duty_chng_end_lsch5_int_raw. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OVF_CNT_LSCH0_INT_RAW + description: reg_ovf_cnt_lsch0_int_raw. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OVF_CNT_LSCH1_INT_RAW + description: reg_ovf_cnt_lsch1_int_raw. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: OVF_CNT_LSCH2_INT_RAW + description: reg_ovf_cnt_lsch2_int_raw. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: OVF_CNT_LSCH3_INT_RAW + description: reg_ovf_cnt_lsch3_int_raw. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: OVF_CNT_LSCH4_INT_RAW + description: reg_ovf_cnt_lsch4_int_raw. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: OVF_CNT_LSCH5_INT_RAW + description: reg_ovf_cnt_lsch5_int_raw. + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: LEDC_INT_ST. + addressOffset: 196 + size: 32 + fields: + - name: LSTIMER0_OVF_INT_ST + description: reg_lstimer0_ovf_int_st. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: LSTIMER1_OVF_INT_ST + description: reg_lstimer1_ovf_int_st. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: LSTIMER2_OVF_INT_ST + description: reg_lstimer2_ovf_int_st. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: LSTIMER3_OVF_INT_ST + description: reg_lstimer3_ovf_int_st. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_LSCH0_INT_ST + description: reg_duty_chng_end_lsch0_int_st. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_LSCH1_INT_ST + description: reg_duty_chng_end_lsch1_int_st. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_LSCH2_INT_ST + description: reg_duty_chng_end_lsch2_int_st. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_LSCH3_INT_ST + description: reg_duty_chng_end_lsch3_int_st. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_LSCH4_INT_ST + description: reg_duty_chng_end_lsch4_int_st. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_LSCH5_INT_ST + description: reg_duty_chng_end_lsch5_int_st. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: OVF_CNT_LSCH0_INT_ST + description: reg_ovf_cnt_lsch0_int_st. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: OVF_CNT_LSCH1_INT_ST + description: reg_ovf_cnt_lsch1_int_st. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: OVF_CNT_LSCH2_INT_ST + description: reg_ovf_cnt_lsch2_int_st. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: OVF_CNT_LSCH3_INT_ST + description: reg_ovf_cnt_lsch3_int_st. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: OVF_CNT_LSCH4_INT_ST + description: reg_ovf_cnt_lsch4_int_st. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: OVF_CNT_LSCH5_INT_ST + description: reg_ovf_cnt_lsch5_int_st. + bitOffset: 15 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: LEDC_INT_ENA. + addressOffset: 200 + size: 32 + fields: + - name: LSTIMER0_OVF_INT_ENA + description: reg_lstimer0_ovf_int_ena. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LSTIMER1_OVF_INT_ENA + description: reg_lstimer1_ovf_int_ena. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: LSTIMER2_OVF_INT_ENA + description: reg_lstimer2_ovf_int_ena. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: LSTIMER3_OVF_INT_ENA + description: reg_lstimer3_ovf_int_ena. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_LSCH0_INT_ENA + description: reg_duty_chng_end_lsch0_int_ena. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_LSCH1_INT_ENA + description: reg_duty_chng_end_lsch1_int_ena. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_LSCH2_INT_ENA + description: reg_duty_chng_end_lsch2_int_ena. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_LSCH3_INT_ENA + description: reg_duty_chng_end_lsch3_int_ena. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_LSCH4_INT_ENA + description: reg_duty_chng_end_lsch4_int_ena. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_LSCH5_INT_ENA + description: reg_duty_chng_end_lsch5_int_ena. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OVF_CNT_LSCH0_INT_ENA + description: reg_ovf_cnt_lsch0_int_ena. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OVF_CNT_LSCH1_INT_ENA + description: reg_ovf_cnt_lsch1_int_ena. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: OVF_CNT_LSCH2_INT_ENA + description: reg_ovf_cnt_lsch2_int_ena. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: OVF_CNT_LSCH3_INT_ENA + description: reg_ovf_cnt_lsch3_int_ena. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: OVF_CNT_LSCH4_INT_ENA + description: reg_ovf_cnt_lsch4_int_ena. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: OVF_CNT_LSCH5_INT_ENA + description: reg_ovf_cnt_lsch5_int_ena. + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: LEDC_INT_CLR. + addressOffset: 204 + size: 32 + fields: + - name: LSTIMER0_OVF_INT_CLR + description: reg_lstimer0_ovf_int_clr. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: LSTIMER1_OVF_INT_CLR + description: reg_lstimer1_ovf_int_clr. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: LSTIMER2_OVF_INT_CLR + description: reg_lstimer2_ovf_int_clr. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: LSTIMER3_OVF_INT_CLR + description: reg_lstimer3_ovf_int_clr. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_LSCH0_INT_CLR + description: reg_duty_chng_end_lsch0_int_clr. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_LSCH1_INT_CLR + description: reg_duty_chng_end_lsch1_int_clr. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_LSCH2_INT_CLR + description: reg_duty_chng_end_lsch2_int_clr. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_LSCH3_INT_CLR + description: reg_duty_chng_end_lsch3_int_clr. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_LSCH4_INT_CLR + description: reg_duty_chng_end_lsch4_int_clr. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_LSCH5_INT_CLR + description: reg_duty_chng_end_lsch5_int_clr. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: OVF_CNT_LSCH0_INT_CLR + description: reg_ovf_cnt_lsch0_int_clr. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: OVF_CNT_LSCH1_INT_CLR + description: reg_ovf_cnt_lsch1_int_clr. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: OVF_CNT_LSCH2_INT_CLR + description: reg_ovf_cnt_lsch2_int_clr. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: OVF_CNT_LSCH3_INT_CLR + description: reg_ovf_cnt_lsch3_int_clr. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: OVF_CNT_LSCH4_INT_CLR + description: reg_ovf_cnt_lsch4_int_clr. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: OVF_CNT_LSCH5_INT_CLR + description: reg_ovf_cnt_lsch5_int_clr. + bitOffset: 15 + bitWidth: 1 + access: write-only + - register: + name: CONF + description: LEDC_CONF. + addressOffset: 208 + size: 32 + fields: + - name: APB_CLK_SEL + description: reg_apb_clk_sel. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CLK_EN + description: reg_clk_en. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: LEDC_DATE. + addressOffset: 252 + size: 32 + resetValue: 419829504 + fields: + - name: LEDC_DATE + description: reg_ledc_date. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: RMT + description: Remote Control + groupName: RMT + baseAddress: 1610702848 + addressBlock: + - offset: 0 + size: 120 + usage: registers + interrupt: + - name: RMT + value: 28 + registers: + - register: + dim: 4 + dimIncrement: 4 + dimIndex: "0,1,2,3" + name: CH%sDATA + description: RMT_CH%sDATA_REG. + addressOffset: 0 + size: 32 + fields: + - name: DATA + description: Reserved. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 2 + dimIncrement: 4 + dimIndex: "0,1" + name: CH%s_TX_CONF0 + description: RMT_CH%sCONF%s_REG. + addressOffset: 16 + size: 32 + resetValue: 7406080 + fields: + - name: TX_START + description: reg_tx_start_ch0. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: MEM_RD_RST + description: reg_mem_rd_rst_ch0. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: APB_MEM_RST + description: reg_apb_mem_rst_ch0. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TX_CONTI_MODE + description: reg_tx_conti_mode_ch0. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MEM_TX_WRAP_EN + description: reg_mem_tx_wrap_en_ch0. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IDLE_OUT_LV + description: reg_idle_out_lv_ch0. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: IDLE_OUT_EN + description: reg_idle_out_en_ch0. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_STOP + description: reg_tx_stop_ch0. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DIV_CNT + description: reg_div_cnt_ch0. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: MEM_SIZE + description: reg_mem_size_ch0. + bitOffset: 16 + bitWidth: 3 + access: read-write + - name: CARRIER_EFF_EN + description: reg_carrier_eff_en_ch0. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CARRIER_EN + description: reg_carrier_en_ch0. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CARRIER_OUT_LV + description: reg_carrier_out_lv_ch0. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: AFIFO_RST + description: reg_afifo_rst_ch0. + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: CONF_UPDATE + description: reg_reg_conf_update_ch0. + bitOffset: 24 + bitWidth: 1 + access: write-only + - register: + dim: 2 + dimIncrement: 8 + dimIndex: "2,3" + name: CH%s_RX_CONF0 + description: RMT_CH2CONF0_REG. + addressOffset: 24 + size: 32 + resetValue: 822083330 + fields: + - name: DIV_CNT + description: reg_div_cnt_ch2. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: IDLE_THRES + description: reg_idle_thres_ch2. + bitOffset: 8 + bitWidth: 15 + access: read-write + - name: MEM_SIZE + description: reg_mem_size_ch2. + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: CARRIER_EN + description: reg_carrier_en_ch2. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CARRIER_OUT_LV + description: reg_carrier_out_lv_ch2. + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + dim: 2 + dimIncrement: 8 + dimIndex: "2,3" + name: CH%s_RX_CONF1 + description: RMT_CH2CONF1_REG. + addressOffset: 28 + size: 32 + resetValue: 488 + fields: + - name: RX_EN + description: reg_rx_en_ch2. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_WR_RST + description: reg_mem_wr_rst_ch2. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: APB_MEM_RST + description: reg_apb_mem_rst_ch2. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: MEM_OWNER + description: reg_mem_owner_ch2. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_FILTER_EN + description: reg_rx_filter_en_ch2. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_FILTER_THRES + description: reg_rx_filter_thres_ch2. + bitOffset: 5 + bitWidth: 8 + access: read-write + - name: MEM_RX_WRAP_EN + description: reg_mem_rx_wrap_en_ch2. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: AFIFO_RST + description: reg_afifo_rst_ch2. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: CONF_UPDATE + description: reg_conf_update_ch2. + bitOffset: 15 + bitWidth: 1 + access: write-only + - register: + dim: 2 + dimIncrement: 4 + dimIndex: "0,1" + name: CH%s_TX_STATUS + description: RMT_CH%sSTATUS_REG. + addressOffset: 40 + size: 32 + fields: + - name: MEM_RADDR_EX + description: reg_mem_raddr_ex_ch0. + bitOffset: 0 + bitWidth: 9 + access: read-only + - name: STATE + description: reg_state_ch0. + bitOffset: 9 + bitWidth: 3 + access: read-only + - name: APB_MEM_WADDR + description: reg_apb_mem_waddr_ch0. + bitOffset: 12 + bitWidth: 9 + access: read-only + - name: APB_MEM_RD_ERR + description: reg_apb_mem_rd_err_ch0. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: MEM_EMPTY + description: reg_mem_empty_ch0. + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: APB_MEM_WR_ERR + description: reg_apb_mem_wr_err_ch0. + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: APB_MEM_RADDR + description: reg_apb_mem_raddr_ch0. + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + dim: 2 + dimIncrement: 4 + dimIndex: "2,3" + name: CH%s_RX_STATUS + description: RMT_CH2STATUS_REG. + addressOffset: 48 + size: 32 + fields: + - name: MEM_WADDR_EX + description: reg_mem_waddr_ex_ch2. + bitOffset: 0 + bitWidth: 9 + access: read-only + - name: APB_MEM_RADDR + description: reg_apb_mem_raddr_ch2. + bitOffset: 12 + bitWidth: 9 + access: read-only + - name: STATE + description: reg_state_ch2. + bitOffset: 22 + bitWidth: 3 + access: read-only + - name: MEM_OWNER_ERR + description: reg_mem_owner_err_ch2. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: MEM_FULL + description: reg_mem_full_ch2. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: APB_MEM_RD_ERR + description: reg_apb_mem_rd_err_ch2. + bitOffset: 27 + bitWidth: 1 + access: read-only + - register: + name: INT_RAW + description: RMT_INT_RAW_REG. + addressOffset: 56 + size: 32 + fields: + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_END + description: reg_ch%s_tx_end_int_raw. + bitOffset: 0 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_END + description: reg_ch2_rx_end_int_raw. + bitOffset: 2 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_ERR + description: reg_ch%s_err_int_raw. + bitOffset: 4 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_ERR + description: reg_ch2_err_int_raw. + bitOffset: 6 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_THR_EVENT + description: reg_ch%s_tx_thr_event_int_raw. + bitOffset: 8 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_THR_EVENT + description: reg_ch2_rx_thr_event_int_raw. + bitOffset: 10 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_LOOP + description: reg_ch%s_tx_loop_int_raw. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: RMT_INT_ST_REG. + addressOffset: 60 + size: 32 + fields: + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_END + description: reg_ch%s_tx_end_int_st. + bitOffset: 0 + bitWidth: 1 + access: read-only + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_END + description: reg_ch2_rx_end_int_st. + bitOffset: 2 + bitWidth: 1 + access: read-only + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_ERR + description: reg_ch%s_err_int_st. + bitOffset: 4 + bitWidth: 1 + access: read-only + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_ERR + description: reg_ch2_err_int_st. + bitOffset: 6 + bitWidth: 1 + access: read-only + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_THR_EVENT + description: reg_ch%s_tx_thr_event_int_st. + bitOffset: 8 + bitWidth: 1 + access: read-only + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_THR_EVENT + description: reg_ch2_rx_thr_event_int_st. + bitOffset: 10 + bitWidth: 1 + access: read-only + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_LOOP + description: reg_ch%s_tx_loop_int_st. + bitOffset: 12 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: RMT_INT_ENA_REG. + addressOffset: 64 + size: 32 + fields: + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_END + description: reg_ch%s_tx_end_int_ena. + bitOffset: 0 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_END + description: reg_ch2_rx_end_int_ena. + bitOffset: 2 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_ERR + description: reg_ch%s_err_int_ena. + bitOffset: 4 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_ERR + description: reg_ch2_err_int_ena. + bitOffset: 6 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_THR_EVENT + description: reg_ch%s_tx_thr_event_int_ena. + bitOffset: 8 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_THR_EVENT + description: reg_ch2_rx_thr_event_int_ena. + bitOffset: 10 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_LOOP + description: reg_ch%s_tx_loop_int_ena. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: RMT_INT_CLR_REG. + addressOffset: 68 + size: 32 + fields: + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_END + description: reg_ch%s_tx_end_int_clr. + bitOffset: 0 + bitWidth: 1 + access: write-only + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_END + description: reg_ch2_rx_end_int_clr. + bitOffset: 2 + bitWidth: 1 + access: write-only + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_ERR + description: reg_ch%s_err_int_clr. + bitOffset: 4 + bitWidth: 1 + access: write-only + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_ERR + description: reg_ch2_err_int_clr. + bitOffset: 6 + bitWidth: 1 + access: write-only + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_THR_EVENT + description: reg_ch%s_tx_thr_event_int_clr. + bitOffset: 8 + bitWidth: 1 + access: write-only + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_THR_EVENT + description: reg_ch2_rx_thr_event_int_clr. + bitOffset: 10 + bitWidth: 1 + access: write-only + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_LOOP + description: reg_ch%s_tx_loop_int_clr. + bitOffset: 12 + bitWidth: 1 + access: write-only + - register: + dim: 2 + dimIncrement: 4 + dimIndex: "0,1" + name: CH%sCARRIER_DUTY + description: RMT_CH%sCARRIER_DUTY_REG. + addressOffset: 72 + size: 32 + resetValue: 4194368 + fields: + - name: CARRIER_LOW + description: reg_carrier_low_ch0. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CARRIER_HIGH + description: reg_carrier_high_ch0. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + dim: 2 + dimIncrement: 4 + dimIndex: "2,3" + name: CH%s_RX_CARRIER_RM + description: RMT_CH2_RX_CARRIER_RM_REG. + addressOffset: 80 + size: 32 + fields: + - name: CARRIER_LOW_THRES + description: reg_carrier_low_thres_ch2. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CARRIER_HIGH_THRES + description: reg_carrier_high_thres_ch2. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + dim: 2 + dimIncrement: 4 + dimIndex: "0,1" + name: CH%s_TX_LIM + description: RMT_CH%s_TX_LIM_REG. + addressOffset: 88 + size: 32 + resetValue: 128 + fields: + - name: TX_LIM + description: reg_rmt_tx_lim_ch0. + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: TX_LOOP_NUM + description: reg_rmt_tx_loop_num_ch0. + bitOffset: 9 + bitWidth: 10 + access: read-write + - name: TX_LOOP_CNT_EN + description: reg_rmt_tx_loop_cnt_en_ch0. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: LOOP_COUNT_RESET + description: reg_loop_count_reset_ch0. + bitOffset: 20 + bitWidth: 1 + access: write-only + - register: + dim: 2 + dimIncrement: 4 + dimIndex: "2,3" + name: CH%s_RX_LIM + description: RMT_CH2_RX_LIM_REG. + addressOffset: 96 + size: 32 + resetValue: 128 + fields: + - name: RX_LIM + description: reg_rmt_rx_lim_ch2. + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SYS_CONF + description: RMT_SYS_CONF_REG. + addressOffset: 104 + size: 32 + resetValue: 83886096 + fields: + - name: APB_FIFO_MASK + description: reg_apb_fifo_mask. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_CLK_FORCE_ON + description: reg_mem_clk_force_on. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PD + description: reg_rmt_mem_force_pd. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PU + description: reg_rmt_mem_force_pu. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SCLK_DIV_NUM + description: reg_rmt_sclk_div_num. + bitOffset: 4 + bitWidth: 8 + access: read-write + - name: SCLK_DIV_A + description: reg_rmt_sclk_div_a. + bitOffset: 12 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_B + description: reg_rmt_sclk_div_b. + bitOffset: 18 + bitWidth: 6 + access: read-write + - name: SCLK_SEL + description: reg_rmt_sclk_sel. + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: SCLK_ACTIVE + description: reg_rmt_sclk_active. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: reg_clk_en. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TX_SIM + description: RMT_TX_SIM_REG. + addressOffset: 108 + size: 32 + fields: + - name: TX_SIM_CH0 + description: reg_rmt_tx_sim_ch0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_SIM_CH1 + description: reg_rmt_tx_sim_ch1. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TX_SIM_EN + description: reg_rmt_tx_sim_en. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: REF_CNT_RST + description: RMT_REF_CNT_RST_REG. + addressOffset: 112 + size: 32 + fields: + - name: CH0 + description: reg_ref_cnt_rst_ch0. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CH1 + description: reg_ref_cnt_rst_ch1. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CH2 + description: reg_ref_cnt_rst_ch2. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CH3 + description: reg_ref_cnt_rst_ch3. + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: DATE + description: RMT_DATE_REG. + addressOffset: 204 + size: 32 + resetValue: 33579569 + fields: + - name: DATE + description: reg_rmt_date. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: RNG + description: Hardware Random Number Generator + groupName: RNG + baseAddress: 1610768384 + addressBlock: + - offset: 0 + size: 4 + usage: registers + registers: + - register: + name: DATA + description: Random number data + addressOffset: 176 + size: 32 + access: read-only + - name: RSA + description: RSA (Rivest Shamir Adleman) Accelerator + groupName: RSA + baseAddress: 1610858496 + addressBlock: + - offset: 0 + size: 116 + usage: registers + interrupt: + - name: RSA + value: 47 + registers: + - register: + dim: 96 + dimIncrement: 4 + name: "M_MEM[%s]" + description: The memory that stores M + addressOffset: 0 + size: 32 + access: read-write + - register: + dim: 96 + dimIncrement: 4 + name: "Z_MEM[%s]" + description: The memory that stores Z + addressOffset: 512 + size: 32 + access: read-write + - register: + dim: 96 + dimIncrement: 4 + name: "Y_MEM[%s]" + description: The memory that stores Y + addressOffset: 1024 + size: 32 + access: read-write + - register: + dim: 96 + dimIncrement: 4 + name: "X_MEM[%s]" + description: The memory that stores X + addressOffset: 1536 + size: 32 + access: read-write + - register: + name: M_PRIME + description: RSA M_prime register + addressOffset: 2048 + size: 32 + fields: + - name: M_PRIME + description: "Those bits stores m'" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: MODE + description: RSA mode register + addressOffset: 2052 + size: 32 + fields: + - name: MODE + description: rsa mode (rsa length). + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: QUERY_CLEAN + description: RSA query clean register + addressOffset: 2056 + size: 32 + fields: + - name: QUERY_CLEAN + description: query clean + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: SET_START_MODEXP + description: RSA modular exponentiation trigger register. + addressOffset: 2060 + size: 32 + fields: + - name: SET_START_MODEXP + description: start modular exponentiation + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_START_MODMULT + description: RSA modular multiplication trigger register. + addressOffset: 2064 + size: 32 + fields: + - name: SET_START_MODMULT + description: start modular multiplication + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_START_MULT + description: RSA normal multiplication trigger register. + addressOffset: 2068 + size: 32 + fields: + - name: SET_START_MULT + description: start multiplicaiton + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: QUERY_IDLE + description: RSA query idle register + addressOffset: 2072 + size: 32 + fields: + - name: QUERY_IDLE + description: "query rsa idle. 1'b0: busy, 1'b1: idle" + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: RSA interrupt clear register + addressOffset: 2076 + size: 32 + fields: + - name: CLEAR_INTERRUPT + description: set this bit to clear RSA interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: CONSTANT_TIME + description: RSA constant time option register + addressOffset: 2080 + size: 32 + resetValue: 1 + fields: + - name: CONSTANT_TIME + description: "Configure this bit to 0 for acceleration. 0: with acceleration, 1: without acceleration(defalut)." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SEARCH_ENABLE + description: RSA search option + addressOffset: 2084 + size: 32 + fields: + - name: SEARCH_ENABLE + description: "Configure this bit to 1 for acceleration. 1: with acceleration, 0: without acceleration(default). This option should be used together with RSA_SEARCH_POS." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SEARCH_POS + description: RSA search position configure register + addressOffset: 2088 + size: 32 + fields: + - name: SEARCH_POS + description: Configure this field to set search position. This field should be used together with RSA_SEARCH_ENABLE. The field is only meaningful when RSA_SEARCH_ENABLE is high. + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: INT_ENA + description: RSA interrupt enable register + addressOffset: 2092 + size: 32 + fields: + - name: INT_ENA + description: "Set this bit to enable interrupt that occurs when rsa calculation is done. 1'b0: disable, 1'b1: enable(default)." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: RSA version control register + addressOffset: 2096 + size: 32 + resetValue: 538969624 + fields: + - name: DATE + description: rsa version information + bitOffset: 0 + bitWidth: 30 + access: read-write + - name: RTC_CNTL + description: Real-Time Clock Control + groupName: RTC_CNTL + baseAddress: 1610645504 + addressBlock: + - offset: 0 + size: 300 + usage: registers + interrupt: + - name: RTC_CORE + value: 27 + registers: + - register: + name: OPTIONS0 + description: rtc configure register + addressOffset: 0 + size: 32 + resetValue: 469803008 + fields: + - name: SW_STALL_APPCPU_C0 + description: "{reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SW_STALL_PROCPU_C0 + description: "{reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: SW_APPCPU_RST + description: APP CPU SW reset + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SW_PROCPU_RST + description: PRO CPU SW reset + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: BB_I2C_FORCE_PD + description: BB_I2C force power down + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BB_I2C_FORCE_PU + description: BB_I2C force power up + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: BBPLL_I2C_FORCE_PD + description: BB_PLL _I2C force power down + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BBPLL_I2C_FORCE_PU + description: BB_PLL_I2C force power up + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: BBPLL_FORCE_PD + description: BB_PLL force power down + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: BBPLL_FORCE_PU + description: BB_PLL force power up + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: XTL_FORCE_PD + description: crystall force power down + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: XTL_FORCE_PU + description: crystall force power up + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: XTL_EN_WAIT + description: wait bias_sleep and current source wakeup + bitOffset: 14 + bitWidth: 4 + access: read-write + - name: XTL_EXT_CTR_SEL + description: analog configure + bitOffset: 20 + bitWidth: 3 + access: read-write + - name: XTL_FORCE_ISO + description: analog configure + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: PLL_FORCE_ISO + description: analog configure + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ANALOG_FORCE_ISO + description: analog configure + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: XTL_FORCE_NOISO + description: analog configure + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: PLL_FORCE_NOISO + description: analog configure + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: ANALOG_FORCE_NOISO + description: analog configure + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_RST + description: digital wrap force reset in deep sleep + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_NORST + description: digital core force no reset in deep sleep + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SW_SYS_RST + description: SW system reset + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SLP_TIMER0 + description: rtc configure register + addressOffset: 4 + size: 32 + fields: + - name: SLP_VAL_LO + description: configure the sleep time + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SLP_TIMER1 + description: rtc configure register + addressOffset: 8 + size: 32 + fields: + - name: SLP_VAL_HI + description: RTC sleep timer high 16 bits + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MAIN_TIMER_ALARM_EN + description: timer alarm enable bit + bitOffset: 16 + bitWidth: 1 + access: write-only + - register: + name: TIME_UPDATE + description: rtc configure register + addressOffset: 12 + size: 32 + fields: + - name: TIMER_SYS_STALL + description: Enable to record system stall time + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: TIMER_XTL_OFF + description: Enable to record 40M XTAL OFF time + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: TIMER_SYS_RST + description: enable to record system reset time + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TIME_UPDATE + description: "Set 1: to update register with RTC timer" + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: TIME_LOW0 + description: rtc configure register + addressOffset: 16 + size: 32 + fields: + - name: TIMER_VALUE0_LOW + description: RTC timer low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: TIME_HIGH0 + description: rtc configure register + addressOffset: 20 + size: 32 + fields: + - name: TIMER_VALUE0_HIGH + description: RTC timer high 16 bits + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: STATE0 + description: rtc configure register + addressOffset: 24 + size: 32 + fields: + - name: SW_CPU_INT + description: rtc software interrupt to main cpu + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SLP_REJECT_CAUSE_CLR + description: clear rtc sleep reject cause + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: APB2RTC_BRIDGE_SEL + description: "1: APB to RTC using bridge" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SDIO_ACTIVE_IND + description: SDIO active indication + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SLP_WAKEUP + description: leep wakeup bit + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SLP_REJECT + description: leep reject bit + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SLEEP_EN + description: sleep enable bit + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TIMER1 + description: rtc configure register + addressOffset: 28 + size: 32 + resetValue: 672400387 + fields: + - name: CPU_STALL_EN + description: CPU stall enable bit + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CPU_STALL_WAIT + description: CPU stall wait cycles in fast_clk_rtc + bitOffset: 1 + bitWidth: 5 + access: read-write + - name: CK8M_WAIT + description: CK8M wait cycles in slow_clk_rtc + bitOffset: 6 + bitWidth: 8 + access: read-write + - name: XTL_BUF_WAIT + description: XTAL wait cycles in slow_clk_rtc + bitOffset: 14 + bitWidth: 10 + access: read-write + - name: PLL_BUF_WAIT + description: PLL wait cycles in slow_clk_rtc + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: TIMER2 + description: rtc configure register + addressOffset: 32 + size: 32 + resetValue: 16777216 + fields: + - name: MIN_TIME_CK8M_OFF + description: minimal cycles in slow_clk_rtc for CK8M in power down state + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: TIMER3 + description: rtc configure register + addressOffset: 36 + size: 32 + resetValue: 168299016 + fields: + - name: WIFI_WAIT_TIMER + description: wifi power domain wakeup time + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: WIFI_POWERUP_TIMER + description: wifi power domain power on time + bitOffset: 9 + bitWidth: 7 + access: read-write + - name: BT_WAIT_TIMER + description: bt power domain wakeup time + bitOffset: 16 + bitWidth: 9 + access: read-write + - name: BT_POWERUP_TIMER + description: bt power domain power on time + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: TIMER4 + description: rtc configure register + addressOffset: 40 + size: 32 + resetValue: 270535176 + fields: + - name: CPU_TOP_WAIT_TIMER + description: cpu top power domain wakeup time + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: CPU_TOP_POWERUP_TIMER + description: cpu top power domain power on time + bitOffset: 9 + bitWidth: 7 + access: read-write + - name: DG_WRAP_WAIT_TIMER + description: digital wrap power domain wakeup time + bitOffset: 16 + bitWidth: 9 + access: read-write + - name: DG_WRAP_POWERUP_TIMER + description: digital wrap power domain power on time + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: TIMER5 + description: rtc configure register + addressOffset: 44 + size: 32 + resetValue: 32768 + fields: + - name: MIN_SLP_VAL + description: minimal sleep cycles in slow_clk_rtc + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: TIMER6 + description: rtc configure register + addressOffset: 48 + size: 32 + resetValue: 168296448 + fields: + - name: DG_PERI_WAIT_TIMER + description: digital peri power domain wakeup time + bitOffset: 16 + bitWidth: 9 + access: read-write + - name: DG_PERI_POWERUP_TIMER + description: digital peri power domain power on time + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: ANA_CONF + description: rtc configure register + addressOffset: 52 + size: 32 + resetValue: 12845056 + fields: + - name: RESET_POR_FORCE_PD + description: force no bypass i2c power on reset + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RESET_POR_FORCE_PU + description: force bypass i2c power on reset + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: GLITCH_RST_EN + description: enable glitch reset + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SAR_I2C_PU + description: PLLA force power up + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: PLLA_FORCE_PD + description: PLLA force power down + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: PLLA_FORCE_PU + description: PLLA force power up + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: BBPLL_CAL_SLP_START + description: start BBPLL calibration during sleep + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PVTMON_PU + description: "1: PVTMON power up" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TXRF_I2C_PU + description: "1: TXRF_I2C power up" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RFRX_PBUS_PU + description: "1: RFRX_PBUS power up" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CKGEN_I2C_PU + description: "1: CKGEN_I2C power up" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: PLL_I2C_PU + description: power up pll i2c + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RESET_STATE + description: rtc configure register + addressOffset: 56 + size: 32 + resetValue: 12288 + fields: + - name: RESET_CAUSE_PROCPU + description: reset cause of PRO CPU + bitOffset: 0 + bitWidth: 6 + access: read-only + - name: RESET_CAUSE_APPCPU + description: reset cause of APP CPU + bitOffset: 6 + bitWidth: 6 + access: read-only + - name: STAT_VECTOR_SEL_APPCPU + description: APP CPU state vector sel + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: STAT_VECTOR_SEL_PROCPU + description: PRO CPU state vector sel + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: ALL_RESET_FLAG_PROCPU + description: PRO CPU reset_flag + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: ALL_RESET_FLAG_APPCPU + description: APP CPU reset flag + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: ALL_RESET_FLAG_CLR_PROCPU + description: clear PRO CPU reset_flag + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: ALL_RESET_FLAG_CLR_APPCPU + description: clear APP CPU reset flag + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: OCD_HALT_ON_RESET_APPCPU + description: APPCPU OcdHaltOnReset + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: OCD_HALT_ON_RESET_PROCPU + description: PROCPU OcdHaltOnReset + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: JTAG_RESET_FLAG_PROCPU + description: configure jtag reset configure + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: JTAG_RESET_FLAG_APPCPU + description: configure jtag reset configure + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: JTAG_RESET_FLAG_CLR_PROCPU + description: configure jtag reset configure + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: JTAG_RESET_FLAG_CLR_APPCPU + description: configure jtag reset configure + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: DRESET_MASK_APPCPU + description: configure dreset configure + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: DRESET_MASK_PROCPU + description: configure dreset configure + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: WAKEUP_STATE + description: rtc configure register + addressOffset: 60 + size: 32 + resetValue: 393216 + fields: + - name: WAKEUP_ENA + description: wakeup enable bitmap + bitOffset: 15 + bitWidth: 17 + access: read-write + - register: + name: INT_ENA_RTC + description: rtc configure register + addressOffset: 64 + size: 32 + fields: + - name: SLP_WAKEUP_INT_ENA + description: enable sleep wakeup interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_REJECT_INT_ENA + description: enable sleep reject interrupt + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: WDT_INT_ENA + description: enable RTC WDT interrupt + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_INT_ENA + description: enable brown out interrupt + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: MAIN_TIMER_INT_ENA + description: enable RTC main timer interrupt + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SWD_INT_ENA + description: enable super watch dog interrupt + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: XTAL32K_DEAD_INT_ENA + description: enable xtal32k_dead interrupt + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: GLITCH_DET_INT_ENA + description: enbale gitch det interrupt + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: BBPLL_CAL_INT_ENA + description: enbale bbpll cal end interrupt + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW_RTC + description: rtc configure register + addressOffset: 68 + size: 32 + fields: + - name: SLP_WAKEUP_INT_RAW + description: sleep wakeup interrupt raw + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SLP_REJECT_INT_RAW + description: sleep reject interrupt raw + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: WDT_INT_RAW + description: RTC WDT interrupt raw + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BROWN_OUT_INT_RAW + description: brown out interrupt raw + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: MAIN_TIMER_INT_RAW + description: RTC main timer interrupt raw + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SWD_INT_RAW + description: super watch dog interrupt raw + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: XTAL32K_DEAD_INT_RAW + description: xtal32k dead detection interrupt raw + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: GLITCH_DET_INT_RAW + description: glitch_det_interrupt_raw + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: BBPLL_CAL_INT_RAW + description: bbpll cal end interrupt state + bitOffset: 20 + bitWidth: 1 + access: read-only + - register: + name: INT_ST_RTC + description: rtc configure register + addressOffset: 72 + size: 32 + fields: + - name: SLP_WAKEUP_INT_ST + description: sleep wakeup interrupt state + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SLP_REJECT_INT_ST + description: sleep reject interrupt state + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: WDT_INT_ST + description: RTC WDT interrupt state + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BROWN_OUT_INT_ST + description: brown out interrupt state + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: MAIN_TIMER_INT_ST + description: RTC main timer interrupt state + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SWD_INT_ST + description: super watch dog interrupt state + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: XTAL32K_DEAD_INT_ST + description: xtal32k dead detection interrupt state + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: GLITCH_DET_INT_ST + description: glitch_det_interrupt state + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: BBPLL_CAL_INT_ST + description: bbpll cal end interrupt state + bitOffset: 20 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR_RTC + description: rtc configure register + addressOffset: 76 + size: 32 + fields: + - name: SLP_WAKEUP_INT_CLR + description: Clear sleep wakeup interrupt state + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SLP_REJECT_INT_CLR + description: Clear sleep reject interrupt state + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: WDT_INT_CLR + description: Clear RTC WDT interrupt state + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: BROWN_OUT_INT_CLR + description: Clear brown out interrupt state + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: MAIN_TIMER_INT_CLR + description: Clear RTC main timer interrupt state + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SWD_INT_CLR + description: Clear super watch dog interrupt state + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: XTAL32K_DEAD_INT_CLR + description: Clear RTC WDT interrupt state + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: GLITCH_DET_INT_CLR + description: Clear glitch det interrupt state + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: BBPLL_CAL_INT_CLR + description: clear bbpll cal end interrupt state + bitOffset: 20 + bitWidth: 1 + access: write-only + - register: + name: STORE0 + description: rtc configure register + addressOffset: 80 + size: 32 + fields: + - name: SCRATCH0 + description: reserved register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE1 + description: rtc configure register + addressOffset: 84 + size: 32 + fields: + - name: SCRATCH1 + description: reserved register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE2 + description: rtc configure register + addressOffset: 88 + size: 32 + fields: + - name: SCRATCH2 + description: reserved register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE3 + description: rtc configure register + addressOffset: 92 + size: 32 + fields: + - name: SCRATCH3 + description: reserved register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: EXT_XTL_CONF + description: rtc configure register + addressOffset: 96 + size: 32 + resetValue: 420992 + fields: + - name: XTAL32K_WDT_EN + description: xtal 32k watch dog enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: XTAL32K_WDT_CLK_FO + description: xtal 32k watch dog clock force on + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: XTAL32K_WDT_RESET + description: xtal 32k watch dog sw reset + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: XTAL32K_EXT_CLK_FO + description: xtal 32k external xtal clock force on + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: XTAL32K_AUTO_BACKUP + description: xtal 32k switch to back up clock when xtal is dead + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: XTAL32K_AUTO_RESTART + description: xtal 32k restart xtal when xtal is dead + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: XTAL32K_AUTO_RETURN + description: xtal 32k switch back xtal when xtal is restarted + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: XTAL32K_XPD_FORCE + description: Xtal 32k xpd control by sw or fsm + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: ENCKINIT_XTAL_32K + description: apply an internal clock to help xtal 32k to start + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DBUF_XTAL_32K + description: "0: single-end buffer 1: differential buffer" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DGM_XTAL_32K + description: xtal_32k gm control + bitOffset: 10 + bitWidth: 3 + access: read-write + - name: DRES_XTAL_32K + description: DRES_XTAL_32K + bitOffset: 13 + bitWidth: 3 + access: read-write + - name: XPD_XTAL_32K + description: XPD_XTAL_32K + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DAC_XTAL_32K + description: DAC_XTAL_32K + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: WDT_STATE + description: state of 32k_wdt + bitOffset: 20 + bitWidth: 3 + access: read-only + - name: XTAL32K_GPIO_SEL + description: "XTAL_32K sel. 0: external XTAL_32K" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: XTL_EXT_CTR_LV + description: "0: power down XTAL at high level" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: XTL_EXT_CTR_EN + description: enable gpio configure xtal power on + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EXT_WAKEUP_CONF + description: rtc configure register + addressOffset: 100 + size: 32 + fields: + - name: GPIO_WAKEUP_FILTER + description: enable filter for gpio wakeup event + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SLP_REJECT_CONF + description: rtc configure register + addressOffset: 104 + size: 32 + fields: + - name: SLEEP_REJECT_ENA + description: sleep reject enable + bitOffset: 12 + bitWidth: 18 + access: read-write + - name: LIGHT_SLP_REJECT_EN + description: enable reject for light sleep + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DEEP_SLP_REJECT_EN + description: enable reject for deep sleep + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CPU_PERIOD_CONF + description: rtc configure register + addressOffset: 108 + size: 32 + fields: + - name: CPUSEL_CONF + description: CPU sel option + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CPUPERIOD_SEL + description: CPU clk sel option + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CLK_CONF + description: rtc configure register + addressOffset: 112 + size: 32 + resetValue: 290992664 + fields: + - name: EFUSE_CLK_FORCE_GATING + description: efuse_clk_force_gating + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EFUSE_CLK_FORCE_NOGATING + description: efuse_clk_force_nogating + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CK8M_DIV_SEL_VLD + description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CK8M_DIV + description: "CK8M_D256_OUT divider. 00: div128" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: ENB_CK8M + description: disable CK8M and CK8M_D256_OUT + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: ENB_CK8M_DIV + description: "1: CK8M_D256_OUT is actually CK8M" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DIG_XTAL32K_EN + description: enable CK_XTAL_32K for digital core (no relationship with RTC core) + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DIG_CLK8M_D256_EN + description: enable CK8M_D256_OUT for digital core (no relationship with RTC core) + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DIG_CLK8M_EN + description: enable CK8M for digital core (no relationship with RTC core) + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CK8M_DIV_SEL + description: divider = reg_ck8m_div_sel + 1 + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: XTAL_FORCE_NOGATING + description: XTAL force no gating during sleep + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CK8M_FORCE_NOGATING + description: CK8M force no gating during sleep + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CK8M_DFREQ + description: CK8M_DFREQ + bitOffset: 17 + bitWidth: 8 + access: read-write + - name: CK8M_FORCE_PD + description: CK8M force power down + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: CK8M_FORCE_PU + description: CK8M force power up + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: XTAL_GLOBAL_FORCE_GATING + description: force enable xtal clk gating + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: XTAL_GLOBAL_FORCE_NOGATING + description: force bypass xtal clk gating + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: FAST_CLK_RTC_SEL + description: "fast_clk_rtc sel. 0: XTAL div 4" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ANA_CLK_RTC_SEL + description: slelect rtc slow clk + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: SLOW_CLK_CONF + description: rtc configure register + addressOffset: 116 + size: 32 + resetValue: 4194304 + fields: + - name: ANA_CLK_DIV_VLD + description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: ANA_CLK_DIV + description: the clk divider num of RTC_CLK + bitOffset: 23 + bitWidth: 8 + access: read-write + - name: SLOW_CLK_NEXT_EDGE + description: flag rtc_slow_clk_next_edge + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SDIO_CONF + description: rtc configure register + addressOffset: 120 + size: 32 + resetValue: 179355146 + fields: + - name: SDIO_TIMER_TARGET + description: timer count to apply reg_sdio_dcap after sdio power on + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SDIO_DTHDRV + description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge current + bitOffset: 9 + bitWidth: 2 + access: read-write + - name: SDIO_DCAP + description: ability to prevent LDO from overshoot + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: SDIO_INITI + description: "add resistor from ldo output to ground. 0: no res" + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: SDIO_EN_INITI + description: "0 to set init[1:0]=0" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SDIO_DCURLIM + description: tune current limit threshold when tieh = 0. About 800mA/(8+d) + bitOffset: 16 + bitWidth: 3 + access: read-write + - name: SDIO_MODECURLIM + description: select current limit mode + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SDIO_ENCURLIM + description: enable current limit + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SDIO_REG_PD_EN + description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SDIO_FORCE + description: "1: use SW option to control SDIO_REG" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SDIO_TIEH + description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1 + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: _1P8_READY + description: read only register for REG1P8_READY + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: DREFL_SDIO + description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1 + bitOffset: 25 + bitWidth: 2 + access: read-write + - name: DREFM_SDIO + description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1 + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: DREFH_SDIO + description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1 + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: XPD_SDIO + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: BIAS_CONF + description: rtc configure register + addressOffset: 124 + size: 32 + resetValue: 67584 + fields: + - name: DG_VDD_DRV_B_SLP + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: DG_VDD_DRV_B_SLP_EN + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BIAS_BUF_IDLE + description: bias buf when rtc in normal work state + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: BIAS_BUF_WAKE + description: bias buf when rtc in wakeup state + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: BIAS_BUF_DEEP_SLP + description: bias buf when rtc in sleep state + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: BIAS_BUF_MONITOR + description: bias buf when rtc in monitor state + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: PD_CUR_DEEP_SLP + description: xpd cur when rtc in sleep_state + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PD_CUR_MONITOR + description: xpd cur when rtc in monitor state + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: BIAS_SLEEP_DEEP_SLP + description: bias_sleep when rtc in sleep_state + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: BIAS_SLEEP_MONITOR + description: bias_sleep when rtc in monitor state + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: DBG_ATTEN_DEEP_SLP + description: DBG_ATTEN when rtc in sleep state + bitOffset: 18 + bitWidth: 4 + access: read-write + - name: DBG_ATTEN_MONITOR + description: DBG_ATTEN when rtc in monitor state + bitOffset: 22 + bitWidth: 4 + access: read-write + - register: + name: RTC_CNTL + description: rtc configure register + addressOffset: 128 + size: 32 + resetValue: 2684354560 + fields: + - name: DIG_REG_CAL_EN + description: software enable digital regulator cali + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SCK_DCAP + description: SCK_DCAP + bitOffset: 14 + bitWidth: 8 + access: read-write + - name: DBOOST_FORCE_PD + description: RTC_DBOOST force power down + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DBOOST_FORCE_PU + description: RTC_DBOOST force power up + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: REGULATOR_FORCE_PD + description: RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower ) + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: REGULATOR_FORCE_PU + description: RTC_REG force power up + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: PWC + description: rtc configure register + addressOffset: 132 + size: 32 + fields: + - name: PAD_FORCE_HOLD + description: rtc pad force hold + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + name: DIG_PWC + description: rtc configure register + addressOffset: 136 + size: 32 + resetValue: 5591056 + fields: + - name: VDD_SPI_PWR_DRV + description: "vdd_spi drv's software value" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: VDD_SPI_PWR_FORCE + description: vdd_spi drv use software value + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: LSLP_MEM_FORCE_PD + description: memories in digital core force PD in sleep + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: LSLP_MEM_FORCE_PU + description: memories in digital core force PU in sleep + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: BT_FORCE_PD + description: bt force power down + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: BT_FORCE_PU + description: bt force power up + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DG_PERI_FORCE_PD + description: digital peri force power down + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DG_PERI_FORCE_PU + description: digital peri force power up + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: FASTMEM_FORCE_LPD + description: fastmemory retention mode in sleep + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: FASTMEM_FORCE_LPU + description: fastmemory donlt entry retention mode in sleep + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: WIFI_FORCE_PD + description: wifi force power down + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: WIFI_FORCE_PU + description: wifi force power up + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_PD + description: digital core force power down + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_PU + description: digital core force power up + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CPU_TOP_FORCE_PD + description: cpu core force power down + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CPU_TOP_FORCE_PU + description: cpu force power up + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: BT_PD_EN + description: enable power down bt in sleep + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: DG_PERI_PD_EN + description: enable power down digital peri in sleep + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CPU_TOP_PD_EN + description: enable power down cpu in sleep + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: WIFI_PD_EN + description: enable power down wifi in sleep + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DG_WRAP_PD_EN + description: enable power down digital wrap in sleep + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DIG_ISO + description: rtc configure register + addressOffset: 140 + size: 32 + resetValue: 2860535936 + fields: + - name: FORCE_OFF + description: DIG_ISO force off + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FORCE_ON + description: DIG_ISO force on + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DG_PAD_AUTOHOLD + description: read only register to indicate digital pad auto-hold status + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: CLR_DG_PAD_AUTOHOLD + description: wtite only register to clear digital pad auto-hold + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: DG_PAD_AUTOHOLD_EN + description: digital pad enable auto-hold + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DG_PAD_FORCE_NOISO + description: digital pad force no ISO + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DG_PAD_FORCE_ISO + description: digital pad force ISO + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DG_PAD_FORCE_UNHOLD + description: digital pad force un-hold + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DG_PAD_FORCE_HOLD + description: digital pad force hold + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: BT_FORCE_ISO + description: bt force ISO + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: BT_FORCE_NOISO + description: bt force no ISO + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: DG_PERI_FORCE_ISO + description: Digital peri force ISO + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: DG_PERI_FORCE_NOISO + description: digital peri force no ISO + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: CPU_TOP_FORCE_ISO + description: cpu force ISO + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CPU_TOP_FORCE_NOISO + description: cpu force no ISO + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: WIFI_FORCE_ISO + description: wifi force ISO + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: WIFI_FORCE_NOISO + description: wifi force no ISO + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_ISO + description: digital core force ISO + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_NOISO + description: digital core force no ISO + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: WDTCONFIG0 + description: rtc configure register + addressOffset: 144 + size: 32 + resetValue: 78356 + fields: + - name: WDT_CHIP_RESET_WIDTH + description: chip reset siginal pulse width + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: WDT_CHIP_RESET_EN + description: wdt reset whole chip enable + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: WDT_PAUSE_IN_SLP + description: pause WDT in sleep + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: WDT_APPCPU_RESET_EN + description: enable WDT reset APP CPU + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: WDT_PROCPU_RESET_EN + description: enable WDT reset PRO CPU + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: WDT_FLASHBOOT_MOD_EN + description: enable WDT in flash boot + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: WDT_SYS_RESET_LENGTH + description: system reset counter length + bitOffset: 13 + bitWidth: 3 + access: read-write + - name: WDT_CPU_RESET_LENGTH + description: CPU reset counter length + bitOffset: 16 + bitWidth: 3 + access: read-write + - name: WDT_STG3 + description: "1: interrupt stage en" + bitOffset: 19 + bitWidth: 3 + access: read-write + - name: WDT_STG2 + description: "1: interrupt stage en" + bitOffset: 22 + bitWidth: 3 + access: read-write + - name: WDT_STG1 + description: "1: interrupt stage en" + bitOffset: 25 + bitWidth: 3 + access: read-write + - name: WDT_STG0 + description: "1: interrupt stage en" + bitOffset: 28 + bitWidth: 3 + access: read-write + - name: WDT_EN + description: enable rtc wdt + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: WDTCONFIG1 + description: rtc configure register + addressOffset: 148 + size: 32 + resetValue: 200000 + fields: + - name: WDT_STG0_HOLD + description: the hold time of stage0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG2 + description: rtc configure register + addressOffset: 152 + size: 32 + resetValue: 80000 + fields: + - name: WDT_STG1_HOLD + description: the hold time of stage1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG3 + description: rtc configure register + addressOffset: 156 + size: 32 + resetValue: 4095 + fields: + - name: WDT_STG2_HOLD + description: the hold time of stage2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG4 + description: rtc configure register + addressOffset: 160 + size: 32 + resetValue: 4095 + fields: + - name: WDT_STG3_HOLD + description: the hold time of stage3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTFEED + description: rtc configure register + addressOffset: 164 + size: 32 + fields: + - name: WDT_FEED + description: sw feed rtc wdt + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: WDTWPROTECT + description: rtc configure register + addressOffset: 168 + size: 32 + fields: + - name: WDT_WKEY + description: the key of rtc wdt + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SWD_CONF + description: rtc configure register + addressOffset: 172 + size: 32 + resetValue: 78643200 + fields: + - name: SWD_RESET_FLAG + description: swd reset flag + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SWD_FEED_INT + description: swd interrupt for feeding + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SWD_BYPASS_RST + description: Bypass swd rst + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SWD_SIGNAL_WIDTH + description: adjust signal width send to swd + bitOffset: 18 + bitWidth: 10 + access: read-write + - name: SWD_RST_FLAG_CLR + description: reset swd reset flag + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: SWD_FEED + description: Sw feed swd + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: SWD_DISABLE + description: disabel SWD + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SWD_AUTO_FEED_EN + description: automatically feed swd when int comes + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SWD_WPROTECT + description: rtc configure register + addressOffset: 176 + size: 32 + fields: + - name: SWD_WKEY + description: the key of super wdt + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SW_CPU_STALL + description: rtc configure register + addressOffset: 180 + size: 32 + fields: + - name: SW_STALL_APPCPU_C1 + description: "{reg_sw_stall_appcpu_c1[5:0]" + bitOffset: 20 + bitWidth: 6 + access: read-write + - name: SW_STALL_PROCPU_C1 + description: stall cpu by software + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: STORE4 + description: rtc configure register + addressOffset: 184 + size: 32 + fields: + - name: SCRATCH4 + description: reserved register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE5 + description: rtc configure register + addressOffset: 188 + size: 32 + fields: + - name: SCRATCH5 + description: reserved register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE6 + description: rtc configure register + addressOffset: 192 + size: 32 + fields: + - name: SCRATCH6 + description: reserved register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE7 + description: rtc configure register + addressOffset: 196 + size: 32 + fields: + - name: SCRATCH7 + description: reserved register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOW_POWER_ST + description: rtc configure register + addressOffset: 200 + size: 32 + fields: + - name: XPD_ROM0 + description: rom0 power down + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: XPD_DIG_DCDC + description: External DCDC power down + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: PERI_ISO + description: rtc peripheral iso + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: XPD_RTC_PERI + description: rtc peripheral power down + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: WIFI_ISO + description: wifi iso + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: XPD_WIFI + description: wifi wrap power down + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: DIG_ISO + description: digital wrap iso + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: XPD_DIG + description: digital wrap power down + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TOUCH_STATE_START + description: touch should start to work + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: TOUCH_STATE_SWITCH + description: touch is about to working. Switch rtc main state + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: TOUCH_STATE_SLP + description: touch is in sleep state + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TOUCH_STATE_DONE + description: touch is done + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: COCPU_STATE_START + description: ulp/cocpu should start to work + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: COCPU_STATE_SWITCH + description: ulp/cocpu is about to working. Switch rtc main state + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: COCPU_STATE_SLP + description: ulp/cocpu is in sleep state + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: COCPU_STATE_DONE + description: ulp/cocpu is done + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: MAIN_STATE_XTAL_ISO + description: no use any more + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: MAIN_STATE_PLL_ON + description: rtc main state machine is in states that pll should be running + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: RDY_FOR_WAKEUP + description: rtc is ready to receive wake up trigger from wake up source + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: MAIN_STATE_WAIT_END + description: rtc main state machine has been waited for some cycles + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: IN_WAKEUP_STATE + description: rtc main state machine is in the states of wakeup process + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: IN_LOW_POWER_STATE + description: rtc main state machine is in the states of low power + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: MAIN_STATE_IN_WAIT_8M + description: rtc main state machine is in wait 8m state + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: MAIN_STATE_IN_WAIT_PLL + description: rtc main state machine is in wait pll state + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: MAIN_STATE_IN_WAIT_XTL + description: rtc main state machine is in wait xtal state + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: MAIN_STATE_IN_SLP + description: rtc main state machine is in sleep state + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: MAIN_STATE_IN_IDLE + description: rtc main state machine is in idle state + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: MAIN_STATE + description: rtc main state machine status + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: DIAG0 + description: rtc configure register + addressOffset: 204 + size: 32 + fields: + - name: LOW_POWER_DIAG1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PAD_HOLD + description: rtc configure register + addressOffset: 208 + size: 32 + fields: + - name: GPIO_PIN0_HOLD + description: the hold configure of rtc gpio0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: GPIO_PIN1_HOLD + description: the hold configure of rtc gpio1 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: GPIO_PIN2_HOLD + description: the hold configure of rtc gpio2 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: GPIO_PIN3_HOLD + description: the hold configure of rtc gpio3 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: GPIO_PIN4_HOLD + description: the hold configure of rtc gpio4 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: GPIO_PIN5_HOLD + description: the hold configure of rtc gpio5 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: DIG_PAD_HOLD + description: rtc configure register + addressOffset: 212 + size: 32 + fields: + - name: DIG_PAD_HOLD + description: the configure of digital pad + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BROWN_OUT + description: rtc configure register + addressOffset: 216 + size: 32 + resetValue: 1140785168 + fields: + - name: BROWN_OUT_INT_WAIT + description: brown out interrupt wait cycles + bitOffset: 4 + bitWidth: 10 + access: read-write + - name: BROWN_OUT_CLOSE_FLASH_ENA + description: enable close flash when brown out happens + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_PD_RF_ENA + description: enable power down RF when brown out happens + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_RST_WAIT + description: brown out reset wait cycles + bitOffset: 16 + bitWidth: 10 + access: read-write + - name: BROWN_OUT_RST_ENA + description: enable brown out reset + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_RST_SEL + description: "1: 4-pos reset" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_ANA_RST_EN + description: brown_out origin reset enable + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_CNT_CLR + description: clear brown out counter + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: BROWN_OUT_ENA + description: enable brown out + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DET + description: the flag of brown det from analog + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: TIME_LOW1 + description: rtc configure register + addressOffset: 220 + size: 32 + fields: + - name: TIMER_VALUE1_LOW + description: RTC timer low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: TIME_HIGH1 + description: rtc configure register + addressOffset: 224 + size: 32 + fields: + - name: TIMER_VALUE1_HIGH + description: RTC timer high 16 bits + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: XTAL32K_CLK_FACTOR + description: rtc configure register + addressOffset: 228 + size: 32 + fields: + - name: XTAL32K_CLK_FACTOR + description: xtal 32k watch dog backup clock factor + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: XTAL32K_CONF + description: rtc configure register + addressOffset: 232 + size: 32 + resetValue: 267386880 + fields: + - name: XTAL32K_RETURN_WAIT + description: cycles to wait to return noral xtal 32k + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: XTAL32K_RESTART_WAIT + description: cycles to wait to repower on xtal 32k + bitOffset: 4 + bitWidth: 16 + access: read-write + - name: XTAL32K_WDT_TIMEOUT + description: If no clock detected for this amount of time + bitOffset: 20 + bitWidth: 8 + access: read-write + - name: XTAL32K_STABLE_THRES + description: if restarted xtal32k period is smaller than this + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: USB_CONF + description: rtc configure register + addressOffset: 236 + size: 32 + fields: + - name: IO_MUX_RESET_DISABLE + description: disable io_mux reset + bitOffset: 18 + bitWidth: 1 + access: read-write + - register: + name: SLP_REJECT_CAUSE + description: RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG + addressOffset: 240 + size: 32 + fields: + - name: REJECT_CAUSE + description: sleep reject cause + bitOffset: 0 + bitWidth: 18 + access: read-only + - register: + name: OPTION1 + description: rtc configure register + addressOffset: 244 + size: 32 + fields: + - name: FORCE_DOWNLOAD_BOOT + description: force chip entry download mode + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SLP_WAKEUP_CAUSE + description: RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG + addressOffset: 248 + size: 32 + fields: + - name: WAKEUP_CAUSE + description: sleep wakeup cause + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: ULP_CP_TIMER_1 + description: rtc configure register + addressOffset: 252 + size: 32 + resetValue: 51200 + fields: + - name: ULP_CP_TIMER_SLP_CYCLE + description: sleep cycles for ULP-coprocessor timer + bitOffset: 8 + bitWidth: 24 + access: read-write + - register: + name: INT_ENA_RTC_W1TS + description: rtc configure register + addressOffset: 256 + size: 32 + fields: + - name: SLP_WAKEUP_INT_ENA_W1TS + description: enable sleep wakeup interrupt + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SLP_REJECT_INT_ENA_W1TS + description: enable sleep reject interrupt + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: WDT_INT_ENA_W1TS + description: enable RTC WDT interrupt + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: BROWN_OUT_INT_ENA_W1TS + description: enable brown out interrupt + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: MAIN_TIMER_INT_ENA_W1TS + description: enable RTC main timer interrupt + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SWD_INT_ENA_W1TS + description: enable super watch dog interrupt + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: XTAL32K_DEAD_INT_ENA_W1TS + description: enable xtal32k_dead interrupt + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: GLITCH_DET_INT_ENA_W1TS + description: enbale gitch det interrupt + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: BBPLL_CAL_INT_ENA_W1TS + description: enbale bbpll cal interrupt + bitOffset: 20 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA_RTC_W1TC + description: rtc configure register + addressOffset: 260 + size: 32 + fields: + - name: SLP_WAKEUP_INT_ENA_W1TC + description: clear sleep wakeup interrupt enable + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SLP_REJECT_INT_ENA_W1TC + description: clear sleep reject interrupt enable + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: WDT_INT_ENA_W1TC + description: clear RTC WDT interrupt enable + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: BROWN_OUT_INT_ENA_W1TC + description: clear brown out interrupt enable + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: MAIN_TIMER_INT_ENA_W1TC + description: Clear RTC main timer interrupt enable + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SWD_INT_ENA_W1TC + description: clear super watch dog interrupt enable + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: XTAL32K_DEAD_INT_ENA_W1TC + description: clear xtal32k_dead interrupt enable + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: GLITCH_DET_INT_ENA_W1TC + description: clear gitch det interrupt enable + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: BBPLL_CAL_INT_ENA_W1TC + description: clear bbpll cal interrupt enable + bitOffset: 20 + bitWidth: 1 + access: write-only + - register: + name: RETENTION_CTRL + description: rtc configure register + addressOffset: 264 + size: 32 + resetValue: 2697986048 + fields: + - name: RETENTION_CLK_SEL + description: Retention clk sel + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RETENTION_DONE_WAIT + description: Retention done wait time + bitOffset: 19 + bitWidth: 3 + access: read-write + - name: RETENTION_CLKOFF_WAIT + description: Retention clkoff wait time + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: RETENTION_EN + description: enable cpu retention when light sleep + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RETENTION_WAIT + description: wait cycles for rention operation + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: FIB_SEL + description: rtc configure register + addressOffset: 268 + size: 32 + resetValue: 7 + fields: + - name: FIB_SEL + description: select use analog fib signal + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: GPIO_WAKEUP + description: rtc configure register + addressOffset: 272 + size: 32 + fields: + - name: GPIO_WAKEUP_STATUS + description: rtc gpio wakeup flag + bitOffset: 0 + bitWidth: 6 + access: read-only + - name: GPIO_WAKEUP_STATUS_CLR + description: clear rtc gpio wakeup flag + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: GPIO_PIN_CLK_GATE + description: enable rtc io clk gate + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: GPIO_PIN5_INT_TYPE + description: configure gpio wakeup type + bitOffset: 8 + bitWidth: 3 + access: read-write + - name: GPIO_PIN4_INT_TYPE + description: configure gpio wakeup type + bitOffset: 11 + bitWidth: 3 + access: read-write + - name: GPIO_PIN3_INT_TYPE + description: configure gpio wakeup type + bitOffset: 14 + bitWidth: 3 + access: read-write + - name: GPIO_PIN2_INT_TYPE + description: configure gpio wakeup type + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: GPIO_PIN1_INT_TYPE + description: configure gpio wakeup type + bitOffset: 20 + bitWidth: 3 + access: read-write + - name: GPIO_PIN0_INT_TYPE + description: configure gpio wakeup type + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: GPIO_PIN5_WAKEUP_ENABLE + description: enable wakeup from rtc gpio5 + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: GPIO_PIN4_WAKEUP_ENABLE + description: enable wakeup from rtc gpio4 + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: GPIO_PIN3_WAKEUP_ENABLE + description: enable wakeup from rtc gpio3 + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: GPIO_PIN2_WAKEUP_ENABLE + description: enable wakeup from rtc gpio2 + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: GPIO_PIN1_WAKEUP_ENABLE + description: enable wakeup from rtc gpio1 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: GPIO_PIN0_WAKEUP_ENABLE + description: enable wakeup from rtc gpio0 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DBG_SEL + description: rtc configure register + addressOffset: 276 + size: 32 + fields: + - name: DEBUG_12M_NO_GATING + description: use for debug + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DEBUG_BIT_SEL + description: use for debug + bitOffset: 2 + bitWidth: 5 + access: read-write + - name: DEBUG_SEL0 + description: use for debug + bitOffset: 7 + bitWidth: 5 + access: read-write + - name: DEBUG_SEL1 + description: use for debug + bitOffset: 12 + bitWidth: 5 + access: read-write + - name: DEBUG_SEL2 + description: use for debug + bitOffset: 17 + bitWidth: 5 + access: read-write + - name: DEBUG_SEL3 + description: use for debug + bitOffset: 22 + bitWidth: 5 + access: read-write + - name: DEBUG_SEL4 + description: use for debug + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: DBG_MAP + description: rtc configure register + addressOffset: 280 + size: 32 + fields: + - name: GPIO_PIN5_MUX_SEL + description: use for debug + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: GPIO_PIN4_MUX_SEL + description: use for debug + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: GPIO_PIN3_MUX_SEL + description: use for debug + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: GPIO_PIN2_MUX_SEL + description: use for debug + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: GPIO_PIN1_MUX_SEL + description: use for debug + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: GPIO_PIN0_MUX_SEL + description: use for debug + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: GPIO_PIN5_FUN_SEL + description: use for debug + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: GPIO_PIN4_FUN_SEL + description: use for debug + bitOffset: 12 + bitWidth: 4 + access: read-write + - name: GPIO_PIN3_FUN_SEL + description: use for debug + bitOffset: 16 + bitWidth: 4 + access: read-write + - name: GPIO_PIN2_FUN_SEL + description: use for debug + bitOffset: 20 + bitWidth: 4 + access: read-write + - name: GPIO_PIN1_FUN_SEL + description: use for debug + bitOffset: 24 + bitWidth: 4 + access: read-write + - name: GPIO_PIN0_FUN_SEL + description: use for debug + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: SENSOR_CTRL + description: rtc configure register + addressOffset: 284 + size: 32 + fields: + - name: SAR2_PWDET_CCT + description: reg_sar2_pwdet_cct + bitOffset: 27 + bitWidth: 3 + access: read-write + - name: FORCE_XPD_SAR + description: force power up SAR + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: DBG_SAR_SEL + description: rtc configure register + addressOffset: 288 + size: 32 + fields: + - name: SAR_DEBUG_SEL + description: use for debug + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: PG_CTRL + description: rtc configure register + addressOffset: 292 + size: 32 + fields: + - name: POWER_GLITCH_DSENSE + description: power glitch desense + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: POWER_GLITCH_FORCE_PD + description: force disable power glitch + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: POWER_GLITCH_FORCE_PU + description: force enable power glitch + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: POWER_GLITCH_EFUSE_SEL + description: use efuse value control power glitch enable + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: POWER_GLITCH_EN + description: enable power glitch + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: rtc configure register + addressOffset: 508 + size: 32 + resetValue: 33583728 + fields: + - name: DATE + description: verision + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SENSITIVE + description: SENSITIVE Peripheral + groupName: SENSITIVE + baseAddress: 1611403264 + addressBlock: + - offset: 0 + size: 376 + usage: registers + registers: + - register: + name: ROM_TABLE_LOCK + description: SENSITIVE_ROM_TABLE_LOCK_REG + addressOffset: 0 + size: 32 + fields: + - name: ROM_TABLE_LOCK + description: rom_table_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: ROM_TABLE + description: SENSITIVE_ROM_TABLE_REG + addressOffset: 4 + size: 32 + fields: + - name: ROM_TABLE + description: rom_table + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PRIVILEGE_MODE_SEL_LOCK + description: SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG + addressOffset: 8 + size: 32 + fields: + - name: PRIVILEGE_MODE_SEL_LOCK + description: privilege_mode_sel_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: PRIVILEGE_MODE_SEL + description: SENSITIVE_PRIVILEGE_MODE_SEL_REG + addressOffset: 12 + size: 32 + fields: + - name: PRIVILEGE_MODE_SEL + description: privilege_mode_sel + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: APB_PERIPHERAL_ACCESS_0 + description: SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG + addressOffset: 16 + size: 32 + fields: + - name: APB_PERIPHERAL_ACCESS_LOCK + description: apb_peripheral_access_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: APB_PERIPHERAL_ACCESS_1 + description: SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG + addressOffset: 20 + size: 32 + resetValue: 1 + fields: + - name: APB_PERIPHERAL_ACCESS_SPLIT_BURST + description: apb_peripheral_access_split_burst + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: INTERNAL_SRAM_USAGE_0 + description: SENSITIVE_INTERNAL_SRAM_USAGE_0_REG + addressOffset: 24 + size: 32 + fields: + - name: INTERNAL_SRAM_USAGE_LOCK + description: internal_sram_usage_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: INTERNAL_SRAM_USAGE_1 + description: SENSITIVE_INTERNAL_SRAM_USAGE_1_REG + addressOffset: 28 + size: 32 + resetValue: 15 + fields: + - name: INTERNAL_SRAM_USAGE_CPU_CACHE + description: internal_sram_usage_cpu_cache + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: INTERNAL_SRAM_USAGE_CPU_SRAM + description: internal_sram_usage_cpu_sram + bitOffset: 1 + bitWidth: 3 + access: read-write + - register: + name: INTERNAL_SRAM_USAGE_3 + description: SENSITIVE_INTERNAL_SRAM_USAGE_3_REG + addressOffset: 32 + size: 32 + fields: + - name: INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM + description: internal_sram_usage_mac_dump_sram + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: INTERNAL_SRAM_ALLOC_MAC_DUMP + description: internal_sram_alloc_mac_dump + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: INTERNAL_SRAM_USAGE_4 + description: SENSITIVE_INTERNAL_SRAM_USAGE_4_REG + addressOffset: 36 + size: 32 + fields: + - name: INTERNAL_SRAM_USAGE_LOG_SRAM + description: internal_sram_usage_log_sram + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CACHE_TAG_ACCESS_0 + description: SENSITIVE_CACHE_TAG_ACCESS_0_REG + addressOffset: 40 + size: 32 + fields: + - name: CACHE_TAG_ACCESS_LOCK + description: cache_tag_access_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CACHE_TAG_ACCESS_1 + description: SENSITIVE_CACHE_TAG_ACCESS_1_REG + addressOffset: 44 + size: 32 + resetValue: 15 + fields: + - name: PRO_I_TAG_RD_ACS + description: pro_i_tag_rd_acs + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_I_TAG_WR_ACS + description: pro_i_tag_wr_acs + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PRO_D_TAG_RD_ACS + description: pro_d_tag_rd_acs + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PRO_D_TAG_WR_ACS + description: pro_d_tag_wr_acs + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: CACHE_MMU_ACCESS_0 + description: SENSITIVE_CACHE_MMU_ACCESS_0_REG + addressOffset: 48 + size: 32 + fields: + - name: CACHE_MMU_ACCESS_LOCK + description: cache_mmu_access_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CACHE_MMU_ACCESS_1 + description: SENSITIVE_CACHE_MMU_ACCESS_1_REG + addressOffset: 52 + size: 32 + resetValue: 3 + fields: + - name: PRO_MMU_RD_ACS + description: pro_mmu_rd_acs + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_MMU_WR_ACS + description: pro_mmu_wr_acs + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_SPI2_PMS_CONSTRAIN_0 + description: SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG + addressOffset: 56 + size: 32 + fields: + - name: DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK + description: dma_apbperi_spi2_pms_constrain_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_SPI2_PMS_CONSTRAIN_1 + description: SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG + addressOffset: 60 + size: 32 + resetValue: 1044735 + fields: + - name: DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + description: dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + description: dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1 + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + description: dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2 + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + description: dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3 + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + description: dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0 + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + description: dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1 + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + description: dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2 + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + description: dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3 + bitOffset: 18 + bitWidth: 2 + access: read-write + - register: + name: DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0 + description: SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG + addressOffset: 64 + size: 32 + fields: + - name: DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK + description: dma_apbperi_uchi0_pms_constrain_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1 + description: SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG + addressOffset: 68 + size: 32 + resetValue: 1044735 + fields: + - name: DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + description: dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + description: dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1 + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + description: dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2 + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + description: dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3 + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + description: dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0 + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + description: dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1 + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + description: dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2 + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + description: dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3 + bitOffset: 18 + bitWidth: 2 + access: read-write + - register: + name: DMA_APBPERI_I2S0_PMS_CONSTRAIN_0 + description: SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG + addressOffset: 72 + size: 32 + fields: + - name: DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK + description: dma_apbperi_i2s0_pms_constrain_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_I2S0_PMS_CONSTRAIN_1 + description: SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG + addressOffset: 76 + size: 32 + resetValue: 1044735 + fields: + - name: DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + description: dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + description: dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1 + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + description: dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2 + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + description: dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3 + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + description: dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0 + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + description: dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1 + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + description: dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2 + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + description: dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3 + bitOffset: 18 + bitWidth: 2 + access: read-write + - register: + name: DMA_APBPERI_MAC_PMS_CONSTRAIN_0 + description: SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG + addressOffset: 80 + size: 32 + fields: + - name: DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK + description: dma_apbperi_mac_pms_constrain_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_MAC_PMS_CONSTRAIN_1 + description: SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG + addressOffset: 84 + size: 32 + resetValue: 1044735 + fields: + - name: DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + description: dma_apbperi_mac_pms_constrain_sram_world_0_pms_0 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + description: dma_apbperi_mac_pms_constrain_sram_world_0_pms_1 + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + description: dma_apbperi_mac_pms_constrain_sram_world_0_pms_2 + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + description: dma_apbperi_mac_pms_constrain_sram_world_0_pms_3 + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + description: dma_apbperi_mac_pms_constrain_sram_world_1_pms_0 + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + description: dma_apbperi_mac_pms_constrain_sram_world_1_pms_1 + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + description: dma_apbperi_mac_pms_constrain_sram_world_1_pms_2 + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + description: dma_apbperi_mac_pms_constrain_sram_world_1_pms_3 + bitOffset: 18 + bitWidth: 2 + access: read-write + - register: + name: DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0 + description: SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG + addressOffset: 88 + size: 32 + fields: + - name: DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK + description: dma_apbperi_backup_pms_constrain_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1 + description: SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG + addressOffset: 92 + size: 32 + resetValue: 1044735 + fields: + - name: DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + description: dma_apbperi_backup_pms_constrain_sram_world_0_pms_0 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + description: dma_apbperi_backup_pms_constrain_sram_world_0_pms_1 + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + description: dma_apbperi_backup_pms_constrain_sram_world_0_pms_2 + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + description: dma_apbperi_backup_pms_constrain_sram_world_0_pms_3 + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + description: dma_apbperi_backup_pms_constrain_sram_world_1_pms_0 + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + description: dma_apbperi_backup_pms_constrain_sram_world_1_pms_1 + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + description: dma_apbperi_backup_pms_constrain_sram_world_1_pms_2 + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + description: dma_apbperi_backup_pms_constrain_sram_world_1_pms_3 + bitOffset: 18 + bitWidth: 2 + access: read-write + - register: + name: DMA_APBPERI_LC_PMS_CONSTRAIN_0 + description: SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG + addressOffset: 96 + size: 32 + fields: + - name: DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK + description: dma_apbperi_lc_pms_constrain_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_LC_PMS_CONSTRAIN_1 + description: SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG + addressOffset: 100 + size: 32 + resetValue: 1044735 + fields: + - name: DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + description: dma_apbperi_lc_pms_constrain_sram_world_0_pms_0 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + description: dma_apbperi_lc_pms_constrain_sram_world_0_pms_1 + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + description: dma_apbperi_lc_pms_constrain_sram_world_0_pms_2 + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + description: dma_apbperi_lc_pms_constrain_sram_world_0_pms_3 + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + description: dma_apbperi_lc_pms_constrain_sram_world_1_pms_0 + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + description: dma_apbperi_lc_pms_constrain_sram_world_1_pms_1 + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + description: dma_apbperi_lc_pms_constrain_sram_world_1_pms_2 + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + description: dma_apbperi_lc_pms_constrain_sram_world_1_pms_3 + bitOffset: 18 + bitWidth: 2 + access: read-write + - register: + name: DMA_APBPERI_AES_PMS_CONSTRAIN_0 + description: SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG + addressOffset: 104 + size: 32 + fields: + - name: DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK + description: dma_apbperi_aes_pms_constrain_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_AES_PMS_CONSTRAIN_1 + description: SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG + addressOffset: 108 + size: 32 + resetValue: 1044735 + fields: + - name: DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + description: dma_apbperi_aes_pms_constrain_sram_world_0_pms_0 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + description: dma_apbperi_aes_pms_constrain_sram_world_0_pms_1 + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + description: dma_apbperi_aes_pms_constrain_sram_world_0_pms_2 + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + description: dma_apbperi_aes_pms_constrain_sram_world_0_pms_3 + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + description: dma_apbperi_aes_pms_constrain_sram_world_1_pms_0 + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + description: dma_apbperi_aes_pms_constrain_sram_world_1_pms_1 + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + description: dma_apbperi_aes_pms_constrain_sram_world_1_pms_2 + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + description: dma_apbperi_aes_pms_constrain_sram_world_1_pms_3 + bitOffset: 18 + bitWidth: 2 + access: read-write + - register: + name: DMA_APBPERI_SHA_PMS_CONSTRAIN_0 + description: SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG + addressOffset: 112 + size: 32 + fields: + - name: DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK + description: dma_apbperi_sha_pms_constrain_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_SHA_PMS_CONSTRAIN_1 + description: SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG + addressOffset: 116 + size: 32 + resetValue: 1044735 + fields: + - name: DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + description: dma_apbperi_sha_pms_constrain_sram_world_0_pms_0 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + description: dma_apbperi_sha_pms_constrain_sram_world_0_pms_1 + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + description: dma_apbperi_sha_pms_constrain_sram_world_0_pms_2 + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + description: dma_apbperi_sha_pms_constrain_sram_world_0_pms_3 + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + description: dma_apbperi_sha_pms_constrain_sram_world_1_pms_0 + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + description: dma_apbperi_sha_pms_constrain_sram_world_1_pms_1 + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + description: dma_apbperi_sha_pms_constrain_sram_world_1_pms_2 + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + description: dma_apbperi_sha_pms_constrain_sram_world_1_pms_3 + bitOffset: 18 + bitWidth: 2 + access: read-write + - register: + name: DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0 + description: SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG + addressOffset: 120 + size: 32 + fields: + - name: DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK + description: dma_apbperi_adc_dac_pms_constrain_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1 + description: SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG + addressOffset: 124 + size: 32 + resetValue: 1044735 + fields: + - name: DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + description: dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + description: dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1 + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + description: dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2 + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + description: dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3 + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + description: dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0 + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + description: dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1 + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + description: dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2 + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + description: dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3 + bitOffset: 18 + bitWidth: 2 + access: read-write + - register: + name: DMA_APBPERI_PMS_MONITOR_0 + description: SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG + addressOffset: 128 + size: 32 + fields: + - name: DMA_APBPERI_PMS_MONITOR_LOCK + description: dma_apbperi_pms_monitor_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_PMS_MONITOR_1 + description: SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG + addressOffset: 132 + size: 32 + resetValue: 3 + fields: + - name: DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR + description: dma_apbperi_pms_monitor_violate_clr + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DMA_APBPERI_PMS_MONITOR_VIOLATE_EN + description: dma_apbperi_pms_monitor_violate_en + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_PMS_MONITOR_2 + description: SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG + addressOffset: 136 + size: 32 + fields: + - name: DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR + description: dma_apbperi_pms_monitor_violate_intr + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD + description: dma_apbperi_pms_monitor_violate_status_world + bitOffset: 1 + bitWidth: 2 + access: read-only + - name: DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR + description: dma_apbperi_pms_monitor_violate_status_addr + bitOffset: 3 + bitWidth: 24 + access: read-only + - register: + name: DMA_APBPERI_PMS_MONITOR_3 + description: SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG + addressOffset: 140 + size: 32 + fields: + - name: DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR + description: dma_apbperi_pms_monitor_violate_status_wr + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN + description: dma_apbperi_pms_monitor_violate_status_byteen + bitOffset: 1 + bitWidth: 4 + access: read-only + - register: + name: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0 + description: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG + addressOffset: 144 + size: 32 + fields: + - name: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK + description: core_x_iram0_dram0_dma_split_line_constrain_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1 + description: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG + addressOffset: 148 + size: 32 + fields: + - name: CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 + description: core_x_iram0_dram0_dma_sram_category_0 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 + description: core_x_iram0_dram0_dma_sram_category_1 + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 + description: core_x_iram0_dram0_dma_sram_category_2 + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR + description: core_x_iram0_dram0_dma_sram_splitaddr + bitOffset: 14 + bitWidth: 8 + access: read-write + - register: + name: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2 + description: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG + addressOffset: 152 + size: 32 + fields: + - name: CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 + description: core_x_iram0_sram_line_0_category_0 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 + description: core_x_iram0_sram_line_0_category_1 + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 + description: core_x_iram0_sram_line_0_category_2 + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR + description: core_x_iram0_sram_line_0_splitaddr + bitOffset: 14 + bitWidth: 8 + access: read-write + - register: + name: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3 + description: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG + addressOffset: 156 + size: 32 + fields: + - name: CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 + description: core_x_iram0_sram_line_1_category_0 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 + description: core_x_iram0_sram_line_1_category_1 + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 + description: core_x_iram0_sram_line_1_category_2 + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR + description: core_x_iram0_sram_line_1_splitaddr + bitOffset: 14 + bitWidth: 8 + access: read-write + - register: + name: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4 + description: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG + addressOffset: 160 + size: 32 + fields: + - name: CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 + description: core_x_dram0_dma_sram_line_0_category_0 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 + description: core_x_dram0_dma_sram_line_0_category_1 + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 + description: core_x_dram0_dma_sram_line_0_category_2 + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR + description: core_x_dram0_dma_sram_line_0_splitaddr + bitOffset: 14 + bitWidth: 8 + access: read-write + - register: + name: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5 + description: SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG + addressOffset: 164 + size: 32 + fields: + - name: CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 + description: core_x_dram0_dma_sram_line_1_category_0 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 + description: core_x_dram0_dma_sram_line_1_category_1 + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 + description: core_x_dram0_dma_sram_line_1_category_2 + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR + description: core_x_dram0_dma_sram_line_1_splitaddr + bitOffset: 14 + bitWidth: 8 + access: read-write + - register: + name: CORE_X_IRAM0_PMS_CONSTRAIN_0 + description: SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG + addressOffset: 168 + size: 32 + fields: + - name: CORE_X_IRAM0_PMS_CONSTRAIN_LOCK + description: core_x_iram0_pms_constrain_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_X_IRAM0_PMS_CONSTRAIN_1 + description: SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG + addressOffset: 172 + size: 32 + resetValue: 1867775 + fields: + - name: CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + description: core_x_iram0_pms_constrain_sram_world_1_pms_0 + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + description: core_x_iram0_pms_constrain_sram_world_1_pms_1 + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + description: core_x_iram0_pms_constrain_sram_world_1_pms_2 + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + description: core_x_iram0_pms_constrain_sram_world_1_pms_3 + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 + description: core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0 + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS + description: core_x_iram0_pms_constrain_rom_world_1_pms + bitOffset: 18 + bitWidth: 3 + access: read-write + - register: + name: CORE_X_IRAM0_PMS_CONSTRAIN_2 + description: SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG + addressOffset: 176 + size: 32 + resetValue: 1867775 + fields: + - name: CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + description: core_x_iram0_pms_constrain_sram_world_0_pms_0 + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + description: core_x_iram0_pms_constrain_sram_world_0_pms_1 + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + description: core_x_iram0_pms_constrain_sram_world_0_pms_2 + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + description: core_x_iram0_pms_constrain_sram_world_0_pms_3 + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 + description: core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0 + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS + description: core_x_iram0_pms_constrain_rom_world_0_pms + bitOffset: 18 + bitWidth: 3 + access: read-write + - register: + name: CORE_0_IRAM0_PMS_MONITOR_0 + description: SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG + addressOffset: 180 + size: 32 + fields: + - name: CORE_0_IRAM0_PMS_MONITOR_LOCK + description: core_0_iram0_pms_monitor_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_IRAM0_PMS_MONITOR_1 + description: SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG + addressOffset: 184 + size: 32 + resetValue: 3 + fields: + - name: CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR + description: core_0_iram0_pms_monitor_violate_clr + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN + description: core_0_iram0_pms_monitor_violate_en + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_IRAM0_PMS_MONITOR_2 + description: SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG + addressOffset: 188 + size: 32 + fields: + - name: CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR + description: core_0_iram0_pms_monitor_violate_intr + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR + description: core_0_iram0_pms_monitor_violate_status_wr + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE + description: core_0_iram0_pms_monitor_violate_status_loadstore + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD + description: core_0_iram0_pms_monitor_violate_status_world + bitOffset: 3 + bitWidth: 2 + access: read-only + - name: CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR + description: core_0_iram0_pms_monitor_violate_status_addr + bitOffset: 5 + bitWidth: 24 + access: read-only + - register: + name: CORE_X_DRAM0_PMS_CONSTRAIN_0 + description: SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG + addressOffset: 192 + size: 32 + fields: + - name: CORE_X_DRAM0_PMS_CONSTRAIN_LOCK + description: core_x_dram0_pms_constrain_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_X_DRAM0_PMS_CONSTRAIN_1 + description: SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG + addressOffset: 196 + size: 32 + resetValue: 252702975 + fields: + - name: CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + description: core_x_dram0_pms_constrain_sram_world_0_pms_0 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + description: core_x_dram0_pms_constrain_sram_world_0_pms_1 + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + description: core_x_dram0_pms_constrain_sram_world_0_pms_2 + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + description: core_x_dram0_pms_constrain_sram_world_0_pms_3 + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + description: core_x_dram0_pms_constrain_sram_world_1_pms_0 + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + description: core_x_dram0_pms_constrain_sram_world_1_pms_1 + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + description: core_x_dram0_pms_constrain_sram_world_1_pms_2 + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + description: core_x_dram0_pms_constrain_sram_world_1_pms_3 + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS + description: core_x_dram0_pms_constrain_rom_world_0_pms + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS + description: core_x_dram0_pms_constrain_rom_world_1_pms + bitOffset: 26 + bitWidth: 2 + access: read-write + - register: + name: CORE_0_DRAM0_PMS_MONITOR_0 + description: SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG + addressOffset: 200 + size: 32 + fields: + - name: CORE_0_DRAM0_PMS_MONITOR_LOCK + description: core_0_dram0_pms_monitor_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_DRAM0_PMS_MONITOR_1 + description: SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG + addressOffset: 204 + size: 32 + resetValue: 3 + fields: + - name: CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR + description: core_0_dram0_pms_monitor_violate_clr + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN + description: core_0_dram0_pms_monitor_violate_en + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_DRAM0_PMS_MONITOR_2 + description: SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG + addressOffset: 208 + size: 32 + fields: + - name: CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR + description: core_0_dram0_pms_monitor_violate_intr + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK + description: core_0_dram0_pms_monitor_violate_status_lock + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD + description: core_0_dram0_pms_monitor_violate_status_world + bitOffset: 2 + bitWidth: 2 + access: read-only + - name: CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR + description: core_0_dram0_pms_monitor_violate_status_addr + bitOffset: 4 + bitWidth: 24 + access: read-only + - register: + name: CORE_0_DRAM0_PMS_MONITOR_3 + description: SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG + addressOffset: 212 + size: 32 + fields: + - name: CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR + description: core_0_dram0_pms_monitor_violate_status_wr + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN + description: core_0_dram0_pms_monitor_violate_status_byteen + bitOffset: 1 + bitWidth: 4 + access: read-only + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_0 + description: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG + addressOffset: 216 + size: 32 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_LOCK + description: core_0_pif_pms_constrain_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_1 + description: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG + addressOffset: 220 + size: 32 + resetValue: 3473932287 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART + description: core_0_pif_pms_constrain_world_0_uart + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 + description: core_0_pif_pms_constrain_world_0_g0spi_1 + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 + description: core_0_pif_pms_constrain_world_0_g0spi_0 + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO + description: core_0_pif_pms_constrain_world_0_gpio + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 + description: core_0_pif_pms_constrain_world_0_fe2 + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE + description: core_0_pif_pms_constrain_world_0_fe + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER + description: core_0_pif_pms_constrain_world_0_timer + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC + description: core_0_pif_pms_constrain_world_0_rtc + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX + description: core_0_pif_pms_constrain_world_0_io_mux + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG + description: core_0_pif_pms_constrain_world_0_wdg + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC + description: core_0_pif_pms_constrain_world_0_misc + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C + description: core_0_pif_pms_constrain_world_0_i2c + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 + description: core_0_pif_pms_constrain_world_0_uart1 + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_2 + description: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG + addressOffset: 224 + size: 32 + resetValue: 4240641267 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT + description: core_0_pif_pms_constrain_world_0_bt + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 + description: core_0_pif_pms_constrain_world_0_i2c_ext0 + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 + description: core_0_pif_pms_constrain_world_0_uhci0 + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT + description: core_0_pif_pms_constrain_world_0_rmt + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC + description: core_0_pif_pms_constrain_world_0_ledc + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB + description: core_0_pif_pms_constrain_world_0_bb + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP + description: core_0_pif_pms_constrain_world_0_timergroup + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 + description: core_0_pif_pms_constrain_world_0_timergroup1 + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER + description: core_0_pif_pms_constrain_world_0_systimer + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_3 + description: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG + addressOffset: 228 + size: 32 + resetValue: 1019268147 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 + description: core_0_pif_pms_constrain_world_0_spi_2 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL + description: core_0_pif_pms_constrain_world_0_apb_ctrl + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN + description: core_0_pif_pms_constrain_world_0_can + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 + description: core_0_pif_pms_constrain_world_0_i2s1 + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT + description: core_0_pif_pms_constrain_world_0_rwbt + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC + description: core_0_pif_pms_constrain_world_0_wifimac + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR + description: core_0_pif_pms_constrain_world_0_pwr + bitOffset: 28 + bitWidth: 2 + access: read-write + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_4 + description: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG + addressOffset: 232 + size: 32 + resetValue: 4294964220 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP + description: core_0_pif_pms_constrain_world_0_usb_wrap + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI + description: core_0_pif_pms_constrain_world_0_crypto_peri + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA + description: core_0_pif_pms_constrain_world_0_crypto_dma + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC + description: core_0_pif_pms_constrain_world_0_apb_adc + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR + description: core_0_pif_pms_constrain_world_0_bt_pwr + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE + description: core_0_pif_pms_constrain_world_0_usb_device + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM + description: core_0_pif_pms_constrain_world_0_system + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE + description: core_0_pif_pms_constrain_world_0_sensitive + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT + description: core_0_pif_pms_constrain_world_0_interrupt + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY + description: core_0_pif_pms_constrain_world_0_dma_copy + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG + description: core_0_pif_pms_constrain_world_0_cache_config + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD + description: core_0_pif_pms_constrain_world_0_ad + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO + description: core_0_pif_pms_constrain_world_0_dio + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER + description: core_0_pif_pms_constrain_world_0_world_controller + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_5 + description: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG + addressOffset: 236 + size: 32 + resetValue: 3473932287 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART + description: core_0_pif_pms_constrain_world_1_uart + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 + description: core_0_pif_pms_constrain_world_1_g0spi_1 + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 + description: core_0_pif_pms_constrain_world_1_g0spi_0 + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO + description: core_0_pif_pms_constrain_world_1_gpio + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 + description: core_0_pif_pms_constrain_world_1_fe2 + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE + description: core_0_pif_pms_constrain_world_1_fe + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER + description: core_0_pif_pms_constrain_world_1_timer + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC + description: core_0_pif_pms_constrain_world_1_rtc + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX + description: core_0_pif_pms_constrain_world_1_io_mux + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG + description: core_0_pif_pms_constrain_world_1_wdg + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC + description: core_0_pif_pms_constrain_world_1_misc + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C + description: core_0_pif_pms_constrain_world_1_i2c + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 + description: core_0_pif_pms_constrain_world_1_uart1 + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_6 + description: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG + addressOffset: 240 + size: 32 + resetValue: 4240641267 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT + description: core_0_pif_pms_constrain_world_1_bt + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 + description: core_0_pif_pms_constrain_world_1_i2c_ext0 + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 + description: core_0_pif_pms_constrain_world_1_uhci0 + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT + description: core_0_pif_pms_constrain_world_1_rmt + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC + description: core_0_pif_pms_constrain_world_1_ledc + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB + description: core_0_pif_pms_constrain_world_1_bb + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP + description: core_0_pif_pms_constrain_world_1_timergroup + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 + description: core_0_pif_pms_constrain_world_1_timergroup1 + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER + description: core_0_pif_pms_constrain_world_1_systimer + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_7 + description: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG + addressOffset: 244 + size: 32 + resetValue: 1019268147 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 + description: core_0_pif_pms_constrain_world_1_spi_2 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL + description: core_0_pif_pms_constrain_world_1_apb_ctrl + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN + description: core_0_pif_pms_constrain_world_1_can + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 + description: core_0_pif_pms_constrain_world_1_i2s1 + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT + description: core_0_pif_pms_constrain_world_1_rwbt + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC + description: core_0_pif_pms_constrain_world_1_wifimac + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR + description: core_0_pif_pms_constrain_world_1_pwr + bitOffset: 28 + bitWidth: 2 + access: read-write + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_8 + description: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG + addressOffset: 248 + size: 32 + resetValue: 4294964220 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP + description: core_0_pif_pms_constrain_world_1_usb_wrap + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI + description: core_0_pif_pms_constrain_world_1_crypto_peri + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA + description: core_0_pif_pms_constrain_world_1_crypto_dma + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC + description: core_0_pif_pms_constrain_world_1_apb_adc + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR + description: core_0_pif_pms_constrain_world_1_bt_pwr + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE + description: core_0_pif_pms_constrain_world_1_usb_device + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM + description: core_0_pif_pms_constrain_world_1_system + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE + description: core_0_pif_pms_constrain_world_1_sensitive + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT + description: core_0_pif_pms_constrain_world_1_interrupt + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY + description: core_0_pif_pms_constrain_world_1_dma_copy + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG + description: core_0_pif_pms_constrain_world_1_cache_config + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD + description: core_0_pif_pms_constrain_world_1_ad + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO + description: core_0_pif_pms_constrain_world_1_dio + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER + description: core_0_pif_pms_constrain_world_1_world_controller + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_9 + description: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG + addressOffset: 252 + size: 32 + resetValue: 4194303 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 + description: core_0_pif_pms_constrain_rtcfast_spltaddr_world_0 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 + description: core_0_pif_pms_constrain_rtcfast_spltaddr_world_1 + bitOffset: 11 + bitWidth: 11 + access: read-write + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_10 + description: SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG + addressOffset: 256 + size: 32 + resetValue: 4095 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L + description: core_0_pif_pms_constrain_rtcfast_world_0_l + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H + description: core_0_pif_pms_constrain_rtcfast_world_0_h + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L + description: core_0_pif_pms_constrain_rtcfast_world_1_l + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H + description: core_0_pif_pms_constrain_rtcfast_world_1_h + bitOffset: 9 + bitWidth: 3 + access: read-write + - register: + name: REGION_PMS_CONSTRAIN_0 + description: SENSITIVE_REGION_PMS_CONSTRAIN_0_REG + addressOffset: 260 + size: 32 + fields: + - name: REGION_PMS_CONSTRAIN_LOCK + description: region_pms_constrain_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: REGION_PMS_CONSTRAIN_1 + description: SENSITIVE_REGION_PMS_CONSTRAIN_1_REG + addressOffset: 264 + size: 32 + resetValue: 16383 + fields: + - name: REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 + description: region_pms_constrain_world_0_area_0 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 + description: region_pms_constrain_world_0_area_1 + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 + description: region_pms_constrain_world_0_area_2 + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 + description: region_pms_constrain_world_0_area_3 + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 + description: region_pms_constrain_world_0_area_4 + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 + description: region_pms_constrain_world_0_area_5 + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 + description: region_pms_constrain_world_0_area_6 + bitOffset: 12 + bitWidth: 2 + access: read-write + - register: + name: REGION_PMS_CONSTRAIN_2 + description: SENSITIVE_REGION_PMS_CONSTRAIN_2_REG + addressOffset: 268 + size: 32 + resetValue: 16383 + fields: + - name: REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 + description: region_pms_constrain_world_1_area_0 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 + description: region_pms_constrain_world_1_area_1 + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 + description: region_pms_constrain_world_1_area_2 + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 + description: region_pms_constrain_world_1_area_3 + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 + description: region_pms_constrain_world_1_area_4 + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 + description: region_pms_constrain_world_1_area_5 + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 + description: region_pms_constrain_world_1_area_6 + bitOffset: 12 + bitWidth: 2 + access: read-write + - register: + name: REGION_PMS_CONSTRAIN_3 + description: SENSITIVE_REGION_PMS_CONSTRAIN_3_REG + addressOffset: 272 + size: 32 + fields: + - name: REGION_PMS_CONSTRAIN_ADDR_0 + description: region_pms_constrain_addr_0 + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: REGION_PMS_CONSTRAIN_4 + description: SENSITIVE_REGION_PMS_CONSTRAIN_4_REG + addressOffset: 276 + size: 32 + fields: + - name: REGION_PMS_CONSTRAIN_ADDR_1 + description: region_pms_constrain_addr_1 + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: REGION_PMS_CONSTRAIN_5 + description: SENSITIVE_REGION_PMS_CONSTRAIN_5_REG + addressOffset: 280 + size: 32 + fields: + - name: REGION_PMS_CONSTRAIN_ADDR_2 + description: region_pms_constrain_addr_2 + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: REGION_PMS_CONSTRAIN_6 + description: SENSITIVE_REGION_PMS_CONSTRAIN_6_REG + addressOffset: 284 + size: 32 + fields: + - name: REGION_PMS_CONSTRAIN_ADDR_3 + description: region_pms_constrain_addr_3 + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: REGION_PMS_CONSTRAIN_7 + description: SENSITIVE_REGION_PMS_CONSTRAIN_7_REG + addressOffset: 288 + size: 32 + fields: + - name: REGION_PMS_CONSTRAIN_ADDR_4 + description: region_pms_constrain_addr_4 + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: REGION_PMS_CONSTRAIN_8 + description: SENSITIVE_REGION_PMS_CONSTRAIN_8_REG + addressOffset: 292 + size: 32 + fields: + - name: REGION_PMS_CONSTRAIN_ADDR_5 + description: region_pms_constrain_addr_5 + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: REGION_PMS_CONSTRAIN_9 + description: SENSITIVE_REGION_PMS_CONSTRAIN_9_REG + addressOffset: 296 + size: 32 + fields: + - name: REGION_PMS_CONSTRAIN_ADDR_6 + description: region_pms_constrain_addr_6 + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: REGION_PMS_CONSTRAIN_10 + description: SENSITIVE_REGION_PMS_CONSTRAIN_10_REG + addressOffset: 300 + size: 32 + fields: + - name: REGION_PMS_CONSTRAIN_ADDR_7 + description: region_pms_constrain_addr_7 + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_0_PIF_PMS_MONITOR_0 + description: SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG + addressOffset: 304 + size: 32 + fields: + - name: CORE_0_PIF_PMS_MONITOR_LOCK + description: core_0_pif_pms_monitor_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_PIF_PMS_MONITOR_1 + description: SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG + addressOffset: 308 + size: 32 + resetValue: 3 + fields: + - name: CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR + description: core_0_pif_pms_monitor_violate_clr + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_PIF_PMS_MONITOR_VIOLATE_EN + description: core_0_pif_pms_monitor_violate_en + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_PIF_PMS_MONITOR_2 + description: SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG + addressOffset: 312 + size: 32 + fields: + - name: CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR + description: core_0_pif_pms_monitor_violate_intr + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 + description: core_0_pif_pms_monitor_violate_status_hport_0 + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE + description: core_0_pif_pms_monitor_violate_status_hsize + bitOffset: 2 + bitWidth: 3 + access: read-only + - name: CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE + description: core_0_pif_pms_monitor_violate_status_hwrite + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD + description: core_0_pif_pms_monitor_violate_status_hworld + bitOffset: 6 + bitWidth: 2 + access: read-only + - register: + name: CORE_0_PIF_PMS_MONITOR_3 + description: SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG + addressOffset: 316 + size: 32 + fields: + - name: CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR + description: core_0_pif_pms_monitor_violate_status_haddr + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_PIF_PMS_MONITOR_4 + description: SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG + addressOffset: 320 + size: 32 + resetValue: 3 + fields: + - name: CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR + description: core_0_pif_pms_monitor_nonword_violate_clr + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN + description: core_0_pif_pms_monitor_nonword_violate_en + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_PIF_PMS_MONITOR_5 + description: SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG + addressOffset: 324 + size: 32 + fields: + - name: CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR + description: core_0_pif_pms_monitor_nonword_violate_intr + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE + description: core_0_pif_pms_monitor_nonword_violate_status_hsize + bitOffset: 1 + bitWidth: 2 + access: read-only + - name: CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD + description: core_0_pif_pms_monitor_nonword_violate_status_hworld + bitOffset: 3 + bitWidth: 2 + access: read-only + - register: + name: CORE_0_PIF_PMS_MONITOR_6 + description: SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG + addressOffset: 328 + size: 32 + fields: + - name: CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR + description: core_0_pif_pms_monitor_nonword_violate_status_haddr + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BACKUP_BUS_PMS_CONSTRAIN_0 + description: SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG + addressOffset: 332 + size: 32 + fields: + - name: BACKUP_BUS_PMS_CONSTRAIN_LOCK + description: backup_bus_pms_constrain_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: BACKUP_BUS_PMS_CONSTRAIN_1 + description: SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG + addressOffset: 336 + size: 32 + resetValue: 3473932287 + fields: + - name: BACKUP_BUS_PMS_CONSTRAIN_UART + description: backup_bus_pms_constrain_uart + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 + description: backup_bus_pms_constrain_g0spi_1 + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 + description: backup_bus_pms_constrain_g0spi_0 + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_GPIO + description: backup_bus_pms_constrain_gpio + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_FE2 + description: backup_bus_pms_constrain_fe2 + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_FE + description: backup_bus_pms_constrain_fe + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_TIMER + description: backup_bus_pms_constrain_timer + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_RTC + description: backup_bus_pms_constrain_rtc + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_IO_MUX + description: backup_bus_pms_constrain_io_mux + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_WDG + description: backup_bus_pms_constrain_wdg + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_MISC + description: backup_bus_pms_constrain_misc + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_I2C + description: backup_bus_pms_constrain_i2c + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_UART1 + description: backup_bus_pms_constrain_uart1 + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: BACKUP_BUS_PMS_CONSTRAIN_2 + description: SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG + addressOffset: 340 + size: 32 + resetValue: 4240641267 + fields: + - name: BACKUP_BUS_PMS_CONSTRAIN_BT + description: backup_bus_pms_constrain_bt + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 + description: backup_bus_pms_constrain_i2c_ext0 + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_UHCI0 + description: backup_bus_pms_constrain_uhci0 + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_RMT + description: backup_bus_pms_constrain_rmt + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_LEDC + description: backup_bus_pms_constrain_ledc + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_BB + description: backup_bus_pms_constrain_bb + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP + description: backup_bus_pms_constrain_timergroup + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 + description: backup_bus_pms_constrain_timergroup1 + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER + description: backup_bus_pms_constrain_systimer + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: BACKUP_BUS_PMS_CONSTRAIN_3 + description: SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG + addressOffset: 344 + size: 32 + resetValue: 1019268147 + fields: + - name: BACKUP_BUS_PMS_CONSTRAIN_SPI_2 + description: backup_bus_pms_constrain_spi_2 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL + description: backup_bus_pms_constrain_apb_ctrl + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_CAN + description: backup_bus_pms_constrain_can + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_I2S1 + description: backup_bus_pms_constrain_i2s1 + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_RWBT + description: backup_bus_pms_constrain_rwbt + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC + description: backup_bus_pms_constrain_wifimac + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_PWR + description: backup_bus_pms_constrain_pwr + bitOffset: 28 + bitWidth: 2 + access: read-write + - register: + name: BACKUP_BUS_PMS_CONSTRAIN_4 + description: SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG + addressOffset: 348 + size: 32 + resetValue: 62460 + fields: + - name: BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP + description: backup_bus_pms_constrain_usb_wrap + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI + description: backup_bus_pms_constrain_crypto_peri + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA + description: backup_bus_pms_constrain_crypto_dma + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_APB_ADC + description: backup_bus_pms_constrain_apb_adc + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_BT_PWR + description: backup_bus_pms_constrain_bt_pwr + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE + description: backup_bus_pms_constrain_usb_device + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: BACKUP_BUS_PMS_MONITOR_0 + description: SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG + addressOffset: 352 + size: 32 + fields: + - name: BACKUP_BUS_PMS_MONITOR_LOCK + description: backup_bus_pms_monitor_lock + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: BACKUP_BUS_PMS_MONITOR_1 + description: SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG + addressOffset: 356 + size: 32 + resetValue: 3 + fields: + - name: BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR + description: backup_bus_pms_monitor_violate_clr + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: BACKUP_BUS_PMS_MONITOR_VIOLATE_EN + description: backup_bus_pms_monitor_violate_en + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: BACKUP_BUS_PMS_MONITOR_2 + description: SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG + addressOffset: 360 + size: 32 + fields: + - name: BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR + description: backup_bus_pms_monitor_violate_intr + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS + description: backup_bus_pms_monitor_violate_status_htrans + bitOffset: 1 + bitWidth: 2 + access: read-only + - name: BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE + description: backup_bus_pms_monitor_violate_status_hsize + bitOffset: 3 + bitWidth: 3 + access: read-only + - name: BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE + description: backup_bus_pms_monitor_violate_status_hwrite + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: BACKUP_BUS_PMS_MONITOR_3 + description: SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG + addressOffset: 364 + size: 32 + fields: + - name: BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR + description: backup_bus_pms_monitor_violate_haddr + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CLOCK_GATE + description: SENSITIVE_CLOCK_GATE_REG_REG + addressOffset: 368 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: clk_en + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: SENSITIVE_DATE_REG + addressOffset: 4092 + size: 32 + resetValue: 33620480 + fields: + - name: DATE + description: reg_date + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SHA + description: SHA (Secure Hash Algorithm) Accelerator + groupName: SHA + baseAddress: 1610854400 + addressBlock: + - offset: 0 + size: 176 + usage: registers + interrupt: + - name: SHA + value: 49 + registers: + - register: + name: MODE + description: Initial configuration register. + addressOffset: 0 + size: 32 + fields: + - name: MODE + description: Sha mode. + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: T_STRING + description: SHA 512/t configuration register 0. + addressOffset: 4 + size: 32 + fields: + - name: T_STRING + description: Sha t_string (used if and only if mode == SHA_512/t). + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: T_LENGTH + description: SHA 512/t configuration register 1. + addressOffset: 8 + size: 32 + fields: + - name: T_LENGTH + description: Sha t_length (used if and only if mode == SHA_512/t). + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: DMA_BLOCK_NUM + description: DMA configuration register 0. + addressOffset: 12 + size: 32 + fields: + - name: DMA_BLOCK_NUM + description: Dma-sha block number. + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: START + description: Typical SHA configuration register 0. + addressOffset: 16 + size: 32 + fields: + - name: START + description: Reserved. + bitOffset: 1 + bitWidth: 31 + access: write-only + - register: + name: CONTINUE + description: Typical SHA configuration register 1. + addressOffset: 20 + size: 32 + fields: + - name: CONTINUE + description: Reserved. + bitOffset: 1 + bitWidth: 31 + access: write-only + - register: + name: BUSY + description: Busy register. + addressOffset: 24 + size: 32 + fields: + - name: STATE + description: "Sha busy state. 1'b0: idle. 1'b1: busy." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: DMA_START + description: DMA configuration register 1. + addressOffset: 28 + size: 32 + fields: + - name: DMA_START + description: Start dma-sha. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: DMA_CONTINUE + description: DMA configuration register 2. + addressOffset: 32 + size: 32 + fields: + - name: DMA_CONTINUE + description: Continue dma-sha. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: CLEAR_IRQ + description: Interrupt clear register. + addressOffset: 36 + size: 32 + fields: + - name: CLEAR_INTERRUPT + description: Clear sha interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: IRQ_ENA + description: Interrupt enable register. + addressOffset: 40 + size: 32 + fields: + - name: INTERRUPT_ENA + description: "Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Date register. + addressOffset: 44 + size: 32 + resetValue: 538969622 + fields: + - name: DATE + description: Sha date information/ sha version information. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + name: "H_MEM[%s]" + description: Sha H memory which contains intermediate hash or finial hash. + addressOffset: 64 + size: 32 + - register: + dim: 16 + dimIncrement: 4 + name: "M_MEM[%s]" + description: Sha M memory which contains message. + addressOffset: 128 + size: 32 + - name: SPI0 + description: SPI (Serial Peripheral Interface) Controller 0 + groupName: SPI0 + baseAddress: 1610625024 + addressBlock: + - offset: 0 + size: 72 + usage: registers + interrupt: + - name: SPI_MEM_REJECT_CACHE + value: 40 + registers: + - register: + name: CTRL + description: SPI0 control register. + addressOffset: 8 + size: 32 + resetValue: 2891776 + fields: + - name: FDUMMY_OUT + description: In the dummy phase the signal level of spi is output by the spi controller. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FCMD_DUAL + description: "Apply 2 signals during command phase 1:enable 0: disable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FCMD_QUAD + description: "Apply 4 signals during command phase 1:enable 0: disable" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FASTRD_MODE + description: "This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FREAD_DUAL + description: "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: Q_POL + description: "The bit is used to set MISO line polarity, 1: high 0, low" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: D_POL + description: "The bit is used to set MOSI line polarity, 1: high 0, low" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: FREAD_QUAD + description: "In the read operations read-data phase apply 4 signals. 1: enable 0: disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: WP + description: "Write protect signal output when SPI is idle. 1: output high, 0: output low." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: FREAD_DIO + description: "In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: FREAD_QIO + description: "In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: CTRL1 + description: SPI0 control1 register. + addressOffset: 12 + size: 32 + fields: + - name: CLK_MODE + description: "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: RXFIFO_RST + description: SPI0 RX FIFO reset signal. + bitOffset: 30 + bitWidth: 1 + access: write-only + - register: + name: CTRL2 + description: SPI0 control2 register. + addressOffset: 16 + size: 32 + resetValue: 33 + fields: + - name: CS_SETUP_TIME + description: (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit. + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: CS_HOLD_TIME + description: Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit. + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: CS_HOLD_DELAY + description: "These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles." + bitOffset: 25 + bitWidth: 6 + access: read-write + - name: SYNC_RESET + description: The FSM will be reset. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: CLOCK + description: SPI clock division control register. + addressOffset: 20 + size: 32 + resetValue: 196867 + fields: + - name: CLKCNT_L + description: In the master mode it must be equal to spi_mem_clkcnt_N. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CLKCNT_H + description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: CLKCNT_N + description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: CLK_EQU_SYSCLK + description: Set this bit in 1-division mode. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USER + description: SPI0 user register. + addressOffset: 24 + size: 32 + fields: + - name: CS_HOLD + description: "spi cs keep low when spi is in done phase. 1: enable 0: disable." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CS_SETUP + description: "spi cs is enable when spi is in prepare phase. 1: enable 0: disable." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CK_OUT_EDGE + description: the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: USR_DUMMY_IDLE + description: spi clock is disable in dummy phase when the bit is enable. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: USR_DUMMY + description: This bit enable the dummy phase of an operation. + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: USER1 + description: SPI0 user1 register. + addressOffset: 28 + size: 32 + resetValue: 1543503879 + fields: + - name: USR_DUMMY_CYCLELEN + description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: USR_ADDR_BITLEN + description: The length in bits of address phase. The register value shall be (bit_num-1). + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: USER2 + description: SPI0 user2 register. + addressOffset: 32 + size: 32 + resetValue: 1879048192 + fields: + - name: USR_COMMAND_VALUE + description: The value of command. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: USR_COMMAND_BITLEN + description: The length in bits of command phase. The register value shall be (bit_num-1) + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: RD_STATUS + description: SPI0 read control register. + addressOffset: 44 + size: 32 + fields: + - name: WB_MODE + description: Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: MISC + description: SPI0 misc register + addressOffset: 52 + size: 32 + fields: + - name: TRANS_END + description: The bit is used to indicate the spi0_mst_st controlled transmitting is done. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TRANS_END_INT_ENA + description: The bit is used to enable the interrupt of spi0_mst_st controlled transmitting is done. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CSPI_ST_TRANS_END + description: The bit is used to indicate the spi0_slv_st controlled transmitting is done. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CSPI_ST_TRANS_END_INT_ENA + description: The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CK_IDLE_EDGE + description: "1: spi clk line is high when idle 0: spi clk line is low when idle" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CS_KEEP_ACTIVE + description: spi cs line keep low when the bit is set. + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: CACHE_FCTRL + description: SPI0 bit mode control register. + addressOffset: 60 + size: 32 + fields: + - name: CACHE_REQ_EN + description: "For SPI0, Cache access enable, 1: enable, 0:disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CACHE_USR_ADDR_4BYTE + description: "For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CACHE_FLASH_USR_CMD + description: "For SPI0, cache read flash for user define command, 1: enable, 0:disable." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FDIN_DUAL + description: "For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FDOUT_DUAL + description: "For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FADDR_DUAL + description: "For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FDIN_QUAD + description: "For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FDOUT_QUAD + description: "For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FADDR_QUAD + description: "For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: FSM + description: SPI0 FSM status register + addressOffset: 84 + size: 32 + resetValue: 512 + fields: + - name: CSPI_ST + description: "The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state." + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: EM_ST + description: "The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state." + bitOffset: 4 + bitWidth: 3 + access: read-only + - name: CSPI_LOCK_DELAY_TIME + description: "The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1." + bitOffset: 7 + bitWidth: 5 + access: read-write + - register: + name: TIMING_CALI + description: SPI0 timing calibration register + addressOffset: 168 + size: 32 + resetValue: 1 + fields: + - name: TIMING_CLK_ENA + description: The bit is used to enable timing adjust clock for all reading operations. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_CALI + description: The bit is used to enable timing auto-calibration for all reading operations. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EXTRA_DUMMY_CYCLELEN + description: add extra dummy spi clock cycle length for spi clock calibration. + bitOffset: 2 + bitWidth: 3 + access: read-write + - register: + name: DIN_MODE + description: SPI0 input delay mode control register + addressOffset: 172 + size: 32 + fields: + - name: DIN0_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DIN1_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DIN2_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DIN3_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 6 + bitWidth: 2 + access: read-write + - register: + name: DIN_NUM + description: SPI0 input delay number control register + addressOffset: 176 + size: 32 + fields: + - name: DIN0_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DIN1_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DIN2_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DIN3_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 6 + bitWidth: 2 + access: read-write + - register: + name: DOUT_MODE + description: SPI0 output delay mode control register + addressOffset: 180 + size: 32 + fields: + - name: DOUT0_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DOUT1_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DOUT2_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DOUT3_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: CLOCK_GATE + description: SPI0 clk_gate register + addressOffset: 220 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: "Register clock gate enable signal. 1: Enable. 0: Disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_CLK_SEL + description: SPI0 module clock select register + addressOffset: 224 + size: 32 + fields: + - name: SPI01_CLK_SEL + description: "When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used." + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 1020 + size: 32 + resetValue: 33583408 + fields: + - name: DATE + description: SPI register version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SPI1 + description: SPI (Serial Peripheral Interface) Controller 1 + groupName: SPI1 + baseAddress: 1610620928 + addressBlock: + - offset: 0 + size: 168 + usage: registers + interrupt: + - name: SPI1 + value: 18 + registers: + - register: + name: CMD + description: SPI1 memory command register + addressOffset: 0 + size: 32 + fields: + - name: SPI1_MST_ST + description: The current status of SPI1 master FSM. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: MSPI_ST + description: "The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state." + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: FLASH_PE + description: "In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: USR + description: "User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: FLASH_HPM + description: "Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: FLASH_RES + description: "This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: FLASH_DP + description: "Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: FLASH_CE + description: "Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: FLASH_BE + description: "Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: FLASH_SE + description: "Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: FLASH_PP + description: "Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: FLASH_WRSR + description: "Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: FLASH_RDSR + description: "Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: FLASH_RDID + description: "Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: FLASH_WRDI + description: "Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: FLASH_WREN + description: "Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: FLASH_READ + description: "Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: ADDR + description: SPI1 address register + addressOffset: 4 + size: 32 + fields: + - name: USR_ADDR_VALUE + description: "In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CTRL + description: SPI1 control register. + addressOffset: 8 + size: 32 + resetValue: 2924544 + fields: + - name: FDUMMY_OUT + description: In the dummy phase the signal level of spi is output by the spi controller. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FCMD_DUAL + description: "Apply 2 signals during command phase 1:enable 0: disable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FCMD_QUAD + description: "Apply 4 signals during command phase 1:enable 0: disable" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FCS_CRC_EN + description: "For SPI1, initialize crc32 module before writing encrypted data to flash. Active low." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TX_CRC_EN + description: "For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FASTRD_MODE + description: "This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FREAD_DUAL + description: "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RESANDRES + description: "The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: Q_POL + description: "The bit is used to set MISO line polarity, 1: high 0, low" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: D_POL + description: "The bit is used to set MOSI line polarity, 1: high 0, low" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: FREAD_QUAD + description: "In the read operations read-data phase apply 4 signals. 1: enable 0: disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: WP + description: "Write protect signal output when SPI is idle. 1: output high, 0: output low." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: WRSR_2B + description: "two bytes data will be written to status register when it is set. 1: enable 0: disable." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: FREAD_DIO + description: "In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: FREAD_QIO + description: "In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: CTRL1 + description: SPI1 control1 register. + addressOffset: 12 + size: 32 + resetValue: 4092 + fields: + - name: CLK_MODE + description: "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CS_HOLD_DLY_RES + description: "After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles." + bitOffset: 2 + bitWidth: 10 + access: read-write + - register: + name: CTRL2 + description: SPI1 control2 register. + addressOffset: 16 + size: 32 + fields: + - name: SYNC_RESET + description: The FSM will be reset. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: CLOCK + description: SPI1 clock division control register. + addressOffset: 20 + size: 32 + resetValue: 196867 + fields: + - name: CLKCNT_L + description: In the master mode it must be equal to spi_mem_clkcnt_N. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CLKCNT_H + description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: CLKCNT_N + description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: CLK_EQU_SYSCLK + description: reserved + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USER + description: SPI1 user register. + addressOffset: 24 + size: 32 + resetValue: 2147483648 + fields: + - name: CK_OUT_EDGE + description: the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FWRITE_DUAL + description: In the write operations read-data phase apply 2 signals + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FWRITE_QUAD + description: In the write operations read-data phase apply 4 signals + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FWRITE_DIO + description: In the write operations address phase and read-data phase apply 2 signals. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: FWRITE_QIO + description: In the write operations address phase and read-data phase apply 4 signals. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: USR_MISO_HIGHPART + description: "read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: USR_MOSI_HIGHPART + description: "write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: USR_DUMMY_IDLE + description: SPI clock is disable in dummy phase when the bit is enable. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: USR_MOSI + description: This bit enable the write-data phase of an operation. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: USR_MISO + description: This bit enable the read-data phase of an operation. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: USR_DUMMY + description: This bit enable the dummy phase of an operation. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: USR_ADDR + description: This bit enable the address phase of an operation. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: USR_COMMAND + description: This bit enable the command phase of an operation. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USER1 + description: SPI1 user1 register. + addressOffset: 28 + size: 32 + resetValue: 1543503879 + fields: + - name: USR_DUMMY_CYCLELEN + description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: USR_ADDR_BITLEN + description: The length in bits of address phase. The register value shall be (bit_num-1). + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: USER2 + description: SPI1 user2 register. + addressOffset: 32 + size: 32 + resetValue: 1879048192 + fields: + - name: USR_COMMAND_VALUE + description: The value of command. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: USR_COMMAND_BITLEN + description: The length in bits of command phase. The register value shall be (bit_num-1) + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: MOSI_DLEN + description: SPI1 send data bit length control register. + addressOffset: 36 + size: 32 + fields: + - name: USR_MOSI_DBITLEN + description: The length in bits of write-data. The register value shall be (bit_num-1). + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: MISO_DLEN + description: SPI1 receive data bit length control register. + addressOffset: 40 + size: 32 + fields: + - name: USR_MISO_DBITLEN + description: The length in bits of read-data. The register value shall be (bit_num-1). + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: RD_STATUS + description: SPI1 status register. + addressOffset: 44 + size: 32 + fields: + - name: STATUS + description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: WB_MODE + description: Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: MISC + description: SPI1 misc register + addressOffset: 52 + size: 32 + resetValue: 2 + fields: + - name: CS0_DIS + description: "SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CS1_DIS + description: "SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CK_IDLE_EDGE + description: "1: spi clk line is high when idle 0: spi clk line is low when idle" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CS_KEEP_ACTIVE + description: spi cs line keep low when the bit is set. + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: TX_CRC + description: SPI1 TX CRC data register. + addressOffset: 56 + size: 32 + resetValue: 4294967295 + fields: + - name: DATA + description: "For SPI1, the value of crc32." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CACHE_FCTRL + description: SPI1 bit mode control register. + addressOffset: 60 + size: 32 + fields: + - name: CACHE_USR_ADDR_4BYTE + description: "For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FDIN_DUAL + description: "For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FDOUT_DUAL + description: "For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FADDR_DUAL + description: "For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FDIN_QUAD + description: "For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FDOUT_QUAD + description: "For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FADDR_QUAD + description: "For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: W0 + description: SPI1 memory data buffer0 + addressOffset: 88 + size: 32 + fields: + - name: BUF0 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W1 + description: SPI1 memory data buffer1 + addressOffset: 92 + size: 32 + fields: + - name: BUF1 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W2 + description: SPI1 memory data buffer2 + addressOffset: 96 + size: 32 + fields: + - name: BUF2 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W3 + description: SPI1 memory data buffer3 + addressOffset: 100 + size: 32 + fields: + - name: BUF3 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W4 + description: SPI1 memory data buffer4 + addressOffset: 104 + size: 32 + fields: + - name: BUF4 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W5 + description: SPI1 memory data buffer5 + addressOffset: 108 + size: 32 + fields: + - name: BUF5 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W6 + description: SPI1 memory data buffer6 + addressOffset: 112 + size: 32 + fields: + - name: BUF6 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W7 + description: SPI1 memory data buffer7 + addressOffset: 116 + size: 32 + fields: + - name: BUF7 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W8 + description: SPI1 memory data buffer8 + addressOffset: 120 + size: 32 + fields: + - name: BUF8 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W9 + description: SPI1 memory data buffer9 + addressOffset: 124 + size: 32 + fields: + - name: BUF9 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W10 + description: SPI1 memory data buffer10 + addressOffset: 128 + size: 32 + fields: + - name: BUF10 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W11 + description: SPI1 memory data buffer11 + addressOffset: 132 + size: 32 + fields: + - name: BUF11 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W12 + description: SPI1 memory data buffer12 + addressOffset: 136 + size: 32 + fields: + - name: BUF12 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W13 + description: SPI1 memory data buffer13 + addressOffset: 140 + size: 32 + fields: + - name: BUF13 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W14 + description: SPI1 memory data buffer14 + addressOffset: 144 + size: 32 + fields: + - name: BUF14 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W15 + description: SPI1 memory data buffer15 + addressOffset: 148 + size: 32 + fields: + - name: BUF15 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FLASH_WAITI_CTRL + description: SPI1 wait idle control register + addressOffset: 152 + size: 32 + resetValue: 20 + fields: + - name: WAITI_DUMMY + description: The dummy phase enable when wait flash idle (RDSR) + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: WAITI_CMD + description: The command to wait flash idle(RDSR). + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: WAITI_DUMMY_CYCLELEN + description: The dummy cycle length when wait flash idle(RDSR). + bitOffset: 10 + bitWidth: 6 + access: read-write + - register: + name: FLASH_SUS_CTRL + description: SPI1 flash suspend control register + addressOffset: 156 + size: 32 + resetValue: 134225920 + fields: + - name: FLASH_PER + description: "program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FLASH_PES + description: "program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FLASH_PER_WAIT_EN + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FLASH_PES_WAIT_EN + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PES_PER_EN + description: "Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FLASH_PES_EN + description: Set this bit to enable Auto-suspending function. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: PESR_END_MSK + description: "The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]." + bitOffset: 6 + bitWidth: 16 + access: read-write + - name: RD_SUS_2B + description: "1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: PER_END_EN + description: "1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: PES_END_EN + description: "1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SUS_TIMEOUT_CNT + description: "When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass." + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: FLASH_SUS_CMD + description: SPI1 flash suspend command register + addressOffset: 160 + size: 32 + resetValue: 357754 + fields: + - name: FLASH_PER_COMMAND + description: Program/Erase resume command. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: FLASH_PES_COMMAND + description: Program/Erase suspend command. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: WAIT_PESR_COMMAND + description: Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SUS_STATUS + description: SPI1 flash suspend status register + addressOffset: 164 + size: 32 + fields: + - name: FLASH_SUS + description: "The status of flash suspend, only used in SPI1." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: WAIT_PESR_CMD_2B + description: "1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FLASH_HPM_DLY_128 + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FLASH_RES_DLY_128 + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FLASH_DP_DLY_128 + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FLASH_PER_DLY_128 + description: "Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FLASH_PES_DLY_128 + description: "Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI0_LOCK_EN + description: "1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it." + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: TIMING_CALI + description: SPI1 timing control register + addressOffset: 168 + size: 32 + fields: + - name: TIMING_CALI + description: The bit is used to enable timing auto-calibration for all reading operations. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EXTRA_DUMMY_CYCLELEN + description: add extra dummy spi clock cycle length for spi clock calibration. + bitOffset: 2 + bitWidth: 3 + access: read-write + - register: + name: INT_ENA + description: SPI1 interrupt enable register + addressOffset: 192 + size: 32 + fields: + - name: PER_END_INT_ENA + description: The enable bit for SPI_MEM_PER_END_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PES_END_INT_ENA + description: The enable bit for SPI_MEM_PES_END_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: WPE_END_INT_ENA + description: The enable bit for SPI_MEM_WPE_END_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLV_ST_END_INT_ENA + description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MST_ST_END_INT_ENA + description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: SPI1 interrupt clear register + addressOffset: 196 + size: 32 + fields: + - name: PER_END_INT_CLR + description: The clear bit for SPI_MEM_PER_END_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: PES_END_INT_CLR + description: The clear bit for SPI_MEM_PES_END_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: WPE_END_INT_CLR + description: The clear bit for SPI_MEM_WPE_END_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SLV_ST_END_INT_CLR + description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: MST_ST_END_INT_CLR + description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - register: + name: INT_RAW + description: SPI1 interrupt raw register + addressOffset: 200 + size: 32 + fields: + - name: PER_END_INT_RAW + description: "The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PES_END_INT_RAW + description: "The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: WPE_END_INT_RAW + description: "The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLV_ST_END_INT_RAW + description: "The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MST_ST_END_INT_RAW + description: "The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others." + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: SPI1 interrupt status register + addressOffset: 204 + size: 32 + fields: + - name: PER_END_INT_ST + description: The status bit for SPI_MEM_PER_END_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PES_END_INT_ST + description: The status bit for SPI_MEM_PES_END_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: WPE_END_INT_ST + description: The status bit for SPI_MEM_WPE_END_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SLV_ST_END_INT_ST + description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: MST_ST_END_INT_ST + description: The status bit for SPI_MEM_MST_ST_END_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - register: + name: CLOCK_GATE + description: SPI1 clk_gate register + addressOffset: 220 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: "Register clock gate enable signal. 1: Enable. 0: Disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 1020 + size: 32 + resetValue: 33583472 + fields: + - name: DATE + description: Version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SPI2 + description: SPI (Serial Peripheral Interface) Controller 2 + groupName: SPI2 + baseAddress: 1610760192 + addressBlock: + - offset: 0 + size: 148 + usage: registers + interrupt: + - name: SPI2 + value: 19 + registers: + - register: + name: CMD + description: Command control register + addressOffset: 0 + size: 32 + fields: + - name: CONF_BITLEN + description: Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 18 + access: read-write + - name: UPDATE + description: "Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: USR + description: "User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf." + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: ADDR + description: Address value register + addressOffset: 4 + size: 32 + fields: + - name: USR_ADDR_VALUE + description: Address to slave. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CTRL + description: SPI control register + addressOffset: 8 + size: 32 + resetValue: 3932160 + fields: + - name: DUMMY_OUT + description: In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FADDR_DUAL + description: "Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FADDR_QUAD + description: "Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FCMD_DUAL + description: "Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FCMD_QUAD + description: "Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FREAD_DUAL + description: "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: FREAD_QUAD + description: "In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: Q_POL + description: "The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: D_POL + description: "The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: HOLD_POL + description: "SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: WP_POL + description: "Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: RD_BIT_ORDER + description: "In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: WR_BIT_ORDER + description: "In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state." + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: CLOCK + description: SPI clock control register + addressOffset: 12 + size: 32 + resetValue: 2147496003 + fields: + - name: CLKCNT_L + description: In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: CLKCNT_H + description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: CLKCNT_N + description: In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + bitOffset: 12 + bitWidth: 6 + access: read-write + - name: CLKDIV_PRE + description: In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + bitOffset: 18 + bitWidth: 4 + access: read-write + - name: CLK_EQU_SYSCLK + description: "In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USER + description: SPI USER control register + addressOffset: 16 + size: 32 + resetValue: 2147483840 + fields: + - name: DOUTDIN + description: "Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: QPI_MODE + description: "Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TSCK_I_EDGE + description: "In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CS_HOLD + description: "spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CS_SETUP + description: "spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RSCK_I_EDGE + description: "In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CK_OUT_EDGE + description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FWRITE_DUAL + description: In the write operations read-data phase apply 2 signals. Can be configured in CONF state. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FWRITE_QUAD + description: In the write operations read-data phase apply 4 signals. Can be configured in CONF state. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: USR_CONF_NXT + description: "1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SIO + description: "Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: USR_MISO_HIGHPART + description: "read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: USR_MOSI_HIGHPART + description: "write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: USR_DUMMY_IDLE + description: spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: USR_MOSI + description: This bit enable the write-data phase of an operation. Can be configured in CONF state. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: USR_MISO + description: This bit enable the read-data phase of an operation. Can be configured in CONF state. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: USR_DUMMY + description: This bit enable the dummy phase of an operation. Can be configured in CONF state. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: USR_ADDR + description: This bit enable the address phase of an operation. Can be configured in CONF state. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: USR_COMMAND + description: This bit enable the command phase of an operation. Can be configured in CONF state. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USER1 + description: SPI USER control register 1 + addressOffset: 20 + size: 32 + resetValue: 3091267591 + fields: + - name: USR_DUMMY_CYCLELEN + description: The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: MST_WFULL_ERR_END_EN + description: "1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CS_SETUP_TIME + description: (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. + bitOffset: 17 + bitWidth: 5 + access: read-write + - name: CS_HOLD_TIME + description: delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. + bitOffset: 22 + bitWidth: 5 + access: read-write + - name: USR_ADDR_BITLEN + description: The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: USER2 + description: SPI USER control register 2 + addressOffset: 24 + size: 32 + resetValue: 2013265920 + fields: + - name: USR_COMMAND_VALUE + description: The value of command. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MST_REMPTY_ERR_END_EN + description: "1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: USR_COMMAND_BITLEN + description: The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: MS_DLEN + description: SPI data bit length control register + addressOffset: 28 + size: 32 + fields: + - name: MS_DATA_BITLEN + description: The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 0 + bitWidth: 18 + access: read-write + - register: + name: MISC + description: SPI misc register + addressOffset: 32 + size: 32 + resetValue: 62 + fields: + - name: CS0_DIS + description: "SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CS1_DIS + description: "SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CS2_DIS + description: "SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CS3_DIS + description: "SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CS4_DIS + description: "SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CS5_DIS + description: "SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CK_DIS + description: "1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: MASTER_CS_POL + description: "In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: SLAVE_CS_POL + description: "spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: CK_IDLE_EDGE + description: "1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CS_KEEP_ACTIVE + description: spi cs line keep low when the bit is set. Can be configured in CONF state. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: QUAD_DIN_PIN_SWAP + description: "1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DIN_MODE + description: SPI input delay mode configuration + addressOffset: 36 + size: 32 + fields: + - name: DIN0_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DIN1_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DIN2_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DIN3_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: TIMING_HCLK_ACTIVE + description: "1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state." + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: DIN_NUM + description: SPI input delay number configuration + addressOffset: 40 + size: 32 + fields: + - name: DIN0_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DIN1_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DIN2_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DIN3_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 6 + bitWidth: 2 + access: read-write + - register: + name: DOUT_MODE + description: SPI output delay mode configuration + addressOffset: 44 + size: 32 + fields: + - name: DOUT0_MODE + description: "The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DOUT1_MODE + description: "The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DOUT2_MODE + description: "The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DOUT3_MODE + description: "The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: DMA_CONF + description: SPI DMA control register + addressOffset: 48 + size: 32 + fields: + - name: DMA_SLV_SEG_TRANS_EN + description: "Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SLV_RX_SEG_TRANS_CLR_EN + description: "1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SLV_TX_SEG_TRANS_CLR_EN + description: "1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: RX_EOF_EN + description: "1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: DMA_RX_ENA + description: Set this bit to enable SPI DMA controlled receive data mode. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: DMA_TX_ENA + description: Set this bit to enable SPI DMA controlled send data mode. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: RX_AFIFO_RST + description: "Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer." + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: BUF_AFIFO_RST + description: "Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer." + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: DMA_AFIFO_RST + description: "Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer." + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: DMA_INT_ENA + description: SPI DMA interrupt enable register + addressOffset: 52 + size: 32 + fields: + - name: DMA_INFIFO_FULL_ERR_INT_ENA + description: The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DMA_OUTFIFO_EMPTY_ERR_INT_ENA + description: The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SLV_EX_QPI_INT_ENA + description: The enable bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLV_EN_QPI_INT_ENA + description: The enable bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLV_CMD7_INT_ENA + description: The enable bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SLV_CMD8_INT_ENA + description: The enable bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SLV_CMD9_INT_ENA + description: The enable bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SLV_CMDA_INT_ENA + description: The enable bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SLV_RD_DMA_DONE_INT_ENA + description: The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLV_WR_DMA_DONE_INT_ENA + description: The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLV_RD_BUF_DONE_INT_ENA + description: The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLV_WR_BUF_DONE_INT_ENA + description: The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TRANS_DONE_INT_ENA + description: The enable bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DMA_SEG_TRANS_DONE_INT_ENA + description: The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SEG_MAGIC_ERR_INT_ENA + description: The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLV_BUF_ADDR_ERR_INT_ENA + description: The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLV_CMD_ERR_INT_ENA + description: The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: MST_RX_AFIFO_WFULL_ERR_INT_ENA + description: The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MST_TX_AFIFO_REMPTY_ERR_INT_ENA + description: The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: APP2_INT_ENA + description: The enable bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: APP1_INT_ENA + description: The enable bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: DMA_INT_CLR + description: SPI DMA interrupt clear register + addressOffset: 56 + size: 32 + fields: + - name: DMA_INFIFO_FULL_ERR_INT_CLR + description: The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: DMA_OUTFIFO_EMPTY_ERR_INT_CLR + description: The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SLV_EX_QPI_INT_CLR + description: The clear bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SLV_EN_QPI_INT_CLR + description: The clear bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SLV_CMD7_INT_CLR + description: The clear bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SLV_CMD8_INT_CLR + description: The clear bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: SLV_CMD9_INT_CLR + description: The clear bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: SLV_CMDA_INT_CLR + description: The clear bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SLV_RD_DMA_DONE_INT_CLR + description: The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SLV_WR_DMA_DONE_INT_CLR + description: The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SLV_RD_BUF_DONE_INT_CLR + description: The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SLV_WR_BUF_DONE_INT_CLR + description: The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TRANS_DONE_INT_CLR + description: The clear bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: DMA_SEG_TRANS_DONE_INT_CLR + description: The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SEG_MAGIC_ERR_INT_CLR + description: The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SLV_BUF_ADDR_ERR_INT_CLR + description: The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: SLV_CMD_ERR_INT_CLR + description: The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: MST_RX_AFIFO_WFULL_ERR_INT_CLR + description: The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: MST_TX_AFIFO_REMPTY_ERR_INT_CLR + description: The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: APP2_INT_CLR + description: The clear bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: APP1_INT_CLR + description: The clear bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: write-only + - register: + name: DMA_INT_RAW + description: SPI DMA interrupt raw register + addressOffset: 60 + size: 32 + fields: + - name: DMA_INFIFO_FULL_ERR_INT_RAW + description: "1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DMA_OUTFIFO_EMPTY_ERR_INT_RAW + description: "1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SLV_EX_QPI_INT_RAW + description: "The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLV_EN_QPI_INT_RAW + description: "The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLV_CMD7_INT_RAW + description: "The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SLV_CMD8_INT_RAW + description: "The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SLV_CMD9_INT_RAW + description: "The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SLV_CMDA_INT_RAW + description: "The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SLV_RD_DMA_DONE_INT_RAW + description: "The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLV_WR_DMA_DONE_INT_RAW + description: "The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLV_RD_BUF_DONE_INT_RAW + description: "The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLV_WR_BUF_DONE_INT_RAW + description: "The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TRANS_DONE_INT_RAW + description: "The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DMA_SEG_TRANS_DONE_INT_RAW + description: "The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SEG_MAGIC_ERR_INT_RAW + description: "The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLV_BUF_ADDR_ERR_INT_RAW + description: "The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLV_CMD_ERR_INT_RAW + description: "The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: MST_RX_AFIFO_WFULL_ERR_INT_RAW + description: "The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MST_TX_AFIFO_REMPTY_ERR_INT_RAW + description: "The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: APP2_INT_RAW + description: The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: APP1_INT_RAW + description: The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application. + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: DMA_INT_ST + description: SPI DMA interrupt status register + addressOffset: 64 + size: 32 + fields: + - name: DMA_INFIFO_FULL_ERR_INT_ST + description: The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DMA_OUTFIFO_EMPTY_ERR_INT_ST + description: The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SLV_EX_QPI_INT_ST + description: The status bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SLV_EN_QPI_INT_ST + description: The status bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SLV_CMD7_INT_ST + description: The status bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SLV_CMD8_INT_ST + description: The status bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SLV_CMD9_INT_ST + description: The status bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SLV_CMDA_INT_ST + description: The status bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SLV_RD_DMA_DONE_INT_ST + description: The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SLV_WR_DMA_DONE_INT_ST + description: The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SLV_RD_BUF_DONE_INT_ST + description: The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SLV_WR_BUF_DONE_INT_ST + description: The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TRANS_DONE_INT_ST + description: The status bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: DMA_SEG_TRANS_DONE_INT_ST + description: The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SEG_MAGIC_ERR_INT_ST + description: The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SLV_BUF_ADDR_ERR_INT_ST + description: The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLV_CMD_ERR_INT_ST + description: The status bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: MST_RX_AFIFO_WFULL_ERR_INT_ST + description: The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: MST_TX_AFIFO_REMPTY_ERR_INT_ST + description: The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: APP2_INT_ST + description: The status bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: APP1_INT_ST + description: The status bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: read-only + - register: + name: W0 + description: SPI CPU-controlled buffer0 + addressOffset: 152 + size: 32 + fields: + - name: BUF0 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W1 + description: SPI CPU-controlled buffer1 + addressOffset: 156 + size: 32 + fields: + - name: BUF1 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W2 + description: SPI CPU-controlled buffer2 + addressOffset: 160 + size: 32 + fields: + - name: BUF2 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W3 + description: SPI CPU-controlled buffer3 + addressOffset: 164 + size: 32 + fields: + - name: BUF3 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W4 + description: SPI CPU-controlled buffer4 + addressOffset: 168 + size: 32 + fields: + - name: BUF4 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W5 + description: SPI CPU-controlled buffer5 + addressOffset: 172 + size: 32 + fields: + - name: BUF5 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W6 + description: SPI CPU-controlled buffer6 + addressOffset: 176 + size: 32 + fields: + - name: BUF6 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W7 + description: SPI CPU-controlled buffer7 + addressOffset: 180 + size: 32 + fields: + - name: BUF7 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W8 + description: SPI CPU-controlled buffer8 + addressOffset: 184 + size: 32 + fields: + - name: BUF8 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W9 + description: SPI CPU-controlled buffer9 + addressOffset: 188 + size: 32 + fields: + - name: BUF9 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W10 + description: SPI CPU-controlled buffer10 + addressOffset: 192 + size: 32 + fields: + - name: BUF10 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W11 + description: SPI CPU-controlled buffer11 + addressOffset: 196 + size: 32 + fields: + - name: BUF11 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W12 + description: SPI CPU-controlled buffer12 + addressOffset: 200 + size: 32 + fields: + - name: BUF12 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W13 + description: SPI CPU-controlled buffer13 + addressOffset: 204 + size: 32 + fields: + - name: BUF13 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W14 + description: SPI CPU-controlled buffer14 + addressOffset: 208 + size: 32 + fields: + - name: BUF14 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W15 + description: SPI CPU-controlled buffer15 + addressOffset: 212 + size: 32 + fields: + - name: BUF15 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SLAVE + description: SPI slave control register + addressOffset: 224 + size: 32 + resetValue: 41943040 + fields: + - name: CLK_MODE + description: "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CLK_MODE_13 + description: "{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RSCK_DATA_OUT + description: "It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLV_RDDMA_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLV_WRDMA_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLV_RDBUF_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLV_WRBUF_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DMA_SEG_MAGIC_VALUE + description: The magic value of BM table in master DMA seg-trans. + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: MODE + description: "Set SPI work mode. 1: slave mode 0: master mode." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SOFT_RESET + description: "Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state." + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: USR_CONF + description: "1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode." + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: SLAVE1 + description: SPI slave control register 1 + addressOffset: 228 + size: 32 + fields: + - name: SLV_DATA_BITLEN + description: The transferred data bit length in SPI slave FD and HD mode. + bitOffset: 0 + bitWidth: 18 + access: read-write + - name: SLV_LAST_COMMAND + description: In the slave mode it is the value of command. + bitOffset: 18 + bitWidth: 8 + access: read-write + - name: SLV_LAST_ADDR + description: In the slave mode it is the value of address. + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: CLK_GATE + description: SPI module clock and register clock control + addressOffset: 232 + size: 32 + fields: + - name: CLK_EN + description: Set this bit to enable clk gate + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MST_CLK_ACTIVE + description: Set this bit to power on the SPI module clock. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MST_CLK_SEL + description: "This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control + addressOffset: 240 + size: 32 + resetValue: 33583648 + fields: + - name: DATE + description: SPI register version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SYSTEM + description: System Configuration Registers + groupName: SYSTEM + baseAddress: 1611399168 + addressBlock: + - offset: 0 + size: 160 + usage: registers + registers: + - register: + name: CPU_PERI_CLK_EN + description: cpu_peripheral clock gating register + addressOffset: 0 + size: 32 + fields: + - name: CLK_EN_ASSIST_DEBUG + description: reg_clk_en_assist_debug + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CLK_EN_DEDICATED_GPIO + description: reg_clk_en_dedicated_gpio + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: CPU_PERI_RST_EN + description: cpu_peripheral reset register + addressOffset: 4 + size: 32 + resetValue: 192 + fields: + - name: RST_EN_ASSIST_DEBUG + description: reg_rst_en_assist_debug + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RST_EN_DEDICATED_GPIO + description: reg_rst_en_dedicated_gpio + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: CPU_PER_CONF + description: cpu clock config register + addressOffset: 8 + size: 32 + resetValue: 12 + fields: + - name: CPUPERIOD_SEL + description: reg_cpuperiod_sel + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: PLL_FREQ_SEL + description: reg_pll_freq_sel + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CPU_WAIT_MODE_FORCE_ON + description: reg_cpu_wait_mode_force_on + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CPU_WAITI_DELAY_NUM + description: reg_cpu_waiti_delay_num + bitOffset: 4 + bitWidth: 4 + access: read-write + - register: + name: MEM_PD_MASK + description: memory power down mask register + addressOffset: 12 + size: 32 + resetValue: 1 + fields: + - name: LSLP_MEM_PD_MASK + description: reg_lslp_mem_pd_mask + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: PERIP_CLK_EN0 + description: peripheral clock gating register + addressOffset: 16 + size: 32 + resetValue: 4190232687 + fields: + - name: TIMERS_CLK_EN + description: reg_timers_clk_en + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI01_CLK_EN + description: reg_spi01_clk_en + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UART_CLK_EN + description: reg_uart_clk_en + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: WDG_CLK_EN + description: reg_wdg_clk_en + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: I2S0_CLK_EN + description: reg_i2s0_clk_en + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: UART1_CLK_EN + description: reg_uart1_clk_en + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI2_CLK_EN + description: reg_spi2_clk_en + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: I2C_EXT0_CLK_EN + description: reg_ext0_clk_en + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: UHCI0_CLK_EN + description: reg_uhci0_clk_en + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RMT_CLK_EN + description: reg_rmt_clk_en + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PCNT_CLK_EN + description: reg_pcnt_clk_en + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: LEDC_CLK_EN + description: reg_ledc_clk_en + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: UHCI1_CLK_EN + description: reg_uhci1_clk_en + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TIMERGROUP_CLK_EN + description: reg_timergroup_clk_en + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: EFUSE_CLK_EN + description: reg_efuse_clk_en + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TIMERGROUP1_CLK_EN + description: reg_timergroup1_clk_en + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI3_CLK_EN + description: reg_spi3_clk_en + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PWM0_CLK_EN + description: reg_pwm0_clk_en + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: EXT1_CLK_EN + description: reg_ext1_clk_en + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TWAI_CLK_EN + description: reg_can_clk_en + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PWM1_CLK_EN + description: reg_pwm1_clk_en + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: I2S1_CLK_EN + description: reg_i2s1_clk_en + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI2_DMA_CLK_EN + description: reg_spi2_dma_clk_en + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: USB_DEVICE_CLK_EN + description: reg_usb_device_clk_en + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: UART_MEM_CLK_EN + description: reg_uart_mem_clk_en + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PWM2_CLK_EN + description: reg_pwm2_clk_en + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PWM3_CLK_EN + description: reg_pwm3_clk_en + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI3_DMA_CLK_EN + description: reg_spi3_dma_clk_en + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: APB_SARADC_CLK_EN + description: reg_apb_saradc_clk_en + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SYSTIMER_CLK_EN + description: reg_systimer_clk_en + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ADC2_ARB_CLK_EN + description: reg_adc2_arb_clk_en + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI4_CLK_EN + description: reg_spi4_clk_en + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: PERIP_CLK_EN1 + description: peripheral clock gating register + addressOffset: 20 + size: 32 + resetValue: 512 + fields: + - name: CRYPTO_AES_CLK_EN + description: reg_crypto_aes_clk_en + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CRYPTO_SHA_CLK_EN + description: reg_crypto_sha_clk_en + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CRYPTO_RSA_CLK_EN + description: reg_crypto_rsa_clk_en + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CRYPTO_DS_CLK_EN + description: reg_crypto_ds_clk_en + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CRYPTO_HMAC_CLK_EN + description: reg_crypto_hmac_clk_en + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DMA_CLK_EN + description: reg_dma_clk_en + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SDIO_HOST_CLK_EN + description: reg_sdio_host_clk_en + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: LCD_CAM_CLK_EN + description: reg_lcd_cam_clk_en + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: UART2_CLK_EN + description: reg_uart2_clk_en + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TSENS_CLK_EN + description: reg_tsens_clk_en + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PERIP_RST_EN0 + description: reserved + addressOffset: 24 + size: 32 + fields: + - name: TIMERS_RST + description: reg_timers_rst + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI01_RST + description: reg_spi01_rst + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UART_RST + description: reg_uart_rst + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: WDG_RST + description: reg_wdg_rst + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: I2S0_RST + description: reg_i2s0_rst + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: UART1_RST + description: reg_uart1_rst + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI2_RST + description: reg_spi2_rst + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: I2C_EXT0_RST + description: reg_ext0_rst + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: UHCI0_RST + description: reg_uhci0_rst + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RMT_RST + description: reg_rmt_rst + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PCNT_RST + description: reg_pcnt_rst + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: LEDC_RST + description: reg_ledc_rst + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: UHCI1_RST + description: reg_uhci1_rst + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TIMERGROUP_RST + description: reg_timergroup_rst + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: EFUSE_RST + description: reg_efuse_rst + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TIMERGROUP1_RST + description: reg_timergroup1_rst + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI3_RST + description: reg_spi3_rst + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PWM0_RST + description: reg_pwm0_rst + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: EXT1_RST + description: reg_ext1_rst + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TWAI_RST + description: reg_can_rst + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PWM1_RST + description: reg_pwm1_rst + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: I2S1_RST + description: reg_i2s1_rst + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI2_DMA_RST + description: reg_spi2_dma_rst + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: USB_DEVICE_RST + description: reg_usb_device_rst + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: UART_MEM_RST + description: reg_uart_mem_rst + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PWM2_RST + description: reg_pwm2_rst + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PWM3_RST + description: reg_pwm3_rst + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI3_DMA_RST + description: reg_spi3_dma_rst + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: APB_SARADC_RST + description: reg_apb_saradc_rst + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SYSTIMER_RST + description: reg_systimer_rst + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ADC2_ARB_RST + description: reg_adc2_arb_rst + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI4_RST + description: reg_spi4_rst + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: PERIP_RST_EN1 + description: peripheral reset register + addressOffset: 28 + size: 32 + resetValue: 510 + fields: + - name: CRYPTO_AES_RST + description: reg_crypto_aes_rst + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CRYPTO_SHA_RST + description: reg_crypto_sha_rst + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CRYPTO_RSA_RST + description: reg_crypto_rsa_rst + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CRYPTO_DS_RST + description: reg_crypto_ds_rst + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CRYPTO_HMAC_RST + description: reg_crypto_hmac_rst + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DMA_RST + description: reg_dma_rst + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SDIO_HOST_RST + description: reg_sdio_host_rst + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: LCD_CAM_RST + description: reg_lcd_cam_rst + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: UART2_RST + description: reg_uart2_rst + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TSENS_RST + description: reg_tsens_rst + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: BT_LPCK_DIV_INT + description: clock config register + addressOffset: 32 + size: 32 + resetValue: 255 + fields: + - name: BT_LPCK_DIV_NUM + description: reg_bt_lpck_div_num + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: BT_LPCK_DIV_FRAC + description: clock config register + addressOffset: 36 + size: 32 + resetValue: 33558529 + fields: + - name: BT_LPCK_DIV_B + description: reg_bt_lpck_div_b + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: BT_LPCK_DIV_A + description: reg_bt_lpck_div_a + bitOffset: 12 + bitWidth: 12 + access: read-write + - name: LPCLK_SEL_RTC_SLOW + description: reg_lpclk_sel_rtc_slow + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: LPCLK_SEL_8M + description: reg_lpclk_sel_8m + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LPCLK_SEL_XTAL + description: reg_lpclk_sel_xtal + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LPCLK_SEL_XTAL32K + description: reg_lpclk_sel_xtal32k + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LPCLK_RTC_EN + description: reg_lpclk_rtc_en + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_0 + description: interrupt generate register + addressOffset: 40 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_0 + description: reg_cpu_intr_from_cpu_0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_1 + description: interrupt generate register + addressOffset: 44 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_1 + description: reg_cpu_intr_from_cpu_1 + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_2 + description: interrupt generate register + addressOffset: 48 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_2 + description: reg_cpu_intr_from_cpu_2 + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_3 + description: interrupt generate register + addressOffset: 52 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_3 + description: reg_cpu_intr_from_cpu_3 + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: RSA_PD_CTRL + description: rsa memory power control register + addressOffset: 56 + size: 32 + resetValue: 1 + fields: + - name: RSA_MEM_PD + description: reg_rsa_mem_pd + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RSA_MEM_FORCE_PU + description: reg_rsa_mem_force_pu + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RSA_MEM_FORCE_PD + description: reg_rsa_mem_force_pd + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: EDMA_CTRL + description: EDMA clock and reset register + addressOffset: 60 + size: 32 + resetValue: 1 + fields: + - name: EDMA_CLK_ON + description: reg_edma_clk_on + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EDMA_RESET + description: reg_edma_reset + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CACHE_CONTROL + description: cache control register + addressOffset: 64 + size: 32 + resetValue: 5 + fields: + - name: ICACHE_CLK_ON + description: reg_icache_clk_on + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ICACHE_RESET + description: reg_icache_reset + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DCACHE_CLK_ON + description: reg_dcache_clk_on + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DCACHE_RESET + description: reg_dcache_reset + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL + description: SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG + addressOffset: 68 + size: 32 + fields: + - name: ENABLE_SPI_MANUAL_ENCRYPT + description: reg_enable_spi_manual_encrypt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ENABLE_DOWNLOAD_DB_ENCRYPT + description: reg_enable_download_db_encrypt + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ENABLE_DOWNLOAD_G0CB_DECRYPT + description: reg_enable_download_g0cb_decrypt + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ENABLE_DOWNLOAD_MANUAL_ENCRYPT + description: reg_enable_download_manual_encrypt + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: RTC_FASTMEM_CONFIG + description: fast memory config register + addressOffset: 72 + size: 32 + resetValue: 2146435072 + fields: + - name: RTC_MEM_CRC_START + description: reg_rtc_mem_crc_start + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RTC_MEM_CRC_ADDR + description: reg_rtc_mem_crc_addr + bitOffset: 9 + bitWidth: 11 + access: read-write + - name: RTC_MEM_CRC_LEN + description: reg_rtc_mem_crc_len + bitOffset: 20 + bitWidth: 11 + access: read-write + - name: RTC_MEM_CRC_FINISH + description: reg_rtc_mem_crc_finish + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: RTC_FASTMEM_CRC + description: reserved + addressOffset: 76 + size: 32 + fields: + - name: RTC_MEM_CRC_RES + description: reg_rtc_mem_crc_res + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: REDUNDANT_ECO_CTRL + description: eco register + addressOffset: 80 + size: 32 + fields: + - name: REDUNDANT_ECO_DRIVE + description: reg_redundant_eco_drive + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REDUNDANT_ECO_RESULT + description: reg_redundant_eco_result + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: CLOCK_GATE + description: clock gating register + addressOffset: 84 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: reg_clk_en + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SYSCLK_CONF + description: system clock config register + addressOffset: 88 + size: 32 + resetValue: 1 + fields: + - name: PRE_DIV_CNT + description: reg_pre_div_cnt + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: SOC_CLK_SEL + description: reg_soc_clk_sel + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CLK_XTAL_FREQ + description: reg_clk_xtal_freq + bitOffset: 12 + bitWidth: 7 + access: read-only + - name: CLK_DIV_EN + description: reg_clk_div_en + bitOffset: 19 + bitWidth: 1 + access: read-only + - register: + name: MEM_PVT + description: mem pvt register + addressOffset: 92 + size: 32 + resetValue: 3 + fields: + - name: MEM_PATH_LEN + description: reg_mem_path_len + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: MEM_ERR_CNT_CLR + description: reg_mem_err_cnt_clr + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: MONITOR_EN + description: reg_mem_pvt_monitor_en + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: MEM_TIMING_ERR_CNT + description: reg_mem_timing_err_cnt + bitOffset: 6 + bitWidth: 16 + access: read-only + - name: MEM_VT_SEL + description: reg_mem_vt_sel + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: COMB_PVT_LVT_CONF + description: mem pvt register + addressOffset: 96 + size: 32 + resetValue: 3 + fields: + - name: COMB_PATH_LEN_LVT + description: reg_comb_path_len_lvt + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: COMB_ERR_CNT_CLR_LVT + description: reg_comb_err_cnt_clr_lvt + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: COMB_PVT_MONITOR_EN_LVT + description: reg_comb_pvt_monitor_en_lvt + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: COMB_PVT_NVT_CONF + description: mem pvt register + addressOffset: 100 + size: 32 + resetValue: 3 + fields: + - name: COMB_PATH_LEN_NVT + description: reg_comb_path_len_nvt + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: COMB_ERR_CNT_CLR_NVT + description: reg_comb_err_cnt_clr_nvt + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: COMB_PVT_MONITOR_EN_NVT + description: reg_comb_pvt_monitor_en_nvt + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: COMB_PVT_HVT_CONF + description: mem pvt register + addressOffset: 104 + size: 32 + resetValue: 3 + fields: + - name: COMB_PATH_LEN_HVT + description: reg_comb_path_len_hvt + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: COMB_ERR_CNT_CLR_HVT + description: reg_comb_err_cnt_clr_hvt + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: COMB_PVT_MONITOR_EN_HVT + description: reg_comb_pvt_monitor_en_hvt + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: COMB_PVT_ERR_LVT_SITE0 + description: mem pvt register + addressOffset: 108 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_LVT_SITE0 + description: reg_comb_timing_err_cnt_lvt_site0 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_NVT_SITE0 + description: mem pvt register + addressOffset: 112 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_NVT_SITE0 + description: reg_comb_timing_err_cnt_nvt_site0 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_HVT_SITE0 + description: mem pvt register + addressOffset: 116 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_HVT_SITE0 + description: reg_comb_timing_err_cnt_hvt_site0 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_LVT_SITE1 + description: mem pvt register + addressOffset: 120 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_LVT_SITE1 + description: reg_comb_timing_err_cnt_lvt_site1 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_NVT_SITE1 + description: mem pvt register + addressOffset: 124 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_NVT_SITE1 + description: reg_comb_timing_err_cnt_nvt_site1 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_HVT_SITE1 + description: mem pvt register + addressOffset: 128 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_HVT_SITE1 + description: reg_comb_timing_err_cnt_hvt_site1 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_LVT_SITE2 + description: mem pvt register + addressOffset: 132 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_LVT_SITE2 + description: reg_comb_timing_err_cnt_lvt_site2 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_NVT_SITE2 + description: mem pvt register + addressOffset: 136 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_NVT_SITE2 + description: reg_comb_timing_err_cnt_nvt_site2 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_HVT_SITE2 + description: mem pvt register + addressOffset: 140 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_HVT_SITE2 + description: reg_comb_timing_err_cnt_hvt_site2 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_LVT_SITE3 + description: mem pvt register + addressOffset: 144 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_LVT_SITE3 + description: reg_comb_timing_err_cnt_lvt_site3 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_NVT_SITE3 + description: mem pvt register + addressOffset: 148 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_NVT_SITE3 + description: reg_comb_timing_err_cnt_nvt_site3 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_HVT_SITE3 + description: mem pvt register + addressOffset: 152 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_HVT_SITE3 + description: reg_comb_timing_err_cnt_hvt_site3 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: SYSTEM_REG_DATE + description: Version register + addressOffset: 4092 + size: 32 + resetValue: 33583440 + fields: + - name: SYSTEM_REG_DATE + description: reg_system_reg_date + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SYSTIMER + description: System Timer + groupName: SYSTIMER + baseAddress: 1610756096 + addressBlock: + - offset: 0 + size: 120 + usage: registers + interrupt: + - name: SYSTIMER_TARGET0 + value: 37 + - name: SYSTIMER_TARGET1 + value: 38 + - name: SYSTIMER_TARGET2 + value: 39 + registers: + - register: + name: CONF + description: SYSTIMER_CONF. + addressOffset: 0 + size: 32 + resetValue: 1174405120 + fields: + - name: SYSTIMER_CLK_FO + description: systimer clock force on + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TARGET2_WORK_EN + description: target2 work enable + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TARGET1_WORK_EN + description: target1 work enable + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TARGET0_WORK_EN + description: target0 work enable + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT1_CORE1_STALL_EN + description: If timer unit1 is stalled when core1 stalled + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT1_CORE0_STALL_EN + description: If timer unit1 is stalled when core0 stalled + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT0_CORE1_STALL_EN + description: If timer unit0 is stalled when core1 stalled + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT0_CORE0_STALL_EN + description: If timer unit0 is stalled when core0 stalled + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT1_WORK_EN + description: timer unit1 work enable + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT0_WORK_EN + description: timer unit0 work enable + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: register file clk gating + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: UNIT0_OP + description: SYSTIMER_UNIT0_OP. + addressOffset: 4 + size: 32 + fields: + - name: TIMER_UNIT0_VALUE_VALID + description: reg_timer_unit0_value_valid + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: TIMER_UNIT0_UPDATE + description: update timer_unit0 + bitOffset: 30 + bitWidth: 1 + access: write-only + - register: + name: UNIT1_OP + description: SYSTIMER_UNIT1_OP. + addressOffset: 8 + size: 32 + fields: + - name: TIMER_UNIT1_VALUE_VALID + description: timer value is sync and valid + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: TIMER_UNIT1_UPDATE + description: update timer unit1 + bitOffset: 30 + bitWidth: 1 + access: write-only + - register: + name: UNIT0_LOAD_HI + description: SYSTIMER_UNIT0_LOAD_HI. + addressOffset: 12 + size: 32 + fields: + - name: TIMER_UNIT0_LOAD_HI + description: timer unit0 load high 32 bit + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: UNIT0_LOAD_LO + description: SYSTIMER_UNIT0_LOAD_LO. + addressOffset: 16 + size: 32 + fields: + - name: TIMER_UNIT0_LOAD_LO + description: timer unit0 load low 32 bit + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: UNIT1_LOAD_HI + description: SYSTIMER_UNIT1_LOAD_HI. + addressOffset: 20 + size: 32 + fields: + - name: TIMER_UNIT1_LOAD_HI + description: timer unit1 load high 32 bit + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: UNIT1_LOAD_LO + description: SYSTIMER_UNIT1_LOAD_LO. + addressOffset: 24 + size: 32 + fields: + - name: TIMER_UNIT1_LOAD_LO + description: timer unit1 load low 32 bit + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET0_HI + description: SYSTIMER_TARGET0_HI. + addressOffset: 28 + size: 32 + fields: + - name: TIMER_TARGET0_HI + description: timer taget0 high 32 bit + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: TARGET0_LO + description: SYSTIMER_TARGET0_LO. + addressOffset: 32 + size: 32 + fields: + - name: TIMER_TARGET0_LO + description: timer taget0 low 32 bit + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET1_HI + description: SYSTIMER_TARGET1_HI. + addressOffset: 36 + size: 32 + fields: + - name: TIMER_TARGET1_HI + description: timer taget1 high 32 bit + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: TARGET1_LO + description: SYSTIMER_TARGET1_LO. + addressOffset: 40 + size: 32 + fields: + - name: TIMER_TARGET1_LO + description: timer taget1 low 32 bit + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET2_HI + description: SYSTIMER_TARGET2_HI. + addressOffset: 44 + size: 32 + fields: + - name: TIMER_TARGET2_HI + description: timer taget2 high 32 bit + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: TARGET2_LO + description: SYSTIMER_TARGET2_LO. + addressOffset: 48 + size: 32 + fields: + - name: TIMER_TARGET2_LO + description: timer taget2 low 32 bit + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET0_CONF + description: SYSTIMER_TARGET0_CONF. + addressOffset: 52 + size: 32 + fields: + - name: TARGET0_PERIOD + description: target0 period + bitOffset: 0 + bitWidth: 26 + access: read-write + - name: TARGET0_PERIOD_MODE + description: Set target0 to period mode + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TARGET0_TIMER_UNIT_SEL + description: select which unit to compare + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TARGET1_CONF + description: SYSTIMER_TARGET1_CONF. + addressOffset: 56 + size: 32 + fields: + - name: TARGET1_PERIOD + description: target1 period + bitOffset: 0 + bitWidth: 26 + access: read-write + - name: TARGET1_PERIOD_MODE + description: Set target1 to period mode + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TARGET1_TIMER_UNIT_SEL + description: select which unit to compare + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TARGET2_CONF + description: SYSTIMER_TARGET2_CONF. + addressOffset: 60 + size: 32 + fields: + - name: TARGET2_PERIOD + description: target2 period + bitOffset: 0 + bitWidth: 26 + access: read-write + - name: TARGET2_PERIOD_MODE + description: Set target2 to period mode + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TARGET2_TIMER_UNIT_SEL + description: select which unit to compare + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: UNIT0_VALUE_HI + description: SYSTIMER_UNIT0_VALUE_HI. + addressOffset: 64 + size: 32 + fields: + - name: TIMER_UNIT0_VALUE_HI + description: timer read value high 32bit + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: UNIT0_VALUE_LO + description: SYSTIMER_UNIT0_VALUE_LO. + addressOffset: 68 + size: 32 + fields: + - name: TIMER_UNIT0_VALUE_LO + description: timer read value low 32bit + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: UNIT1_VALUE_HI + description: SYSTIMER_UNIT1_VALUE_HI. + addressOffset: 72 + size: 32 + fields: + - name: TIMER_UNIT1_VALUE_HI + description: timer read value high 32bit + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: UNIT1_VALUE_LO + description: SYSTIMER_UNIT1_VALUE_LO. + addressOffset: 76 + size: 32 + fields: + - name: TIMER_UNIT1_VALUE_LO + description: timer read value low 32bit + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: COMP0_LOAD + description: SYSTIMER_COMP0_LOAD. + addressOffset: 80 + size: 32 + fields: + - name: TIMER_COMP0_LOAD + description: timer comp0 load value + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: COMP1_LOAD + description: SYSTIMER_COMP1_LOAD. + addressOffset: 84 + size: 32 + fields: + - name: TIMER_COMP1_LOAD + description: timer comp1 load value + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: COMP2_LOAD + description: SYSTIMER_COMP2_LOAD. + addressOffset: 88 + size: 32 + fields: + - name: TIMER_COMP2_LOAD + description: timer comp2 load value + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: UNIT0_LOAD + description: SYSTIMER_UNIT0_LOAD. + addressOffset: 92 + size: 32 + fields: + - name: TIMER_UNIT0_LOAD + description: timer unit0 load value + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: UNIT1_LOAD + description: SYSTIMER_UNIT1_LOAD. + addressOffset: 96 + size: 32 + fields: + - name: TIMER_UNIT1_LOAD + description: timer unit1 load value + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + description: SYSTIMER_INT_ENA. + addressOffset: 100 + size: 32 + fields: + - name: TARGET0_INT_ENA + description: interupt0 enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TARGET1_INT_ENA + description: interupt1 enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TARGET2_INT_ENA + description: interupt2 enable + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: SYSTIMER_INT_RAW. + addressOffset: 104 + size: 32 + fields: + - name: TARGET0_INT_RAW + description: interupt0 raw + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TARGET1_INT_RAW + description: interupt1 raw + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TARGET2_INT_RAW + description: interupt2 raw + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: SYSTIMER_INT_CLR. + addressOffset: 108 + size: 32 + fields: + - name: TARGET0_INT_CLR + description: interupt0 clear + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TARGET1_INT_CLR + description: interupt1 clear + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TARGET2_INT_CLR + description: interupt2 clear + bitOffset: 2 + bitWidth: 1 + access: write-only + - register: + name: INT_ST + description: SYSTIMER_INT_ST. + addressOffset: 112 + size: 32 + fields: + - name: TARGET0_INT_ST + description: reg_target0_int_st + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TARGET1_INT_ST + description: reg_target1_int_st + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TARGET2_INT_ST + description: reg_target2_int_st + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: SYSTIMER_DATE. + addressOffset: 252 + size: 32 + resetValue: 33579377 + fields: + - name: DATE + description: reg_date + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: TIMG0 + description: Timer Group 0 + groupName: TIMG + baseAddress: 1610739712 + addressBlock: + - offset: 0 + size: 104 + usage: registers + interrupt: + - name: TG0_T0_LEVEL + value: 32 + - name: TG0_WDT_LEVEL + value: 33 + registers: + - register: + name: T0CONFIG + description: TIMG_T0CONFIG_REG. + addressOffset: 0 + size: 32 + resetValue: 1610620928 + fields: + - name: USE_XTAL + description: reg_t0_use_xtal. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: ALARM_EN + description: reg_t0_alarm_en. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DIVCNT_RST + description: reg_t0_divcnt_rst. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: DIVIDER + description: reg_t0_divider. + bitOffset: 13 + bitWidth: 16 + access: read-write + - name: AUTORELOAD + description: reg_t0_autoreload. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: INCREASE + description: reg_t0_increase. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: EN + description: reg_t0_en. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: T0LO + description: TIMG_T0LO_REG. + addressOffset: 4 + size: 32 + fields: + - name: LO + description: t0_lo + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: T0HI + description: TIMG_T0HI_REG. + addressOffset: 8 + size: 32 + fields: + - name: HI + description: t0_hi + bitOffset: 0 + bitWidth: 22 + access: read-only + - register: + name: T0UPDATE + description: TIMG_T0UPDATE_REG. + addressOffset: 12 + size: 32 + fields: + - name: UPDATE + description: t0_update + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: T0ALARMLO + description: TIMG_T0ALARMLO_REG. + addressOffset: 16 + size: 32 + fields: + - name: ALARM_LO + description: reg_t0_alarm_lo. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: T0ALARMHI + description: TIMG_T0ALARMHI_REG. + addressOffset: 20 + size: 32 + fields: + - name: ALARM_HI + description: reg_t0_alarm_hi. + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: T0LOADLO + description: TIMG_T0LOADLO_REG. + addressOffset: 24 + size: 32 + fields: + - name: LOAD_LO + description: reg_t0_load_lo. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: T0LOADHI + description: TIMG_T0LOADHI_REG. + addressOffset: 28 + size: 32 + fields: + - name: LOAD_HI + description: reg_t0_load_hi. + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: T0LOAD + description: TIMG_T0LOAD_REG. + addressOffset: 32 + size: 32 + fields: + - name: LOAD + description: t0_load + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: WDTCONFIG0 + description: TIMG_WDTCONFIG0_REG. + addressOffset: 72 + size: 32 + resetValue: 311296 + fields: + - name: WDT_APPCPU_RESET_EN + description: reg_wdt_appcpu_reset_en. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: WDT_PROCPU_RESET_EN + description: reg_wdt_procpu_reset_en. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: WDT_FLASHBOOT_MOD_EN + description: reg_wdt_flashboot_mod_en. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: WDT_SYS_RESET_LENGTH + description: reg_wdt_sys_reset_length. + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: WDT_CPU_RESET_LENGTH + description: reg_wdt_cpu_reset_length. + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: WDT_USE_XTAL + description: reg_wdt_use_xtal. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: WDT_CONF_UPDATE_EN + description: reg_wdt_conf_update_en. + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: WDT_STG3 + description: reg_wdt_stg3. + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: WDT_STG2 + description: reg_wdt_stg2. + bitOffset: 25 + bitWidth: 2 + access: read-write + - name: WDT_STG1 + description: reg_wdt_stg1. + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: WDT_STG0 + description: reg_wdt_stg0. + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: WDT_EN + description: reg_wdt_en. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: WDTCONFIG1 + description: TIMG_WDTCONFIG1_REG. + addressOffset: 76 + size: 32 + resetValue: 65536 + fields: + - name: WDT_DIVCNT_RST + description: reg_wdt_divcnt_rst. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: WDT_CLK_PRESCALE + description: reg_wdt_clk_prescale. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: WDTCONFIG2 + description: TIMG_WDTCONFIG2_REG. + addressOffset: 80 + size: 32 + resetValue: 26000000 + fields: + - name: WDT_STG0_HOLD + description: reg_wdt_stg0_hold. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG3 + description: TIMG_WDTCONFIG3_REG. + addressOffset: 84 + size: 32 + resetValue: 134217727 + fields: + - name: WDT_STG1_HOLD + description: reg_wdt_stg1_hold. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG4 + description: TIMG_WDTCONFIG4_REG. + addressOffset: 88 + size: 32 + resetValue: 1048575 + fields: + - name: WDT_STG2_HOLD + description: reg_wdt_stg2_hold. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG5 + description: TIMG_WDTCONFIG5_REG. + addressOffset: 92 + size: 32 + resetValue: 1048575 + fields: + - name: WDT_STG3_HOLD + description: reg_wdt_stg3_hold. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTFEED + description: TIMG_WDTFEED_REG. + addressOffset: 96 + size: 32 + fields: + - name: WDT_FEED + description: wdt_feed + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: WDTWPROTECT + description: TIMG_WDTWPROTECT_REG. + addressOffset: 100 + size: 32 + resetValue: 1356348065 + fields: + - name: WDT_WKEY + description: reg_wdt_wkey. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RTCCALICFG + description: TIMG_RTCCALICFG_REG. + addressOffset: 104 + size: 32 + resetValue: 77824 + fields: + - name: RTC_CALI_START_CYCLING + description: reg_rtc_cali_start_cycling. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RTC_CALI_CLK_SEL + description: "reg_rtc_cali_clk_sel.0:rtcslowclock.1:clk_80m.2:xtal_32k" + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: RTC_CALI_RDY + description: rtc_cali_rdy + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: RTC_CALI_MAX + description: reg_rtc_cali_max. + bitOffset: 16 + bitWidth: 15 + access: read-write + - name: RTC_CALI_START + description: reg_rtc_cali_start. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RTCCALICFG1 + description: TIMG_RTCCALICFG1_REG. + addressOffset: 108 + size: 32 + fields: + - name: RTC_CALI_CYCLING_DATA_VLD + description: rtc_cali_cycling_data_vld + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RTC_CALI_VALUE + description: rtc_cali_value + bitOffset: 7 + bitWidth: 25 + access: read-only + - register: + name: INT_ENA_TIMERS + description: INT_ENA_TIMG_REG + addressOffset: 112 + size: 32 + fields: + - name: T0_INT_ENA + description: t0_int_ena + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: WDT_INT_ENA + description: wdt_int_ena + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW_TIMERS + description: INT_RAW_TIMG_REG + addressOffset: 116 + size: 32 + fields: + - name: T0_INT_RAW + description: t0_int_raw + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: WDT_INT_RAW + description: wdt_int_raw + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_ST_TIMERS + description: INT_ST_TIMG_REG + addressOffset: 120 + size: 32 + fields: + - name: T0_INT_ST + description: t0_int_st + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: WDT_INT_ST + description: wdt_int_st + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR_TIMERS + description: INT_CLR_TIMG_REG + addressOffset: 124 + size: 32 + fields: + - name: T0_INT_CLR + description: t0_int_clr + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: WDT_INT_CLR + description: wdt_int_clr + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: RTCCALICFG2 + description: TIMG_RTCCALICFG2_REG. + addressOffset: 128 + size: 32 + resetValue: 4294967192 + fields: + - name: RTC_CALI_TIMEOUT + description: timeoutindicator + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RTC_CALI_TIMEOUT_RST_CNT + description: reg_rtc_cali_timeout_rst_cnt.Cyclesthatreleasecalibrationtimeoutreset + bitOffset: 3 + bitWidth: 4 + access: read-write + - name: RTC_CALI_TIMEOUT_THRES + description: reg_rtc_cali_timeout_thres.timeoutifcalivaluecountsoverthreshold + bitOffset: 7 + bitWidth: 25 + access: read-write + - register: + name: NTIMG_DATE + description: TIMG_NTIMG_DATE_REG. + addressOffset: 248 + size: 32 + resetValue: 33579409 + fields: + - name: NTIMGS_DATE + description: reg_ntimers_date. + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + name: REGCLK + description: TIMG_REGCLK_REG. + addressOffset: 252 + size: 32 + resetValue: 1610612736 + fields: + - name: WDT_CLK_IS_ACTIVE + description: reg_wdt_clk_is_active. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TIMER_CLK_IS_ACTIVE + description: reg_timer_clk_is_active. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: reg_clk_en. + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: TIMG1 + description: Timer Group 1 + baseAddress: 1610743808 + interrupt: + - name: TG1_T0_LEVEL + value: 34 + - name: TG1_WDT_LEVEL + value: 35 + derivedFrom: TIMG0 + - name: TWAI0 + description: Two-Wire Automotive Interface + groupName: TWAI + baseAddress: 1610788864 + addressBlock: + - offset: 0 + size: 108 + usage: registers + interrupt: + - name: TWAI0 + value: 25 + registers: + - register: + name: MODE + description: Mode Register + addressOffset: 0 + size: 32 + resetValue: 1 + fields: + - name: RESET_MODE + description: "This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LISTEN_ONLY_MODE + description: "1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SELF_TEST_MODE + description: "1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_FILTER_MODE + description: "This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode." + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: CMD + description: Command Register + addressOffset: 4 + size: 32 + fields: + - name: TX_REQ + description: Set the bit to 1 to allow the driving nodes start transmission. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ABORT_TX + description: Set the bit to 1 to cancel a pending transmission request. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RELEASE_BUF + description: Set the bit to 1 to release the RX buffer. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CLR_OVERRUN + description: Set the bit to 1 to clear the data overrun status bit. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SELF_RX_REQ + description: Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously. + bitOffset: 4 + bitWidth: 1 + access: write-only + - register: + name: STATUS + description: Status register + addressOffset: 8 + size: 32 + fields: + - name: RX_BUF_ST + description: "1: The data in the RX buffer is not empty, with at least one received data packet." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OVERRUN_ST + description: "1: The RX FIFO is full and data overrun has occurred." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TX_BUF_ST + description: "1: The TX buffer is empty, the CPU may write a message into it." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_COMPLETE + description: "1: The TWAI controller has successfully received a packet from the bus." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: RX_ST + description: "1: The TWAI Controller is receiving a message from the bus." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TX_ST + description: "1: The TWAI Controller is transmitting a message to the bus." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ERR_ST + description: "1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG." + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BUS_OFF_ST + description: "1: In bus-off status, the TWAI Controller is no longer involved in bus activities." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: MISS_ST + description: "This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete" + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INT_RAW + description: Interrupt Register + addressOffset: 12 + size: 32 + fields: + - name: RX_INT_ST + description: "Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_INT_ST + description: "Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ERR_WARN_INT_ST + description: "Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0)." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: OVERRUN_INT_ST + description: "Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: ERR_PASSIVE_INT_ST + description: "Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ARB_LOST_INT_ST + description: "Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated." + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BUS_ERR_INT_ST + description: "Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus." + bitOffset: 7 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt Enable Register + addressOffset: 16 + size: 32 + fields: + - name: RX_INT_ENA + description: Set this bit to 1 to enable receive interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_INT_ENA + description: Set this bit to 1 to enable transmit interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ERR_WARN_INT_ENA + description: Set this bit to 1 to enable error warning interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OVERRUN_INT_ENA + description: Set this bit to 1 to enable data overrun interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ERR_PASSIVE_INT_ENA + description: Set this bit to 1 to enable error passive interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: ARB_LOST_INT_ENA + description: Set this bit to 1 to enable arbitration lost interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BUS_ERR_INT_ENA + description: Set this bit to 1 to enable error interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: BUS_TIMING_0 + description: Bus Timing Register 0 + addressOffset: 24 + size: 32 + fields: + - name: BAUD_PRESC + description: "Baud Rate Prescaler, determines the frequency dividing ratio." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: SYNC_JUMP_WIDTH + description: "Synchronization Jump Width (SJW), 1 \\verb+~+ 14 Tq wide." + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: BUS_TIMING_1 + description: Bus Timing Register 1 + addressOffset: 28 + size: 32 + fields: + - name: TIME_SEG1 + description: The width of PBS1. + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: TIME_SEG2 + description: The width of PBS2. + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: TIME_SAMP + description: "The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times" + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: ARB_LOST_CAP + description: Arbitration Lost Capture Register + addressOffset: 44 + size: 32 + fields: + - name: ARB_LOST_CAP + description: This register contains information about the bit position of lost arbitration. + bitOffset: 0 + bitWidth: 5 + access: read-only + - register: + name: ERR_CODE_CAP + description: Error Code Capture Register + addressOffset: 48 + size: 32 + fields: + - name: ECC_SEGMENT + description: "This register contains information about the location of errors, see Table 181 for details." + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: ECC_DIRECTION + description: "This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ECC_TYPE + description: "This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error" + bitOffset: 6 + bitWidth: 2 + access: read-only + - register: + name: ERR_WARNING_LIMIT + description: Error Warning Limit Register + addressOffset: 52 + size: 32 + resetValue: 96 + fields: + - name: ERR_WARNING_LIMIT + description: "Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid)." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: RX_ERR_CNT + description: Receive Error Counter Register + addressOffset: 56 + size: 32 + fields: + - name: RX_ERR_CNT + description: "The RX error counter register, reflects value changes under reception status." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: TX_ERR_CNT + description: Transmit Error Counter Register + addressOffset: 60 + size: 32 + fields: + - name: TX_ERR_CNT + description: "The TX error counter register, reflects value changes under transmission status." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_0 + description: Data register 0 + addressOffset: 64 + size: 32 + fields: + - name: TX_BYTE_0 + description: "In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_1 + description: Data register 1 + addressOffset: 68 + size: 32 + fields: + - name: TX_BYTE_1 + description: "In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_2 + description: Data register 2 + addressOffset: 72 + size: 32 + fields: + - name: TX_BYTE_2 + description: "In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_3 + description: Data register 3 + addressOffset: 76 + size: 32 + fields: + - name: TX_BYTE_3 + description: "In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_4 + description: Data register 4 + addressOffset: 80 + size: 32 + fields: + - name: TX_BYTE_4 + description: "In reset mode, it is acceptance code register 4 with R/W Permission. In operation mode, it stores the 4th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_5 + description: Data register 5 + addressOffset: 84 + size: 32 + fields: + - name: TX_BYTE_5 + description: "In reset mode, it is acceptance code register 5 with R/W Permission. In operation mode, it stores the 5th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_6 + description: Data register 6 + addressOffset: 88 + size: 32 + fields: + - name: TX_BYTE_6 + description: "In reset mode, it is acceptance code register 6 with R/W Permission. In operation mode, it stores the 6th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_7 + description: Data register 7 + addressOffset: 92 + size: 32 + fields: + - name: TX_BYTE_7 + description: "In reset mode, it is acceptance code register 7 with R/W Permission. In operation mode, it stores the 7th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_8 + description: Data register 8 + addressOffset: 96 + size: 32 + fields: + - name: TX_BYTE_8 + description: "In operation mode, it stores the 8th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_9 + description: Data register 9 + addressOffset: 100 + size: 32 + fields: + - name: TX_BYTE_9 + description: "In operation mode, it stores the 9th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_10 + description: Data register 10 + addressOffset: 104 + size: 32 + fields: + - name: TX_BYTE_10 + description: "In operation mode, it stores the 10th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_11 + description: Data register 11 + addressOffset: 108 + size: 32 + fields: + - name: TX_BYTE_11 + description: "In operation mode, it stores the 11th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_12 + description: Data register 12 + addressOffset: 112 + size: 32 + fields: + - name: TX_BYTE_12 + description: "In operation mode, it stores the 12th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: RX_MESSAGE_CNT + description: Receive Message Counter Register + addressOffset: 116 + size: 32 + fields: + - name: RX_MESSAGE_COUNTER + description: This register reflects the number of messages available within the RX FIFO. + bitOffset: 0 + bitWidth: 7 + access: read-only + - register: + name: CLOCK_DIVIDER + description: Clock Divider register + addressOffset: 124 + size: 32 + fields: + - name: CD + description: These bits are used to configure frequency dividing coefficients of the external CLKOUT pin. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CLOCK_OFF + description: "This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: UART0 + description: UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + groupName: UART + baseAddress: 1610612736 + addressBlock: + - offset: 0 + size: 132 + usage: registers + interrupt: + - name: UART0 + value: 21 + registers: + - register: + name: FIFO + description: FIFO data register + addressOffset: 0 + size: 32 + fields: + - name: RXFIFO_RD_BYTE + description: UART 0 accesses FIFO via this register. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 4 + size: 32 + resetValue: 2 + fields: + - name: RXFIFO_FULL_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_EMPTY_INT_RAW + description: This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PARITY_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a parity error in the data. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FRM_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a data frame error . + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DSR_CHG_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CTS_CHG_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BRK_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RXFIFO_TOUT_INT_RAW + description: This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SW_XON_INT_RAW + description: This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SW_XOFF_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GLITCH_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_BRK_DONE_INT_RAW + description: "This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_BRK_IDLE_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RS485_PARITY_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RS485_FRM_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RS485_CLASH_INT_RAW + description: This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: AT_CMD_CHAR_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: WAKEUP_INT_RAW + description: This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 8 + size: 32 + fields: + - name: RXFIFO_FULL_INT_ST + description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_EMPTY_INT_ST + description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: PARITY_ERR_INT_ST + description: This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FRM_ERR_INT_ST + description: This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_ST + description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DSR_CHG_INT_ST + description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CTS_CHG_INT_ST + description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BRK_DET_INT_ST + description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: RXFIFO_TOUT_INT_ST + description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SW_XON_INT_ST + description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SW_XOFF_INT_ST + description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: GLITCH_DET_INT_ST + description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TX_BRK_DONE_INT_ST + description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: TX_BRK_IDLE_DONE_INT_ST + description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_ST + description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: RS485_PARITY_ERR_INT_ST + description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: RS485_FRM_ERR_INT_ST + description: This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: RS485_CLASH_INT_ST + description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: AT_CMD_CHAR_DET_INT_ST + description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: WAKEUP_INT_ST + description: This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + bitOffset: 19 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 12 + size: 32 + fields: + - name: RXFIFO_FULL_INT_ENA + description: This is the enable bit for rxfifo_full_int_st register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_EMPTY_INT_ENA + description: This is the enable bit for txfifo_empty_int_st register. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PARITY_ERR_INT_ENA + description: This is the enable bit for parity_err_int_st register. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FRM_ERR_INT_ENA + description: This is the enable bit for frm_err_int_st register. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_ENA + description: This is the enable bit for rxfifo_ovf_int_st register. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DSR_CHG_INT_ENA + description: This is the enable bit for dsr_chg_int_st register. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CTS_CHG_INT_ENA + description: This is the enable bit for cts_chg_int_st register. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BRK_DET_INT_ENA + description: This is the enable bit for brk_det_int_st register. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RXFIFO_TOUT_INT_ENA + description: This is the enable bit for rxfifo_tout_int_st register. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SW_XON_INT_ENA + description: This is the enable bit for sw_xon_int_st register. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SW_XOFF_INT_ENA + description: This is the enable bit for sw_xoff_int_st register. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GLITCH_DET_INT_ENA + description: This is the enable bit for glitch_det_int_st register. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_BRK_DONE_INT_ENA + description: This is the enable bit for tx_brk_done_int_st register. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_BRK_IDLE_DONE_INT_ENA + description: This is the enable bit for tx_brk_idle_done_int_st register. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_ENA + description: This is the enable bit for tx_done_int_st register. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RS485_PARITY_ERR_INT_ENA + description: This is the enable bit for rs485_parity_err_int_st register. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RS485_FRM_ERR_INT_ENA + description: This is the enable bit for rs485_parity_err_int_st register. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RS485_CLASH_INT_ENA + description: This is the enable bit for rs485_clash_int_st register. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: AT_CMD_CHAR_DET_INT_ENA + description: This is the enable bit for at_cmd_char_det_int_st register. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: WAKEUP_INT_ENA + description: This is the enable bit for uart_wakeup_int_st register. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 16 + size: 32 + fields: + - name: RXFIFO_FULL_INT_CLR + description: Set this bit to clear the rxfifo_full_int_raw interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TXFIFO_EMPTY_INT_CLR + description: Set this bit to clear txfifo_empty_int_raw interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: PARITY_ERR_INT_CLR + description: Set this bit to clear parity_err_int_raw interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: FRM_ERR_INT_CLR + description: Set this bit to clear frm_err_int_raw interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: RXFIFO_OVF_INT_CLR + description: Set this bit to clear rxfifo_ovf_int_raw interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: DSR_CHG_INT_CLR + description: Set this bit to clear the dsr_chg_int_raw interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CTS_CHG_INT_CLR + description: Set this bit to clear the cts_chg_int_raw interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: BRK_DET_INT_CLR + description: Set this bit to clear the brk_det_int_raw interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: RXFIFO_TOUT_INT_CLR + description: Set this bit to clear the rxfifo_tout_int_raw interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SW_XON_INT_CLR + description: Set this bit to clear the sw_xon_int_raw interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SW_XOFF_INT_CLR + description: Set this bit to clear the sw_xoff_int_raw interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: GLITCH_DET_INT_CLR + description: Set this bit to clear the glitch_det_int_raw interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TX_BRK_DONE_INT_CLR + description: Set this bit to clear the tx_brk_done_int_raw interrupt.. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: TX_BRK_IDLE_DONE_INT_CLR + description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: TX_DONE_INT_CLR + description: Set this bit to clear the tx_done_int_raw interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: RS485_PARITY_ERR_INT_CLR + description: Set this bit to clear the rs485_parity_err_int_raw interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: RS485_FRM_ERR_INT_CLR + description: Set this bit to clear the rs485_frm_err_int_raw interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: RS485_CLASH_INT_CLR + description: Set this bit to clear the rs485_clash_int_raw interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: AT_CMD_CHAR_DET_INT_CLR + description: Set this bit to clear the at_cmd_char_det_int_raw interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: WAKEUP_INT_CLR + description: Set this bit to clear the uart_wakeup_int_raw interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - register: + name: CLKDIV + description: Clock divider configuration + addressOffset: 20 + size: 32 + resetValue: 694 + fields: + - name: CLKDIV + description: The integral part of the frequency divider factor. + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: FRAG + description: The decimal part of the frequency divider factor. + bitOffset: 20 + bitWidth: 4 + access: read-write + - register: + name: RX_FILT + description: Rx Filter configuration + addressOffset: 24 + size: 32 + resetValue: 8 + fields: + - name: GLITCH_FILT + description: "when input pulse width is lower than this value, the pulse is ignored." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GLITCH_FILT_EN + description: Set this bit to enable Rx signal filter. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: STATUS + description: UART status register + addressOffset: 28 + size: 32 + resetValue: 3758145536 + fields: + - name: RXFIFO_CNT + description: Stores the byte number of valid data in Rx-FIFO. + bitOffset: 0 + bitWidth: 10 + access: read-only + - name: DSRN + description: The register represent the level value of the internal uart dsr signal. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: CTSN + description: This register represent the level value of the internal uart cts signal. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: RXD + description: This register represent the level value of the internal uart rxd signal. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TXFIFO_CNT + description: Stores the byte number of data in Tx-FIFO. + bitOffset: 16 + bitWidth: 10 + access: read-only + - name: DTRN + description: This bit represents the level of the internal uart dtr signal. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: RTSN + description: This bit represents the level of the internal uart rts signal. + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: TXD + description: This bit represents the level of the internal uart txd signal. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CONF0 + description: a + addressOffset: 32 + size: 32 + resetValue: 268435484 + fields: + - name: PARITY + description: This register is used to configure the parity check mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PARITY_EN + description: Set this bit to enable uart parity check. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BIT_NUM + description: This register is used to set the length of data. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: STOP_BIT_NUM + description: This register is used to set the length of stop bit. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: SW_RTS + description: This register is used to configure the software rts signal which is used in software flow control. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SW_DTR + description: This register is used to configure the software dtr signal which is used in software flow control. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TXD_BRK + description: Set this bit to enbale transmitter to send NULL when the process of sending data is done. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: IRDA_DPLX + description: Set this bit to enable IrDA loopback mode. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: IRDA_TX_EN + description: This is the start enable bit for IrDA transmitter. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: IRDA_WCTL + description: "1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: IRDA_TX_INV + description: Set this bit to invert the level of IrDA transmitter. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: IRDA_RX_INV + description: Set this bit to invert the level of IrDA receiver. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: LOOPBACK + description: Set this bit to enable uart loopback test mode. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TX_FLOW_EN + description: Set this bit to enable flow control function for transmitter. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: IRDA_EN + description: Set this bit to enable IrDA protocol. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RXFIFO_RST + description: Set this bit to reset the uart receive-FIFO. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: TXFIFO_RST + description: Set this bit to reset the uart transmit-FIFO. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RXD_INV + description: Set this bit to inverse the level value of uart rxd signal. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: CTS_INV + description: Set this bit to inverse the level value of uart cts signal. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: DSR_INV + description: Set this bit to inverse the level value of uart dsr signal. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: TXD_INV + description: Set this bit to inverse the level value of uart txd signal. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RTS_INV + description: Set this bit to inverse the level value of uart rts signal. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: DTR_INV + description: Set this bit to inverse the level value of uart dtr signal. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: ERR_WR_MASK + description: "1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: AUTOBAUD_EN + description: This is the enable bit for detecting baudrate. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: MEM_CLK_EN + description: UART memory clock gate enable signal. + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: CONF1 + description: Configuration register 1 + addressOffset: 36 + size: 32 + resetValue: 49248 + fields: + - name: RXFIFO_FULL_THRHD + description: It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: TXFIFO_EMPTY_THRHD + description: It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + bitOffset: 9 + bitWidth: 9 + access: read-write + - name: DIS_RX_DAT_OVF + description: Disable UART Rx data overflow detect. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RX_TOUT_FLOW_DIS + description: Set this bit to stop accumulating idle_cnt when hardware flow control works. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RX_FLOW_EN + description: This is the flow enable bit for UART receiver. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: RX_TOUT_EN + description: "This is the enble bit for uart receiver's timeout function." + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + name: LOWPULSE + description: Autobaud minimum low pulse duration register + addressOffset: 40 + size: 32 + resetValue: 4095 + fields: + - name: MIN_CNT + description: This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process. + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: HIGHPULSE + description: Autobaud minimum high pulse duration register + addressOffset: 44 + size: 32 + resetValue: 4095 + fields: + - name: MIN_CNT + description: This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process. + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: RXD_CNT + description: Autobaud edge change count register + addressOffset: 48 + size: 32 + fields: + - name: RXD_EDGE_CNT + description: This register stores the count of rxd edge change. It is used in baud rate-detect process. + bitOffset: 0 + bitWidth: 10 + access: read-only + - register: + name: FLOW_CONF + description: Software flow-control configuration + addressOffset: 52 + size: 32 + fields: + - name: SW_FLOW_CON_EN + description: Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: XONOFF_DEL + description: Set this bit to remove flow control char from the received data. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FORCE_XON + description: Set this bit to enable the transmitter to go on sending data. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FORCE_XOFF + description: Set this bit to stop the transmitter from sending data. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SEND_XON + description: Set this bit to send Xon char. It is cleared by hardware automatically. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SEND_XOFF + description: Set this bit to send Xoff char. It is cleared by hardware automatically. + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: SLEEP_CONF + description: Sleep-mode configuration + addressOffset: 56 + size: 32 + resetValue: 240 + fields: + - name: ACTIVE_THRESHOLD + description: The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: SWFC_CONF0 + description: Software flow-control character configuration + addressOffset: 60 + size: 32 + resetValue: 9952 + fields: + - name: XOFF_THRESHOLD + description: "When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: XOFF_CHAR + description: This register stores the Xoff flow control char. + bitOffset: 9 + bitWidth: 8 + access: read-write + - register: + name: SWFC_CONF1 + description: Software flow-control character configuration + addressOffset: 64 + size: 32 + resetValue: 8704 + fields: + - name: XON_THRESHOLD + description: "When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: XON_CHAR + description: This register stores the Xon flow control char. + bitOffset: 9 + bitWidth: 8 + access: read-write + - register: + name: TXBRK_CONF + description: Tx Break character configuration + addressOffset: 68 + size: 32 + resetValue: 10 + fields: + - name: TX_BRK_NUM + description: This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: IDLE_CONF + description: Frame-end idle configuration + addressOffset: 72 + size: 32 + resetValue: 262400 + fields: + - name: RX_IDLE_THRHD + description: It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: TX_IDLE_NUM + description: This register is used to configure the duration time between transfers. + bitOffset: 10 + bitWidth: 10 + access: read-write + - register: + name: RS485_CONF + description: RS485 mode configuration + addressOffset: 76 + size: 32 + fields: + - name: RS485_EN + description: Set this bit to choose the rs485 mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DL0_EN + description: Set this bit to delay the stop bit by 1 bit. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DL1_EN + description: Set this bit to delay the stop bit by 1 bit. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RS485TX_RX_EN + description: Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RS485RXBY_TX_EN + description: "1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RS485_RX_DLY_NUM + description: "This register is used to delay the receiver's internal data signal." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RS485_TX_DLY_NUM + description: "This register is used to delay the transmitter's internal data signal." + bitOffset: 6 + bitWidth: 4 + access: read-write + - register: + name: AT_CMD_PRECNT + description: Pre-sequence timing configuration + addressOffset: 80 + size: 32 + resetValue: 2305 + fields: + - name: PRE_IDLE_NUM + description: This register is used to configure the idle duration time before the first at_cmd is received by receiver. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_POSTCNT + description: Post-sequence timing configuration + addressOffset: 84 + size: 32 + resetValue: 2305 + fields: + - name: POST_IDLE_NUM + description: This register is used to configure the duration time between the last at_cmd and the next data. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_GAPTOUT + description: Timeout configuration + addressOffset: 88 + size: 32 + resetValue: 11 + fields: + - name: RX_GAP_TOUT + description: This register is used to configure the duration time between the at_cmd chars. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_CHAR + description: AT escape sequence detection configuration + addressOffset: 92 + size: 32 + resetValue: 811 + fields: + - name: AT_CMD_CHAR + description: This register is used to configure the content of at_cmd char. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CHAR_NUM + description: This register is used to configure the num of continuous at_cmd chars received by receiver. + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: MEM_CONF + description: UART threshold and allocation configuration + addressOffset: 96 + size: 32 + resetValue: 655378 + fields: + - name: RX_SIZE + description: This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: TX_SIZE + description: This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes. + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: RX_FLOW_THRHD + description: This register is used to configure the maximum amount of data that can be received when hardware flow control works. + bitOffset: 7 + bitWidth: 9 + access: read-write + - name: RX_TOUT_THRHD + description: This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + bitOffset: 16 + bitWidth: 10 + access: read-write + - name: MEM_FORCE_PD + description: Set this bit to force power down UART memory. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PU + description: Set this bit to force power up UART memory. + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: MEM_TX_STATUS + description: Tx-FIFO write and read offset address. + addressOffset: 100 + size: 32 + fields: + - name: APB_TX_WADDR + description: This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB. + bitOffset: 0 + bitWidth: 10 + access: read-only + - name: TX_RADDR + description: This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl. + bitOffset: 11 + bitWidth: 10 + access: read-only + - register: + name: MEM_RX_STATUS + description: Rx-FIFO write and read offset address. + addressOffset: 104 + size: 32 + resetValue: 524544 + fields: + - name: APB_RX_RADDR + description: "This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180." + bitOffset: 0 + bitWidth: 10 + access: read-only + - name: RX_WADDR + description: "This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180." + bitOffset: 11 + bitWidth: 10 + access: read-only + - register: + name: FSM_STATUS + description: UART transmit and receive status. + addressOffset: 108 + size: 32 + fields: + - name: ST_URX_OUT + description: This is the status register of receiver. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: ST_UTX_OUT + description: This is the status register of transmitter. + bitOffset: 4 + bitWidth: 4 + access: read-only + - register: + name: POSPULSE + description: Autobaud high pulse register + addressOffset: 112 + size: 32 + resetValue: 4095 + fields: + - name: POSEDGE_MIN_CNT + description: This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process. + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: NEGPULSE + description: Autobaud low pulse register + addressOffset: 116 + size: 32 + resetValue: 4095 + fields: + - name: NEGEDGE_MIN_CNT + description: This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process. + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: CLK_CONF + description: UART core clock configuration + addressOffset: 120 + size: 32 + resetValue: 57675776 + fields: + - name: SCLK_DIV_B + description: The denominator of the frequency divider factor. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_A + description: The numerator of the frequency divider factor. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_NUM + description: The integral part of the frequency divider factor. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: SCLK_SEL + description: "UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: SCLK_EN + description: Set this bit to enable UART Tx/Rx clock. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RST_CORE + description: "Write 1 then write 0 to this bit, reset UART Tx/Rx." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TX_SCLK_EN + description: Set this bit to enable UART Tx clock. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: RX_SCLK_EN + description: Set this bit to enable UART Rx clock. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TX_RST_CORE + description: "Write 1 then write 0 to this bit, reset UART Tx." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RX_RST_CORE + description: "Write 1 then write 0 to this bit, reset UART Rx." + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: UART Version register + addressOffset: 124 + size: 32 + resetValue: 33587824 + fields: + - name: DATE + description: This is the version register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ID + description: UART ID register + addressOffset: 128 + size: 32 + resetValue: 1073743104 + fields: + - name: ID + description: This register is used to configure the uart_id. + bitOffset: 0 + bitWidth: 30 + access: read-write + - name: HIGH_SPEED + description: "This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: REG_UPDATE + description: Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: UART1 + description: UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + baseAddress: 1610678272 + interrupt: + - name: UART1 + value: 22 + derivedFrom: UART0 + - name: UHCI0 + description: Universal Host Controller Interface 0 + groupName: UHCI + baseAddress: 1610694656 + addressBlock: + - offset: 0 + size: 132 + usage: registers + interrupt: + - name: UHCI0 + value: 15 + registers: + - register: + name: CONF0 + description: a + addressOffset: 0 + size: 32 + resetValue: 1760 + fields: + - name: TX_RST + description: "Write 1, then write 0 to this bit to reset decode state machine." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_RST + description: "Write 1, then write 0 to this bit to reset encode state machine." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UART0_CE + description: Set this bit to link up HCI and UART0. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: UART1_CE + description: Set this bit to link up HCI and UART1. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SEPER_EN + description: Set this bit to separate the data frame using a special char. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: HEAD_EN + description: Set this bit to encode the data packet with a formatting header. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CRC_REC_EN + description: Set this bit to enable UHCI to receive the 16 bit CRC. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: UART_IDLE_EOF_EN + description: "If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: LEN_EOF_EN + description: "If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: ENCODE_CRC_EN + description: Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: UART_RX_BRK_EOF_EN + description: "If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART." + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: a + addressOffset: 4 + size: 32 + fields: + - name: RX_START_INT_RAW + description: a + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_START_INT_RAW + description: a + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_HUNG_INT_RAW + description: a + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_HUNG_INT_RAW + description: a + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SEND_S_REG_Q_INT_RAW + description: a + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SEND_A_REG_Q_INT_RAW + description: a + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUT_EOF_INT_RAW + description: This is the interrupt raw bit. Triggered when there are some errors in EOF in the + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: APP_CTRL0_INT_RAW + description: Soft control int raw bit. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: APP_CTRL1_INT_RAW + description: Soft control int raw bit. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: a + addressOffset: 8 + size: 32 + fields: + - name: RX_START_INT_ST + description: a + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_START_INT_ST + description: a + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_ST + description: a + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_ST + description: a + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SEND_S_REG_Q_INT_ST + description: a + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SEND_A_REG_Q_INT_ST + description: a + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OUTLINK_EOF_ERR_INT_ST + description: a + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: APP_CTRL0_INT_ST + description: a + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: APP_CTRL1_INT_ST + description: a + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: a + addressOffset: 12 + size: 32 + fields: + - name: RX_START_INT_ENA + description: a + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_START_INT_ENA + description: a + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_HUNG_INT_ENA + description: a + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_HUNG_INT_ENA + description: a + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SEND_S_REG_Q_INT_ENA + description: a + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SEND_A_REG_Q_INT_ENA + description: a + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUTLINK_EOF_ERR_INT_ENA + description: a + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: APP_CTRL0_INT_ENA + description: a + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: APP_CTRL1_INT_ENA + description: a + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: a + addressOffset: 16 + size: 32 + fields: + - name: RX_START_INT_CLR + description: a + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TX_START_INT_CLR + description: a + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_HUNG_INT_CLR + description: a + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TX_HUNG_INT_CLR + description: a + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SEND_S_REG_Q_INT_CLR + description: a + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SEND_A_REG_Q_INT_CLR + description: a + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: OUTLINK_EOF_ERR_INT_CLR + description: a + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: APP_CTRL0_INT_CLR + description: a + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: APP_CTRL1_INT_CLR + description: a + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: CONF1 + description: a + addressOffset: 20 + size: 32 + resetValue: 51 + fields: + - name: CHECK_SUM_EN + description: a + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CHECK_SEQ_EN + description: a + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CRC_DISABLE + description: a + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SAVE_HEAD + description: a + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_CHECK_SUM_RE + description: a + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TX_ACK_NUM_RE + description: a + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: WAIT_SW_START + description: a + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SW_START + description: a + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: STATE0 + description: a + addressOffset: 24 + size: 32 + fields: + - name: RX_ERR_CAUSE + description: a + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: DECODE_STATE + description: a + bitOffset: 3 + bitWidth: 3 + access: read-only + - register: + name: STATE1 + description: a + addressOffset: 28 + size: 32 + fields: + - name: ENCODE_STATE + description: a + bitOffset: 0 + bitWidth: 3 + access: read-only + - register: + name: ESCAPE_CONF + description: a + addressOffset: 32 + size: 32 + resetValue: 51 + fields: + - name: TX_C0_ESC_EN + description: a + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_DB_ESC_EN + description: a + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TX_11_ESC_EN + description: a + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_13_ESC_EN + description: a + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_C0_ESC_EN + description: a + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_DB_ESC_EN + description: a + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RX_11_ESC_EN + description: a + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_13_ESC_EN + description: a + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: HUNG_CONF + description: a + addressOffset: 36 + size: 32 + resetValue: 8456208 + fields: + - name: TXFIFO_TIMEOUT + description: a + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TXFIFO_TIMEOUT_SHIFT + description: a + bitOffset: 8 + bitWidth: 3 + access: read-write + - name: TXFIFO_TIMEOUT_ENA + description: a + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RXFIFO_TIMEOUT + description: a + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: RXFIFO_TIMEOUT_SHIFT + description: a + bitOffset: 20 + bitWidth: 3 + access: read-write + - name: RXFIFO_TIMEOUT_ENA + description: a + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: ACK_NUM + description: a + addressOffset: 40 + size: 32 + resetValue: 8 + fields: + - name: ACK_NUM + description: a + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: LOAD + description: a + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: RX_HEAD + description: a + addressOffset: 44 + size: 32 + fields: + - name: RX_HEAD + description: a + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: QUICK_SENT + description: a + addressOffset: 48 + size: 32 + fields: + - name: SINGLE_SEND_NUM + description: a + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SINGLE_SEND_EN + description: a + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ALWAYS_SEND_NUM + description: a + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: ALWAYS_SEND_EN + description: a + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: REG_Q0_WORD0 + description: a + addressOffset: 52 + size: 32 + fields: + - name: SEND_Q0_WORD0 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q0_WORD1 + description: a + addressOffset: 56 + size: 32 + fields: + - name: SEND_Q0_WORD1 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q1_WORD0 + description: a + addressOffset: 60 + size: 32 + fields: + - name: SEND_Q1_WORD0 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q1_WORD1 + description: a + addressOffset: 64 + size: 32 + fields: + - name: SEND_Q1_WORD1 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q2_WORD0 + description: a + addressOffset: 68 + size: 32 + fields: + - name: SEND_Q2_WORD0 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q2_WORD1 + description: a + addressOffset: 72 + size: 32 + fields: + - name: SEND_Q2_WORD1 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q3_WORD0 + description: a + addressOffset: 76 + size: 32 + fields: + - name: SEND_Q3_WORD0 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q3_WORD1 + description: a + addressOffset: 80 + size: 32 + fields: + - name: SEND_Q3_WORD1 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q4_WORD0 + description: a + addressOffset: 84 + size: 32 + fields: + - name: SEND_Q4_WORD0 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q4_WORD1 + description: a + addressOffset: 88 + size: 32 + fields: + - name: SEND_Q4_WORD1 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q5_WORD0 + description: a + addressOffset: 92 + size: 32 + fields: + - name: SEND_Q5_WORD0 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q5_WORD1 + description: a + addressOffset: 96 + size: 32 + fields: + - name: SEND_Q5_WORD1 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q6_WORD0 + description: a + addressOffset: 100 + size: 32 + fields: + - name: SEND_Q6_WORD0 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q6_WORD1 + description: a + addressOffset: 104 + size: 32 + fields: + - name: SEND_Q6_WORD1 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ESC_CONF0 + description: a + addressOffset: 108 + size: 32 + resetValue: 14474176 + fields: + - name: SEPER_CHAR + description: a + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SEPER_ESC_CHAR0 + description: a + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SEPER_ESC_CHAR1 + description: a + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: ESC_CONF1 + description: a + addressOffset: 112 + size: 32 + resetValue: 14539739 + fields: + - name: ESC_SEQ0 + description: a + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: ESC_SEQ0_CHAR0 + description: a + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: ESC_SEQ0_CHAR1 + description: a + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: ESC_CONF2 + description: a + addressOffset: 116 + size: 32 + resetValue: 14605073 + fields: + - name: ESC_SEQ1 + description: a + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: ESC_SEQ1_CHAR0 + description: a + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: ESC_SEQ1_CHAR1 + description: a + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: ESC_CONF3 + description: a + addressOffset: 120 + size: 32 + resetValue: 14670611 + fields: + - name: ESC_SEQ2 + description: a + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: ESC_SEQ2_CHAR0 + description: a + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: ESC_SEQ2_CHAR1 + description: a + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: PKT_THRES + description: a + addressOffset: 124 + size: 32 + resetValue: 128 + fields: + - name: PKT_THRS + description: a + bitOffset: 0 + bitWidth: 13 + access: read-write + - register: + name: DATE + description: a + addressOffset: 128 + size: 32 + resetValue: 33583472 + fields: + - name: DATE + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: UHCI1 + description: Universal Host Controller Interface 1 + baseAddress: 1610661888 + derivedFrom: UHCI0 + - name: USB_DEVICE + description: Full-speed USB Serial/JTAG Controller + groupName: USB_DEVICE + baseAddress: 1610887168 + addressBlock: + - offset: 0 + size: 80 + usage: registers + interrupt: + - name: USB_DEVICE + value: 26 + registers: + - register: + name: EP1 + description: USB_DEVICE_EP1_REG. + addressOffset: 0 + size: 32 + fields: + - name: RDWR_BYTE + description: "Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: EP1_CONF + description: USB_DEVICE_EP1_CONF_REG. + addressOffset: 4 + size: 32 + resetValue: 2 + fields: + - name: WR_DONE + description: Set this bit to indicate writing byte data to UART Tx FIFO is done. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SERIAL_IN_EP_DATA_FREE + description: "1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SERIAL_OUT_EP_DATA_AVAIL + description: "1'b1: Indicate there is data in UART Rx FIFO." + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: INT_RAW + description: USB_DEVICE_INT_RAW_REG. + addressOffset: 8 + size: 32 + resetValue: 8 + fields: + - name: JTAG_IN_FLUSH_INT_RAW + description: The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SOF_INT_RAW + description: The raw interrupt bit turns to high level when SOF frame is received. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SERIAL_OUT_RECV_PKT_INT_RAW + description: The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SERIAL_IN_EMPTY_INT_RAW + description: The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PID_ERR_INT_RAW + description: The raw interrupt bit turns to high level when pid error is detected. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CRC5_ERR_INT_RAW + description: The raw interrupt bit turns to high level when CRC5 error is detected. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CRC16_ERR_INT_RAW + description: The raw interrupt bit turns to high level when CRC16 error is detected. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: STUFF_ERR_INT_RAW + description: The raw interrupt bit turns to high level when stuff error is detected. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IN_TOKEN_REC_IN_EP1_INT_RAW + description: The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: USB_BUS_RESET_INT_RAW + description: The raw interrupt bit turns to high level when usb bus reset is detected. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OUT_EP1_ZERO_PAYLOAD_INT_RAW + description: The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OUT_EP2_ZERO_PAYLOAD_INT_RAW + description: The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload. + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: USB_DEVICE_INT_ST_REG. + addressOffset: 12 + size: 32 + fields: + - name: JTAG_IN_FLUSH_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SOF_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SERIAL_OUT_RECV_PKT_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SERIAL_IN_EMPTY_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: PID_ERR_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: CRC5_ERR_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CRC16_ERR_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: STUFF_ERR_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IN_TOKEN_REC_IN_EP1_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: USB_BUS_RESET_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: OUT_EP1_ZERO_PAYLOAD_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: OUT_EP2_ZERO_PAYLOAD_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: USB_DEVICE_INT_ENA_REG. + addressOffset: 16 + size: 32 + fields: + - name: JTAG_IN_FLUSH_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SOF_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SERIAL_OUT_RECV_PKT_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SERIAL_IN_EMPTY_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PID_ERR_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CRC5_ERR_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CRC16_ERR_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: STUFF_ERR_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IN_TOKEN_REC_IN_EP1_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: USB_BUS_RESET_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OUT_EP1_ZERO_PAYLOAD_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OUT_EP2_ZERO_PAYLOAD_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: USB_DEVICE_INT_CLR_REG. + addressOffset: 20 + size: 32 + fields: + - name: JTAG_IN_FLUSH_INT_CLR + description: Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SOF_INT_CLR + description: Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SERIAL_OUT_RECV_PKT_INT_CLR + description: Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SERIAL_IN_EMPTY_INT_CLR + description: Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: PID_ERR_INT_CLR + description: Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: CRC5_ERR_INT_CLR + description: Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CRC16_ERR_INT_CLR + description: Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: STUFF_ERR_INT_CLR + description: Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: IN_TOKEN_REC_IN_EP1_INT_CLR + description: Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: USB_BUS_RESET_INT_CLR + description: Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: OUT_EP1_ZERO_PAYLOAD_INT_CLR + description: Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: OUT_EP2_ZERO_PAYLOAD_INT_CLR + description: Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - register: + name: CONF0 + description: USB_DEVICE_CONF0_REG. + addressOffset: 24 + size: 32 + resetValue: 16896 + fields: + - name: PHY_SEL + description: Select internal/external PHY + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EXCHG_PINS_OVERRIDE + description: Enable software control USB D+ D- exchange + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EXCHG_PINS + description: USB D+ D- exchange + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: VREFH + description: "Control single-end input high threshold,1.76V to 2V, step 80mV" + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: VREFL + description: "Control single-end input low threshold,0.8V to 1.04V, step 80mV" + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: VREF_OVERRIDE + description: Enable software control input threshold + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: PAD_PULL_OVERRIDE + description: Enable software control USB D+ D- pullup pulldown + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DP_PULLUP + description: Control USB D+ pull up. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DP_PULLDOWN + description: Control USB D+ pull down. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DM_PULLUP + description: Control USB D- pull up. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DM_PULLDOWN + description: Control USB D- pull down. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PULLUP_VALUE + description: Control pull up value. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: USB_PAD_ENABLE + description: Enable USB pad function. + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: TEST + description: USB_DEVICE_TEST_REG. + addressOffset: 28 + size: 32 + fields: + - name: ENABLE + description: Enable test of the USB pad + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: USB_OE + description: USB pad oen in test + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TX_DP + description: USB D+ tx value in test + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_DM + description: USB D- tx value in test + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: JFIFO_ST + description: USB_DEVICE_JFIFO_ST_REG. + addressOffset: 32 + size: 32 + resetValue: 68 + fields: + - name: IN_FIFO_CNT + description: JTAT in fifo counter. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_FIFO_EMPTY + description: "1: JTAG in fifo is empty." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: IN_FIFO_FULL + description: "1: JTAG in fifo is full." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: OUT_FIFO_CNT + description: JTAT out fifo counter. + bitOffset: 4 + bitWidth: 2 + access: read-only + - name: OUT_FIFO_EMPTY + description: "1: JTAG out fifo is empty." + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUT_FIFO_FULL + description: "1: JTAG out fifo is full." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IN_FIFO_RESET + description: Write 1 to reset JTAG in fifo. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: OUT_FIFO_RESET + description: Write 1 to reset JTAG out fifo. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: FRAM_NUM + description: USB_DEVICE_FRAM_NUM_REG. + addressOffset: 36 + size: 32 + fields: + - name: SOF_FRAME_INDEX + description: Frame index of received SOF frame. + bitOffset: 0 + bitWidth: 11 + access: read-only + - register: + name: IN_EP0_ST + description: USB_DEVICE_IN_EP0_ST_REG. + addressOffset: 40 + size: 32 + resetValue: 1 + fields: + - name: IN_EP0_STATE + description: State of IN Endpoint 0. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_EP0_WR_ADDR + description: Write data address of IN endpoint 0. + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: IN_EP0_RD_ADDR + description: Read data address of IN endpoint 0. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: IN_EP1_ST + description: USB_DEVICE_IN_EP1_ST_REG. + addressOffset: 44 + size: 32 + resetValue: 1 + fields: + - name: IN_EP1_STATE + description: State of IN Endpoint 1. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_EP1_WR_ADDR + description: Write data address of IN endpoint 1. + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: IN_EP1_RD_ADDR + description: Read data address of IN endpoint 1. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: IN_EP2_ST + description: USB_DEVICE_IN_EP2_ST_REG. + addressOffset: 48 + size: 32 + resetValue: 1 + fields: + - name: IN_EP2_STATE + description: State of IN Endpoint 2. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_EP2_WR_ADDR + description: Write data address of IN endpoint 2. + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: IN_EP2_RD_ADDR + description: Read data address of IN endpoint 2. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: IN_EP3_ST + description: USB_DEVICE_IN_EP3_ST_REG. + addressOffset: 52 + size: 32 + resetValue: 1 + fields: + - name: IN_EP3_STATE + description: State of IN Endpoint 3. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_EP3_WR_ADDR + description: Write data address of IN endpoint 3. + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: IN_EP3_RD_ADDR + description: Read data address of IN endpoint 3. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: OUT_EP0_ST + description: USB_DEVICE_OUT_EP0_ST_REG. + addressOffset: 56 + size: 32 + fields: + - name: OUT_EP0_STATE + description: State of OUT Endpoint 0. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: OUT_EP0_WR_ADDR + description: "Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0." + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: OUT_EP0_RD_ADDR + description: Read data address of OUT endpoint 0. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: OUT_EP1_ST + description: USB_DEVICE_OUT_EP1_ST_REG. + addressOffset: 60 + size: 32 + fields: + - name: OUT_EP1_STATE + description: State of OUT Endpoint 1. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: OUT_EP1_WR_ADDR + description: "Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1." + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: OUT_EP1_RD_ADDR + description: Read data address of OUT endpoint 1. + bitOffset: 9 + bitWidth: 7 + access: read-only + - name: OUT_EP1_REC_DATA_CNT + description: Data count in OUT endpoint 1 when one packet is received. + bitOffset: 16 + bitWidth: 7 + access: read-only + - register: + name: OUT_EP2_ST + description: USB_DEVICE_OUT_EP2_ST_REG. + addressOffset: 64 + size: 32 + fields: + - name: OUT_EP2_STATE + description: State of OUT Endpoint 2. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: OUT_EP2_WR_ADDR + description: "Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2." + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: OUT_EP2_RD_ADDR + description: Read data address of OUT endpoint 2. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: MISC_CONF + description: USB_DEVICE_MISC_CONF_REG. + addressOffset: 68 + size: 32 + fields: + - name: CLK_EN + description: "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: MEM_CONF + description: USB_DEVICE_MEM_CONF_REG. + addressOffset: 72 + size: 32 + resetValue: 2 + fields: + - name: USB_MEM_PD + description: "1: power down usb memory." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: USB_MEM_CLK_EN + description: "1: Force clock on for usb memory." + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: USB_DEVICE_DATE_REG. + addressOffset: 128 + size: 32 + resetValue: 33583872 + fields: + - name: DATE + description: register version. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: XTS_AES + description: XTS-AES-128 Flash Encryption + groupName: XTS_AES + baseAddress: 1611448320 + addressBlock: + - offset: 0 + size: 48 + usage: registers + registers: + - register: + dim: 4 + dimIncrement: 4 + name: "PLAIN_MEM[%s]" + description: The memory that stores plaintext + addressOffset: 0 + size: 32 + - register: + name: LINESIZE + description: XTS-AES line-size register + addressOffset: 64 + size: 32 + fields: + - name: LINESIZE + description: "This bit stores the line size parameter. 0: 16Byte, 1: 32Byte." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DESTINATION + description: XTS-AES destination register + addressOffset: 68 + size: 32 + fields: + - name: DESTINATION + description: "This bit stores the destination. 0: flash(default). 1: reserved." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: PHYSICAL_ADDRESS + description: XTS-AES physical address register + addressOffset: 72 + size: 32 + fields: + - name: PHYSICAL_ADDRESS + description: "Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes." + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: TRIGGER + description: XTS-AES trigger register + addressOffset: 76 + size: 32 + fields: + - name: TRIGGER + description: Set this bit to start manual encryption calculation + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: RELEASE + description: XTS-AES release register + addressOffset: 80 + size: 32 + fields: + - name: RELEASE + description: "Set this bit to release the manual encrypted result, after that the result will be visible to spi" + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: DESTROY + description: XTS-AES destroy register + addressOffset: 84 + size: 32 + fields: + - name: DESTROY + description: Set this bit to destroy XTS-AES result. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: STATE + description: XTS-AES status register + addressOffset: 88 + size: 32 + fields: + - name: STATE + description: "Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means the encrypted result is generated but not visible to mspi. USE means that the encrypted result is visible to mspi." + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: DATE + description: XTS-AES version control register + addressOffset: 92 + size: 32 + resetValue: 538969635 + fields: + - name: DATE + description: Those bits stores the version information of XTS-AES. + bitOffset: 0 + bitWidth: 30 + access: read-write diff --git a/esp32c6-lp/svd/esp32c6-lp.svd.yaml b/esp32c6-lp/svd/esp32c6-lp.svd.yaml new file mode 100644 index 0000000000..0694a2fde1 --- /dev/null +++ b/esp32c6-lp/svd/esp32c6-lp.svd.yaml @@ -0,0 +1,4582 @@ +--- +vendor: "ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD." +vendorID: ESPRESSIF +name: ESP32-C6-LP +series: ESP32 Series +version: "2" +description: 32-bit RISC-V MCU +licenseText: "Copyright 2024 Espressif Systems (Shanghai) PTE LTD\n\n Licensed under the Apache License, Version 2.0 (the \"License\");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an \"AS IS\" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License." +cpu: + name: RV32IMAC + revision: r0p0 + endian: little + mpuPresent: false + fpuPresent: false + nvicPrioBits: 0 + vendorSystickConfig: false +addressUnitBits: 32 +width: 32 +resetValue: 0 +resetMask: 4294967295 +peripherals: + - name: LP_I2C0 + description: Low-power I2C (Inter-Integrated Circuit) Controller 0 + groupName: I2C + baseAddress: 1611339776 + addressBlock: + - offset: 0 + size: 136 + usage: registers + interrupt: + - name: LP_I2C + value: 17 + registers: + - register: + name: SCL_LOW_PERIOD + description: "Configures the low level width of the SCL\nClock" + addressOffset: 0 + size: 32 + fields: + - name: SCL_LOW_PERIOD + description: "This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: CTR + description: Transmission setting + addressOffset: 4 + size: 32 + resetValue: 520 + fields: + - name: SDA_FORCE_OUT + description: "1: direct output, 0: open drain output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_FORCE_OUT + description: "1: direct output, 0: open drain output." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SAMPLE_SCL_LEVEL + description: "This register is used to select the sample mode.\n1: sample SDA data on the SCL low level.\n0: sample SDA data on the SCL high level." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_FULL_ACK_LEVEL + description: This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TRANS_START + description: Set this bit to start sending the data in txfifo. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TX_LSB_FIRST + description: "This bit is used to control the sending mode for data needing to be sent. \n1: send data from the least significant bit,\n0: send data from the most significant bit." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_LSB_FIRST + description: "This bit is used to control the storage mode for received data.\n1: receive data from the least significant bit,\n0: receive data from the most significant bit." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ARBITRATION_EN + description: This is the enable bit for arbitration_lost. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FSM_RST + description: This register is used to reset the scl FMS. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: CONF_UPGATE + description: synchronization bit + bitOffset: 11 + bitWidth: 1 + access: write-only + - register: + name: SR + description: Describe I2C work status. + addressOffset: 8 + size: 32 + fields: + - name: RESP_REC + description: "The received ACK value in master mode or slave mode. 0: ACK, 1: NACK." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ARB_LOST + description: "When the I2C controller loses control of SCL line, this register changes to 1." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BUS_BUSY + description: "1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: RXFIFO_CNT + description: This field represents the amount of data needed to be sent. + bitOffset: 8 + bitWidth: 5 + access: read-only + - name: TXFIFO_CNT + description: This field stores the amount of received data in RAM. + bitOffset: 18 + bitWidth: 5 + access: read-only + - name: SCL_MAIN_STATE_LAST + description: "This field indicates the states of the I2C module state machine. \n0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK" + bitOffset: 24 + bitWidth: 3 + access: read-only + - name: SCL_STATE_LAST + description: "This field indicates the states of the state machine used to produce SCL.\n0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop" + bitOffset: 28 + bitWidth: 3 + access: read-only + - register: + name: TO + description: Setting time out control for receiving data. + addressOffset: 12 + size: 32 + resetValue: 16 + fields: + - name: TIME_OUT_VALUE + description: "This register is used to configure the timeout for receiving a data bit in APB\nclock cycles." + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: TIME_OUT_EN + description: This is the enable bit for time out control. + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: FIFO_ST + description: FIFO status register. + addressOffset: 20 + size: 32 + fields: + - name: RXFIFO_RADDR + description: This is the offset address of the APB reading from rxfifo + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: RXFIFO_WADDR + description: This is the offset address of i2c module receiving data and writing to rxfifo. + bitOffset: 5 + bitWidth: 4 + access: read-only + - name: TXFIFO_RADDR + description: This is the offset address of i2c module reading from txfifo. + bitOffset: 10 + bitWidth: 4 + access: read-only + - name: TXFIFO_WADDR + description: This is the offset address of APB bus writing to txfifo. + bitOffset: 15 + bitWidth: 4 + access: read-only + - register: + name: FIFO_CONF + description: FIFO configuration register. + addressOffset: 24 + size: 32 + resetValue: 16454 + fields: + - name: RXFIFO_WM_THRHD + description: "The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: TXFIFO_WM_THRHD + description: "The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid." + bitOffset: 5 + bitWidth: 4 + access: read-write + - name: NONFIFO_EN + description: Set this bit to enable APB nonfifo access. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: RX_FIFO_RST + description: Set this bit to reset rx-fifo. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_FIFO_RST + description: Set this bit to reset tx-fifo. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FIFO_PRT_EN + description: "The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty." + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DATA + description: Rx FIFO read data. + addressOffset: 28 + size: 32 + fields: + - name: FIFO_RDATA + description: The value of rx FIFO read data. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 32 + size: 32 + resetValue: 2 + fields: + - name: RXFIFO_WM_INT_RAW + description: The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_WM_INT_RAW + description: The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_RAW + description: The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: END_DETECT_INT_RAW + description: The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS_DONE_INT_RAW + description: The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_RAW + description: The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: MST_TXFIFO_UDF_INT_RAW + description: The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_RAW + description: The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_RAW + description: The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TRANS_START_INT_RAW + description: The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: NACK_INT_RAW + description: The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: TXFIFO_OVF_INT_RAW + description: The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: RXFIFO_UDF_INT_RAW + description: The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SCL_ST_TO_INT_RAW + description: The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SCL_MAIN_ST_TO_INT_RAW + description: The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DET_START_INT_RAW + description: The raw interrupt bit for I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 36 + size: 32 + fields: + - name: RXFIFO_WM_INT_CLR + description: Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TXFIFO_WM_INT_CLR + description: Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RXFIFO_OVF_INT_CLR + description: Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: END_DETECT_INT_CLR + description: Set this bit to clear the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: BYTE_TRANS_DONE_INT_CLR + description: Set this bit to clear the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: ARBITRATION_LOST_INT_CLR + description: Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: MST_TXFIFO_UDF_INT_CLR + description: Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TRANS_COMPLETE_INT_CLR + description: Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: TIME_OUT_INT_CLR + description: Set this bit to clear the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: TRANS_START_INT_CLR + description: Set this bit to clear the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: NACK_INT_CLR + description: Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: TXFIFO_OVF_INT_CLR + description: Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: RXFIFO_UDF_INT_CLR + description: Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: SCL_ST_TO_INT_CLR + description: Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SCL_MAIN_ST_TO_INT_CLR + description: Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: DET_START_INT_CLR + description: Set this bit to clear I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 40 + size: 32 + fields: + - name: RXFIFO_WM_INT_ENA + description: The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_WM_INT_ENA + description: The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_ENA + description: The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: END_DETECT_INT_ENA + description: The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: BYTE_TRANS_DONE_INT_ENA + description: The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ARBITRATION_LOST_INT_ENA + description: The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: MST_TXFIFO_UDF_INT_ENA + description: The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TRANS_COMPLETE_INT_ENA + description: The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TIME_OUT_INT_ENA + description: The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TRANS_START_INT_ENA + description: The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: NACK_INT_ENA + description: The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TXFIFO_OVF_INT_ENA + description: The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RXFIFO_UDF_INT_ENA + description: The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SCL_ST_TO_INT_ENA + description: The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SCL_MAIN_ST_TO_INT_ENA + description: The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DET_START_INT_ENA + description: The interrupt enable bit for I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: INT_STATUS + description: Status of captured I2C communication events + addressOffset: 44 + size: 32 + fields: + - name: RXFIFO_WM_INT_ST + description: The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_WM_INT_ST + description: The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_ST + description: The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: END_DETECT_INT_ST + description: The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS_DONE_INT_ST + description: The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_ST + description: The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: MST_TXFIFO_UDF_INT_ST + description: The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_ST + description: The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_ST + description: The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TRANS_START_INT_ST + description: The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: NACK_INT_ST + description: The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: TXFIFO_OVF_INT_ST + description: The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: RXFIFO_UDF_INT_ST + description: The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SCL_ST_TO_INT_ST + description: The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SCL_MAIN_ST_TO_INT_ST + description: The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DET_START_INT_ST + description: The masked interrupt status bit for I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - register: + name: SDA_HOLD + description: Configures the hold time after a negative SCL edge. + addressOffset: 48 + size: 32 + fields: + - name: TIME + description: "This register is used to configure the time to hold the data after the negative\nedge of SCL, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SDA_SAMPLE + description: Configures the sample time after a positive SCL edge. + addressOffset: 52 + size: 32 + fields: + - name: TIME + description: "This register is used to configure for how long SDA is sampled, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_HIGH_PERIOD + description: Configures the high level width of SCL + addressOffset: 56 + size: 32 + fields: + - name: SCL_HIGH_PERIOD + description: "This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: SCL_WAIT_HIGH_PERIOD + description: "This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles." + bitOffset: 9 + bitWidth: 7 + access: read-write + - register: + name: SCL_START_HOLD + description: Configures the delay between the SDA and SCL negative edge for a start condition + addressOffset: 64 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the time between the negative edge\nof SDA and the negative edge of SCL for a START condition, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_RSTART_SETUP + description: "Configures the delay between the positive\nedge of SCL and the negative edge of SDA" + addressOffset: 68 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the time between the positive\nedge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_STOP_HOLD + description: "Configures the delay after the SCL clock\nedge for a stop condition" + addressOffset: 72 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the delay after the STOP condition,\nin I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_STOP_SETUP + description: "Configures the delay between the SDA and\nSCL positive edge for a stop condition" + addressOffset: 76 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the time between the positive edge\nof SCL and the positive edge of SDA, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: FILTER_CFG + description: SCL and SDA filter configuration register + addressOffset: 80 + size: 32 + resetValue: 768 + fields: + - name: SCL_FILTER_THRES + description: "When a pulse on the SCL input has smaller width than this register value\nin I2C module clock cycles, the I2C controller will ignore that pulse." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: SDA_FILTER_THRES + description: "When a pulse on the SDA input has smaller width than this register value\nin I2C module clock cycles, the I2C controller will ignore that pulse." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: SCL_FILTER_EN + description: This is the filter enable bit for SCL. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SDA_FILTER_EN + description: This is the filter enable bit for SDA. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: CLK_CONF + description: I2C CLK configuration register + addressOffset: 84 + size: 32 + resetValue: 2097152 + fields: + - name: SCLK_DIV_NUM + description: the integral part of the fractional divisor for i2c module + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SCLK_DIV_A + description: the numerator of the fractional part of the fractional divisor for i2c module + bitOffset: 8 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_B + description: the denominator of the fractional part of the fractional divisor for i2c module + bitOffset: 14 + bitWidth: 6 + access: read-write + - name: SCLK_SEL + description: "The clock selection for i2c module:0-XTAL,1-CLK_8MHz." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SCLK_ACTIVE + description: The clock switch for i2c module + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + name: COMD0 + description: I2C command register 0 + addressOffset: 88 + size: 32 + fields: + - name: COMMAND0 + description: "This is the content of command 0. It consists of three parts: \nop_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.\nByte_num represents the number of bytes that need to be sent or received.\nack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more\nInformation." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND0_DONE + description: "When command 0 is done in I2C Master mode, this bit changes to high\nlevel." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD1 + description: I2C command register 1 + addressOffset: 92 + size: 32 + fields: + - name: COMMAND1 + description: "This is the content of command 1. It consists of three parts: \nop_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.\nByte_num represents the number of bytes that need to be sent or received.\nack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more\nInformation." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND1_DONE + description: "When command 1 is done in I2C Master mode, this bit changes to high\nlevel." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD2 + description: I2C command register 2 + addressOffset: 96 + size: 32 + fields: + - name: COMMAND2 + description: "This is the content of command 2. It consists of three parts: \nop_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.\nByte_num represents the number of bytes that need to be sent or received.\nack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more\nInformation." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND2_DONE + description: "When command 2 is done in I2C Master mode, this bit changes to high\nLevel." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD3 + description: I2C command register 3 + addressOffset: 100 + size: 32 + fields: + - name: COMMAND3 + description: "This is the content of command 3. It consists of three parts: \nop_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.\nByte_num represents the number of bytes that need to be sent or received.\nack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more\nInformation." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND3_DONE + description: "When command 3 is done in I2C Master mode, this bit changes to high\nlevel." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD4 + description: I2C command register 4 + addressOffset: 104 + size: 32 + fields: + - name: COMMAND4 + description: "This is the content of command 4. It consists of three parts: \nop_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.\nByte_num represents the number of bytes that need to be sent or received.\nack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more\nInformation." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND4_DONE + description: "When command 4 is done in I2C Master mode, this bit changes to high\nlevel." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD5 + description: I2C command register 5 + addressOffset: 108 + size: 32 + fields: + - name: COMMAND5 + description: "This is the content of command 5. It consists of three parts:\nop_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.\nByte_num represents the number of bytes that need to be sent or received.\nack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more\nInformation." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND5_DONE + description: "When command 5 is done in I2C Master mode, this bit changes to high level." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD6 + description: I2C command register 6 + addressOffset: 112 + size: 32 + fields: + - name: COMMAND6 + description: "This is the content of command 6. It consists of three parts: \nop_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.\nByte_num represents the number of bytes that need to be sent or received.\nack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more\nInformation." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND6_DONE + description: "When command 6 is done in I2C Master mode, this bit changes to high level." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD7 + description: I2C command register 7 + addressOffset: 116 + size: 32 + fields: + - name: COMMAND7 + description: "This is the content of command 7. It consists of three parts: \nop_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.\nByte_num represents the number of bytes that need to be sent or received.\nack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more\nInformation." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND7_DONE + description: "When command 7 is done in I2C Master mode, this bit changes to high level." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SCL_ST_TIME_OUT + description: SCL status time out register + addressOffset: 120 + size: 32 + resetValue: 16 + fields: + - name: SCL_ST_TO_I2C + description: The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SCL_MAIN_ST_TIME_OUT + description: SCL main status time out register + addressOffset: 124 + size: 32 + resetValue: 16 + fields: + - name: SCL_MAIN_ST_TO_I2C + description: The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23 + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SCL_SP_CONF + description: Power configuration register + addressOffset: 128 + size: 32 + fields: + - name: SCL_RST_SLV_EN + description: "When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_RST_SLV_NUM + description: Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. + bitOffset: 1 + bitWidth: 5 + access: read-write + - name: SCL_PD_EN + description: "The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SDA_PD_EN + description: "The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low." + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version register + addressOffset: 248 + size: 32 + resetValue: 35656003 + fields: + - name: DATE + description: This is the the version register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TXFIFO_START_ADDR + description: I2C TXFIFO base address register + addressOffset: 256 + size: 32 + fields: + - name: TXFIFO_START_ADDR + description: This is the I2C txfifo first address. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RXFIFO_START_ADDR + description: I2C RXFIFO base address register + addressOffset: 384 + size: 32 + fields: + - name: RXFIFO_START_ADDR + description: This is the I2C rxfifo first address. + bitOffset: 0 + bitWidth: 32 + access: read-only + - name: LP_PERI + description: LP_PERI Peripheral + groupName: LPPERI + baseAddress: 1611343872 + addressBlock: + - offset: 0 + size: 40 + usage: registers + interrupt: + - name: LP_PERI_TIMEOUT + value: 19 + registers: + - register: + name: CLK_EN + description: need_des + addressOffset: 0 + size: 32 + resetValue: 2139095040 + fields: + - name: LP_TOUCH_CK_EN + description: need_des + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: RNG_CK_EN + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: OTP_DBG_CK_EN + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LP_UART_CK_EN + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LP_IO_CK_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LP_EXT_I2C_CK_EN + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_ANA_I2C_CK_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: EFUSE_CK_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_CPU_CK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RESET_EN + description: need_des + addressOffset: 4 + size: 32 + fields: + - name: BUS_RESET_EN + description: need_des + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: LP_TOUCH_RESET_EN + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: OTP_DBG_RESET_EN + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LP_UART_RESET_EN + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LP_IO_RESET_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LP_EXT_I2C_RESET_EN + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_ANA_I2C_RESET_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: EFUSE_RESET_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_CPU_RESET_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: RNG_DATA + description: need_des + addressOffset: 8 + size: 32 + fields: + - name: RND_DATA + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CPU + description: need_des + addressOffset: 12 + size: 32 + resetValue: 2147483648 + fields: + - name: LPCORE_DBGM_UNAVALIABLE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: BUS_TIMEOUT + description: need_des + addressOffset: 16 + size: 32 + resetValue: 3221209088 + fields: + - name: LP_PERI_TIMEOUT_THRES + description: need_des + bitOffset: 14 + bitWidth: 16 + access: read-write + - name: LP_PERI_TIMEOUT_INT_CLEAR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: LP_PERI_TIMEOUT_PROTECT_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: BUS_TIMEOUT_ADDR + description: need_des + addressOffset: 20 + size: 32 + fields: + - name: LP_PERI_TIMEOUT_ADDR + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BUS_TIMEOUT_UID + description: need_des + addressOffset: 24 + size: 32 + fields: + - name: LP_PERI_TIMEOUT_UID + description: need_des + bitOffset: 0 + bitWidth: 7 + access: read-only + - register: + name: MEM_CTRL + description: need_des + addressOffset: 28 + size: 32 + resetValue: 2147483648 + fields: + - name: UART_WAKEUP_FLAG_CLR + description: need_des + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: UART_WAKEUP_FLAG + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UART_WAKEUP_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: UART_MEM_FORCE_PD + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: UART_MEM_FORCE_PU + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INTERRUPT_SOURCE + description: need_des + addressOffset: 32 + size: 32 + fields: + - name: LP_INTERRUPT_SOURCE + description: "BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, lp_io_int" + bitOffset: 0 + bitWidth: 6 + access: read-only + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 35676464 + fields: + - name: LPPERI_DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: LP_ANA_PERI + description: LP_ANA_PERI Peripheral + groupName: LP_ANA + baseAddress: 1611344896 + addressBlock: + - offset: 0 + size: 52 + usage: registers + registers: + - register: + name: BOD_MODE0_CNTL + description: need_des + addressOffset: 0 + size: 32 + resetValue: 268173568 + fields: + - name: BOD_MODE0_CLOSE_FLASH_ENA + description: need_des + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BOD_MODE0_PD_RF_ENA + description: need_des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: BOD_MODE0_INTR_WAIT + description: need_des + bitOffset: 8 + bitWidth: 10 + access: read-write + - name: BOD_MODE0_RESET_WAIT + description: need_des + bitOffset: 18 + bitWidth: 10 + access: read-write + - name: BOD_MODE0_CNT_CLR + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: BOD_MODE0_INTR_ENA + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: BOD_MODE0_RESET_SEL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: BOD_MODE0_RESET_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: BOD_MODE1_CNTL + description: need_des + addressOffset: 4 + size: 32 + fields: + - name: BOD_MODE1_RESET_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CK_GLITCH_CNTL + description: need_des + addressOffset: 8 + size: 32 + fields: + - name: CK_GLITCH_RESET_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: FIB_ENABLE + description: need_des + addressOffset: 12 + size: 32 + resetValue: 4294967295 + fields: + - name: ANA_FIB_ENA + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: INT_RAW + description: need_des + addressOffset: 16 + size: 32 + fields: + - name: BOD_MODE0_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: need_des + addressOffset: 20 + size: 32 + fields: + - name: BOD_MODE0_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: need_des + addressOffset: 24 + size: 32 + fields: + - name: BOD_MODE0_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: need_des + addressOffset: 28 + size: 32 + fields: + - name: BOD_MODE0_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: LP_INT_RAW + description: need_des + addressOffset: 32 + size: 32 + fields: + - name: BOD_MODE0_LP_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_INT_ST + description: need_des + addressOffset: 36 + size: 32 + fields: + - name: BOD_MODE0_LP_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: LP_INT_ENA + description: need_des + addressOffset: 40 + size: 32 + fields: + - name: BOD_MODE0_LP_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_INT_CLR + description: need_des + addressOffset: 44 + size: 32 + fields: + - name: BOD_MODE0_LP_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 35660384 + fields: + - name: LP_ANA_DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: LP_AON + description: LP_AON Peripheral + groupName: LP_AON + baseAddress: 1611337728 + addressBlock: + - offset: 0 + size: 92 + usage: registers + registers: + - register: + name: STORE0 + description: need_des + addressOffset: 0 + size: 32 + fields: + - name: LP_AON_STORE0 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE1 + description: need_des + addressOffset: 4 + size: 32 + fields: + - name: LP_AON_STORE1 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE2 + description: need_des + addressOffset: 8 + size: 32 + fields: + - name: LP_AON_STORE2 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE3 + description: need_des + addressOffset: 12 + size: 32 + fields: + - name: LP_AON_STORE3 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE4 + description: need_des + addressOffset: 16 + size: 32 + fields: + - name: LP_AON_STORE4 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE5 + description: need_des + addressOffset: 20 + size: 32 + fields: + - name: LP_AON_STORE5 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE6 + description: need_des + addressOffset: 24 + size: 32 + fields: + - name: LP_AON_STORE6 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE7 + description: need_des + addressOffset: 28 + size: 32 + fields: + - name: LP_AON_STORE7 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE8 + description: need_des + addressOffset: 32 + size: 32 + fields: + - name: LP_AON_STORE8 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE9 + description: need_des + addressOffset: 36 + size: 32 + fields: + - name: LP_AON_STORE9 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: GPIO_MUX + description: need_des + addressOffset: 40 + size: 32 + fields: + - name: SEL + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: GPIO_HOLD0 + description: need_des + addressOffset: 44 + size: 32 + fields: + - name: GPIO_HOLD0 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: GPIO_HOLD1 + description: need_des + addressOffset: 48 + size: 32 + fields: + - name: GPIO_HOLD1 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SYS_CFG + description: need_des + addressOffset: 52 + size: 32 + fields: + - name: FORCE_DOWNLOAD_BOOT + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HPSYS_SW_RESET + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: CPUCORE0_CFG + description: need_des + addressOffset: 56 + size: 32 + resetValue: 1073741824 + fields: + - name: CPU_CORE0_SW_STALL + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CPU_CORE0_SW_RESET + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: CPU_CORE0_OCD_HALT_ON_RESET + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CPU_CORE0_STAT_VECTOR_SEL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CPU_CORE0_DRESET_MASK + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: IO_MUX + description: need_des + addressOffset: 60 + size: 32 + fields: + - name: RESET_DISABLE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EXT_WAKEUP_CNTL + description: need_des + addressOffset: 64 + size: 32 + fields: + - name: EXT_WAKEUP_STATUS + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: EXT_WAKEUP_STATUS_CLR + description: need_des + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: EXT_WAKEUP_SEL + description: need_des + bitOffset: 15 + bitWidth: 8 + access: read-write + - name: EXT_WAKEUP_LV + description: need_des + bitOffset: 23 + bitWidth: 8 + access: read-write + - name: EXT_WAKEUP_FILTER + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USB + description: need_des + addressOffset: 68 + size: 32 + fields: + - name: RESET_DISABLE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LPBUS + description: need_des + addressOffset: 72 + size: 32 + resetValue: 2954887168 + fields: + - name: FAST_MEM_WPULSE + description: This field controls fast memory WPULSE parameter. + bitOffset: 16 + bitWidth: 3 + access: read-write + - name: FAST_MEM_WA + description: This field controls fast memory WA parameter. + bitOffset: 19 + bitWidth: 3 + access: read-write + - name: FAST_MEM_RA + description: This field controls fast memory RA parameter. + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: FAST_MEM_MUX_FSM_IDLE + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: FAST_MEM_MUX_SEL_STATUS + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: FAST_MEM_MUX_SEL_UPDATE + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: FAST_MEM_MUX_SEL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SDIO_ACTIVE + description: need_des + addressOffset: 76 + size: 32 + resetValue: 41943040 + fields: + - name: SDIO_ACT_DNUM + description: need_des + bitOffset: 22 + bitWidth: 10 + access: read-write + - register: + name: LPCORE + description: need_des + addressOffset: 80 + size: 32 + fields: + - name: ETM_WAKEUP_FLAG_CLR + description: need_des + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ETM_WAKEUP_FLAG + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DISABLE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAR_CCT + description: need_des + addressOffset: 84 + size: 32 + fields: + - name: SAR2_PWDET_CCT + description: need_des + bitOffset: 29 + bitWidth: 3 + access: read-write + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 35672704 + fields: + - name: DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: LP_APM + description: Low-power Access Permission Management Controller + groupName: LP_APM + baseAddress: 1611347968 + addressBlock: + - offset: 0 + size: 100 + usage: registers + interrupt: + - name: LP_APM_M0 + value: 20 + - name: LP_APM_M1 + value: 21 + registers: + - register: + name: REGION_FILTER_EN + description: Region filter enable register + addressOffset: 0 + size: 32 + resetValue: 1 + fields: + - name: REGION_FILTER_EN + description: Region filter enable + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: REGION0_ADDR_START + description: Region address register + addressOffset: 4 + size: 32 + fields: + - name: REGION0_ADDR_START + description: Start address of region0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION0_ADDR_END + description: Region address register + addressOffset: 8 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION0_ADDR_END + description: End address of region0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION0_PMS_ATTR + description: Region access authority attribute register + addressOffset: 12 + size: 32 + fields: + - name: REGION0_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION0_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION0_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION0_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION0_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION0_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION0_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION0_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION0_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION1_ADDR_START + description: Region address register + addressOffset: 16 + size: 32 + fields: + - name: REGION1_ADDR_START + description: Start address of region1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION1_ADDR_END + description: Region address register + addressOffset: 20 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION1_ADDR_END + description: End address of region1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION1_PMS_ATTR + description: Region access authority attribute register + addressOffset: 24 + size: 32 + fields: + - name: REGION1_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION1_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION1_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION1_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION1_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION1_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION1_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION1_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION1_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION2_ADDR_START + description: Region address register + addressOffset: 28 + size: 32 + fields: + - name: REGION2_ADDR_START + description: Start address of region2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION2_ADDR_END + description: Region address register + addressOffset: 32 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION2_ADDR_END + description: End address of region2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION2_PMS_ATTR + description: Region access authority attribute register + addressOffset: 36 + size: 32 + fields: + - name: REGION2_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION2_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION2_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION2_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION2_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION2_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION2_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION2_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION2_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION3_ADDR_START + description: Region address register + addressOffset: 40 + size: 32 + fields: + - name: REGION3_ADDR_START + description: Start address of region3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION3_ADDR_END + description: Region address register + addressOffset: 44 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION3_ADDR_END + description: End address of region3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION3_PMS_ATTR + description: Region access authority attribute register + addressOffset: 48 + size: 32 + fields: + - name: REGION3_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION3_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION3_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION3_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION3_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION3_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION3_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION3_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION3_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: FUNC_CTRL + description: PMS function control register + addressOffset: 196 + size: 32 + resetValue: 3 + fields: + - name: M0_PMS_FUNC_EN + description: PMS M0 function enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: M1_PMS_FUNC_EN + description: PMS M1 function enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: M0_STATUS + description: M0 status register + addressOffset: 200 + size: 32 + fields: + - name: M0_EXCEPTION_STATUS + description: Exception status + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: M0_STATUS_CLR + description: M0 status clear register + addressOffset: 204 + size: 32 + fields: + - name: M0_REGION_STATUS_CLR + description: Clear exception status + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: M0_EXCEPTION_INFO0 + description: M0 exception_info0 register + addressOffset: 208 + size: 32 + fields: + - name: M0_EXCEPTION_REGION + description: Exception region + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: M0_EXCEPTION_MODE + description: Exception mode + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: M0_EXCEPTION_ID + description: Exception id information + bitOffset: 18 + bitWidth: 5 + access: read-only + - register: + name: M0_EXCEPTION_INFO1 + description: M0 exception_info1 register + addressOffset: 212 + size: 32 + fields: + - name: M0_EXCEPTION_ADDR + description: Exception addr + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: M1_STATUS + description: M1 status register + addressOffset: 216 + size: 32 + fields: + - name: M1_EXCEPTION_STATUS + description: Exception status + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: M1_STATUS_CLR + description: M1 status clear register + addressOffset: 220 + size: 32 + fields: + - name: M1_REGION_STATUS_CLR + description: Clear exception status + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: M1_EXCEPTION_INFO0 + description: M1 exception_info0 register + addressOffset: 224 + size: 32 + fields: + - name: M1_EXCEPTION_REGION + description: Exception region + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: M1_EXCEPTION_MODE + description: Exception mode + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: M1_EXCEPTION_ID + description: Exception id information + bitOffset: 18 + bitWidth: 5 + access: read-only + - register: + name: M1_EXCEPTION_INFO1 + description: M1 exception_info1 register + addressOffset: 228 + size: 32 + fields: + - name: M1_EXCEPTION_ADDR + description: Exception addr + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INT_EN + description: APM interrupt enable register + addressOffset: 232 + size: 32 + fields: + - name: M0_APM_INT_EN + description: APM M0 interrupt enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: M1_APM_INT_EN + description: APM M1 interrupt enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CLOCK_GATE + description: clock gating register + addressOffset: 236 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: reg_clk_en + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version register + addressOffset: 252 + size: 32 + resetValue: 35672640 + fields: + - name: DATE + description: reg_date + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: LP_CLKRST + description: LP_CLKRST Peripheral + groupName: LP_CLKRST + baseAddress: 1611334656 + addressBlock: + - offset: 0 + size: 52 + usage: registers + registers: + - register: + name: LP_CLK_CONF + description: need_des + addressOffset: 0 + size: 32 + resetValue: 4 + fields: + - name: SLOW_CLK_SEL + description: need_des + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: FAST_CLK_SEL + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: LP_PERI_DIV_NUM + description: need_des + bitOffset: 3 + bitWidth: 8 + access: read-write + - register: + name: LP_CLK_PO_EN + description: need_des + addressOffset: 4 + size: 32 + resetValue: 2047 + fields: + - name: AON_SLOW_OEN + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: AON_FAST_OEN + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SOSC_OEN + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FOSC_OEN + description: need_des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OSC32K_OEN + description: need_des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: XTAL32K_OEN + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CORE_EFUSE_OEN + description: need_des + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SLOW_OEN + description: need_des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FAST_OEN + description: need_des + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RNG_OEN + description: need_des + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: LPBUS_OEN + description: need_des + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: LP_CLK_EN + description: need_des + addressOffset: 8 + size: 32 + fields: + - name: FAST_ORI_GATE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_RST_EN + description: need_des + addressOffset: 12 + size: 32 + fields: + - name: AON_EFUSE_CORE_RESET_EN + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_TIMER_RESET_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: WDT_RESET_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: ANA_PERI_RESET_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RESET_CAUSE + description: need_des + addressOffset: 16 + size: 32 + resetValue: 32 + fields: + - name: RESET_CAUSE + description: need_des + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: CORE0_RESET_FLAG + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CORE0_RESET_CAUSE_CLR + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: CORE0_RESET_FLAG_SET + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: CORE0_RESET_FLAG_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: CPU_RESET + description: need_des + addressOffset: 20 + size: 32 + resetValue: 71303168 + fields: + - name: RTC_WDT_CPU_RESET_LENGTH + description: need_des + bitOffset: 22 + bitWidth: 3 + access: read-write + - name: RTC_WDT_CPU_RESET_EN + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: CPU_STALL_WAIT + description: need_des + bitOffset: 26 + bitWidth: 5 + access: read-write + - name: CPU_STALL_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: FOSC_CNTL + description: need_des + addressOffset: 24 + size: 32 + resetValue: 721420288 + fields: + - name: FOSC_DFREQ + description: need_des + bitOffset: 22 + bitWidth: 10 + access: read-write + - register: + name: RC32K_CNTL + description: need_des + addressOffset: 28 + size: 32 + resetValue: 721420288 + fields: + - name: RC32K_DFREQ + description: need_des + bitOffset: 22 + bitWidth: 10 + access: read-write + - register: + name: CLK_TO_HP + description: need_des + addressOffset: 32 + size: 32 + resetValue: 4026531840 + fields: + - name: ICG_HP_XTAL32K + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: ICG_HP_SOSC + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ICG_HP_OSC32K + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: ICG_HP_FOSC + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LPMEM_FORCE + description: need_des + addressOffset: 36 + size: 32 + fields: + - name: LPMEM_CLK_FORCE_ON + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LPPERI + description: need_des + addressOffset: 40 + size: 32 + fields: + - name: LP_I2C_CLK_SEL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_UART_CLK_SEL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: XTAL32K + description: need_des + addressOffset: 44 + size: 32 + resetValue: 1723858944 + fields: + - name: DRES_XTAL32K + description: need_des + bitOffset: 22 + bitWidth: 3 + access: read-write + - name: DGM_XTAL32K + description: need_des + bitOffset: 25 + bitWidth: 3 + access: read-write + - name: DBUF_XTAL32K + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DAC_XTAL32K + description: need_des + bitOffset: 29 + bitWidth: 3 + access: read-write + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 35676304 + fields: + - name: CLKRST_DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: LP_I2C_ANA_MST + description: LP_I2C_ANA_MST Peripheral + groupName: LP_I2C_ANA_MST + baseAddress: 1611342848 + addressBlock: + - offset: 0 + size: 28 + usage: registers + registers: + - register: + name: I2C0_CTRL + description: need_des + addressOffset: 0 + size: 32 + fields: + - name: LP_I2C_ANA_MAST_I2C0_CTRL + description: need_des + bitOffset: 0 + bitWidth: 25 + access: read-write + - name: LP_I2C_ANA_MAST_I2C0_BUSY + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-only + - register: + name: I2C0_CONF + description: need_des + addressOffset: 4 + size: 32 + resetValue: 117440512 + fields: + - name: LP_I2C_ANA_MAST_I2C0_CONF + description: need_des + bitOffset: 0 + bitWidth: 24 + access: read-write + - name: LP_I2C_ANA_MAST_I2C0_STATUS + description: reserved + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: I2C0_DATA + description: need_des + addressOffset: 8 + size: 32 + resetValue: 2304 + fields: + - name: LP_I2C_ANA_MAST_I2C0_RDATA + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: LP_I2C_ANA_MAST_I2C0_CLK_SEL + description: need_des + bitOffset: 8 + bitWidth: 3 + access: read-write + - name: LP_I2C_ANA_MAST_I2C_MST_SEL + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: ANA_CONF1 + description: need_des + addressOffset: 12 + size: 32 + fields: + - name: LP_I2C_ANA_MAST_ANA_CONF1 + description: need_des + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: NOUSE + description: need_des + addressOffset: 16 + size: 32 + fields: + - name: LP_I2C_ANA_MAST_I2C_MST_NOUSE + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DEVICE_EN + description: need_des + addressOffset: 20 + size: 32 + fields: + - name: LP_I2C_ANA_MAST_I2C_DEVICE_EN + description: need_des + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 33583873 + fields: + - name: LP_I2C_ANA_MAST_I2C_MAT_DATE + description: need_des + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: LP_I2C_ANA_MAST_I2C_MAT_CLK_EN + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_IO + description: LP_IO Peripheral + groupName: LP_IO + baseAddress: 1611341824 + addressBlock: + - offset: 0 + size: 124 + usage: registers + registers: + - register: + name: OUT + description: need des + addressOffset: 0 + size: 32 + fields: + - name: OUT_DATA + description: set lp gpio output data + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: OUT_W1TS + description: need des + addressOffset: 4 + size: 32 + fields: + - name: OUT_DATA_W1TS + description: set one time output data + bitOffset: 0 + bitWidth: 8 + access: write-only + - register: + name: OUT_W1TC + description: need des + addressOffset: 8 + size: 32 + fields: + - name: OUT_DATA_W1TC + description: clear one time output data + bitOffset: 0 + bitWidth: 8 + access: write-only + - register: + name: ENABLE + description: need des + addressOffset: 12 + size: 32 + fields: + - name: ENABLE + description: set lp gpio output data + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: ENABLE_W1TS + description: need des + addressOffset: 16 + size: 32 + fields: + - name: ENABLE_W1TS + description: set one time output data + bitOffset: 0 + bitWidth: 8 + access: write-only + - register: + name: ENABLE_W1TC + description: need des + addressOffset: 20 + size: 32 + fields: + - name: ENABLE_W1TC + description: clear one time output data + bitOffset: 0 + bitWidth: 8 + access: write-only + - register: + name: STATUS + description: need des + addressOffset: 24 + size: 32 + fields: + - name: INTERRUPT + description: set lp gpio output data + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: STATUS_W1TS + description: need des + addressOffset: 28 + size: 32 + fields: + - name: STATUS_W1TS + description: set one time output data + bitOffset: 0 + bitWidth: 8 + access: write-only + - register: + name: STATUS_W1TC + description: need des + addressOffset: 32 + size: 32 + fields: + - name: STATUS_W1TC + description: clear one time output data + bitOffset: 0 + bitWidth: 8 + access: write-only + - register: + name: IN + description: need des + addressOffset: 36 + size: 32 + fields: + - name: DATA_NEXT + description: need des + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + dim: 8 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7" + name: PIN%s + description: need des + addressOffset: 40 + size: 32 + fields: + - name: SYNC_BYPASS + description: need des + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: PAD_DRIVER + description: need des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EDGE_WAKEUP_CLR + description: need des + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: INT_TYPE + description: need des + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: need des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7" + name: GPIO%s + description: need des + addressOffset: 72 + size: 32 + fields: + - name: MCU_OE + description: need des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: need des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: need des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: need des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: need des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: need des + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: need des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: need des + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: need des + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: need des + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: FUN_SEL + description: need des + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: STATUS_INT + description: need des + addressOffset: 104 + size: 32 + fields: + - name: NEXT + description: need des + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: DATE + description: need des + addressOffset: 1020 + size: 32 + resetValue: 35660032 + fields: + - name: LP_IO_DATE + description: need des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: LP_TEE + description: Low-power Trusted Execution Environment + groupName: LP_TEE + baseAddress: 1611346944 + addressBlock: + - offset: 0 + size: 16 + usage: registers + registers: + - register: + name: M0_MODE_CTRL + description: Tee mode control register + addressOffset: 0 + size: 32 + resetValue: 3 + fields: + - name: M0_MODE + description: "M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: CLOCK_GATE + description: Clock gating register + addressOffset: 4 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: reg_clk_en + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: FORCE_ACC_HP + description: need_des + addressOffset: 144 + size: 32 + fields: + - name: LP_AON_FORCE_ACC_HPMEM_EN + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version register + addressOffset: 252 + size: 32 + resetValue: 35672688 + fields: + - name: DATE + description: reg_tee_date + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: LP_TIMER + description: Low-power Timer + groupName: LP_TIMER + baseAddress: 1611336704 + addressBlock: + - offset: 0 + size: 76 + usage: registers + interrupt: + - name: LP_TIMER + value: 7 + registers: + - register: + name: TAR0_LOW + description: need_des + addressOffset: 0 + size: 32 + fields: + - name: MAIN_TIMER_TAR_LOW0 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TAR0_HIGH + description: need_des + addressOffset: 4 + size: 32 + fields: + - name: MAIN_TIMER_TAR_HIGH0 + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MAIN_TIMER_TAR_EN0 + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: TAR1_LOW + description: need_des + addressOffset: 8 + size: 32 + fields: + - name: MAIN_TIMER_TAR_LOW1 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TAR1_HIGH + description: need_des + addressOffset: 12 + size: 32 + fields: + - name: MAIN_TIMER_TAR_HIGH1 + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MAIN_TIMER_TAR_EN1 + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: UPDATE + description: need_des + addressOffset: 16 + size: 32 + fields: + - name: MAIN_TIMER_UPDATE + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: MAIN_TIMER_XTAL_OFF + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: MAIN_TIMER_SYS_STALL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: MAIN_TIMER_SYS_RST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: MAIN_BUF0_LOW + description: need_des + addressOffset: 20 + size: 32 + fields: + - name: MAIN_TIMER_BUF0_LOW + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: MAIN_BUF0_HIGH + description: need_des + addressOffset: 24 + size: 32 + fields: + - name: MAIN_TIMER_BUF0_HIGH + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: MAIN_BUF1_LOW + description: need_des + addressOffset: 28 + size: 32 + fields: + - name: MAIN_TIMER_BUF1_LOW + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: MAIN_BUF1_HIGH + description: need_des + addressOffset: 32 + size: 32 + fields: + - name: MAIN_TIMER_BUF1_HIGH + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: MAIN_OVERFLOW + description: need_des + addressOffset: 36 + size: 32 + fields: + - name: MAIN_TIMER_ALARM_LOAD + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: INT_RAW + description: need_des + addressOffset: 40 + size: 32 + fields: + - name: OVERFLOW_RAW + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SOC_WAKEUP_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: need_des + addressOffset: 44 + size: 32 + fields: + - name: OVERFLOW_ST + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: SOC_WAKEUP_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: need_des + addressOffset: 48 + size: 32 + fields: + - name: OVERFLOW_ENA + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SOC_WAKEUP_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: need_des + addressOffset: 52 + size: 32 + fields: + - name: OVERFLOW_CLR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: SOC_WAKEUP_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: LP_INT_RAW + description: need_des + addressOffset: 56 + size: 32 + fields: + - name: MAIN_TIMER_OVERFLOW_LP_INT_RAW + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: MAIN_TIMER_LP_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_INT_ST + description: need_des + addressOffset: 60 + size: 32 + fields: + - name: MAIN_TIMER_OVERFLOW_LP_INT_ST + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: MAIN_TIMER_LP_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: LP_INT_ENA + description: need_des + addressOffset: 64 + size: 32 + fields: + - name: MAIN_TIMER_OVERFLOW_LP_INT_ENA + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: MAIN_TIMER_LP_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_INT_CLR + description: need_des + addressOffset: 68 + size: 32 + fields: + - name: MAIN_TIMER_OVERFLOW_LP_INT_CLR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: MAIN_TIMER_LP_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 34672976 + fields: + - name: DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: LP_UART + description: Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller + groupName: LP_UART + baseAddress: 1611338752 + addressBlock: + - offset: 0 + size: 132 + usage: registers + interrupt: + - name: LP_UART + value: 16 + registers: + - register: + name: FIFO + description: FIFO data register + addressOffset: 0 + size: 32 + fields: + - name: RXFIFO_RD_BYTE + description: UART 0 accesses FIFO via this register. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 4 + size: 32 + resetValue: 2 + fields: + - name: RXFIFO_FULL_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_EMPTY_INT_RAW + description: This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PARITY_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a parity error in the data. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FRM_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a data frame error . + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DSR_CHG_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CTS_CHG_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BRK_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RXFIFO_TOUT_INT_RAW + description: This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SW_XON_INT_RAW + description: This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SW_XOFF_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GLITCH_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_BRK_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_BRK_IDLE_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: AT_CMD_CHAR_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: WAKEUP_INT_RAW + description: This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 8 + size: 32 + fields: + - name: RXFIFO_FULL_INT_ST + description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_EMPTY_INT_ST + description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: PARITY_ERR_INT_ST + description: This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FRM_ERR_INT_ST + description: This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_ST + description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DSR_CHG_INT_ST + description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CTS_CHG_INT_ST + description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BRK_DET_INT_ST + description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: RXFIFO_TOUT_INT_ST + description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SW_XON_INT_ST + description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SW_XOFF_INT_ST + description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: GLITCH_DET_INT_ST + description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TX_BRK_DONE_INT_ST + description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: TX_BRK_IDLE_DONE_INT_ST + description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_ST + description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: AT_CMD_CHAR_DET_INT_ST + description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: WAKEUP_INT_ST + description: This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + bitOffset: 19 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 12 + size: 32 + fields: + - name: RXFIFO_FULL_INT_ENA + description: This is the enable bit for rxfifo_full_int_st register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_EMPTY_INT_ENA + description: This is the enable bit for txfifo_empty_int_st register. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PARITY_ERR_INT_ENA + description: This is the enable bit for parity_err_int_st register. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FRM_ERR_INT_ENA + description: This is the enable bit for frm_err_int_st register. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_ENA + description: This is the enable bit for rxfifo_ovf_int_st register. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DSR_CHG_INT_ENA + description: This is the enable bit for dsr_chg_int_st register. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CTS_CHG_INT_ENA + description: This is the enable bit for cts_chg_int_st register. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BRK_DET_INT_ENA + description: This is the enable bit for brk_det_int_st register. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RXFIFO_TOUT_INT_ENA + description: This is the enable bit for rxfifo_tout_int_st register. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SW_XON_INT_ENA + description: This is the enable bit for sw_xon_int_st register. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SW_XOFF_INT_ENA + description: This is the enable bit for sw_xoff_int_st register. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GLITCH_DET_INT_ENA + description: This is the enable bit for glitch_det_int_st register. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_BRK_DONE_INT_ENA + description: This is the enable bit for tx_brk_done_int_st register. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_BRK_IDLE_DONE_INT_ENA + description: This is the enable bit for tx_brk_idle_done_int_st register. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_ENA + description: This is the enable bit for tx_done_int_st register. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: AT_CMD_CHAR_DET_INT_ENA + description: This is the enable bit for at_cmd_char_det_int_st register. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: WAKEUP_INT_ENA + description: This is the enable bit for uart_wakeup_int_st register. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 16 + size: 32 + fields: + - name: RXFIFO_FULL_INT_CLR + description: Set this bit to clear the rxfifo_full_int_raw interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TXFIFO_EMPTY_INT_CLR + description: Set this bit to clear txfifo_empty_int_raw interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: PARITY_ERR_INT_CLR + description: Set this bit to clear parity_err_int_raw interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: FRM_ERR_INT_CLR + description: Set this bit to clear frm_err_int_raw interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: RXFIFO_OVF_INT_CLR + description: Set this bit to clear rxfifo_ovf_int_raw interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: DSR_CHG_INT_CLR + description: Set this bit to clear the dsr_chg_int_raw interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CTS_CHG_INT_CLR + description: Set this bit to clear the cts_chg_int_raw interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: BRK_DET_INT_CLR + description: Set this bit to clear the brk_det_int_raw interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: RXFIFO_TOUT_INT_CLR + description: Set this bit to clear the rxfifo_tout_int_raw interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SW_XON_INT_CLR + description: Set this bit to clear the sw_xon_int_raw interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SW_XOFF_INT_CLR + description: Set this bit to clear the sw_xoff_int_raw interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: GLITCH_DET_INT_CLR + description: Set this bit to clear the glitch_det_int_raw interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TX_BRK_DONE_INT_CLR + description: Set this bit to clear the tx_brk_done_int_raw interrupt.. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: TX_BRK_IDLE_DONE_INT_CLR + description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: TX_DONE_INT_CLR + description: Set this bit to clear the tx_done_int_raw interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: AT_CMD_CHAR_DET_INT_CLR + description: Set this bit to clear the at_cmd_char_det_int_raw interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: WAKEUP_INT_CLR + description: Set this bit to clear the uart_wakeup_int_raw interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - register: + name: CLKDIV_SYNC + description: Clock divider configuration + addressOffset: 20 + size: 32 + resetValue: 694 + fields: + - name: CLKDIV + description: The integral part of the frequency divider factor. + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: CLKDIV_FRAG + description: The decimal part of the frequency divider factor. + bitOffset: 20 + bitWidth: 4 + access: read-write + - register: + name: RX_FILT + description: Rx Filter configuration + addressOffset: 24 + size: 32 + resetValue: 8 + fields: + - name: GLITCH_FILT + description: when input pulse width is lower than this value the pulse is ignored. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GLITCH_FILT_EN + description: Set this bit to enable Rx signal filter. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: STATUS + description: UART status register + addressOffset: 28 + size: 32 + resetValue: 3758145536 + fields: + - name: RXFIFO_CNT + description: Stores the byte number of valid data in Rx-FIFO. + bitOffset: 3 + bitWidth: 5 + access: read-only + - name: DSRN + description: The register represent the level value of the internal uart dsr signal. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: CTSN + description: This register represent the level value of the internal uart cts signal. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: RXD + description: This register represent the level value of the internal uart rxd signal. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TXFIFO_CNT + description: Stores the byte number of data in Tx-FIFO. + bitOffset: 19 + bitWidth: 5 + access: read-only + - name: DTRN + description: This bit represents the level of the internal uart dtr signal. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: RTSN + description: This bit represents the level of the internal uart rts signal. + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: TXD + description: This bit represents the level of the internal uart txd signal. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CONF0_SYNC + description: Configuration register 0 + addressOffset: 32 + size: 32 + resetValue: 1048604 + fields: + - name: PARITY + description: This register is used to configure the parity check mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PARITY_EN + description: Set this bit to enable uart parity check. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BIT_NUM + description: This register is used to set the length of data. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: STOP_BIT_NUM + description: This register is used to set the length of stop bit. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: TXD_BRK + description: Set this bit to enbale transmitter to send NULL when the process of sending data is done. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: LOOPBACK + description: Set this bit to enable uart loopback test mode. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_FLOW_EN + description: Set this bit to enable flow control function for transmitter. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: RXD_INV + description: Set this bit to inverse the level value of uart rxd signal. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TXD_INV + description: Set this bit to inverse the level value of uart txd signal. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DIS_RX_DAT_OVF + description: Disable UART Rx data overflow detect. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: ERR_WR_MASK + description: "1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: MEM_CLK_EN + description: UART memory clock gate enable signal. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SW_RTS + description: This register is used to configure the software rts signal which is used in software flow control. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: RXFIFO_RST + description: Set this bit to reset the uart receive-FIFO. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TXFIFO_RST + description: Set this bit to reset the uart transmit-FIFO. + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: CONF1 + description: Configuration register 1 + addressOffset: 36 + size: 32 + resetValue: 24672 + fields: + - name: RXFIFO_FULL_THRHD + description: It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + bitOffset: 3 + bitWidth: 5 + access: read-write + - name: TXFIFO_EMPTY_THRHD + description: It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + bitOffset: 11 + bitWidth: 5 + access: read-write + - name: CTS_INV + description: Set this bit to inverse the level value of uart cts signal. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DSR_INV + description: Set this bit to inverse the level value of uart dsr signal. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: RTS_INV + description: Set this bit to inverse the level value of uart rts signal. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: DTR_INV + description: Set this bit to inverse the level value of uart dtr signal. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SW_DTR + description: This register is used to configure the software dtr signal which is used in software flow control. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers." + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + name: HWFC_CONF_SYNC + description: Hardware flow-control configuration + addressOffset: 44 + size: 32 + fields: + - name: RX_FLOW_THRHD + description: This register is used to configure the maximum amount of data that can be received when hardware flow control works. + bitOffset: 3 + bitWidth: 5 + access: read-write + - name: RX_FLOW_EN + description: This is the flow enable bit for UART receiver. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: SLEEP_CONF0 + description: UART sleep configure register 0 + addressOffset: 48 + size: 32 + fields: + - name: WK_CHAR1 + description: This register restores the specified wake up char1 to wake up + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: WK_CHAR2 + description: This register restores the specified wake up char2 to wake up + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: WK_CHAR3 + description: This register restores the specified wake up char3 to wake up + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: WK_CHAR4 + description: This register restores the specified wake up char4 to wake up + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: SLEEP_CONF1 + description: UART sleep configure register 1 + addressOffset: 52 + size: 32 + fields: + - name: WK_CHAR0 + description: This register restores the specified char0 to wake up + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: SLEEP_CONF2 + description: UART sleep configure register 2 + addressOffset: 56 + size: 32 + resetValue: 1319152 + fields: + - name: ACTIVE_THRESHOLD + description: The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: RX_WAKE_UP_THRHD + description: In wake up mode 1 this field is used to set the received data number threshold to wake up chip. + bitOffset: 13 + bitWidth: 5 + access: read-write + - name: WK_CHAR_NUM + description: This register is used to select number of wake up char. + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: WK_CHAR_MASK + description: This register is used to mask wake up char. + bitOffset: 21 + bitWidth: 5 + access: read-write + - name: WK_MODE_SEL + description: "This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than" + bitOffset: 26 + bitWidth: 2 + access: read-write + - register: + name: SWFC_CONF0_SYNC + description: Software flow-control character configuration + addressOffset: 60 + size: 32 + resetValue: 4881 + fields: + - name: XON_CHAR + description: This register stores the Xon flow control char. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: XOFF_CHAR + description: This register stores the Xoff flow control char. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: XON_XOFF_STILL_SEND + description: "In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SW_FLOW_CON_EN + description: Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: XONOFF_DEL + description: Set this bit to remove flow control char from the received data. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: FORCE_XON + description: Set this bit to enable the transmitter to go on sending data. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: FORCE_XOFF + description: Set this bit to stop the transmitter from sending data. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SEND_XON + description: Set this bit to send Xon char. It is cleared by hardware automatically. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SEND_XOFF + description: Set this bit to send Xoff char. It is cleared by hardware automatically. + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: SWFC_CONF1 + description: Software flow-control character configuration + addressOffset: 64 + size: 32 + resetValue: 24576 + fields: + - name: XON_THRESHOLD + description: When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char. + bitOffset: 3 + bitWidth: 5 + access: read-write + - name: XOFF_THRESHOLD + description: When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char. + bitOffset: 11 + bitWidth: 5 + access: read-write + - register: + name: TXBRK_CONF_SYNC + description: Tx Break character configuration + addressOffset: 68 + size: 32 + resetValue: 10 + fields: + - name: TX_BRK_NUM + description: This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: IDLE_CONF_SYNC + description: Frame-end idle configuration + addressOffset: 72 + size: 32 + resetValue: 262400 + fields: + - name: RX_IDLE_THRHD + description: It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: TX_IDLE_NUM + description: This register is used to configure the duration time between transfers. + bitOffset: 10 + bitWidth: 10 + access: read-write + - register: + name: RS485_CONF_SYNC + description: RS485 mode configuration + addressOffset: 76 + size: 32 + fields: + - name: DL0_EN + description: Set this bit to delay the stop bit by 1 bit. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DL1_EN + description: Set this bit to delay the stop bit by 1 bit. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: AT_CMD_PRECNT_SYNC + description: Pre-sequence timing configuration + addressOffset: 80 + size: 32 + resetValue: 2305 + fields: + - name: PRE_IDLE_NUM + description: This register is used to configure the idle duration time before the first at_cmd is received by receiver. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_POSTCNT_SYNC + description: Post-sequence timing configuration + addressOffset: 84 + size: 32 + resetValue: 2305 + fields: + - name: POST_IDLE_NUM + description: This register is used to configure the duration time between the last at_cmd and the next data. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_GAPTOUT_SYNC + description: Timeout configuration + addressOffset: 88 + size: 32 + resetValue: 11 + fields: + - name: RX_GAP_TOUT + description: This register is used to configure the duration time between the at_cmd chars. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_CHAR_SYNC + description: AT escape sequence detection configuration + addressOffset: 92 + size: 32 + resetValue: 811 + fields: + - name: AT_CMD_CHAR + description: This register is used to configure the content of at_cmd char. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CHAR_NUM + description: This register is used to configure the num of continuous at_cmd chars received by receiver. + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: MEM_CONF + description: UART memory power configuration + addressOffset: 96 + size: 32 + fields: + - name: MEM_FORCE_PD + description: Set this bit to force power down UART memory. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PU + description: Set this bit to force power up UART memory. + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: TOUT_CONF_SYNC + description: UART threshold and allocation configuration + addressOffset: 100 + size: 32 + resetValue: 40 + fields: + - name: RX_TOUT_EN + description: "This is the enble bit for uart receiver's timeout function." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_TOUT_FLOW_DIS + description: Set this bit to stop accumulating idle_cnt when hardware flow control works. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_TOUT_THRHD + description: This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + bitOffset: 2 + bitWidth: 10 + access: read-write + - register: + name: MEM_TX_STATUS + description: Tx-SRAM write and read offset address. + addressOffset: 104 + size: 32 + fields: + - name: TX_SRAM_WADDR + description: This register stores the offset write address in Tx-SRAM. + bitOffset: 3 + bitWidth: 5 + access: read-only + - name: TX_SRAM_RADDR + description: This register stores the offset read address in Tx-SRAM. + bitOffset: 12 + bitWidth: 5 + access: read-only + - register: + name: MEM_RX_STATUS + description: Rx-SRAM write and read offset address. + addressOffset: 108 + size: 32 + resetValue: 65664 + fields: + - name: RX_SRAM_RADDR + description: This register stores the offset read address in RX-SRAM. + bitOffset: 3 + bitWidth: 5 + access: read-only + - name: RX_SRAM_WADDR + description: This register stores the offset write address in Rx-SRAM. + bitOffset: 12 + bitWidth: 5 + access: read-only + - register: + name: FSM_STATUS + description: UART transmit and receive status. + addressOffset: 112 + size: 32 + fields: + - name: ST_URX_OUT + description: This is the status register of receiver. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: ST_UTX_OUT + description: This is the status register of transmitter. + bitOffset: 4 + bitWidth: 4 + access: read-only + - register: + name: CLK_CONF + description: UART core clock configuration + addressOffset: 136 + size: 32 + resetValue: 57675776 + fields: + - name: SCLK_DIV_B + description: The denominator of the frequency divider factor. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_A + description: The numerator of the frequency divider factor. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_NUM + description: The integral part of the frequency divider factor. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: SCLK_SEL + description: "UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: SCLK_EN + description: Set this bit to enable UART Tx/Rx clock. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RST_CORE + description: Write 1 then write 0 to this bit to reset UART Tx/Rx. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TX_SCLK_EN + description: Set this bit to enable UART Tx clock. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: RX_SCLK_EN + description: Set this bit to enable UART Rx clock. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TX_RST_CORE + description: Write 1 then write 0 to this bit to reset UART Tx. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RX_RST_CORE + description: Write 1 then write 0 to this bit to reset UART Rx. + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: UART Version register + addressOffset: 140 + size: 32 + resetValue: 35656288 + fields: + - name: DATE + description: This is the version register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: AFIFO_STATUS + description: UART AFIFO Status + addressOffset: 144 + size: 32 + resetValue: 10 + fields: + - name: TX_AFIFO_FULL + description: Full signal of APB TX AFIFO. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_AFIFO_EMPTY + description: Empty signal of APB TX AFIFO. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_AFIFO_FULL + description: Full signal of APB RX AFIFO. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: RX_AFIFO_EMPTY + description: Empty signal of APB RX AFIFO. + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: REG_UPDATE + description: UART Registers Configuration Update register + addressOffset: 152 + size: 32 + fields: + - name: REG_UPDATE + description: Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: ID + description: UART ID register + addressOffset: 156 + size: 32 + resetValue: 1280 + fields: + - name: ID + description: This register is used to configure the uart_id. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: LP_WDT + description: Low-power Watchdog Timer + groupName: LP_WDT + baseAddress: 1611340800 + addressBlock: + - offset: 0 + size: 56 + usage: registers + interrupt: + - name: LP_WDT + value: 18 + registers: + - register: + name: CONFIG0 + description: need_des + addressOffset: 0 + size: 32 + resetValue: 78356 + fields: + - name: WDT_CHIP_RESET_WIDTH + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: WDT_CHIP_RESET_EN + description: need_des + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: WDT_PAUSE_IN_SLP + description: need_des + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: WDT_APPCPU_RESET_EN + description: need_des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: WDT_PROCPU_RESET_EN + description: need_des + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: WDT_FLASHBOOT_MOD_EN + description: need_des + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: WDT_SYS_RESET_LENGTH + description: need_des + bitOffset: 13 + bitWidth: 3 + access: read-write + - name: WDT_CPU_RESET_LENGTH + description: need_des + bitOffset: 16 + bitWidth: 3 + access: read-write + - name: WDT_STG3 + description: need_des + bitOffset: 19 + bitWidth: 3 + access: read-write + - name: WDT_STG2 + description: need_des + bitOffset: 22 + bitWidth: 3 + access: read-write + - name: WDT_STG1 + description: need_des + bitOffset: 25 + bitWidth: 3 + access: read-write + - name: WDT_STG0 + description: need_des + bitOffset: 28 + bitWidth: 3 + access: read-write + - name: WDT_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CONFIG1 + description: need_des + addressOffset: 4 + size: 32 + resetValue: 200000 + fields: + - name: WDT_STG0_HOLD + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CONFIG2 + description: need_des + addressOffset: 8 + size: 32 + resetValue: 80000 + fields: + - name: WDT_STG1_HOLD + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CONFIG3 + description: need_des + addressOffset: 12 + size: 32 + resetValue: 4095 + fields: + - name: WDT_STG2_HOLD + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CONFIG4 + description: need_des + addressOffset: 16 + size: 32 + resetValue: 4095 + fields: + - name: WDT_STG3_HOLD + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FEED + description: need_des + addressOffset: 20 + size: 32 + fields: + - name: RTC_WDT_FEED + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: WPROTECT + description: need_des + addressOffset: 24 + size: 32 + fields: + - name: WDT_WKEY + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SWD_CONFIG + description: need_des + addressOffset: 28 + size: 32 + resetValue: 314572800 + fields: + - name: SWD_RESET_FLAG + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SWD_AUTO_FEED_EN + description: need_des + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SWD_RST_FLAG_CLR + description: need_des + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: SWD_SIGNAL_WIDTH + description: need_des + bitOffset: 20 + bitWidth: 10 + access: read-write + - name: SWD_DISABLE + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SWD_FEED + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SWD_WPROTECT + description: need_des + addressOffset: 32 + size: 32 + fields: + - name: SWD_WKEY + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: INT_RAW + description: need_des + addressOffset: 36 + size: 32 + fields: + - name: SUPER_WDT_INT_RAW + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_WDT_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: need_des + addressOffset: 40 + size: 32 + fields: + - name: SUPER_WDT_INT_ST + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: LP_WDT_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: need_des + addressOffset: 44 + size: 32 + fields: + - name: SUPER_WDT_INT_ENA + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_WDT_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: need_des + addressOffset: 48 + size: 32 + fields: + - name: SUPER_WDT_INT_CLR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: LP_WDT_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 34676864 + fields: + - name: LP_WDT_DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write diff --git a/esp32c6/svd/esp32c6.svd.yaml b/esp32c6/svd/esp32c6.svd.yaml new file mode 100644 index 0000000000..0ebc672b36 --- /dev/null +++ b/esp32c6/svd/esp32c6.svd.yaml @@ -0,0 +1,49968 @@ +--- +vendor: "ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD." +vendorID: ESPRESSIF +name: ESP32-C6 +series: ESP32 C-Series +version: "10" +description: 32-bit RISC-V MCU & 2.4 GHz Wi-Fi 6 & Bluetooth 5 (LE) & IEEE 802.15.4 +licenseText: "Copyright 2024 Espressif Systems (Shanghai) PTE LTD\n\n Licensed under the Apache License, Version 2.0 (the \"License\");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an \"AS IS\" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License." +cpu: + name: RV32IMAC + revision: r0p0 + endian: little + mpuPresent: false + fpuPresent: false + nvicPrioBits: 0 + vendorSystickConfig: false +addressUnitBits: 32 +width: 32 +resetValue: 0 +resetMask: 4294967295 +peripherals: + - name: AES + description: AES (Advanced Encryption Standard) Accelerator + groupName: AES + baseAddress: 1611169792 + addressBlock: + - offset: 0 + size: 188 + usage: registers + interrupt: + - name: AES + value: 73 + registers: + - register: + name: KEY_0 + description: Key material key_0 configure register + addressOffset: 0 + size: 32 + fields: + - name: KEY_0 + description: This bits stores key_0 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_1 + description: Key material key_1 configure register + addressOffset: 4 + size: 32 + fields: + - name: KEY_1 + description: This bits stores key_1 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_2 + description: Key material key_2 configure register + addressOffset: 8 + size: 32 + fields: + - name: KEY_2 + description: This bits stores key_2 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_3 + description: Key material key_3 configure register + addressOffset: 12 + size: 32 + fields: + - name: KEY_3 + description: This bits stores key_3 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_4 + description: Key material key_4 configure register + addressOffset: 16 + size: 32 + fields: + - name: KEY_4 + description: This bits stores key_4 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_5 + description: Key material key_5 configure register + addressOffset: 20 + size: 32 + fields: + - name: KEY_5 + description: This bits stores key_5 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_6 + description: Key material key_6 configure register + addressOffset: 24 + size: 32 + fields: + - name: KEY_6 + description: This bits stores key_6 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_7 + description: Key material key_7 configure register + addressOffset: 28 + size: 32 + fields: + - name: KEY_7 + description: This bits stores key_7 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_IN_0 + description: source text material text_in_0 configure register + addressOffset: 32 + size: 32 + fields: + - name: TEXT_IN_0 + description: This bits stores text_in_0 that is a part of source text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_IN_1 + description: source text material text_in_1 configure register + addressOffset: 36 + size: 32 + fields: + - name: TEXT_IN_1 + description: This bits stores text_in_1 that is a part of source text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_IN_2 + description: source text material text_in_2 configure register + addressOffset: 40 + size: 32 + fields: + - name: TEXT_IN_2 + description: This bits stores text_in_2 that is a part of source text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_IN_3 + description: source text material text_in_3 configure register + addressOffset: 44 + size: 32 + fields: + - name: TEXT_IN_3 + description: This bits stores text_in_3 that is a part of source text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_OUT_0 + description: result text material text_out_0 configure register + addressOffset: 48 + size: 32 + fields: + - name: TEXT_OUT_0 + description: This bits stores text_out_0 that is a part of result text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_OUT_1 + description: result text material text_out_1 configure register + addressOffset: 52 + size: 32 + fields: + - name: TEXT_OUT_1 + description: This bits stores text_out_1 that is a part of result text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_OUT_2 + description: result text material text_out_2 configure register + addressOffset: 56 + size: 32 + fields: + - name: TEXT_OUT_2 + description: This bits stores text_out_2 that is a part of result text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_OUT_3 + description: result text material text_out_3 configure register + addressOffset: 60 + size: 32 + fields: + - name: TEXT_OUT_3 + description: This bits stores text_out_3 that is a part of result text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: MODE + description: AES Mode register + addressOffset: 64 + size: 32 + fields: + - name: MODE + description: "This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256." + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: ENDIAN + description: AES Endian configure register + addressOffset: 68 + size: 32 + fields: + - name: ENDIAN + description: "endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out endian or out_stream endian" + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: TRIGGER + description: AES trigger register + addressOffset: 72 + size: 32 + fields: + - name: TRIGGER + description: Set this bit to start AES calculation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: STATE + description: AES state register + addressOffset: 76 + size: 32 + fields: + - name: STATE + description: "Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done." + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + dim: 4 + dimIncrement: 4 + name: "IV_MEM[%s]" + description: The memory that stores initialization vector + addressOffset: 80 + size: 32 + - register: + dim: 4 + dimIncrement: 4 + name: "H_MEM[%s]" + description: The memory that stores GCM hash subkey + addressOffset: 96 + size: 32 + - register: + dim: 4 + dimIncrement: 4 + name: "J0_MEM[%s]" + description: The memory that stores J0 + addressOffset: 112 + size: 32 + - register: + dim: 4 + dimIncrement: 4 + name: "T0_MEM[%s]" + description: The memory that stores T0 + addressOffset: 128 + size: 32 + - register: + name: DMA_ENABLE + description: DMA-AES working mode register + addressOffset: 144 + size: 32 + fields: + - name: DMA_ENABLE + description: "1'b0: typical AES working mode, 1'b1: DMA-AES working mode." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: BLOCK_MODE + description: AES cipher block mode register + addressOffset: 148 + size: 32 + fields: + - name: BLOCK_MODE + description: "Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved." + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: BLOCK_NUM + description: AES block number register + addressOffset: 152 + size: 32 + fields: + - name: BLOCK_NUM + description: Those bits stores the number of Plaintext/ciphertext block. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: INC_SEL + description: Standard incrementing function configure register + addressOffset: 156 + size: 32 + fields: + - name: INC_SEL + description: "This bit decides the standard incrementing function. 0: INC32. 1: INC128." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: AAD_BLOCK_NUM + description: Additional Authential Data block number register + addressOffset: 160 + size: 32 + fields: + - name: AAD_BLOCK_NUM + description: Those bits stores the number of AAD block. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REMAINDER_BIT_NUM + description: AES remainder bit number register + addressOffset: 164 + size: 32 + fields: + - name: REMAINDER_BIT_NUM + description: Those bits stores the number of remainder bit. + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: CONTINUE + description: AES continue register + addressOffset: 168 + size: 32 + fields: + - name: CONTINUE + description: Set this bit to continue GCM operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: INT_CLEAR + description: AES Interrupt clear register + addressOffset: 172 + size: 32 + fields: + - name: INT_CLEAR + description: Set this bit to clear the AES interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + description: AES Interrupt enable register + addressOffset: 176 + size: 32 + fields: + - name: INT_ENA + description: Set this bit to enable interrupt that occurs when DMA-AES calculation is done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: AES version control register + addressOffset: 180 + size: 32 + resetValue: 538513936 + fields: + - name: DATE + description: This bits stores the version information of AES. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: DMA_EXIT + description: AES-DMA exit config + addressOffset: 184 + size: 32 + fields: + - name: DMA_EXIT + description: "Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer." + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: APB_SARADC + description: SAR (Successive Approximation Register) Analog-to-Digital Converter + groupName: APB_SARADC + baseAddress: 1610670080 + addressBlock: + - offset: 0 + size: 112 + usage: registers + interrupt: + - name: APB_SARADC + value: 60 + registers: + - register: + name: CTRL + description: digital saradc configure register + addressOffset: 0 + size: 32 + resetValue: 1073971776 + fields: + - name: SARADC_START_FORCE + description: select software enable saradc sample + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SARADC_START + description: software enable saradc sample + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SARADC_SAR_CLK_GATED + description: SAR clock gated + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SARADC_SAR_CLK_DIV + description: SAR clock divider + bitOffset: 7 + bitWidth: 8 + access: read-write + - name: SARADC_SAR_PATT_LEN + description: 0 ~ 15 means length 1 ~ 16 + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: SARADC_SAR_PATT_P_CLEAR + description: clear the pointer of pattern table for DIG ADC1 CTRL + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SARADC_XPD_SAR_FORCE + description: force option to xpd sar blocks + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: SARADC2_PWDET_DRV + description: enable saradc2 power detect driven func. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SARADC_WAIT_ARB_CYCLE + description: wait arbit signal stable after sar_done + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CTRL2 + description: digital saradc configure register + addressOffset: 4 + size: 32 + resetValue: 41470 + fields: + - name: SARADC_MEAS_NUM_LIMIT + description: enable max meas num + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SARADC_MAX_MEAS_NUM + description: max conversion number + bitOffset: 1 + bitWidth: 8 + access: read-write + - name: SARADC_SAR1_INV + description: "1: data to DIG ADC1 CTRL is inverted, otherwise not" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SARADC_SAR2_INV + description: "1: data to DIG ADC2 CTRL is inverted, otherwise not" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SARADC_TIMER_TARGET + description: to set saradc timer target + bitOffset: 12 + bitWidth: 12 + access: read-write + - name: SARADC_TIMER_EN + description: to enable saradc timer trigger + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: FILTER_CTRL1 + description: digital saradc configure register + addressOffset: 8 + size: 32 + fields: + - name: APB_SARADC_FILTER_FACTOR1 + description: Factor of saradc filter1 + bitOffset: 26 + bitWidth: 3 + access: read-write + - name: APB_SARADC_FILTER_FACTOR0 + description: Factor of saradc filter0 + bitOffset: 29 + bitWidth: 3 + access: read-write + - register: + name: FSM_WAIT + description: digital saradc configure register + addressOffset: 12 + size: 32 + resetValue: 16713736 + fields: + - name: SARADC_XPD_WAIT + description: saradc_xpd_wait + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SARADC_RSTB_WAIT + description: saradc_rstb_wait + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SARADC_STANDBY_WAIT + description: saradc_standby_wait + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: SAR1_STATUS + description: digital saradc configure register + addressOffset: 16 + size: 32 + resetValue: 536870912 + fields: + - name: SARADC_SAR1_STATUS + description: saradc1 status about data and channel + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SAR2_STATUS + description: digital saradc configure register + addressOffset: 20 + size: 32 + resetValue: 536870912 + fields: + - name: SARADC_SAR2_STATUS + description: saradc2 status about data and channel + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SAR_PATT_TAB1 + description: digital saradc configure register + addressOffset: 24 + size: 32 + resetValue: 16777215 + fields: + - name: SARADC_SAR_PATT_TAB1 + description: item 0 ~ 3 for pattern table 1 (each item one byte) + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: SAR_PATT_TAB2 + description: digital saradc configure register + addressOffset: 28 + size: 32 + resetValue: 16777215 + fields: + - name: SARADC_SAR_PATT_TAB2 + description: Item 4 ~ 7 for pattern table 1 (each item one byte) + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: ONETIME_SAMPLE + description: digital saradc configure register + addressOffset: 32 + size: 32 + resetValue: 436207616 + fields: + - name: SARADC_ONETIME_ATTEN + description: configure onetime atten + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: SARADC_ONETIME_CHANNEL + description: configure onetime channel + bitOffset: 25 + bitWidth: 4 + access: read-write + - name: SARADC_ONETIME_START + description: trigger adc onetime sample + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SARADC2_ONETIME_SAMPLE + description: enable adc2 onetime sample + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SARADC1_ONETIME_SAMPLE + description: enable adc1 onetime sample + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: ARB_CTRL + description: digital saradc configure register + addressOffset: 36 + size: 32 + resetValue: 2304 + fields: + - name: ADC_ARB_APB_FORCE + description: adc2 arbiter force to enableapb controller + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ADC_ARB_RTC_FORCE + description: adc2 arbiter force to enable rtc controller + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ADC_ARB_WIFI_FORCE + description: adc2 arbiter force to enable wifi controller + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ADC_ARB_GRANT_FORCE + description: adc2 arbiter force grant + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: ADC_ARB_APB_PRIORITY + description: Set adc2 arbiterapb priority + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: ADC_ARB_RTC_PRIORITY + description: Set adc2 arbiter rtc priority + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: ADC_ARB_WIFI_PRIORITY + description: Set adc2 arbiter wifi priority + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: ADC_ARB_FIX_PRIORITY + description: adc2 arbiter uses fixed priority + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: FILTER_CTRL0 + description: digital saradc configure register + addressOffset: 40 + size: 32 + resetValue: 57933824 + fields: + - name: APB_SARADC_FILTER_CHANNEL1 + description: configure filter1 to adc channel + bitOffset: 18 + bitWidth: 4 + access: read-write + - name: APB_SARADC_FILTER_CHANNEL0 + description: configure filter0 to adc channel + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: APB_SARADC_FILTER_RESET + description: enable apb_adc1_filter + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAR1DATA_STATUS + description: digital saradc configure register + addressOffset: 44 + size: 32 + fields: + - name: APB_SARADC1_DATA + description: saradc1 data + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: SAR2DATA_STATUS + description: digital saradc configure register + addressOffset: 48 + size: 32 + fields: + - name: APB_SARADC2_DATA + description: saradc2 data + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: THRES0_CTRL + description: digital saradc configure register + addressOffset: 52 + size: 32 + resetValue: 262125 + fields: + - name: APB_SARADC_THRES0_CHANNEL + description: configure thres0 to adc channel + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: APB_SARADC_THRES0_HIGH + description: saradc thres0 monitor thres + bitOffset: 5 + bitWidth: 13 + access: read-write + - name: APB_SARADC_THRES0_LOW + description: saradc thres0 monitor thres + bitOffset: 18 + bitWidth: 13 + access: read-write + - register: + name: THRES1_CTRL + description: digital saradc configure register + addressOffset: 56 + size: 32 + resetValue: 262125 + fields: + - name: APB_SARADC_THRES1_CHANNEL + description: configure thres1 to adc channel + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: APB_SARADC_THRES1_HIGH + description: saradc thres1 monitor thres + bitOffset: 5 + bitWidth: 13 + access: read-write + - name: APB_SARADC_THRES1_LOW + description: saradc thres1 monitor thres + bitOffset: 18 + bitWidth: 13 + access: read-write + - register: + name: THRES_CTRL + description: digital saradc configure register + addressOffset: 60 + size: 32 + fields: + - name: APB_SARADC_THRES_ALL_EN + description: enable thres to all channel + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES1_EN + description: enable thres1 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES0_EN + description: enable thres0 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_ENA + description: digital saradc int register + addressOffset: 64 + size: 32 + fields: + - name: APB_SARADC_TSENS_INT_ENA + description: tsens low interrupt enable + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES1_LOW_INT_ENA + description: saradc thres1 low interrupt enable + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES0_LOW_INT_ENA + description: saradc thres0 low interrupt enable + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES1_HIGH_INT_ENA + description: saradc thres1 high interrupt enable + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES0_HIGH_INT_ENA + description: saradc thres0 high interrupt enable + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: APB_SARADC2_DONE_INT_ENA + description: saradc2 done interrupt enable + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: APB_SARADC1_DONE_INT_ENA + description: saradc1 done interrupt enable + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: digital saradc int register + addressOffset: 68 + size: 32 + fields: + - name: APB_SARADC_TSENS_INT_RAW + description: saradc tsens interrupt raw + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES1_LOW_INT_RAW + description: saradc thres1 low interrupt raw + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES0_LOW_INT_RAW + description: saradc thres0 low interrupt raw + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES1_HIGH_INT_RAW + description: saradc thres1 high interrupt raw + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES0_HIGH_INT_RAW + description: saradc thres0 high interrupt raw + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: APB_SARADC2_DONE_INT_RAW + description: saradc2 done interrupt raw + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: APB_SARADC1_DONE_INT_RAW + description: saradc1 done interrupt raw + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: digital saradc int register + addressOffset: 72 + size: 32 + fields: + - name: APB_SARADC_TSENS_INT_ST + description: saradc tsens interrupt state + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: APB_SARADC_THRES1_LOW_INT_ST + description: saradc thres1 low interrupt state + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: APB_SARADC_THRES0_LOW_INT_ST + description: saradc thres0 low interrupt state + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: APB_SARADC_THRES1_HIGH_INT_ST + description: saradc thres1 high interrupt state + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: APB_SARADC_THRES0_HIGH_INT_ST + description: saradc thres0 high interrupt state + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: APB_SARADC2_DONE_INT_ST + description: saradc2 done interrupt state + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: APB_SARADC1_DONE_INT_ST + description: saradc1 done interrupt state + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: digital saradc int register + addressOffset: 76 + size: 32 + fields: + - name: APB_SARADC_TSENS_INT_CLR + description: saradc tsens interrupt clear + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: APB_SARADC_THRES1_LOW_INT_CLR + description: saradc thres1 low interrupt clear + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: APB_SARADC_THRES0_LOW_INT_CLR + description: saradc thres0 low interrupt clear + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: APB_SARADC_THRES1_HIGH_INT_CLR + description: saradc thres1 high interrupt clear + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: APB_SARADC_THRES0_HIGH_INT_CLR + description: saradc thres0 high interrupt clear + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: APB_SARADC2_DONE_INT_CLR + description: saradc2 done interrupt clear + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: APB_SARADC1_DONE_INT_CLR + description: saradc1 done interrupt clear + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: DMA_CONF + description: digital saradc configure register + addressOffset: 80 + size: 32 + resetValue: 255 + fields: + - name: APB_ADC_EOF_NUM + description: the dma_in_suc_eof gen when sample cnt = spi_eof_num + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: APB_ADC_RESET_FSM + description: reset_apb_adc_state + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: APB_ADC_TRANS + description: enable apb_adc use spi_dma + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CLKM_CONF + description: digital saradc configure register + addressOffset: 84 + size: 32 + resetValue: 4 + fields: + - name: CLKM_DIV_NUM + description: Integral I2S clock divider value + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CLKM_DIV_B + description: Fractional clock divider numerator value + bitOffset: 8 + bitWidth: 6 + access: read-write + - name: CLKM_DIV_A + description: Fractional clock divider denominator value + bitOffset: 14 + bitWidth: 6 + access: read-write + - name: CLK_EN + description: reg clk en + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CLK_SEL + description: Set this bit to enable clk_apll + bitOffset: 21 + bitWidth: 2 + access: read-write + - register: + name: APB_TSENS_CTRL + description: digital tsens configure register + addressOffset: 88 + size: 32 + resetValue: 98432 + fields: + - name: TSENS_OUT + description: temperature sensor data out + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: TSENS_IN_INV + description: invert temperature sensor data + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TSENS_CLK_DIV + description: temperature sensor clock divider + bitOffset: 14 + bitWidth: 8 + access: read-write + - name: TSENS_PU + description: temperature sensor power up + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: TSENS_CTRL2 + description: digital tsens configure register + addressOffset: 92 + size: 32 + resetValue: 16386 + fields: + - name: TSENS_XPD_WAIT + description: the time that power up tsens need wait + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: TSENS_XPD_FORCE + description: force power up tsens + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: TSENS_CLK_INV + description: inv tsens clk + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TSENS_CLK_SEL + description: tsens clk select + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: CALI + description: digital saradc configure register + addressOffset: 96 + size: 32 + resetValue: 32768 + fields: + - name: APB_SARADC_CALI_CFG + description: saradc cali factor + bitOffset: 0 + bitWidth: 17 + access: read-write + - register: + name: APB_TSENS_WAKE + description: digital tsens configure register + addressOffset: 100 + size: 32 + resetValue: 65280 + fields: + - name: WAKEUP_TH_LOW + description: reg_wakeup_th_low + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: WAKEUP_TH_HIGH + description: reg_wakeup_th_high + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: WAKEUP_OVER_UPPER_TH + description: reg_wakeup_over_upper_th + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: WAKEUP_MODE + description: reg_wakeup_mode + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: WAKEUP_EN + description: reg_wakeup_en + bitOffset: 18 + bitWidth: 1 + access: read-write + - register: + name: APB_TSENS_SAMPLE + description: digital tsens configure register + addressOffset: 104 + size: 32 + resetValue: 20 + fields: + - name: TSENS_SAMPLE_RATE + description: HW sample rate + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: TSENS_SAMPLE_EN + description: HW sample en + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: CTRL_DATE + description: version + addressOffset: 1020 + size: 32 + resetValue: 35676736 + fields: + - name: DATE + description: version + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: ASSIST_DEBUG + description: Debug Assist + groupName: ASSIST_DEBUG + baseAddress: 1611407360 + addressBlock: + - offset: 0 + size: 128 + usage: registers + interrupt: + - name: ASSIST_DEBUG + value: 26 + registers: + - register: + name: CORE_0_MONTR_ENA + description: core0 monitor enable configuration register + addressOffset: 0 + size: 32 + fields: + - name: CORE_0_AREA_DRAM0_0_RD_ENA + description: Core0 dram0 area0 read monitor enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_0_WR_ENA + description: Core0 dram0 area0 write monitor enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_1_RD_ENA + description: Core0 dram0 area1 read monitor enable + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_1_WR_ENA + description: Core0 dram0 area1 write monitor enable + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_0_RD_ENA + description: Core0 PIF area0 read monitor enable + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_0_WR_ENA + description: Core0 PIF area0 write monitor enable + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_1_RD_ENA + description: Core0 PIF area1 read monitor enable + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_1_WR_ENA + description: Core0 PIF area1 write monitor enable + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CORE_0_SP_SPILL_MIN_ENA + description: Core0 stackpoint underflow monitor enable + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CORE_0_SP_SPILL_MAX_ENA + description: Core0 stackpoint overflow monitor enable + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CORE_0_IRAM0_EXCEPTION_MONITOR_ENA + description: IBUS busy monitor enable + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CORE_0_DRAM0_EXCEPTION_MONITOR_ENA + description: DBUS busy monitor enbale + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_INTR_RAW + description: core0 monitor interrupt status register + addressOffset: 4 + size: 32 + fields: + - name: CORE_0_AREA_DRAM0_0_RD_RAW + description: Core0 dram0 area0 read monitor interrupt status + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_DRAM0_0_WR_RAW + description: Core0 dram0 area0 write monitor interrupt status + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_DRAM0_1_RD_RAW + description: Core0 dram0 area1 read monitor interrupt status + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_DRAM0_1_WR_RAW + description: Core0 dram0 area1 write monitor interrupt status + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_PIF_0_RD_RAW + description: Core0 PIF area0 read monitor interrupt status + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_PIF_0_WR_RAW + description: Core0 PIF area0 write monitor interrupt status + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_PIF_1_RD_RAW + description: Core0 PIF area1 read monitor interrupt status + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_PIF_1_WR_RAW + description: Core0 PIF area1 write monitor interrupt status + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: CORE_0_SP_SPILL_MIN_RAW + description: Core0 stackpoint underflow monitor interrupt status + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: CORE_0_SP_SPILL_MAX_RAW + description: Core0 stackpoint overflow monitor interrupt status + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: CORE_0_IRAM0_EXCEPTION_MONITOR_RAW + description: IBUS busy monitor interrupt status + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: CORE_0_DRAM0_EXCEPTION_MONITOR_RAW + description: DBUS busy monitor initerrupt status + bitOffset: 11 + bitWidth: 1 + access: read-only + - register: + name: CORE_0_INTR_ENA + description: core0 monitor interrupt enable register + addressOffset: 8 + size: 32 + fields: + - name: CORE_0_AREA_DRAM0_0_RD_INTR_ENA + description: Core0 dram0 area0 read monitor interrupt enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_0_WR_INTR_ENA + description: Core0 dram0 area0 write monitor interrupt enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_1_RD_INTR_ENA + description: Core0 dram0 area1 read monitor interrupt enable + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_1_WR_INTR_ENA + description: Core0 dram0 area1 write monitor interrupt enable + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_0_RD_INTR_ENA + description: Core0 PIF area0 read monitor interrupt enable + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_0_WR_INTR_ENA + description: Core0 PIF area0 write monitor interrupt enable + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_1_RD_INTR_ENA + description: Core0 PIF area1 read monitor interrupt enable + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_1_WR_INTR_ENA + description: Core0 PIF area1 write monitor interrupt enable + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CORE_0_SP_SPILL_MIN_INTR_ENA + description: Core0 stackpoint underflow monitor interrupt enable + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CORE_0_SP_SPILL_MAX_INTR_ENA + description: Core0 stackpoint overflow monitor interrupt enable + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA + description: IBUS busy monitor interrupt enable + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA + description: DBUS busy monitor interrupt enbale + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_INTR_CLR + description: core0 monitor interrupt clr register + addressOffset: 12 + size: 32 + fields: + - name: CORE_0_AREA_DRAM0_0_RD_CLR + description: Core0 dram0 area0 read monitor interrupt clr + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CORE_0_AREA_DRAM0_0_WR_CLR + description: Core0 dram0 area0 write monitor interrupt clr + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CORE_0_AREA_DRAM0_1_RD_CLR + description: Core0 dram0 area1 read monitor interrupt clr + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CORE_0_AREA_DRAM0_1_WR_CLR + description: Core0 dram0 area1 write monitor interrupt clr + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: CORE_0_AREA_PIF_0_RD_CLR + description: Core0 PIF area0 read monitor interrupt clr + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: CORE_0_AREA_PIF_0_WR_CLR + description: Core0 PIF area0 write monitor interrupt clr + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CORE_0_AREA_PIF_1_RD_CLR + description: Core0 PIF area1 read monitor interrupt clr + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: CORE_0_AREA_PIF_1_WR_CLR + description: Core0 PIF area1 write monitor interrupt clr + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: CORE_0_SP_SPILL_MIN_CLR + description: Core0 stackpoint underflow monitor interrupt clr + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: CORE_0_SP_SPILL_MAX_CLR + description: Core0 stackpoint overflow monitor interrupt clr + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: CORE_0_IRAM0_EXCEPTION_MONITOR_CLR + description: IBUS busy monitor interrupt clr + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: CORE_0_DRAM0_EXCEPTION_MONITOR_CLR + description: DBUS busy monitor interrupt clr + bitOffset: 11 + bitWidth: 1 + access: write-only + - register: + name: CORE_0_AREA_DRAM0_0_MIN + description: core0 dram0 region0 addr configuration register + addressOffset: 16 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_AREA_DRAM0_0_MIN + description: Core0 dram0 region0 start addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_DRAM0_0_MAX + description: core0 dram0 region0 addr configuration register + addressOffset: 20 + size: 32 + fields: + - name: CORE_0_AREA_DRAM0_0_MAX + description: Core0 dram0 region0 end addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_DRAM0_1_MIN + description: core0 dram0 region1 addr configuration register + addressOffset: 24 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_AREA_DRAM0_1_MIN + description: Core0 dram0 region1 start addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_DRAM0_1_MAX + description: core0 dram0 region1 addr configuration register + addressOffset: 28 + size: 32 + fields: + - name: CORE_0_AREA_DRAM0_1_MAX + description: Core0 dram0 region1 end addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_PIF_0_MIN + description: core0 PIF region0 addr configuration register + addressOffset: 32 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_AREA_PIF_0_MIN + description: Core0 PIF region0 start addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_PIF_0_MAX + description: core0 PIF region0 addr configuration register + addressOffset: 36 + size: 32 + fields: + - name: CORE_0_AREA_PIF_0_MAX + description: Core0 PIF region0 end addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_PIF_1_MIN + description: core0 PIF region1 addr configuration register + addressOffset: 40 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_AREA_PIF_1_MIN + description: Core0 PIF region1 start addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_PIF_1_MAX + description: core0 PIF region1 addr configuration register + addressOffset: 44 + size: 32 + fields: + - name: CORE_0_AREA_PIF_1_MAX + description: Core0 PIF region1 end addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_PC + description: core0 area pc status register + addressOffset: 48 + size: 32 + fields: + - name: CORE_0_AREA_PC + description: the stackpointer when first touch region monitor interrupt + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_AREA_SP + description: core0 area sp status register + addressOffset: 52 + size: 32 + fields: + - name: CORE_0_AREA_SP + description: the PC when first touch region monitor interrupt + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_SP_MIN + description: stack min value + addressOffset: 56 + size: 32 + fields: + - name: CORE_0_SP_MIN + description: core0 sp region configuration regsiter + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_SP_MAX + description: stack max value + addressOffset: 60 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_SP_MAX + description: core0 sp pc status register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_SP_PC + description: stack monitor pc status register + addressOffset: 64 + size: 32 + fields: + - name: CORE_0_SP_PC + description: This regsiter stores the PC when trigger stack monitor. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_RCD_EN + description: record enable configuration register + addressOffset: 68 + size: 32 + fields: + - name: CORE_0_RCD_RECORDEN + description: Set 1 to enable record PC + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_RCD_PDEBUGEN + description: "Set 1 to enable cpu pdebug function, must set this bit can get cpu PC" + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_RCD_PDEBUGPC + description: record status regsiter + addressOffset: 72 + size: 32 + fields: + - name: CORE_0_RCD_PDEBUGPC + description: recorded PC + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_RCD_PDEBUGSP + description: record status regsiter + addressOffset: 76 + size: 32 + fields: + - name: CORE_0_RCD_PDEBUGSP + description: recorded sp + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_IRAM0_EXCEPTION_MONITOR_0 + description: exception monitor status register0 + addressOffset: 80 + size: 32 + fields: + - name: CORE_0_IRAM0_RECORDING_ADDR_0 + description: reg_core_0_iram0_recording_addr_0 + bitOffset: 0 + bitWidth: 24 + access: read-only + - name: CORE_0_IRAM0_RECORDING_WR_0 + description: reg_core_0_iram0_recording_wr_0 + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: CORE_0_IRAM0_RECORDING_LOADSTORE_0 + description: reg_core_0_iram0_recording_loadstore_0 + bitOffset: 25 + bitWidth: 1 + access: read-only + - register: + name: CORE_0_IRAM0_EXCEPTION_MONITOR_1 + description: exception monitor status register1 + addressOffset: 84 + size: 32 + fields: + - name: CORE_0_IRAM0_RECORDING_ADDR_1 + description: reg_core_0_iram0_recording_addr_1 + bitOffset: 0 + bitWidth: 24 + access: read-only + - name: CORE_0_IRAM0_RECORDING_WR_1 + description: reg_core_0_iram0_recording_wr_1 + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: CORE_0_IRAM0_RECORDING_LOADSTORE_1 + description: reg_core_0_iram0_recording_loadstore_1 + bitOffset: 25 + bitWidth: 1 + access: read-only + - register: + name: CORE_0_DRAM0_EXCEPTION_MONITOR_0 + description: exception monitor status register2 + addressOffset: 88 + size: 32 + fields: + - name: CORE_0_DRAM0_RECORDING_ADDR_0 + description: reg_core_0_dram0_recording_addr_0 + bitOffset: 0 + bitWidth: 24 + access: read-only + - name: CORE_0_DRAM0_RECORDING_WR_0 + description: reg_core_0_dram0_recording_wr_0 + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: CORE_0_DRAM0_RECORDING_BYTEEN_0 + description: reg_core_0_dram0_recording_byteen_0 + bitOffset: 25 + bitWidth: 4 + access: read-only + - register: + name: CORE_0_DRAM0_EXCEPTION_MONITOR_1 + description: exception monitor status register3 + addressOffset: 92 + size: 32 + fields: + - name: CORE_0_DRAM0_RECORDING_PC_0 + description: reg_core_0_dram0_recording_pc_0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_DRAM0_EXCEPTION_MONITOR_2 + description: exception monitor status register4 + addressOffset: 96 + size: 32 + fields: + - name: CORE_0_DRAM0_RECORDING_ADDR_1 + description: reg_core_0_dram0_recording_addr_1 + bitOffset: 0 + bitWidth: 24 + access: read-only + - name: CORE_0_DRAM0_RECORDING_WR_1 + description: reg_core_0_dram0_recording_wr_1 + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: CORE_0_DRAM0_RECORDING_BYTEEN_1 + description: reg_core_0_dram0_recording_byteen_1 + bitOffset: 25 + bitWidth: 4 + access: read-only + - register: + name: CORE_0_DRAM0_EXCEPTION_MONITOR_3 + description: exception monitor status register5 + addressOffset: 100 + size: 32 + fields: + - name: CORE_0_DRAM0_RECORDING_PC_1 + description: reg_core_0_dram0_recording_pc_1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 + description: exception monitor status register6 + addressOffset: 104 + size: 32 + fields: + - name: CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 + description: reg_core_x_iram0_dram0_limit_cycle_0 + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 + description: exception monitor status register7 + addressOffset: 108 + size: 32 + fields: + - name: CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 + description: reg_core_x_iram0_dram0_limit_cycle_1 + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: C0RE_0_LASTPC_BEFORE_EXCEPTION + description: cpu status register + addressOffset: 112 + size: 32 + fields: + - name: CORE_0_LASTPC_BEFORE_EXC + description: "cpu's lastpc before exception" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: C0RE_0_DEBUG_MODE + description: cpu status register + addressOffset: 116 + size: 32 + fields: + - name: CORE_0_DEBUG_MODE + description: "cpu debug mode status, 1 means cpu enter debug mode." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_0_DEBUG_MODULE_ACTIVE + description: cpu debug_module active status + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: CLOCK_GATE + description: clock register + addressOffset: 120 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: Set 1 force on the clock gate + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: version register + addressOffset: 1020 + size: 32 + resetValue: 34640176 + fields: + - name: ASSIST_DEBUG_DATE + description: version register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: ATOMIC + description: Atomic Locker + groupName: ATOMIC + baseAddress: 1610682368 + addressBlock: + - offset: 0 + size: 20 + usage: registers + registers: + - register: + name: ADDR_LOCK + description: hardware lock regsiter + addressOffset: 0 + size: 32 + fields: + - name: LOCK + description: "read to acquire hardware lock, write to release hardware lock" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: LR_ADDR + description: gloable lr address regsiter + addressOffset: 4 + size: 32 + fields: + - name: GLOABLE_LR_ADDR + description: backup gloable address + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LR_VALUE + description: gloable lr value regsiter + addressOffset: 8 + size: 32 + fields: + - name: GLOABLE_LR_VALUE + description: backup gloable value + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOCK_STATUS + description: lock status regsiter + addressOffset: 12 + size: 32 + fields: + - name: LOCK_STATUS + description: read hareware lock status for debug + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: COUNTER + description: wait counter register + addressOffset: 16 + size: 32 + fields: + - name: WAIT_COUNTER + description: delay counter + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: DMA + description: DMA (Direct Memory Access) Controller + groupName: DMA + baseAddress: 1611137024 + addressBlock: + - offset: 0 + size: 420 + usage: registers + interrupt: + - name: DMA_IN_CH0 + value: 66 + - name: DMA_IN_CH1 + value: 67 + - name: DMA_IN_CH2 + value: 68 + - name: DMA_OUT_CH0 + value: 69 + - name: DMA_OUT_CH1 + value: 70 + - name: DMA_OUT_CH2 + value: 71 + registers: + - cluster: + dim: 3 + dimIncrement: 16 + dimIndex: "0,1,2" + name: IN_INT_CH%s + description: "Cluster IN_INT_CH%s, containing IN_INT_RAW_CH?, IN_INT_ST_CH?, IN_INT_ENA_CH?, IN_INT_CLR_CH?" + addressOffset: 0 + children: + - register: + name: RAW + description: Raw status interrupt of channel 0 + addressOffset: 0 + size: 32 + fields: + - name: IN_DONE + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF + description: The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR + description: The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY + description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF + description: This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF + description: This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: ST + description: Masked interrupt of channel 0 + addressOffset: 4 + size: 32 + fields: + - name: IN_DONE + description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: IN_SUC_EOF + description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: IN_ERR_EOF + description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: IN_DSCR_ERR + description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: IN_DSCR_EMPTY + description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: INFIFO_OVF + description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: INFIFO_UDF + description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: ENA + description: Interrupt enable bits of channel 0 + addressOffset: 8 + size: 32 + fields: + - name: IN_DONE + description: The interrupt enable bit for the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF + description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF + description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR + description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY + description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF + description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF + description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: CLR + description: Interrupt clear bits of channel 0 + addressOffset: 12 + size: 32 + fields: + - name: IN_DONE + description: Set this bit to clear the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: IN_SUC_EOF + description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: IN_ERR_EOF + description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: IN_DSCR_ERR + description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: IN_DSCR_EMPTY + description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: INFIFO_OVF + description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: INFIFO_UDF + description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - cluster: + dim: 3 + dimIncrement: 16 + dimIndex: "0,1,2" + name: OUT_INT_CH%s + description: "Cluster OUT_INT_CH%s, containing OUT_INT_RAW_CH?, OUT_INT_ST_CH?, OUT_INT_ENA_CH?, OUT_INT_CLR_CH?" + addressOffset: 48 + children: + - register: + name: RAW + description: Raw status interrupt of channel 0 + addressOffset: 0 + size: 32 + fields: + - name: OUT_DONE + description: The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_EOF + description: The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR + description: The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel 0. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF + description: The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF + description: This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF + description: This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: ST + description: Masked interrupt of channel 0 + addressOffset: 4 + size: 32 + fields: + - name: OUT_DONE + description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUT_EOF + description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: OUT_DSCR_ERR + description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: OUT_TOTAL_EOF + description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: OUTFIFO_OVF + description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: OUTFIFO_UDF + description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: ENA + description: Interrupt enable bits of channel 0 + addressOffset: 8 + size: 32 + fields: + - name: OUT_DONE + description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_EOF + description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR + description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF + description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF + description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF + description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: CLR + description: Interrupt clear bits of channel 0 + addressOffset: 12 + size: 32 + fields: + - name: OUT_DONE + description: Set this bit to clear the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: OUT_EOF + description: Set this bit to clear the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: OUT_DSCR_ERR + description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: OUT_TOTAL_EOF + description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: OUTFIFO_OVF + description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: OUTFIFO_UDF + description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: AHB_TEST + description: reserved + addressOffset: 96 + size: 32 + fields: + - name: AHB_TESTMODE + description: reserved + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: AHB_TESTADDR + description: reserved + bitOffset: 4 + bitWidth: 2 + access: read-write + - register: + name: MISC_CONF + description: MISC register + addressOffset: 100 + size: 32 + fields: + - name: AHBM_RST_INTER + description: Set this bit then clear this bit to reset the internal ahb FSM. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ARB_PRI_DIS + description: Set this bit to disable priority arbitration function. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers." + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 104 + size: 32 + resetValue: 35660368 + fields: + - name: DATE + description: register version. + bitOffset: 0 + bitWidth: 32 + access: read-write + - cluster: + dim: 3 + dimIncrement: 192 + dimIndex: "0,1,2" + name: CH%s + description: "Cluster CH%s, containing IN_CONF0_CH?, IN_CONF1_CH?, INFIFO_STATUS_CH?, IN_POP_CH?, IN_LINK_CH?, IN_STATE_CH?, IN_SUC_EOF_DES_ADDR_CH?, IN_ERR_EOF_DES_ADDR_CH?, IN_DSCR_CH?, IN_DSCR_BF0_CH?, IN_DSCR_BF1_CH?, IN_PRI_CH?, IN_PERI_SEL_CH?, OUT_CONF0_CH?, OUT_CONF1_CH?, OUTFIFO_STATUS_CH?, OUT_PUSH_CH?, OUT_LINK_CH?, OUT_STATE_CH?, OUT_EOF_DES_ADDR_CH?, OUT_EOF_BFR_DES_ADDR_CH?, OUT_DSCR_CH?, OUT_DSCR_BF0_CH?, OUT_DSCR_BF1_CH?, OUT_PRI_CH?, OUT_PERI_SEL_CH?" + addressOffset: 112 + children: + - register: + name: IN_CONF0 + description: Configure 0 register of Rx channel 0 + addressOffset: 0 + size: 32 + fields: + - name: IN_RST + description: This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_LOOP_TEST + description: reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: INDSCR_BURST_EN + description: Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DATA_BURST_EN + description: Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MEM_TRANS_EN + description: Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IN_ETM_EN + description: "Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task." + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: IN_CONF1 + description: Configure 1 register of Rx channel 0 + addressOffset: 4 + size: 32 + fields: + - name: IN_CHECK_OWNER + description: Set this bit to enable checking the owner attribute of the link descriptor. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: INFIFO_STATUS + description: Receive FIFO status of Rx channel 0 + addressOffset: 8 + size: 32 + resetValue: 125829123 + fields: + - name: INFIFO_FULL + description: L1 Rx FIFO full signal for Rx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: INFIFO_EMPTY + description: L1 Rx FIFO empty signal for Rx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: INFIFO_CNT + description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + bitOffset: 2 + bitWidth: 6 + access: read-only + - name: IN_REMAIN_UNDER_1B + description: reserved + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: IN_REMAIN_UNDER_2B + description: reserved + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: IN_REMAIN_UNDER_3B + description: reserved + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: IN_REMAIN_UNDER_4B + description: reserved + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: IN_BUF_HUNGRY + description: reserved + bitOffset: 27 + bitWidth: 1 + access: read-only + - register: + name: IN_POP + description: Pop control register of Rx channel 0 + addressOffset: 12 + size: 32 + resetValue: 2048 + fields: + - name: INFIFO_RDATA + description: This register stores the data popping from DMA FIFO. + bitOffset: 0 + bitWidth: 12 + access: read-only + - name: INFIFO_POP + description: Set this bit to pop data from DMA FIFO. + bitOffset: 12 + bitWidth: 1 + access: write-only + - register: + name: IN_LINK + description: Link descriptor configure and control register of Rx channel 0 + addressOffset: 16 + size: 32 + resetValue: 17825792 + fields: + - name: INLINK_ADDR + description: "This register stores the 20 least significant bits of the first inlink descriptor's address." + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: INLINK_AUTO_RET + description: "Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: INLINK_STOP + description: Set this bit to stop dealing with the inlink descriptors. + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: INLINK_START + description: Set this bit to start dealing with the inlink descriptors. + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: INLINK_RESTART + description: Set this bit to mount a new inlink descriptor. + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: INLINK_PARK + description: "1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working." + bitOffset: 24 + bitWidth: 1 + access: read-only + - register: + name: IN_STATE + description: Receive status of Rx channel 0 + addressOffset: 20 + size: 32 + fields: + - name: INLINK_DSCR_ADDR + description: "This register stores the current inlink descriptor's address." + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: IN_DSCR_STATE + description: reserved + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: IN_STATE + description: reserved + bitOffset: 20 + bitWidth: 3 + access: read-only + - register: + name: IN_SUC_EOF_DES_ADDR + description: Inlink descriptor address when EOF occurs of Rx channel 0 + addressOffset: 24 + size: 32 + fields: + - name: IN_SUC_EOF_DES_ADDR + description: This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_ERR_EOF_DES_ADDR + description: Inlink descriptor address when errors occur of Rx channel 0 + addressOffset: 28 + size: 32 + fields: + - name: IN_ERR_EOF_DES_ADDR + description: This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR + description: Current inlink descriptor address of Rx channel 0 + addressOffset: 32 + size: 32 + fields: + - name: INLINK_DSCR + description: The address of the current inlink descriptor x. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_BF0 + description: The last inlink descriptor address of Rx channel 0 + addressOffset: 36 + size: 32 + fields: + - name: INLINK_DSCR_BF0 + description: The address of the last inlink descriptor x-1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_BF1 + description: The second-to-last inlink descriptor address of Rx channel 0 + addressOffset: 40 + size: 32 + fields: + - name: INLINK_DSCR_BF1 + description: The address of the second-to-last inlink descriptor x-2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_PRI + description: Priority register of Rx channel 0 + addressOffset: 44 + size: 32 + fields: + - name: RX_PRI + description: The priority of Rx channel 0. The larger of the value the higher of the priority. + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: IN_PERI_SEL + description: Peripheral selection of Rx channel 0 + addressOffset: 48 + size: 32 + resetValue: 63 + fields: + - name: PERI_IN_SEL + description: "This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. 10~15: Dummy" + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: OUT_CONF0 + description: Configure 0 register of Tx channel 1 + addressOffset: 96 + size: 32 + resetValue: 8 + fields: + - name: OUT_RST + description: This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_LOOP_TEST + description: reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_AUTO_WRBACK + description: Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_EOF_MODE + description: "EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTDSCR_BURST_EN + description: Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUT_DATA_BURST_EN + description: Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUT_ETM_EN + description: "Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm task." + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: OUT_CONF1 + description: Configure 1 register of Tx channel 0 + addressOffset: 100 + size: 32 + fields: + - name: OUT_CHECK_OWNER + description: Set this bit to enable checking the owner attribute of the link descriptor. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: OUTFIFO_STATUS + description: Transmit FIFO status of Tx channel 0 + addressOffset: 104 + size: 32 + resetValue: 125829122 + fields: + - name: OUTFIFO_FULL + description: L1 Tx FIFO full signal for Tx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY + description: L1 Tx FIFO empty signal for Tx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: OUTFIFO_CNT + description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + bitOffset: 2 + bitWidth: 6 + access: read-only + - name: OUT_REMAIN_UNDER_1B + description: reserved + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: OUT_REMAIN_UNDER_2B + description: reserved + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: OUT_REMAIN_UNDER_3B + description: reserved + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: OUT_REMAIN_UNDER_4B + description: reserved + bitOffset: 26 + bitWidth: 1 + access: read-only + - register: + name: OUT_PUSH + description: Push control register of Rx channel 0 + addressOffset: 108 + size: 32 + fields: + - name: OUTFIFO_WDATA + description: This register stores the data that need to be pushed into DMA FIFO. + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: OUTFIFO_PUSH + description: Set this bit to push data into DMA FIFO. + bitOffset: 9 + bitWidth: 1 + access: write-only + - register: + name: OUT_LINK + description: Link descriptor configure and control register of Tx channel 0 + addressOffset: 112 + size: 32 + resetValue: 8388608 + fields: + - name: OUTLINK_ADDR + description: "This register stores the 20 least significant bits of the first outlink descriptor's address." + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: OUTLINK_STOP + description: Set this bit to stop dealing with the outlink descriptors. + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: OUTLINK_START + description: Set this bit to start dealing with the outlink descriptors. + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: OUTLINK_RESTART + description: Set this bit to restart a new outlink from the last address. + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: OUTLINK_PARK + description: "1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working." + bitOffset: 23 + bitWidth: 1 + access: read-only + - register: + name: OUT_STATE + description: Transmit status of Tx channel 0 + addressOffset: 116 + size: 32 + fields: + - name: OUTLINK_DSCR_ADDR + description: "This register stores the current outlink descriptor's address." + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: OUT_DSCR_STATE + description: reserved + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: OUT_STATE + description: reserved + bitOffset: 20 + bitWidth: 3 + access: read-only + - register: + name: OUT_EOF_DES_ADDR + description: Outlink descriptor address when EOF occurs of Tx channel 0 + addressOffset: 120 + size: 32 + fields: + - name: OUT_EOF_DES_ADDR + description: This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_EOF_BFR_DES_ADDR + description: The last outlink descriptor address when EOF occurs of Tx channel 0 + addressOffset: 124 + size: 32 + fields: + - name: OUT_EOF_BFR_DES_ADDR + description: This register stores the address of the outlink descriptor before the last outlink descriptor. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR + description: Current inlink descriptor address of Tx channel 0 + addressOffset: 128 + size: 32 + fields: + - name: OUTLINK_DSCR + description: The address of the current outlink descriptor y. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_BF0 + description: The last inlink descriptor address of Tx channel 0 + addressOffset: 132 + size: 32 + fields: + - name: OUTLINK_DSCR_BF0 + description: The address of the last outlink descriptor y-1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_BF1 + description: The second-to-last inlink descriptor address of Tx channel 0 + addressOffset: 136 + size: 32 + fields: + - name: OUTLINK_DSCR_BF1 + description: The address of the second-to-last inlink descriptor x-2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_PRI + description: Priority register of Tx channel 0. + addressOffset: 140 + size: 32 + fields: + - name: TX_PRI + description: The priority of Tx channel 0. The larger of the value the higher of the priority. + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: OUT_PERI_SEL + description: Peripheral selection of Tx channel 0 + addressOffset: 144 + size: 32 + resetValue: 63 + fields: + - name: PERI_OUT_SEL + description: "This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. 10~15: Dummy" + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: DS + description: Digital Signature + groupName: DS + baseAddress: 1611186176 + addressBlock: + - offset: 0 + size: 2652 + usage: registers + registers: + - register: + dim: 128 + dimIncrement: 4 + name: "Y_MEM[%s]" + description: memory that stores Y + addressOffset: 0 + size: 32 + - register: + dim: 128 + dimIncrement: 4 + name: "M_MEM[%s]" + description: memory that stores M + addressOffset: 512 + size: 32 + - register: + dim: 128 + dimIncrement: 4 + name: "RB_MEM[%s]" + description: memory that stores Rb + addressOffset: 1024 + size: 32 + - register: + dim: 12 + dimIncrement: 4 + name: "BOX_MEM[%s]" + description: memory that stores BOX + addressOffset: 1536 + size: 32 + - register: + dim: 4 + dimIncrement: 4 + name: "IV_MEM[%s]" + description: memory that stores IV + addressOffset: 1584 + size: 32 + - register: + dim: 128 + dimIncrement: 4 + name: "X_MEM[%s]" + description: memory that stores X + addressOffset: 2048 + size: 32 + - register: + dim: 128 + dimIncrement: 4 + name: "Z_MEM[%s]" + description: memory that stores Z + addressOffset: 2560 + size: 32 + - register: + name: SET_START + description: DS start control register + addressOffset: 3584 + size: 32 + fields: + - name: SET_START + description: set this bit to start DS operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_CONTINUE + description: DS continue control register + addressOffset: 3588 + size: 32 + fields: + - name: SET_CONTINUE + description: set this bit to continue DS operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_FINISH + description: DS finish control register + addressOffset: 3592 + size: 32 + fields: + - name: SET_FINISH + description: Set this bit to finish DS process. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: QUERY_BUSY + description: DS query busy register + addressOffset: 3596 + size: 32 + fields: + - name: QUERY_BUSY + description: "digital signature state. 1'b0: idle, 1'b1: busy" + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: QUERY_KEY_WRONG + description: DS query key-wrong counter register + addressOffset: 3600 + size: 32 + fields: + - name: QUERY_KEY_WRONG + description: digital signature key wrong counter + bitOffset: 0 + bitWidth: 4 + access: read-only + - register: + name: QUERY_CHECK + description: DS query check result register + addressOffset: 3604 + size: 32 + fields: + - name: MD_ERROR + description: "MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PADDING_BAD + description: "padding checkout result. 1'b0: a good padding, 1'b1: a bad padding" + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: DS version control register + addressOffset: 3616 + size: 32 + resetValue: 538969624 + fields: + - name: DATE + description: ds version information + bitOffset: 0 + bitWidth: 30 + access: read-write + - name: ECC + description: ECC (ECC Hardware Accelerator) + groupName: ECC + baseAddress: 1611182080 + addressBlock: + - offset: 0 + size: 120 + usage: registers + interrupt: + - name: ECC + value: 76 + registers: + - register: + name: MULT_INT_RAW + description: "ECC interrupt raw register, valid in level." + addressOffset: 12 + size: 32 + fields: + - name: CALC_DONE_INT_RAW + description: The raw interrupt status bit for the ecc_calc_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: MULT_INT_ST + description: ECC interrupt status register. + addressOffset: 16 + size: 32 + fields: + - name: CALC_DONE_INT_ST + description: The masked interrupt status bit for the ecc_calc_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: MULT_INT_ENA + description: ECC interrupt enable register. + addressOffset: 20 + size: 32 + fields: + - name: CALC_DONE_INT_ENA + description: The interrupt enable bit for the ecc_calc_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: MULT_INT_CLR + description: ECC interrupt clear register. + addressOffset: 24 + size: 32 + fields: + - name: CALC_DONE_INT_CLR + description: Set this bit to clear the ecc_calc_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: MULT_CONF + description: ECC configure register + addressOffset: 28 + size: 32 + resetValue: 2147483648 + fields: + - name: START + description: Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after the caculatrion is done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RESET + description: Write 1 to reset ECC Accelerator. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: KEY_LENGTH + description: "The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SECURITY_MODE + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: Write 1 to force on register clock gate. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: WORK_MODE + description: "The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Division mode. 2: Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Reserved. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode." + bitOffset: 5 + bitWidth: 3 + access: read-write + - name: VERIFICATION_RESULT + description: "The verification result bit of ECC Accelerator, only valid when calculation is done." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: MEM_CLOCK_GATE_FORCE_ON + description: ECC memory clock gate force on register + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: MULT_DATE + description: Version control register + addressOffset: 252 + size: 32 + resetValue: 35656256 + fields: + - name: DATE + description: ECC mult version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + name: "K_MEM[%s]" + description: The memory that stores k. + addressOffset: 256 + size: 32 + - register: + dim: 8 + dimIncrement: 4 + name: "PX_MEM[%s]" + description: The memory that stores Px. + addressOffset: 288 + size: 32 + - register: + dim: 8 + dimIncrement: 4 + name: "PY_MEM[%s]" + description: The memory that stores Py. + addressOffset: 320 + size: 32 + - name: EFUSE + description: eFuse Controller + groupName: EFUSE + baseAddress: 1611335680 + addressBlock: + - offset: 0 + size: 464 + usage: registers + interrupt: + - name: EFUSE + value: 14 + registers: + - register: + name: PGM_DATA0 + description: Register 0 that stores data to be programmed. + addressOffset: 0 + size: 32 + fields: + - name: PGM_DATA_0 + description: Configures the 0th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA1 + description: Register 1 that stores data to be programmed. + addressOffset: 4 + size: 32 + fields: + - name: PGM_DATA_1 + description: Configures the 1st 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA2 + description: Register 2 that stores data to be programmed. + addressOffset: 8 + size: 32 + fields: + - name: PGM_DATA_2 + description: Configures the 2nd 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA3 + description: Register 3 that stores data to be programmed. + addressOffset: 12 + size: 32 + fields: + - name: PGM_DATA_3 + description: Configures the 3rd 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA4 + description: Register 4 that stores data to be programmed. + addressOffset: 16 + size: 32 + fields: + - name: PGM_DATA_4 + description: Configures the 4th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA5 + description: Register 5 that stores data to be programmed. + addressOffset: 20 + size: 32 + fields: + - name: PGM_DATA_5 + description: Configures the 5th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA6 + description: Register 6 that stores data to be programmed. + addressOffset: 24 + size: 32 + fields: + - name: PGM_DATA_6 + description: Configures the 6th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA7 + description: Register 7 that stores data to be programmed. + addressOffset: 28 + size: 32 + fields: + - name: PGM_DATA_7 + description: Configures the 7th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_CHECK_VALUE0 + description: Register 0 that stores the RS code to be programmed. + addressOffset: 32 + size: 32 + fields: + - name: PGM_RS_DATA_0 + description: Configures the 0th 32-bit RS code to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_CHECK_VALUE1 + description: Register 1 that stores the RS code to be programmed. + addressOffset: 36 + size: 32 + fields: + - name: PGM_RS_DATA_1 + description: Configures the 1st 32-bit RS code to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_CHECK_VALUE2 + description: Register 2 that stores the RS code to be programmed. + addressOffset: 40 + size: 32 + fields: + - name: PGM_RS_DATA_2 + description: Configures the 2nd 32-bit RS code to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RD_WR_DIS + description: BLOCK0 data register 0. + addressOffset: 44 + size: 32 + fields: + - name: WR_DIS + description: "Represents whether programming of individual eFuse memory bit is disabled or enabled. 1: Disabled. 0 Enabled." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_REPEAT_DATA0 + description: BLOCK0 data register 1. + addressOffset: 48 + size: 32 + fields: + - name: RD_DIS + description: "Represents whether reading of individual eFuse block(block4~block10) is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 0 + bitWidth: 7 + access: read-only + - name: SWAP_UART_SDIO_EN + description: "Represents whether pad of uart and sdio is swapped or not. 1: swapped. 0: not swapped." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DIS_ICACHE + description: "Represents whether icache is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DIS_USB_JTAG + description: "Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_ICACHE + description: "Represents whether icache is disabled or enabled in Download mode. 1: disabled. 0: enabled." + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: DIS_USB_SERIAL_JTAG + description: "Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: DIS_FORCE_DOWNLOAD + description: "Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SPI_DOWNLOAD_MSPI_DIS + description: "Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: DIS_CAN + description: "Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: JTAG_SEL_ENABLE + description: "Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled." + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SOFT_DIS_JTAG + description: "Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled." + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: DIS_PAD_JTAG + description: "Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled." + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_MANUAL_ENCRYPT + description: "Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled." + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: USB_DREFH + description: "Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV." + bitOffset: 21 + bitWidth: 2 + access: read-only + - name: USB_DREFL + description: "Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV." + bitOffset: 23 + bitWidth: 2 + access: read-only + - name: USB_EXCHG_PINS + description: "Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged." + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: VDD_SPI_AS_GPIO + description: "Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned." + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED0_2 + description: Reserved. + bitOffset: 27 + bitWidth: 2 + access: read-only + - name: RPT4_RESERVED0_1 + description: Reserved. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED0_0 + description: Reserved. + bitOffset: 30 + bitWidth: 2 + access: read-only + - register: + name: RD_REPEAT_DATA1 + description: BLOCK0 data register 2. + addressOffset: 52 + size: 32 + fields: + - name: RPT4_RESERVED1_0 + description: Reserved. + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: WDT_DELAY_SEL + description: "Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected." + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: SPI_BOOT_CRYPT_CNT + description: "Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 1: enabled. Even number of 1: disabled." + bitOffset: 18 + bitWidth: 3 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE0 + description: "Represents whether revoking first secure boot key is enabled or disabled. 1: enabled. 0: disabled." + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE1 + description: "Represents whether revoking second secure boot key is enabled or disabled. 1: enabled. 0: disabled." + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE2 + description: "Represents whether revoking third secure boot key is enabled or disabled. 1: enabled. 0: disabled." + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: KEY_PURPOSE_0 + description: Represents the purpose of Key0. + bitOffset: 24 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_1 + description: Represents the purpose of Key1. + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_REPEAT_DATA2 + description: BLOCK0 data register 3. + addressOffset: 56 + size: 32 + resetValue: 524288 + fields: + - name: KEY_PURPOSE_2 + description: Represents the purpose of Key2. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_3 + description: Represents the purpose of Key3. + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_4 + description: Represents the purpose of Key4. + bitOffset: 8 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_5 + description: Represents the purpose of Key5. + bitOffset: 12 + bitWidth: 4 + access: read-only + - name: DPA_SEC_LEVEL + description: Represents the spa secure level by configuring the clock random divide mode. + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: RPT4_RESERVED2_1 + description: Reserved. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: CRYPT_DPA_ENABLE + description: "Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled." + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_EN + description: "Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled." + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_AGGRESSIVE_REVOKE + description: "Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled." + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED2_0 + description: Reserved. + bitOffset: 22 + bitWidth: 6 + access: read-only + - name: FLASH_TPUW + description: "Represents the flash waiting time after power-up, in unit of ms. When the value less than 15, the waiting time is the programmed value. Otherwise, the waiting time is 2 times the programmed value." + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_REPEAT_DATA3 + description: BLOCK0 data register 4. + addressOffset: 60 + size: 32 + fields: + - name: DIS_DOWNLOAD_MODE + description: "Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DIS_DIRECT_BOOT + description: "Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: DIS_USB_PRINT + description: "Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED3_5 + description: Reserved. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + description: "Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ENABLE_SECURITY_DOWNLOAD + description: "Represents whether security download is enabled or disabled. 1: enabled. 0: disabled." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: UART_PRINT_CONTROL + description: "Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing." + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: RPT4_RESERVED3_4 + description: Reserved. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED3_3 + description: Reserved. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED3_2 + description: Reserved. + bitOffset: 10 + bitWidth: 2 + access: read-only + - name: RPT4_RESERVED3_1 + description: Reserved. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: FORCE_SEND_RESUME + description: "Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced." + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SECURE_VERSION + description: Represents the version used by ESP-IDF anti-rollback feature. + bitOffset: 14 + bitWidth: 16 + access: read-only + - name: SECURE_BOOT_DISABLE_FAST_WAKE + description: "Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled." + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED3_0 + description: Reserved. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: RD_REPEAT_DATA4 + description: BLOCK0 data register 5. + addressOffset: 64 + size: 32 + fields: + - name: RPT4_RESERVED4_1 + description: Reserved. + bitOffset: 0 + bitWidth: 24 + access: read-only + - name: RPT4_RESERVED4_0 + description: Reserved. + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: RD_MAC_SPI_SYS_0 + description: BLOCK1 data register $n. + addressOffset: 68 + size: 32 + fields: + - name: MAC_0 + description: Stores the low 32 bits of MAC address. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_MAC_SPI_SYS_1 + description: BLOCK1 data register $n. + addressOffset: 72 + size: 32 + fields: + - name: MAC_1 + description: Stores the high 16 bits of MAC address. + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: MAC_EXT + description: Stores the extended bits of MAC address. + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: RD_MAC_SPI_SYS_2 + description: BLOCK1 data register $n. + addressOffset: 76 + size: 32 + fields: + - name: ACTIVE_HP_DBIAS + description: Stores the active hp dbias. + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: ACTIVE_LP_DBIAS + description: Stores the active lp dbias. + bitOffset: 5 + bitWidth: 5 + access: read-only + - name: LSLP_HP_DBG + description: Stores the lslp hp dbg. + bitOffset: 10 + bitWidth: 2 + access: read-only + - name: LSLP_HP_DBIAS + description: Stores the lslp hp dbias. + bitOffset: 12 + bitWidth: 4 + access: read-only + - name: DSLP_LP_DBG + description: Stores the dslp lp dbg. + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: DSLP_LP_DBIAS + description: Stores the dslp lp dbias. + bitOffset: 19 + bitWidth: 4 + access: read-only + - name: DBIAS_VOL_GAP + description: Stores the hp and lp dbias vol gap. + bitOffset: 23 + bitWidth: 5 + access: read-only + - name: SPI_PAD_CONF_1 + description: Reserved. + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_MAC_SPI_SYS_3 + description: BLOCK1 data register $n. + addressOffset: 80 + size: 32 + fields: + - name: SPI_PAD_CONF_2 + description: Stores the second part of SPI_PAD_CONF. + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: SYS_DATA_PART0_0 + description: Stores the first 14 bits of the zeroth part of system data. + bitOffset: 18 + bitWidth: 14 + access: read-only + - register: + name: RD_MAC_SPI_SYS_4 + description: BLOCK1 data register $n. + addressOffset: 84 + size: 32 + fields: + - name: SYS_DATA_PART0_1 + description: Stores the first 32 bits of the zeroth part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_MAC_SPI_SYS_5 + description: BLOCK1 data register $n. + addressOffset: 88 + size: 32 + fields: + - name: SYS_DATA_PART0_2 + description: Stores the second 32 bits of the zeroth part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA0 + description: Register $n of BLOCK2 (system). + addressOffset: 92 + size: 32 + fields: + - name: SYS_DATA_PART1_0 + description: Stores the zeroth 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA1 + description: Register $n of BLOCK2 (system). + addressOffset: 96 + size: 32 + fields: + - name: SYS_DATA_PART1_1 + description: Stores the first 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA2 + description: Register $n of BLOCK2 (system). + addressOffset: 100 + size: 32 + fields: + - name: SYS_DATA_PART1_2 + description: Stores the second 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA3 + description: Register $n of BLOCK2 (system). + addressOffset: 104 + size: 32 + fields: + - name: SYS_DATA_PART1_3 + description: Stores the third 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA4 + description: Register $n of BLOCK2 (system). + addressOffset: 108 + size: 32 + fields: + - name: SYS_DATA_PART1_4 + description: Stores the fourth 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA5 + description: Register $n of BLOCK2 (system). + addressOffset: 112 + size: 32 + fields: + - name: SYS_DATA_PART1_5 + description: Stores the fifth 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA6 + description: Register $n of BLOCK2 (system). + addressOffset: 116 + size: 32 + fields: + - name: SYS_DATA_PART1_6 + description: Stores the sixth 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA7 + description: Register $n of BLOCK2 (system). + addressOffset: 120 + size: 32 + fields: + - name: SYS_DATA_PART1_7 + description: Stores the seventh 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA0 + description: Register $n of BLOCK3 (user). + addressOffset: 124 + size: 32 + fields: + - name: USR_DATA0 + description: Stores the zeroth 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA1 + description: Register $n of BLOCK3 (user). + addressOffset: 128 + size: 32 + fields: + - name: USR_DATA1 + description: Stores the first 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA2 + description: Register $n of BLOCK3 (user). + addressOffset: 132 + size: 32 + fields: + - name: USR_DATA2 + description: Stores the second 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA3 + description: Register $n of BLOCK3 (user). + addressOffset: 136 + size: 32 + fields: + - name: USR_DATA3 + description: Stores the third 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA4 + description: Register $n of BLOCK3 (user). + addressOffset: 140 + size: 32 + fields: + - name: USR_DATA4 + description: Stores the fourth 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA5 + description: Register $n of BLOCK3 (user). + addressOffset: 144 + size: 32 + fields: + - name: USR_DATA5 + description: Stores the fifth 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA6 + description: Register $n of BLOCK3 (user). + addressOffset: 148 + size: 32 + fields: + - name: USR_DATA6 + description: Stores the sixth 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA7 + description: Register $n of BLOCK3 (user). + addressOffset: 152 + size: 32 + fields: + - name: USR_DATA7 + description: Stores the seventh 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA0 + description: Register $n of BLOCK4 (KEY0). + addressOffset: 156 + size: 32 + fields: + - name: KEY0_DATA0 + description: Stores the zeroth 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA1 + description: Register $n of BLOCK4 (KEY0). + addressOffset: 160 + size: 32 + fields: + - name: KEY0_DATA1 + description: Stores the first 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA2 + description: Register $n of BLOCK4 (KEY0). + addressOffset: 164 + size: 32 + fields: + - name: KEY0_DATA2 + description: Stores the second 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA3 + description: Register $n of BLOCK4 (KEY0). + addressOffset: 168 + size: 32 + fields: + - name: KEY0_DATA3 + description: Stores the third 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA4 + description: Register $n of BLOCK4 (KEY0). + addressOffset: 172 + size: 32 + fields: + - name: KEY0_DATA4 + description: Stores the fourth 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA5 + description: Register $n of BLOCK4 (KEY0). + addressOffset: 176 + size: 32 + fields: + - name: KEY0_DATA5 + description: Stores the fifth 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA6 + description: Register $n of BLOCK4 (KEY0). + addressOffset: 180 + size: 32 + fields: + - name: KEY0_DATA6 + description: Stores the sixth 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA7 + description: Register $n of BLOCK4 (KEY0). + addressOffset: 184 + size: 32 + fields: + - name: KEY0_DATA7 + description: Stores the seventh 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA0 + description: Register $n of BLOCK5 (KEY1). + addressOffset: 188 + size: 32 + fields: + - name: KEY1_DATA0 + description: Stores the zeroth 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA1 + description: Register $n of BLOCK5 (KEY1). + addressOffset: 192 + size: 32 + fields: + - name: KEY1_DATA1 + description: Stores the first 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA2 + description: Register $n of BLOCK5 (KEY1). + addressOffset: 196 + size: 32 + fields: + - name: KEY1_DATA2 + description: Stores the second 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA3 + description: Register $n of BLOCK5 (KEY1). + addressOffset: 200 + size: 32 + fields: + - name: KEY1_DATA3 + description: Stores the third 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA4 + description: Register $n of BLOCK5 (KEY1). + addressOffset: 204 + size: 32 + fields: + - name: KEY1_DATA4 + description: Stores the fourth 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA5 + description: Register $n of BLOCK5 (KEY1). + addressOffset: 208 + size: 32 + fields: + - name: KEY1_DATA5 + description: Stores the fifth 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA6 + description: Register $n of BLOCK5 (KEY1). + addressOffset: 212 + size: 32 + fields: + - name: KEY1_DATA6 + description: Stores the sixth 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA7 + description: Register $n of BLOCK5 (KEY1). + addressOffset: 216 + size: 32 + fields: + - name: KEY1_DATA7 + description: Stores the seventh 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA0 + description: Register $n of BLOCK6 (KEY2). + addressOffset: 220 + size: 32 + fields: + - name: KEY2_DATA0 + description: Stores the zeroth 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA1 + description: Register $n of BLOCK6 (KEY2). + addressOffset: 224 + size: 32 + fields: + - name: KEY2_DATA1 + description: Stores the first 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA2 + description: Register $n of BLOCK6 (KEY2). + addressOffset: 228 + size: 32 + fields: + - name: KEY2_DATA2 + description: Stores the second 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA3 + description: Register $n of BLOCK6 (KEY2). + addressOffset: 232 + size: 32 + fields: + - name: KEY2_DATA3 + description: Stores the third 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA4 + description: Register $n of BLOCK6 (KEY2). + addressOffset: 236 + size: 32 + fields: + - name: KEY2_DATA4 + description: Stores the fourth 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA5 + description: Register $n of BLOCK6 (KEY2). + addressOffset: 240 + size: 32 + fields: + - name: KEY2_DATA5 + description: Stores the fifth 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA6 + description: Register $n of BLOCK6 (KEY2). + addressOffset: 244 + size: 32 + fields: + - name: KEY2_DATA6 + description: Stores the sixth 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA7 + description: Register $n of BLOCK6 (KEY2). + addressOffset: 248 + size: 32 + fields: + - name: KEY2_DATA7 + description: Stores the seventh 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA0 + description: Register $n of BLOCK7 (KEY3). + addressOffset: 252 + size: 32 + fields: + - name: KEY3_DATA0 + description: Stores the zeroth 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA1 + description: Register $n of BLOCK7 (KEY3). + addressOffset: 256 + size: 32 + fields: + - name: KEY3_DATA1 + description: Stores the first 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA2 + description: Register $n of BLOCK7 (KEY3). + addressOffset: 260 + size: 32 + fields: + - name: KEY3_DATA2 + description: Stores the second 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA3 + description: Register $n of BLOCK7 (KEY3). + addressOffset: 264 + size: 32 + fields: + - name: KEY3_DATA3 + description: Stores the third 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA4 + description: Register $n of BLOCK7 (KEY3). + addressOffset: 268 + size: 32 + fields: + - name: KEY3_DATA4 + description: Stores the fourth 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA5 + description: Register $n of BLOCK7 (KEY3). + addressOffset: 272 + size: 32 + fields: + - name: KEY3_DATA5 + description: Stores the fifth 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA6 + description: Register $n of BLOCK7 (KEY3). + addressOffset: 276 + size: 32 + fields: + - name: KEY3_DATA6 + description: Stores the sixth 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA7 + description: Register $n of BLOCK7 (KEY3). + addressOffset: 280 + size: 32 + fields: + - name: KEY3_DATA7 + description: Stores the seventh 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA0 + description: Register $n of BLOCK8 (KEY4). + addressOffset: 284 + size: 32 + fields: + - name: KEY4_DATA0 + description: Stores the zeroth 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA1 + description: Register $n of BLOCK8 (KEY4). + addressOffset: 288 + size: 32 + fields: + - name: KEY4_DATA1 + description: Stores the first 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA2 + description: Register $n of BLOCK8 (KEY4). + addressOffset: 292 + size: 32 + fields: + - name: KEY4_DATA2 + description: Stores the second 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA3 + description: Register $n of BLOCK8 (KEY4). + addressOffset: 296 + size: 32 + fields: + - name: KEY4_DATA3 + description: Stores the third 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA4 + description: Register $n of BLOCK8 (KEY4). + addressOffset: 300 + size: 32 + fields: + - name: KEY4_DATA4 + description: Stores the fourth 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA5 + description: Register $n of BLOCK8 (KEY4). + addressOffset: 304 + size: 32 + fields: + - name: KEY4_DATA5 + description: Stores the fifth 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA6 + description: Register $n of BLOCK8 (KEY4). + addressOffset: 308 + size: 32 + fields: + - name: KEY4_DATA6 + description: Stores the sixth 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA7 + description: Register $n of BLOCK8 (KEY4). + addressOffset: 312 + size: 32 + fields: + - name: KEY4_DATA7 + description: Stores the seventh 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA0 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 316 + size: 32 + fields: + - name: KEY5_DATA0 + description: Stores the zeroth 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA1 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 320 + size: 32 + fields: + - name: KEY5_DATA1 + description: Stores the first 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA2 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 324 + size: 32 + fields: + - name: KEY5_DATA2 + description: Stores the second 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA3 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 328 + size: 32 + fields: + - name: KEY5_DATA3 + description: Stores the third 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA4 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 332 + size: 32 + fields: + - name: KEY5_DATA4 + description: Stores the fourth 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA5 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 336 + size: 32 + fields: + - name: KEY5_DATA5 + description: Stores the fifth 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA6 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 340 + size: 32 + fields: + - name: KEY5_DATA6 + description: Stores the sixth 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA7 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 344 + size: 32 + fields: + - name: KEY5_DATA7 + description: Stores the seventh 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA0 + description: Register $n of BLOCK10 (system). + addressOffset: 348 + size: 32 + fields: + - name: SYS_DATA_PART2_0 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA1 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 352 + size: 32 + fields: + - name: SYS_DATA_PART2_1 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA2 + description: Register $n of BLOCK10 (system). + addressOffset: 356 + size: 32 + fields: + - name: SYS_DATA_PART2_2 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA3 + description: Register $n of BLOCK10 (system). + addressOffset: 360 + size: 32 + fields: + - name: SYS_DATA_PART2_3 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA4 + description: Register $n of BLOCK10 (system). + addressOffset: 364 + size: 32 + fields: + - name: SYS_DATA_PART2_4 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA5 + description: Register $n of BLOCK10 (system). + addressOffset: 368 + size: 32 + fields: + - name: SYS_DATA_PART2_5 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA6 + description: Register $n of BLOCK10 (system). + addressOffset: 372 + size: 32 + fields: + - name: SYS_DATA_PART2_6 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA7 + description: Register $n of BLOCK10 (system). + addressOffset: 376 + size: 32 + fields: + - name: SYS_DATA_PART2_7 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_REPEAT_ERR0 + description: Programming error record register 0 of BLOCK0. + addressOffset: 380 + size: 32 + fields: + - name: RD_DIS_ERR + description: Indicates a programming error of RD_DIS. + bitOffset: 0 + bitWidth: 7 + access: read-only + - name: SWAP_UART_SDIO_EN_ERR + description: Indicates a programming error of SWAP_UART_SDIO_EN. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DIS_ICACHE_ERR + description: Indicates a programming error of DIS_ICACHE. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DIS_USB_JTAG_ERR + description: Indicates a programming error of DIS_USB_JTAG. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_ICACHE_ERR + description: Indicates a programming error of DIS_DOWNLOAD_ICACHE. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: DIS_USB_SERIAL_JTAG_ERR + description: Indicates a programming error of DIS_USB_DEVICE. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: DIS_FORCE_DOWNLOAD_ERR + description: Indicates a programming error of DIS_FORCE_DOWNLOAD. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SPI_DOWNLOAD_MSPI_DIS_ERR + description: Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: DIS_TWAI_ERR + description: Indicates a programming error of DIS_CAN. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: JTAG_SEL_ENABLE_ERR + description: Indicates a programming error of JTAG_SEL_ENABLE. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SOFT_DIS_JTAG_ERR + description: Indicates a programming error of SOFT_DIS_JTAG. + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: DIS_PAD_JTAG_ERR + description: Indicates a programming error of DIS_PAD_JTAG. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR + description: Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: USB_DREFH_ERR + description: Indicates a programming error of USB_DREFH. + bitOffset: 21 + bitWidth: 2 + access: read-only + - name: USB_DREFL_ERR + description: Indicates a programming error of USB_DREFL. + bitOffset: 23 + bitWidth: 2 + access: read-only + - name: USB_EXCHG_PINS_ERR + description: Indicates a programming error of USB_EXCHG_PINS. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: VDD_SPI_AS_GPIO_ERR + description: Indicates a programming error of VDD_SPI_AS_GPIO. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED0_ERR_2 + description: Reserved. + bitOffset: 27 + bitWidth: 2 + access: read-only + - name: RPT4_RESERVED0_ERR_1 + description: Reserved. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED0_ERR_0 + description: Reserved. + bitOffset: 30 + bitWidth: 2 + access: read-only + - register: + name: RD_REPEAT_ERR1 + description: Programming error record register 1 of BLOCK0. + addressOffset: 384 + size: 32 + fields: + - name: RPT4_RESERVED1_ERR_0 + description: Reserved. + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: WDT_DELAY_SEL_ERR + description: Indicates a programming error of WDT_DELAY_SEL. + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: SPI_BOOT_CRYPT_CNT_ERR + description: Indicates a programming error of SPI_BOOT_CRYPT_CNT. + bitOffset: 18 + bitWidth: 3 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE0_ERR + description: Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE1_ERR + description: Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE2_ERR + description: Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: KEY_PURPOSE_0_ERR + description: Indicates a programming error of KEY_PURPOSE_0. + bitOffset: 24 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_1_ERR + description: Indicates a programming error of KEY_PURPOSE_1. + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_REPEAT_ERR2 + description: Programming error record register 2 of BLOCK0. + addressOffset: 388 + size: 32 + fields: + - name: KEY_PURPOSE_2_ERR + description: Indicates a programming error of KEY_PURPOSE_2. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_3_ERR + description: Indicates a programming error of KEY_PURPOSE_3. + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_4_ERR + description: Indicates a programming error of KEY_PURPOSE_4. + bitOffset: 8 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_5_ERR + description: Indicates a programming error of KEY_PURPOSE_5. + bitOffset: 12 + bitWidth: 4 + access: read-only + - name: SEC_DPA_LEVEL_ERR + description: Indicates a programming error of SEC_DPA_LEVEL. + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: RPT4_RESERVED2_ERR_1 + description: Reserved. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: CRYPT_DPA_ENABLE_ERR + description: Indicates a programming error of CRYPT_DPA_ENABLE. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_EN_ERR + description: Indicates a programming error of SECURE_BOOT_EN. + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_AGGRESSIVE_REVOKE_ERR + description: Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED2_ERR_0 + description: Reserved. + bitOffset: 22 + bitWidth: 6 + access: read-only + - name: FLASH_TPUW_ERR + description: Indicates a programming error of FLASH_TPUW. + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_REPEAT_ERR3 + description: Programming error record register 3 of BLOCK0. + addressOffset: 392 + size: 32 + fields: + - name: DIS_DOWNLOAD_MODE_ERR + description: Indicates a programming error of DIS_DOWNLOAD_MODE. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DIS_DIRECT_BOOT_ERR + description: Indicates a programming error of DIS_DIRECT_BOOT. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: USB_PRINT_ERR + description: Indicates a programming error of UART_PRINT_CHANNEL. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED3_ERR_5 + description: Reserved. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR + description: Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ENABLE_SECURITY_DOWNLOAD_ERR + description: Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: UART_PRINT_CONTROL_ERR + description: Indicates a programming error of UART_PRINT_CONTROL. + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: RPT4_RESERVED3_ERR_4 + description: Reserved. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED3_ERR_3 + description: Reserved. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED3_ERR_2 + description: Reserved. + bitOffset: 10 + bitWidth: 2 + access: read-only + - name: RPT4_RESERVED3_ERR_1 + description: Reserved. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: FORCE_SEND_RESUME_ERR + description: Indicates a programming error of FORCE_SEND_RESUME. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SECURE_VERSION_ERR + description: Indicates a programming error of SECURE_VERSION. + bitOffset: 14 + bitWidth: 16 + access: read-only + - name: RPT4_RESERVED3_ERR_0 + description: Reserved. + bitOffset: 30 + bitWidth: 2 + access: read-only + - register: + name: RD_REPEAT_ERR4 + description: Programming error record register 4 of BLOCK0. + addressOffset: 400 + size: 32 + fields: + - name: RPT4_RESERVED4_ERR_1 + description: Reserved. + bitOffset: 0 + bitWidth: 24 + access: read-only + - name: RPT4_RESERVED4_ERR_0 + description: Reserved. + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: RD_RS_ERR0 + description: Programming error record register 0 of BLOCK1-10. + addressOffset: 448 + size: 32 + fields: + - name: MAC_SPI_8M_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: MAC_SPI_8M_FAIL + description: "0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SYS_PART1_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 4 + bitWidth: 3 + access: read-only + - name: SYS_PART1_FAIL + description: "0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: USR_DATA_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 8 + bitWidth: 3 + access: read-only + - name: USR_DATA_FAIL + description: "0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: KEY0_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 12 + bitWidth: 3 + access: read-only + - name: KEY0_FAIL + description: "0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6." + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: KEY1_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: KEY1_FAIL + description: "0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6." + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: KEY2_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 20 + bitWidth: 3 + access: read-only + - name: KEY2_FAIL + description: "0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6." + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: KEY3_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 24 + bitWidth: 3 + access: read-only + - name: KEY3_FAIL + description: "0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6." + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: KEY4_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 28 + bitWidth: 3 + access: read-only + - name: KEY4_FAIL + description: "0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: RD_RS_ERR1 + description: Programming error record register 1 of BLOCK1-10. + addressOffset: 452 + size: 32 + fields: + - name: KEY5_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: KEY5_FAIL + description: "0: Means no failure and that the data of key5 is reliable 1: Means that programming key5 failed and the number of error bytes is over 6." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SYS_PART2_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 4 + bitWidth: 3 + access: read-only + - name: SYS_PART2_FAIL + description: "0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 7 + bitWidth: 1 + access: read-only + - register: + name: CLK + description: eFuse clcok configuration register. + addressOffset: 456 + size: 32 + resetValue: 2 + fields: + - name: MEM_FORCE_PD + description: Set this bit to force eFuse SRAM into power-saving mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_CLK_FORCE_ON + description: Set this bit and force to activate clock signal of eFuse SRAM. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PU + description: Set this bit to force eFuse SRAM into working mode. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EN + description: Set this bit to force enable eFuse register configuration clock signal. + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: CONF + description: eFuse operation mode configuraiton register + addressOffset: 460 + size: 32 + fields: + - name: OP_CODE + description: "0x5A5A: programming operation command 0x5AA5: read operation command." + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: STATUS + description: eFuse status register. + addressOffset: 464 + size: 32 + fields: + - name: STATE + description: Indicates the state of the eFuse state machine. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: OTP_LOAD_SW + description: The value of OTP_LOAD_SW. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: OTP_VDDQ_C_SYNC2 + description: The value of OTP_VDDQ_C_SYNC2. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OTP_STROBE_SW + description: The value of OTP_STROBE_SW. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OTP_CSB_SW + description: The value of OTP_CSB_SW. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OTP_PGENB_SW + description: The value of OTP_PGENB_SW. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: OTP_VDDQ_IS_SW + description: The value of OTP_VDDQ_IS_SW. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: BLK0_VALID_BIT_CNT + description: Indicates the number of block valid bit. + bitOffset: 10 + bitWidth: 10 + access: read-only + - register: + name: CMD + description: eFuse command register. + addressOffset: 468 + size: 32 + fields: + - name: READ_CMD + description: Set this bit to send read command. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PGM_CMD + description: Set this bit to send programming command. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BLK_NUM + description: "The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively." + bitOffset: 2 + bitWidth: 4 + access: read-write + - register: + name: INT_RAW + description: eFuse raw interrupt register. + addressOffset: 472 + size: 32 + fields: + - name: READ_DONE_INT_RAW + description: The raw bit signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PGM_DONE_INT_RAW + description: The raw bit signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: eFuse interrupt status register. + addressOffset: 476 + size: 32 + fields: + - name: READ_DONE_INT_ST + description: The status signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PGM_DONE_INT_ST + description: The status signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: eFuse interrupt enable register. + addressOffset: 480 + size: 32 + fields: + - name: READ_DONE_INT_ENA + description: The enable signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PGM_DONE_INT_ENA + description: The enable signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: eFuse interrupt clear register. + addressOffset: 484 + size: 32 + fields: + - name: READ_DONE_INT_CLR + description: The clear signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: PGM_DONE_INT_CLR + description: The clear signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: DAC_CONF + description: Controls the eFuse programming voltage. + addressOffset: 488 + size: 32 + resetValue: 130588 + fields: + - name: DAC_CLK_DIV + description: Controls the division factor of the rising clock of the programming voltage. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: DAC_CLK_PAD_SEL + description: "Don't care." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DAC_NUM + description: Controls the rising period of the programming voltage. + bitOffset: 9 + bitWidth: 8 + access: read-write + - name: OE_CLR + description: Reduces the power supply of the programming voltage. + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: RD_TIM_CONF + description: Configures read timing parameters. + addressOffset: 492 + size: 32 + resetValue: 302055937 + fields: + - name: THR_A + description: Configures the read hold time. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TRD + description: Configures the read time. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: TSUR_A + description: Configures the read setup time. + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: READ_INIT_NUM + description: Configures the waiting time of reading eFuse memory. + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: WR_TIM_CONF1 + description: Configurarion register 1 of eFuse programming timing parameters. + addressOffset: 496 + size: 32 + resetValue: 19922945 + fields: + - name: TSUP_A + description: Configures the programming setup time. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: PWR_ON_NUM + description: Configures the power up time for VDDQ. + bitOffset: 8 + bitWidth: 16 + access: read-write + - name: THP_A + description: Configures the programming hold time. + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: WR_TIM_CONF2 + description: Configurarion register 2 of eFuse programming timing parameters. + addressOffset: 500 + size: 32 + resetValue: 13107600 + fields: + - name: PWR_OFF_NUM + description: Configures the power outage time for VDDQ. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: TPGM + description: Configures the active programming time. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: WR_TIM_CONF0_RS_BYPASS + description: Configurarion register0 of eFuse programming time parameters and rs bypass operation. + addressOffset: 504 + size: 32 + resetValue: 8192 + fields: + - name: BYPASS_RS_CORRECTION + description: Set this bit to bypass reed solomon correction step. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: BYPASS_RS_BLK_NUM + description: Configures block number of programming twice operation. + bitOffset: 1 + bitWidth: 11 + access: read-write + - name: UPDATE + description: Set this bit to update multi-bit register signals. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: TPGM_INACTIVE + description: Configures the inactive programming time. + bitOffset: 13 + bitWidth: 8 + access: read-write + - register: + name: DATE + description: eFuse version register. + addressOffset: 508 + size: 32 + resetValue: 35676928 + fields: + - name: DATE + description: Stores eFuse version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: EXTMEM + description: External Memory + groupName: EXTMEM + baseAddress: 1611431936 + addressBlock: + - offset: 0 + size: 968 + usage: registers + registers: + - register: + name: L1_ICACHE_CTRL + description: L1 instruction Cache(L1-ICache) control register + addressOffset: 0 + size: 32 + fields: + - name: L1_ICACHE_SHUT_IBUS0 + description: "The bit is used to disable core0 ibus access L1-ICache, 0: enable, 1: disable" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE_SHUT_IBUS1 + description: "The bit is used to disable core1 ibus access L1-ICache, 0: enable, 1: disable" + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE_SHUT_IBUS2 + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE_SHUT_IBUS3 + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L1_ICACHE_UNDEF_OP + description: Reserved + bitOffset: 4 + bitWidth: 4 + access: read-only + - register: + name: L1_CACHE_CTRL + description: L1 data Cache(L1-Cache) control register + addressOffset: 4 + size: 32 + fields: + - name: L1_CACHE_SHUT_BUS0 + description: "The bit is used to disable core0 dbus access L1-Cache, 0: enable, 1: disable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: L1_CACHE_SHUT_BUS1 + description: "The bit is used to disable core1 dbus access L1-Cache, 0: enable, 1: disable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: L1_CACHE_SHUT_DBUS2 + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_CACHE_SHUT_DBUS3 + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L1_CACHE_SHUT_DMA + description: "The bit is used to disable DMA access L1-Cache, 0: enable, 1: disable" + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: L1_CACHE_UNDEF_OP + description: Reserved + bitOffset: 8 + bitWidth: 4 + access: read-write + - register: + name: L1_BYPASS_CACHE_CONF + description: Bypass Cache configure register + addressOffset: 8 + size: 32 + fields: + - name: BYPASS_L1_ICACHE0_EN + description: "The bit is used to enable bypass L1-ICache0. 0: disable bypass, 1: enable bypass." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: BYPASS_L1_ICACHE1_EN + description: "The bit is used to enable bypass L1-ICache1. 0: disable bypass, 1: enable bypass." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: BYPASS_L1_ICACHE2_EN + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: BYPASS_L1_ICACHE3_EN + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BYPASS_L1_DCACHE_EN + description: "The bit is used to enable bypass L1-DCache. 0: disable bypass, 1: enable bypass." + bitOffset: 4 + bitWidth: 1 + access: read-only + - register: + name: L1_CACHE_ATOMIC_CONF + description: L1 Cache atomic feature configure register + addressOffset: 12 + size: 32 + fields: + - name: L1_CACHE_ATOMIC_EN + description: "The bit is used to enable atomic feature on L1-Cache when multiple cores access L1-Cache. 1: disable, 1: enable." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: L1_ICACHE_CACHESIZE_CONF + description: L1 instruction Cache CacheSize mode configure register + addressOffset: 16 + size: 32 + fields: + - name: L1_ICACHE_CACHESIZE_1K + description: The field is used to configure cachesize of L1-ICache as 1k bytes. This field and all other fields within this register is onehot. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE_CACHESIZE_2K + description: The field is used to configure cachesize of L1-ICache as 2k bytes. This field and all other fields within this register is onehot. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE_CACHESIZE_4K + description: The field is used to configure cachesize of L1-ICache as 4k bytes. This field and all other fields within this register is onehot. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE_CACHESIZE_8K + description: The field is used to configure cachesize of L1-ICache as 8k bytes. This field and all other fields within this register is onehot. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L1_ICACHE_CACHESIZE_16K + description: The field is used to configure cachesize of L1-ICache as 16k bytes. This field and all other fields within this register is onehot. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: L1_ICACHE_CACHESIZE_32K + description: The field is used to configure cachesize of L1-ICache as 32k bytes. This field and all other fields within this register is onehot. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: L1_ICACHE_CACHESIZE_64K + description: The field is used to configure cachesize of L1-ICache as 64k bytes. This field and all other fields within this register is onehot. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: L1_ICACHE_CACHESIZE_128K + description: The field is used to configure cachesize of L1-ICache as 128k bytes. This field and all other fields within this register is onehot. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: L1_ICACHE_CACHESIZE_256K + description: The field is used to configure cachesize of L1-ICache as 256k bytes. This field and all other fields within this register is onehot. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: L1_ICACHE_CACHESIZE_512K + description: The field is used to configure cachesize of L1-ICache as 512k bytes. This field and all other fields within this register is onehot. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: L1_ICACHE_CACHESIZE_1024K + description: The field is used to configure cachesize of L1-ICache as 1024k bytes. This field and all other fields within this register is onehot. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: L1_ICACHE_CACHESIZE_2048K + description: The field is used to configure cachesize of L1-ICache as 2048k bytes. This field and all other fields within this register is onehot. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: L1_ICACHE_CACHESIZE_4096K + description: The field is used to configure cachesize of L1-ICache as 4096k bytes. This field and all other fields within this register is onehot. + bitOffset: 12 + bitWidth: 1 + access: read-only + - register: + name: L1_ICACHE_BLOCKSIZE_CONF + description: L1 instruction Cache BlockSize mode configure register + addressOffset: 20 + size: 32 + fields: + - name: L1_ICACHE_BLOCKSIZE_8 + description: The field is used to configureblocksize of L1-ICache as 8 bytes. This field and all other fields within this register is onehot. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE_BLOCKSIZE_16 + description: The field is used to configureblocksize of L1-ICache as 16 bytes. This field and all other fields within this register is onehot. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE_BLOCKSIZE_32 + description: The field is used to configureblocksize of L1-ICache as 32 bytes. This field and all other fields within this register is onehot. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE_BLOCKSIZE_64 + description: The field is used to configureblocksize of L1-ICache as 64 bytes. This field and all other fields within this register is onehot. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L1_ICACHE_BLOCKSIZE_128 + description: The field is used to configureblocksize of L1-ICache as 128 bytes. This field and all other fields within this register is onehot. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: L1_ICACHE_BLOCKSIZE_256 + description: The field is used to configureblocksize of L1-ICache as 256 bytes. This field and all other fields within this register is onehot. + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: L1_CACHE_CACHESIZE_CONF + description: L1 data Cache CacheSize mode configure register + addressOffset: 24 + size: 32 + resetValue: 32 + fields: + - name: L1_CACHE_CACHESIZE_1K + description: The field is used to configure cachesize of L1-Cache as 1k bytes. This field and all other fields within this register is onehot. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_CACHE_CACHESIZE_2K + description: The field is used to configure cachesize of L1-Cache as 2k bytes. This field and all other fields within this register is onehot. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_CACHE_CACHESIZE_4K + description: The field is used to configure cachesize of L1-Cache as 4k bytes. This field and all other fields within this register is onehot. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_CACHE_CACHESIZE_8K + description: The field is used to configure cachesize of L1-Cache as 8k bytes. This field and all other fields within this register is onehot. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L1_CACHE_CACHESIZE_16K + description: The field is used to configure cachesize of L1-Cache as 16k bytes. This field and all other fields within this register is onehot. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: L1_CACHE_CACHESIZE_32K + description: The field is used to configure cachesize of L1-Cache as 32k bytes. This field and all other fields within this register is onehot. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: L1_CACHE_CACHESIZE_64K + description: The field is used to configure cachesize of L1-Cache as 64k bytes. This field and all other fields within this register is onehot. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: L1_CACHE_CACHESIZE_128K + description: The field is used to configure cachesize of L1-Cache as 128k bytes. This field and all other fields within this register is onehot. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: L1_CACHE_CACHESIZE_256K + description: The field is used to configure cachesize of L1-Cache as 256k bytes. This field and all other fields within this register is onehot. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: L1_CACHE_CACHESIZE_512K + description: The field is used to configure cachesize of L1-Cache as 512k bytes. This field and all other fields within this register is onehot. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: L1_CACHE_CACHESIZE_1024K + description: The field is used to configure cachesize of L1-Cache as 1024k bytes. This field and all other fields within this register is onehot. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: L1_CACHE_CACHESIZE_2048K + description: The field is used to configure cachesize of L1-Cache as 2048k bytes. This field and all other fields within this register is onehot. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: L1_CACHE_CACHESIZE_4096K + description: The field is used to configure cachesize of L1-Cache as 4096k bytes. This field and all other fields within this register is onehot. + bitOffset: 12 + bitWidth: 1 + access: read-only + - register: + name: L1_CACHE_BLOCKSIZE_CONF + description: L1 data Cache BlockSize mode configure register + addressOffset: 28 + size: 32 + resetValue: 4 + fields: + - name: L1_CACHE_BLOCKSIZE_8 + description: The field is used to configureblocksize of L1-DCache as 8 bytes. This field and all other fields within this register is onehot. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_CACHE_BLOCKSIZE_16 + description: The field is used to configureblocksize of L1-DCache as 16 bytes. This field and all other fields within this register is onehot. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_CACHE_BLOCKSIZE_32 + description: The field is used to configureblocksize of L1-DCache as 32 bytes. This field and all other fields within this register is onehot. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_CACHE_BLOCKSIZE_64 + description: The field is used to configureblocksize of L1-DCache as 64 bytes. This field and all other fields within this register is onehot. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L1_CACHE_BLOCKSIZE_128 + description: The field is used to configureblocksize of L1-DCache as 128 bytes. This field and all other fields within this register is onehot. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: L1_CACHE_BLOCKSIZE_256 + description: The field is used to configureblocksize of L1-DCache as 256 bytes. This field and all other fields within this register is onehot. + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: L1_CACHE_WRAP_AROUND_CTRL + description: Cache wrap around control register + addressOffset: 32 + size: 32 + fields: + - name: L1_ICACHE0_WRAP + description: Set this bit as 1 to enable L1-ICache0 wrap around mode. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_WRAP + description: Set this bit as 1 to enable L1-ICache1 wrap around mode. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_WRAP + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_WRAP + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L1_CACHE_WRAP + description: Set this bit as 1 to enable L1-DCache wrap around mode. + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: L1_CACHE_TAG_MEM_POWER_CTRL + description: Cache tag memory power control register + addressOffset: 36 + size: 32 + resetValue: 349525 + fields: + - name: L1_ICACHE0_TAG_MEM_FORCE_ON + description: "The bit is used to close clock gating of L1-ICache0 tag memory. 1: close gating, 0: open clock gating." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE0_TAG_MEM_FORCE_PD + description: "The bit is used to power L1-ICache0 tag memory down. 0: follow rtc_lslp, 1: power down" + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE0_TAG_MEM_FORCE_PU + description: "The bit is used to power L1-ICache0 tag memory up. 0: follow rtc_lslp, 1: power up" + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_TAG_MEM_FORCE_ON + description: "The bit is used to close clock gating of L1-ICache1 tag memory. 1: close gating, 0: open clock gating." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_TAG_MEM_FORCE_PD + description: "The bit is used to power L1-ICache1 tag memory down. 0: follow rtc_lslp, 1: power down" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_TAG_MEM_FORCE_PU + description: "The bit is used to power L1-ICache1 tag memory up. 0: follow rtc_lslp, 1: power up" + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_TAG_MEM_FORCE_ON + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_TAG_MEM_FORCE_PD + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_TAG_MEM_FORCE_PU + description: Reserved + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_TAG_MEM_FORCE_ON + description: Reserved + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_TAG_MEM_FORCE_PD + description: Reserved + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_TAG_MEM_FORCE_PU + description: Reserved + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: L1_CACHE_TAG_MEM_FORCE_ON + description: "The bit is used to close clock gating of L1-Cache tag memory. 1: close gating, 0: open clock gating." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: L1_CACHE_TAG_MEM_FORCE_PD + description: "The bit is used to power L1-Cache tag memory down. 0: follow rtc_lslp, 1: power down" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: L1_CACHE_TAG_MEM_FORCE_PU + description: "The bit is used to power L1-Cache tag memory up. 0: follow rtc_lslp, 1: power up" + bitOffset: 18 + bitWidth: 1 + access: read-write + - register: + name: L1_CACHE_DATA_MEM_POWER_CTRL + description: Cache data memory power control register + addressOffset: 40 + size: 32 + resetValue: 349525 + fields: + - name: L1_ICACHE0_DATA_MEM_FORCE_ON + description: "The bit is used to close clock gating of L1-ICache0 data memory. 1: close gating, 0: open clock gating." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE0_DATA_MEM_FORCE_PD + description: "The bit is used to power L1-ICache0 data memory down. 0: follow rtc_lslp, 1: power down" + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE0_DATA_MEM_FORCE_PU + description: "The bit is used to power L1-ICache0 data memory up. 0: follow rtc_lslp, 1: power up" + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_DATA_MEM_FORCE_ON + description: "The bit is used to close clock gating of L1-ICache1 data memory. 1: close gating, 0: open clock gating." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_DATA_MEM_FORCE_PD + description: "The bit is used to power L1-ICache1 data memory down. 0: follow rtc_lslp, 1: power down" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_DATA_MEM_FORCE_PU + description: "The bit is used to power L1-ICache1 data memory up. 0: follow rtc_lslp, 1: power up" + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_DATA_MEM_FORCE_ON + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_DATA_MEM_FORCE_PD + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_DATA_MEM_FORCE_PU + description: Reserved + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_DATA_MEM_FORCE_ON + description: Reserved + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_DATA_MEM_FORCE_PD + description: Reserved + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_DATA_MEM_FORCE_PU + description: Reserved + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: L1_CACHE_DATA_MEM_FORCE_ON + description: "The bit is used to close clock gating of L1-Cache data memory. 1: close gating, 0: open clock gating." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: L1_CACHE_DATA_MEM_FORCE_PD + description: "The bit is used to power L1-Cache data memory down. 0: follow rtc_lslp, 1: power down" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: L1_CACHE_DATA_MEM_FORCE_PU + description: "The bit is used to power L1-Cache data memory up. 0: follow rtc_lslp, 1: power up" + bitOffset: 18 + bitWidth: 1 + access: read-write + - register: + name: L1_CACHE_FREEZE_CTRL + description: Cache Freeze control register + addressOffset: 44 + size: 32 + fields: + - name: L1_ICACHE0_FREEZE_EN + description: The bit is used to enable freeze operation on L1-ICache0. It can be cleared by software. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE0_FREEZE_MODE + description: "The bit is used to configure mode of freeze operation L1-ICache0. 0: a miss-access will not stuck. 1: a miss-access will stuck." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE0_FREEZE_DONE + description: "The bit is used to indicate whether freeze operation on L1-ICache0 is finished or not. 0: not finished. 1: finished." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_FREEZE_EN + description: The bit is used to enable freeze operation on L1-ICache1. It can be cleared by software. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_FREEZE_MODE + description: "The bit is used to configure mode of freeze operation L1-ICache1. 0: a miss-access will not stuck. 1: a miss-access will stuck." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_FREEZE_DONE + description: "The bit is used to indicate whether freeze operation on L1-ICache1 is finished or not. 0: not finished. 1: finished." + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_FREEZE_EN + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_FREEZE_MODE + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_FREEZE_DONE + description: Reserved + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_FREEZE_EN + description: Reserved + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_FREEZE_MODE + description: Reserved + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_FREEZE_DONE + description: Reserved + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: L1_CACHE_FREEZE_EN + description: The bit is used to enable freeze operation on L1-Cache. It can be cleared by software. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: L1_CACHE_FREEZE_MODE + description: "The bit is used to configure mode of freeze operation L1-Cache. 0: a miss-access will not stuck. 1: a miss-access will stuck." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: L1_CACHE_FREEZE_DONE + description: "The bit is used to indicate whether freeze operation on L1-Cache is finished or not. 0: not finished. 1: finished." + bitOffset: 18 + bitWidth: 1 + access: read-only + - register: + name: L1_CACHE_DATA_MEM_ACS_CONF + description: Cache data memory access configure register + addressOffset: 48 + size: 32 + resetValue: 209715 + fields: + - name: L1_ICACHE0_DATA_MEM_RD_EN + description: "The bit is used to enable config-bus read L1-ICache0 data memoryory. 0: disable, 1: enable." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE0_DATA_MEM_WR_EN + description: "The bit is used to enable config-bus write L1-ICache0 data memoryory. 0: disable, 1: enable." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_DATA_MEM_RD_EN + description: "The bit is used to enable config-bus read L1-ICache1 data memoryory. 0: disable, 1: enable." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_DATA_MEM_WR_EN + description: "The bit is used to enable config-bus write L1-ICache1 data memoryory. 0: disable, 1: enable." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_DATA_MEM_RD_EN + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_DATA_MEM_WR_EN + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_DATA_MEM_RD_EN + description: Reserved + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_DATA_MEM_WR_EN + description: Reserved + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: L1_CACHE_DATA_MEM_RD_EN + description: "The bit is used to enable config-bus read L1-Cache data memoryory. 0: disable, 1: enable." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: L1_CACHE_DATA_MEM_WR_EN + description: "The bit is used to enable config-bus write L1-Cache data memoryory. 0: disable, 1: enable." + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: L1_CACHE_TAG_MEM_ACS_CONF + description: Cache tag memory access configure register + addressOffset: 52 + size: 32 + resetValue: 209715 + fields: + - name: L1_ICACHE0_TAG_MEM_RD_EN + description: "The bit is used to enable config-bus read L1-ICache0 tag memoryory. 0: disable, 1: enable." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE0_TAG_MEM_WR_EN + description: "The bit is used to enable config-bus write L1-ICache0 tag memoryory. 0: disable, 1: enable." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_TAG_MEM_RD_EN + description: "The bit is used to enable config-bus read L1-ICache1 tag memoryory. 0: disable, 1: enable." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_TAG_MEM_WR_EN + description: "The bit is used to enable config-bus write L1-ICache1 tag memoryory. 0: disable, 1: enable." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_TAG_MEM_RD_EN + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_TAG_MEM_WR_EN + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_TAG_MEM_RD_EN + description: Reserved + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_TAG_MEM_WR_EN + description: Reserved + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: L1_CACHE_TAG_MEM_RD_EN + description: "The bit is used to enable config-bus read L1-Cache tag memoryory. 0: disable, 1: enable." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: L1_CACHE_TAG_MEM_WR_EN + description: "The bit is used to enable config-bus write L1-Cache tag memoryory. 0: disable, 1: enable." + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: L1_ICACHE0_PRELOCK_CONF + description: L1 instruction Cache 0 prelock configure register + addressOffset: 56 + size: 32 + fields: + - name: L1_ICACHE0_PRELOCK_SCT0_EN + description: The bit is used to enable the first section of prelock function on L1-ICache0. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE0_PRELOCK_SCT1_EN + description: The bit is used to enable the second section of prelock function on L1-ICache0. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE0_PRELOCK_RGID + description: The bit is used to set the gid of l1 icache0 prelock. + bitOffset: 2 + bitWidth: 4 + access: read-only + - register: + name: L1_ICACHE0_PRELOCK_SCT0_ADDR + description: L1 instruction Cache 0 prelock section0 address configure register + addressOffset: 60 + size: 32 + fields: + - name: L1_ICACHE0_PRELOCK_SCT0_ADDR + description: "Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_ICACHE0_PRELOCK_SCT1_ADDR + description: L1 instruction Cache 0 prelock section1 address configure register + addressOffset: 64 + size: 32 + fields: + - name: L1_ICACHE0_PRELOCK_SCT1_ADDR + description: "Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_ICACHE0_PRELOCK_SCT_SIZE + description: L1 instruction Cache 0 prelock section size configure register + addressOffset: 68 + size: 32 + resetValue: 1073692671 + fields: + - name: L1_ICACHE0_PRELOCK_SCT0_SIZE + description: "Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT0_ADDR_REG" + bitOffset: 0 + bitWidth: 14 + access: read-only + - name: L1_ICACHE0_PRELOCK_SCT1_SIZE + description: "Those bits are used to configure the size of the second section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOCK_SCT1_ADDR_REG" + bitOffset: 16 + bitWidth: 14 + access: read-only + - register: + name: L1_ICACHE1_PRELOCK_CONF + description: L1 instruction Cache 1 prelock configure register + addressOffset: 72 + size: 32 + fields: + - name: L1_ICACHE1_PRELOCK_SCT0_EN + description: The bit is used to enable the first section of prelock function on L1-ICache1. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_PRELOCK_SCT1_EN + description: The bit is used to enable the second section of prelock function on L1-ICache1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_PRELOCK_RGID + description: The bit is used to set the gid of l1 icache1 prelock. + bitOffset: 2 + bitWidth: 4 + access: read-only + - register: + name: L1_ICACHE1_PRELOCK_SCT0_ADDR + description: L1 instruction Cache 1 prelock section0 address configure register + addressOffset: 76 + size: 32 + fields: + - name: L1_ICACHE1_PRELOCK_SCT0_ADDR + description: "Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_ICACHE1_PRELOCK_SCT1_ADDR + description: L1 instruction Cache 1 prelock section1 address configure register + addressOffset: 80 + size: 32 + fields: + - name: L1_ICACHE1_PRELOCK_SCT1_ADDR + description: "Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_ICACHE1_PRELOCK_SCT_SIZE + description: L1 instruction Cache 1 prelock section size configure register + addressOffset: 84 + size: 32 + resetValue: 1073692671 + fields: + - name: L1_ICACHE1_PRELOCK_SCT0_SIZE + description: "Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT0_ADDR_REG" + bitOffset: 0 + bitWidth: 14 + access: read-only + - name: L1_ICACHE1_PRELOCK_SCT1_SIZE + description: "Those bits are used to configure the size of the second section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOCK_SCT1_ADDR_REG" + bitOffset: 16 + bitWidth: 14 + access: read-only + - register: + name: L1_ICACHE2_PRELOCK_CONF + description: L1 instruction Cache 2 prelock configure register + addressOffset: 88 + size: 32 + fields: + - name: L1_ICACHE2_PRELOCK_SCT0_EN + description: The bit is used to enable the first section of prelock function on L1-ICache2. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_PRELOCK_SCT1_EN + description: The bit is used to enable the second section of prelock function on L1-ICache2. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_PRELOCK_RGID + description: The bit is used to set the gid of l1 icache2 prelock. + bitOffset: 2 + bitWidth: 4 + access: read-only + - register: + name: L1_ICACHE2_PRELOCK_SCT0_ADDR + description: L1 instruction Cache 2 prelock section0 address configure register + addressOffset: 92 + size: 32 + fields: + - name: L1_ICACHE2_PRELOCK_SCT0_ADDR + description: "Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_ICACHE2_PRELOCK_SCT1_ADDR + description: L1 instruction Cache 2 prelock section1 address configure register + addressOffset: 96 + size: 32 + fields: + - name: L1_ICACHE2_PRELOCK_SCT1_ADDR + description: "Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_ICACHE2_PRELOCK_SCT_SIZE + description: L1 instruction Cache 2 prelock section size configure register + addressOffset: 100 + size: 32 + resetValue: 1073692671 + fields: + - name: L1_ICACHE2_PRELOCK_SCT0_SIZE + description: "Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT0_ADDR_REG" + bitOffset: 0 + bitWidth: 14 + access: read-only + - name: L1_ICACHE2_PRELOCK_SCT1_SIZE + description: "Those bits are used to configure the size of the second section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOCK_SCT1_ADDR_REG" + bitOffset: 16 + bitWidth: 14 + access: read-only + - register: + name: L1_ICACHE3_PRELOCK_CONF + description: L1 instruction Cache 3 prelock configure register + addressOffset: 104 + size: 32 + fields: + - name: L1_ICACHE3_PRELOCK_SCT0_EN + description: The bit is used to enable the first section of prelock function on L1-ICache3. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_PRELOCK_SCT1_EN + description: The bit is used to enable the second section of prelock function on L1-ICache3. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_PRELOCK_RGID + description: The bit is used to set the gid of l1 icache3 prelock. + bitOffset: 2 + bitWidth: 4 + access: read-only + - register: + name: L1_ICACHE3_PRELOCK_SCT0_ADDR + description: L1 instruction Cache 3 prelock section0 address configure register + addressOffset: 108 + size: 32 + fields: + - name: L1_ICACHE3_PRELOCK_SCT0_ADDR + description: "Those bits are used to configure the start virtual address of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_ICACHE3_PRELOCK_SCT1_ADDR + description: L1 instruction Cache 3 prelock section1 address configure register + addressOffset: 112 + size: 32 + fields: + - name: L1_ICACHE3_PRELOCK_SCT1_ADDR + description: "Those bits are used to configure the start virtual address of the second section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_ICACHE3_PRELOCK_SCT_SIZE + description: L1 instruction Cache 3 prelock section size configure register + addressOffset: 116 + size: 32 + resetValue: 1073692671 + fields: + - name: L1_ICACHE3_PRELOCK_SCT0_SIZE + description: "Those bits are used to configure the size of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT0_ADDR_REG" + bitOffset: 0 + bitWidth: 14 + access: read-only + - name: L1_ICACHE3_PRELOCK_SCT1_SIZE + description: "Those bits are used to configure the size of the second section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOCK_SCT1_ADDR_REG" + bitOffset: 16 + bitWidth: 14 + access: read-only + - register: + name: L1_CACHE_PRELOCK_CONF + description: L1 Cache prelock configure register + addressOffset: 120 + size: 32 + fields: + - name: L1_CACHE_PRELOCK_SCT0_EN + description: The bit is used to enable the first section of prelock function on L1-Cache. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: L1_CACHE_PRELOCK_SCT1_EN + description: The bit is used to enable the second section of prelock function on L1-Cache. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: L1_CACHE_PRELOCK_RGID + description: The bit is used to set the gid of l1 cache prelock. + bitOffset: 2 + bitWidth: 4 + access: read-only + - register: + name: L1_CACHE_PRELOCK_SCT0_ADDR + description: L1 Cache prelock section0 address configure register + addressOffset: 124 + size: 32 + fields: + - name: L1_CACHE_PRELOCK_SCT0_ADDR + description: "Those bits are used to configure the start virtual address of the first section of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: L1_DCACHE_PRELOCK_SCT1_ADDR + description: L1 Cache prelock section1 address configure register + addressOffset: 128 + size: 32 + fields: + - name: L1_CACHE_PRELOCK_SCT1_ADDR + description: "Those bits are used to configure the start virtual address of the second section of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: L1_DCACHE_PRELOCK_SCT_SIZE + description: L1 Cache prelock section size configure register + addressOffset: 132 + size: 32 + resetValue: 1073692671 + fields: + - name: L1_CACHE_PRELOCK_SCT0_SIZE + description: "Those bits are used to configure the size of the first section of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT0_ADDR_REG" + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: L1_CACHE_PRELOCK_SCT1_SIZE + description: "Those bits are used to configure the size of the second section of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOCK_SCT1_ADDR_REG" + bitOffset: 16 + bitWidth: 14 + access: read-write + - register: + name: CACHE_LOCK_CTRL + description: Lock-class (manual lock) operation control register + addressOffset: 136 + size: 32 + resetValue: 4 + fields: + - name: CACHE_LOCK_ENA + description: The bit is used to enable lock operation. It will be cleared by hardware after lock operation done + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CACHE_UNLOCK_ENA + description: The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CACHE_LOCK_DONE + description: "The bit is used to indicate whether unlock/lock operation is finished or not. 0: not finished. 1: finished." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CACHE_LOCK_RGID + description: The bit is used to set the gid of cache lock/unlock. + bitOffset: 3 + bitWidth: 4 + access: read-only + - register: + name: CACHE_LOCK_MAP + description: Lock (manual lock) map configure register + addressOffset: 140 + size: 32 + fields: + - name: CACHE_LOCK_MAP + description: "Those bits are used to indicate which caches in the two-level cache structure will apply this lock/unlock operation. [4]: L1-Cache" + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: CACHE_LOCK_ADDR + description: Lock (manual lock) address configure register + addressOffset: 144 + size: 32 + fields: + - name: CACHE_LOCK_ADDR + description: "Those bits are used to configure the start virtual address of the lock/unlock operation, which should be used together with CACHE_LOCK_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CACHE_LOCK_SIZE + description: Lock (manual lock) size configure register + addressOffset: 148 + size: 32 + fields: + - name: CACHE_LOCK_SIZE + description: "Those bits are used to configure the size of the lock/unlock operation, which should be used together with CACHE_LOCK_ADDR_REG" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: CACHE_SYNC_CTRL + description: Sync-class operation control register + addressOffset: 152 + size: 32 + resetValue: 1 + fields: + - name: CACHE_INVALIDATE_ENA + description: "The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. Note that this bit and the other sync-bits (clean_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CACHE_CLEAN_ENA + description: "The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. Note that this bit and the other sync-bits (invalidate_ena, writeback_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CACHE_WRITEBACK_ENA + description: "The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_invalidate_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CACHE_WRITEBACK_INVALIDATE_ENA + description: "The bit is used to enable writeback-invalidate operation. It will be cleared by hardware after writeback-invalidate operation done. Note that this bit and the other sync-bits (invalidate_ena, clean_ena, writeback_ena) are mutually exclusive, that is, those bits can not be set to 1 at the same time." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CACHE_SYNC_DONE + description: "The bit is used to indicate whether sync operation (invalidate, clean, writeback, writeback_invalidate) is finished or not. 0: not finished. 1: finished." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: CACHE_SYNC_RGID + description: "The bit is used to set the gid of cache sync operation (invalidate, clean, writeback, writeback_invalidate)" + bitOffset: 5 + bitWidth: 4 + access: read-only + - register: + name: CACHE_SYNC_MAP + description: Sync map configure register + addressOffset: 156 + size: 32 + resetValue: 63 + fields: + - name: CACHE_SYNC_MAP + description: "Those bits are used to indicate which caches in the two-level cache structure will apply the sync operation. [4]: L1-Cache" + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: CACHE_SYNC_ADDR + description: Sync address configure register + addressOffset: 160 + size: 32 + fields: + - name: CACHE_SYNC_ADDR + description: "Those bits are used to configure the start virtual address of the sync operation, which should be used together with CACHE_SYNC_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CACHE_SYNC_SIZE + description: Sync size configure register + addressOffset: 164 + size: 32 + fields: + - name: CACHE_SYNC_SIZE + description: "Those bits are used to configure the size of the sync operation, which should be used together with CACHE_SYNC_ADDR_REG" + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: L1_ICACHE0_PRELOAD_CTRL + description: L1 instruction Cache 0 preload-operation control register + addressOffset: 168 + size: 32 + resetValue: 2 + fields: + - name: L1_ICACHE0_PRELOAD_ENA + description: The bit is used to enable preload operation on L1-ICache0. It will be cleared by hardware automatically after preload operation is done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: L1_ICACHE0_PRELOAD_DONE + description: "The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE0_PRELOAD_ORDER + description: "The bit is used to configure the direction of preload operation. 0: ascending, 1: descending." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE0_PRELOAD_RGID + description: The bit is used to set the gid of l1 icache0 preload. + bitOffset: 3 + bitWidth: 4 + access: read-only + - register: + name: L1_ICACHE0_PRELOAD_ADDR + description: L1 instruction Cache 0 preload address configure register + addressOffset: 172 + size: 32 + fields: + - name: L1_ICACHE0_PRELOAD_ADDR + description: "Those bits are used to configure the start virtual address of preload on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_ICACHE0_PRELOAD_SIZE + description: L1 instruction Cache 0 preload size configure register + addressOffset: 176 + size: 32 + fields: + - name: L1_ICACHE0_PRELOAD_SIZE + description: "Those bits are used to configure the size of the first section of prelock on L1-ICache0, which should be used together with L1_ICACHE0_PRELOAD_ADDR_REG" + bitOffset: 0 + bitWidth: 14 + access: read-only + - register: + name: L1_ICACHE1_PRELOAD_CTRL + description: L1 instruction Cache 1 preload-operation control register + addressOffset: 180 + size: 32 + resetValue: 2 + fields: + - name: L1_ICACHE1_PRELOAD_ENA + description: The bit is used to enable preload operation on L1-ICache1. It will be cleared by hardware automatically after preload operation is done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: L1_ICACHE1_PRELOAD_DONE + description: "The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_PRELOAD_ORDER + description: "The bit is used to configure the direction of preload operation. 0: ascending, 1: descending." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_PRELOAD_RGID + description: The bit is used to set the gid of l1 icache1 preload. + bitOffset: 3 + bitWidth: 4 + access: read-only + - register: + name: L1_ICACHE1_PRELOAD_ADDR + description: L1 instruction Cache 1 preload address configure register + addressOffset: 184 + size: 32 + fields: + - name: L1_ICACHE1_PRELOAD_ADDR + description: "Those bits are used to configure the start virtual address of preload on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_ICACHE1_PRELOAD_SIZE + description: L1 instruction Cache 1 preload size configure register + addressOffset: 188 + size: 32 + fields: + - name: L1_ICACHE1_PRELOAD_SIZE + description: "Those bits are used to configure the size of the first section of prelock on L1-ICache1, which should be used together with L1_ICACHE1_PRELOAD_ADDR_REG" + bitOffset: 0 + bitWidth: 14 + access: read-only + - register: + name: L1_ICACHE2_PRELOAD_CTRL + description: L1 instruction Cache 2 preload-operation control register + addressOffset: 192 + size: 32 + resetValue: 2 + fields: + - name: L1_ICACHE2_PRELOAD_ENA + description: The bit is used to enable preload operation on L1-ICache2. It will be cleared by hardware automatically after preload operation is done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: L1_ICACHE2_PRELOAD_DONE + description: "The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_PRELOAD_ORDER + description: "The bit is used to configure the direction of preload operation. 0: ascending, 1: descending." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_PRELOAD_RGID + description: The bit is used to set the gid of l1 icache2 preload. + bitOffset: 3 + bitWidth: 4 + access: read-only + - register: + name: L1_ICACHE2_PRELOAD_ADDR + description: L1 instruction Cache 2 preload address configure register + addressOffset: 196 + size: 32 + fields: + - name: L1_ICACHE2_PRELOAD_ADDR + description: "Those bits are used to configure the start virtual address of preload on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_ICACHE2_PRELOAD_SIZE + description: L1 instruction Cache 2 preload size configure register + addressOffset: 200 + size: 32 + fields: + - name: L1_ICACHE2_PRELOAD_SIZE + description: "Those bits are used to configure the size of the first section of prelock on L1-ICache2, which should be used together with L1_ICACHE2_PRELOAD_ADDR_REG" + bitOffset: 0 + bitWidth: 14 + access: read-only + - register: + name: L1_ICACHE3_PRELOAD_CTRL + description: L1 instruction Cache 3 preload-operation control register + addressOffset: 204 + size: 32 + resetValue: 2 + fields: + - name: L1_ICACHE3_PRELOAD_ENA + description: The bit is used to enable preload operation on L1-ICache3. It will be cleared by hardware automatically after preload operation is done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: L1_ICACHE3_PRELOAD_DONE + description: "The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_PRELOAD_ORDER + description: "The bit is used to configure the direction of preload operation. 0: ascending, 1: descending." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_PRELOAD_RGID + description: The bit is used to set the gid of l1 icache3 preload. + bitOffset: 3 + bitWidth: 4 + access: read-only + - register: + name: L1_ICACHE3_PRELOAD_ADDR + description: L1 instruction Cache 3 preload address configure register + addressOffset: 208 + size: 32 + fields: + - name: L1_ICACHE3_PRELOAD_ADDR + description: "Those bits are used to configure the start virtual address of preload on L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_ICACHE3_PRELOAD_SIZE + description: L1 instruction Cache 3 preload size configure register + addressOffset: 212 + size: 32 + fields: + - name: L1_ICACHE3_PRELOAD_SIZE + description: "Those bits are used to configure the size of the first section of prelock on L1-ICache3, which should be used together with L1_ICACHE3_PRELOAD_ADDR_REG" + bitOffset: 0 + bitWidth: 14 + access: read-only + - register: + name: L1_CACHE_PRELOAD_CTRL + description: L1 Cache preload-operation control register + addressOffset: 216 + size: 32 + resetValue: 2 + fields: + - name: L1_CACHE_PRELOAD_ENA + description: The bit is used to enable preload operation on L1-Cache. It will be cleared by hardware automatically after preload operation is done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: L1_CACHE_PRELOAD_DONE + description: "The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_CACHE_PRELOAD_ORDER + description: "The bit is used to configure the direction of preload operation. 0: ascending, 1: descending." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: L1_CACHE_PRELOAD_RGID + description: The bit is used to set the gid of l1 cache preload. + bitOffset: 3 + bitWidth: 4 + access: read-only + - register: + name: L1_DCACHE_PRELOAD_ADDR + description: L1 Cache preload address configure register + addressOffset: 220 + size: 32 + fields: + - name: L1_CACHE_PRELOAD_ADDR + description: "Those bits are used to configure the start virtual address of preload on L1-Cache, which should be used together with L1_CACHE_PRELOAD_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: L1_DCACHE_PRELOAD_SIZE + description: L1 Cache preload size configure register + addressOffset: 224 + size: 32 + fields: + - name: L1_CACHE_PRELOAD_SIZE + description: "Those bits are used to configure the size of the first section of prelock on L1-Cache, which should be used together with L1_CACHE_PRELOAD_ADDR_REG" + bitOffset: 0 + bitWidth: 14 + access: read-write + - register: + name: L1_ICACHE0_AUTOLOAD_CTRL + description: L1 instruction Cache 0 autoload-operation control register + addressOffset: 228 + size: 32 + resetValue: 2 + fields: + - name: L1_ICACHE0_AUTOLOAD_ENA + description: "The bit is used to enable and disable autoload operation on L1-ICache0. 1: enable, 0: disable." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE0_AUTOLOAD_DONE + description: "The bit is used to indicate whether autoload operation on L1-ICache0 is finished or not. 0: not finished. 1: finished." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE0_AUTOLOAD_ORDER + description: "The bit is used to configure the direction of autoload operation on L1-ICache0. 0: ascending. 1: descending." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE0_AUTOLOAD_TRIGGER_MODE + description: "The field is used to configure trigger mode of autoload operation on L1-ICache0. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger." + bitOffset: 3 + bitWidth: 2 + access: read-only + - name: L1_ICACHE0_AUTOLOAD_SCT0_ENA + description: The bit is used to enable the first section for autoload operation on L1-ICache0. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: L1_ICACHE0_AUTOLOAD_SCT1_ENA + description: The bit is used to enable the second section for autoload operation on L1-ICache0. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: L1_ICACHE0_AUTOLOAD_RGID + description: The bit is used to set the gid of l1 icache0 autoload. + bitOffset: 10 + bitWidth: 4 + access: read-only + - register: + name: L1_ICACHE0_AUTOLOAD_SCT0_ADDR + description: L1 instruction Cache 0 autoload section 0 address configure register + addressOffset: 232 + size: 32 + fields: + - name: L1_ICACHE0_AUTOLOAD_SCT0_ADDR + description: Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_ICACHE0_AUTOLOAD_SCT0_SIZE + description: L1 instruction Cache 0 autoload section 0 size configure register + addressOffset: 236 + size: 32 + fields: + - name: L1_ICACHE0_AUTOLOAD_SCT0_SIZE + description: Those bits are used to configure the size of the first section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + bitOffset: 0 + bitWidth: 28 + access: read-only + - register: + name: L1_ICACHE0_AUTOLOAD_SCT1_ADDR + description: L1 instruction Cache 0 autoload section 1 address configure register + addressOffset: 240 + size: 32 + fields: + - name: L1_ICACHE0_AUTOLOAD_SCT1_ADDR + description: Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_ICACHE0_AUTOLOAD_SCT1_SIZE + description: L1 instruction Cache 0 autoload section 1 size configure register + addressOffset: 244 + size: 32 + fields: + - name: L1_ICACHE0_AUTOLOAD_SCT1_SIZE + description: Those bits are used to configure the size of the second section for autoload operation on L1-ICache0. Note that it should be used together with L1_ICACHE0_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + bitOffset: 0 + bitWidth: 28 + access: read-only + - register: + name: L1_ICACHE1_AUTOLOAD_CTRL + description: L1 instruction Cache 1 autoload-operation control register + addressOffset: 248 + size: 32 + resetValue: 2 + fields: + - name: L1_ICACHE1_AUTOLOAD_ENA + description: "The bit is used to enable and disable autoload operation on L1-ICache1. 1: enable, 0: disable." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_AUTOLOAD_DONE + description: "The bit is used to indicate whether autoload operation on L1-ICache1 is finished or not. 0: not finished. 1: finished." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_AUTOLOAD_ORDER + description: "The bit is used to configure the direction of autoload operation on L1-ICache1. 0: ascending. 1: descending." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_AUTOLOAD_TRIGGER_MODE + description: "The field is used to configure trigger mode of autoload operation on L1-ICache1. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger." + bitOffset: 3 + bitWidth: 2 + access: read-only + - name: L1_ICACHE1_AUTOLOAD_SCT0_ENA + description: The bit is used to enable the first section for autoload operation on L1-ICache1. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_AUTOLOAD_SCT1_ENA + description: The bit is used to enable the second section for autoload operation on L1-ICache1. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_AUTOLOAD_RGID + description: The bit is used to set the gid of l1 icache1 autoload. + bitOffset: 10 + bitWidth: 4 + access: read-only + - register: + name: L1_ICACHE1_AUTOLOAD_SCT0_ADDR + description: L1 instruction Cache 1 autoload section 0 address configure register + addressOffset: 252 + size: 32 + fields: + - name: L1_ICACHE1_AUTOLOAD_SCT0_ADDR + description: Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_ICACHE1_AUTOLOAD_SCT0_SIZE + description: L1 instruction Cache 1 autoload section 0 size configure register + addressOffset: 256 + size: 32 + fields: + - name: L1_ICACHE1_AUTOLOAD_SCT0_SIZE + description: Those bits are used to configure the size of the first section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + bitOffset: 0 + bitWidth: 28 + access: read-only + - register: + name: L1_ICACHE1_AUTOLOAD_SCT1_ADDR + description: L1 instruction Cache 1 autoload section 1 address configure register + addressOffset: 260 + size: 32 + fields: + - name: L1_ICACHE1_AUTOLOAD_SCT1_ADDR + description: Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_ICACHE1_AUTOLOAD_SCT1_SIZE + description: L1 instruction Cache 1 autoload section 1 size configure register + addressOffset: 264 + size: 32 + fields: + - name: L1_ICACHE1_AUTOLOAD_SCT1_SIZE + description: Those bits are used to configure the size of the second section for autoload operation on L1-ICache1. Note that it should be used together with L1_ICACHE1_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + bitOffset: 0 + bitWidth: 28 + access: read-only + - register: + name: L1_ICACHE2_AUTOLOAD_CTRL + description: L1 instruction Cache 2 autoload-operation control register + addressOffset: 268 + size: 32 + resetValue: 2 + fields: + - name: L1_ICACHE2_AUTOLOAD_ENA + description: "The bit is used to enable and disable autoload operation on L1-ICache2. 1: enable, 0: disable." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_AUTOLOAD_DONE + description: "The bit is used to indicate whether autoload operation on L1-ICache2 is finished or not. 0: not finished. 1: finished." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_AUTOLOAD_ORDER + description: "The bit is used to configure the direction of autoload operation on L1-ICache2. 0: ascending. 1: descending." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_AUTOLOAD_TRIGGER_MODE + description: "The field is used to configure trigger mode of autoload operation on L1-ICache2. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger." + bitOffset: 3 + bitWidth: 2 + access: read-only + - name: L1_ICACHE2_AUTOLOAD_SCT0_ENA + description: The bit is used to enable the first section for autoload operation on L1-ICache2. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_AUTOLOAD_SCT1_ENA + description: The bit is used to enable the second section for autoload operation on L1-ICache2. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_AUTOLOAD_RGID + description: The bit is used to set the gid of l1 icache2 autoload. + bitOffset: 10 + bitWidth: 4 + access: read-only + - register: + name: L1_ICACHE2_AUTOLOAD_SCT0_ADDR + description: L1 instruction Cache 2 autoload section 0 address configure register + addressOffset: 272 + size: 32 + fields: + - name: L1_ICACHE2_AUTOLOAD_SCT0_ADDR + description: Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_ICACHE2_AUTOLOAD_SCT0_SIZE + description: L1 instruction Cache 2 autoload section 0 size configure register + addressOffset: 276 + size: 32 + fields: + - name: L1_ICACHE2_AUTOLOAD_SCT0_SIZE + description: Those bits are used to configure the size of the first section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + bitOffset: 0 + bitWidth: 28 + access: read-only + - register: + name: L1_ICACHE2_AUTOLOAD_SCT1_ADDR + description: L1 instruction Cache 2 autoload section 1 address configure register + addressOffset: 280 + size: 32 + fields: + - name: L1_ICACHE2_AUTOLOAD_SCT1_ADDR + description: Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_ICACHE2_AUTOLOAD_SCT1_SIZE + description: L1 instruction Cache 2 autoload section 1 size configure register + addressOffset: 284 + size: 32 + fields: + - name: L1_ICACHE2_AUTOLOAD_SCT1_SIZE + description: Those bits are used to configure the size of the second section for autoload operation on L1-ICache2. Note that it should be used together with L1_ICACHE2_AUTOLOAD_SCT1_ADDR and L1_ICACHE_AUTOLOAD_SCT1_ENA. + bitOffset: 0 + bitWidth: 28 + access: read-only + - register: + name: L1_ICACHE3_AUTOLOAD_CTRL + description: L1 instruction Cache 3 autoload-operation control register + addressOffset: 288 + size: 32 + resetValue: 2 + fields: + - name: L1_ICACHE3_AUTOLOAD_ENA + description: "The bit is used to enable and disable autoload operation on L1-ICache3. 1: enable, 0: disable." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_AUTOLOAD_DONE + description: "The bit is used to indicate whether autoload operation on L1-ICache3 is finished or not. 0: not finished. 1: finished." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_AUTOLOAD_ORDER + description: "The bit is used to configure the direction of autoload operation on L1-ICache3. 0: ascending. 1: descending." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_AUTOLOAD_TRIGGER_MODE + description: "The field is used to configure trigger mode of autoload operation on L1-ICache3. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger." + bitOffset: 3 + bitWidth: 2 + access: read-only + - name: L1_ICACHE3_AUTOLOAD_SCT0_ENA + description: The bit is used to enable the first section for autoload operation on L1-ICache3. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_AUTOLOAD_SCT1_ENA + description: The bit is used to enable the second section for autoload operation on L1-ICache3. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_AUTOLOAD_RGID + description: The bit is used to set the gid of l1 icache3 autoload. + bitOffset: 10 + bitWidth: 4 + access: read-only + - register: + name: L1_ICACHE3_AUTOLOAD_SCT0_ADDR + description: L1 instruction Cache 3 autoload section 0 address configure register + addressOffset: 292 + size: 32 + fields: + - name: L1_ICACHE3_AUTOLOAD_SCT0_ADDR + description: Those bits are used to configure the start virtual address of the first section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_SIZE and L1_ICACHE_AUTOLOAD_SCT0_ENA. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_ICACHE3_AUTOLOAD_SCT0_SIZE + description: L1 instruction Cache 3 autoload section 0 size configure register + addressOffset: 296 + size: 32 + fields: + - name: L1_ICACHE3_AUTOLOAD_SCT0_SIZE + description: Those bits are used to configure the size of the first section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT0_ADDR and L1_ICACHE_AUTOLOAD_SCT0_ENA. + bitOffset: 0 + bitWidth: 28 + access: read-only + - register: + name: L1_ICACHE3_AUTOLOAD_SCT1_ADDR + description: L1 instruction Cache 3 autoload section 1 address configure register + addressOffset: 300 + size: 32 + fields: + - name: L1_ICACHE3_AUTOLOAD_SCT1_ADDR + description: Those bits are used to configure the start virtual address of the second section for autoload operation on L1-ICache3. Note that it should be used together with L1_ICACHE3_AUTOLOAD_SCT1_SIZE and L1_ICACHE_AUTOLOAD_SCT1_ENA. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_ICACHE3_AUTOLOAD_SCT1_SIZE + description: L1 instruction Cache 3 autoload section 1 size configure register + addressOffset: 304 + size: 32 + fields: + - name: L1_ICACHE3_AUTOLOAD_SCT1_SIZE + description: Reserved + bitOffset: 0 + bitWidth: 28 + access: read-only + - register: + name: L1_CACHE_AUTOLOAD_CTRL + description: L1 Cache autoload-operation control register + addressOffset: 308 + size: 32 + resetValue: 2 + fields: + - name: L1_CACHE_AUTOLOAD_ENA + description: "The bit is used to enable and disable autoload operation on L1-Cache. 1: enable, 0: disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: L1_CACHE_AUTOLOAD_DONE + description: "The bit is used to indicate whether autoload operation on L1-Cache is finished or not. 0: not finished. 1: finished." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_CACHE_AUTOLOAD_ORDER + description: "The bit is used to configure the direction of autoload operation on L1-Cache. 0: ascending. 1: descending." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: L1_CACHE_AUTOLOAD_TRIGGER_MODE + description: "The field is used to configure trigger mode of autoload operation on L1-Cache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger." + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: L1_CACHE_AUTOLOAD_SCT0_ENA + description: The bit is used to enable the first section for autoload operation on L1-Cache. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: L1_CACHE_AUTOLOAD_SCT1_ENA + description: The bit is used to enable the second section for autoload operation on L1-Cache. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: L1_CACHE_AUTOLOAD_SCT2_ENA + description: The bit is used to enable the third section for autoload operation on L1-Cache. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: L1_CACHE_AUTOLOAD_SCT3_ENA + description: The bit is used to enable the fourth section for autoload operation on L1-Cache. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: L1_CACHE_AUTOLOAD_RGID + description: The bit is used to set the gid of l1 cache autoload. + bitOffset: 12 + bitWidth: 4 + access: read-only + - register: + name: L1_CACHE_AUTOLOAD_SCT0_ADDR + description: L1 Cache autoload section 0 address configure register + addressOffset: 312 + size: 32 + fields: + - name: L1_CACHE_AUTOLOAD_SCT0_ADDR + description: Those bits are used to configure the start virtual address of the first section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT0_SIZE and L1_CACHE_AUTOLOAD_SCT0_ENA. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: L1_CACHE_AUTOLOAD_SCT0_SIZE + description: L1 Cache autoload section 0 size configure register + addressOffset: 316 + size: 32 + fields: + - name: L1_CACHE_AUTOLOAD_SCT0_SIZE + description: Those bits are used to configure the size of the first section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT0_ADDR and L1_CACHE_AUTOLOAD_SCT0_ENA. + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + name: L1_CACHE_AUTOLOAD_SCT1_ADDR + description: L1 Cache autoload section 1 address configure register + addressOffset: 320 + size: 32 + fields: + - name: L1_CACHE_AUTOLOAD_SCT1_ADDR + description: Those bits are used to configure the start virtual address of the second section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT1_SIZE and L1_CACHE_AUTOLOAD_SCT1_ENA. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: L1_CACHE_AUTOLOAD_SCT1_SIZE + description: L1 Cache autoload section 1 size configure register + addressOffset: 324 + size: 32 + fields: + - name: L1_CACHE_AUTOLOAD_SCT1_SIZE + description: Those bits are used to configure the size of the second section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT1_ADDR and L1_CACHE_AUTOLOAD_SCT1_ENA. + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + name: L1_CACHE_AUTOLOAD_SCT2_ADDR + description: L1 Cache autoload section 2 address configure register + addressOffset: 328 + size: 32 + fields: + - name: L1_CACHE_AUTOLOAD_SCT2_ADDR + description: Those bits are used to configure the start virtual address of the third section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT2_SIZE and L1_CACHE_AUTOLOAD_SCT2_ENA. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_CACHE_AUTOLOAD_SCT2_SIZE + description: L1 Cache autoload section 2 size configure register + addressOffset: 332 + size: 32 + fields: + - name: L1_CACHE_AUTOLOAD_SCT2_SIZE + description: Those bits are used to configure the size of the third section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT2_ADDR and L1_CACHE_AUTOLOAD_SCT2_ENA. + bitOffset: 0 + bitWidth: 28 + access: read-only + - register: + name: L1_CACHE_AUTOLOAD_SCT3_ADDR + description: L1 Cache autoload section 1 address configure register + addressOffset: 336 + size: 32 + fields: + - name: L1_CACHE_AUTOLOAD_SCT3_ADDR + description: Those bits are used to configure the start virtual address of the fourth section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT3_SIZE and L1_CACHE_AUTOLOAD_SCT3_ENA. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_CACHE_AUTOLOAD_SCT3_SIZE + description: L1 Cache autoload section 1 size configure register + addressOffset: 340 + size: 32 + fields: + - name: L1_CACHE_AUTOLOAD_SCT3_SIZE + description: Those bits are used to configure the size of the fourth section for autoload operation on L1-Cache. Note that it should be used together with L1_CACHE_AUTOLOAD_SCT3_ADDR and L1_CACHE_AUTOLOAD_SCT3_ENA. + bitOffset: 0 + bitWidth: 28 + access: read-only + - register: + name: L1_CACHE_ACS_CNT_INT_ENA + description: Cache Access Counter Interrupt enable register + addressOffset: 344 + size: 32 + fields: + - name: L1_IBUS0_OVF_INT_ENA + description: The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_IBUS1_OVF_INT_ENA + description: The bit is used to enable interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_IBUS2_OVF_INT_ENA + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_IBUS3_OVF_INT_ENA + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L1_BUS0_OVF_INT_ENA + description: The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: L1_BUS1_OVF_INT_ENA + description: The bit is used to enable interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: L1_DBUS2_OVF_INT_ENA + description: Reserved + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: L1_DBUS3_OVF_INT_ENA + description: Reserved + bitOffset: 7 + bitWidth: 1 + access: read-only + - register: + name: L1_CACHE_ACS_CNT_INT_CLR + description: Cache Access Counter Interrupt clear register + addressOffset: 348 + size: 32 + fields: + - name: L1_IBUS0_OVF_INT_CLR + description: The bit is used to clear counters overflow interrupt and counters in L1-ICache0 due to bus0 accesses L1-ICache0. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_IBUS1_OVF_INT_CLR + description: The bit is used to clear counters overflow interrupt and counters in L1-ICache1 due to bus1 accesses L1-ICache1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_IBUS2_OVF_INT_CLR + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_IBUS3_OVF_INT_CLR + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L1_BUS0_OVF_INT_CLR + description: The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus0 accesses L1-DCache. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: L1_BUS1_OVF_INT_CLR + description: The bit is used to clear counters overflow interrupt and counters in L1-DCache due to bus1 accesses L1-DCache. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: L1_DBUS2_OVF_INT_CLR + description: Reserved + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: L1_DBUS3_OVF_INT_CLR + description: Reserved + bitOffset: 7 + bitWidth: 1 + access: read-only + - register: + name: L1_CACHE_ACS_CNT_INT_RAW + description: Cache Access Counter Interrupt raw register + addressOffset: 352 + size: 32 + fields: + - name: L1_IBUS0_OVF_INT_RAW + description: The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: L1_IBUS1_OVF_INT_RAW + description: The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: L1_IBUS2_OVF_INT_RAW + description: The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache2 due to bus2 accesses L1-ICache2. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: L1_IBUS3_OVF_INT_RAW + description: The raw bit of the interrupt of one of counters overflow that occurs in L1-ICache3 due to bus3 accesses L1-ICache3. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: L1_BUS0_OVF_INT_RAW + description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: L1_BUS1_OVF_INT_RAW + description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: L1_DBUS2_OVF_INT_RAW + description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus2 accesses L1-DCache. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: L1_DBUS3_OVF_INT_RAW + description: The raw bit of the interrupt of one of counters overflow that occurs in L1-DCache due to bus3 accesses L1-DCache. + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: L1_CACHE_ACS_CNT_INT_ST + description: Cache Access Counter Interrupt status register + addressOffset: 356 + size: 32 + fields: + - name: L1_IBUS0_OVF_INT_ST + description: The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache0 due to bus0 accesses L1-ICache0. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_IBUS1_OVF_INT_ST + description: The bit indicates the interrupt status of one of counters overflow that occurs in L1-ICache1 due to bus1 accesses L1-ICache1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_IBUS2_OVF_INT_ST + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_IBUS3_OVF_INT_ST + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L1_BUS0_OVF_INT_ST + description: The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus0 accesses L1-DCache. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: L1_BUS1_OVF_INT_ST + description: The bit indicates the interrupt status of one of counters overflow that occurs in L1-DCache due to bus1 accesses L1-DCache. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: L1_DBUS2_OVF_INT_ST + description: Reserved + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: L1_DBUS3_OVF_INT_ST + description: Reserved + bitOffset: 7 + bitWidth: 1 + access: read-only + - register: + name: L1_CACHE_ACS_FAIL_INT_ENA + description: Cache Access Fail Interrupt enable register + addressOffset: 360 + size: 32 + fields: + - name: L1_ICACHE0_FAIL_INT_ENA + description: The bit is used to enable interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_FAIL_INT_ENA + description: The bit is used to enable interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_FAIL_INT_ENA + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_FAIL_INT_ENA + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L1_CACHE_FAIL_INT_ENA + description: The bit is used to enable interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: L1_CACHE_ACS_FAIL_INT_CLR + description: L1-Cache Access Fail Interrupt clear register + addressOffset: 364 + size: 32 + fields: + - name: L1_ICACHE0_FAIL_INT_CLR + description: The bit is used to clear interrupt of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache0. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_FAIL_INT_CLR + description: The bit is used to clear interrupt of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_FAIL_INT_CLR + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_FAIL_INT_CLR + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L1_CACHE_FAIL_INT_CLR + description: The bit is used to clear interrupt of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. + bitOffset: 4 + bitWidth: 1 + access: write-only + - register: + name: L1_CACHE_ACS_FAIL_INT_RAW + description: Cache Access Fail Interrupt raw register + addressOffset: 368 + size: 32 + fields: + - name: L1_ICACHE0_FAIL_INT_RAW + description: The raw bit of the interrupt of access fail that occurs in L1-ICache0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: L1_ICACHE1_FAIL_INT_RAW + description: The raw bit of the interrupt of access fail that occurs in L1-ICache1. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: L1_ICACHE2_FAIL_INT_RAW + description: The raw bit of the interrupt of access fail that occurs in L1-ICache2. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: L1_ICACHE3_FAIL_INT_RAW + description: The raw bit of the interrupt of access fail that occurs in L1-ICache3. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: L1_CACHE_FAIL_INT_RAW + description: The raw bit of the interrupt of access fail that occurs in L1-DCache. + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: L1_CACHE_ACS_FAIL_INT_ST + description: Cache Access Fail Interrupt status register + addressOffset: 372 + size: 32 + fields: + - name: L1_ICACHE0_FAIL_INT_ST + description: The bit indicates the interrupt status of access fail that occurs in L1-ICache0 due to cpu accesses L1-ICache. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_FAIL_INT_ST + description: The bit indicates the interrupt status of access fail that occurs in L1-ICache1 due to cpu accesses L1-ICache. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_FAIL_INT_ST + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_FAIL_INT_ST + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L1_CACHE_FAIL_INT_ST + description: The bit indicates the interrupt status of access fail that occurs in L1-DCache due to cpu accesses L1-DCache. + bitOffset: 4 + bitWidth: 1 + access: read-only + - register: + name: L1_CACHE_ACS_CNT_CTRL + description: Cache Access Counter enable and clear register + addressOffset: 376 + size: 32 + fields: + - name: L1_IBUS0_CNT_ENA + description: The bit is used to enable ibus0 counter in L1-ICache0. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_IBUS1_CNT_ENA + description: The bit is used to enable ibus1 counter in L1-ICache1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_IBUS2_CNT_ENA + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_IBUS3_CNT_ENA + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L1_BUS0_CNT_ENA + description: The bit is used to enable dbus0 counter in L1-DCache. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: L1_BUS1_CNT_ENA + description: The bit is used to enable dbus1 counter in L1-DCache. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: L1_DBUS2_CNT_ENA + description: Reserved + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: L1_DBUS3_CNT_ENA + description: Reserved + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: L1_IBUS0_CNT_CLR + description: The bit is used to clear ibus0 counter in L1-ICache0. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: L1_IBUS1_CNT_CLR + description: The bit is used to clear ibus1 counter in L1-ICache1. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: L1_IBUS2_CNT_CLR + description: Reserved + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: L1_IBUS3_CNT_CLR + description: Reserved + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: L1_BUS0_CNT_CLR + description: The bit is used to clear dbus0 counter in L1-DCache. + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: L1_BUS1_CNT_CLR + description: The bit is used to clear dbus1 counter in L1-DCache. + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: L1_DBUS2_CNT_CLR + description: Reserved + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: L1_DBUS3_CNT_CLR + description: Reserved + bitOffset: 23 + bitWidth: 1 + access: read-only + - register: + name: L1_IBUS0_ACS_HIT_CNT + description: L1-ICache bus0 Hit-Access Counter register + addressOffset: 380 + size: 32 + fields: + - name: L1_IBUS0_HIT_CNT + description: The register records the number of hits when bus0 accesses L1-ICache0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_IBUS0_ACS_MISS_CNT + description: L1-ICache bus0 Miss-Access Counter register + addressOffset: 384 + size: 32 + fields: + - name: L1_IBUS0_MISS_CNT + description: The register records the number of missing when bus0 accesses L1-ICache0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_IBUS0_ACS_CONFLICT_CNT + description: L1-ICache bus0 Conflict-Access Counter register + addressOffset: 388 + size: 32 + fields: + - name: L1_IBUS0_CONFLICT_CNT + description: The register records the number of access-conflicts when bus0 accesses L1-ICache0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_IBUS0_ACS_NXTLVL_CNT + description: L1-ICache bus0 Next-Level-Access Counter register + addressOffset: 392 + size: 32 + fields: + - name: L1_IBUS0_NXTLVL_CNT + description: The register records the number of times that L1-ICache accesses L2-Cache due to bus0 accessing L1-ICache0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_IBUS1_ACS_HIT_CNT + description: L1-ICache bus1 Hit-Access Counter register + addressOffset: 396 + size: 32 + fields: + - name: L1_IBUS1_HIT_CNT + description: The register records the number of hits when bus1 accesses L1-ICache1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_IBUS1_ACS_MISS_CNT + description: L1-ICache bus1 Miss-Access Counter register + addressOffset: 400 + size: 32 + fields: + - name: L1_IBUS1_MISS_CNT + description: The register records the number of missing when bus1 accesses L1-ICache1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_IBUS1_ACS_CONFLICT_CNT + description: L1-ICache bus1 Conflict-Access Counter register + addressOffset: 404 + size: 32 + fields: + - name: L1_IBUS1_CONFLICT_CNT + description: The register records the number of access-conflicts when bus1 accesses L1-ICache1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_IBUS1_ACS_NXTLVL_CNT + description: L1-ICache bus1 Next-Level-Access Counter register + addressOffset: 408 + size: 32 + fields: + - name: L1_IBUS1_NXTLVL_CNT + description: The register records the number of times that L1-ICache accesses L2-Cache due to bus1 accessing L1-ICache1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_IBUS2_ACS_HIT_CNT + description: L1-ICache bus2 Hit-Access Counter register + addressOffset: 412 + size: 32 + fields: + - name: L1_IBUS2_HIT_CNT + description: The register records the number of hits when bus2 accesses L1-ICache2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_IBUS2_ACS_MISS_CNT + description: L1-ICache bus2 Miss-Access Counter register + addressOffset: 416 + size: 32 + fields: + - name: L1_IBUS2_MISS_CNT + description: The register records the number of missing when bus2 accesses L1-ICache2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_IBUS2_ACS_CONFLICT_CNT + description: L1-ICache bus2 Conflict-Access Counter register + addressOffset: 420 + size: 32 + fields: + - name: L1_IBUS2_CONFLICT_CNT + description: The register records the number of access-conflicts when bus2 accesses L1-ICache2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_IBUS2_ACS_NXTLVL_CNT + description: L1-ICache bus2 Next-Level-Access Counter register + addressOffset: 424 + size: 32 + fields: + - name: L1_IBUS2_NXTLVL_CNT + description: The register records the number of times that L1-ICache accesses L2-Cache due to bus2 accessing L1-ICache2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_IBUS3_ACS_HIT_CNT + description: L1-ICache bus3 Hit-Access Counter register + addressOffset: 428 + size: 32 + fields: + - name: L1_IBUS3_HIT_CNT + description: The register records the number of hits when bus3 accesses L1-ICache3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_IBUS3_ACS_MISS_CNT + description: L1-ICache bus3 Miss-Access Counter register + addressOffset: 432 + size: 32 + fields: + - name: L1_IBUS3_MISS_CNT + description: The register records the number of missing when bus3 accesses L1-ICache3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_IBUS3_ACS_CONFLICT_CNT + description: L1-ICache bus3 Conflict-Access Counter register + addressOffset: 436 + size: 32 + fields: + - name: L1_IBUS3_CONFLICT_CNT + description: The register records the number of access-conflicts when bus3 accesses L1-ICache3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_IBUS3_ACS_NXTLVL_CNT + description: L1-ICache bus3 Next-Level-Access Counter register + addressOffset: 440 + size: 32 + fields: + - name: L1_IBUS3_NXTLVL_CNT + description: The register records the number of times that L1-ICache accesses L2-Cache due to bus3 accessing L1-ICache3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_BUS0_ACS_HIT_CNT + description: L1-Cache bus0 Hit-Access Counter register + addressOffset: 444 + size: 32 + fields: + - name: L1_BUS0_HIT_CNT + description: The register records the number of hits when bus0 accesses L1-Cache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_BUS0_ACS_MISS_CNT + description: L1-Cache bus0 Miss-Access Counter register + addressOffset: 448 + size: 32 + fields: + - name: L1_BUS0_MISS_CNT + description: The register records the number of missing when bus0 accesses L1-Cache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_BUS0_ACS_CONFLICT_CNT + description: L1-Cache bus0 Conflict-Access Counter register + addressOffset: 452 + size: 32 + fields: + - name: L1_BUS0_CONFLICT_CNT + description: The register records the number of access-conflicts when bus0 accesses L1-Cache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_BUS0_ACS_NXTLVL_CNT + description: L1-Cache bus0 Next-Level-Access Counter register + addressOffset: 456 + size: 32 + fields: + - name: L1_BUS0_NXTLVL_CNT + description: The register records the number of times that L1-Cache accesses L2-Cache due to bus0 accessing L1-Cache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_BUS1_ACS_HIT_CNT + description: L1-Cache bus1 Hit-Access Counter register + addressOffset: 460 + size: 32 + fields: + - name: L1_BUS1_HIT_CNT + description: The register records the number of hits when bus1 accesses L1-Cache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_BUS1_ACS_MISS_CNT + description: L1-Cache bus1 Miss-Access Counter register + addressOffset: 464 + size: 32 + fields: + - name: L1_BUS1_MISS_CNT + description: The register records the number of missing when bus1 accesses L1-Cache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_BUS1_ACS_CONFLICT_CNT + description: L1-Cache bus1 Conflict-Access Counter register + addressOffset: 468 + size: 32 + fields: + - name: L1_BUS1_CONFLICT_CNT + description: The register records the number of access-conflicts when bus1 accesses L1-Cache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_BUS1_ACS_NXTLVL_CNT + description: L1-Cache bus1 Next-Level-Access Counter register + addressOffset: 472 + size: 32 + fields: + - name: L1_BUS1_NXTLVL_CNT + description: The register records the number of times that L1-Cache accesses L2-Cache due to bus1 accessing L1-Cache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_DBUS2_ACS_HIT_CNT + description: L1-DCache bus2 Hit-Access Counter register + addressOffset: 476 + size: 32 + fields: + - name: L1_DBUS2_HIT_CNT + description: The register records the number of hits when bus2 accesses L1-DCache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_DBUS2_ACS_MISS_CNT + description: L1-DCache bus2 Miss-Access Counter register + addressOffset: 480 + size: 32 + fields: + - name: L1_DBUS2_MISS_CNT + description: The register records the number of missing when bus2 accesses L1-DCache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_DBUS2_ACS_CONFLICT_CNT + description: L1-DCache bus2 Conflict-Access Counter register + addressOffset: 484 + size: 32 + fields: + - name: L1_DBUS2_CONFLICT_CNT + description: The register records the number of access-conflicts when bus2 accesses L1-DCache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_DBUS2_ACS_NXTLVL_CNT + description: L1-DCache bus2 Next-Level-Access Counter register + addressOffset: 488 + size: 32 + fields: + - name: L1_DBUS2_NXTLVL_CNT + description: The register records the number of times that L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_DBUS3_ACS_HIT_CNT + description: L1-DCache bus3 Hit-Access Counter register + addressOffset: 492 + size: 32 + fields: + - name: L1_DBUS3_HIT_CNT + description: The register records the number of hits when bus3 accesses L1-DCache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_DBUS3_ACS_MISS_CNT + description: L1-DCache bus3 Miss-Access Counter register + addressOffset: 496 + size: 32 + fields: + - name: L1_DBUS3_MISS_CNT + description: The register records the number of missing when bus3 accesses L1-DCache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_DBUS3_ACS_CONFLICT_CNT + description: L1-DCache bus3 Conflict-Access Counter register + addressOffset: 500 + size: 32 + fields: + - name: L1_DBUS3_CONFLICT_CNT + description: The register records the number of access-conflicts when bus3 accesses L1-DCache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_DBUS3_ACS_NXTLVL_CNT + description: L1-DCache bus3 Next-Level-Access Counter register + addressOffset: 504 + size: 32 + fields: + - name: L1_DBUS3_NXTLVL_CNT + description: The register records the number of times that L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_ICACHE0_ACS_FAIL_ID_ATTR + description: L1-ICache0 Access Fail ID/attribution information register + addressOffset: 508 + size: 32 + fields: + - name: L1_ICACHE0_FAIL_ID + description: The register records the ID of fail-access when cache0 accesses L1-ICache. + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: L1_ICACHE0_FAIL_ATTR + description: The register records the attribution of fail-access when cache0 accesses L1-ICache. + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: L1_ICACHE0_ACS_FAIL_ADDR + description: L1-ICache0 Access Fail Address information register + addressOffset: 512 + size: 32 + fields: + - name: L1_ICACHE0_FAIL_ADDR + description: The register records the address of fail-access when cache0 accesses L1-ICache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_ICACHE1_ACS_FAIL_ID_ATTR + description: L1-ICache0 Access Fail ID/attribution information register + addressOffset: 516 + size: 32 + fields: + - name: L1_ICACHE1_FAIL_ID + description: The register records the ID of fail-access when cache1 accesses L1-ICache. + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: L1_ICACHE1_FAIL_ATTR + description: The register records the attribution of fail-access when cache1 accesses L1-ICache. + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: L1_ICACHE1_ACS_FAIL_ADDR + description: L1-ICache0 Access Fail Address information register + addressOffset: 520 + size: 32 + fields: + - name: L1_ICACHE1_FAIL_ADDR + description: The register records the address of fail-access when cache1 accesses L1-ICache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_ICACHE2_ACS_FAIL_ID_ATTR + description: L1-ICache0 Access Fail ID/attribution information register + addressOffset: 524 + size: 32 + fields: + - name: L1_ICACHE2_FAIL_ID + description: The register records the ID of fail-access when cache2 accesses L1-ICache. + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: L1_ICACHE2_FAIL_ATTR + description: The register records the attribution of fail-access when cache2 accesses L1-ICache. + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: L1_ICACHE2_ACS_FAIL_ADDR + description: L1-ICache0 Access Fail Address information register + addressOffset: 528 + size: 32 + fields: + - name: L1_ICACHE2_FAIL_ADDR + description: The register records the address of fail-access when cache2 accesses L1-ICache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_ICACHE3_ACS_FAIL_ID_ATTR + description: L1-ICache0 Access Fail ID/attribution information register + addressOffset: 532 + size: 32 + fields: + - name: L1_ICACHE3_FAIL_ID + description: The register records the ID of fail-access when cache3 accesses L1-ICache. + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: L1_ICACHE3_FAIL_ATTR + description: The register records the attribution of fail-access when cache3 accesses L1-ICache. + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: L1_ICACHE3_ACS_FAIL_ADDR + description: L1-ICache0 Access Fail Address information register + addressOffset: 536 + size: 32 + fields: + - name: L1_ICACHE3_FAIL_ADDR + description: The register records the address of fail-access when cache3 accesses L1-ICache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_CACHE_ACS_FAIL_ID_ATTR + description: L1-Cache Access Fail ID/attribution information register + addressOffset: 540 + size: 32 + fields: + - name: L1_CACHE_FAIL_ID + description: The register records the ID of fail-access when cache accesses L1-Cache. + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: L1_CACHE_FAIL_ATTR + description: The register records the attribution of fail-access when cache accesses L1-Cache. + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: L1_DCACHE_ACS_FAIL_ADDR + description: L1-Cache Access Fail Address information register + addressOffset: 544 + size: 32 + fields: + - name: L1_CACHE_FAIL_ADDR + description: The register records the address of fail-access when cache accesses L1-Cache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L1_CACHE_SYNC_PRELOAD_INT_ENA + description: L1-Cache Access Fail Interrupt enable register + addressOffset: 548 + size: 32 + fields: + - name: L1_ICACHE0_PLD_DONE_INT_ENA + description: "The bit is used to enable interrupt of L1-ICache0 preload-operation. If preload operation is done, interrupt occurs." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_PLD_DONE_INT_ENA + description: "The bit is used to enable interrupt of L1-ICache1 preload-operation. If preload operation is done, interrupt occurs." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_PLD_DONE_INT_ENA + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_PLD_DONE_INT_ENA + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L1_CACHE_PLD_DONE_INT_ENA + description: "The bit is used to enable interrupt of L1-Cache preload-operation. If preload operation is done, interrupt occurs." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CACHE_SYNC_DONE_INT_ENA + description: The bit is used to enable interrupt of Cache sync-operation done. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: L1_ICACHE0_PLD_ERR_INT_ENA + description: The bit is used to enable interrupt of L1-ICache0 preload-operation error. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_PLD_ERR_INT_ENA + description: The bit is used to enable interrupt of L1-ICache1 preload-operation error. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_PLD_ERR_INT_ENA + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_PLD_ERR_INT_ENA + description: Reserved + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: L1_CACHE_PLD_ERR_INT_ENA + description: The bit is used to enable interrupt of L1-Cache preload-operation error. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CACHE_SYNC_ERR_INT_ENA + description: The bit is used to enable interrupt of Cache sync-operation error. + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: L1_CACHE_SYNC_PRELOAD_INT_CLR + description: Sync Preload operation Interrupt clear register + addressOffset: 552 + size: 32 + fields: + - name: L1_ICACHE0_PLD_DONE_INT_CLR + description: The bit is used to clear interrupt that occurs only when L1-ICache0 preload-operation is done. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_PLD_DONE_INT_CLR + description: The bit is used to clear interrupt that occurs only when L1-ICache1 preload-operation is done. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_PLD_DONE_INT_CLR + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_PLD_DONE_INT_CLR + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L1_CACHE_PLD_DONE_INT_CLR + description: The bit is used to clear interrupt that occurs only when L1-Cache preload-operation is done. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: CACHE_SYNC_DONE_INT_CLR + description: The bit is used to clear interrupt that occurs only when Cache sync-operation is done. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: L1_ICACHE0_PLD_ERR_INT_CLR + description: The bit is used to clear interrupt of L1-ICache0 preload-operation error. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_PLD_ERR_INT_CLR + description: The bit is used to clear interrupt of L1-ICache1 preload-operation error. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_PLD_ERR_INT_CLR + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_PLD_ERR_INT_CLR + description: Reserved + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: L1_CACHE_PLD_ERR_INT_CLR + description: The bit is used to clear interrupt of L1-Cache preload-operation error. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: CACHE_SYNC_ERR_INT_CLR + description: The bit is used to clear interrupt of Cache sync-operation error. + bitOffset: 13 + bitWidth: 1 + access: write-only + - register: + name: L1_CACHE_SYNC_PRELOAD_INT_RAW + description: Sync Preload operation Interrupt raw register + addressOffset: 556 + size: 32 + fields: + - name: L1_ICACHE0_PLD_DONE_INT_RAW + description: The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation is done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: L1_ICACHE1_PLD_DONE_INT_RAW + description: The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation is done. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: L1_ICACHE2_PLD_DONE_INT_RAW + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: L1_ICACHE3_PLD_DONE_INT_RAW + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: L1_CACHE_PLD_DONE_INT_RAW + description: The raw bit of the interrupt that occurs only when L1-Cache preload-operation is done. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CACHE_SYNC_DONE_INT_RAW + description: The raw bit of the interrupt that occurs only when Cache sync-operation is done. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: L1_ICACHE0_PLD_ERR_INT_RAW + description: The raw bit of the interrupt that occurs only when L1-ICache0 preload-operation error occurs. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: L1_ICACHE1_PLD_ERR_INT_RAW + description: The raw bit of the interrupt that occurs only when L1-ICache1 preload-operation error occurs. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: L1_ICACHE2_PLD_ERR_INT_RAW + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: L1_ICACHE3_PLD_ERR_INT_RAW + description: Reserved + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: L1_CACHE_PLD_ERR_INT_RAW + description: The raw bit of the interrupt that occurs only when L1-Cache preload-operation error occurs. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CACHE_SYNC_ERR_INT_RAW + description: The raw bit of the interrupt that occurs only when Cache sync-operation error occurs. + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: L1_CACHE_SYNC_PRELOAD_INT_ST + description: L1-Cache Access Fail Interrupt status register + addressOffset: 560 + size: 32 + fields: + - name: L1_ICACHE0_PLD_DONE_INT_ST + description: The bit indicates the status of the interrupt that occurs only when L1-ICache0 preload-operation is done. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_PLD_DONE_INT_ST + description: The bit indicates the status of the interrupt that occurs only when L1-ICache1 preload-operation is done. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_PLD_DONE_INT_ST + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_PLD_DONE_INT_ST + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L1_CACHE_PLD_DONE_INT_ST + description: The bit indicates the status of the interrupt that occurs only when L1-Cache preload-operation is done. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: CACHE_SYNC_DONE_INT_ST + description: The bit indicates the status of the interrupt that occurs only when Cache sync-operation is done. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: L1_ICACHE0_PLD_ERR_INT_ST + description: The bit indicates the status of the interrupt of L1-ICache0 preload-operation error. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_PLD_ERR_INT_ST + description: The bit indicates the status of the interrupt of L1-ICache1 preload-operation error. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_PLD_ERR_INT_ST + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_PLD_ERR_INT_ST + description: Reserved + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: L1_CACHE_PLD_ERR_INT_ST + description: The bit indicates the status of the interrupt of L1-Cache preload-operation error. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: CACHE_SYNC_ERR_INT_ST + description: The bit indicates the status of the interrupt of Cache sync-operation error. + bitOffset: 13 + bitWidth: 1 + access: read-only + - register: + name: L1_CACHE_SYNC_PRELOAD_EXCEPTION + description: Cache Sync/Preload Operation exception register + addressOffset: 564 + size: 32 + fields: + - name: L1_ICACHE0_PLD_ERR_CODE + description: The value 2 is Only available which means preload size is error in L1-ICache0. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: L1_ICACHE1_PLD_ERR_CODE + description: The value 2 is Only available which means preload size is error in L1-ICache1. + bitOffset: 2 + bitWidth: 2 + access: read-only + - name: L1_ICACHE2_PLD_ERR_CODE + description: Reserved + bitOffset: 4 + bitWidth: 2 + access: read-only + - name: L1_ICACHE3_PLD_ERR_CODE + description: Reserved + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: L1_CACHE_PLD_ERR_CODE + description: The value 2 is Only available which means preload size is error in L1-Cache. + bitOffset: 8 + bitWidth: 2 + access: read-only + - name: CACHE_SYNC_ERR_CODE + description: "The values 0-2 are available which means sync map, command conflict and size are error in Cache System." + bitOffset: 12 + bitWidth: 2 + access: read-only + - register: + name: L1_CACHE_SYNC_RST_CTRL + description: Cache Sync Reset control register + addressOffset: 568 + size: 32 + fields: + - name: L1_ICACHE0_SYNC_RST + description: set this bit to reset sync-logic inside L1-ICache0. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_SYNC_RST + description: set this bit to reset sync-logic inside L1-ICache1. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_SYNC_RST + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_SYNC_RST + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L1_CACHE_SYNC_RST + description: set this bit to reset sync-logic inside L1-Cache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: L1_CACHE_PRELOAD_RST_CTRL + description: Cache Preload Reset control register + addressOffset: 572 + size: 32 + fields: + - name: L1_ICACHE0_PLD_RST + description: set this bit to reset preload-logic inside L1-ICache0. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_PLD_RST + description: set this bit to reset preload-logic inside L1-ICache1. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_PLD_RST + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_PLD_RST + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L1_CACHE_PLD_RST + description: set this bit to reset preload-logic inside L1-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: L1_CACHE_AUTOLOAD_BUF_CLR_CTRL + description: Cache Autoload buffer clear control register + addressOffset: 576 + size: 32 + fields: + - name: L1_ICACHE0_ALD_BUF_CLR + description: "set this bit to clear autoload-buffer inside L1-ICache0. If this bit is active, autoload will not work in L1-ICache0. This bit should not be active when autoload works in L1-ICache0." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_ALD_BUF_CLR + description: "set this bit to clear autoload-buffer inside L1-ICache1. If this bit is active, autoload will not work in L1-ICache1. This bit should not be active when autoload works in L1-ICache1." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_ALD_BUF_CLR + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_ALD_BUF_CLR + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L1_CACHE_ALD_BUF_CLR + description: "set this bit to clear autoload-buffer inside L1-Cache. If this bit is active, autoload will not work in L1-Cache. This bit should not be active when autoload works in L1-Cache." + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: L1_UNALLOCATE_BUFFER_CLEAR + description: Unallocate request buffer clear registers + addressOffset: 580 + size: 32 + fields: + - name: L1_ICACHE0_UNALLOC_CLR + description: The bit is used to clear the unallocate request buffer of l1 icache0 where the unallocate request is responsed but not completed. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_UNALLOC_CLR + description: The bit is used to clear the unallocate request buffer of l1 icache1 where the unallocate request is responsed but not completed. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_UNALLOC_CLR + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_UNALLOC_CLR + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L1_CACHE_UNALLOC_CLR + description: The bit is used to clear the unallocate request buffer of l1 cache where the unallocate request is responsed but not completed. + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: L1_CACHE_OBJECT_CTRL + description: Cache Tag and Data memory Object control register + addressOffset: 584 + size: 32 + fields: + - name: L1_ICACHE0_TAG_OBJECT + description: Set this bit to set L1-ICache0 tag memory as object. This bit should be onehot with the others fields inside this register. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_TAG_OBJECT + description: Set this bit to set L1-ICache1 tag memory as object. This bit should be onehot with the others fields inside this register. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_TAG_OBJECT + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_TAG_OBJECT + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L1_CACHE_TAG_OBJECT + description: Set this bit to set L1-Cache tag memory as object. This bit should be onehot with the others fields inside this register. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: L1_ICACHE0_MEM_OBJECT + description: Set this bit to set L1-ICache0 data memory as object. This bit should be onehot with the others fields inside this register. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: L1_ICACHE1_MEM_OBJECT + description: Set this bit to set L1-ICache1 data memory as object. This bit should be onehot with the others fields inside this register. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: L1_ICACHE2_MEM_OBJECT + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: L1_ICACHE3_MEM_OBJECT + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: L1_CACHE_MEM_OBJECT + description: Set this bit to set L1-Cache data memory as object. This bit should be onehot with the others fields inside this register. + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: L1_CACHE_WAY_OBJECT + description: Cache Tag and Data memory way register + addressOffset: 588 + size: 32 + fields: + - name: L1_CACHE_WAY_OBJECT + description: "Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7." + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: L1_CACHE_VADDR + description: Cache Vaddr register + addressOffset: 592 + size: 32 + resetValue: 1073741824 + fields: + - name: L1_CACHE_VADDR + description: Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: L1_CACHE_DEBUG_BUS + description: Cache Tag/data memory content register + addressOffset: 596 + size: 32 + resetValue: 596 + fields: + - name: L1_CACHE_DEBUG_BUS + description: This is a constant place where we can write data to or read data from the tag/data memory on the specified cache. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LEVEL_SPLIT0 + description: USED TO SPLIT L1 CACHE AND L2 CACHE + addressOffset: 600 + size: 32 + resetValue: 600 + fields: + - name: LEVEL_SPLIT0 + description: Reserved + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_CACHE_CTRL + description: L2 Cache(L2-Cache) control register + addressOffset: 604 + size: 32 + fields: + - name: L2_CACHE_SHUT_DMA + description: "The bit is used to disable DMA access L2-Cache, 0: enable, 1: disable" + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: L2_CACHE_UNDEF_OP + description: Reserved + bitOffset: 5 + bitWidth: 4 + access: read-only + - register: + name: L2_BYPASS_CACHE_CONF + description: Bypass Cache configure register + addressOffset: 608 + size: 32 + fields: + - name: BYPASS_L2_CACHE_EN + description: "The bit is used to enable bypass L2-Cache. 0: disable bypass, 1: enable bypass." + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: L2_CACHE_CACHESIZE_CONF + description: L2 Cache CacheSize mode configure register + addressOffset: 612 + size: 32 + fields: + - name: L2_CACHE_CACHESIZE_1K + description: The field is used to configure cachesize of L2-Cache as 1k bytes. This field and all other fields within this register is onehot. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L2_CACHE_CACHESIZE_2K + description: The field is used to configure cachesize of L2-Cache as 2k bytes. This field and all other fields within this register is onehot. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L2_CACHE_CACHESIZE_4K + description: The field is used to configure cachesize of L2-Cache as 4k bytes. This field and all other fields within this register is onehot. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L2_CACHE_CACHESIZE_8K + description: The field is used to configure cachesize of L2-Cache as 8k bytes. This field and all other fields within this register is onehot. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L2_CACHE_CACHESIZE_16K + description: The field is used to configure cachesize of L2-Cache as 16k bytes. This field and all other fields within this register is onehot. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: L2_CACHE_CACHESIZE_32K + description: The field is used to configure cachesize of L2-Cache as 32k bytes. This field and all other fields within this register is onehot. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: L2_CACHE_CACHESIZE_64K + description: The field is used to configure cachesize of L2-Cache as 64k bytes. This field and all other fields within this register is onehot. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: L2_CACHE_CACHESIZE_128K + description: The field is used to configure cachesize of L2-Cache as 128k bytes. This field and all other fields within this register is onehot. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: L2_CACHE_CACHESIZE_256K + description: The field is used to configure cachesize of L2-Cache as 256k bytes. This field and all other fields within this register is onehot. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: L2_CACHE_CACHESIZE_512K + description: The field is used to configure cachesize of L2-Cache as 512k bytes. This field and all other fields within this register is onehot. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: L2_CACHE_CACHESIZE_1024K + description: The field is used to configure cachesize of L2-Cache as 1024k bytes. This field and all other fields within this register is onehot. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: L2_CACHE_CACHESIZE_2048K + description: The field is used to configure cachesize of L2-Cache as 2048k bytes. This field and all other fields within this register is onehot. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: L2_CACHE_CACHESIZE_4096K + description: The field is used to configure cachesize of L2-Cache as 4096k bytes. This field and all other fields within this register is onehot. + bitOffset: 12 + bitWidth: 1 + access: read-only + - register: + name: L2_CACHE_BLOCKSIZE_CONF + description: L2 Cache BlockSize mode configure register + addressOffset: 616 + size: 32 + fields: + - name: L2_CACHE_BLOCKSIZE_8 + description: The field is used to configureblocksize of L2-Cache as 8 bytes. This field and all other fields within this register is onehot. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L2_CACHE_BLOCKSIZE_16 + description: The field is used to configureblocksize of L2-Cache as 16 bytes. This field and all other fields within this register is onehot. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L2_CACHE_BLOCKSIZE_32 + description: The field is used to configureblocksize of L2-Cache as 32 bytes. This field and all other fields within this register is onehot. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L2_CACHE_BLOCKSIZE_64 + description: The field is used to configureblocksize of L2-Cache as 64 bytes. This field and all other fields within this register is onehot. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L2_CACHE_BLOCKSIZE_128 + description: The field is used to configureblocksize of L2-Cache as 128 bytes. This field and all other fields within this register is onehot. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: L2_CACHE_BLOCKSIZE_256 + description: The field is used to configureblocksize of L2-Cache as 256 bytes. This field and all other fields within this register is onehot. + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: L2_CACHE_WRAP_AROUND_CTRL + description: Cache wrap around control register + addressOffset: 620 + size: 32 + fields: + - name: L2_CACHE_WRAP + description: Set this bit as 1 to enable L2-Cache wrap around mode. + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: L2_CACHE_TAG_MEM_POWER_CTRL + description: Cache tag memory power control register + addressOffset: 624 + size: 32 + fields: + - name: L2_CACHE_TAG_MEM_FORCE_ON + description: "The bit is used to close clock gating of L2-Cache tag memory. 1: close gating, 0: open clock gating." + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: L2_CACHE_TAG_MEM_FORCE_PD + description: "The bit is used to power L2-Cache tag memory down. 0: follow rtc_lslp, 1: power down" + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: L2_CACHE_TAG_MEM_FORCE_PU + description: "The bit is used to power L2-Cache tag memory up. 0: follow rtc_lslp, 1: power up" + bitOffset: 22 + bitWidth: 1 + access: read-only + - register: + name: L2_CACHE_DATA_MEM_POWER_CTRL + description: Cache data memory power control register + addressOffset: 628 + size: 32 + fields: + - name: L2_CACHE_DATA_MEM_FORCE_ON + description: "The bit is used to close clock gating of L2-Cache data memory. 1: close gating, 0: open clock gating." + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: L2_CACHE_DATA_MEM_FORCE_PD + description: "The bit is used to power L2-Cache data memory down. 0: follow rtc_lslp, 1: power down" + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: L2_CACHE_DATA_MEM_FORCE_PU + description: "The bit is used to power L2-Cache data memory up. 0: follow rtc_lslp, 1: power up" + bitOffset: 22 + bitWidth: 1 + access: read-only + - register: + name: L2_CACHE_FREEZE_CTRL + description: Cache Freeze control register + addressOffset: 632 + size: 32 + fields: + - name: L2_CACHE_FREEZE_EN + description: The bit is used to enable freeze operation on L2-Cache. It can be cleared by software. + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: L2_CACHE_FREEZE_MODE + description: "The bit is used to configure mode of freeze operation L2-Cache. 0: a miss-access will not stuck. 1: a miss-access will stuck." + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: L2_CACHE_FREEZE_DONE + description: "The bit is used to indicate whether freeze operation on L2-Cache is finished or not. 0: not finished. 1: finished." + bitOffset: 22 + bitWidth: 1 + access: read-only + - register: + name: L2_CACHE_DATA_MEM_ACS_CONF + description: Cache data memory access configure register + addressOffset: 636 + size: 32 + fields: + - name: L2_CACHE_DATA_MEM_RD_EN + description: "The bit is used to enable config-bus read L2-Cache data memoryory. 0: disable, 1: enable." + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: L2_CACHE_DATA_MEM_WR_EN + description: "The bit is used to enable config-bus write L2-Cache data memoryory. 0: disable, 1: enable." + bitOffset: 21 + bitWidth: 1 + access: read-only + - register: + name: L2_CACHE_TAG_MEM_ACS_CONF + description: Cache tag memory access configure register + addressOffset: 640 + size: 32 + fields: + - name: L2_CACHE_TAG_MEM_RD_EN + description: "The bit is used to enable config-bus read L2-Cache tag memoryory. 0: disable, 1: enable." + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: L2_CACHE_TAG_MEM_WR_EN + description: "The bit is used to enable config-bus write L2-Cache tag memoryory. 0: disable, 1: enable." + bitOffset: 21 + bitWidth: 1 + access: read-only + - register: + name: L2_CACHE_PRELOCK_CONF + description: L2 Cache prelock configure register + addressOffset: 644 + size: 32 + fields: + - name: L2_CACHE_PRELOCK_SCT0_EN + description: The bit is used to enable the first section of prelock function on L2-Cache. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L2_CACHE_PRELOCK_SCT1_EN + description: The bit is used to enable the second section of prelock function on L2-Cache. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L2_CACHE_PRELOCK_RGID + description: The bit is used to set the gid of l2 cache prelock. + bitOffset: 2 + bitWidth: 4 + access: read-only + - register: + name: L2_CACHE_PRELOCK_SCT0_ADDR + description: L2 Cache prelock section0 address configure register + addressOffset: 648 + size: 32 + fields: + - name: L2_CACHE_PRELOCK_SCT0_ADDR + description: "Those bits are used to configure the start virtual address of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_CACHE_PRELOCK_SCT1_ADDR + description: L2 Cache prelock section1 address configure register + addressOffset: 652 + size: 32 + fields: + - name: L2_CACHE_PRELOCK_SCT1_ADDR + description: "Those bits are used to configure the start virtual address of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_CACHE_PRELOCK_SCT_SIZE + description: L2 Cache prelock section size configure register + addressOffset: 656 + size: 32 + resetValue: 4294967295 + fields: + - name: L2_CACHE_PRELOCK_SCT0_SIZE + description: "Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT0_ADDR_REG" + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: L2_CACHE_PRELOCK_SCT1_SIZE + description: "Those bits are used to configure the size of the second section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOCK_SCT1_ADDR_REG" + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: L2_CACHE_PRELOAD_CTRL + description: L2 Cache preload-operation control register + addressOffset: 660 + size: 32 + resetValue: 2 + fields: + - name: L2_CACHE_PRELOAD_ENA + description: The bit is used to enable preload operation on L2-Cache. It will be cleared by hardware automatically after preload operation is done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: L2_CACHE_PRELOAD_DONE + description: "The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L2_CACHE_PRELOAD_ORDER + description: "The bit is used to configure the direction of preload operation. 0: ascending, 1: descending." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L2_CACHE_PRELOAD_RGID + description: The bit is used to set the gid of l2 cache preload. + bitOffset: 3 + bitWidth: 4 + access: read-only + - register: + name: L2_CACHE_PRELOAD_ADDR + description: L2 Cache preload address configure register + addressOffset: 664 + size: 32 + fields: + - name: L2_CACHE_PRELOAD_ADDR + description: "Those bits are used to configure the start virtual address of preload on L2-Cache, which should be used together with L2_CACHE_PRELOAD_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_CACHE_PRELOAD_SIZE + description: L2 Cache preload size configure register + addressOffset: 668 + size: 32 + fields: + - name: L2_CACHE_PRELOAD_SIZE + description: "Those bits are used to configure the size of the first section of prelock on L2-Cache, which should be used together with L2_CACHE_PRELOAD_ADDR_REG" + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: L2_CACHE_AUTOLOAD_CTRL + description: L2 Cache autoload-operation control register + addressOffset: 672 + size: 32 + resetValue: 2 + fields: + - name: L2_CACHE_AUTOLOAD_ENA + description: "The bit is used to enable and disable autoload operation on L2-Cache. 1: enable, 0: disable." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L2_CACHE_AUTOLOAD_DONE + description: "The bit is used to indicate whether autoload operation on L2-Cache is finished or not. 0: not finished. 1: finished." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L2_CACHE_AUTOLOAD_ORDER + description: "The bit is used to configure the direction of autoload operation on L2-Cache. 0: ascending. 1: descending." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L2_CACHE_AUTOLOAD_TRIGGER_MODE + description: "The field is used to configure trigger mode of autoload operation on L2-Cache. 0/3: miss-trigger, 1: hit-trigger, 2: miss-hit-trigger." + bitOffset: 3 + bitWidth: 2 + access: read-only + - name: L2_CACHE_AUTOLOAD_SCT0_ENA + description: The bit is used to enable the first section for autoload operation on L2-Cache. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: L2_CACHE_AUTOLOAD_SCT1_ENA + description: The bit is used to enable the second section for autoload operation on L2-Cache. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: L2_CACHE_AUTOLOAD_SCT2_ENA + description: The bit is used to enable the third section for autoload operation on L2-Cache. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: L2_CACHE_AUTOLOAD_SCT3_ENA + description: The bit is used to enable the fourth section for autoload operation on L2-Cache. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: L2_CACHE_AUTOLOAD_RGID + description: The bit is used to set the gid of l2 cache autoload. + bitOffset: 12 + bitWidth: 4 + access: read-only + - register: + name: L2_CACHE_AUTOLOAD_SCT0_ADDR + description: L2 Cache autoload section 0 address configure register + addressOffset: 676 + size: 32 + fields: + - name: L2_CACHE_AUTOLOAD_SCT0_ADDR + description: Those bits are used to configure the start virtual address of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_SIZE and L2_CACHE_AUTOLOAD_SCT0_ENA. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_CACHE_AUTOLOAD_SCT0_SIZE + description: L2 Cache autoload section 0 size configure register + addressOffset: 680 + size: 32 + fields: + - name: L2_CACHE_AUTOLOAD_SCT0_SIZE + description: Those bits are used to configure the size of the first section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT0_ADDR and L2_CACHE_AUTOLOAD_SCT0_ENA. + bitOffset: 0 + bitWidth: 28 + access: read-only + - register: + name: L2_CACHE_AUTOLOAD_SCT1_ADDR + description: L2 Cache autoload section 1 address configure register + addressOffset: 684 + size: 32 + fields: + - name: L2_CACHE_AUTOLOAD_SCT1_ADDR + description: Those bits are used to configure the start virtual address of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_SIZE and L2_CACHE_AUTOLOAD_SCT1_ENA. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_CACHE_AUTOLOAD_SCT1_SIZE + description: L2 Cache autoload section 1 size configure register + addressOffset: 688 + size: 32 + fields: + - name: L2_CACHE_AUTOLOAD_SCT1_SIZE + description: Those bits are used to configure the size of the second section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT1_ADDR and L2_CACHE_AUTOLOAD_SCT1_ENA. + bitOffset: 0 + bitWidth: 28 + access: read-only + - register: + name: L2_CACHE_AUTOLOAD_SCT2_ADDR + description: L2 Cache autoload section 2 address configure register + addressOffset: 692 + size: 32 + fields: + - name: L2_CACHE_AUTOLOAD_SCT2_ADDR + description: Those bits are used to configure the start virtual address of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_SIZE and L2_CACHE_AUTOLOAD_SCT2_ENA. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_CACHE_AUTOLOAD_SCT2_SIZE + description: L2 Cache autoload section 2 size configure register + addressOffset: 696 + size: 32 + fields: + - name: L2_CACHE_AUTOLOAD_SCT2_SIZE + description: Those bits are used to configure the size of the third section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT2_ADDR and L2_CACHE_AUTOLOAD_SCT2_ENA. + bitOffset: 0 + bitWidth: 28 + access: read-only + - register: + name: L2_CACHE_AUTOLOAD_SCT3_ADDR + description: L2 Cache autoload section 3 address configure register + addressOffset: 700 + size: 32 + fields: + - name: L2_CACHE_AUTOLOAD_SCT3_ADDR + description: Those bits are used to configure the start virtual address of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_SIZE and L2_CACHE_AUTOLOAD_SCT3_ENA. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_CACHE_AUTOLOAD_SCT3_SIZE + description: L2 Cache autoload section 3 size configure register + addressOffset: 704 + size: 32 + fields: + - name: L2_CACHE_AUTOLOAD_SCT3_SIZE + description: Those bits are used to configure the size of the fourth section for autoload operation on L2-Cache. Note that it should be used together with L2_CACHE_AUTOLOAD_SCT3_ADDR and L2_CACHE_AUTOLOAD_SCT3_ENA. + bitOffset: 0 + bitWidth: 28 + access: read-only + - register: + name: L2_CACHE_ACS_CNT_INT_ENA + description: Cache Access Counter Interrupt enable register + addressOffset: 708 + size: 32 + fields: + - name: L2_IBUS0_OVF_INT_ENA + description: The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: L2_IBUS1_OVF_INT_ENA + description: The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: L2_IBUS2_OVF_INT_ENA + description: Reserved + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: L2_IBUS3_OVF_INT_ENA + description: Reserved + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: L2_DBUS0_OVF_INT_ENA + description: The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: L2_DBUS1_OVF_INT_ENA + description: The bit is used to enable interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: L2_DBUS2_OVF_INT_ENA + description: Reserved + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: L2_DBUS3_OVF_INT_ENA + description: Reserved + bitOffset: 15 + bitWidth: 1 + access: read-only + - register: + name: L2_CACHE_ACS_CNT_INT_CLR + description: Cache Access Counter Interrupt clear register + addressOffset: 712 + size: 32 + fields: + - name: L2_IBUS0_OVF_INT_CLR + description: The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: L2_IBUS1_OVF_INT_CLR + description: The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: L2_IBUS2_OVF_INT_CLR + description: Reserved + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: L2_IBUS3_OVF_INT_CLR + description: Reserved + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: L2_DBUS0_OVF_INT_CLR + description: The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus0 accesses L2-Cache. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: L2_DBUS1_OVF_INT_CLR + description: The bit is used to clear counters overflow interrupt and counters in L2-Cache due to bus1 accesses L2-Cache. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: L2_DBUS2_OVF_INT_CLR + description: Reserved + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: L2_DBUS3_OVF_INT_CLR + description: Reserved + bitOffset: 15 + bitWidth: 1 + access: read-only + - register: + name: L2_CACHE_ACS_CNT_INT_RAW + description: Cache Access Counter Interrupt raw register + addressOffset: 716 + size: 32 + fields: + - name: L2_IBUS0_OVF_INT_RAW + description: The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-ICache0. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: L2_IBUS1_OVF_INT_RAW + description: The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-ICache1. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: L2_IBUS2_OVF_INT_RAW + description: The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-ICache2. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: L2_IBUS3_OVF_INT_RAW + description: The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-ICache3. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: L2_DBUS0_OVF_INT_RAW + description: The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-DCache. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: L2_DBUS1_OVF_INT_RAW + description: The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-DCache. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: L2_DBUS2_OVF_INT_RAW + description: The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus2 accesses L2-DCache. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: L2_DBUS3_OVF_INT_RAW + description: The raw bit of the interrupt of one of counters overflow that occurs in L2-Cache due to bus3 accesses L2-DCache. + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: L2_CACHE_ACS_CNT_INT_ST + description: Cache Access Counter Interrupt status register + addressOffset: 720 + size: 32 + fields: + - name: L2_IBUS0_OVF_INT_ST + description: The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: L2_IBUS1_OVF_INT_ST + description: The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: L2_IBUS2_OVF_INT_ST + description: Reserved + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: L2_IBUS3_OVF_INT_ST + description: Reserved + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: L2_DBUS0_OVF_INT_ST + description: The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus0 accesses L2-Cache. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: L2_DBUS1_OVF_INT_ST + description: The bit indicates the interrupt status of one of counters overflow that occurs in L2-Cache due to bus1 accesses L2-Cache. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: L2_DBUS2_OVF_INT_ST + description: Reserved + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: L2_DBUS3_OVF_INT_ST + description: Reserved + bitOffset: 15 + bitWidth: 1 + access: read-only + - register: + name: L2_CACHE_ACS_FAIL_INT_ENA + description: Cache Access Fail Interrupt enable register + addressOffset: 724 + size: 32 + fields: + - name: L2_CACHE_FAIL_INT_ENA + description: The bit is used to enable interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: L2_CACHE_ACS_FAIL_INT_CLR + description: L1-Cache Access Fail Interrupt clear register + addressOffset: 728 + size: 32 + fields: + - name: L2_CACHE_FAIL_INT_CLR + description: The bit is used to clear interrupt of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: L2_CACHE_ACS_FAIL_INT_RAW + description: Cache Access Fail Interrupt raw register + addressOffset: 732 + size: 32 + fields: + - name: L2_CACHE_FAIL_INT_RAW + description: The raw bit of the interrupt of access fail that occurs in L2-Cache. + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: L2_CACHE_ACS_FAIL_INT_ST + description: Cache Access Fail Interrupt status register + addressOffset: 736 + size: 32 + fields: + - name: L2_CACHE_FAIL_INT_ST + description: The bit indicates the interrupt status of access fail that occurs in L2-Cache due to l1 cache accesses L2-Cache. + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: L2_CACHE_ACS_CNT_CTRL + description: Cache Access Counter enable and clear register + addressOffset: 740 + size: 32 + fields: + - name: L2_IBUS0_CNT_ENA + description: The bit is used to enable ibus0 counter in L2-Cache. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: L2_IBUS1_CNT_ENA + description: The bit is used to enable ibus1 counter in L2-Cache. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: L2_IBUS2_CNT_ENA + description: Reserved + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: L2_IBUS3_CNT_ENA + description: Reserved + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: L2_DBUS0_CNT_ENA + description: The bit is used to enable dbus0 counter in L2-Cache. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: L2_DBUS1_CNT_ENA + description: The bit is used to enable dbus1 counter in L2-Cache. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: L2_DBUS2_CNT_ENA + description: Reserved + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: L2_DBUS3_CNT_ENA + description: Reserved + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: L2_IBUS0_CNT_CLR + description: The bit is used to clear ibus0 counter in L2-Cache. + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: L2_IBUS1_CNT_CLR + description: The bit is used to clear ibus1 counter in L2-Cache. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: L2_IBUS2_CNT_CLR + description: Reserved + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: L2_IBUS3_CNT_CLR + description: Reserved + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: L2_DBUS0_CNT_CLR + description: The bit is used to clear dbus0 counter in L2-Cache. + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: L2_DBUS1_CNT_CLR + description: The bit is used to clear dbus1 counter in L2-Cache. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: L2_DBUS2_CNT_CLR + description: Reserved + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: L2_DBUS3_CNT_CLR + description: Reserved + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: L2_IBUS0_ACS_HIT_CNT + description: L2-Cache bus0 Hit-Access Counter register + addressOffset: 744 + size: 32 + fields: + - name: L2_IBUS0_HIT_CNT + description: The register records the number of hits when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_IBUS0_ACS_MISS_CNT + description: L2-Cache bus0 Miss-Access Counter register + addressOffset: 748 + size: 32 + fields: + - name: L2_IBUS0_MISS_CNT + description: The register records the number of missing when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_IBUS0_ACS_CONFLICT_CNT + description: L2-Cache bus0 Conflict-Access Counter register + addressOffset: 752 + size: 32 + fields: + - name: L2_IBUS0_CONFLICT_CNT + description: The register records the number of access-conflicts when L1-ICache0 accesses L2-Cache due to bus0 accessing L1-ICache0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_IBUS0_ACS_NXTLVL_CNT + description: L2-Cache bus0 Next-Level-Access Counter register + addressOffset: 756 + size: 32 + fields: + - name: L2_IBUS0_NXTLVL_CNT + description: The register records the number of times that L2-Cache accesses external memory due to L1-ICache0 accessing L2-Cache due to bus0 accessing L1-ICache0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_IBUS1_ACS_HIT_CNT + description: L2-Cache bus1 Hit-Access Counter register + addressOffset: 760 + size: 32 + fields: + - name: L2_IBUS1_HIT_CNT + description: The register records the number of hits when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_IBUS1_ACS_MISS_CNT + description: L2-Cache bus1 Miss-Access Counter register + addressOffset: 764 + size: 32 + fields: + - name: L2_IBUS1_MISS_CNT + description: The register records the number of missing when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_IBUS1_ACS_CONFLICT_CNT + description: L2-Cache bus1 Conflict-Access Counter register + addressOffset: 768 + size: 32 + fields: + - name: L2_IBUS1_CONFLICT_CNT + description: The register records the number of access-conflicts when L1-ICache1 accesses L2-Cache due to bus1 accessing L1-ICache1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_IBUS1_ACS_NXTLVL_CNT + description: L2-Cache bus1 Next-Level-Access Counter register + addressOffset: 772 + size: 32 + fields: + - name: L2_IBUS1_NXTLVL_CNT + description: The register records the number of times that L2-Cache accesses external memory due to L1-ICache1 accessing L2-Cache due to bus1 accessing L1-ICache1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_IBUS2_ACS_HIT_CNT + description: L2-Cache bus2 Hit-Access Counter register + addressOffset: 776 + size: 32 + fields: + - name: L2_IBUS2_HIT_CNT + description: The register records the number of hits when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_IBUS2_ACS_MISS_CNT + description: L2-Cache bus2 Miss-Access Counter register + addressOffset: 780 + size: 32 + fields: + - name: L2_IBUS2_MISS_CNT + description: The register records the number of missing when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_IBUS2_ACS_CONFLICT_CNT + description: L2-Cache bus2 Conflict-Access Counter register + addressOffset: 784 + size: 32 + fields: + - name: L2_IBUS2_CONFLICT_CNT + description: The register records the number of access-conflicts when L1-ICache2 accesses L2-Cache due to bus2 accessing L1-ICache2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_IBUS2_ACS_NXTLVL_CNT + description: L2-Cache bus2 Next-Level-Access Counter register + addressOffset: 788 + size: 32 + fields: + - name: L2_IBUS2_NXTLVL_CNT + description: The register records the number of times that L2-Cache accesses external memory due to L1-ICache2 accessing L2-Cache due to bus2 accessing L1-ICache2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_IBUS3_ACS_HIT_CNT + description: L2-Cache bus3 Hit-Access Counter register + addressOffset: 792 + size: 32 + fields: + - name: L2_IBUS3_HIT_CNT + description: The register records the number of hits when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_IBUS3_ACS_MISS_CNT + description: L2-Cache bus3 Miss-Access Counter register + addressOffset: 796 + size: 32 + fields: + - name: L2_IBUS3_MISS_CNT + description: The register records the number of missing when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_IBUS3_ACS_CONFLICT_CNT + description: L2-Cache bus3 Conflict-Access Counter register + addressOffset: 800 + size: 32 + fields: + - name: L2_IBUS3_CONFLICT_CNT + description: The register records the number of access-conflicts when L1-ICache3 accesses L2-Cache due to bus3 accessing L1-ICache3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_IBUS3_ACS_NXTLVL_CNT + description: L2-Cache bus3 Next-Level-Access Counter register + addressOffset: 804 + size: 32 + fields: + - name: L2_IBUS3_NXTLVL_CNT + description: The register records the number of times that L2-Cache accesses external memory due to L1-ICache3 accessing L2-Cache due to bus3 accessing L1-ICache3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_DBUS0_ACS_HIT_CNT + description: L2-Cache bus0 Hit-Access Counter register + addressOffset: 808 + size: 32 + fields: + - name: L2_DBUS0_HIT_CNT + description: The register records the number of hits when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_DBUS0_ACS_MISS_CNT + description: L2-Cache bus0 Miss-Access Counter register + addressOffset: 812 + size: 32 + fields: + - name: L2_DBUS0_MISS_CNT + description: The register records the number of missing when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_DBUS0_ACS_CONFLICT_CNT + description: L2-Cache bus0 Conflict-Access Counter register + addressOffset: 816 + size: 32 + fields: + - name: L2_DBUS0_CONFLICT_CNT + description: The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus0 accessing L1-DCache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_DBUS0_ACS_NXTLVL_CNT + description: L2-Cache bus0 Next-Level-Access Counter register + addressOffset: 820 + size: 32 + fields: + - name: L2_DBUS0_NXTLVL_CNT + description: The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus0 accessing L1-DCache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_DBUS1_ACS_HIT_CNT + description: L2-Cache bus1 Hit-Access Counter register + addressOffset: 824 + size: 32 + fields: + - name: L2_DBUS1_HIT_CNT + description: The register records the number of hits when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_DBUS1_ACS_MISS_CNT + description: L2-Cache bus1 Miss-Access Counter register + addressOffset: 828 + size: 32 + fields: + - name: L2_DBUS1_MISS_CNT + description: The register records the number of missing when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_DBUS1_ACS_CONFLICT_CNT + description: L2-Cache bus1 Conflict-Access Counter register + addressOffset: 832 + size: 32 + fields: + - name: L2_DBUS1_CONFLICT_CNT + description: The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus1 accessing L1-DCache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_DBUS1_ACS_NXTLVL_CNT + description: L2-Cache bus1 Next-Level-Access Counter register + addressOffset: 836 + size: 32 + fields: + - name: L2_DBUS1_NXTLVL_CNT + description: The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus1 accessing L1-DCache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_DBUS2_ACS_HIT_CNT + description: L2-Cache bus2 Hit-Access Counter register + addressOffset: 840 + size: 32 + fields: + - name: L2_DBUS2_HIT_CNT + description: The register records the number of hits when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_DBUS2_ACS_MISS_CNT + description: L2-Cache bus2 Miss-Access Counter register + addressOffset: 844 + size: 32 + fields: + - name: L2_DBUS2_MISS_CNT + description: The register records the number of missing when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_DBUS2_ACS_CONFLICT_CNT + description: L2-Cache bus2 Conflict-Access Counter register + addressOffset: 848 + size: 32 + fields: + - name: L2_DBUS2_CONFLICT_CNT + description: The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus2 accessing L1-DCache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_DBUS2_ACS_NXTLVL_CNT + description: L2-Cache bus2 Next-Level-Access Counter register + addressOffset: 852 + size: 32 + fields: + - name: L2_DBUS2_NXTLVL_CNT + description: The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus2 accessing L1-DCache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_DBUS3_ACS_HIT_CNT + description: L2-Cache bus3 Hit-Access Counter register + addressOffset: 856 + size: 32 + fields: + - name: L2_DBUS3_HIT_CNT + description: The register records the number of hits when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_DBUS3_ACS_MISS_CNT + description: L2-Cache bus3 Miss-Access Counter register + addressOffset: 860 + size: 32 + fields: + - name: L2_DBUS3_MISS_CNT + description: The register records the number of missing when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_DBUS3_ACS_CONFLICT_CNT + description: L2-Cache bus3 Conflict-Access Counter register + addressOffset: 864 + size: 32 + fields: + - name: L2_DBUS3_CONFLICT_CNT + description: The register records the number of access-conflicts when L1-DCache accesses L2-Cache due to bus3 accessing L1-DCache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_DBUS3_ACS_NXTLVL_CNT + description: L2-Cache bus3 Next-Level-Access Counter register + addressOffset: 868 + size: 32 + fields: + - name: L2_DBUS3_NXTLVL_CNT + description: The register records the number of times that L2-Cache accesses external memory due to L1-DCache accessing L2-Cache due to bus3 accessing L1-DCache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_CACHE_ACS_FAIL_ID_ATTR + description: L2-Cache Access Fail ID/attribution information register + addressOffset: 872 + size: 32 + fields: + - name: L2_CACHE_FAIL_ID + description: The register records the ID of fail-access when L1-Cache accesses L2-Cache. + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: L2_CACHE_FAIL_ATTR + description: The register records the attribution of fail-access when L1-Cache accesses L2-Cache due to cache accessing L1-Cache. + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: L2_CACHE_ACS_FAIL_ADDR + description: L2-Cache Access Fail Address information register + addressOffset: 876 + size: 32 + fields: + - name: L2_CACHE_FAIL_ADDR + description: The register records the address of fail-access when L1-Cache accesses L2-Cache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_CACHE_SYNC_PRELOAD_INT_ENA + description: L1-Cache Access Fail Interrupt enable register + addressOffset: 880 + size: 32 + fields: + - name: L2_CACHE_PLD_DONE_INT_ENA + description: The bit is used to enable interrupt of L2-Cache preload-operation done. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: L2_CACHE_PLD_ERR_INT_ENA + description: The bit is used to enable interrupt of L2-Cache preload-operation error. + bitOffset: 12 + bitWidth: 1 + access: read-only + - register: + name: L2_CACHE_SYNC_PRELOAD_INT_CLR + description: Sync Preload operation Interrupt clear register + addressOffset: 884 + size: 32 + fields: + - name: L2_CACHE_PLD_DONE_INT_CLR + description: The bit is used to clear interrupt that occurs only when L2-Cache preload-operation is done. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: L2_CACHE_PLD_ERR_INT_CLR + description: The bit is used to clear interrupt of L2-Cache preload-operation error. + bitOffset: 12 + bitWidth: 1 + access: read-only + - register: + name: L2_CACHE_SYNC_PRELOAD_INT_RAW + description: Sync Preload operation Interrupt raw register + addressOffset: 888 + size: 32 + fields: + - name: L2_CACHE_PLD_DONE_INT_RAW + description: The raw bit of the interrupt that occurs only when L2-Cache preload-operation is done. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: L2_CACHE_PLD_ERR_INT_RAW + description: The raw bit of the interrupt that occurs only when L2-Cache preload-operation error occurs. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: L2_CACHE_SYNC_PRELOAD_INT_ST + description: L1-Cache Access Fail Interrupt status register + addressOffset: 892 + size: 32 + fields: + - name: L2_CACHE_PLD_DONE_INT_ST + description: The bit indicates the status of the interrupt that occurs only when L2-Cache preload-operation is done. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: L2_CACHE_PLD_ERR_INT_ST + description: The bit indicates the status of the interrupt of L2-Cache preload-operation error. + bitOffset: 12 + bitWidth: 1 + access: read-only + - register: + name: L2_CACHE_SYNC_PRELOAD_EXCEPTION + description: Cache Sync/Preload Operation exception register + addressOffset: 896 + size: 32 + fields: + - name: L2_CACHE_PLD_ERR_CODE + description: The value 2 is Only available which means preload size is error in L2-Cache. + bitOffset: 10 + bitWidth: 2 + access: read-only + - register: + name: L2_CACHE_SYNC_RST_CTRL + description: Cache Sync Reset control register + addressOffset: 900 + size: 32 + fields: + - name: L2_CACHE_SYNC_RST + description: set this bit to reset sync-logic inside L2-Cache. Recommend that this should only be used to initialize sync-logic when some fatal error of sync-logic occurs. + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: L2_CACHE_PRELOAD_RST_CTRL + description: Cache Preload Reset control register + addressOffset: 904 + size: 32 + fields: + - name: L2_CACHE_PLD_RST + description: set this bit to reset preload-logic inside L2-Cache. Recommend that this should only be used to initialize preload-logic when some fatal error of preload-logic occurs. + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: L2_CACHE_AUTOLOAD_BUF_CLR_CTRL + description: Cache Autoload buffer clear control register + addressOffset: 908 + size: 32 + fields: + - name: L2_CACHE_ALD_BUF_CLR + description: "set this bit to clear autoload-buffer inside L2-Cache. If this bit is active, autoload will not work in L2-Cache. This bit should not be active when autoload works in L2-Cache." + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: L2_UNALLOCATE_BUFFER_CLEAR + description: Unallocate request buffer clear registers + addressOffset: 912 + size: 32 + fields: + - name: L2_CACHE_UNALLOC_CLR + description: The bit is used to clear the unallocate request buffer of l2 icache where the unallocate request is responsed but not completed. + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: L2_CACHE_ACCESS_ATTR_CTRL + description: L1 Cache access Attribute propagation control register + addressOffset: 916 + size: 32 + resetValue: 15 + fields: + - name: L2_CACHE_ACCESS_FORCE_CC + description: "Set this bit to force the request to l2 cache with cacheable attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of cacheable and non-cacheable." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: L2_CACHE_ACCESS_FORCE_WB + description: "Set this bit to force the request to l2 cache with write-back attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-back and write-through." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: L2_CACHE_ACCESS_FORCE_WMA + description: "Set this bit to force the request to l2 cache with write-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of write-miss-allocate and write-miss-no-allocate." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: L2_CACHE_ACCESS_FORCE_RMA + description: "Set this bit to force the request to l2 cache with read-miss-allocate attribute, otherwise, the attribute is propagated from L1 cache or CPU, it could be one of read-miss-allocate and read-miss-no-allocate." + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: L2_CACHE_OBJECT_CTRL + description: Cache Tag and Data memory Object control register + addressOffset: 920 + size: 32 + fields: + - name: L2_CACHE_TAG_OBJECT + description: Set this bit to set L2-Cache tag memory as object. This bit should be onehot with the others fields inside this register. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: L2_CACHE_MEM_OBJECT + description: Set this bit to set L2-Cache data memory as object. This bit should be onehot with the others fields inside this register. + bitOffset: 11 + bitWidth: 1 + access: read-only + - register: + name: L2_CACHE_WAY_OBJECT + description: Cache Tag and Data memory way register + addressOffset: 924 + size: 32 + fields: + - name: L2_CACHE_WAY_OBJECT + description: "Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, ?, 7: way7." + bitOffset: 0 + bitWidth: 3 + access: read-only + - register: + name: L2_CACHE_VADDR + description: Cache Vaddr register + addressOffset: 928 + size: 32 + resetValue: 1073741824 + fields: + - name: L2_CACHE_VADDR + description: Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_CACHE_DEBUG_BUS + description: Cache Tag/data memory content register + addressOffset: 932 + size: 32 + resetValue: 932 + fields: + - name: L2_CACHE_DEBUG_BUS + description: This is a constant place where we can write data to or read data from the tag/data memory on the specified cache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: LEVEL_SPLIT1 + description: USED TO SPLIT L1 CACHE AND L2 CACHE + addressOffset: 936 + size: 32 + resetValue: 936 + fields: + - name: LEVEL_SPLIT1 + description: Reserved + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CLOCK_GATE + description: Clock gate control register + addressOffset: 940 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: The bit is used to enable clock gate when access all registers in this module. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: REDUNDANCY_SIG0 + description: Cache redundancy signal 0 register + addressOffset: 944 + size: 32 + fields: + - name: CACHE_REDCY_SIG0 + description: Those bits are prepared for ECO. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REDUNDANCY_SIG1 + description: Cache redundancy signal 1 register + addressOffset: 948 + size: 32 + fields: + - name: CACHE_REDCY_SIG1 + description: Those bits are prepared for ECO. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REDUNDANCY_SIG2 + description: Cache redundancy signal 2 register + addressOffset: 952 + size: 32 + fields: + - name: CACHE_REDCY_SIG2 + description: Those bits are prepared for ECO. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REDUNDANCY_SIG3 + description: Cache redundancy signal 3 register + addressOffset: 956 + size: 32 + fields: + - name: CACHE_REDCY_SIG3 + description: Those bits are prepared for ECO. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REDUNDANCY_SIG4 + description: Cache redundancy signal 0 register + addressOffset: 960 + size: 32 + fields: + - name: CACHE_REDCY_SIG4 + description: Those bits are prepared for ECO. + bitOffset: 0 + bitWidth: 4 + access: read-only + - register: + name: DATE + description: Version control register + addressOffset: 1020 + size: 32 + resetValue: 35659904 + fields: + - name: DATE + description: version control register. Note that this default value stored is the latest date when the hardware logic was updated. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: GPIO + description: General Purpose Input/Output + groupName: GPIO + baseAddress: 1611206656 + addressBlock: + - offset: 0 + size: 924 + usage: registers + interrupt: + - name: GPIO + value: 30 + - name: GPIO_NMI + value: 31 + registers: + - register: + name: BT_SELECT + description: GPIO bit select register + addressOffset: 0 + size: 32 + fields: + - name: BT_SEL + description: GPIO bit select register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: OUT + description: GPIO output register for GPIO0-31 + addressOffset: 4 + size: 32 + fields: + - name: DATA_ORIG + description: GPIO output register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: OUT_W1TS + description: GPIO output set register for GPIO0-31 + addressOffset: 8 + size: 32 + fields: + - name: OUT_W1TS + description: GPIO output set register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: OUT_W1TC + description: GPIO output clear register for GPIO0-31 + addressOffset: 12 + size: 32 + fields: + - name: OUT_W1TC + description: GPIO output clear register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: OUT1 + description: GPIO output register for GPIO32-34 + addressOffset: 16 + size: 32 + fields: + - name: DATA_ORIG + description: GPIO output register for GPIO32-34 + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: OUT1_W1TS + description: GPIO output set register for GPIO32-34 + addressOffset: 20 + size: 32 + fields: + - name: OUT1_W1TS + description: GPIO output set register for GPIO32-34 + bitOffset: 0 + bitWidth: 3 + access: write-only + - register: + name: OUT1_W1TC + description: GPIO output clear register for GPIO32-34 + addressOffset: 24 + size: 32 + fields: + - name: OUT1_W1TC + description: GPIO output clear register for GPIO32-34 + bitOffset: 0 + bitWidth: 3 + access: write-only + - register: + name: SDIO_SELECT + description: GPIO sdio select register + addressOffset: 28 + size: 32 + fields: + - name: SDIO_SEL + description: GPIO sdio select register + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: ENABLE + description: GPIO output enable register for GPIO0-31 + addressOffset: 32 + size: 32 + fields: + - name: DATA + description: GPIO output enable register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ENABLE_W1TS + description: GPIO output enable set register for GPIO0-31 + addressOffset: 36 + size: 32 + fields: + - name: ENABLE_W1TS + description: GPIO output enable set register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: ENABLE_W1TC + description: GPIO output enable clear register for GPIO0-31 + addressOffset: 40 + size: 32 + fields: + - name: ENABLE_W1TC + description: GPIO output enable clear register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: ENABLE1 + description: GPIO output enable register for GPIO32-34 + addressOffset: 44 + size: 32 + fields: + - name: DATA + description: GPIO output enable register for GPIO32-34 + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: ENABLE1_W1TS + description: GPIO output enable set register for GPIO32-34 + addressOffset: 48 + size: 32 + fields: + - name: ENABLE1_W1TS + description: GPIO output enable set register for GPIO32-34 + bitOffset: 0 + bitWidth: 3 + access: write-only + - register: + name: ENABLE1_W1TC + description: GPIO output enable clear register for GPIO32-34 + addressOffset: 52 + size: 32 + fields: + - name: ENABLE1_W1TC + description: GPIO output enable clear register for GPIO32-34 + bitOffset: 0 + bitWidth: 3 + access: write-only + - register: + name: STRAP + description: pad strapping register + addressOffset: 56 + size: 32 + fields: + - name: STRAPPING + description: pad strapping register + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: IN + description: GPIO input register for GPIO0-31 + addressOffset: 60 + size: 32 + fields: + - name: DATA_NEXT + description: GPIO input register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN1 + description: GPIO input register for GPIO32-34 + addressOffset: 64 + size: 32 + fields: + - name: DATA_NEXT + description: GPIO input register for GPIO32-34 + bitOffset: 0 + bitWidth: 3 + access: read-only + - register: + name: STATUS + description: GPIO interrupt status register for GPIO0-31 + addressOffset: 68 + size: 32 + fields: + - name: INTERRUPT + description: GPIO interrupt status register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STATUS_W1TS + description: GPIO interrupt status set register for GPIO0-31 + addressOffset: 72 + size: 32 + fields: + - name: STATUS_W1TS + description: GPIO interrupt status set register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: STATUS_W1TC + description: GPIO interrupt status clear register for GPIO0-31 + addressOffset: 76 + size: 32 + fields: + - name: STATUS_W1TC + description: GPIO interrupt status clear register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: STATUS1 + description: GPIO interrupt status register for GPIO32-34 + addressOffset: 80 + size: 32 + fields: + - name: INTERRUPT + description: GPIO interrupt status register for GPIO32-34 + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: STATUS1_W1TS + description: GPIO interrupt status set register for GPIO32-34 + addressOffset: 84 + size: 32 + fields: + - name: STATUS1_W1TS + description: GPIO interrupt status set register for GPIO32-34 + bitOffset: 0 + bitWidth: 3 + access: write-only + - register: + name: STATUS1_W1TC + description: GPIO interrupt status clear register for GPIO32-34 + addressOffset: 88 + size: 32 + fields: + - name: STATUS1_W1TC + description: GPIO interrupt status clear register for GPIO32-34 + bitOffset: 0 + bitWidth: 3 + access: write-only + - register: + name: PCPU_INT + description: GPIO PRO_CPU interrupt status register for GPIO0-31 + addressOffset: 92 + size: 32 + fields: + - name: PROCPU_INT + description: GPIO PRO_CPU interrupt status register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PCPU_NMI_INT + description: GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + addressOffset: 96 + size: 32 + fields: + - name: PROCPU_NMI_INT + description: GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CPUSDIO_INT + description: GPIO CPUSDIO interrupt status register for GPIO0-31 + addressOffset: 100 + size: 32 + fields: + - name: SDIO_INT + description: GPIO CPUSDIO interrupt status register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PCPU_INT1 + description: GPIO PRO_CPU interrupt status register for GPIO32-34 + addressOffset: 104 + size: 32 + fields: + - name: PROCPU_INT1 + description: GPIO PRO_CPU interrupt status register for GPIO32-34 + bitOffset: 0 + bitWidth: 3 + access: read-only + - register: + name: PCPU_NMI_INT1 + description: GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-34 + addressOffset: 108 + size: 32 + fields: + - name: PROCPU_NMI_INT1 + description: GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-34 + bitOffset: 0 + bitWidth: 3 + access: read-only + - register: + name: CPUSDIO_INT1 + description: GPIO CPUSDIO interrupt status register for GPIO32-34 + addressOffset: 112 + size: 32 + fields: + - name: SDIO_INT1 + description: GPIO CPUSDIO interrupt status register for GPIO32-34 + bitOffset: 0 + bitWidth: 3 + access: read-only + - register: + dim: 35 + dimIncrement: 4 + name: PIN%s + description: GPIO pin configuration register + addressOffset: 116 + size: 32 + fields: + - name: SYNC2_BYPASS + description: "set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: PAD_DRIVER + description: "set this bit to select pad driver. 1:open-drain. 0:normal." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SYNC1_BYPASS + description: "set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge." + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: INT_TYPE + description: "set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CONFIG + description: reserved + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: INT_ENA + description: set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. + bitOffset: 13 + bitWidth: 5 + access: read-write + - register: + name: STATUS_NEXT + description: GPIO interrupt source register for GPIO0-31 + addressOffset: 332 + size: 32 + fields: + - name: STATUS_INTERRUPT_NEXT + description: GPIO interrupt source register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: STATUS_NEXT1 + description: GPIO interrupt source register for GPIO32-34 + addressOffset: 336 + size: 32 + fields: + - name: STATUS_INTERRUPT_NEXT1 + description: GPIO interrupt source register for GPIO32-34 + bitOffset: 0 + bitWidth: 3 + access: read-only + - register: + dim: 128 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" + name: FUNC%s_IN_SEL_CFG + description: GPIO input function configuration register + addressOffset: 340 + size: 32 + resetValue: 60 + fields: + - name: IN_SEL + description: "set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level." + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: IN_INV_SEL + description: "set this bit to invert input signal. 1:invert. 0:not invert." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SEL + description: "set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO." + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + dim: 30 + dimIncrement: 4 + name: FUNC%s_OUT_SEL_CFG + description: GPIO output function select register + addressOffset: 1364 + size: 32 + resetValue: 128 + fields: + - name: OUT_SEL + description: "The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals GPIO_OUT_REG[n]." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: INV_SEL + description: "set this bit to invert output signal.1:invert.0:not invert." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: OEN_SEL + description: "set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OEN_INV_SEL + description: "set this bit to invert output enable signal.1:invert.0:not invert." + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: CLOCK_GATE + description: GPIO clock gate register + addressOffset: 1580 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: set this bit to enable GPIO clock gate + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: GPIO version register + addressOffset: 1788 + size: 32 + resetValue: 35655968 + fields: + - name: DATE + description: version register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: GPIO_SD + description: Sigma-Delta Modulation + groupName: GPIOSD + baseAddress: 1611210496 + addressBlock: + - offset: 0 + size: 124 + usage: registers + registers: + - register: + dim: 4 + dimIncrement: 4 + name: SIGMADELTA%s + description: Duty Cycle Configure Register of SDM%s + addressOffset: 0 + size: 32 + resetValue: 65280 + fields: + - name: SD0_IN + description: This field is used to configure the duty cycle of sigma delta modulation output. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SD0_PRESCALE + description: This field is used to set a divider value to divide APB clock. + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: CLOCK_GATE + description: Clock Gating Configure Register + addressOffset: 32 + size: 32 + fields: + - name: CLK_EN + description: Clock enable bit of configuration registers for sigma delta modulation. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SIGMADELTA_MISC + description: MISC Register + addressOffset: 36 + size: 32 + fields: + - name: FUNCTION_CLK_EN + description: Clock enable bit of sigma delta modulation. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI_SWAP + description: Reserved. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + name: GLITCH_FILTER_CH%s + description: Glitch Filter Configure Register of Channel%s + addressOffset: 48 + size: 32 + fields: + - name: FILTER_CH0_EN + description: Glitch Filter channel enable bit. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FILTER_CH0_INPUT_IO_NUM + description: Glitch Filter input io number. + bitOffset: 1 + bitWidth: 6 + access: read-write + - name: FILTER_CH0_WINDOW_THRES + description: Glitch Filter window threshold. + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: FILTER_CH0_WINDOW_WIDTH + description: Glitch Filter window width. + bitOffset: 13 + bitWidth: 6 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + name: ETM_EVENT_CH%s_CFG + description: Etm Config register of Channel%s + addressOffset: 96 + size: 32 + fields: + - name: ETM_CH0_EVENT_SEL + description: Etm event channel select gpio. + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: ETM_CH0_EVENT_EN + description: Etm event send enable bit. + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: ETM_TASK_P0_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 160 + size: 32 + fields: + - name: ETM_TASK_GPIO0_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO0_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO1_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO1_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO2_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO2_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO3_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO3_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P1_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 164 + size: 32 + fields: + - name: ETM_TASK_GPIO4_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO4_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO5_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO5_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO6_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO6_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO7_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO7_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P2_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 168 + size: 32 + fields: + - name: ETM_TASK_GPIO8_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO8_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO9_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO9_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO10_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO10_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO11_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO11_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P3_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 172 + size: 32 + fields: + - name: ETM_TASK_GPIO12_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO12_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO13_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO13_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO14_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO14_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO15_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO15_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P4_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 176 + size: 32 + fields: + - name: ETM_TASK_GPIO16_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO16_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO17_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO17_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO18_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO18_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO19_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO19_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P5_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 180 + size: 32 + fields: + - name: ETM_TASK_GPIO20_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO20_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO21_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO21_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO22_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO22_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO23_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO23_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P6_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 184 + size: 32 + fields: + - name: ETM_TASK_GPIO24_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO24_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO25_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO25_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO26_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO26_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO27_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO27_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P7_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 188 + size: 32 + fields: + - name: ETM_TASK_GPIO28_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO28_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO29_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO29_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO30_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO30_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - register: + name: VERSION + description: Version Control Register + addressOffset: 252 + size: 32 + resetValue: 35663952 + fields: + - name: GPIO_SD_DATE + description: Version control register. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: HINF + description: HINF Peripheral + groupName: HINF + baseAddress: 1610702848 + addressBlock: + - offset: 0 + size: 84 + usage: registers + registers: + - register: + name: CFG_DATA0 + description: Configure sdio cis content + addressOffset: 0 + size: 32 + resetValue: 9594470 + fields: + - name: DEVICE_ID_FN1 + description: configure device id of function1 in cis + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: USER_ID_FN1 + description: configure user id of function1 in cis + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: CFG_DATA1 + description: SDIO configuration register + addressOffset: 4 + size: 32 + resetValue: 2301969 + fields: + - name: SDIO_ENABLE + description: Sdio clock enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SDIO_IOREADY1 + description: sdio function1 io ready signal in cis + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: HIGHSPEED_ENABLE + description: Highspeed enable in cccr + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: HIGHSPEED_MODE + description: highspeed mode status in cccr + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SDIO_CD_ENABLE + description: sdio card detect enable + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SDIO_IOREADY2 + description: sdio function1 io ready signal in cis + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SDIO_INT_MASK + description: "mask sdio interrupt in cccr, high active" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: IOENABLE2 + description: ioe2 status in cccr + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: CD_DISABLE + description: card disable status in cccr + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: FUNC1_EPS + description: function1 eps status in fbr + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: EMP + description: empc status in cccr + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: IOENABLE1 + description: ioe1 status in cccr + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: SDIO_VER + description: sdio version in cccr + bitOffset: 12 + bitWidth: 12 + access: read-write + - name: FUNC2_EPS + description: function2 eps status in fbr + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: SDIO20_CONF + description: "[29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat in delayed cycles control,0:no delay, 1:delay 1 cycle.\n[25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed mode. \n[26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when [12]=0,posedge when highspeed mode enable.\n[27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay.\n[28]: sdio data pad pull up enable" + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: CFG_TIMING + description: Timing configuration registers + addressOffset: 8 + size: 32 + resetValue: 360187922 + fields: + - name: NCRC + description: "configure Ncrc parameter in sdr50/104 mode, no more than 6." + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: PST_END_CMD_LOW_VALUE + description: configure cycles to lower cmd after voltage is changed to 1.8V. + bitOffset: 3 + bitWidth: 7 + access: read-write + - name: PST_END_DATA_LOW_VALUE + description: configure cycles to lower data after voltage is changed to 1.8V. + bitOffset: 10 + bitWidth: 6 + access: read-write + - name: SDCLK_STOP_THRES + description: Configure the number of cycles of module clk to judge sdclk has stopped + bitOffset: 16 + bitWidth: 11 + access: read-write + - name: SAMPLE_CLK_DIVIDER + description: module clk divider to sample sdclk + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: CFG_UPDATE + description: update sdio configurations + addressOffset: 12 + size: 32 + fields: + - name: CONF_UPDATE + description: update the timing configurations + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: CFG_DATA7 + description: SDIO configuration register + addressOffset: 28 + size: 32 + resetValue: 595722240 + fields: + - name: PIN_STATE + description: configure cis addr 318 and 574 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CHIP_STATE + description: "configure cis addr 312, 315, 568 and 571" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SDIO_RST + description: soft reset control for sdio module + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SDIO_IOREADY0 + description: "sdio io ready, high enable" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SDIO_MEM_PD + description: "sdio memory power down, high active" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: ESDIO_DATA1_INT_EN + description: enable sdio interrupt on data1 line + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SDIO_SWITCH_VOLT_SW + description: "control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: DDR50_BLK_LEN_FIX_EN + description: enable block length to be fixed to 512 bytes in ddr50 mode + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "sdio apb clock for configuration force on control:0-gating,1-force on." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SDDR50 + description: configure if support sdr50 mode in cccr + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SSDR104 + description: configure if support sdr104 mode in cccr + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SSDR50 + description: configure if support ddr50 mode in cccr + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: SDTD + description: configure if support driver type D in cccr + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SDTA + description: configure if support driver type A in cccr + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SDTC + description: configure if support driver type C in cccr + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SAI + description: configure if support asynchronous interrupt in cccr + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SDIO_WAKEUP_CLR + description: clear sdio_wake_up signal after the chip wakes up + bitOffset: 30 + bitWidth: 1 + access: write-only + - register: + name: CIS_CONF_W0 + description: SDIO cis configuration register + addressOffset: 32 + size: 32 + resetValue: 4294967295 + fields: + - name: CIS_CONF_W0 + description: Configure cis addr 39~36 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CIS_CONF_W1 + description: SDIO cis configuration register + addressOffset: 36 + size: 32 + resetValue: 4294967295 + fields: + - name: CIS_CONF_W1 + description: Configure cis addr 43~40 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CIS_CONF_W2 + description: SDIO cis configuration register + addressOffset: 40 + size: 32 + resetValue: 4294967295 + fields: + - name: CIS_CONF_W2 + description: Configure cis addr 47~44 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CIS_CONF_W3 + description: SDIO cis configuration register + addressOffset: 44 + size: 32 + resetValue: 4294967295 + fields: + - name: CIS_CONF_W3 + description: Configure cis addr 51~48 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CIS_CONF_W4 + description: SDIO cis configuration register + addressOffset: 48 + size: 32 + resetValue: 4294967295 + fields: + - name: CIS_CONF_W4 + description: Configure cis addr 55~52 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CIS_CONF_W5 + description: SDIO cis configuration register + addressOffset: 52 + size: 32 + resetValue: 4294967295 + fields: + - name: CIS_CONF_W5 + description: Configure cis addr 59~56 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CIS_CONF_W6 + description: SDIO cis configuration register + addressOffset: 56 + size: 32 + resetValue: 4294967295 + fields: + - name: CIS_CONF_W6 + description: Configure cis addr 63~60 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CIS_CONF_W7 + description: SDIO cis configuration register + addressOffset: 60 + size: 32 + resetValue: 4294967295 + fields: + - name: CIS_CONF_W7 + description: Configure cis addr 67~64 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CFG_DATA16 + description: SDIO cis configuration register + addressOffset: 64 + size: 32 + resetValue: 9598839 + fields: + - name: DEVICE_ID_FN2 + description: configure device id of function2 in cis + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: USER_ID_FN2 + description: configure user id of function2 in cis + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: CFG_UHS1_INT_MODE + description: configure int to start and end ahead of time in uhs1 mode + addressOffset: 68 + size: 32 + fields: + - name: INTOE_END_AHEAD_MODE + description: "intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: INT_END_AHEAD_MODE + description: "int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: INTOE_ST_AHEAD_MODE + description: "intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: INT_ST_AHEAD_MODE + description: "int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk" + bitOffset: 6 + bitWidth: 2 + access: read-write + - register: + name: CONF_STATUS + description: func0 config0 status + addressOffset: 84 + size: 32 + fields: + - name: FUNC0_CONFIG0 + description: "func0 config0 (addr: 0x20f0 ) status" + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: SDR25_ST + description: sdr25 status + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SDR50_ST + description: sdr50 status + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SDR104_ST + description: sdr104 status + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: DDR50_ST + description: ddr50 status + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TUNE_ST + description: tune_st fsm status + bitOffset: 12 + bitWidth: 3 + access: read-only + - name: SDIO_SWITCH_VOLT_ST + description: "sdio switch voltage status:0-3.3V, 1-1.8V." + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SDIO_SWITCH_END + description: sdio switch voltage ldo ready + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: SDIO_SLAVE_ECO_LOW + description: sdio_slave redundant control registers + addressOffset: 164 + size: 32 + fields: + - name: RDN_ECO_LOW + description: redundant registers for sdio_slave + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SDIO_SLAVE_ECO_HIGH + description: sdio_slave redundant control registers + addressOffset: 168 + size: 32 + resetValue: 4294967295 + fields: + - name: RDN_ECO_HIGH + description: redundant registers for sdio_slave + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SDIO_SLAVE_ECO_CONF + description: sdio_slave redundant control registers + addressOffset: 172 + size: 32 + fields: + - name: SDIO_SLAVE_RDN_RESULT + description: redundant registers for sdio_slave + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SDIO_SLAVE_RDN_ENA + description: redundant registers for sdio_slave + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SDIO_SLAVE_SDIO_CLK_RDN_RESULT + description: redundant registers for sdio_slave + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SDIO_SLAVE_SDIO_CLK_RDN_ENA + description: redundant registers for sdio_slave + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SDIO_SLAVE_SDCLK_PAD_RDN_RESULT + description: redundant registers for sdio_slave + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SDIO_SLAVE_SDCLK_PAD_RDN_ENA + description: redundant registers for sdio_slave + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: SDIO_SLAVE_LDO_CONF + description: sdio slave ldo control register + addressOffset: 176 + size: 32 + resetValue: 20 + fields: + - name: LDO_READY_CTL_IN_EN + description: control ldo ready signal by sdio slave itself + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LDO_READY_THRES + description: "configure ldo ready counting threshold value, the actual counting target is 2^(ldo_ready_thres)-1" + bitOffset: 1 + bitWidth: 5 + access: read-write + - name: LDO_READY_IGNORE_EN + description: ignore ldo ready signal + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: SDIO_DATE + description: "******* Description ***********" + addressOffset: 252 + size: 32 + resetValue: 35664208 + fields: + - name: SDIO_DATE + description: sdio version date. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: HMAC + description: HMAC (Hash-based Message Authentication Code) Accelerator + groupName: HMAC + baseAddress: 1611190272 + addressBlock: + - offset: 0 + size: 164 + usage: registers + registers: + - register: + name: SET_START + description: Process control register 0. + addressOffset: 64 + size: 32 + fields: + - name: SET_START + description: Start hmac operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_PARA_PURPOSE + description: Configure purpose. + addressOffset: 68 + size: 32 + fields: + - name: PURPOSE_SET + description: Set hmac parameter purpose. + bitOffset: 0 + bitWidth: 4 + access: write-only + - register: + name: SET_PARA_KEY + description: Configure key. + addressOffset: 72 + size: 32 + fields: + - name: KEY_SET + description: Set hmac parameter key. + bitOffset: 0 + bitWidth: 3 + access: write-only + - register: + name: SET_PARA_FINISH + description: Finish initial configuration. + addressOffset: 76 + size: 32 + fields: + - name: SET_PARA_END + description: Finish hmac configuration. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_MESSAGE_ONE + description: Process control register 1. + addressOffset: 80 + size: 32 + fields: + - name: SET_TEXT_ONE + description: Call SHA to calculate one message block. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_MESSAGE_ING + description: Process control register 2. + addressOffset: 84 + size: 32 + fields: + - name: SET_TEXT_ING + description: Continue typical hmac. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_MESSAGE_END + description: Process control register 3. + addressOffset: 88 + size: 32 + fields: + - name: SET_TEXT_END + description: Start hardware padding. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_RESULT_FINISH + description: Process control register 4. + addressOffset: 92 + size: 32 + fields: + - name: SET_RESULT_END + description: "After read result from upstream, then let hmac back to idle." + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_INVALIDATE_JTAG + description: Invalidate register 0. + addressOffset: 96 + size: 32 + fields: + - name: SET_INVALIDATE_JTAG + description: Clear result from hmac downstream JTAG. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_INVALIDATE_DS + description: Invalidate register 1. + addressOffset: 100 + size: 32 + fields: + - name: SET_INVALIDATE_DS + description: Clear result from hmac downstream DS. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: QUERY_ERROR + description: Error register. + addressOffset: 104 + size: 32 + fields: + - name: QUERY_CHECK + description: "Hmac configuration state. 0: key are agree with purpose. 1: error" + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: QUERY_BUSY + description: Busy register. + addressOffset: 108 + size: 32 + fields: + - name: BUSY_STATE + description: "Hmac state. 1'b0: idle. 1'b1: busy" + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + dim: 16 + dimIncrement: 4 + name: "WR_MESSAGE_MEM[%s]" + description: Message block memory. + addressOffset: 128 + size: 32 + - register: + dim: 8 + dimIncrement: 4 + name: "RD_RESULT_MEM[%s]" + description: Result from upstream. + addressOffset: 192 + size: 32 + - register: + name: SET_MESSAGE_PAD + description: Process control register 5. + addressOffset: 240 + size: 32 + fields: + - name: SET_TEXT_PAD + description: Start software padding. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: ONE_BLOCK + description: Process control register 6. + addressOffset: 244 + size: 32 + fields: + - name: SET_ONE_BLOCK + description: "Don't have to do padding." + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SOFT_JTAG_CTRL + description: Jtag register 0. + addressOffset: 248 + size: 32 + fields: + - name: SOFT_JTAG_CTRL + description: Turn on JTAG verification. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: WR_JTAG + description: Jtag register 1. + addressOffset: 252 + size: 32 + fields: + - name: WR_JTAG + description: 32-bit of key to be compared. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: DATE + description: Date register. + addressOffset: 508 + size: 32 + resetValue: 538969624 + fields: + - name: DATE + description: Hmac date information/ hmac version information. + bitOffset: 0 + bitWidth: 30 + access: read-write + - name: HP_APM + description: HP_APM Peripheral + groupName: HP_APM + baseAddress: 1611239424 + addressBlock: + - offset: 0 + size: 276 + usage: registers + interrupt: + - name: HP_APM_M0 + value: 35 + - name: HP_APM_M1 + value: 36 + - name: HP_APM_M2 + value: 37 + - name: HP_APM_M3 + value: 38 + registers: + - register: + name: REGION_FILTER_EN + description: Region filter enable register + addressOffset: 0 + size: 32 + resetValue: 1 + fields: + - name: REGION_FILTER_EN + description: Region filter enable + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: REGION0_ADDR_START + description: Region address register + addressOffset: 4 + size: 32 + fields: + - name: REGION0_ADDR_START + description: Start address of region0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION0_ADDR_END + description: Region address register + addressOffset: 8 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION0_ADDR_END + description: End address of region0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION0_PMS_ATTR + description: Region access authority attribute register + addressOffset: 12 + size: 32 + fields: + - name: REGION0_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION0_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION0_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION0_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION0_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION0_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION0_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION0_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION0_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION1_ADDR_START + description: Region address register + addressOffset: 16 + size: 32 + fields: + - name: REGION1_ADDR_START + description: Start address of region1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION1_ADDR_END + description: Region address register + addressOffset: 20 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION1_ADDR_END + description: End address of region1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION1_PMS_ATTR + description: Region access authority attribute register + addressOffset: 24 + size: 32 + fields: + - name: REGION1_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION1_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION1_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION1_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION1_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION1_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION1_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION1_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION1_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION2_ADDR_START + description: Region address register + addressOffset: 28 + size: 32 + fields: + - name: REGION2_ADDR_START + description: Start address of region2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION2_ADDR_END + description: Region address register + addressOffset: 32 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION2_ADDR_END + description: End address of region2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION2_PMS_ATTR + description: Region access authority attribute register + addressOffset: 36 + size: 32 + fields: + - name: REGION2_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION2_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION2_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION2_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION2_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION2_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION2_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION2_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION2_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION3_ADDR_START + description: Region address register + addressOffset: 40 + size: 32 + fields: + - name: REGION3_ADDR_START + description: Start address of region3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION3_ADDR_END + description: Region address register + addressOffset: 44 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION3_ADDR_END + description: End address of region3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION3_PMS_ATTR + description: Region access authority attribute register + addressOffset: 48 + size: 32 + fields: + - name: REGION3_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION3_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION3_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION3_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION3_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION3_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION3_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION3_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION3_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION4_ADDR_START + description: Region address register + addressOffset: 52 + size: 32 + fields: + - name: REGION4_ADDR_START + description: Start address of region4 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION4_ADDR_END + description: Region address register + addressOffset: 56 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION4_ADDR_END + description: End address of region4 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION4_PMS_ATTR + description: Region access authority attribute register + addressOffset: 60 + size: 32 + fields: + - name: REGION4_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION4_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION4_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION4_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION4_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION4_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION4_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION4_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION4_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION5_ADDR_START + description: Region address register + addressOffset: 64 + size: 32 + fields: + - name: REGION5_ADDR_START + description: Start address of region5 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION5_ADDR_END + description: Region address register + addressOffset: 68 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION5_ADDR_END + description: End address of region5 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION5_PMS_ATTR + description: Region access authority attribute register + addressOffset: 72 + size: 32 + fields: + - name: REGION5_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION5_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION5_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION5_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION5_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION5_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION5_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION5_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION5_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION6_ADDR_START + description: Region address register + addressOffset: 76 + size: 32 + fields: + - name: REGION6_ADDR_START + description: Start address of region6 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION6_ADDR_END + description: Region address register + addressOffset: 80 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION6_ADDR_END + description: End address of region6 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION6_PMS_ATTR + description: Region access authority attribute register + addressOffset: 84 + size: 32 + fields: + - name: REGION6_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION6_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION6_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION6_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION6_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION6_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION6_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION6_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION6_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION7_ADDR_START + description: Region address register + addressOffset: 88 + size: 32 + fields: + - name: REGION7_ADDR_START + description: Start address of region7 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION7_ADDR_END + description: Region address register + addressOffset: 92 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION7_ADDR_END + description: End address of region7 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION7_PMS_ATTR + description: Region access authority attribute register + addressOffset: 96 + size: 32 + fields: + - name: REGION7_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION7_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION7_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION7_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION7_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION7_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION7_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION7_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION7_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION8_ADDR_START + description: Region address register + addressOffset: 100 + size: 32 + fields: + - name: REGION8_ADDR_START + description: Start address of region8 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION8_ADDR_END + description: Region address register + addressOffset: 104 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION8_ADDR_END + description: End address of region8 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION8_PMS_ATTR + description: Region access authority attribute register + addressOffset: 108 + size: 32 + fields: + - name: REGION8_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION8_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION8_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION8_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION8_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION8_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION8_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION8_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION8_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION9_ADDR_START + description: Region address register + addressOffset: 112 + size: 32 + fields: + - name: REGION9_ADDR_START + description: Start address of region9 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION9_ADDR_END + description: Region address register + addressOffset: 116 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION9_ADDR_END + description: End address of region9 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION9_PMS_ATTR + description: Region access authority attribute register + addressOffset: 120 + size: 32 + fields: + - name: REGION9_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION9_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION9_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION9_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION9_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION9_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION9_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION9_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION9_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION10_ADDR_START + description: Region address register + addressOffset: 124 + size: 32 + fields: + - name: REGION10_ADDR_START + description: Start address of region10 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION10_ADDR_END + description: Region address register + addressOffset: 128 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION10_ADDR_END + description: End address of region10 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION10_PMS_ATTR + description: Region access authority attribute register + addressOffset: 132 + size: 32 + fields: + - name: REGION10_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION10_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION10_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION10_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION10_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION10_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION10_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION10_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION10_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION11_ADDR_START + description: Region address register + addressOffset: 136 + size: 32 + fields: + - name: REGION11_ADDR_START + description: Start address of region11 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION11_ADDR_END + description: Region address register + addressOffset: 140 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION11_ADDR_END + description: End address of region11 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION11_PMS_ATTR + description: Region access authority attribute register + addressOffset: 144 + size: 32 + fields: + - name: REGION11_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION11_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION11_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION11_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION11_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION11_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION11_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION11_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION11_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION12_ADDR_START + description: Region address register + addressOffset: 148 + size: 32 + fields: + - name: REGION12_ADDR_START + description: Start address of region12 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION12_ADDR_END + description: Region address register + addressOffset: 152 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION12_ADDR_END + description: End address of region12 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION12_PMS_ATTR + description: Region access authority attribute register + addressOffset: 156 + size: 32 + fields: + - name: REGION12_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION12_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION12_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION12_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION12_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION12_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION12_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION12_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION12_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION13_ADDR_START + description: Region address register + addressOffset: 160 + size: 32 + fields: + - name: REGION13_ADDR_START + description: Start address of region13 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION13_ADDR_END + description: Region address register + addressOffset: 164 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION13_ADDR_END + description: End address of region13 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION13_PMS_ATTR + description: Region access authority attribute register + addressOffset: 168 + size: 32 + fields: + - name: REGION13_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION13_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION13_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION13_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION13_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION13_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION13_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION13_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION13_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION14_ADDR_START + description: Region address register + addressOffset: 172 + size: 32 + fields: + - name: REGION14_ADDR_START + description: Start address of region14 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION14_ADDR_END + description: Region address register + addressOffset: 176 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION14_ADDR_END + description: End address of region14 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION14_PMS_ATTR + description: Region access authority attribute register + addressOffset: 180 + size: 32 + fields: + - name: REGION14_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION14_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION14_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION14_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION14_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION14_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION14_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION14_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION14_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION15_ADDR_START + description: Region address register + addressOffset: 184 + size: 32 + fields: + - name: REGION15_ADDR_START + description: Start address of region15 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION15_ADDR_END + description: Region address register + addressOffset: 188 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION15_ADDR_END + description: End address of region15 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION15_PMS_ATTR + description: Region access authority attribute register + addressOffset: 192 + size: 32 + fields: + - name: REGION15_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION15_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION15_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION15_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION15_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION15_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION15_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION15_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION15_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: FUNC_CTRL + description: PMS function control register + addressOffset: 196 + size: 32 + resetValue: 15 + fields: + - name: M0_PMS_FUNC_EN + description: PMS M0 function enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: M1_PMS_FUNC_EN + description: PMS M1 function enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: M2_PMS_FUNC_EN + description: PMS M2 function enable + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: M3_PMS_FUNC_EN + description: PMS M3 function enable + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: M0_STATUS + description: M0 status register + addressOffset: 200 + size: 32 + fields: + - name: M0_EXCEPTION_STATUS + description: Exception status + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: M0_STATUS_CLR + description: M0 status clear register + addressOffset: 204 + size: 32 + fields: + - name: M0_REGION_STATUS_CLR + description: Clear exception status + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: M0_EXCEPTION_INFO0 + description: M0 exception_info0 register + addressOffset: 208 + size: 32 + fields: + - name: M0_EXCEPTION_REGION + description: Exception region + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: M0_EXCEPTION_MODE + description: Exception mode + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: M0_EXCEPTION_ID + description: Exception id information + bitOffset: 18 + bitWidth: 5 + access: read-only + - register: + name: M0_EXCEPTION_INFO1 + description: M0 exception_info1 register + addressOffset: 212 + size: 32 + fields: + - name: M0_EXCEPTION_ADDR + description: Exception addr + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: M1_STATUS + description: M1 status register + addressOffset: 216 + size: 32 + fields: + - name: M1_EXCEPTION_STATUS + description: Exception status + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: M1_STATUS_CLR + description: M1 status clear register + addressOffset: 220 + size: 32 + fields: + - name: M1_REGION_STATUS_CLR + description: Clear exception status + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: M1_EXCEPTION_INFO0 + description: M1 exception_info0 register + addressOffset: 224 + size: 32 + fields: + - name: M1_EXCEPTION_REGION + description: Exception region + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: M1_EXCEPTION_MODE + description: Exception mode + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: M1_EXCEPTION_ID + description: Exception id information + bitOffset: 18 + bitWidth: 5 + access: read-only + - register: + name: M1_EXCEPTION_INFO1 + description: M1 exception_info1 register + addressOffset: 228 + size: 32 + fields: + - name: M1_EXCEPTION_ADDR + description: Exception addr + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: M2_STATUS + description: M2 status register + addressOffset: 232 + size: 32 + fields: + - name: M2_EXCEPTION_STATUS + description: Exception status + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: M2_STATUS_CLR + description: M2 status clear register + addressOffset: 236 + size: 32 + fields: + - name: M2_REGION_STATUS_CLR + description: Clear exception status + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: M2_EXCEPTION_INFO0 + description: M2 exception_info0 register + addressOffset: 240 + size: 32 + fields: + - name: M2_EXCEPTION_REGION + description: Exception region + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: M2_EXCEPTION_MODE + description: Exception mode + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: M2_EXCEPTION_ID + description: Exception id information + bitOffset: 18 + bitWidth: 5 + access: read-only + - register: + name: M2_EXCEPTION_INFO1 + description: M2 exception_info1 register + addressOffset: 244 + size: 32 + fields: + - name: M2_EXCEPTION_ADDR + description: Exception addr + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: M3_STATUS + description: M3 status register + addressOffset: 248 + size: 32 + fields: + - name: M3_EXCEPTION_STATUS + description: Exception status + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: M3_STATUS_CLR + description: M3 status clear register + addressOffset: 252 + size: 32 + fields: + - name: M3_REGION_STATUS_CLR + description: Clear exception status + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: M3_EXCEPTION_INFO0 + description: M3 exception_info0 register + addressOffset: 256 + size: 32 + fields: + - name: M3_EXCEPTION_REGION + description: Exception region + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: M3_EXCEPTION_MODE + description: Exception mode + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: M3_EXCEPTION_ID + description: Exception id information + bitOffset: 18 + bitWidth: 5 + access: read-only + - register: + name: M3_EXCEPTION_INFO1 + description: M3 exception_info1 register + addressOffset: 260 + size: 32 + fields: + - name: M3_EXCEPTION_ADDR + description: Exception addr + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INT_EN + description: APM interrupt enable register + addressOffset: 264 + size: 32 + fields: + - name: M0_APM_INT_EN + description: APM M0 interrupt enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: M1_APM_INT_EN + description: APM M1 interrupt enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: M2_APM_INT_EN + description: APM M2 interrupt enable + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: M3_APM_INT_EN + description: APM M3 interrupt enable + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: CLOCK_GATE + description: clock gating register + addressOffset: 268 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: reg_clk_en + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version register + addressOffset: 2044 + size: 32 + resetValue: 35672640 + fields: + - name: DATE + description: reg_date + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: HP_SYS + description: High-Power System + groupName: HP_SYS + baseAddress: 1611223040 + addressBlock: + - offset: 0 + size: 92 + usage: registers + interrupt: + - name: HP_PERI_TIMEOUT + value: 33 + - name: MODEM_PERI_TIMEOUT + value: 34 + registers: + - register: + name: EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL + description: EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register + addressOffset: 0 + size: 32 + fields: + - name: ENABLE_SPI_MANUAL_ENCRYPT + description: Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ENABLE_DOWNLOAD_DB_ENCRYPT + description: reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ENABLE_DOWNLOAD_G0CB_DECRYPT + description: Set this bit as 1 to enable mspi xts auto decrypt in download boot mode. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ENABLE_DOWNLOAD_MANUAL_ENCRYPT + description: Set this bit as 1 to enable mspi xts manual encrypt in download boot mode. + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: SRAM_USAGE_CONF + description: HP memory usage configuration register + addressOffset: 4 + size: 32 + fields: + - name: CACHE_USAGE + description: reserved + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SRAM_USAGE + description: "0: cpu use hp-memory. 1:mac-dump accessing hp-memory." + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: MAC_DUMP_ALLOC + description: Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory. + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: SEC_DPA_CONF + description: HP anti-DPA security configuration register + addressOffset: 8 + size: 32 + fields: + - name: SEC_DPA_LEVEL + description: "0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger the number, the stronger the ability to resist DPA attacks and the higher the security level, but it will increase the computational overhead of the hardware crypto-accelerators. Only avaliable if HP_SYS_SEC_DPA_CFG_SEL is 0." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SEC_DPA_CFG_SEL + description: "This field is used to select either HP_SYS_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYS_SEC_DPA_LEVEL." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: CPU_PERI_TIMEOUT_CONF + description: CPU_PERI_TIMEOUT configuration register + addressOffset: 12 + size: 32 + resetValue: 196607 + fields: + - name: CPU_PERI_TIMEOUT_THRES + description: "Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CPU_PERI_TIMEOUT_INT_CLEAR + description: Set this bit as 1 to clear timeout interrupt + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: CPU_PERI_TIMEOUT_PROTECT_EN + description: Set this bit as 1 to enable timeout protection for accessing cpu peripheral registers + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: CPU_PERI_TIMEOUT_ADDR + description: CPU_PERI_TIMEOUT_ADDR register + addressOffset: 16 + size: 32 + fields: + - name: CPU_PERI_TIMEOUT_ADDR + description: Record the address information of abnormal access + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CPU_PERI_TIMEOUT_UID + description: CPU_PERI_TIMEOUT_UID register + addressOffset: 20 + size: 32 + fields: + - name: CPU_PERI_TIMEOUT_UID + description: "Record master id[4:0] & master permission[6:5] when trigger timeout. This register will be cleared after the interrupt is cleared." + bitOffset: 0 + bitWidth: 7 + access: read-only + - register: + name: HP_PERI_TIMEOUT_CONF + description: HP_PERI_TIMEOUT configuration register + addressOffset: 24 + size: 32 + resetValue: 196607 + fields: + - name: HP_PERI_TIMEOUT_THRES + description: "Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: HP_PERI_TIMEOUT_INT_CLEAR + description: Set this bit as 1 to clear timeout interrupt + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: HP_PERI_TIMEOUT_PROTECT_EN + description: Set this bit as 1 to enable timeout protection for accessing hp peripheral registers + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: HP_PERI_TIMEOUT_ADDR + description: HP_PERI_TIMEOUT_ADDR register + addressOffset: 28 + size: 32 + fields: + - name: HP_PERI_TIMEOUT_ADDR + description: Record the address information of abnormal access + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HP_PERI_TIMEOUT_UID + description: HP_PERI_TIMEOUT_UID register + addressOffset: 32 + size: 32 + fields: + - name: HP_PERI_TIMEOUT_UID + description: "Record master id[4:0] & master permission[6:5] when trigger timeout. This register will be cleared after the interrupt is cleared." + bitOffset: 0 + bitWidth: 7 + access: read-only + - register: + name: MODEM_PERI_TIMEOUT_CONF + description: MODEM_PERI_TIMEOUT configuration register + addressOffset: 36 + size: 32 + resetValue: 196607 + fields: + - name: MODEM_PERI_TIMEOUT_THRES + description: "Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MODEM_PERI_TIMEOUT_INT_CLEAR + description: Set this bit as 1 to clear timeout interrupt + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: MODEM_PERI_TIMEOUT_PROTECT_EN + description: Set this bit as 1 to enable timeout protection for accessing modem registers + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: MODEM_PERI_TIMEOUT_ADDR + description: MODEM_PERI_TIMEOUT_ADDR register + addressOffset: 40 + size: 32 + fields: + - name: MODEM_PERI_TIMEOUT_ADDR + description: Record the address information of abnormal access + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: MODEM_PERI_TIMEOUT_UID + description: MODEM_PERI_TIMEOUT_UID register + addressOffset: 44 + size: 32 + fields: + - name: MODEM_PERI_TIMEOUT_UID + description: "Record master id[4:0] & master permission[6:5] when trigger timeout. This register will be cleared after the interrupt is cleared." + bitOffset: 0 + bitWidth: 7 + access: read-only + - register: + name: SDIO_CTRL + description: SDIO Control configuration register + addressOffset: 48 + size: 32 + resetValue: 3 + fields: + - name: DIS_SDIO_PROB + description: Set this bit as 1 to disable SDIO_PROB function. disable by default. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SDIO_WIN_ACCESS_EN + description: Enable sdio slave to access other peripherals on the chip + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: RETENTION_CONF + description: Retention configuration register + addressOffset: 52 + size: 32 + fields: + - name: RETENTION_DISABLE + description: Set this bit as 1 to disable retention function. Not disable by default. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: ROM_TABLE_LOCK + description: Rom-Table lock register + addressOffset: 56 + size: 32 + fields: + - name: ROM_TABLE_LOCK + description: XXXX + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: ROM_TABLE + description: Rom-Table register + addressOffset: 60 + size: 32 + fields: + - name: ROM_TABLE + description: XXXX + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_DEBUG_RUNSTALL_CONF + description: Core Debug runstall configure register + addressOffset: 64 + size: 32 + fields: + - name: CORE_DEBUG_RUNSTALL_ENABLE + description: Set this field to 1 to enable debug runstall feature between HP-core and LP-core. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: MEM_TEST_CONF + description: MEM_TEST configuration register + addressOffset: 68 + size: 32 + resetValue: 32 + fields: + - name: HP_MEM_WPULSE + description: This field controls hp system memory WPULSE parameter. + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: HP_MEM_WA + description: This field controls hp system memory WA parameter. + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: HP_MEM_RA + description: This field controls hp system memory RA parameter. + bitOffset: 6 + bitWidth: 2 + access: read-write + - register: + name: RND_ECO + description: redcy eco register. + addressOffset: 992 + size: 32 + fields: + - name: REDCY_ENA + description: Only reserved for ECO. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REDCY_RESULT + description: Only reserved for ECO. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: RND_ECO_LOW + description: redcy eco low register. + addressOffset: 996 + size: 32 + fields: + - name: REDCY_LOW + description: Only reserved for ECO. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RND_ECO_HIGH + description: redcy eco high register. + addressOffset: 1000 + size: 32 + resetValue: 4294967295 + fields: + - name: REDCY_HIGH + description: Only reserved for ECO. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CLOCK_GATE + description: HP-SYSTEM clock gating configure register + addressOffset: 1016 + size: 32 + fields: + - name: CLK_EN + description: Set this bit as 1 to force on clock gating. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Date register. + addressOffset: 1020 + size: 32 + resetValue: 35676432 + fields: + - name: DATE + description: HP-SYSTEM date information/ HP-SYSTEM version information. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: I2C0 + description: I2C (Inter-Integrated Circuit) Controller 0 + groupName: I2C + baseAddress: 1610629120 + addressBlock: + - offset: 0 + size: 144 + usage: registers + interrupt: + - name: I2C_MASTER + value: 11 + - name: I2C_EXT0 + value: 50 + registers: + - register: + name: SCL_LOW_PERIOD + description: "Configures the low level width of the SCL\nClock" + addressOffset: 0 + size: 32 + fields: + - name: SCL_LOW_PERIOD + description: "This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: CTR + description: Transmission setting + addressOffset: 4 + size: 32 + resetValue: 520 + fields: + - name: SDA_FORCE_OUT + description: "1: direct output, 0: open drain output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_FORCE_OUT + description: "1: direct output, 0: open drain output." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SAMPLE_SCL_LEVEL + description: "This register is used to select the sample mode.\n1: sample SDA data on the SCL low level.\n0: sample SDA data on the SCL high level." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_FULL_ACK_LEVEL + description: This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MS_MODE + description: "Set this bit to configure the module as an I2C Master. Clear this bit to configure the\nmodule as an I2C Slave." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TRANS_START + description: Set this bit to start sending the data in txfifo. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TX_LSB_FIRST + description: "This bit is used to control the sending mode for data needing to be sent. \n1: send data from the least significant bit,\n0: send data from the most significant bit." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_LSB_FIRST + description: "This bit is used to control the storage mode for received data.\n1: receive data from the least significant bit,\n0: receive data from the most significant bit." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ARBITRATION_EN + description: This is the enable bit for arbitration_lost. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FSM_RST + description: This register is used to reset the scl FMS. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: CONF_UPGATE + description: synchronization bit + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: SLV_TX_AUTO_START_EN + description: This is the enable bit for slave to send data automatically + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: ADDR_10BIT_RW_CHECK_EN + description: This is the enable bit to check if the r/w bit of 10bit addressing consists with I2C protocol + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: ADDR_BROADCASTING_EN + description: This is the enable bit to support the 7bit general call function. + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: SR + description: Describe I2C work status. + addressOffset: 8 + size: 32 + resetValue: 49152 + fields: + - name: RESP_REC + description: "The received ACK value in master mode or slave mode. 0: ACK, 1: NACK." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SLAVE_RW + description: "When in slave mode, 1: master reads from slave, 0: master writes to slave." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ARB_LOST + description: "When the I2C controller loses control of SCL line, this register changes to 1." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BUS_BUSY + description: "1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SLAVE_ADDRESSED + description: "When configured as an I2C Slave, and the address sent by the master is\nequal to the address of the slave, then this bit will be of high level." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: RXFIFO_CNT + description: This field represents the amount of data needed to be sent. + bitOffset: 8 + bitWidth: 6 + access: read-only + - name: STRETCH_CAUSE + description: "The cause of stretching SCL low in slave mode. 0: stretching SCL low at the beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode." + bitOffset: 14 + bitWidth: 2 + access: read-only + - name: TXFIFO_CNT + description: This field stores the amount of received data in RAM. + bitOffset: 18 + bitWidth: 6 + access: read-only + - name: SCL_MAIN_STATE_LAST + description: "This field indicates the states of the I2C module state machine. \n0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK" + bitOffset: 24 + bitWidth: 3 + access: read-only + - name: SCL_STATE_LAST + description: "This field indicates the states of the state machine used to produce SCL.\n0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop" + bitOffset: 28 + bitWidth: 3 + access: read-only + - register: + name: TO + description: Setting time out control for receiving data. + addressOffset: 12 + size: 32 + resetValue: 16 + fields: + - name: TIME_OUT_VALUE + description: "This register is used to configure the timeout for receiving a data bit in APB\nclock cycles." + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: TIME_OUT_EN + description: This is the enable bit for time out control. + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: SLAVE_ADDR + description: Local slave address setting + addressOffset: 16 + size: 32 + fields: + - name: SLAVE_ADDR + description: "When configured as an I2C Slave, this field is used to configure the slave address." + bitOffset: 0 + bitWidth: 15 + access: read-write + - name: ADDR_10BIT_EN + description: This field is used to enable the slave 10-bit addressing mode in master mode. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: FIFO_ST + description: FIFO status register. + addressOffset: 20 + size: 32 + fields: + - name: RXFIFO_RADDR + description: This is the offset address of the APB reading from rxfifo + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: RXFIFO_WADDR + description: This is the offset address of i2c module receiving data and writing to rxfifo. + bitOffset: 5 + bitWidth: 5 + access: read-only + - name: TXFIFO_RADDR + description: This is the offset address of i2c module reading from txfifo. + bitOffset: 10 + bitWidth: 5 + access: read-only + - name: TXFIFO_WADDR + description: This is the offset address of APB bus writing to txfifo. + bitOffset: 15 + bitWidth: 5 + access: read-only + - name: SLAVE_RW_POINT + description: The received data in I2C slave mode. + bitOffset: 22 + bitWidth: 8 + access: read-only + - register: + name: FIFO_CONF + description: FIFO configuration register. + addressOffset: 24 + size: 32 + resetValue: 16523 + fields: + - name: RXFIFO_WM_THRHD + description: "The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid." + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: TXFIFO_WM_THRHD + description: "The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid." + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: NONFIFO_EN + description: Set this bit to enable APB nonfifo access. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FIFO_ADDR_CFG_EN + description: "When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RX_FIFO_RST + description: Set this bit to reset rx-fifo. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_FIFO_RST + description: Set this bit to reset tx-fifo. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FIFO_PRT_EN + description: "The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty." + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DATA + description: Rx FIFO read data. + addressOffset: 28 + size: 32 + fields: + - name: FIFO_RDATA + description: The value of rx FIFO read data. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 32 + size: 32 + resetValue: 2 + fields: + - name: RXFIFO_WM_INT_RAW + description: The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_WM_INT_RAW + description: The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_RAW + description: The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: END_DETECT_INT_RAW + description: The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS_DONE_INT_RAW + description: The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_RAW + description: The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: MST_TXFIFO_UDF_INT_RAW + description: The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_RAW + description: The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_RAW + description: The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TRANS_START_INT_RAW + description: The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: NACK_INT_RAW + description: The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: TXFIFO_OVF_INT_RAW + description: The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: RXFIFO_UDF_INT_RAW + description: The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SCL_ST_TO_INT_RAW + description: The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SCL_MAIN_ST_TO_INT_RAW + description: The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DET_START_INT_RAW + description: The raw interrupt bit for I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLAVE_STRETCH_INT_RAW + description: The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: GENERAL_CALL_INT_RAW + description: The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: SLAVE_ADDR_UNMATCH_INT_RAW + description: The raw interrupt bit for I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 36 + size: 32 + fields: + - name: RXFIFO_WM_INT_CLR + description: Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TXFIFO_WM_INT_CLR + description: Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RXFIFO_OVF_INT_CLR + description: Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: END_DETECT_INT_CLR + description: Set this bit to clear the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: BYTE_TRANS_DONE_INT_CLR + description: Set this bit to clear the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: ARBITRATION_LOST_INT_CLR + description: Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: MST_TXFIFO_UDF_INT_CLR + description: Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TRANS_COMPLETE_INT_CLR + description: Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: TIME_OUT_INT_CLR + description: Set this bit to clear the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: TRANS_START_INT_CLR + description: Set this bit to clear the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: NACK_INT_CLR + description: Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: TXFIFO_OVF_INT_CLR + description: Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: RXFIFO_UDF_INT_CLR + description: Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: SCL_ST_TO_INT_CLR + description: Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SCL_MAIN_ST_TO_INT_CLR + description: Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: DET_START_INT_CLR + description: Set this bit to clear I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: SLAVE_STRETCH_INT_CLR + description: Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: GENERAL_CALL_INT_CLR + description: Set this bit to clear I2C_GENARAL_CALL_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: SLAVE_ADDR_UNMATCH_INT_CLR + description: Set this bit to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 40 + size: 32 + fields: + - name: RXFIFO_WM_INT_ENA + description: The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_WM_INT_ENA + description: The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_ENA + description: The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: END_DETECT_INT_ENA + description: The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: BYTE_TRANS_DONE_INT_ENA + description: The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ARBITRATION_LOST_INT_ENA + description: The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: MST_TXFIFO_UDF_INT_ENA + description: The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TRANS_COMPLETE_INT_ENA + description: The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TIME_OUT_INT_ENA + description: The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TRANS_START_INT_ENA + description: The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: NACK_INT_ENA + description: The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TXFIFO_OVF_INT_ENA + description: The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RXFIFO_UDF_INT_ENA + description: The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SCL_ST_TO_INT_ENA + description: The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SCL_MAIN_ST_TO_INT_ENA + description: The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DET_START_INT_ENA + description: The interrupt enable bit for I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLAVE_STRETCH_INT_ENA + description: The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: GENERAL_CALL_INT_ENA + description: The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SLAVE_ADDR_UNMATCH_INT_ENA + description: The interrupt enable bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-write + - register: + name: INT_STATUS + description: Status of captured I2C communication events + addressOffset: 44 + size: 32 + fields: + - name: RXFIFO_WM_INT_ST + description: The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_WM_INT_ST + description: The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_ST + description: The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: END_DETECT_INT_ST + description: The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS_DONE_INT_ST + description: The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_ST + description: The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: MST_TXFIFO_UDF_INT_ST + description: The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_ST + description: The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_ST + description: The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TRANS_START_INT_ST + description: The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: NACK_INT_ST + description: The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: TXFIFO_OVF_INT_ST + description: The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: RXFIFO_UDF_INT_ST + description: The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SCL_ST_TO_INT_ST + description: The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SCL_MAIN_ST_TO_INT_ST + description: The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DET_START_INT_ST + description: The masked interrupt status bit for I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLAVE_STRETCH_INT_ST + description: The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: GENERAL_CALL_INT_ST + description: The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: SLAVE_ADDR_UNMATCH_INT_ST + description: The masked interrupt status bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-only + - register: + name: SDA_HOLD + description: Configures the hold time after a negative SCL edge. + addressOffset: 48 + size: 32 + fields: + - name: TIME + description: "This register is used to configure the time to hold the data after the negative\nedge of SCL, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SDA_SAMPLE + description: Configures the sample time after a positive SCL edge. + addressOffset: 52 + size: 32 + fields: + - name: TIME + description: "This register is used to configure for how long SDA is sampled, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_HIGH_PERIOD + description: Configures the high level width of SCL + addressOffset: 56 + size: 32 + fields: + - name: SCL_HIGH_PERIOD + description: "This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: SCL_WAIT_HIGH_PERIOD + description: "This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles." + bitOffset: 9 + bitWidth: 7 + access: read-write + - register: + name: SCL_START_HOLD + description: Configures the delay between the SDA and SCL negative edge for a start condition + addressOffset: 64 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the time between the negative edge\nof SDA and the negative edge of SCL for a START condition, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_RSTART_SETUP + description: "Configures the delay between the positive\nedge of SCL and the negative edge of SDA" + addressOffset: 68 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the time between the positive\nedge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_STOP_HOLD + description: "Configures the delay after the SCL clock\nedge for a stop condition" + addressOffset: 72 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the delay after the STOP condition,\nin I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_STOP_SETUP + description: "Configures the delay between the SDA and\nSCL positive edge for a stop condition" + addressOffset: 76 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the time between the positive edge\nof SCL and the positive edge of SDA, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: FILTER_CFG + description: SCL and SDA filter configuration register + addressOffset: 80 + size: 32 + resetValue: 768 + fields: + - name: SCL_FILTER_THRES + description: "When a pulse on the SCL input has smaller width than this register value\nin I2C module clock cycles, the I2C controller will ignore that pulse." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: SDA_FILTER_THRES + description: "When a pulse on the SDA input has smaller width than this register value\nin I2C module clock cycles, the I2C controller will ignore that pulse." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: SCL_FILTER_EN + description: This is the filter enable bit for SCL. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SDA_FILTER_EN + description: This is the filter enable bit for SDA. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: CLK_CONF + description: I2C CLK configuration register + addressOffset: 84 + size: 32 + resetValue: 2097152 + fields: + - name: SCLK_DIV_NUM + description: the integral part of the fractional divisor for i2c module + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SCLK_DIV_A + description: the numerator of the fractional part of the fractional divisor for i2c module + bitOffset: 8 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_B + description: the denominator of the fractional part of the fractional divisor for i2c module + bitOffset: 14 + bitWidth: 6 + access: read-write + - name: SCLK_SEL + description: "The clock selection for i2c module:0-XTAL,1-CLK_8MHz." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SCLK_ACTIVE + description: The clock switch for i2c module + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7" + name: COMD%s + description: I2C command register %s + addressOffset: 88 + size: 32 + fields: + - name: COMMAND + description: "This is the content of command 0. It consists of three parts: \nop_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.\nByte_num represents the number of bytes that need to be sent or received.\nack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more\nInformation." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND_DONE + description: "When command 0 is done in I2C Master mode, this bit changes to high\nlevel." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SCL_ST_TIME_OUT + description: SCL status time out register + addressOffset: 120 + size: 32 + resetValue: 16 + fields: + - name: SCL_ST_TO_I2C + description: The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SCL_MAIN_ST_TIME_OUT + description: SCL main status time out register + addressOffset: 124 + size: 32 + resetValue: 16 + fields: + - name: SCL_MAIN_ST_TO_I2C + description: The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23 + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SCL_SP_CONF + description: Power configuration register + addressOffset: 128 + size: 32 + fields: + - name: SCL_RST_SLV_EN + description: "When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_RST_SLV_NUM + description: Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. + bitOffset: 1 + bitWidth: 5 + access: read-write + - name: SCL_PD_EN + description: "The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SDA_PD_EN + description: "The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low." + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: SCL_STRETCH_CONF + description: Set SCL stretch of I2C slave + addressOffset: 132 + size: 32 + fields: + - name: STRETCH_PROTECT_NUM + description: Configure the period of I2C slave stretching SCL line. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: SLAVE_SCL_STRETCH_EN + description: "The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLAVE_SCL_STRETCH_CLR + description: Set this bit to clear the I2C slave SCL stretch function. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: SLAVE_BYTE_ACK_CTL_EN + description: The enable bit for slave to control ACK level function. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SLAVE_BYTE_ACK_LVL + description: Set the ACK level when slave controlling ACK level function enables. + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version register + addressOffset: 248 + size: 32 + resetValue: 35656050 + fields: + - name: DATE + description: This is the the version register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TXFIFO_START_ADDR + description: I2C TXFIFO base address register + addressOffset: 256 + size: 32 + fields: + - name: TXFIFO_START_ADDR + description: This is the I2C txfifo first address. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RXFIFO_START_ADDR + description: I2C RXFIFO base address register + addressOffset: 384 + size: 32 + fields: + - name: RXFIFO_START_ADDR + description: This is the I2C rxfifo first address. + bitOffset: 0 + bitWidth: 32 + access: read-only + - name: I2S0 + description: I2S (Inter-IC Sound) Controller 0 + groupName: I2S + baseAddress: 1610661888 + addressBlock: + - offset: 0 + size: 96 + usage: registers + interrupt: + - name: I2S0 + value: 41 + registers: + - register: + name: INT_RAW + description: "I2S interrupt raw register, valid in level." + addressOffset: 12 + size: 32 + fields: + - name: RX_DONE_INT_RAW + description: The raw interrupt status bit for the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_RAW + description: The raw interrupt status bit for the i2s_tx_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_RAW + description: The raw interrupt status bit for the i2s_rx_hung_int interrupt + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_RAW + description: The raw interrupt status bit for the i2s_tx_hung_int interrupt + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: I2S interrupt status register. + addressOffset: 16 + size: 32 + fields: + - name: RX_DONE_INT_ST + description: The masked interrupt status bit for the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_ST + description: The masked interrupt status bit for the i2s_tx_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_ST + description: The masked interrupt status bit for the i2s_rx_hung_int interrupt + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_ST + description: The masked interrupt status bit for the i2s_tx_hung_int interrupt + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: I2S interrupt enable register. + addressOffset: 20 + size: 32 + fields: + - name: RX_DONE_INT_ENA + description: The interrupt enable bit for the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_ENA + description: The interrupt enable bit for the i2s_tx_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_HUNG_INT_ENA + description: The interrupt enable bit for the i2s_rx_hung_int interrupt + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_HUNG_INT_ENA + description: The interrupt enable bit for the i2s_tx_hung_int interrupt + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: I2S interrupt clear register. + addressOffset: 24 + size: 32 + fields: + - name: RX_DONE_INT_CLR + description: Set this bit to clear the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TX_DONE_INT_CLR + description: Set this bit to clear the i2s_tx_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_HUNG_INT_CLR + description: Set this bit to clear the i2s_rx_hung_int interrupt + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TX_HUNG_INT_CLR + description: Set this bit to clear the i2s_tx_hung_int interrupt + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: RX_CONF + description: I2S RX configure register + addressOffset: 32 + size: 32 + resetValue: 38400 + fields: + - name: RX_RESET + description: Set this bit to reset receiver + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: RX_FIFO_RESET + description: Set this bit to reset Rx AFIFO + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_START + description: Set this bit to start receiving data + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_SLAVE_MOD + description: Set this bit to enable slave receiver mode + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_MONO + description: Set this bit to enable receiver in mono mode + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RX_BIG_ENDIAN + description: "I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RX_UPDATE + description: Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RX_MONO_FST_VLD + description: "1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RX_PCM_CONF + description: "I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: RX_PCM_BYPASS + description: Set this bit to bypass Compress/Decompress module for received data. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RX_STOP_MODE + description: "0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full." + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: RX_LEFT_ALIGN + description: "1: I2S RX left alignment mode. 0: I2S RX right alignment mode." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RX_24_FILL_EN + description: "1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RX_WS_IDLE_POL + description: "0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: RX_BIT_ORDER + description: "I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RX_TDM_EN + description: "1: Enable I2S TDM Rx mode . 0: Disable." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RX_PDM_EN + description: "1: Enable I2S PDM Rx mode . 0: Disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: TX_CONF + description: I2S TX configure register + addressOffset: 36 + size: 32 + resetValue: 45568 + fields: + - name: TX_RESET + description: Set this bit to reset transmitter + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TX_FIFO_RESET + description: Set this bit to reset Tx AFIFO + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TX_START + description: Set this bit to start transmitting data + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_SLAVE_MOD + description: Set this bit to enable slave transmitter mode + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_MONO + description: Set this bit to enable transmitter in mono mode + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TX_CHAN_EQUAL + description: "1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_BIG_ENDIAN + description: "I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TX_UPDATE + description: Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TX_MONO_FST_VLD + description: "1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TX_PCM_CONF + description: "I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: TX_PCM_BYPASS + description: Set this bit to bypass Compress/Decompress module for transmitted data. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_STOP_EN + description: Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_LEFT_ALIGN + description: "1: I2S TX left alignment mode. 0: I2S TX right alignment mode." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TX_24_FILL_EN + description: "1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: TX_WS_IDLE_POL + description: "0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: TX_BIT_ORDER + description: "I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TX_TDM_EN + description: "1: Enable I2S TDM Tx mode . 0: Disable." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: TX_PDM_EN + description: "1: Enable I2S PDM Tx mode . 0: Disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TX_CHAN_MOD + description: I2S transmitter channel mode configuration bits. + bitOffset: 24 + bitWidth: 3 + access: read-write + - name: SIG_LOOPBACK + description: Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: RX_CONF1 + description: I2S RX configure register 1 + addressOffset: 40 + size: 32 + resetValue: 792584960 + fields: + - name: RX_TDM_WS_WIDTH + description: "The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck" + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: RX_BCK_DIV_NUM + description: Bit clock configuration bits in receiver mode. + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: RX_BITS_MOD + description: "Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode." + bitOffset: 13 + bitWidth: 5 + access: read-write + - name: RX_HALF_SAMPLE_BITS + description: I2S Rx half sample bits -1. + bitOffset: 18 + bitWidth: 6 + access: read-write + - name: RX_TDM_CHAN_BITS + description: The Rx bit number for each channel minus 1in TDM mode. + bitOffset: 24 + bitWidth: 5 + access: read-write + - name: RX_MSB_SHIFT + description: Set this bit to enable receiver in Phillips standard mode + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: TX_CONF1 + description: I2S TX configure register 1 + addressOffset: 44 + size: 32 + resetValue: 1866326784 + fields: + - name: TX_TDM_WS_WIDTH + description: "The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck" + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: TX_BCK_DIV_NUM + description: Bit clock configuration bits in transmitter mode. + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: TX_BITS_MOD + description: "Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode." + bitOffset: 13 + bitWidth: 5 + access: read-write + - name: TX_HALF_SAMPLE_BITS + description: I2S Tx half sample bits -1. + bitOffset: 18 + bitWidth: 6 + access: read-write + - name: TX_TDM_CHAN_BITS + description: The Tx bit number for each channel minus 1in TDM mode. + bitOffset: 24 + bitWidth: 5 + access: read-write + - name: TX_MSB_SHIFT + description: Set this bit to enable transmitter in Phillips standard mode + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TX_BCK_NO_DLY + description: "1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode." + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: RX_CLKM_CONF + description: I2S RX clock configure register + addressOffset: 48 + size: 32 + resetValue: 2 + fields: + - name: RX_CLKM_DIV_NUM + description: Integral I2S clock divider value + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: RX_CLK_ACTIVE + description: I2S Rx module clock enable signal. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RX_CLK_SEL + description: "Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in." + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: MCLK_SEL + description: "0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT." + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: TX_CLKM_CONF + description: I2S TX clock configure register + addressOffset: 52 + size: 32 + resetValue: 2 + fields: + - name: TX_CLKM_DIV_NUM + description: "Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TX_CLK_ACTIVE + description: I2S Tx module clock enable signal. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TX_CLK_SEL + description: "Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in." + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: CLK_EN + description: Set this bit to enable clk gate + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: RX_CLKM_DIV_CONF + description: I2S RX module clock divider configure register + addressOffset: 56 + size: 32 + resetValue: 512 + fields: + - name: RX_CLKM_DIV_Z + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: RX_CLKM_DIV_Y + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))." + bitOffset: 9 + bitWidth: 9 + access: read-write + - name: RX_CLKM_DIV_X + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1." + bitOffset: 18 + bitWidth: 9 + access: read-write + - name: RX_CLKM_DIV_YN1 + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1." + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: TX_CLKM_DIV_CONF + description: I2S TX module clock divider configure register + addressOffset: 60 + size: 32 + resetValue: 512 + fields: + - name: TX_CLKM_DIV_Z + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: TX_CLKM_DIV_Y + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))." + bitOffset: 9 + bitWidth: 9 + access: read-write + - name: TX_CLKM_DIV_X + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1." + bitOffset: 18 + bitWidth: 9 + access: read-write + - name: TX_CLKM_DIV_YN1 + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1." + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: TX_PCM2PDM_CONF + description: I2S TX PCM2PDM configuration register + addressOffset: 64 + size: 32 + resetValue: 4890628 + fields: + - name: TX_PDM_HP_BYPASS + description: I2S TX PDM bypass hp filter or not. The option has been removed. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_PDM_SINC_OSR2 + description: I2S TX PDM OSR2 value + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: TX_PDM_PRESCALE + description: I2S TX PDM prescale for sigmadelta + bitOffset: 5 + bitWidth: 8 + access: read-write + - name: TX_PDM_HP_IN_SHIFT + description: "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4" + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: TX_PDM_LP_IN_SHIFT + description: "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4" + bitOffset: 15 + bitWidth: 2 + access: read-write + - name: TX_PDM_SINC_IN_SHIFT + description: "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4" + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: TX_PDM_SIGMADELTA_IN_SHIFT + description: "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4" + bitOffset: 19 + bitWidth: 2 + access: read-write + - name: TX_PDM_SIGMADELTA_DITHER2 + description: I2S TX PDM sigmadelta dither2 value + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: TX_PDM_SIGMADELTA_DITHER + description: I2S TX PDM sigmadelta dither value + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TX_PDM_DAC_2OUT_EN + description: I2S TX PDM dac mode enable + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TX_PDM_DAC_MODE_EN + description: I2S TX PDM dac 2channel enable + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PCM2PDM_CONV_EN + description: I2S TX PDM Converter enable + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: TX_PCM2PDM_CONF1 + description: I2S TX PCM2PDM configuration register + addressOffset: 68 + size: 32 + resetValue: 66552768 + fields: + - name: TX_PDM_FP + description: I2S TX PDM Fp + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: TX_PDM_FS + description: I2S TX PDM Fs + bitOffset: 10 + bitWidth: 10 + access: read-write + - name: TX_IIR_HP_MULT12_5 + description: "The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])" + bitOffset: 20 + bitWidth: 3 + access: read-write + - name: TX_IIR_HP_MULT12_0 + description: "The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])" + bitOffset: 23 + bitWidth: 3 + access: read-write + - register: + name: RX_TDM_CTRL + description: I2S TX TDM mode control register + addressOffset: 80 + size: 32 + resetValue: 65535 + fields: + - name: RX_TDM_PDM_CHAN0_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN1_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN2_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN3_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN4_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN5_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN6_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN7_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN8_EN + description: "1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN9_EN + description: "1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN10_EN + description: "1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN11_EN + description: "1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN12_EN + description: "1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN13_EN + description: "1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN14_EN + description: "1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN15_EN + description: "1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RX_TDM_TOT_CHAN_NUM + description: The total channel number of I2S TX TDM mode. + bitOffset: 16 + bitWidth: 4 + access: read-write + - register: + name: TX_TDM_CTRL + description: I2S TX TDM mode control register + addressOffset: 84 + size: 32 + resetValue: 65535 + fields: + - name: TX_TDM_CHAN0_EN + description: "1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN1_EN + description: "1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN2_EN + description: "1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN3_EN + description: "1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN4_EN + description: "1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN5_EN + description: "1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN6_EN + description: "1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN7_EN + description: "1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN8_EN + description: "1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN9_EN + description: "1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN10_EN + description: "1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN11_EN + description: "1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN12_EN + description: "1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN13_EN + description: "1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN14_EN + description: "1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN15_EN + description: "1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TX_TDM_TOT_CHAN_NUM + description: The total channel number of I2S TX TDM mode. + bitOffset: 16 + bitWidth: 4 + access: read-write + - name: TX_TDM_SKIP_MSK_EN + description: "When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels." + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: RX_TIMING + description: I2S RX timing control register + addressOffset: 88 + size: 32 + fields: + - name: RX_SD_IN_DM + description: "The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: RX_WS_OUT_DM + description: "The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: RX_BCK_OUT_DM + description: "The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: RX_WS_IN_DM + description: "The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: RX_BCK_IN_DM + description: "The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 28 + bitWidth: 2 + access: read-write + - register: + name: TX_TIMING + description: I2S TX timing control register + addressOffset: 92 + size: 32 + fields: + - name: TX_SD_OUT_DM + description: "The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: TX_SD1_OUT_DM + description: "The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: TX_WS_OUT_DM + description: "The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: TX_BCK_OUT_DM + description: "The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TX_WS_IN_DM + description: "The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: TX_BCK_IN_DM + description: "The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 28 + bitWidth: 2 + access: read-write + - register: + name: LC_HUNG_CONF + description: I2S HUNG configure register. + addressOffset: 96 + size: 32 + resetValue: 2064 + fields: + - name: LC_FIFO_TIMEOUT + description: the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: LC_FIFO_TIMEOUT_SHIFT + description: The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + bitOffset: 8 + bitWidth: 3 + access: read-write + - name: LC_FIFO_TIMEOUT_ENA + description: The enable bit for FIFO timeout + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: RXEOF_NUM + description: I2S RX data number control register. + addressOffset: 100 + size: 32 + resetValue: 64 + fields: + - name: RX_EOF_NUM + description: "The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel." + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: CONF_SIGLE_DATA + description: I2S signal data register + addressOffset: 104 + size: 32 + fields: + - name: SINGLE_DATA + description: The configured constant channel data to be sent out. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STATE + description: I2S TX status register + addressOffset: 108 + size: 32 + resetValue: 1 + fields: + - name: TX_IDLE + description: "1: i2s_tx is idle state. 0: i2s_tx is working." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: ETM_CONF + description: I2S ETM configure register + addressOffset: 112 + size: 32 + resetValue: 65600 + fields: + - name: ETM_TX_SEND_WORD_NUM + description: "I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event." + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: ETM_RX_RECEIVE_WORD_NUM + description: "I2S ETM receive x words event. When receiving word number of reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event." + bitOffset: 10 + bitWidth: 10 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 128 + size: 32 + resetValue: 35655792 + fields: + - name: DATE + description: I2S version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: INTERRUPT_CORE0 + description: Interrupt Controller (Core 0) + groupName: INTMTX_CORE0 + baseAddress: 1610678272 + addressBlock: + - offset: 0 + size: 328 + usage: registers + interrupt: + - name: WIFI_MAC + value: 0 + - name: WIFI_MAC_NMI + value: 1 + - name: WIFI_PWR + value: 2 + - name: WIFI_BB + value: 3 + - name: BT_MAC + value: 4 + - name: BT_BB + value: 5 + - name: BT_BB_NMI + value: 6 + - name: LP_TIMER + value: 7 + - name: COEX + value: 8 + - name: BLE_TIMER + value: 9 + - name: BLE_SEC + value: 10 + - name: ZB_MAC + value: 12 + - name: FROM_CPU_INTR0 + value: 22 + - name: FROM_CPU_INTR1 + value: 23 + - name: FROM_CPU_INTR2 + value: 24 + - name: FROM_CPU_INTR3 + value: 25 + - name: CACHE + value: 28 + - name: CPU_PERI_TIMEOUT + value: 29 + registers: + - register: + name: WIFI_MAC_INTR_MAP + description: register description + addressOffset: 0 + size: 32 + fields: + - name: WIFI_MAC_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: WIFI_MAC_NMI_MAP + description: register description + addressOffset: 4 + size: 32 + fields: + - name: WIFI_MAC_NMI_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: WIFI_PWR_INTR_MAP + description: register description + addressOffset: 8 + size: 32 + fields: + - name: WIFI_PWR_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: WIFI_BB_INTR_MAP + description: register description + addressOffset: 12 + size: 32 + fields: + - name: WIFI_BB_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BT_MAC_INTR_MAP + description: register description + addressOffset: 16 + size: 32 + fields: + - name: BT_MAC_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BT_BB_INTR_MAP + description: register description + addressOffset: 20 + size: 32 + fields: + - name: BT_BB_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BT_BB_NMI_MAP + description: register description + addressOffset: 24 + size: 32 + fields: + - name: BT_BB_NMI_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: LP_TIMER_INTR_MAP + description: register description + addressOffset: 28 + size: 32 + fields: + - name: LP_TIMER_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: COEX_INTR_MAP + description: register description + addressOffset: 32 + size: 32 + fields: + - name: COEX_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BLE_TIMER_INTR_MAP + description: register description + addressOffset: 36 + size: 32 + fields: + - name: BLE_TIMER_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BLE_SEC_INTR_MAP + description: register description + addressOffset: 40 + size: 32 + fields: + - name: BLE_SEC_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: I2C_MST_INTR_MAP + description: register description + addressOffset: 44 + size: 32 + fields: + - name: I2C_MST_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: ZB_MAC_INTR_MAP + description: register description + addressOffset: 48 + size: 32 + fields: + - name: ZB_MAC_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PMU_INTR_MAP + description: register description + addressOffset: 52 + size: 32 + fields: + - name: PMU_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: EFUSE_INTR_MAP + description: register description + addressOffset: 56 + size: 32 + fields: + - name: EFUSE_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: LP_RTC_TIMER_INTR_MAP + description: register description + addressOffset: 60 + size: 32 + fields: + - name: LP_RTC_TIMER_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: LP_UART_INTR_MAP + description: register description + addressOffset: 64 + size: 32 + fields: + - name: LP_UART_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: LP_I2C_INTR_MAP + description: register description + addressOffset: 68 + size: 32 + fields: + - name: LP_I2C_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: LP_WDT_INTR_MAP + description: register description + addressOffset: 72 + size: 32 + fields: + - name: LP_WDT_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: LP_PERI_TIMEOUT_INTR_MAP + description: register description + addressOffset: 76 + size: 32 + fields: + - name: LP_PERI_TIMEOUT_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: LP_APM_M0_INTR_MAP + description: register description + addressOffset: 80 + size: 32 + fields: + - name: LP_APM_M0_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: LP_APM_M1_INTR_MAP + description: register description + addressOffset: 84 + size: 32 + fields: + - name: LP_APM_M1_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_0_MAP + description: register description + addressOffset: 88 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_0_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_1_MAP + description: register description + addressOffset: 92 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_1_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_2_MAP + description: register description + addressOffset: 96 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_2_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_3_MAP + description: register description + addressOffset: 100 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_3_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: ASSIST_DEBUG_INTR_MAP + description: register description + addressOffset: 104 + size: 32 + fields: + - name: ASSIST_DEBUG_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TRACE_INTR_MAP + description: register description + addressOffset: 108 + size: 32 + fields: + - name: TRACE_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CACHE_INTR_MAP + description: register description + addressOffset: 112 + size: 32 + fields: + - name: CACHE_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_PERI_TIMEOUT_INTR_MAP + description: register description + addressOffset: 116 + size: 32 + fields: + - name: CPU_PERI_TIMEOUT_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: GPIO_INTERRUPT_PRO_MAP + description: register description + addressOffset: 120 + size: 32 + fields: + - name: GPIO_INTERRUPT_PRO_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: GPIO_INTERRUPT_PRO_NMI_MAP + description: register description + addressOffset: 124 + size: 32 + fields: + - name: GPIO_INTERRUPT_PRO_NMI_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PAU_INTR_MAP + description: register description + addressOffset: 128 + size: 32 + fields: + - name: PAU_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: HP_PERI_TIMEOUT_INTR_MAP + description: register description + addressOffset: 132 + size: 32 + fields: + - name: HP_PERI_TIMEOUT_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: MODEM_PERI_TIMEOUT_INTR_MAP + description: register description + addressOffset: 136 + size: 32 + fields: + - name: MODEM_PERI_TIMEOUT_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: HP_APM_M0_INTR_MAP + description: register description + addressOffset: 140 + size: 32 + fields: + - name: HP_APM_M0_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: HP_APM_M1_INTR_MAP + description: register description + addressOffset: 144 + size: 32 + fields: + - name: HP_APM_M1_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: HP_APM_M2_INTR_MAP + description: register description + addressOffset: 148 + size: 32 + fields: + - name: HP_APM_M2_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: HP_APM_M3_INTR_MAP + description: register description + addressOffset: 152 + size: 32 + fields: + - name: HP_APM_M3_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: LP_APM0_INTR_MAP + description: register description + addressOffset: 156 + size: 32 + fields: + - name: LP_APM0_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: MSPI_INTR_MAP + description: register description + addressOffset: 160 + size: 32 + fields: + - name: MSPI_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: I2S1_INTR_MAP + description: register description + addressOffset: 164 + size: 32 + fields: + - name: I2S1_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: UHCI0_INTR_MAP + description: register description + addressOffset: 168 + size: 32 + fields: + - name: UHCI0_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: UART0_INTR_MAP + description: register description + addressOffset: 172 + size: 32 + fields: + - name: UART0_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: UART1_INTR_MAP + description: register description + addressOffset: 176 + size: 32 + fields: + - name: UART1_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: LEDC_INTR_MAP + description: register description + addressOffset: 180 + size: 32 + fields: + - name: LEDC_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CAN0_INTR_MAP + description: register description + addressOffset: 184 + size: 32 + fields: + - name: CAN0_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CAN1_INTR_MAP + description: register description + addressOffset: 188 + size: 32 + fields: + - name: CAN1_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: USB_INTR_MAP + description: register description + addressOffset: 192 + size: 32 + fields: + - name: USB_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RMT_INTR_MAP + description: register description + addressOffset: 196 + size: 32 + fields: + - name: RMT_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: I2C_EXT0_INTR_MAP + description: register description + addressOffset: 200 + size: 32 + fields: + - name: I2C_EXT0_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG0_T0_INTR_MAP + description: register description + addressOffset: 204 + size: 32 + fields: + - name: TG0_T0_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG0_T1_INTR_MAP + description: register description + addressOffset: 208 + size: 32 + fields: + - name: TG0_T1_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG0_WDT_INTR_MAP + description: register description + addressOffset: 212 + size: 32 + fields: + - name: TG0_WDT_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG1_T0_INTR_MAP + description: register description + addressOffset: 216 + size: 32 + fields: + - name: TG1_T0_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG1_T1_INTR_MAP + description: register description + addressOffset: 220 + size: 32 + fields: + - name: TG1_T1_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG1_WDT_INTR_MAP + description: register description + addressOffset: 224 + size: 32 + fields: + - name: TG1_WDT_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SYSTIMER_TARGET0_INTR_MAP + description: register description + addressOffset: 228 + size: 32 + fields: + - name: SYSTIMER_TARGET0_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SYSTIMER_TARGET1_INTR_MAP + description: register description + addressOffset: 232 + size: 32 + fields: + - name: SYSTIMER_TARGET1_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SYSTIMER_TARGET2_INTR_MAP + description: register description + addressOffset: 236 + size: 32 + fields: + - name: SYSTIMER_TARGET2_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APB_ADC_INTR_MAP + description: register description + addressOffset: 240 + size: 32 + fields: + - name: APB_ADC_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PWM_INTR_MAP + description: register description + addressOffset: 244 + size: 32 + fields: + - name: PWM_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PCNT_INTR_MAP + description: register description + addressOffset: 248 + size: 32 + fields: + - name: PCNT_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PARL_IO_INTR_MAP + description: register description + addressOffset: 252 + size: 32 + fields: + - name: PARL_IO_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SLC0_INTR_MAP + description: register description + addressOffset: 256 + size: 32 + fields: + - name: SLC0_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SLC1_INTR_MAP + description: register description + addressOffset: 260 + size: 32 + fields: + - name: SLC1_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_IN_CH0_INTR_MAP + description: register description + addressOffset: 264 + size: 32 + fields: + - name: DMA_IN_CH0_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_IN_CH1_INTR_MAP + description: register description + addressOffset: 268 + size: 32 + fields: + - name: DMA_IN_CH1_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_IN_CH2_INTR_MAP + description: register description + addressOffset: 272 + size: 32 + fields: + - name: DMA_IN_CH2_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_OUT_CH0_INTR_MAP + description: register description + addressOffset: 276 + size: 32 + fields: + - name: DMA_OUT_CH0_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_OUT_CH1_INTR_MAP + description: register description + addressOffset: 280 + size: 32 + fields: + - name: DMA_OUT_CH1_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_OUT_CH2_INTR_MAP + description: register description + addressOffset: 284 + size: 32 + fields: + - name: DMA_OUT_CH2_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: GPSPI2_INTR_MAP + description: register description + addressOffset: 288 + size: 32 + fields: + - name: GPSPI2_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: AES_INTR_MAP + description: register description + addressOffset: 292 + size: 32 + fields: + - name: AES_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SHA_INTR_MAP + description: register description + addressOffset: 296 + size: 32 + fields: + - name: SHA_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RSA_INTR_MAP + description: register description + addressOffset: 300 + size: 32 + fields: + - name: RSA_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: ECC_INTR_MAP + description: register description + addressOffset: 304 + size: 32 + fields: + - name: ECC_INTR_MAP + description: Need add description + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: INTR_STATUS_REG_0 + description: register description + addressOffset: 308 + size: 32 + fields: + - name: INTR_STATUS_0 + description: Need add description + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INTR_STATUS_REG_1 + description: register description + addressOffset: 312 + size: 32 + fields: + - name: INTR_STATUS_1 + description: Need add description + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INT_STATUS_REG_2 + description: register description + addressOffset: 316 + size: 32 + fields: + - name: INT_STATUS_2 + description: Need add description + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CLOCK_GATE + description: register description + addressOffset: 320 + size: 32 + resetValue: 1 + fields: + - name: REG_CLK_EN + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: INTERRUPT_REG_DATE + description: register description + addressOffset: 2044 + size: 32 + resetValue: 35664144 + fields: + - name: INTERRUPT_REG_DATE + description: Need add description + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: INTPRI + description: INTPRI Peripheral + groupName: INTPRI + baseAddress: 1611419648 + addressBlock: + - offset: 0 + size: 184 + usage: registers + registers: + - register: + name: CPU_INT_ENABLE + description: register description + addressOffset: 0 + size: 32 + fields: + - name: CPU_INT_ENABLE + description: Need add description + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CPU_INT_TYPE + description: register description + addressOffset: 4 + size: 32 + fields: + - name: CPU_INT_TYPE + description: Need add description + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CPU_INT_EIP_STATUS + description: register description + addressOffset: 8 + size: 32 + fields: + - name: CPU_INT_EIP_STATUS + description: Need add description + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CPU_INT_PRI_0 + description: register description + addressOffset: 12 + size: 32 + fields: + - name: CPU_PRI_0_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_1 + description: register description + addressOffset: 16 + size: 32 + fields: + - name: CPU_PRI_1_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_2 + description: register description + addressOffset: 20 + size: 32 + fields: + - name: CPU_PRI_2_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_3 + description: register description + addressOffset: 24 + size: 32 + fields: + - name: CPU_PRI_3_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_4 + description: register description + addressOffset: 28 + size: 32 + fields: + - name: CPU_PRI_4_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_5 + description: register description + addressOffset: 32 + size: 32 + fields: + - name: CPU_PRI_5_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_6 + description: register description + addressOffset: 36 + size: 32 + fields: + - name: CPU_PRI_6_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_7 + description: register description + addressOffset: 40 + size: 32 + fields: + - name: CPU_PRI_7_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_8 + description: register description + addressOffset: 44 + size: 32 + fields: + - name: CPU_PRI_8_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_9 + description: register description + addressOffset: 48 + size: 32 + fields: + - name: CPU_PRI_9_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_10 + description: register description + addressOffset: 52 + size: 32 + fields: + - name: CPU_PRI_10_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_11 + description: register description + addressOffset: 56 + size: 32 + fields: + - name: CPU_PRI_11_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_12 + description: register description + addressOffset: 60 + size: 32 + fields: + - name: CPU_PRI_12_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_13 + description: register description + addressOffset: 64 + size: 32 + fields: + - name: CPU_PRI_13_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_14 + description: register description + addressOffset: 68 + size: 32 + fields: + - name: CPU_PRI_14_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_15 + description: register description + addressOffset: 72 + size: 32 + fields: + - name: CPU_PRI_15_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_16 + description: register description + addressOffset: 76 + size: 32 + fields: + - name: CPU_PRI_16_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_17 + description: register description + addressOffset: 80 + size: 32 + fields: + - name: CPU_PRI_17_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_18 + description: register description + addressOffset: 84 + size: 32 + fields: + - name: CPU_PRI_18_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_19 + description: register description + addressOffset: 88 + size: 32 + fields: + - name: CPU_PRI_19_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_20 + description: register description + addressOffset: 92 + size: 32 + fields: + - name: CPU_PRI_20_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_21 + description: register description + addressOffset: 96 + size: 32 + fields: + - name: CPU_PRI_21_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_22 + description: register description + addressOffset: 100 + size: 32 + fields: + - name: CPU_PRI_22_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_23 + description: register description + addressOffset: 104 + size: 32 + fields: + - name: CPU_PRI_23_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_24 + description: register description + addressOffset: 108 + size: 32 + fields: + - name: CPU_PRI_24_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_25 + description: register description + addressOffset: 112 + size: 32 + fields: + - name: CPU_PRI_25_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_26 + description: register description + addressOffset: 116 + size: 32 + fields: + - name: CPU_PRI_26_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_27 + description: register description + addressOffset: 120 + size: 32 + fields: + - name: CPU_PRI_27_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_28 + description: register description + addressOffset: 124 + size: 32 + fields: + - name: CPU_PRI_28_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_29 + description: register description + addressOffset: 128 + size: 32 + fields: + - name: CPU_PRI_29_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_30 + description: register description + addressOffset: 132 + size: 32 + fields: + - name: CPU_PRI_30_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_31 + description: register description + addressOffset: 136 + size: 32 + fields: + - name: CPU_PRI_31_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_THRESH + description: register description + addressOffset: 140 + size: 32 + fields: + - name: CPU_INT_THRESH + description: Need add description + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_0 + description: register description + addressOffset: 144 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_0 + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_1 + description: register description + addressOffset: 148 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_1 + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_2 + description: register description + addressOffset: 152 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_2 + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_3 + description: register description + addressOffset: 156 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_3 + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: register description + addressOffset: 160 + size: 32 + resetValue: 35655824 + fields: + - name: DATE + description: Need add description + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + name: CLOCK_GATE + description: register description + addressOffset: 164 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INT_CLEAR + description: register description + addressOffset: 168 + size: 32 + fields: + - name: CPU_INT_CLEAR + description: Need add description + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RND_ECO + description: redcy eco register. + addressOffset: 172 + size: 32 + fields: + - name: REDCY_ENA + description: Only reserved for ECO. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REDCY_RESULT + description: Only reserved for ECO. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: RND_ECO_LOW + description: redcy eco low register. + addressOffset: 176 + size: 32 + fields: + - name: REDCY_LOW + description: Only reserved for ECO. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RND_ECO_HIGH + description: redcy eco high register. + addressOffset: 1020 + size: 32 + resetValue: 4294967295 + fields: + - name: REDCY_HIGH + description: Only reserved for ECO. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: IO_MUX + description: Input/Output Multiplexer + groupName: IO_MUX + baseAddress: 1611202560 + addressBlock: + - offset: 0 + size: 136 + usage: registers + registers: + - register: + name: PIN_CTRL + description: Clock Output Configuration Register + addressOffset: 0 + size: 32 + resetValue: 7663 + fields: + - name: CLK_OUT1 + description: "If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals." + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: CLK_OUT2 + description: "If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals." + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: CLK_OUT3 + description: "If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals." + bitOffset: 10 + bitWidth: 5 + access: read-write + - register: + dim: 31 + dimIncrement: 4 + name: GPIO%s + description: IO MUX Configure Register for pad XTAL_32K_P + addressOffset: 4 + size: 32 + resetValue: 2048 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: "Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA." + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled. 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: MODEM_DIAG_EN + description: GPIO MATRIX Configure Register for modem diag + addressOffset: 188 + size: 32 + fields: + - name: MODEM_DIAG_EN + description: "bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i] into gpio matrix. 0:enable other signals into gpio matrix" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DATE + description: IO MUX Version Control Register + addressOffset: 252 + size: 32 + resetValue: 35655776 + fields: + - name: REG_DATE + description: Version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: LEDC + description: LED Control PWM (Pulse Width Modulation) + groupName: LEDC + baseAddress: 1610641408 + addressBlock: + - offset: 0 + size: 340 + usage: registers + interrupt: + - name: LEDC + value: 45 + registers: + - register: + dim: 6 + dimIncrement: 20 + name: CH%s_CONF0 + description: Configuration register 0 for channel %s + addressOffset: 0 + size: 32 + fields: + - name: TIMER_SEL + description: "This field is used to select one of timers for channel %s.\n\n0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SIG_OUT_EN + description: Set this bit to enable signal output on channel %s. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IDLE_LV + description: This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0). + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PARA_UP + description: "This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware." + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: OVF_NUM + description: "This register is used to configure the maximum times of overflow minus 1.\n\nThe LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times." + bitOffset: 5 + bitWidth: 10 + access: read-write + - name: OVF_CNT_EN + description: This bit is used to enable the ovf_cnt of channel %s. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: OVF_CNT_RESET + description: Set this bit to reset the ovf_cnt of channel %s. + bitOffset: 16 + bitWidth: 1 + access: write-only + - register: + dim: 6 + dimIncrement: 20 + name: CH%s_HPOINT + description: High point register for channel %s + addressOffset: 4 + size: 32 + fields: + - name: HPOINT + description: The output value changes to high when the selected timers has reached the value specified by this register. + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + dim: 6 + dimIncrement: 20 + name: CH%s_DUTY + description: Initial duty cycle for channel %s + addressOffset: 8 + size: 32 + fields: + - name: DUTY + description: "This register is used to change the output duty by controlling the Lpoint.\n\nThe output value turns to low when the selected timers has reached the Lpoint." + bitOffset: 0 + bitWidth: 25 + access: read-write + - register: + dim: 6 + dimIncrement: 20 + name: CH%s_CONF1 + description: Configuration register 1 for channel %s + addressOffset: 12 + size: 32 + fields: + - name: DUTY_START + description: Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + dim: 6 + dimIncrement: 20 + name: CH%s_DUTY_R + description: Current duty cycle for channel %s + addressOffset: 16 + size: 32 + fields: + - name: DUTY_CH_R + description: This register stores the current duty of output signal on channel %s. + bitOffset: 0 + bitWidth: 25 + access: read-only + - register: + dim: 4 + dimIncrement: 8 + name: TIMER%s_CONF + description: Timer %s configuration + addressOffset: 160 + size: 32 + resetValue: 16777216 + fields: + - name: DUTY_RES + description: This register is used to control the range of the counter in timer %s. + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: CLK_DIV + description: "This register is used to configure the divisor for the divider in timer %s.\n\nThe least significant eight bits represent the fractional part." + bitOffset: 5 + bitWidth: 18 + access: read-write + - name: PAUSE + description: This bit is used to suspend the counter in timer %s. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: RST + description: This bit is used to reset timer %s. The counter will show 0 after reset. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TICK_SEL + description: "This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate.\n\n1'h0: SLOW_CLK 1'h1: REF_TICK" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PARA_UP + description: Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES. + bitOffset: 26 + bitWidth: 1 + access: write-only + - register: + dim: 4 + dimIncrement: 8 + name: TIMER%s_VALUE + description: Timer %s current counter value + addressOffset: 164 + size: 32 + fields: + - name: TIMER_CNT + description: This register stores the current counter value of timer %s. + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 192 + size: 32 + fields: + - name: TIMER0_OVF_INT_RAW + description: Triggered when the timer0 has reached its maximum counter value. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMER1_OVF_INT_RAW + description: Triggered when the timer1 has reached its maximum counter value. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER2_OVF_INT_RAW + description: Triggered when the timer2 has reached its maximum counter value. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TIMER3_OVF_INT_RAW + description: Triggered when the timer3 has reached its maximum counter value. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH0_INT_RAW + description: Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH1_INT_RAW + description: Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH2_INT_RAW + description: Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH3_INT_RAW + description: Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH4_INT_RAW + description: Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH5_INT_RAW + description: Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH0_INT_RAW + description: Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH1_INT_RAW + description: Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH2_INT_RAW + description: Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH3_INT_RAW + description: Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH4_INT_RAW + description: Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH5_INT_RAW + description: Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 196 + size: 32 + fields: + - name: TIMER0_OVF_INT_ST + description: This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TIMER1_OVF_INT_ST + description: This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TIMER2_OVF_INT_ST + description: This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TIMER3_OVF_INT_ST + description: This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH0_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH1_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH2_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH3_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH4_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH5_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH0_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH1_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH2_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH3_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH4_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH5_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + bitOffset: 17 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 200 + size: 32 + fields: + - name: TIMER0_OVF_INT_ENA + description: The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMER1_OVF_INT_ENA + description: The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER2_OVF_INT_ENA + description: The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TIMER3_OVF_INT_ENA + description: The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH0_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH1_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH2_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH3_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH4_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH5_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH0_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH1_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH2_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH3_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH4_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH5_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 204 + size: 32 + fields: + - name: TIMER0_OVF_INT_CLR + description: Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TIMER1_OVF_INT_CLR + description: Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TIMER2_OVF_INT_CLR + description: Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TIMER3_OVF_INT_CLR + description: Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH0_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH1_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH2_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH3_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH4_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH5_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH0_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH1_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH2_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH3_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH4_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH5_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - register: + dim: 6 + dimIncrement: 16 + name: CH%s_GAMMA_WR + description: Ledc ch%s gamma ram write register. + addressOffset: 256 + size: 32 + fields: + - name: CH_GAMMA_DUTY_INC + description: "Ledc ch%s gamma duty inc of current ram write address.This register is used to increase or decrease the duty of output signal on channel %s. \n\n1: Increase 0: Decrease." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CH_GAMMA_DUTY_CYCLE + description: Ledc ch%s gamma duty cycle of current ram write address.The duty will change every LEDC_CH%s_GAMMA_DUTY_CYCLE on channel %s. + bitOffset: 1 + bitWidth: 10 + access: read-write + - name: CH_GAMMA_SCALE + description: Ledc ch%s gamma scale of current ram write address.This register is used to configure the changing step scale of duty on channel %s. + bitOffset: 11 + bitWidth: 10 + access: read-write + - name: CH_GAMMA_DUTY_NUM + description: Ledc ch%s gamma duty num of current ram write address.This register is used to control the number of times the duty cycle will be changed. + bitOffset: 21 + bitWidth: 10 + access: read-write + - register: + dim: 6 + dimIncrement: 16 + name: CH%s_GAMMA_WR_ADDR + description: Ledc ch%s gamma ram write address register. + addressOffset: 260 + size: 32 + fields: + - name: CH_GAMMA_WR_ADDR + description: Ledc ch%s gamma ram write address. + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + dim: 6 + dimIncrement: 16 + name: CH%s_GAMMA_RD_ADDR + description: Ledc ch%s gamma ram read address register. + addressOffset: 264 + size: 32 + fields: + - name: CH_GAMMA_RD_ADDR + description: Ledc ch%s gamma ram read address. + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + dim: 6 + dimIncrement: 16 + name: CH%s_GAMMA_RD_DATA + description: Ledc ch%s gamma ram read data register. + addressOffset: 268 + size: 32 + fields: + - name: CH_GAMMA_RD_DATA + description: Ledc ch%s gamma ram read data. + bitOffset: 0 + bitWidth: 31 + access: read-only + - register: + dim: 6 + dimIncrement: 4 + name: CH%s_GAMMA_CONF + description: Ledc ch%s gamma config register. + addressOffset: 384 + size: 32 + fields: + - name: CH_GAMMA_ENTRY_NUM + description: Ledc ch%s gamma entry num. + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: CH_GAMMA_PAUSE + description: "Ledc ch%s gamma pause, write 1 to pause." + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CH_GAMMA_RESUME + description: "Ledc ch%s gamma resume, write 1 to resume." + bitOffset: 6 + bitWidth: 1 + access: write-only + - register: + name: EVT_TASK_EN0 + description: Ledc event task enable bit register0. + addressOffset: 416 + size: 32 + fields: + - name: EVT_DUTY_CHNG_END_CH0_EN + description: "Ledc ch0 duty change end event enable register, write 1 to enable this event." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EVT_DUTY_CHNG_END_CH1_EN + description: "Ledc ch1 duty change end event enable register, write 1 to enable this event." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EVT_DUTY_CHNG_END_CH2_EN + description: "Ledc ch2 duty change end event enable register, write 1 to enable this event." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EVT_DUTY_CHNG_END_CH3_EN + description: "Ledc ch3 duty change end event enable register, write 1 to enable this event." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: EVT_DUTY_CHNG_END_CH4_EN + description: "Ledc ch4 duty change end event enable register, write 1 to enable this event." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: EVT_DUTY_CHNG_END_CH5_EN + description: "Ledc ch5 duty change end event enable register, write 1 to enable this event." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: EVT_OVF_CNT_PLS_CH0_EN + description: "Ledc ch0 overflow count pulse event enable register, write 1 to enable this event." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: EVT_OVF_CNT_PLS_CH1_EN + description: "Ledc ch1 overflow count pulse event enable register, write 1 to enable this event." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: EVT_OVF_CNT_PLS_CH2_EN + description: "Ledc ch2 overflow count pulse event enable register, write 1 to enable this event." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: EVT_OVF_CNT_PLS_CH3_EN + description: "Ledc ch3 overflow count pulse event enable register, write 1 to enable this event." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: EVT_OVF_CNT_PLS_CH4_EN + description: "Ledc ch4 overflow count pulse event enable register, write 1 to enable this event." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: EVT_OVF_CNT_PLS_CH5_EN + description: "Ledc ch5 overflow count pulse event enable register, write 1 to enable this event." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: EVT_TIME_OVF_TIMER0_EN + description: "Ledc timer0 overflow event enable register, write 1 to enable this event." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: EVT_TIME_OVF_TIMER1_EN + description: "Ledc timer1 overflow event enable register, write 1 to enable this event." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: EVT_TIME_OVF_TIMER2_EN + description: "Ledc timer2 overflow event enable register, write 1 to enable this event." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: EVT_TIME_OVF_TIMER3_EN + description: "Ledc timer3 overflow event enable register, write 1 to enable this event." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: EVT_TIME0_CMP_EN + description: "Ledc timer0 compare event enable register, write 1 to enable this event." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: EVT_TIME1_CMP_EN + description: "Ledc timer1 compare event enable register, write 1 to enable this event." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: EVT_TIME2_CMP_EN + description: "Ledc timer2 compare event enable register, write 1 to enable this event." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: EVT_TIME3_CMP_EN + description: "Ledc timer3 compare event enable register, write 1 to enable this event." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TASK_DUTY_SCALE_UPDATE_CH0_EN + description: "Ledc ch0 duty scale update task enable register, write 1 to enable this task." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TASK_DUTY_SCALE_UPDATE_CH1_EN + description: "Ledc ch1 duty scale update task enable register, write 1 to enable this task." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TASK_DUTY_SCALE_UPDATE_CH2_EN + description: "Ledc ch2 duty scale update task enable register, write 1 to enable this task." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TASK_DUTY_SCALE_UPDATE_CH3_EN + description: "Ledc ch3 duty scale update task enable register, write 1 to enable this task." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: TASK_DUTY_SCALE_UPDATE_CH4_EN + description: "Ledc ch4 duty scale update task enable register, write 1 to enable this task." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: TASK_DUTY_SCALE_UPDATE_CH5_EN + description: "Ledc ch5 duty scale update task enable register, write 1 to enable this task." + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: EVT_TASK_EN1 + description: Ledc event task enable bit register1. + addressOffset: 420 + size: 32 + fields: + - name: TASK_TIMER0_RES_UPDATE_EN + description: "Ledc timer0 res update task enable register, write 1 to enable this task." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TASK_TIMER1_RES_UPDATE_EN + description: "Ledc timer1 res update task enable register, write 1 to enable this task." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TASK_TIMER2_RES_UPDATE_EN + description: "Ledc timer2 res update task enable register, write 1 to enable this task." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TASK_TIMER3_RES_UPDATE_EN + description: "Ledc timer3 res update task enable register, write 1 to enable this task." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TASK_TIMER0_CAP_EN + description: "Ledc timer0 capture task enable register, write 1 to enable this task." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TASK_TIMER1_CAP_EN + description: "Ledc timer1 capture task enable register, write 1 to enable this task." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TASK_TIMER2_CAP_EN + description: "Ledc timer2 capture task enable register, write 1 to enable this task." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TASK_TIMER3_CAP_EN + description: "Ledc timer3 capture task enable register, write 1 to enable this task." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TASK_SIG_OUT_DIS_CH0_EN + description: "Ledc ch0 signal out disable task enable register, write 1 to enable this task." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TASK_SIG_OUT_DIS_CH1_EN + description: "Ledc ch1 signal out disable task enable register, write 1 to enable this task." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TASK_SIG_OUT_DIS_CH2_EN + description: "Ledc ch2 signal out disable task enable register, write 1 to enable this task." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TASK_SIG_OUT_DIS_CH3_EN + description: "Ledc ch3 signal out disable task enable register, write 1 to enable this task." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TASK_SIG_OUT_DIS_CH4_EN + description: "Ledc ch4 signal out disable task enable register, write 1 to enable this task." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TASK_SIG_OUT_DIS_CH5_EN + description: "Ledc ch5 signal out disable task enable register, write 1 to enable this task." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TASK_OVF_CNT_RST_CH0_EN + description: "Ledc ch0 overflow count reset task enable register, write 1 to enable this task." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: TASK_OVF_CNT_RST_CH1_EN + description: "Ledc ch1 overflow count reset task enable register, write 1 to enable this task." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: TASK_OVF_CNT_RST_CH2_EN + description: "Ledc ch2 overflow count reset task enable register, write 1 to enable this task." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TASK_OVF_CNT_RST_CH3_EN + description: "Ledc ch3 overflow count reset task enable register, write 1 to enable this task." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: TASK_OVF_CNT_RST_CH4_EN + description: "Ledc ch4 overflow count reset task enable register, write 1 to enable this task." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TASK_OVF_CNT_RST_CH5_EN + description: "Ledc ch5 overflow count reset task enable register, write 1 to enable this task." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: TASK_TIMER0_RST_EN + description: "Ledc timer0 reset task enable register, write 1 to enable this task." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TASK_TIMER1_RST_EN + description: "Ledc timer1 reset task enable register, write 1 to enable this task." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TASK_TIMER2_RST_EN + description: "Ledc timer2 reset task enable register, write 1 to enable this task." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TASK_TIMER3_RST_EN + description: "Ledc timer3 reset task enable register, write 1 to enable this task." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: TASK_TIMER0_PAUSE_RESUME_EN + description: "Ledc timer0 pause resume task enable register, write 1 to enable this task." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: TASK_TIMER1_PAUSE_RESUME_EN + description: "Ledc timer1 pause resume task enable register, write 1 to enable this task." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TASK_TIMER2_PAUSE_RESUME_EN + description: "Ledc timer2 pause resume task enable register, write 1 to enable this task." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TASK_TIMER3_PAUSE_RESUME_EN + description: "Ledc timer3 pause resume task enable register, write 1 to enable this task." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EVT_TASK_EN2 + description: Ledc event task enable bit register2. + addressOffset: 424 + size: 32 + fields: + - name: TASK_GAMMA_RESTART_CH0_EN + description: "Ledc ch0 gamma restart task enable register, write 1 to enable this task." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESTART_CH1_EN + description: "Ledc ch1 gamma restart task enable register, write 1 to enable this task." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESTART_CH2_EN + description: "Ledc ch2 gamma restart task enable register, write 1 to enable this task." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESTART_CH3_EN + description: "Ledc ch3 gamma restart task enable register, write 1 to enable this task." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESTART_CH4_EN + description: "Ledc ch4 gamma restart task enable register, write 1 to enable this task." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESTART_CH5_EN + description: "Ledc ch5 gamma restart task enable register, write 1 to enable this task." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_PAUSE_CH0_EN + description: "Ledc ch0 gamma pause task enable register, write 1 to enable this task." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_PAUSE_CH1_EN + description: "Ledc ch1 gamma pause task enable register, write 1 to enable this task." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_PAUSE_CH2_EN + description: "Ledc ch2 gamma pause task enable register, write 1 to enable this task." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_PAUSE_CH3_EN + description: "Ledc ch3 gamma pause task enable register, write 1 to enable this task." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_PAUSE_CH4_EN + description: "Ledc ch4 gamma pause task enable register, write 1 to enable this task." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_PAUSE_CH5_EN + description: "Ledc ch5 gamma pause task enable register, write 1 to enable this task." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESUME_CH0_EN + description: "Ledc ch0 gamma resume task enable register, write 1 to enable this task." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESUME_CH1_EN + description: "Ledc ch1 gamma resume task enable register, write 1 to enable this task." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESUME_CH2_EN + description: "Ledc ch2 gamma resume task enable register, write 1 to enable this task." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESUME_CH3_EN + description: "Ledc ch3 gamma resume task enable register, write 1 to enable this task." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESUME_CH4_EN + description: "Ledc ch4 gamma resume task enable register, write 1 to enable this task." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESUME_CH5_EN + description: "Ledc ch5 gamma resume task enable register, write 1 to enable this task." + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: TIMER%s_CMP + description: Ledc timer%s compare value register. + addressOffset: 432 + size: 32 + fields: + - name: TIMER_CMP + description: This register stores ledc timer%s compare value. + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: TIMER%s_CNT_CAP + description: Ledc timer%s count value capture register. + addressOffset: 448 + size: 32 + fields: + - name: TIMER_CNT_CAP + description: This register stores ledc timer%s count value. + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: CONF + description: Global ledc configuration register + addressOffset: 496 + size: 32 + fields: + - name: APB_CLK_SEL + description: "This bit is used to select clock source for the 4 timers .\n\n2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: GAMMA_RAM_CLK_EN_CH0 + description: "This bit is used to control clock.\n\n1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: GAMMA_RAM_CLK_EN_CH1 + description: "This bit is used to control clock.\n\n1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: GAMMA_RAM_CLK_EN_CH2 + description: "This bit is used to control clock.\n\n1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: GAMMA_RAM_CLK_EN_CH3 + description: "This bit is used to control clock.\n\n1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: GAMMA_RAM_CLK_EN_CH4 + description: "This bit is used to control clock.\n\n1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: GAMMA_RAM_CLK_EN_CH5 + description: "This bit is used to control clock.\n\n1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "This bit is used to control clock.\n\n1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 508 + size: 32 + resetValue: 34672976 + fields: + - name: LEDC_DATE + description: This is the version control register. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: LP_PERI + description: LP_PERI Peripheral + groupName: LPPERI + baseAddress: 1611343872 + addressBlock: + - offset: 0 + size: 40 + usage: registers + interrupt: + - name: LP_PERI_TIMEOUT + value: 19 + registers: + - register: + name: CLK_EN + description: need_des + addressOffset: 0 + size: 32 + resetValue: 2139095040 + fields: + - name: LP_TOUCH_CK_EN + description: need_des + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: RNG_CK_EN + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: OTP_DBG_CK_EN + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LP_UART_CK_EN + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LP_IO_CK_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LP_EXT_I2C_CK_EN + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_ANA_I2C_CK_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: EFUSE_CK_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_CPU_CK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RESET_EN + description: need_des + addressOffset: 4 + size: 32 + fields: + - name: BUS_RESET_EN + description: need_des + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: LP_TOUCH_RESET_EN + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: OTP_DBG_RESET_EN + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LP_UART_RESET_EN + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LP_IO_RESET_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LP_EXT_I2C_RESET_EN + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_ANA_I2C_RESET_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: EFUSE_RESET_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_CPU_RESET_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: RNG_DATA + description: need_des + addressOffset: 8 + size: 32 + fields: + - name: RND_DATA + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CPU + description: need_des + addressOffset: 12 + size: 32 + resetValue: 2147483648 + fields: + - name: LPCORE_DBGM_UNAVALIABLE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: BUS_TIMEOUT + description: need_des + addressOffset: 16 + size: 32 + resetValue: 3221209088 + fields: + - name: LP_PERI_TIMEOUT_THRES + description: need_des + bitOffset: 14 + bitWidth: 16 + access: read-write + - name: LP_PERI_TIMEOUT_INT_CLEAR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: LP_PERI_TIMEOUT_PROTECT_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: BUS_TIMEOUT_ADDR + description: need_des + addressOffset: 20 + size: 32 + fields: + - name: LP_PERI_TIMEOUT_ADDR + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BUS_TIMEOUT_UID + description: need_des + addressOffset: 24 + size: 32 + fields: + - name: LP_PERI_TIMEOUT_UID + description: need_des + bitOffset: 0 + bitWidth: 7 + access: read-only + - register: + name: MEM_CTRL + description: need_des + addressOffset: 28 + size: 32 + resetValue: 2147483648 + fields: + - name: UART_WAKEUP_FLAG_CLR + description: need_des + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: UART_WAKEUP_FLAG + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UART_WAKEUP_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: UART_MEM_FORCE_PD + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: UART_MEM_FORCE_PU + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INTERRUPT_SOURCE + description: need_des + addressOffset: 32 + size: 32 + fields: + - name: LP_INTERRUPT_SOURCE + description: "BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, lp_io_int" + bitOffset: 0 + bitWidth: 6 + access: read-only + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 35676464 + fields: + - name: LPPERI_DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: LP_ANA + description: LP_ANA Peripheral + groupName: LP_ANA + baseAddress: 1611344896 + addressBlock: + - offset: 0 + size: 52 + usage: registers + registers: + - register: + name: BOD_MODE0_CNTL + description: need_des + addressOffset: 0 + size: 32 + resetValue: 268173568 + fields: + - name: BOD_MODE0_CLOSE_FLASH_ENA + description: need_des + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BOD_MODE0_PD_RF_ENA + description: need_des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: BOD_MODE0_INTR_WAIT + description: need_des + bitOffset: 8 + bitWidth: 10 + access: read-write + - name: BOD_MODE0_RESET_WAIT + description: need_des + bitOffset: 18 + bitWidth: 10 + access: read-write + - name: BOD_MODE0_CNT_CLR + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: BOD_MODE0_INTR_ENA + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: BOD_MODE0_RESET_SEL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: BOD_MODE0_RESET_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: BOD_MODE1_CNTL + description: need_des + addressOffset: 4 + size: 32 + fields: + - name: BOD_MODE1_RESET_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CK_GLITCH_CNTL + description: need_des + addressOffset: 8 + size: 32 + fields: + - name: CK_GLITCH_RESET_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: FIB_ENABLE + description: need_des + addressOffset: 12 + size: 32 + resetValue: 4294967295 + fields: + - name: ANA_FIB_ENA + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: INT_RAW + description: need_des + addressOffset: 16 + size: 32 + fields: + - name: BOD_MODE0_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: need_des + addressOffset: 20 + size: 32 + fields: + - name: BOD_MODE0_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: need_des + addressOffset: 24 + size: 32 + fields: + - name: BOD_MODE0_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: need_des + addressOffset: 28 + size: 32 + fields: + - name: BOD_MODE0_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: LP_INT_RAW + description: need_des + addressOffset: 32 + size: 32 + fields: + - name: BOD_MODE0_LP_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_INT_ST + description: need_des + addressOffset: 36 + size: 32 + fields: + - name: BOD_MODE0_LP_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: LP_INT_ENA + description: need_des + addressOffset: 40 + size: 32 + fields: + - name: BOD_MODE0_LP_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_INT_CLR + description: need_des + addressOffset: 44 + size: 32 + fields: + - name: BOD_MODE0_LP_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 35660384 + fields: + - name: LP_ANA_DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: LP_AON + description: LP_AON Peripheral + groupName: LP_AON + baseAddress: 1611337728 + addressBlock: + - offset: 0 + size: 92 + usage: registers + registers: + - register: + name: STORE0 + description: need_des + addressOffset: 0 + size: 32 + fields: + - name: LP_AON_STORE0 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE1 + description: need_des + addressOffset: 4 + size: 32 + fields: + - name: LP_AON_STORE1 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE2 + description: need_des + addressOffset: 8 + size: 32 + fields: + - name: LP_AON_STORE2 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE3 + description: need_des + addressOffset: 12 + size: 32 + fields: + - name: LP_AON_STORE3 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE4 + description: need_des + addressOffset: 16 + size: 32 + fields: + - name: LP_AON_STORE4 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE5 + description: need_des + addressOffset: 20 + size: 32 + fields: + - name: LP_AON_STORE5 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE6 + description: need_des + addressOffset: 24 + size: 32 + fields: + - name: LP_AON_STORE6 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE7 + description: need_des + addressOffset: 28 + size: 32 + fields: + - name: LP_AON_STORE7 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE8 + description: need_des + addressOffset: 32 + size: 32 + fields: + - name: LP_AON_STORE8 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE9 + description: need_des + addressOffset: 36 + size: 32 + fields: + - name: LP_AON_STORE9 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: GPIO_MUX + description: need_des + addressOffset: 40 + size: 32 + fields: + - name: SEL + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: GPIO_HOLD0 + description: need_des + addressOffset: 44 + size: 32 + fields: + - name: GPIO_HOLD0 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: GPIO_HOLD1 + description: need_des + addressOffset: 48 + size: 32 + fields: + - name: GPIO_HOLD1 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SYS_CFG + description: need_des + addressOffset: 52 + size: 32 + fields: + - name: FORCE_DOWNLOAD_BOOT + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HPSYS_SW_RESET + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: CPUCORE0_CFG + description: need_des + addressOffset: 56 + size: 32 + resetValue: 1073741824 + fields: + - name: CPU_CORE0_SW_STALL + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CPU_CORE0_SW_RESET + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: CPU_CORE0_OCD_HALT_ON_RESET + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CPU_CORE0_STAT_VECTOR_SEL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CPU_CORE0_DRESET_MASK + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: IO_MUX + description: need_des + addressOffset: 60 + size: 32 + fields: + - name: RESET_DISABLE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EXT_WAKEUP_CNTL + description: need_des + addressOffset: 64 + size: 32 + fields: + - name: EXT_WAKEUP_STATUS + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: EXT_WAKEUP_STATUS_CLR + description: need_des + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: EXT_WAKEUP_SEL + description: need_des + bitOffset: 15 + bitWidth: 8 + access: read-write + - name: EXT_WAKEUP_LV + description: need_des + bitOffset: 23 + bitWidth: 8 + access: read-write + - name: EXT_WAKEUP_FILTER + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USB + description: need_des + addressOffset: 68 + size: 32 + fields: + - name: RESET_DISABLE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LPBUS + description: need_des + addressOffset: 72 + size: 32 + resetValue: 2954887168 + fields: + - name: FAST_MEM_WPULSE + description: This field controls fast memory WPULSE parameter. + bitOffset: 16 + bitWidth: 3 + access: read-write + - name: FAST_MEM_WA + description: This field controls fast memory WA parameter. + bitOffset: 19 + bitWidth: 3 + access: read-write + - name: FAST_MEM_RA + description: This field controls fast memory RA parameter. + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: FAST_MEM_MUX_FSM_IDLE + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: FAST_MEM_MUX_SEL_STATUS + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: FAST_MEM_MUX_SEL_UPDATE + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: FAST_MEM_MUX_SEL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SDIO_ACTIVE + description: need_des + addressOffset: 76 + size: 32 + resetValue: 41943040 + fields: + - name: SDIO_ACT_DNUM + description: need_des + bitOffset: 22 + bitWidth: 10 + access: read-write + - register: + name: LPCORE + description: need_des + addressOffset: 80 + size: 32 + fields: + - name: ETM_WAKEUP_FLAG_CLR + description: need_des + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ETM_WAKEUP_FLAG + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DISABLE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAR_CCT + description: need_des + addressOffset: 84 + size: 32 + fields: + - name: SAR2_PWDET_CCT + description: need_des + bitOffset: 29 + bitWidth: 3 + access: read-write + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 35672704 + fields: + - name: DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: LP_APM + description: Low-power Access Permission Management Controller + groupName: LP_APM + baseAddress: 1611347968 + addressBlock: + - offset: 0 + size: 100 + usage: registers + interrupt: + - name: LP_APM_M0 + value: 20 + - name: LP_APM_M1 + value: 21 + - name: LP_APM0 + value: 39 + registers: + - register: + name: REGION_FILTER_EN + description: Region filter enable register + addressOffset: 0 + size: 32 + resetValue: 1 + fields: + - name: REGION_FILTER_EN + description: Region filter enable + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: REGION0_ADDR_START + description: Region address register + addressOffset: 4 + size: 32 + fields: + - name: REGION0_ADDR_START + description: Start address of region0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION0_ADDR_END + description: Region address register + addressOffset: 8 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION0_ADDR_END + description: End address of region0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION0_PMS_ATTR + description: Region access authority attribute register + addressOffset: 12 + size: 32 + fields: + - name: REGION0_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION0_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION0_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION0_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION0_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION0_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION0_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION0_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION0_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION1_ADDR_START + description: Region address register + addressOffset: 16 + size: 32 + fields: + - name: REGION1_ADDR_START + description: Start address of region1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION1_ADDR_END + description: Region address register + addressOffset: 20 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION1_ADDR_END + description: End address of region1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION1_PMS_ATTR + description: Region access authority attribute register + addressOffset: 24 + size: 32 + fields: + - name: REGION1_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION1_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION1_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION1_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION1_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION1_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION1_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION1_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION1_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION2_ADDR_START + description: Region address register + addressOffset: 28 + size: 32 + fields: + - name: REGION2_ADDR_START + description: Start address of region2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION2_ADDR_END + description: Region address register + addressOffset: 32 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION2_ADDR_END + description: End address of region2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION2_PMS_ATTR + description: Region access authority attribute register + addressOffset: 36 + size: 32 + fields: + - name: REGION2_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION2_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION2_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION2_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION2_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION2_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION2_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION2_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION2_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION3_ADDR_START + description: Region address register + addressOffset: 40 + size: 32 + fields: + - name: REGION3_ADDR_START + description: Start address of region3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION3_ADDR_END + description: Region address register + addressOffset: 44 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION3_ADDR_END + description: End address of region3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION3_PMS_ATTR + description: Region access authority attribute register + addressOffset: 48 + size: 32 + fields: + - name: REGION3_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION3_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION3_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION3_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION3_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION3_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION3_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION3_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION3_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: FUNC_CTRL + description: PMS function control register + addressOffset: 196 + size: 32 + resetValue: 3 + fields: + - name: M0_PMS_FUNC_EN + description: PMS M0 function enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: M1_PMS_FUNC_EN + description: PMS M1 function enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: M0_STATUS + description: M0 status register + addressOffset: 200 + size: 32 + fields: + - name: M0_EXCEPTION_STATUS + description: Exception status + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: M0_STATUS_CLR + description: M0 status clear register + addressOffset: 204 + size: 32 + fields: + - name: M0_REGION_STATUS_CLR + description: Clear exception status + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: M0_EXCEPTION_INFO0 + description: M0 exception_info0 register + addressOffset: 208 + size: 32 + fields: + - name: M0_EXCEPTION_REGION + description: Exception region + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: M0_EXCEPTION_MODE + description: Exception mode + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: M0_EXCEPTION_ID + description: Exception id information + bitOffset: 18 + bitWidth: 5 + access: read-only + - register: + name: M0_EXCEPTION_INFO1 + description: M0 exception_info1 register + addressOffset: 212 + size: 32 + fields: + - name: M0_EXCEPTION_ADDR + description: Exception addr + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: M1_STATUS + description: M1 status register + addressOffset: 216 + size: 32 + fields: + - name: M1_EXCEPTION_STATUS + description: Exception status + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: M1_STATUS_CLR + description: M1 status clear register + addressOffset: 220 + size: 32 + fields: + - name: M1_REGION_STATUS_CLR + description: Clear exception status + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: M1_EXCEPTION_INFO0 + description: M1 exception_info0 register + addressOffset: 224 + size: 32 + fields: + - name: M1_EXCEPTION_REGION + description: Exception region + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: M1_EXCEPTION_MODE + description: Exception mode + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: M1_EXCEPTION_ID + description: Exception id information + bitOffset: 18 + bitWidth: 5 + access: read-only + - register: + name: M1_EXCEPTION_INFO1 + description: M1 exception_info1 register + addressOffset: 228 + size: 32 + fields: + - name: M1_EXCEPTION_ADDR + description: Exception addr + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INT_EN + description: APM interrupt enable register + addressOffset: 232 + size: 32 + fields: + - name: M0_APM_INT_EN + description: APM M0 interrupt enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: M1_APM_INT_EN + description: APM M1 interrupt enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CLOCK_GATE + description: clock gating register + addressOffset: 236 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: reg_clk_en + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version register + addressOffset: 252 + size: 32 + resetValue: 35672640 + fields: + - name: DATE + description: reg_date + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: LP_APM0 + description: LP_APM0 Peripheral + groupName: LP_APM0 + baseAddress: 1611241472 + addressBlock: + - offset: 0 + size: 84 + usage: registers + registers: + - register: + name: REGION_FILTER_EN + description: Region filter enable register + addressOffset: 0 + size: 32 + resetValue: 1 + fields: + - name: REGION_FILTER_EN + description: Region filter enable + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: REGION0_ADDR_START + description: Region address register + addressOffset: 4 + size: 32 + fields: + - name: REGION0_ADDR_START + description: Start address of region0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION0_ADDR_END + description: Region address register + addressOffset: 8 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION0_ADDR_END + description: End address of region0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION0_PMS_ATTR + description: Region access authority attribute register + addressOffset: 12 + size: 32 + fields: + - name: REGION0_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION0_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION0_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION0_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION0_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION0_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION0_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION0_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION0_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION1_ADDR_START + description: Region address register + addressOffset: 16 + size: 32 + fields: + - name: REGION1_ADDR_START + description: Start address of region1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION1_ADDR_END + description: Region address register + addressOffset: 20 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION1_ADDR_END + description: End address of region1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION1_PMS_ATTR + description: Region access authority attribute register + addressOffset: 24 + size: 32 + fields: + - name: REGION1_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION1_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION1_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION1_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION1_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION1_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION1_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION1_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION1_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION2_ADDR_START + description: Region address register + addressOffset: 28 + size: 32 + fields: + - name: REGION2_ADDR_START + description: Start address of region2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION2_ADDR_END + description: Region address register + addressOffset: 32 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION2_ADDR_END + description: End address of region2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION2_PMS_ATTR + description: Region access authority attribute register + addressOffset: 36 + size: 32 + fields: + - name: REGION2_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION2_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION2_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION2_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION2_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION2_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION2_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION2_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION2_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION3_ADDR_START + description: Region address register + addressOffset: 40 + size: 32 + fields: + - name: REGION3_ADDR_START + description: Start address of region3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION3_ADDR_END + description: Region address register + addressOffset: 44 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION3_ADDR_END + description: End address of region3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION3_PMS_ATTR + description: Region access authority attribute register + addressOffset: 48 + size: 32 + fields: + - name: REGION3_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION3_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION3_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION3_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION3_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION3_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION3_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION3_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION3_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: FUNC_CTRL + description: PMS function control register + addressOffset: 196 + size: 32 + resetValue: 1 + fields: + - name: M0_PMS_FUNC_EN + description: PMS M0 function enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: M0_STATUS + description: M0 status register + addressOffset: 200 + size: 32 + fields: + - name: M0_EXCEPTION_STATUS + description: Exception status + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: M0_STATUS_CLR + description: M0 status clear register + addressOffset: 204 + size: 32 + fields: + - name: M0_REGION_STATUS_CLR + description: Clear exception status + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: M0_EXCEPTION_INFO0 + description: M0 exception_info0 register + addressOffset: 208 + size: 32 + fields: + - name: M0_EXCEPTION_REGION + description: Exception region + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: M0_EXCEPTION_MODE + description: Exception mode + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: M0_EXCEPTION_ID + description: Exception id information + bitOffset: 18 + bitWidth: 5 + access: read-only + - register: + name: M0_EXCEPTION_INFO1 + description: M0 exception_info1 register + addressOffset: 212 + size: 32 + fields: + - name: M0_EXCEPTION_ADDR + description: Exception addr + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INT_EN + description: APM interrupt enable register + addressOffset: 216 + size: 32 + fields: + - name: M0_APM_INT_EN + description: APM M0 interrupt enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CLOCK_GATE + description: clock gating register + addressOffset: 220 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: reg_clk_en + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version register + addressOffset: 2044 + size: 32 + resetValue: 35672640 + fields: + - name: DATE + description: reg_date + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: LP_CLKRST + description: LP_CLKRST Peripheral + groupName: LP_CLKRST + baseAddress: 1611334656 + addressBlock: + - offset: 0 + size: 52 + usage: registers + registers: + - register: + name: LP_CLK_CONF + description: need_des + addressOffset: 0 + size: 32 + resetValue: 4 + fields: + - name: SLOW_CLK_SEL + description: need_des + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: FAST_CLK_SEL + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: LP_PERI_DIV_NUM + description: need_des + bitOffset: 3 + bitWidth: 8 + access: read-write + - register: + name: LP_CLK_PO_EN + description: need_des + addressOffset: 4 + size: 32 + resetValue: 2047 + fields: + - name: AON_SLOW_OEN + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: AON_FAST_OEN + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SOSC_OEN + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FOSC_OEN + description: need_des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OSC32K_OEN + description: need_des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: XTAL32K_OEN + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CORE_EFUSE_OEN + description: need_des + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SLOW_OEN + description: need_des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FAST_OEN + description: need_des + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RNG_OEN + description: need_des + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: LPBUS_OEN + description: need_des + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: LP_CLK_EN + description: need_des + addressOffset: 8 + size: 32 + fields: + - name: FAST_ORI_GATE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_RST_EN + description: need_des + addressOffset: 12 + size: 32 + fields: + - name: AON_EFUSE_CORE_RESET_EN + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_TIMER_RESET_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: WDT_RESET_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: ANA_PERI_RESET_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RESET_CAUSE + description: need_des + addressOffset: 16 + size: 32 + resetValue: 32 + fields: + - name: RESET_CAUSE + description: need_des + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: CORE0_RESET_FLAG + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CORE0_RESET_CAUSE_CLR + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: CORE0_RESET_FLAG_SET + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: CORE0_RESET_FLAG_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: CPU_RESET + description: need_des + addressOffset: 20 + size: 32 + resetValue: 71303168 + fields: + - name: RTC_WDT_CPU_RESET_LENGTH + description: need_des + bitOffset: 22 + bitWidth: 3 + access: read-write + - name: RTC_WDT_CPU_RESET_EN + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: CPU_STALL_WAIT + description: need_des + bitOffset: 26 + bitWidth: 5 + access: read-write + - name: CPU_STALL_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: FOSC_CNTL + description: need_des + addressOffset: 24 + size: 32 + resetValue: 721420288 + fields: + - name: FOSC_DFREQ + description: need_des + bitOffset: 22 + bitWidth: 10 + access: read-write + - register: + name: RC32K_CNTL + description: need_des + addressOffset: 28 + size: 32 + resetValue: 721420288 + fields: + - name: RC32K_DFREQ + description: need_des + bitOffset: 22 + bitWidth: 10 + access: read-write + - register: + name: CLK_TO_HP + description: need_des + addressOffset: 32 + size: 32 + resetValue: 4026531840 + fields: + - name: ICG_HP_XTAL32K + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: ICG_HP_SOSC + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ICG_HP_OSC32K + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: ICG_HP_FOSC + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LPMEM_FORCE + description: need_des + addressOffset: 36 + size: 32 + fields: + - name: LPMEM_CLK_FORCE_ON + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LPPERI + description: need_des + addressOffset: 40 + size: 32 + fields: + - name: LP_I2C_CLK_SEL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_UART_CLK_SEL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: XTAL32K + description: need_des + addressOffset: 44 + size: 32 + resetValue: 1723858944 + fields: + - name: DRES_XTAL32K + description: need_des + bitOffset: 22 + bitWidth: 3 + access: read-write + - name: DGM_XTAL32K + description: need_des + bitOffset: 25 + bitWidth: 3 + access: read-write + - name: DBUF_XTAL32K + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DAC_XTAL32K + description: need_des + bitOffset: 29 + bitWidth: 3 + access: read-write + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 35676304 + fields: + - name: CLKRST_DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: LP_I2C0 + description: Low-power I2C (Inter-Integrated Circuit) Controller 0 + groupName: LP_I2C0 + baseAddress: 1611339776 + addressBlock: + - offset: 0 + size: 136 + usage: registers + interrupt: + - name: LP_I2C + value: 17 + registers: + - register: + name: SCL_LOW_PERIOD + description: "Configures the low level width of the SCL\nClock" + addressOffset: 0 + size: 32 + fields: + - name: SCL_LOW_PERIOD + description: "This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: CTR + description: Transmission setting + addressOffset: 4 + size: 32 + resetValue: 520 + fields: + - name: SDA_FORCE_OUT + description: "1: direct output, 0: open drain output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_FORCE_OUT + description: "1: direct output, 0: open drain output." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SAMPLE_SCL_LEVEL + description: "This register is used to select the sample mode.\n1: sample SDA data on the SCL low level.\n0: sample SDA data on the SCL high level." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_FULL_ACK_LEVEL + description: This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TRANS_START + description: Set this bit to start sending the data in txfifo. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TX_LSB_FIRST + description: "This bit is used to control the sending mode for data needing to be sent. \n1: send data from the least significant bit,\n0: send data from the most significant bit." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_LSB_FIRST + description: "This bit is used to control the storage mode for received data.\n1: receive data from the least significant bit,\n0: receive data from the most significant bit." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ARBITRATION_EN + description: This is the enable bit for arbitration_lost. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FSM_RST + description: This register is used to reset the scl FMS. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: CONF_UPGATE + description: synchronization bit + bitOffset: 11 + bitWidth: 1 + access: write-only + - register: + name: SR + description: Describe I2C work status. + addressOffset: 8 + size: 32 + fields: + - name: RESP_REC + description: "The received ACK value in master mode or slave mode. 0: ACK, 1: NACK." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ARB_LOST + description: "When the I2C controller loses control of SCL line, this register changes to 1." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BUS_BUSY + description: "1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: RXFIFO_CNT + description: This field represents the amount of data needed to be sent. + bitOffset: 8 + bitWidth: 5 + access: read-only + - name: TXFIFO_CNT + description: This field stores the amount of received data in RAM. + bitOffset: 18 + bitWidth: 5 + access: read-only + - name: SCL_MAIN_STATE_LAST + description: "This field indicates the states of the I2C module state machine. \n0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK" + bitOffset: 24 + bitWidth: 3 + access: read-only + - name: SCL_STATE_LAST + description: "This field indicates the states of the state machine used to produce SCL.\n0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop" + bitOffset: 28 + bitWidth: 3 + access: read-only + - register: + name: TO + description: Setting time out control for receiving data. + addressOffset: 12 + size: 32 + resetValue: 16 + fields: + - name: TIME_OUT_VALUE + description: "This register is used to configure the timeout for receiving a data bit in APB\nclock cycles." + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: TIME_OUT_EN + description: This is the enable bit for time out control. + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: FIFO_ST + description: FIFO status register. + addressOffset: 20 + size: 32 + fields: + - name: RXFIFO_RADDR + description: This is the offset address of the APB reading from rxfifo + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: RXFIFO_WADDR + description: This is the offset address of i2c module receiving data and writing to rxfifo. + bitOffset: 5 + bitWidth: 4 + access: read-only + - name: TXFIFO_RADDR + description: This is the offset address of i2c module reading from txfifo. + bitOffset: 10 + bitWidth: 4 + access: read-only + - name: TXFIFO_WADDR + description: This is the offset address of APB bus writing to txfifo. + bitOffset: 15 + bitWidth: 4 + access: read-only + - register: + name: FIFO_CONF + description: FIFO configuration register. + addressOffset: 24 + size: 32 + resetValue: 16454 + fields: + - name: RXFIFO_WM_THRHD + description: "The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: TXFIFO_WM_THRHD + description: "The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid." + bitOffset: 5 + bitWidth: 4 + access: read-write + - name: NONFIFO_EN + description: Set this bit to enable APB nonfifo access. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: RX_FIFO_RST + description: Set this bit to reset rx-fifo. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_FIFO_RST + description: Set this bit to reset tx-fifo. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FIFO_PRT_EN + description: "The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty." + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DATA + description: Rx FIFO read data. + addressOffset: 28 + size: 32 + fields: + - name: FIFO_RDATA + description: The value of rx FIFO read data. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 32 + size: 32 + resetValue: 2 + fields: + - name: RXFIFO_WM_INT_RAW + description: The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_WM_INT_RAW + description: The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_RAW + description: The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: END_DETECT_INT_RAW + description: The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS_DONE_INT_RAW + description: The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_RAW + description: The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: MST_TXFIFO_UDF_INT_RAW + description: The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_RAW + description: The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_RAW + description: The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TRANS_START_INT_RAW + description: The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: NACK_INT_RAW + description: The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: TXFIFO_OVF_INT_RAW + description: The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: RXFIFO_UDF_INT_RAW + description: The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SCL_ST_TO_INT_RAW + description: The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SCL_MAIN_ST_TO_INT_RAW + description: The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DET_START_INT_RAW + description: The raw interrupt bit for I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 36 + size: 32 + fields: + - name: RXFIFO_WM_INT_CLR + description: Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TXFIFO_WM_INT_CLR + description: Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RXFIFO_OVF_INT_CLR + description: Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: END_DETECT_INT_CLR + description: Set this bit to clear the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: BYTE_TRANS_DONE_INT_CLR + description: Set this bit to clear the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: ARBITRATION_LOST_INT_CLR + description: Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: MST_TXFIFO_UDF_INT_CLR + description: Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TRANS_COMPLETE_INT_CLR + description: Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: TIME_OUT_INT_CLR + description: Set this bit to clear the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: TRANS_START_INT_CLR + description: Set this bit to clear the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: NACK_INT_CLR + description: Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: TXFIFO_OVF_INT_CLR + description: Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: RXFIFO_UDF_INT_CLR + description: Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: SCL_ST_TO_INT_CLR + description: Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SCL_MAIN_ST_TO_INT_CLR + description: Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: DET_START_INT_CLR + description: Set this bit to clear I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 40 + size: 32 + fields: + - name: RXFIFO_WM_INT_ENA + description: The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_WM_INT_ENA + description: The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_ENA + description: The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: END_DETECT_INT_ENA + description: The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: BYTE_TRANS_DONE_INT_ENA + description: The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ARBITRATION_LOST_INT_ENA + description: The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: MST_TXFIFO_UDF_INT_ENA + description: The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TRANS_COMPLETE_INT_ENA + description: The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TIME_OUT_INT_ENA + description: The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TRANS_START_INT_ENA + description: The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: NACK_INT_ENA + description: The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TXFIFO_OVF_INT_ENA + description: The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RXFIFO_UDF_INT_ENA + description: The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SCL_ST_TO_INT_ENA + description: The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SCL_MAIN_ST_TO_INT_ENA + description: The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DET_START_INT_ENA + description: The interrupt enable bit for I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: INT_STATUS + description: Status of captured I2C communication events + addressOffset: 44 + size: 32 + fields: + - name: RXFIFO_WM_INT_ST + description: The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_WM_INT_ST + description: The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_ST + description: The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: END_DETECT_INT_ST + description: The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS_DONE_INT_ST + description: The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_ST + description: The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: MST_TXFIFO_UDF_INT_ST + description: The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_ST + description: The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_ST + description: The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TRANS_START_INT_ST + description: The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: NACK_INT_ST + description: The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: TXFIFO_OVF_INT_ST + description: The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: RXFIFO_UDF_INT_ST + description: The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SCL_ST_TO_INT_ST + description: The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SCL_MAIN_ST_TO_INT_ST + description: The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DET_START_INT_ST + description: The masked interrupt status bit for I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - register: + name: SDA_HOLD + description: Configures the hold time after a negative SCL edge. + addressOffset: 48 + size: 32 + fields: + - name: TIME + description: "This register is used to configure the time to hold the data after the negative\nedge of SCL, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SDA_SAMPLE + description: Configures the sample time after a positive SCL edge. + addressOffset: 52 + size: 32 + fields: + - name: TIME + description: "This register is used to configure for how long SDA is sampled, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_HIGH_PERIOD + description: Configures the high level width of SCL + addressOffset: 56 + size: 32 + fields: + - name: SCL_HIGH_PERIOD + description: "This register is used to configure for how long SCL setup to high level and remains high in master mode, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: SCL_WAIT_HIGH_PERIOD + description: "This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles." + bitOffset: 9 + bitWidth: 7 + access: read-write + - register: + name: SCL_START_HOLD + description: Configures the delay between the SDA and SCL negative edge for a start condition + addressOffset: 64 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the time between the negative edge\nof SDA and the negative edge of SCL for a START condition, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_RSTART_SETUP + description: "Configures the delay between the positive\nedge of SCL and the negative edge of SDA" + addressOffset: 68 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the time between the positive\nedge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_STOP_HOLD + description: "Configures the delay after the SCL clock\nedge for a stop condition" + addressOffset: 72 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the delay after the STOP condition,\nin I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_STOP_SETUP + description: "Configures the delay between the SDA and\nSCL positive edge for a stop condition" + addressOffset: 76 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the time between the positive edge\nof SCL and the positive edge of SDA, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: FILTER_CFG + description: SCL and SDA filter configuration register + addressOffset: 80 + size: 32 + resetValue: 768 + fields: + - name: SCL_FILTER_THRES + description: "When a pulse on the SCL input has smaller width than this register value\nin I2C module clock cycles, the I2C controller will ignore that pulse." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: SDA_FILTER_THRES + description: "When a pulse on the SDA input has smaller width than this register value\nin I2C module clock cycles, the I2C controller will ignore that pulse." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: SCL_FILTER_EN + description: This is the filter enable bit for SCL. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SDA_FILTER_EN + description: This is the filter enable bit for SDA. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: CLK_CONF + description: I2C CLK configuration register + addressOffset: 84 + size: 32 + resetValue: 2097152 + fields: + - name: SCLK_DIV_NUM + description: the integral part of the fractional divisor for i2c module + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SCLK_DIV_A + description: the numerator of the fractional part of the fractional divisor for i2c module + bitOffset: 8 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_B + description: the denominator of the fractional part of the fractional divisor for i2c module + bitOffset: 14 + bitWidth: 6 + access: read-write + - name: SCLK_SEL + description: "The clock selection for i2c module:0-XTAL,1-CLK_8MHz." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SCLK_ACTIVE + description: The clock switch for i2c module + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + name: COMD0 + description: I2C command register 0 + addressOffset: 88 + size: 32 + fields: + - name: COMMAND0 + description: "This is the content of command 0. It consists of three parts: \nop_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.\nByte_num represents the number of bytes that need to be sent or received.\nack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more\nInformation." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND0_DONE + description: "When command 0 is done in I2C Master mode, this bit changes to high\nlevel." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD1 + description: I2C command register 1 + addressOffset: 92 + size: 32 + fields: + - name: COMMAND1 + description: "This is the content of command 1. It consists of three parts: \nop_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.\nByte_num represents the number of bytes that need to be sent or received.\nack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more\nInformation." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND1_DONE + description: "When command 1 is done in I2C Master mode, this bit changes to high\nlevel." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD2 + description: I2C command register 2 + addressOffset: 96 + size: 32 + fields: + - name: COMMAND2 + description: "This is the content of command 2. It consists of three parts: \nop_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.\nByte_num represents the number of bytes that need to be sent or received.\nack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more\nInformation." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND2_DONE + description: "When command 2 is done in I2C Master mode, this bit changes to high\nLevel." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD3 + description: I2C command register 3 + addressOffset: 100 + size: 32 + fields: + - name: COMMAND3 + description: "This is the content of command 3. It consists of three parts: \nop_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.\nByte_num represents the number of bytes that need to be sent or received.\nack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more\nInformation." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND3_DONE + description: "When command 3 is done in I2C Master mode, this bit changes to high\nlevel." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD4 + description: I2C command register 4 + addressOffset: 104 + size: 32 + fields: + - name: COMMAND4 + description: "This is the content of command 4. It consists of three parts: \nop_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.\nByte_num represents the number of bytes that need to be sent or received.\nack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more\nInformation." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND4_DONE + description: "When command 4 is done in I2C Master mode, this bit changes to high\nlevel." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD5 + description: I2C command register 5 + addressOffset: 108 + size: 32 + fields: + - name: COMMAND5 + description: "This is the content of command 5. It consists of three parts:\nop_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.\nByte_num represents the number of bytes that need to be sent or received.\nack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more\nInformation." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND5_DONE + description: "When command 5 is done in I2C Master mode, this bit changes to high level." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD6 + description: I2C command register 6 + addressOffset: 112 + size: 32 + fields: + - name: COMMAND6 + description: "This is the content of command 6. It consists of three parts: \nop_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.\nByte_num represents the number of bytes that need to be sent or received.\nack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more\nInformation." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND6_DONE + description: "When command 6 is done in I2C Master mode, this bit changes to high level." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD7 + description: I2C command register 7 + addressOffset: 116 + size: 32 + fields: + - name: COMMAND7 + description: "This is the content of command 7. It consists of three parts: \nop_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.\nByte_num represents the number of bytes that need to be sent or received.\nack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more\nInformation." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND7_DONE + description: "When command 7 is done in I2C Master mode, this bit changes to high level." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SCL_ST_TIME_OUT + description: SCL status time out register + addressOffset: 120 + size: 32 + resetValue: 16 + fields: + - name: SCL_ST_TO_I2C + description: The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SCL_MAIN_ST_TIME_OUT + description: SCL main status time out register + addressOffset: 124 + size: 32 + resetValue: 16 + fields: + - name: SCL_MAIN_ST_TO_I2C + description: The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23 + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SCL_SP_CONF + description: Power configuration register + addressOffset: 128 + size: 32 + fields: + - name: SCL_RST_SLV_EN + description: "When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_RST_SLV_NUM + description: Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. + bitOffset: 1 + bitWidth: 5 + access: read-write + - name: SCL_PD_EN + description: "The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SDA_PD_EN + description: "The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low." + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version register + addressOffset: 248 + size: 32 + resetValue: 35656003 + fields: + - name: DATE + description: This is the the version register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TXFIFO_START_ADDR + description: I2C TXFIFO base address register + addressOffset: 256 + size: 32 + fields: + - name: TXFIFO_START_ADDR + description: This is the I2C txfifo first address. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RXFIFO_START_ADDR + description: I2C RXFIFO base address register + addressOffset: 384 + size: 32 + fields: + - name: RXFIFO_START_ADDR + description: This is the I2C rxfifo first address. + bitOffset: 0 + bitWidth: 32 + access: read-only + - name: LP_I2C_ANA_MST + description: LP_I2C_ANA_MST Peripheral + groupName: LP_I2C_ANA_MST + baseAddress: 1611342848 + addressBlock: + - offset: 0 + size: 28 + usage: registers + registers: + - register: + name: I2C0_CTRL + description: need_des + addressOffset: 0 + size: 32 + fields: + - name: LP_I2C_ANA_MAST_I2C0_CTRL + description: need_des + bitOffset: 0 + bitWidth: 25 + access: read-write + - name: LP_I2C_ANA_MAST_I2C0_BUSY + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-only + - register: + name: I2C0_CONF + description: need_des + addressOffset: 4 + size: 32 + resetValue: 117440512 + fields: + - name: LP_I2C_ANA_MAST_I2C0_CONF + description: need_des + bitOffset: 0 + bitWidth: 24 + access: read-write + - name: LP_I2C_ANA_MAST_I2C0_STATUS + description: reserved + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: I2C0_DATA + description: need_des + addressOffset: 8 + size: 32 + resetValue: 2304 + fields: + - name: LP_I2C_ANA_MAST_I2C0_RDATA + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: LP_I2C_ANA_MAST_I2C0_CLK_SEL + description: need_des + bitOffset: 8 + bitWidth: 3 + access: read-write + - name: LP_I2C_ANA_MAST_I2C_MST_SEL + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: ANA_CONF1 + description: need_des + addressOffset: 12 + size: 32 + fields: + - name: LP_I2C_ANA_MAST_ANA_CONF1 + description: need_des + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: NOUSE + description: need_des + addressOffset: 16 + size: 32 + fields: + - name: LP_I2C_ANA_MAST_I2C_MST_NOUSE + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DEVICE_EN + description: need_des + addressOffset: 20 + size: 32 + fields: + - name: LP_I2C_ANA_MAST_I2C_DEVICE_EN + description: need_des + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 33583873 + fields: + - name: LP_I2C_ANA_MAST_I2C_MAT_DATE + description: need_des + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: LP_I2C_ANA_MAST_I2C_MAT_CLK_EN + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_IO + description: LP_IO Peripheral + groupName: LP_IO + baseAddress: 1611341824 + addressBlock: + - offset: 0 + size: 124 + usage: registers + registers: + - register: + name: OUT_DATA + description: need des + addressOffset: 0 + size: 32 + fields: + - name: OUT_DATA + description: set lp gpio output data + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: OUT_DATA_W1TS + description: need des + addressOffset: 4 + size: 32 + fields: + - name: OUT_DATA_W1TS + description: set one time output data + bitOffset: 0 + bitWidth: 8 + access: write-only + - register: + name: OUT_DATA_W1TC + description: need des + addressOffset: 8 + size: 32 + fields: + - name: OUT_DATA_W1TC + description: clear one time output data + bitOffset: 0 + bitWidth: 8 + access: write-only + - register: + name: OUT_ENABLE + description: need des + addressOffset: 12 + size: 32 + fields: + - name: ENABLE + description: set lp gpio output data + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: OUT_ENABLE_W1TS + description: need des + addressOffset: 16 + size: 32 + fields: + - name: ENABLE_W1TS + description: set one time output data + bitOffset: 0 + bitWidth: 8 + access: write-only + - register: + name: OUT_ENABLE_W1TC + description: need des + addressOffset: 20 + size: 32 + fields: + - name: ENABLE_W1TC + description: clear one time output data + bitOffset: 0 + bitWidth: 8 + access: write-only + - register: + name: STATUS + description: need des + addressOffset: 24 + size: 32 + fields: + - name: INTERRUPT + description: set lp gpio output data + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: STATUS_W1TS + description: need des + addressOffset: 28 + size: 32 + fields: + - name: STATUS_W1TS + description: set one time output data + bitOffset: 0 + bitWidth: 8 + access: write-only + - register: + name: STATUS_W1TC + description: need des + addressOffset: 32 + size: 32 + fields: + - name: STATUS_W1TC + description: clear one time output data + bitOffset: 0 + bitWidth: 8 + access: write-only + - register: + name: IN + description: need des + addressOffset: 36 + size: 32 + fields: + - name: DATA_NEXT + description: need des + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: PIN0 + description: need des + addressOffset: 40 + size: 32 + fields: + - name: SYNC_BYPASS + description: need des + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: PAD_DRIVER + description: need des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EDGE_WAKEUP_CLR + description: need des + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: INT_TYPE + description: need des + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: need des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: PIN1 + description: need des + addressOffset: 44 + size: 32 + fields: + - name: SYNC_BYPASS + description: need des + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: PAD_DRIVER + description: need des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EDGE_WAKEUP_CLR + description: need des + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: INT_TYPE + description: need des + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: need des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: PIN2 + description: need des + addressOffset: 48 + size: 32 + fields: + - name: SYNC_BYPASS + description: need des + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: PAD_DRIVER + description: need des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EDGE_WAKEUP_CLR + description: need des + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: INT_TYPE + description: need des + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: need des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: PIN3 + description: need des + addressOffset: 52 + size: 32 + fields: + - name: SYNC_BYPASS + description: need des + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: PAD_DRIVER + description: need des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EDGE_WAKEUP_CLR + description: need des + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: INT_TYPE + description: need des + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: need des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: PIN4 + description: need des + addressOffset: 56 + size: 32 + fields: + - name: SYNC_BYPASS + description: need des + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: PAD_DRIVER + description: need des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EDGE_WAKEUP_CLR + description: need des + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: INT_TYPE + description: need des + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: need des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: PIN5 + description: need des + addressOffset: 60 + size: 32 + fields: + - name: SYNC_BYPASS + description: need des + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: PAD_DRIVER + description: need des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EDGE_WAKEUP_CLR + description: need des + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: INT_TYPE + description: need des + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: need des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: PIN6 + description: need des + addressOffset: 64 + size: 32 + fields: + - name: SYNC_BYPASS + description: need des + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: PAD_DRIVER + description: need des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EDGE_WAKEUP_CLR + description: need des + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: INT_TYPE + description: need des + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: need des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: PIN7 + description: need des + addressOffset: 68 + size: 32 + fields: + - name: SYNC_BYPASS + description: need des + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: PAD_DRIVER + description: need des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EDGE_WAKEUP_CLR + description: need des + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: INT_TYPE + description: need des + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: need des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: GPIO0 + description: need des + addressOffset: 72 + size: 32 + fields: + - name: MCU_OE + description: need des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: need des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: need des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: need des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: need des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: need des + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: need des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: need des + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: need des + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: need des + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: need des + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO1 + description: need des + addressOffset: 76 + size: 32 + fields: + - name: MCU_OE + description: need des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: need des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: need des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: need des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: need des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: need des + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: need des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: need des + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: need des + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: need des + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: need des + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO2 + description: need des + addressOffset: 80 + size: 32 + fields: + - name: MCU_OE + description: need des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: need des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: need des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: need des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: need des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: need des + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: need des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: need des + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: need des + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: need des + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: need des + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO3 + description: need des + addressOffset: 84 + size: 32 + fields: + - name: MCU_OE + description: need des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: need des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: need des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: need des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: need des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: need des + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: need des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: need des + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: need des + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: need des + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: need des + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO4 + description: need des + addressOffset: 88 + size: 32 + fields: + - name: MCU_OE + description: need des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: need des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: need des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: need des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: need des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: need des + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: need des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: need des + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: need des + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: need des + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: need des + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO5 + description: need des + addressOffset: 92 + size: 32 + fields: + - name: MCU_OE + description: need des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: need des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: need des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: need des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: need des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: need des + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: need des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: need des + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: need des + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: need des + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: need des + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO6 + description: need des + addressOffset: 96 + size: 32 + fields: + - name: MCU_OE + description: need des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: need des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: need des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: need des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: need des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: need des + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: need des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: need des + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: need des + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: need des + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: need des + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: GPIO7 + description: need des + addressOffset: 100 + size: 32 + fields: + - name: MCU_OE + description: need des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: need des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: need des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: need des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: need des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: need des + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: need des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: need des + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: need des + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: need des + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: need des + bitOffset: 12 + bitWidth: 3 + access: read-write + - register: + name: STATUS_INTERRUPT + description: need des + addressOffset: 104 + size: 32 + fields: + - name: NEXT + description: need des + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: DEBUG_SEL0 + description: need des + addressOffset: 108 + size: 32 + fields: + - name: LP_DEBUG_SEL0 + description: need des + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: LP_DEBUG_SEL1 + description: need des + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: LP_DEBUG_SEL2 + description: need des + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: LP_DEBUG_SEL3 + description: need des + bitOffset: 21 + bitWidth: 7 + access: read-write + - register: + name: DEBUG_SEL1 + description: need des + addressOffset: 112 + size: 32 + fields: + - name: LP_DEBUG_SEL4 + description: need des + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: LPI2C + description: need des + addressOffset: 116 + size: 32 + resetValue: 3221225472 + fields: + - name: LP_I2C_SDA_IE + description: need des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_I2C_SCL_IE + description: need des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: need des + addressOffset: 1020 + size: 32 + resetValue: 35660032 + fields: + - name: LP_IO_DATE + description: need des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: LP_TEE + description: Low-power Trusted Execution Environment + groupName: LP_TEE + baseAddress: 1611346944 + addressBlock: + - offset: 0 + size: 16 + usage: registers + registers: + - register: + name: M0_MODE_CTRL + description: Tee mode control register + addressOffset: 0 + size: 32 + resetValue: 3 + fields: + - name: M0_MODE + description: "M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: CLOCK_GATE + description: Clock gating register + addressOffset: 4 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: reg_clk_en + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: FORCE_ACC_HP + description: need_des + addressOffset: 144 + size: 32 + fields: + - name: LP_AON_FORCE_ACC_HPMEM_EN + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version register + addressOffset: 252 + size: 32 + resetValue: 35672688 + fields: + - name: DATE + description: reg_tee_date + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: LP_TIMER + description: Low-power Timer + groupName: LP_TIMER + baseAddress: 1611336704 + addressBlock: + - offset: 0 + size: 76 + usage: registers + interrupt: + - name: LP_RTC_TIMER + value: 15 + registers: + - register: + name: TAR0_LOW + description: need_des + addressOffset: 0 + size: 32 + fields: + - name: MAIN_TIMER_TAR_LOW0 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TAR0_HIGH + description: need_des + addressOffset: 4 + size: 32 + fields: + - name: MAIN_TIMER_TAR_HIGH0 + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MAIN_TIMER_TAR_EN0 + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: TAR1_LOW + description: need_des + addressOffset: 8 + size: 32 + fields: + - name: MAIN_TIMER_TAR_LOW1 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TAR1_HIGH + description: need_des + addressOffset: 12 + size: 32 + fields: + - name: MAIN_TIMER_TAR_HIGH1 + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MAIN_TIMER_TAR_EN1 + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: UPDATE + description: need_des + addressOffset: 16 + size: 32 + fields: + - name: MAIN_TIMER_UPDATE + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: MAIN_TIMER_XTAL_OFF + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: MAIN_TIMER_SYS_STALL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: MAIN_TIMER_SYS_RST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: MAIN_BUF0_LOW + description: need_des + addressOffset: 20 + size: 32 + fields: + - name: MAIN_TIMER_BUF0_LOW + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: MAIN_BUF0_HIGH + description: need_des + addressOffset: 24 + size: 32 + fields: + - name: MAIN_TIMER_BUF0_HIGH + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: MAIN_BUF1_LOW + description: need_des + addressOffset: 28 + size: 32 + fields: + - name: MAIN_TIMER_BUF1_LOW + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: MAIN_BUF1_HIGH + description: need_des + addressOffset: 32 + size: 32 + fields: + - name: MAIN_TIMER_BUF1_HIGH + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: MAIN_OVERFLOW + description: need_des + addressOffset: 36 + size: 32 + fields: + - name: MAIN_TIMER_ALARM_LOAD + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: INT_RAW + description: need_des + addressOffset: 40 + size: 32 + fields: + - name: OVERFLOW_RAW + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SOC_WAKEUP_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: need_des + addressOffset: 44 + size: 32 + fields: + - name: OVERFLOW_ST + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: SOC_WAKEUP_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: need_des + addressOffset: 48 + size: 32 + fields: + - name: OVERFLOW_ENA + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SOC_WAKEUP_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: need_des + addressOffset: 52 + size: 32 + fields: + - name: OVERFLOW_CLR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: SOC_WAKEUP_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: LP_INT_RAW + description: need_des + addressOffset: 56 + size: 32 + fields: + - name: MAIN_TIMER_OVERFLOW_LP_INT_RAW + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: MAIN_TIMER_LP_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_INT_ST + description: need_des + addressOffset: 60 + size: 32 + fields: + - name: MAIN_TIMER_OVERFLOW_LP_INT_ST + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: MAIN_TIMER_LP_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: LP_INT_ENA + description: need_des + addressOffset: 64 + size: 32 + fields: + - name: MAIN_TIMER_OVERFLOW_LP_INT_ENA + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: MAIN_TIMER_LP_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_INT_CLR + description: need_des + addressOffset: 68 + size: 32 + fields: + - name: MAIN_TIMER_OVERFLOW_LP_INT_CLR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: MAIN_TIMER_LP_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 34672976 + fields: + - name: DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: LP_UART + description: Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller + groupName: LP_UART + baseAddress: 1611338752 + addressBlock: + - offset: 0 + size: 132 + usage: registers + interrupt: + - name: LP_UART + value: 16 + registers: + - register: + name: FIFO + description: FIFO data register + addressOffset: 0 + size: 32 + fields: + - name: RXFIFO_RD_BYTE + description: UART 0 accesses FIFO via this register. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 4 + size: 32 + resetValue: 2 + fields: + - name: RXFIFO_FULL_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_EMPTY_INT_RAW + description: This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PARITY_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a parity error in the data. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FRM_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a data frame error . + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DSR_CHG_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CTS_CHG_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BRK_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RXFIFO_TOUT_INT_RAW + description: This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SW_XON_INT_RAW + description: This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SW_XOFF_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GLITCH_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_BRK_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_BRK_IDLE_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: AT_CMD_CHAR_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: WAKEUP_INT_RAW + description: This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 8 + size: 32 + fields: + - name: RXFIFO_FULL_INT_ST + description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_EMPTY_INT_ST + description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: PARITY_ERR_INT_ST + description: This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FRM_ERR_INT_ST + description: This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_ST + description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DSR_CHG_INT_ST + description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CTS_CHG_INT_ST + description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BRK_DET_INT_ST + description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: RXFIFO_TOUT_INT_ST + description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SW_XON_INT_ST + description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SW_XOFF_INT_ST + description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: GLITCH_DET_INT_ST + description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TX_BRK_DONE_INT_ST + description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: TX_BRK_IDLE_DONE_INT_ST + description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_ST + description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: AT_CMD_CHAR_DET_INT_ST + description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: WAKEUP_INT_ST + description: This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + bitOffset: 19 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 12 + size: 32 + fields: + - name: RXFIFO_FULL_INT_ENA + description: This is the enable bit for rxfifo_full_int_st register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_EMPTY_INT_ENA + description: This is the enable bit for txfifo_empty_int_st register. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PARITY_ERR_INT_ENA + description: This is the enable bit for parity_err_int_st register. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FRM_ERR_INT_ENA + description: This is the enable bit for frm_err_int_st register. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_ENA + description: This is the enable bit for rxfifo_ovf_int_st register. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DSR_CHG_INT_ENA + description: This is the enable bit for dsr_chg_int_st register. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CTS_CHG_INT_ENA + description: This is the enable bit for cts_chg_int_st register. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BRK_DET_INT_ENA + description: This is the enable bit for brk_det_int_st register. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RXFIFO_TOUT_INT_ENA + description: This is the enable bit for rxfifo_tout_int_st register. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SW_XON_INT_ENA + description: This is the enable bit for sw_xon_int_st register. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SW_XOFF_INT_ENA + description: This is the enable bit for sw_xoff_int_st register. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GLITCH_DET_INT_ENA + description: This is the enable bit for glitch_det_int_st register. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_BRK_DONE_INT_ENA + description: This is the enable bit for tx_brk_done_int_st register. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_BRK_IDLE_DONE_INT_ENA + description: This is the enable bit for tx_brk_idle_done_int_st register. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_ENA + description: This is the enable bit for tx_done_int_st register. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: AT_CMD_CHAR_DET_INT_ENA + description: This is the enable bit for at_cmd_char_det_int_st register. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: WAKEUP_INT_ENA + description: This is the enable bit for uart_wakeup_int_st register. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 16 + size: 32 + fields: + - name: RXFIFO_FULL_INT_CLR + description: Set this bit to clear the rxfifo_full_int_raw interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TXFIFO_EMPTY_INT_CLR + description: Set this bit to clear txfifo_empty_int_raw interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: PARITY_ERR_INT_CLR + description: Set this bit to clear parity_err_int_raw interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: FRM_ERR_INT_CLR + description: Set this bit to clear frm_err_int_raw interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: RXFIFO_OVF_INT_CLR + description: Set this bit to clear rxfifo_ovf_int_raw interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: DSR_CHG_INT_CLR + description: Set this bit to clear the dsr_chg_int_raw interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CTS_CHG_INT_CLR + description: Set this bit to clear the cts_chg_int_raw interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: BRK_DET_INT_CLR + description: Set this bit to clear the brk_det_int_raw interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: RXFIFO_TOUT_INT_CLR + description: Set this bit to clear the rxfifo_tout_int_raw interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SW_XON_INT_CLR + description: Set this bit to clear the sw_xon_int_raw interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SW_XOFF_INT_CLR + description: Set this bit to clear the sw_xoff_int_raw interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: GLITCH_DET_INT_CLR + description: Set this bit to clear the glitch_det_int_raw interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TX_BRK_DONE_INT_CLR + description: Set this bit to clear the tx_brk_done_int_raw interrupt.. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: TX_BRK_IDLE_DONE_INT_CLR + description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: TX_DONE_INT_CLR + description: Set this bit to clear the tx_done_int_raw interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: AT_CMD_CHAR_DET_INT_CLR + description: Set this bit to clear the at_cmd_char_det_int_raw interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: WAKEUP_INT_CLR + description: Set this bit to clear the uart_wakeup_int_raw interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - register: + name: CLKDIV + description: Clock divider configuration + addressOffset: 20 + size: 32 + resetValue: 694 + fields: + - name: CLKDIV + description: The integral part of the frequency divider factor. + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: FRAG + description: The decimal part of the frequency divider factor. + bitOffset: 20 + bitWidth: 4 + access: read-write + - register: + name: RX_FILT + description: Rx Filter configuration + addressOffset: 24 + size: 32 + resetValue: 8 + fields: + - name: GLITCH_FILT + description: when input pulse width is lower than this value the pulse is ignored. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GLITCH_FILT_EN + description: Set this bit to enable Rx signal filter. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: STATUS + description: UART status register + addressOffset: 28 + size: 32 + resetValue: 3758145536 + fields: + - name: RXFIFO_CNT + description: Stores the byte number of valid data in Rx-FIFO. + bitOffset: 3 + bitWidth: 5 + access: read-only + - name: DSRN + description: The register represent the level value of the internal uart dsr signal. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: CTSN + description: This register represent the level value of the internal uart cts signal. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: RXD + description: This register represent the level value of the internal uart rxd signal. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TXFIFO_CNT + description: Stores the byte number of data in Tx-FIFO. + bitOffset: 19 + bitWidth: 5 + access: read-only + - name: DTRN + description: This bit represents the level of the internal uart dtr signal. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: RTSN + description: This bit represents the level of the internal uart rts signal. + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: TXD + description: This bit represents the level of the internal uart txd signal. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CONF0 + description: Configuration register 0 + addressOffset: 32 + size: 32 + resetValue: 1048604 + fields: + - name: PARITY + description: This register is used to configure the parity check mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PARITY_EN + description: Set this bit to enable uart parity check. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BIT_NUM + description: This register is used to set the length of data. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: STOP_BIT_NUM + description: This register is used to set the length of stop bit. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: TXD_BRK + description: Set this bit to enbale transmitter to send NULL when the process of sending data is done. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: LOOPBACK + description: Set this bit to enable uart loopback test mode. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_FLOW_EN + description: Set this bit to enable flow control function for transmitter. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: RXD_INV + description: Set this bit to inverse the level value of uart rxd signal. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TXD_INV + description: Set this bit to inverse the level value of uart txd signal. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DIS_RX_DAT_OVF + description: Disable UART Rx data overflow detect. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: ERR_WR_MASK + description: "1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: MEM_CLK_EN + description: UART memory clock gate enable signal. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SW_RTS + description: This register is used to configure the software rts signal which is used in software flow control. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: RXFIFO_RST + description: Set this bit to reset the uart receive-FIFO. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TXFIFO_RST + description: Set this bit to reset the uart transmit-FIFO. + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: CONF1 + description: Configuration register 1 + addressOffset: 36 + size: 32 + resetValue: 24672 + fields: + - name: RXFIFO_FULL_THRHD + description: It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + bitOffset: 3 + bitWidth: 5 + access: read-write + - name: TXFIFO_EMPTY_THRHD + description: It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + bitOffset: 11 + bitWidth: 5 + access: read-write + - name: CTS_INV + description: Set this bit to inverse the level value of uart cts signal. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DSR_INV + description: Set this bit to inverse the level value of uart dsr signal. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: RTS_INV + description: Set this bit to inverse the level value of uart rts signal. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: DTR_INV + description: Set this bit to inverse the level value of uart dtr signal. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SW_DTR + description: This register is used to configure the software dtr signal which is used in software flow control. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers." + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + name: HWFC_CONF + description: Hardware flow-control configuration + addressOffset: 44 + size: 32 + fields: + - name: RX_FLOW_THRHD + description: This register is used to configure the maximum amount of data that can be received when hardware flow control works. + bitOffset: 3 + bitWidth: 5 + access: read-write + - name: RX_FLOW_EN + description: This is the flow enable bit for UART receiver. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: SLEEP_CONF0 + description: UART sleep configure register 0 + addressOffset: 48 + size: 32 + fields: + - name: WK_CHAR1 + description: This register restores the specified wake up char1 to wake up + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: WK_CHAR2 + description: This register restores the specified wake up char2 to wake up + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: WK_CHAR3 + description: This register restores the specified wake up char3 to wake up + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: WK_CHAR4 + description: This register restores the specified wake up char4 to wake up + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: SLEEP_CONF1 + description: UART sleep configure register 1 + addressOffset: 52 + size: 32 + fields: + - name: WK_CHAR0 + description: This register restores the specified char0 to wake up + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: SLEEP_CONF2 + description: UART sleep configure register 2 + addressOffset: 56 + size: 32 + resetValue: 1319152 + fields: + - name: ACTIVE_THRESHOLD + description: The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: RX_WAKE_UP_THRHD + description: In wake up mode 1 this field is used to set the received data number threshold to wake up chip. + bitOffset: 13 + bitWidth: 5 + access: read-write + - name: WK_CHAR_NUM + description: This register is used to select number of wake up char. + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: WK_CHAR_MASK + description: This register is used to mask wake up char. + bitOffset: 21 + bitWidth: 5 + access: read-write + - name: WK_MODE_SEL + description: "This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than" + bitOffset: 26 + bitWidth: 2 + access: read-write + - register: + name: SWFC_CONF0 + description: Software flow-control character configuration + addressOffset: 60 + size: 32 + resetValue: 4881 + fields: + - name: XON_CHAR + description: This register stores the Xon flow control char. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: XOFF_CHAR + description: This register stores the Xoff flow control char. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: XON_XOFF_STILL_SEND + description: "In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SW_FLOW_CON_EN + description: Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: XONOFF_DEL + description: Set this bit to remove flow control char from the received data. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: FORCE_XON + description: Set this bit to enable the transmitter to go on sending data. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: FORCE_XOFF + description: Set this bit to stop the transmitter from sending data. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SEND_XON + description: Set this bit to send Xon char. It is cleared by hardware automatically. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SEND_XOFF + description: Set this bit to send Xoff char. It is cleared by hardware automatically. + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: SWFC_CONF1 + description: Software flow-control character configuration + addressOffset: 64 + size: 32 + resetValue: 24576 + fields: + - name: XON_THRESHOLD + description: When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char. + bitOffset: 3 + bitWidth: 5 + access: read-write + - name: XOFF_THRESHOLD + description: When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char. + bitOffset: 11 + bitWidth: 5 + access: read-write + - register: + name: TXBRK_CONF + description: Tx Break character configuration + addressOffset: 68 + size: 32 + resetValue: 10 + fields: + - name: TX_BRK_NUM + description: This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: IDLE_CONF + description: Frame-end idle configuration + addressOffset: 72 + size: 32 + resetValue: 262400 + fields: + - name: RX_IDLE_THRHD + description: It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: TX_IDLE_NUM + description: This register is used to configure the duration time between transfers. + bitOffset: 10 + bitWidth: 10 + access: read-write + - register: + name: RS485_CONF + description: RS485 mode configuration + addressOffset: 76 + size: 32 + fields: + - name: DL0_EN + description: Set this bit to delay the stop bit by 1 bit. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DL1_EN + description: Set this bit to delay the stop bit by 1 bit. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: AT_CMD_PRECNT + description: Pre-sequence timing configuration + addressOffset: 80 + size: 32 + resetValue: 2305 + fields: + - name: PRE_IDLE_NUM + description: This register is used to configure the idle duration time before the first at_cmd is received by receiver. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_POSTCNT + description: Post-sequence timing configuration + addressOffset: 84 + size: 32 + resetValue: 2305 + fields: + - name: POST_IDLE_NUM + description: This register is used to configure the duration time between the last at_cmd and the next data. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_GAPTOUT + description: Timeout configuration + addressOffset: 88 + size: 32 + resetValue: 11 + fields: + - name: RX_GAP_TOUT + description: This register is used to configure the duration time between the at_cmd chars. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_CHAR + description: AT escape sequence detection configuration + addressOffset: 92 + size: 32 + resetValue: 811 + fields: + - name: AT_CMD_CHAR + description: This register is used to configure the content of at_cmd char. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CHAR_NUM + description: This register is used to configure the num of continuous at_cmd chars received by receiver. + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: MEM_CONF + description: UART memory power configuration + addressOffset: 96 + size: 32 + fields: + - name: MEM_FORCE_PD + description: Set this bit to force power down UART memory. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PU + description: Set this bit to force power up UART memory. + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: TOUT_CONF + description: UART threshold and allocation configuration + addressOffset: 100 + size: 32 + resetValue: 40 + fields: + - name: RX_TOUT_EN + description: "This is the enble bit for uart receiver's timeout function." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_TOUT_FLOW_DIS + description: Set this bit to stop accumulating idle_cnt when hardware flow control works. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_TOUT_THRHD + description: This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + bitOffset: 2 + bitWidth: 10 + access: read-write + - register: + name: MEM_TX_STATUS + description: Tx-SRAM write and read offset address. + addressOffset: 104 + size: 32 + fields: + - name: TX_SRAM_WADDR + description: This register stores the offset write address in Tx-SRAM. + bitOffset: 3 + bitWidth: 5 + access: read-only + - name: TX_SRAM_RADDR + description: This register stores the offset read address in Tx-SRAM. + bitOffset: 12 + bitWidth: 5 + access: read-only + - register: + name: MEM_RX_STATUS + description: Rx-SRAM write and read offset address. + addressOffset: 108 + size: 32 + resetValue: 65664 + fields: + - name: RX_SRAM_RADDR + description: This register stores the offset read address in RX-SRAM. + bitOffset: 3 + bitWidth: 5 + access: read-only + - name: RX_SRAM_WADDR + description: This register stores the offset write address in Rx-SRAM. + bitOffset: 12 + bitWidth: 5 + access: read-only + - register: + name: FSM_STATUS + description: UART transmit and receive status. + addressOffset: 112 + size: 32 + fields: + - name: ST_URX_OUT + description: This is the status register of receiver. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: ST_UTX_OUT + description: This is the status register of transmitter. + bitOffset: 4 + bitWidth: 4 + access: read-only + - register: + name: CLK_CONF + description: UART core clock configuration + addressOffset: 136 + size: 32 + resetValue: 57675776 + fields: + - name: SCLK_DIV_B + description: The denominator of the frequency divider factor. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_A + description: The numerator of the frequency divider factor. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_NUM + description: The integral part of the frequency divider factor. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: SCLK_SEL + description: "UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: SCLK_EN + description: Set this bit to enable UART Tx/Rx clock. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RST_CORE + description: Write 1 then write 0 to this bit to reset UART Tx/Rx. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TX_SCLK_EN + description: Set this bit to enable UART Tx clock. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: RX_SCLK_EN + description: Set this bit to enable UART Rx clock. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TX_RST_CORE + description: Write 1 then write 0 to this bit to reset UART Tx. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RX_RST_CORE + description: Write 1 then write 0 to this bit to reset UART Rx. + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: UART Version register + addressOffset: 140 + size: 32 + resetValue: 35656288 + fields: + - name: DATE + description: This is the version register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: AFIFO_STATUS + description: UART AFIFO Status + addressOffset: 144 + size: 32 + resetValue: 10 + fields: + - name: TX_AFIFO_FULL + description: Full signal of APB TX AFIFO. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_AFIFO_EMPTY + description: Empty signal of APB TX AFIFO. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_AFIFO_FULL + description: Full signal of APB RX AFIFO. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: RX_AFIFO_EMPTY + description: Empty signal of APB RX AFIFO. + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: REG_UPDATE + description: UART Registers Configuration Update register + addressOffset: 152 + size: 32 + fields: + - name: REG_UPDATE + description: Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: ID + description: UART ID register + addressOffset: 156 + size: 32 + resetValue: 1280 + fields: + - name: ID + description: This register is used to configure the uart_id. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: LP_WDT + description: Low-power Watchdog Timer + groupName: LP_WDT + baseAddress: 1611340800 + addressBlock: + - offset: 0 + size: 56 + usage: registers + interrupt: + - name: LP_WDT + value: 18 + registers: + - register: + name: WDTCONFIG0 + description: need_des + addressOffset: 0 + size: 32 + resetValue: 78356 + fields: + - name: WDT_CHIP_RESET_WIDTH + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: WDT_CHIP_RESET_EN + description: need_des + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: WDT_PAUSE_IN_SLP + description: need_des + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: WDT_APPCPU_RESET_EN + description: need_des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: WDT_PROCPU_RESET_EN + description: need_des + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: WDT_FLASHBOOT_MOD_EN + description: need_des + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: WDT_SYS_RESET_LENGTH + description: need_des + bitOffset: 13 + bitWidth: 3 + access: read-write + - name: WDT_CPU_RESET_LENGTH + description: need_des + bitOffset: 16 + bitWidth: 3 + access: read-write + - name: WDT_STG3 + description: need_des + bitOffset: 19 + bitWidth: 3 + access: read-write + - name: WDT_STG2 + description: need_des + bitOffset: 22 + bitWidth: 3 + access: read-write + - name: WDT_STG1 + description: need_des + bitOffset: 25 + bitWidth: 3 + access: read-write + - name: WDT_STG0 + description: need_des + bitOffset: 28 + bitWidth: 3 + access: read-write + - name: WDT_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CONFIG1 + description: need_des + addressOffset: 4 + size: 32 + resetValue: 200000 + fields: + - name: WDT_STG0_HOLD + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CONFIG2 + description: need_des + addressOffset: 8 + size: 32 + resetValue: 80000 + fields: + - name: WDT_STG1_HOLD + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CONFIG3 + description: need_des + addressOffset: 12 + size: 32 + resetValue: 4095 + fields: + - name: WDT_STG2_HOLD + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CONFIG4 + description: need_des + addressOffset: 16 + size: 32 + resetValue: 4095 + fields: + - name: WDT_STG3_HOLD + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTFEED + description: need_des + addressOffset: 20 + size: 32 + fields: + - name: RTC_WDT_FEED + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: WDTWPROTECT + description: need_des + addressOffset: 24 + size: 32 + fields: + - name: WDT_WKEY + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SWD_CONF + description: need_des + addressOffset: 28 + size: 32 + resetValue: 314572800 + fields: + - name: SWD_RESET_FLAG + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SWD_AUTO_FEED_EN + description: need_des + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SWD_RST_FLAG_CLR + description: need_des + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: SWD_SIGNAL_WIDTH + description: need_des + bitOffset: 20 + bitWidth: 10 + access: read-write + - name: SWD_DISABLE + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SWD_FEED + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SWD_WPROTECT + description: need_des + addressOffset: 32 + size: 32 + fields: + - name: SWD_WKEY + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: INT_RAW + description: need_des + addressOffset: 36 + size: 32 + fields: + - name: SUPER_WDT_INT_RAW + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_WDT_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_ST_RTC + description: need_des + addressOffset: 40 + size: 32 + fields: + - name: SUPER_WDT_INT_ST + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: WDT_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA_RTC + description: need_des + addressOffset: 44 + size: 32 + fields: + - name: SUPER_WDT_INT_ENA + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: WDT_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR_RTC + description: need_des + addressOffset: 48 + size: 32 + fields: + - name: SUPER_WDT_INT_CLR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: WDT_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 34676864 + fields: + - name: LP_WDT_DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: MCPWM0 + description: Motor Control Pulse-Width Modulation 0 + groupName: MCPWM + baseAddress: 1610694656 + addressBlock: + - offset: 0 + size: 304 + usage: registers + interrupt: + - name: MCPWM0 + value: 61 + registers: + - register: + name: CLK_CFG + description: PWM clock prescaler register. + addressOffset: 0 + size: 32 + fields: + - name: CLK_PRESCALE + description: Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1) + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: TIMER0_CFG0 + description: PWM timer0 period and update method configuration register. + addressOffset: 4 + size: 32 + resetValue: 65280 + fields: + - name: TIMER0_PRESCALE + description: period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1) + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TIMER0_PERIOD + description: period shadow register of PWM timer0 + bitOffset: 8 + bitWidth: 16 + access: read-write + - name: TIMER0_PERIOD_UPMETHOD + description: "Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event" + bitOffset: 24 + bitWidth: 2 + access: read-write + - register: + name: TIMER0_CFG1 + description: PWM timer0 working mode and start/stop control configuration register. + addressOffset: 8 + size: 32 + fields: + - name: TIMER0_START + description: "PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: TIMER0_MOD + description: "PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode" + bitOffset: 3 + bitWidth: 2 + access: read-write + - register: + name: TIMER0_SYNC + description: PWM timer0 sync function configuration register. + addressOffset: 12 + size: 32 + fields: + - name: TIMER0_SYNCI_EN + description: "When set, timer reloading with phase on sync input event is enabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SW + description: Toggling this bit will trigger a software sync. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER0_SYNCO_SEL + description: "PWM timer0 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always generate when toggling the reg_timer0_sync_sw bit" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: TIMER0_PHASE + description: phase for timer reload on sync event + bitOffset: 4 + bitWidth: 16 + access: read-write + - name: TIMER0_PHASE_DIRECTION + description: "Configure the PWM timer0's direction when timer0 mode is up-down mode: 0-increase,1-decrease" + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: TIMER0_STATUS + description: PWM timer0 status register. + addressOffset: 16 + size: 32 + fields: + - name: TIMER0_VALUE + description: current PWM timer0 counter value + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: TIMER0_DIRECTION + description: "current PWM timer0 counter direction, 0: increment 1: decrement" + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: TIMER1_CFG0 + description: PWM timer1 period and update method configuration register. + addressOffset: 20 + size: 32 + resetValue: 65280 + fields: + - name: TIMER1_PRESCALE + description: period of PT0_clk = Period of PWM_clk * (PWM_timer1_PRESCALE + 1) + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TIMER1_PERIOD + description: period shadow register of PWM timer1 + bitOffset: 8 + bitWidth: 16 + access: read-write + - name: TIMER1_PERIOD_UPMETHOD + description: "Update method for active register of PWM timer1 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event" + bitOffset: 24 + bitWidth: 2 + access: read-write + - register: + name: TIMER1_CFG1 + description: PWM timer1 working mode and start/stop control configuration register. + addressOffset: 24 + size: 32 + fields: + - name: TIMER1_START + description: "PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at TEZ, 1: if timer1 starts, then stops at TEP, 2: PWM timer1 starts and runs on, 3: timer1 starts and stops at the next TEZ, 4: timer1 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: TIMER1_MOD + description: "PWM timer1 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode" + bitOffset: 3 + bitWidth: 2 + access: read-write + - register: + name: TIMER1_SYNC + description: PWM timer1 sync function configuration register. + addressOffset: 28 + size: 32 + fields: + - name: TIMER1_SYNCI_EN + description: "When set, timer reloading with phase on sync input event is enabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SW + description: Toggling this bit will trigger a software sync. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER1_SYNCO_SEL + description: "PWM timer1 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always generate when toggling the reg_timer1_sync_sw bit" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: TIMER1_PHASE + description: phase for timer reload on sync event + bitOffset: 4 + bitWidth: 16 + access: read-write + - name: TIMER1_PHASE_DIRECTION + description: "Configure the PWM timer1's direction when timer1 mode is up-down mode: 0-increase,1-decrease" + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: TIMER1_STATUS + description: PWM timer1 status register. + addressOffset: 32 + size: 32 + fields: + - name: TIMER1_VALUE + description: current PWM timer1 counter value + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: TIMER1_DIRECTION + description: "current PWM timer1 counter direction, 0: increment 1: decrement" + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: TIMER2_CFG0 + description: PWM timer2 period and update method configuration register. + addressOffset: 36 + size: 32 + resetValue: 65280 + fields: + - name: TIMER2_PRESCALE + description: period of PT0_clk = Period of PWM_clk * (PWM_timer2_PRESCALE + 1) + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TIMER2_PERIOD + description: period shadow register of PWM timer2 + bitOffset: 8 + bitWidth: 16 + access: read-write + - name: TIMER2_PERIOD_UPMETHOD + description: "Update method for active register of PWM timer2 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event" + bitOffset: 24 + bitWidth: 2 + access: read-write + - register: + name: TIMER2_CFG1 + description: PWM timer2 working mode and start/stop control configuration register. + addressOffset: 40 + size: 32 + fields: + - name: TIMER2_START + description: "PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at TEZ, 1: if timer2 starts, then stops at TEP, 2: PWM timer2 starts and runs on, 3: timer2 starts and stops at the next TEZ, 4: timer2 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: TIMER2_MOD + description: "PWM timer2 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode" + bitOffset: 3 + bitWidth: 2 + access: read-write + - register: + name: TIMER2_SYNC + description: PWM timer2 sync function configuration register. + addressOffset: 44 + size: 32 + fields: + - name: TIMER2_SYNCI_EN + description: "When set, timer reloading with phase on sync input event is enabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SW + description: Toggling this bit will trigger a software sync. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER2_SYNCO_SEL + description: "PWM timer2 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always generate when toggling the reg_timer0_sync_sw bit" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: TIMER2_PHASE + description: phase for timer reload on sync event + bitOffset: 4 + bitWidth: 16 + access: read-write + - name: TIMER2_PHASE_DIRECTION + description: "Configure the PWM timer2's direction when timer2 mode is up-down mode: 0-increase,1-decrease" + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: TIMER2_STATUS + description: PWM timer2 status register. + addressOffset: 48 + size: 32 + fields: + - name: TIMER2_VALUE + description: current PWM timer2 counter value + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: TIMER2_DIRECTION + description: "current PWM timer2 counter direction, 0: increment 1: decrement" + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: TIMER_SYNCI_CFG + description: Synchronization input selection for three PWM timers. + addressOffset: 52 + size: 32 + fields: + - name: TIMER0_SYNCISEL + description: "select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: TIMER1_SYNCISEL + description: "select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected" + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: TIMER2_SYNCISEL + description: "select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: EXTERNAL_SYNCI0_INVERT + description: invert SYNC0 from GPIO matrix + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: EXTERNAL_SYNCI1_INVERT + description: invert SYNC1 from GPIO matrix + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: EXTERNAL_SYNCI2_INVERT + description: invert SYNC2 from GPIO matrix + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: OPERATOR_TIMERSEL + description: Select specific timer for PWM operators. + addressOffset: 56 + size: 32 + fields: + - name: OPERATOR0_TIMERSEL + description: "Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: OPERATOR1_TIMERSEL + description: "Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: OPERATOR2_TIMERSEL + description: "Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2" + bitOffset: 4 + bitWidth: 2 + access: read-write + - register: + name: GEN0_STMP_CFG + description: Transfer status and update method for time stamp registers A and B + addressOffset: 60 + size: 32 + fields: + - name: CMPR0_A_UPMETHOD + description: "Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: CMPR0_B_UPMETHOD + description: "Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: CMPR0_A_SHDW_FULL + description: "Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CMPR0_B_SHDW_FULL + description: "Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value" + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: GEN0_TSTMP_A + description: Shadow register for register A. + addressOffset: 64 + size: 32 + fields: + - name: CMPR0_A + description: "PWM generator 0 time stamp A's shadow register" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: GEN0_TSTMP_B + description: Shadow register for register B. + addressOffset: 68 + size: 32 + fields: + - name: CMPR0_B + description: "PWM generator 0 time stamp B's shadow register" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: GEN0_CFG0 + description: Fault event T0 and T1 handling + addressOffset: 72 + size: 32 + fields: + - name: GEN0_CFG_UPMETHOD + description: "Update method for PWM generator 0's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update" + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: GEN0_T0_SEL + description: "Source selection for PWM generator 0 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none" + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: GEN0_T1_SEL + description: "Source selection for PWM generator 0 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none" + bitOffset: 7 + bitWidth: 3 + access: read-write + - register: + name: GEN0_FORCE + description: Permissives to force PWM0A and PWM0B outputs by software + addressOffset: 76 + size: 32 + resetValue: 32 + fields: + - name: GEN0_CNTUFORCE_UPMETHOD + description: "Updating method for continuous software force of PWM generator0. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.)" + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: GEN0_A_CNTUFORCE_MODE + description: "Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: GEN0_B_CNTUFORCE_MODE + description: "Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: GEN0_A_NCIFORCE + description: "Trigger of non-continuous immediate software-force event for PWM0A, a toggle will trigger a force event." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GEN0_A_NCIFORCE_MODE + description: "non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: GEN0_B_NCIFORCE + description: "Trigger of non-continuous immediate software-force event for PWM0B, a toggle will trigger a force event." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: GEN0_B_NCIFORCE_MODE + description: "non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: GEN0_A + description: Actions triggered by events on PWM0A + addressOffset: 80 + size: 32 + fields: + - name: UTEZ + description: Action on PWM0A triggered by event TEZ when timer increasing + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + description: Action on PWM0A triggered by event TEP when timer increasing + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + description: Action on PWM0A triggered by event TEA when timer increasing + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + description: Action on PWM0A triggered by event TEB when timer increasing + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + description: Action on PWM0A triggered by event_t0 when timer increasing + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + description: Action on PWM0A triggered by event_t1 when timer increasing + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + description: Action on PWM0A triggered by event TEZ when timer decreasing + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + description: Action on PWM0A triggered by event TEP when timer decreasing + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + description: Action on PWM0A triggered by event TEA when timer decreasing + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + description: Action on PWM0A triggered by event TEB when timer decreasing + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + description: Action on PWM0A triggered by event_t0 when timer decreasing + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + description: "Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: GEN0_B + description: Actions triggered by events on PWM0B + addressOffset: 84 + size: 32 + fields: + - name: UTEZ + description: Action on PWM0B triggered by event TEZ when timer increasing + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + description: Action on PWM0B triggered by event TEP when timer increasing + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + description: Action on PWM0B triggered by event TEA when timer increasing + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + description: Action on PWM0B triggered by event TEB when timer increasing + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + description: Action on PWM0B triggered by event_t0 when timer increasing + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + description: Action on PWM0B triggered by event_t1 when timer increasing + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + description: Action on PWM0B triggered by event TEZ when timer decreasing + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + description: Action on PWM0B triggered by event TEP when timer decreasing + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + description: Action on PWM0B triggered by event TEA when timer decreasing + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + description: Action on PWM0B triggered by event TEB when timer decreasing + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + description: Action on PWM0B triggered by event_t0 when timer decreasing + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + description: "Action on PWM0B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: DT0_CFG + description: dead time type selection and configuration + addressOffset: 88 + size: 32 + resetValue: 98304 + fields: + - name: DB0_FED_UPMETHOD + description: "Update method for FED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update" + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: DB0_RED_UPMETHOD + description: "Update method for RED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update" + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: DB0_DEB_MODE + description: "S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DB0_A_OUTSWAP + description: S6 in table + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DB0_B_OUTSWAP + description: S7 in table + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DB0_RED_INSEL + description: S4 in table + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DB0_FED_INSEL + description: S5 in table + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DB0_RED_OUTINVERT + description: S2 in table + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DB0_FED_OUTINVERT + description: S3 in table + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DB0_A_OUTBYPASS + description: S1 in table + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DB0_B_OUTBYPASS + description: S0 in table + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DB0_CLK_SEL + description: "Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk" + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: DT0_FED_CFG + description: Shadow register for falling edge delay (FED). + addressOffset: 92 + size: 32 + fields: + - name: DB0_FED + description: Shadow register for FED + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: DT0_RED_CFG + description: Shadow register for rising edge delay (RED). + addressOffset: 96 + size: 32 + fields: + - name: DB0_RED + description: Shadow register for RED + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: CARRIER0_CFG + description: Carrier enable and configuratoin + addressOffset: 100 + size: 32 + fields: + - name: CHOPPER0_EN + description: "When set, carrier0 function is enabled. When cleared, carrier0 is bypassed" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CHOPPER0_PRESCALE + description: PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CHOPPER0_DUTY + description: carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + bitOffset: 5 + bitWidth: 3 + access: read-write + - name: CHOPPER0_OSHTWTH + description: width of the first pulse in number of periods of the carrier + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: CHOPPER0_OUT_INVERT + description: "when set, invert the output of PWM0A and PWM0B for this submodule" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CHOPPER0_IN_INVERT + description: "when set, invert the input of PWM0A and PWM0B for this submodule" + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: FH0_CFG0 + description: Actions on PWM0A and PWM0B trip events + addressOffset: 104 + size: 32 + fields: + - name: TZ0_SW_CBC + description: "Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TZ0_F2_CBC + description: "event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TZ0_F1_CBC + description: "event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TZ0_F0_CBC + description: "event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TZ0_SW_OST + description: "Enable register for software force one-shot mode action. 0: disable, 1: enable" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TZ0_F2_OST + description: "event_f2 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TZ0_F1_OST + description: "event_f1 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TZ0_F0_OST + description: "event_f0 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TZ0_A_CBC_D + description: "Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: TZ0_A_CBC_U + description: "Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: TZ0_A_OST_D + description: "One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: TZ0_A_OST_U + description: "One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: TZ0_B_CBC_D + description: "Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: TZ0_B_CBC_U + description: "Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing,1: force low, 2: force high, 3: toggle" + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: TZ0_B_OST_D + description: "One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TZ0_B_OST_U + description: "One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: FH0_CFG1 + description: Software triggers for fault handler actions + addressOffset: 108 + size: 32 + fields: + - name: TZ0_CLR_OST + description: a rising edge will clear on going one-shot mode action + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TZ0_CBCPULSE + description: "cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP" + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: TZ0_FORCE_CBC + description: a toggle trigger a cycle-by-cycle mode action + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TZ0_FORCE_OST + description: a toggle (software negate its value) triggers a one-shot mode action + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: FH0_STATUS + description: Status of fault events. + addressOffset: 112 + size: 32 + fields: + - name: TZ0_CBC_ON + description: "Set and reset by hardware. If set, a cycle-by-cycle mode action is on going" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TZ0_OST_ON + description: "Set and reset by hardware. If set, an one-shot mode action is on going" + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: GEN1_STMP_CFG + description: Transfer status and update method for time stamp registers A and B + addressOffset: 116 + size: 32 + fields: + - name: CMPR1_A_UPMETHOD + description: "Update method for PWM generator 1 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: CMPR1_B_UPMETHOD + description: "Update method for PWM generator 1 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: CMPR1_A_SHDW_FULL + description: "Set and reset by hardware. If set, PWM generator 1 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CMPR1_B_SHDW_FULL + description: "Set and reset by hardware. If set, PWM generator 1 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value" + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: GEN1_TSTMP_A + description: Shadow register for register A. + addressOffset: 120 + size: 32 + fields: + - name: CMPR1_A + description: "PWM generator 1 time stamp A's shadow register" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: GEN1_TSTMP_B + description: Shadow register for register B. + addressOffset: 124 + size: 32 + fields: + - name: CMPR1_B + description: "PWM generator 1 time stamp B's shadow register" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: GEN1_CFG0 + description: Fault event T0 and T1 handling + addressOffset: 128 + size: 32 + fields: + - name: GEN1_CFG_UPMETHOD + description: "Update method for PWM generator 1's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:sync;when bit3 is set to 1:disable the update." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: GEN1_T0_SEL + description: "Source selection for PWM generator 1 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none" + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: GEN1_T1_SEL + description: "Source selection for PWM generator 1 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none" + bitOffset: 7 + bitWidth: 3 + access: read-write + - register: + name: GEN1_FORCE + description: Permissives to force PWM1A and PWM1B outputs by software + addressOffset: 132 + size: 32 + resetValue: 32 + fields: + - name: GEN1_CNTUFORCE_UPMETHOD + description: "Updating method for continuous software force of PWM generator 1. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.)" + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: GEN1_A_CNTUFORCE_MODE + description: "Continuous software force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: GEN1_B_CNTUFORCE_MODE + description: "Continuous software force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: GEN1_A_NCIFORCE + description: "Trigger of non-continuous immediate software-force event for PWM1A, a toggle will trigger a force event." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GEN1_A_NCIFORCE_MODE + description: "non-continuous immediate software force mode for PWM1A, 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: GEN1_B_NCIFORCE + description: "Trigger of non-continuous immediate software-force event for PWM1B, a toggle will trigger a force event." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: GEN1_B_NCIFORCE_MODE + description: "non-continuous immediate software force mode for PWM1B, 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: GEN1_A + description: Actions triggered by events on PWM1A + addressOffset: 136 + size: 32 + fields: + - name: UTEZ + description: Action on PWM1A triggered by event TEZ when timer increasing + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + description: Action on PWM1A triggered by event TEP when timer increasing + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + description: Action on PWM1A triggered by event TEA when timer increasing + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + description: Action on PWM1A triggered by event TEB when timer increasing + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + description: Action on PWM1A triggered by event_t0 when timer increasing + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + description: Action on PWM1A triggered by event_t1 when timer increasing + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + description: Action on PWM1A triggered by event TEZ when timer decreasing + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + description: Action on PWM1A triggered by event TEP when timer decreasing + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + description: Action on PWM1A triggered by event TEA when timer decreasing + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + description: Action on PWM1A triggered by event TEB when timer decreasing + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + description: Action on PWM1A triggered by event_t0 when timer decreasing + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + description: "Action on PWM1A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: GEN1_B + description: Actions triggered by events on PWM1B + addressOffset: 140 + size: 32 + fields: + - name: UTEZ + description: Action on PWM1B triggered by event TEZ when timer increasing + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + description: Action on PWM1B triggered by event TEP when timer increasing + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + description: Action on PWM1B triggered by event TEA when timer increasing + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + description: Action on PWM1B triggered by event TEB when timer increasing + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + description: Action on PWM1B triggered by event_t0 when timer increasing + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + description: Action on PWM1B triggered by event_t1 when timer increasing + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + description: Action on PWM1B triggered by event TEZ when timer decreasing + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + description: Action on PWM1B triggered by event TEP when timer decreasing + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + description: Action on PWM1B triggered by event TEA when timer decreasing + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + description: Action on PWM1B triggered by event TEB when timer decreasing + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + description: Action on PWM1B triggered by event_t0 when timer decreasing + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + description: "Action on PWM1B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: DT1_CFG + description: dead time type selection and configuration + addressOffset: 144 + size: 32 + resetValue: 98304 + fields: + - name: DB1_FED_UPMETHOD + description: "Update method for FED (falling edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update" + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: DB1_RED_UPMETHOD + description: "Update method for RED (rising edge delay) active register. 0: immediate,when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update" + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: DB1_DEB_MODE + description: "S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DB1_A_OUTSWAP + description: S6 in table + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DB1_B_OUTSWAP + description: S7 in table + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DB1_RED_INSEL + description: S4 in table + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DB1_FED_INSEL + description: S5 in table + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DB1_RED_OUTINVERT + description: S2 in table + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DB1_FED_OUTINVERT + description: S3 in table + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DB1_A_OUTBYPASS + description: S1 in table + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DB1_B_OUTBYPASS + description: S0 in table + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DB1_CLK_SEL + description: "Dead time generator 1 clock selection. 0: PWM_clk, 1: PT_clk" + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: DT1_FED_CFG + description: Shadow register for falling edge delay (FED). + addressOffset: 148 + size: 32 + fields: + - name: DB1_FED + description: Shadow register for FED + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: DT1_RED_CFG + description: Shadow register for rising edge delay (RED). + addressOffset: 152 + size: 32 + fields: + - name: DB1_RED + description: Shadow register for RED + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: CARRIER1_CFG + description: Carrier enable and configuratoin + addressOffset: 156 + size: 32 + fields: + - name: CHOPPER1_EN + description: "When set, carrier1 function is enabled. When cleared, carrier1 is bypassed" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CHOPPER1_PRESCALE + description: PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CHOPPER1_DUTY + description: carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + bitOffset: 5 + bitWidth: 3 + access: read-write + - name: CHOPPER1_OSHTWTH + description: width of the first pulse in number of periods of the carrier + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: CHOPPER1_OUT_INVERT + description: "when set, invert the output of PWM1A and PWM1B for this submodule" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CHOPPER1_IN_INVERT + description: "when set, invert the input of PWM1A and PWM1B for this submodule" + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: FH1_CFG0 + description: Actions on PWM1A and PWM1B trip events + addressOffset: 160 + size: 32 + fields: + - name: TZ1_SW_CBC + description: "Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TZ1_F2_CBC + description: "event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TZ1_F1_CBC + description: "event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TZ1_F0_CBC + description: "event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TZ1_SW_OST + description: "Enable register for software force one-shot mode action. 0: disable, 1: enable" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TZ1_F2_OST + description: "event_f2 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TZ1_F1_OST + description: "event_f1 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TZ1_F0_OST + description: "event_f0 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TZ1_A_CBC_D + description: "Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: TZ1_A_CBC_U + description: "Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: TZ1_A_OST_D + description: "One-shot mode action on PWM1A when fault event occurs and timer is decreasing. 0: do nothing,1: force low, 2: force high, 3: toggle" + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: TZ1_A_OST_U + description: "One-shot mode action on PWM1A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: TZ1_B_CBC_D + description: "Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: TZ1_B_CBC_U + description: "Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: TZ1_B_OST_D + description: "One-shot mode action on PWM1B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TZ1_B_OST_U + description: "One-shot mode action on PWM1B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: FH1_CFG1 + description: Software triggers for fault handler actions + addressOffset: 164 + size: 32 + fields: + - name: TZ1_CLR_OST + description: a rising edge will clear on going one-shot mode action + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TZ1_CBCPULSE + description: "cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP" + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: TZ1_FORCE_CBC + description: a toggle trigger a cycle-by-cycle mode action + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TZ1_FORCE_OST + description: a toggle (software negate its value) triggers a one-shot mode action + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: FH1_STATUS + description: Status of fault events. + addressOffset: 168 + size: 32 + fields: + - name: TZ1_CBC_ON + description: "Set and reset by hardware. If set, a cycle-by-cycle mode action is on going" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TZ1_OST_ON + description: "Set and reset by hardware. If set, an one-shot mode action is on going" + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: GEN2_STMP_CFG + description: Transfer status and update method for time stamp registers A and B + addressOffset: 172 + size: 32 + fields: + - name: CMPR2_A_UPMETHOD + description: "Update method for PWM generator 2 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: CMPR2_B_UPMETHOD + description: "Update method for PWM generator 2 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: CMPR2_A_SHDW_FULL + description: "Set and reset by hardware. If set, PWM generator 2 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CMPR2_B_SHDW_FULL + description: "Set and reset by hardware. If set, PWM generator 2 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value" + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: GEN2_TSTMP_A + description: Shadow register for register A. + addressOffset: 176 + size: 32 + fields: + - name: CMPR2_A + description: "PWM generator 2 time stamp A's shadow register" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: GEN2_TSTMP_B + description: Shadow register for register B. + addressOffset: 180 + size: 32 + fields: + - name: CMPR2_B + description: "PWM generator 2 time stamp B's shadow register" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: GEN2_CFG0 + description: Fault event T0 and T1 handling + addressOffset: 184 + size: 32 + fields: + - name: GEN2_CFG_UPMETHOD + description: "Update method for PWM generator 2's active register of configuration. 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:sync;when bit3 is set to 1:disable the update." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: GEN2_T0_SEL + description: "Source selection for PWM generator 2 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none" + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: GEN2_T1_SEL + description: "Source selection for PWM generator 2 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none" + bitOffset: 7 + bitWidth: 3 + access: read-write + - register: + name: GEN2_FORCE + description: Permissives to force PWM2A and PWM2B outputs by software + addressOffset: 188 + size: 32 + resetValue: 32 + fields: + - name: GEN2_CNTUFORCE_UPMETHOD + description: "Updating method for continuous software force of PWM generator 2. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.)" + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: GEN2_A_CNTUFORCE_MODE + description: "Continuous software force mode for PWM2A. 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: GEN2_B_CNTUFORCE_MODE + description: "Continuous software force mode for PWM2B. 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: GEN2_A_NCIFORCE + description: "Trigger of non-continuous immediate software-force event for PWM2A, a toggle will trigger a force event." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GEN2_A_NCIFORCE_MODE + description: "non-continuous immediate software force mode for PWM2A, 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: GEN2_B_NCIFORCE + description: "Trigger of non-continuous immediate software-force event for PWM2B, a toggle will trigger a force event." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: GEN2_B_NCIFORCE_MODE + description: "non-continuous immediate software force mode for PWM2B, 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: GEN2_A + description: Actions triggered by events on PWM2A + addressOffset: 192 + size: 32 + fields: + - name: UTEZ + description: Action on PWM2A triggered by event TEZ when timer increasing + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + description: Action on PWM2A triggered by event TEP when timer increasing + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + description: Action on PWM2A triggered by event TEA when timer increasing + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + description: Action on PWM2A triggered by event TEB when timer increasing + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + description: Action on PWM2A triggered by event_t0 when timer increasing + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + description: Action on PWM2A triggered by event_t1 when timer increasing + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + description: Action on PWM2A triggered by event TEZ when timer decreasing + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + description: Action on PWM2A triggered by event TEP when timer decreasing + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + description: Action on PWM2A triggered by event TEA when timer decreasing + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + description: Action on PWM2A triggered by event TEB when timer decreasing + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + description: Action on PWM2A triggered by event_t0 when timer decreasing + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + description: "Action on PWM2A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: GEN2_B + description: Actions triggered by events on PWM2B + addressOffset: 196 + size: 32 + fields: + - name: UTEZ + description: Action on PWM2B triggered by event TEZ when timer increasing + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + description: Action on PWM2B triggered by event TEP when timer increasing + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + description: Action on PWM2B triggered by event TEA when timer increasing + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + description: Action on PWM2B triggered by event TEB when timer increasing + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + description: Action on PWM2B triggered by event_t0 when timer increasing + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + description: Action on PWM2B triggered by event_t1 when timer increasing + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + description: Action on PWM2B triggered by event TEZ when timer decreasing + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + description: Action on PWM2B triggered by event TEP when timer decreasing + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + description: Action on PWM2B triggered by event TEA when timer decreasing + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + description: Action on PWM2B triggered by event TEB when timer decreasing + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + description: Action on PWM2B triggered by event_t0 when timer decreasing + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + description: "Action on PWM2B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: DT2_CFG + description: dead time type selection and configuration + addressOffset: 200 + size: 32 + resetValue: 98304 + fields: + - name: DB2_FED_UPMETHOD + description: "Update method for FED (falling edge delay) active register. 0: immediate,when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update" + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: DB2_RED_UPMETHOD + description: "Update method for RED (rising edge delay) active register. 0: immediate,when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update" + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: DB2_DEB_MODE + description: "S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DB2_A_OUTSWAP + description: S6 in table + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DB2_B_OUTSWAP + description: S7 in table + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DB2_RED_INSEL + description: S4 in table + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DB2_FED_INSEL + description: S5 in table + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DB2_RED_OUTINVERT + description: S2 in table + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DB2_FED_OUTINVERT + description: S3 in table + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DB2_A_OUTBYPASS + description: S1 in table + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DB2_B_OUTBYPASS + description: S0 in table + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DB2_CLK_SEL + description: "Dead time generator 2 clock selection. 0: PWM_clk, 1: PT_clk" + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: DT2_FED_CFG + description: Shadow register for falling edge delay (FED). + addressOffset: 204 + size: 32 + fields: + - name: DB2_FED + description: Shadow register for FED + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: DT2_RED_CFG + description: Shadow register for rising edge delay (RED). + addressOffset: 208 + size: 32 + fields: + - name: DB2_RED + description: Shadow register for RED + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: CARRIER2_CFG + description: Carrier enable and configuratoin + addressOffset: 212 + size: 32 + fields: + - name: CHOPPER2_EN + description: "When set, carrier2 function is enabled. When cleared, carrier2 is bypassed" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CHOPPER2_PRESCALE + description: PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CHOPPER2_DUTY + description: carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + bitOffset: 5 + bitWidth: 3 + access: read-write + - name: CHOPPER2_OSHTWTH + description: width of the first pulse in number of periods of the carrier + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: CHOPPER2_OUT_INVERT + description: "when set, invert the output of PWM2A and PWM2B for this submodule" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CHOPPER2_IN_INVERT + description: "when set, invert the input of PWM2A and PWM2B for this submodule" + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: FH2_CFG0 + description: Actions on PWM2A and PWM2B trip events + addressOffset: 216 + size: 32 + fields: + - name: TZ2_SW_CBC + description: "Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TZ2_F2_CBC + description: "event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TZ2_F1_CBC + description: "event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TZ2_F0_CBC + description: "event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TZ2_SW_OST + description: "Enable register for software force one-shot mode action. 0: disable, 1: enable" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TZ2_F2_OST + description: "event_f2 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TZ2_F1_OST + description: "event_f1 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TZ2_F0_OST + description: "event_f0 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TZ2_A_CBC_D + description: "Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: TZ2_A_CBC_U + description: "Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: TZ2_A_OST_D + description: "One-shot mode action on PWM2A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: TZ2_A_OST_U + description: "One-shot mode action on PWM2A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: TZ2_B_CBC_D + description: "Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: TZ2_B_CBC_U + description: "Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: TZ2_B_OST_D + description: "One-shot mode action on PWM2B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TZ2_B_OST_U + description: "One-shot mode action on PWM2B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: FH2_CFG1 + description: Software triggers for fault handler actions + addressOffset: 220 + size: 32 + fields: + - name: TZ2_CLR_OST + description: a rising edge will clear on going one-shot mode action + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TZ2_CBCPULSE + description: "cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP" + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: TZ2_FORCE_CBC + description: a toggle trigger a cycle-by-cycle mode action + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TZ2_FORCE_OST + description: a toggle (software negate its value) triggers a one-shot mode action + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: FH2_STATUS + description: Status of fault events. + addressOffset: 224 + size: 32 + fields: + - name: TZ2_CBC_ON + description: "Set and reset by hardware. If set, a cycle-by-cycle mode action is on going" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TZ2_OST_ON + description: "Set and reset by hardware. If set, an one-shot mode action is on going" + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: FAULT_DETECT + description: Fault detection configuration and status + addressOffset: 228 + size: 32 + fields: + - name: F0_EN + description: "When set, event_f0 generation is enabled" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: F1_EN + description: "When set, event_f1 generation is enabled" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: F2_EN + description: "When set, event_f2 generation is enabled" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: F0_POLE + description: "Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: F1_POLE + description: "Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: F2_POLE + description: "Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: EVENT_F0 + description: "Set and reset by hardware. If set, event_f0 is on going" + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: EVENT_F1 + description: "Set and reset by hardware. If set, event_f1 is on going" + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: EVENT_F2 + description: "Set and reset by hardware. If set, event_f2 is on going" + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: CAP_TIMER_CFG + description: Configure capture timer + addressOffset: 232 + size: 32 + fields: + - name: CAP_TIMER_EN + description: "When set, capture timer incrementing under APB_clk is enabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CAP_SYNCI_EN + description: "When set, capture timer sync is enabled." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CAP_SYNCI_SEL + description: "capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix" + bitOffset: 2 + bitWidth: 3 + access: read-write + - name: CAP_SYNC_SW + description: "When reg_cap_synci_en is 1, write 1 will trigger a capture timer sync, capture timer is loaded with value in phase register." + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: CAP_TIMER_PHASE + description: Phase for capture timer sync + addressOffset: 236 + size: 32 + fields: + - name: CAP_PHASE + description: Phase value for capture timer sync operation. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CAP_CH0_CFG + description: Capture channel 0 configuration and enable + addressOffset: 240 + size: 32 + fields: + - name: CAP0_EN + description: "When set, capture on channel 0 is enabled" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CAP0_MODE + description: "Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge." + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: CAP0_PRESCALE + description: Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1 + bitOffset: 3 + bitWidth: 8 + access: read-write + - name: CAP0_IN_INVERT + description: "when set, CAP0 form GPIO matrix is inverted before prescale" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CAP0_SW + description: Write 1 will trigger a software forced capture on channel 0 + bitOffset: 12 + bitWidth: 1 + access: write-only + - register: + name: CAP_CH1_CFG + description: Capture channel 1 configuration and enable + addressOffset: 244 + size: 32 + fields: + - name: CAP1_EN + description: "When set, capture on channel 2 is enabled" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CAP1_MODE + description: "Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge." + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: CAP1_PRESCALE + description: Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE + 1 + bitOffset: 3 + bitWidth: 8 + access: read-write + - name: CAP1_IN_INVERT + description: "when set, CAP1 form GPIO matrix is inverted before prescale" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CAP1_SW + description: Write 1 will trigger a software forced capture on channel 1 + bitOffset: 12 + bitWidth: 1 + access: write-only + - register: + name: CAP_CH2_CFG + description: Capture channel 2 configuration and enable + addressOffset: 248 + size: 32 + fields: + - name: CAP2_EN + description: "When set, capture on channel 2 is enabled" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CAP2_MODE + description: "Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge." + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: CAP2_PRESCALE + description: Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE + 1 + bitOffset: 3 + bitWidth: 8 + access: read-write + - name: CAP2_IN_INVERT + description: "when set, CAP2 form GPIO matrix is inverted before prescale" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CAP2_SW + description: Write 1 will trigger a software forced capture on channel 2 + bitOffset: 12 + bitWidth: 1 + access: write-only + - register: + name: CAP_CH0 + description: ch0 capture value status register + addressOffset: 252 + size: 32 + fields: + - name: CAP0_VALUE + description: Value of last capture on channel 0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CAP_CH1 + description: ch1 capture value status register + addressOffset: 256 + size: 32 + fields: + - name: CAP1_VALUE + description: Value of last capture on channel 1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CAP_CH2 + description: ch2 capture value status register + addressOffset: 260 + size: 32 + fields: + - name: CAP2_VALUE + description: Value of last capture on channel 2 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CAP_STATUS + description: Edge of last capture trigger + addressOffset: 264 + size: 32 + fields: + - name: CAP0_EDGE + description: "Edge of last capture trigger on channel 0, 0: posedge, 1: negedge" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CAP1_EDGE + description: "Edge of last capture trigger on channel 1, 0: posedge, 1: negedge" + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CAP2_EDGE + description: "Edge of last capture trigger on channel 2, 0: posedge, 1: negedge" + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: UPDATE_CFG + description: Enable update. + addressOffset: 268 + size: 32 + resetValue: 85 + fields: + - name: GLOBAL_UP_EN + description: The global enable of update of all active registers in MCPWM module + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: GLOBAL_FORCE_UP + description: a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OP0_UP_EN + description: "When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 are enabled" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OP0_FORCE_UP + description: a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OP1_UP_EN + description: "When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 are enabled" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OP1_FORCE_UP + description: a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OP2_UP_EN + description: "When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 are enabled" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OP2_FORCE_UP + description: a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2 + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 272 + size: 32 + fields: + - name: TIMER0_STOP_INT_ENA + description: The enable bit for the interrupt triggered when the timer 0 stops. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMER1_STOP_INT_ENA + description: The enable bit for the interrupt triggered when the timer 1 stops. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER2_STOP_INT_ENA + description: The enable bit for the interrupt triggered when the timer 2 stops. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TIMER0_TEZ_INT_ENA + description: The enable bit for the interrupt triggered by a PWM timer 0 TEZ event. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TIMER1_TEZ_INT_ENA + description: The enable bit for the interrupt triggered by a PWM timer 1 TEZ event. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TIMER2_TEZ_INT_ENA + description: The enable bit for the interrupt triggered by a PWM timer 2 TEZ event. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TIMER0_TEP_INT_ENA + description: The enable bit for the interrupt triggered by a PWM timer 0 TEP event. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TIMER1_TEP_INT_ENA + description: The enable bit for the interrupt triggered by a PWM timer 1 TEP event. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TIMER2_TEP_INT_ENA + description: The enable bit for the interrupt triggered by a PWM timer 2 TEP event. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FAULT0_INT_ENA + description: The enable bit for the interrupt triggered when event_f0 starts. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FAULT1_INT_ENA + description: The enable bit for the interrupt triggered when event_f1 starts. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FAULT2_INT_ENA + description: The enable bit for the interrupt triggered when event_f2 starts. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FAULT0_CLR_INT_ENA + description: The enable bit for the interrupt triggered when event_f0 ends. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FAULT1_CLR_INT_ENA + description: The enable bit for the interrupt triggered when event_f1 ends. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FAULT2_CLR_INT_ENA + description: The enable bit for the interrupt triggered when event_f2 ends. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CMPR0_TEA_INT_ENA + description: The enable bit for the interrupt triggered by a PWM operator 0 TEA event + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CMPR1_TEA_INT_ENA + description: The enable bit for the interrupt triggered by a PWM operator 1 TEA event + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CMPR2_TEA_INT_ENA + description: The enable bit for the interrupt triggered by a PWM operator 2 TEA event + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: CMPR0_TEB_INT_ENA + description: The enable bit for the interrupt triggered by a PWM operator 0 TEB event + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: CMPR1_TEB_INT_ENA + description: The enable bit for the interrupt triggered by a PWM operator 1 TEB event + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: CMPR2_TEB_INT_ENA + description: The enable bit for the interrupt triggered by a PWM operator 2 TEB event + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TZ0_CBC_INT_ENA + description: The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: TZ1_CBC_INT_ENA + description: The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TZ2_CBC_INT_ENA + description: The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TZ0_OST_INT_ENA + description: The enable bit for the interrupt triggered by a one-shot mode action on PWM0. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TZ1_OST_INT_ENA + description: The enable bit for the interrupt triggered by a one-shot mode action on PWM1. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TZ2_OST_INT_ENA + description: The enable bit for the interrupt triggered by a one-shot mode action on PWM2. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CAP0_INT_ENA + description: The enable bit for the interrupt triggered by capture on channel 0. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: CAP1_INT_ENA + description: The enable bit for the interrupt triggered by capture on channel 1. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CAP2_INT_ENA + description: The enable bit for the interrupt triggered by capture on channel 2. + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 276 + size: 32 + fields: + - name: TIMER0_STOP_INT_RAW + description: The raw status bit for the interrupt triggered when the timer 0 stops. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMER1_STOP_INT_RAW + description: The raw status bit for the interrupt triggered when the timer 1 stops. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER2_STOP_INT_RAW + description: The raw status bit for the interrupt triggered when the timer 2 stops. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TIMER0_TEZ_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TIMER1_TEZ_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TIMER2_TEZ_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TIMER0_TEP_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM timer 0 TEP event. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TIMER1_TEP_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM timer 1 TEP event. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TIMER2_TEP_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM timer 2 TEP event. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FAULT0_INT_RAW + description: The raw status bit for the interrupt triggered when event_f0 starts. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FAULT1_INT_RAW + description: The raw status bit for the interrupt triggered when event_f1 starts. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FAULT2_INT_RAW + description: The raw status bit for the interrupt triggered when event_f2 starts. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FAULT0_CLR_INT_RAW + description: The raw status bit for the interrupt triggered when event_f0 ends. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FAULT1_CLR_INT_RAW + description: The raw status bit for the interrupt triggered when event_f1 ends. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FAULT2_CLR_INT_RAW + description: The raw status bit for the interrupt triggered when event_f2 ends. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CMPR0_TEA_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM operator 0 TEA event + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CMPR1_TEA_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM operator 1 TEA event + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CMPR2_TEA_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM operator 2 TEA event + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: CMPR0_TEB_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM operator 0 TEB event + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: CMPR1_TEB_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM operator 1 TEB event + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: CMPR2_TEB_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM operator 2 TEB event + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TZ0_CBC_INT_RAW + description: The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: TZ1_CBC_INT_RAW + description: The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TZ2_CBC_INT_RAW + description: The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TZ0_OST_INT_RAW + description: The raw status bit for the interrupt triggered by a one-shot mode action on PWM0. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TZ1_OST_INT_RAW + description: The raw status bit for the interrupt triggered by a one-shot mode action on PWM1. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TZ2_OST_INT_RAW + description: The raw status bit for the interrupt triggered by a one-shot mode action on PWM2. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CAP0_INT_RAW + description: The raw status bit for the interrupt triggered by capture on channel 0. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: CAP1_INT_RAW + description: The raw status bit for the interrupt triggered by capture on channel 1. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CAP2_INT_RAW + description: The raw status bit for the interrupt triggered by capture on channel 2. + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 280 + size: 32 + fields: + - name: TIMER0_STOP_INT_ST + description: The masked status bit for the interrupt triggered when the timer 0 stops. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TIMER1_STOP_INT_ST + description: The masked status bit for the interrupt triggered when the timer 1 stops. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TIMER2_STOP_INT_ST + description: The masked status bit for the interrupt triggered when the timer 2 stops. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TIMER0_TEZ_INT_ST + description: The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TIMER1_TEZ_INT_ST + description: The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TIMER2_TEZ_INT_ST + description: The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: TIMER0_TEP_INT_ST + description: The masked status bit for the interrupt triggered by a PWM timer 0 TEP event. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TIMER1_TEP_INT_ST + description: The masked status bit for the interrupt triggered by a PWM timer 1 TEP event. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIMER2_TEP_INT_ST + description: The masked status bit for the interrupt triggered by a PWM timer 2 TEP event. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: FAULT0_INT_ST + description: The masked status bit for the interrupt triggered when event_f0 starts. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: FAULT1_INT_ST + description: The masked status bit for the interrupt triggered when event_f1 starts. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: FAULT2_INT_ST + description: The masked status bit for the interrupt triggered when event_f2 starts. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: FAULT0_CLR_INT_ST + description: The masked status bit for the interrupt triggered when event_f0 ends. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: FAULT1_CLR_INT_ST + description: The masked status bit for the interrupt triggered when event_f1 ends. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: FAULT2_CLR_INT_ST + description: The masked status bit for the interrupt triggered when event_f2 ends. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: CMPR0_TEA_INT_ST + description: The masked status bit for the interrupt triggered by a PWM operator 0 TEA event + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: CMPR1_TEA_INT_ST + description: The masked status bit for the interrupt triggered by a PWM operator 1 TEA event + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: CMPR2_TEA_INT_ST + description: The masked status bit for the interrupt triggered by a PWM operator 2 TEA event + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: CMPR0_TEB_INT_ST + description: The masked status bit for the interrupt triggered by a PWM operator 0 TEB event + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: CMPR1_TEB_INT_ST + description: The masked status bit for the interrupt triggered by a PWM operator 1 TEB event + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: CMPR2_TEB_INT_ST + description: The masked status bit for the interrupt triggered by a PWM operator 2 TEB event + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: TZ0_CBC_INT_ST + description: The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: TZ1_CBC_INT_ST + description: The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: TZ2_CBC_INT_ST + description: The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: TZ0_OST_INT_ST + description: The masked status bit for the interrupt triggered by a one-shot mode action on PWM0. + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: TZ1_OST_INT_ST + description: The masked status bit for the interrupt triggered by a one-shot mode action on PWM1. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: TZ2_OST_INT_ST + description: The masked status bit for the interrupt triggered by a one-shot mode action on PWM2. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: CAP0_INT_ST + description: The masked status bit for the interrupt triggered by capture on channel 0. + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: CAP1_INT_ST + description: The masked status bit for the interrupt triggered by capture on channel 1. + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: CAP2_INT_ST + description: The masked status bit for the interrupt triggered by capture on channel 2. + bitOffset: 29 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 284 + size: 32 + fields: + - name: TIMER0_STOP_INT_CLR + description: Set this bit to clear the interrupt triggered when the timer 0 stops. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TIMER1_STOP_INT_CLR + description: Set this bit to clear the interrupt triggered when the timer 1 stops. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TIMER2_STOP_INT_CLR + description: Set this bit to clear the interrupt triggered when the timer 2 stops. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TIMER0_TEZ_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TIMER1_TEZ_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: TIMER2_TEZ_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TIMER0_TEP_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TIMER1_TEP_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: TIMER2_TEP_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: FAULT0_INT_CLR + description: Set this bit to clear the interrupt triggered when event_f0 starts. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: FAULT1_INT_CLR + description: Set this bit to clear the interrupt triggered when event_f1 starts. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: FAULT2_INT_CLR + description: Set this bit to clear the interrupt triggered when event_f2 starts. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: FAULT0_CLR_INT_CLR + description: Set this bit to clear the interrupt triggered when event_f0 ends. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: FAULT1_CLR_INT_CLR + description: Set this bit to clear the interrupt triggered when event_f1 ends. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: FAULT2_CLR_INT_CLR + description: Set this bit to clear the interrupt triggered when event_f2 ends. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: CMPR0_TEA_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: CMPR1_TEA_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: CMPR2_TEA_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: CMPR0_TEB_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: CMPR1_TEB_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: CMPR2_TEB_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: TZ0_CBC_INT_CLR + description: Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0. + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: TZ1_CBC_INT_CLR + description: Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1. + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: TZ2_CBC_INT_CLR + description: Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2. + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: TZ0_OST_INT_CLR + description: Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0. + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: TZ1_OST_INT_CLR + description: Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1. + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: TZ2_OST_INT_CLR + description: Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2. + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: CAP0_INT_CLR + description: Set this bit to clear the interrupt triggered by capture on channel 0. + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: CAP1_INT_CLR + description: Set this bit to clear the interrupt triggered by capture on channel 1. + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: CAP2_INT_CLR + description: Set this bit to clear the interrupt triggered by capture on channel 2. + bitOffset: 29 + bitWidth: 1 + access: write-only + - register: + name: EVT_EN + description: MCPWM event enable register + addressOffset: 288 + size: 32 + fields: + - name: EVT_TIMER0_STOP_EN + description: set this bit high to enable timer0 stop event generate + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EVT_TIMER1_STOP_EN + description: set this bit high to enable timer1 stop event generate + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EVT_TIMER2_STOP_EN + description: set this bit high to enable timer2 stop event generate + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EVT_TIMER0_TEZ_EN + description: set this bit high to enable timer0 equal zero event generate + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: EVT_TIMER1_TEZ_EN + description: set this bit high to enable timer1 equal zero event generate + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: EVT_TIMER2_TEZ_EN + description: set this bit high to enable timer2 equal zero event generate + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: EVT_TIMER0_TEP_EN + description: set this bit high to enable timer0 equal period event generate + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: EVT_TIMER1_TEP_EN + description: set this bit high to enable timer1 equal period event generate + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: EVT_TIMER2_TEP_EN + description: set this bit high to enable timer2 equal period event generate + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: EVT_OP0_TEA_EN + description: set this bit high to enable PWM generator0 timer equal a event generate + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: EVT_OP1_TEA_EN + description: set this bit high to enable PWM generator1 timer equal a event generate + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: EVT_OP2_TEA_EN + description: set this bit high to enable PWM generator2 timer equal a event generate + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: EVT_OP0_TEB_EN + description: set this bit high to enable PWM generator0 timer equal b event generate + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: EVT_OP1_TEB_EN + description: set this bit high to enable PWM generator1 timer equal b event generate + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: EVT_OP2_TEB_EN + description: set this bit high to enable PWM generator2 timer equal b event generate + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: EVT_F0_EN + description: set this bit high to enable fault0 event generate + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: EVT_F1_EN + description: set this bit high to enable fault1 event generate + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: EVT_F2_EN + description: set this bit high to enable fault2 event generate + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: EVT_F0_CLR_EN + description: set this bit high to enable fault0 clear event generate + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: EVT_F1_CLR_EN + description: set this bit high to enable fault1 clear event generate + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: EVT_F2_CLR_EN + description: set this bit high to enable fault2 clear event generate + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: EVT_TZ0_CBC_EN + description: set this bit high to enable cycle by cycle trip0 event generate + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: EVT_TZ1_CBC_EN + description: set this bit high to enable cycle by cycle trip1 event generate + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: EVT_TZ2_CBC_EN + description: set this bit high to enable cycle by cycle trip2 event generate + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: EVT_TZ0_OST_EN + description: set this bit high to enable one shot trip0 event generate + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: EVT_TZ1_OST_EN + description: set this bit high to enable one shot trip1 event generate + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: EVT_TZ2_OST_EN + description: set this bit high to enable one shot trip2 event generate + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: EVT_CAP0_EN + description: set this bit high to enable capture0 event generate + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: EVT_CAP1_EN + description: set this bit high to enable capture1 event generate + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: EVT_CAP2_EN + description: set this bit high to enable capture2 event generate + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: TASK_EN + description: MCPWM task enable register + addressOffset: 292 + size: 32 + fields: + - name: TASK_CMPR0_A_UP_EN + description: "set this bit high to enable PWM generator0 timer stamp A's shadow register update task receive" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TASK_CMPR1_A_UP_EN + description: "set this bit high to enable PWM generator1 timer stamp A's shadow register update task receive" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TASK_CMPR2_A_UP_EN + description: "set this bit high to enable PWM generator2 timer stamp A's shadow register update task receive" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TASK_CMPR0_B_UP_EN + description: "set this bit high to enable PWM generator0 timer stamp B's shadow register update task receive" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TASK_CMPR1_B_UP_EN + description: "set this bit high to enable PWM generator1 timer stamp B's shadow register update task receive" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TASK_CMPR2_B_UP_EN + description: "set this bit high to enable PWM generator2 timer stamp B's shadow register update task receive" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TASK_GEN_STOP_EN + description: set this bit high to enable all PWM generate stop task receive + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TASK_TIMER0_SYNC_EN + description: set this bit high to enable timer0 sync task receive + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TASK_TIMER1_SYNC_EN + description: set this bit high to enable timer1 sync task receive + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TASK_TIMER2_SYNC_EN + description: set this bit high to enable timer2 sync task receive + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TASK_TIMER0_PERIOD_UP_EN + description: set this bit high to enable timer0 period update task receive + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TASK_TIMER1_PERIOD_UP_EN + description: set this bit high to enable timer1 period update task receive + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TASK_TIMER2_PERIOD_UP_EN + description: set this bit high to enable timer2 period update task receive + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TASK_TZ0_OST_EN + description: set this bit high to enable one shot trip0 task receive + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TASK_TZ1_OST_EN + description: set this bit high to enable one shot trip1 task receive + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TASK_TZ2_OST_EN + description: set this bit high to enable one shot trip2 task receive + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TASK_CLR0_OST_EN + description: set this bit high to enable one shot trip0 clear task receive + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: TASK_CLR1_OST_EN + description: set this bit high to enable one shot trip1 clear task receive + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: TASK_CLR2_OST_EN + description: set this bit high to enable one shot trip2 clear task receive + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TASK_CAP0_EN + description: set this bit high to enable capture0 task receive + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: TASK_CAP1_EN + description: set this bit high to enable capture1 task receive + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TASK_CAP2_EN + description: set this bit high to enable capture2 task receive + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + name: CLK + description: MCPWM APB configuration register + addressOffset: 296 + size: 32 + fields: + - name: EN + description: Force clock on for this register file + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: VERSION + description: Version register. + addressOffset: 300 + size: 32 + resetValue: 35656256 + fields: + - name: DATE + description: Version of this register file + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: MEM_MONITOR + description: MEM_MONITOR Peripheral + groupName: MEM_MONITOR + baseAddress: 1611210752 + addressBlock: + - offset: 0 + size: 48 + usage: registers + registers: + - register: + name: LOG_SETTING + description: log config regsiter + addressOffset: 0 + size: 32 + resetValue: 128 + fields: + - name: LOG_ENA + description: "enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA." + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: LOG_MODE + description: "This field must be onehot. 4'b0001 : WR monitor, 4'b0010: WORD monitor, 4'b0100: HALFWORD monitor, 4'b1000: BYTE monitor." + bitOffset: 3 + bitWidth: 4 + access: read-write + - name: LOG_MEM_LOOP_ENABLE + description: "Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END" + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: LOG_CHECK_DATA + description: check data regsiter + addressOffset: 4 + size: 32 + fields: + - name: LOG_CHECK_DATA + description: "The special check data, when write this special data, it will trigger logging." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOG_DATA_MASK + description: check data mask register + addressOffset: 8 + size: 32 + fields: + - name: LOG_DATA_MASK + description: "byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1 mask second byte, and so on." + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: LOG_MIN + description: log boundary regsiter + addressOffset: 12 + size: 32 + fields: + - name: LOG_MIN + description: the min address of log range + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOG_MAX + description: log boundary regsiter + addressOffset: 16 + size: 32 + fields: + - name: LOG_MAX + description: the max address of log range + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOG_MEM_START + description: log message store range register + addressOffset: 20 + size: 32 + fields: + - name: LOG_MEM_START + description: the start address of writing logging message + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOG_MEM_END + description: log message store range register + addressOffset: 24 + size: 32 + fields: + - name: LOG_MEM_END + description: the end address of writing logging message + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOG_MEM_CURRENT_ADDR + description: current writing address. + addressOffset: 28 + size: 32 + fields: + - name: LOG_MEM_CURRENT_ADDR + description: means next writing address + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: LOG_MEM_ADDR_UPDATE + description: writing address update + addressOffset: 32 + size: 32 + fields: + - name: LOG_MEM_ADDR_UPDATE + description: "Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1, MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START" + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: LOG_MEM_FULL_FLAG + description: full flag status register + addressOffset: 36 + size: 32 + fields: + - name: LOG_MEM_FULL_FLAG + description: 1 means memory write loop at least one time at the range of MEM_START and MEM_END + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CLR_LOG_MEM_FULL_FLAG + description: Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: CLOCK_GATE + description: clock gate force on register + addressOffset: 40 + size: 32 + fields: + - name: CLK_EN + description: Set 1 to force on the clk of mem_monitor register + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: version register + addressOffset: 1020 + size: 32 + resetValue: 35660096 + fields: + - name: DATE + description: version register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: MODEM_LPCON + description: MODEM_LPCON Peripheral + groupName: MODEM_LPCON + baseAddress: 1611329536 + addressBlock: + - offset: 0 + size: 48 + usage: registers + registers: + - register: + name: TEST_CONF + addressOffset: 0 + size: 32 + fields: + - name: CLK_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CLK_DEBUG_ENA + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: LP_TIMER_CONF + addressOffset: 4 + size: 32 + fields: + - name: CLK_LP_TIMER_SEL_OSC_SLOW + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CLK_LP_TIMER_SEL_OSC_FAST + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CLK_LP_TIMER_SEL_XTAL + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CLK_LP_TIMER_SEL_XTAL32K + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CLK_LP_TIMER_DIV_NUM + bitOffset: 4 + bitWidth: 12 + access: read-write + - register: + name: COEX_LP_CLK_CONF + addressOffset: 8 + size: 32 + fields: + - name: CLK_COEX_LP_SEL_OSC_SLOW + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CLK_COEX_LP_SEL_OSC_FAST + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CLK_COEX_LP_SEL_XTAL + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CLK_COEX_LP_SEL_XTAL32K + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CLK_COEX_LP_DIV_NUM + bitOffset: 4 + bitWidth: 12 + access: read-write + - register: + name: WIFI_LP_CLK_CONF + addressOffset: 12 + size: 32 + fields: + - name: CLK_WIFIPWR_LP_SEL_OSC_SLOW + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CLK_WIFIPWR_LP_SEL_OSC_FAST + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CLK_WIFIPWR_LP_SEL_XTAL + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CLK_WIFIPWR_LP_SEL_XTAL32K + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CLK_WIFIPWR_LP_DIV_NUM + bitOffset: 4 + bitWidth: 12 + access: read-write + - register: + name: I2C_MST_CLK_CONF + addressOffset: 16 + size: 32 + fields: + - name: CLK_I2C_MST_SEL_160M + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: MODEM_32K_CLK_CONF + addressOffset: 20 + size: 32 + fields: + - name: CLK_MODEM_32K_SEL + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: CLK_CONF + addressOffset: 24 + size: 32 + fields: + - name: CLK_WIFIPWR_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CLK_COEX_EN + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CLK_I2C_MST_EN + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CLK_LP_TIMER_EN + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: CLK_CONF_FORCE_ON + addressOffset: 28 + size: 32 + fields: + - name: CLK_WIFIPWR_FO + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CLK_COEX_FO + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CLK_I2C_MST_FO + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CLK_LP_TIMER_FO + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CLK_BCMEM_FO + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CLK_I2C_MST_MEM_FO + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CLK_CHAN_FREQ_MEM_FO + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CLK_PBUS_MEM_FO + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_AGC_MEM_FO + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CLK_DC_MEM_FO + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: CLK_CONF_POWER_ST + addressOffset: 32 + size: 32 + fields: + - name: CLK_WIFIPWR_ST_MAP + bitOffset: 16 + bitWidth: 4 + access: read-write + - name: CLK_COEX_ST_MAP + bitOffset: 20 + bitWidth: 4 + access: read-write + - name: CLK_I2C_MST_ST_MAP + bitOffset: 24 + bitWidth: 4 + access: read-write + - name: CLK_LP_APB_ST_MAP + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: RST_CONF + addressOffset: 36 + size: 32 + fields: + - name: RST_WIFIPWR + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: RST_COEX + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RST_I2C_MST + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: RST_LP_TIMER + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: MEM_CONF + addressOffset: 40 + size: 32 + resetValue: 131093 + fields: + - name: DC_MEM_FORCE_PU + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DC_MEM_FORCE_PD + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AGC_MEM_FORCE_PU + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: AGC_MEM_FORCE_PD + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PBUS_MEM_FORCE_PU + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: PBUS_MEM_FORCE_PD + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BC_MEM_FORCE_PU + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BC_MEM_FORCE_PD + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: I2C_MST_MEM_FORCE_PU + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: I2C_MST_MEM_FORCE_PD + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CHAN_FREQ_MEM_FORCE_PU + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CHAN_FREQ_MEM_FORCE_PD + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: MODEM_PWR_MEM_WP + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: MODEM_PWR_MEM_WA + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: MODEM_PWR_MEM_RA + bitOffset: 18 + bitWidth: 2 + access: read-write + - register: + name: DATE + addressOffset: 44 + size: 32 + resetValue: 35676736 + fields: + - name: DATE + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: MODEM_SYSCON + description: MODEM_SYSCON Peripheral + groupName: MODEM_SYSCON + baseAddress: 1611307008 + addressBlock: + - offset: 0 + size: 40 + usage: registers + registers: + - register: + name: TEST_CONF + addressOffset: 0 + size: 32 + fields: + - name: CLK_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CLK_CONF + addressOffset: 4 + size: 32 + resetValue: 2097152 + fields: + - name: CLK_DATA_DUMP_MUX + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CLK_ETM_EN + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: CLK_ZB_APB_EN + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: CLK_ZB_MAC_EN + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: CLK_MODEM_SEC_ECB_EN + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: CLK_MODEM_SEC_CCM_EN + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CLK_MODEM_SEC_BAH_EN + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: CLK_MODEM_SEC_APB_EN + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CLK_MODEM_SEC_EN + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CLK_BLE_TIMER_EN + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CLK_DATA_DUMP_EN + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CLK_CONF_FORCE_ON + addressOffset: 8 + size: 32 + fields: + - name: CLK_ETM_FO + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: CLK_ZB_APB_FO + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: CLK_ZB_MAC_FO + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: CLK_MODEM_SEC_ECB_FO + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: CLK_MODEM_SEC_CCM_FO + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CLK_MODEM_SEC_BAH_FO + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: CLK_MODEM_SEC_APB_FO + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CLK_MODEM_SEC_FO + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CLK_BLE_TIMER_FO + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CLK_DATA_DUMP_FO + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CLK_CONF_POWER_ST + addressOffset: 12 + size: 32 + fields: + - name: CLK_ZB_ST_MAP + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: CLK_FE_ST_MAP + bitOffset: 12 + bitWidth: 4 + access: read-write + - name: CLK_BT_ST_MAP + bitOffset: 16 + bitWidth: 4 + access: read-write + - name: CLK_WIFI_ST_MAP + bitOffset: 20 + bitWidth: 4 + access: read-write + - name: CLK_MODEM_PERI_ST_MAP + bitOffset: 24 + bitWidth: 4 + access: read-write + - name: CLK_MODEM_APB_ST_MAP + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: MODEM_RST_CONF + addressOffset: 16 + size: 32 + fields: + - name: RST_WIFIBB + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RST_WIFIMAC + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: RST_FE + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RST_BTMAC_APB + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RST_BTMAC + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RST_BTBB_APB + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: RST_BTBB + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RST_ETM + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RST_ZBMAC + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: RST_MODEM_ECB + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: RST_MODEM_CCM + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RST_MODEM_BAH + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RST_MODEM_SEC + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: RST_BLE_TIMER + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: RST_DATA_DUMP + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CLK_CONF1 + addressOffset: 20 + size: 32 + fields: + - name: CLK_WIFIBB_22M_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CLK_WIFIBB_40M_EN + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CLK_WIFIBB_44M_EN + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CLK_WIFIBB_80M_EN + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CLK_WIFIBB_40X_EN + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CLK_WIFIBB_80X_EN + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CLK_WIFIBB_40X1_EN + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CLK_WIFIBB_80X1_EN + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_WIFIBB_160X1_EN + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CLK_WIFIMAC_EN + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CLK_WIFI_APB_EN + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CLK_FE_20M_EN + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CLK_FE_40M_EN + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CLK_FE_80M_EN + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: CLK_FE_160M_EN + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CLK_FE_CAL_160M_EN + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CLK_FE_APB_EN + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CLK_BT_APB_EN + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: CLK_BT_EN + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: CLK_WIFIBB_480M_EN + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: CLK_FE_480M_EN + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CLK_FE_ANAMODE_40M_EN + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CLK_FE_ANAMODE_80M_EN + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: CLK_FE_ANAMODE_160M_EN + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: CLK_CONF1_FORCE_ON + addressOffset: 24 + size: 32 + fields: + - name: CLK_WIFIBB_22M_FO + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CLK_WIFIBB_40M_FO + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CLK_WIFIBB_44M_FO + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CLK_WIFIBB_80M_FO + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CLK_WIFIBB_40X_FO + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CLK_WIFIBB_80X_FO + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CLK_WIFIBB_40X1_FO + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CLK_WIFIBB_80X1_FO + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_WIFIBB_160X1_FO + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CLK_WIFIMAC_FO + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CLK_WIFI_APB_FO + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CLK_FE_20M_FO + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CLK_FE_40M_FO + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CLK_FE_80M_FO + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: CLK_FE_160M_FO + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CLK_FE_CAL_160M_FO + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CLK_FE_APB_FO + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CLK_BT_APB_FO + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: CLK_BT_FO + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: CLK_WIFIBB_480M_FO + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: CLK_FE_480M_FO + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CLK_FE_ANAMODE_40M_FO + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CLK_FE_ANAMODE_80M_FO + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: CLK_FE_ANAMODE_160M_FO + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: WIFI_BB_CFG + addressOffset: 28 + size: 32 + fields: + - name: WIFI_BB_CFG + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: MEM_CONF + addressOffset: 32 + size: 32 + resetValue: 32 + fields: + - name: MODEM_MEM_WP + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: MODEM_MEM_WA + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: MODEM_MEM_RA + bitOffset: 6 + bitWidth: 2 + access: read-write + - register: + name: DATE + addressOffset: 36 + size: 32 + resetValue: 35676928 + fields: + - name: DATE + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: OTP_DEBUG + description: OTP_DEBUG Peripheral + groupName: OTP_DEBUG + baseAddress: 1611348992 + addressBlock: + - offset: 0 + size: 528 + usage: registers + registers: + - register: + name: WR_DIS + description: Otp debuger block0 data register1. + addressOffset: 0 + size: 32 + fields: + - name: BLOCK0_WR_DIS + description: Otp block0 write disable data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP1_W1 + description: Otp debuger block0 data register2. + addressOffset: 4 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP1_W1 + description: Otp block0 backup1 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP1_W2 + description: Otp debuger block0 data register3. + addressOffset: 8 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP1_W2 + description: Otp block0 backup1 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP1_W3 + description: Otp debuger block0 data register4. + addressOffset: 12 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP1_W3 + description: Otp block0 backup1 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP1_W4 + description: Otp debuger block0 data register5. + addressOffset: 16 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP1_W4 + description: Otp block0 backup1 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP1_W5 + description: Otp debuger block0 data register6. + addressOffset: 20 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP1_W5 + description: Otp block0 backup1 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP2_W1 + description: Otp debuger block0 data register7. + addressOffset: 24 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP2_W1 + description: Otp block0 backup2 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP2_W2 + description: Otp debuger block0 data register8. + addressOffset: 28 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP2_W2 + description: Otp block0 backup2 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP2_W3 + description: Otp debuger block0 data register9. + addressOffset: 32 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP2_W3 + description: Otp block0 backup2 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP2_W4 + description: Otp debuger block0 data register10. + addressOffset: 36 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP2_W4 + description: Otp block0 backup2 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP2_W5 + description: Otp debuger block0 data register11. + addressOffset: 40 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP2_W5 + description: Otp block0 backup2 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP3_W1 + description: Otp debuger block0 data register12. + addressOffset: 44 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP3_W1 + description: Otp block0 backup3 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP3_W2 + description: Otp debuger block0 data register13. + addressOffset: 48 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP3_W2 + description: Otp block0 backup3 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP3_W3 + description: Otp debuger block0 data register14. + addressOffset: 52 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP3_W3 + description: Otp block0 backup3 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP3_W4 + description: Otp debuger block0 data register15. + addressOffset: 56 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP3_W4 + description: Otp block0 backup3 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP3_W5 + description: Otp debuger block0 data register16. + addressOffset: 60 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP3_W5 + description: Otp block0 backup3 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP4_W1 + description: Otp debuger block0 data register17. + addressOffset: 64 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP4_W1 + description: Otp block0 backup4 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP4_W2 + description: Otp debuger block0 data register18. + addressOffset: 68 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP4_W2 + description: Otp block0 backup4 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP4_W3 + description: Otp debuger block0 data register19. + addressOffset: 72 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP4_W3 + description: Otp block0 backup4 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP4_W4 + description: Otp debuger block0 data register20. + addressOffset: 76 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP4_W4 + description: Otp block0 backup4 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP4_W5 + description: Otp debuger block0 data register21. + addressOffset: 80 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP4_W5 + description: Otp block0 backup4 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_W1 + description: Otp debuger block1 data register1. + addressOffset: 84 + size: 32 + fields: + - name: BLOCK1_W1 + description: Otp block1 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_W2 + description: Otp debuger block1 data register2. + addressOffset: 88 + size: 32 + fields: + - name: BLOCK1_W2 + description: Otp block1 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_W3 + description: Otp debuger block1 data register3. + addressOffset: 92 + size: 32 + fields: + - name: BLOCK1_W3 + description: Otp block1 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_W4 + description: Otp debuger block1 data register4. + addressOffset: 96 + size: 32 + fields: + - name: BLOCK1_W4 + description: Otp block1 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_W5 + description: Otp debuger block1 data register5. + addressOffset: 100 + size: 32 + fields: + - name: BLOCK1_W5 + description: Otp block1 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_W6 + description: Otp debuger block1 data register6. + addressOffset: 104 + size: 32 + fields: + - name: BLOCK1_W6 + description: Otp block1 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_W7 + description: Otp debuger block1 data register7. + addressOffset: 108 + size: 32 + fields: + - name: BLOCK1_W7 + description: Otp block1 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_W8 + description: Otp debuger block1 data register8. + addressOffset: 112 + size: 32 + fields: + - name: BLOCK1_W8 + description: Otp block1 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_W9 + description: Otp debuger block1 data register9. + addressOffset: 116 + size: 32 + fields: + - name: BLOCK1_W9 + description: Otp block1 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_W1 + description: Otp debuger block2 data register1. + addressOffset: 120 + size: 32 + fields: + - name: BLOCK2_W1 + description: Otp block2 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_W2 + description: Otp debuger block2 data register2. + addressOffset: 124 + size: 32 + fields: + - name: BLOCK2_W2 + description: Otp block2 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_W3 + description: Otp debuger block2 data register3. + addressOffset: 128 + size: 32 + fields: + - name: BLOCK2_W3 + description: Otp block2 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_W4 + description: Otp debuger block2 data register4. + addressOffset: 132 + size: 32 + fields: + - name: BLOCK2_W4 + description: Otp block2 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_W5 + description: Otp debuger block2 data register5. + addressOffset: 136 + size: 32 + fields: + - name: BLOCK2_W5 + description: Otp block2 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_W6 + description: Otp debuger block2 data register6. + addressOffset: 140 + size: 32 + fields: + - name: BLOCK2_W6 + description: Otp block2 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_W7 + description: Otp debuger block2 data register7. + addressOffset: 144 + size: 32 + fields: + - name: BLOCK2_W7 + description: Otp block2 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_W8 + description: Otp debuger block2 data register8. + addressOffset: 148 + size: 32 + fields: + - name: BLOCK2_W8 + description: Otp block2 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_W9 + description: Otp debuger block2 data register9. + addressOffset: 152 + size: 32 + fields: + - name: BLOCK2_W9 + description: Otp block2 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_W10 + description: Otp debuger block2 data register10. + addressOffset: 156 + size: 32 + fields: + - name: BLOCK2_W10 + description: Otp block2 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_W11 + description: Otp debuger block2 data register11. + addressOffset: 160 + size: 32 + fields: + - name: BLOCK2_W11 + description: Otp block2 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_W1 + description: Otp debuger block3 data register1. + addressOffset: 164 + size: 32 + fields: + - name: BLOCK3_W1 + description: Otp block3 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_W2 + description: Otp debuger block3 data register2. + addressOffset: 168 + size: 32 + fields: + - name: BLOCK3_W2 + description: Otp block3 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_W3 + description: Otp debuger block3 data register3. + addressOffset: 172 + size: 32 + fields: + - name: BLOCK3_W3 + description: Otp block3 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_W4 + description: Otp debuger block3 data register4. + addressOffset: 176 + size: 32 + fields: + - name: BLOCK3_W4 + description: Otp block3 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_W5 + description: Otp debuger block3 data register5. + addressOffset: 180 + size: 32 + fields: + - name: BLOCK3_W5 + description: Otp block3 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_W6 + description: Otp debuger block3 data register6. + addressOffset: 184 + size: 32 + fields: + - name: BLOCK3_W6 + description: Otp block3 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_W7 + description: Otp debuger block3 data register7. + addressOffset: 188 + size: 32 + fields: + - name: BLOCK3_W7 + description: Otp block3 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_W8 + description: Otp debuger block3 data register8. + addressOffset: 192 + size: 32 + fields: + - name: BLOCK3_W8 + description: Otp block3 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_W9 + description: Otp debuger block3 data register9. + addressOffset: 196 + size: 32 + fields: + - name: BLOCK3_W9 + description: Otp block3 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_W10 + description: Otp debuger block3 data register10. + addressOffset: 200 + size: 32 + fields: + - name: BLOCK3_W10 + description: Otp block3 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_W11 + description: Otp debuger block3 data register11. + addressOffset: 204 + size: 32 + fields: + - name: BLOCK3_W11 + description: Otp block3 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK4_W1 + description: Otp debuger block4 data register1. + addressOffset: 208 + size: 32 + fields: + - name: BLOCK4_W1 + description: Otp block4 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK4_W2 + description: Otp debuger block4 data register2. + addressOffset: 212 + size: 32 + fields: + - name: BLOCK4_W2 + description: Otp block4 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK4_W3 + description: Otp debuger block4 data register3. + addressOffset: 216 + size: 32 + fields: + - name: BLOCK4_W3 + description: Otp block4 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK4_W4 + description: Otp debuger block4 data register4. + addressOffset: 220 + size: 32 + fields: + - name: BLOCK4_W4 + description: Otp block4 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK4_W5 + description: Otp debuger block4 data register5. + addressOffset: 224 + size: 32 + fields: + - name: BLOCK4_W5 + description: Otp block4 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK4_W6 + description: Otp debuger block4 data register6. + addressOffset: 228 + size: 32 + fields: + - name: BLOCK4_W6 + description: Otp block4 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK4_W7 + description: Otp debuger block4 data register7. + addressOffset: 232 + size: 32 + fields: + - name: BLOCK4_W7 + description: Otp block4 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK4_W8 + description: Otp debuger block4 data register8. + addressOffset: 236 + size: 32 + fields: + - name: BLOCK4_W8 + description: Otp block4 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK4_W9 + description: Otp debuger block4 data register9. + addressOffset: 240 + size: 32 + fields: + - name: BLOCK4_W9 + description: Otp block4 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK4_W10 + description: Otp debuger block4 data registe10. + addressOffset: 244 + size: 32 + fields: + - name: BLOCK4_W10 + description: Otp block4 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK4_W11 + description: Otp debuger block4 data register11. + addressOffset: 248 + size: 32 + fields: + - name: BLOCK4_W11 + description: Otp block4 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK5_W1 + description: Otp debuger block5 data register1. + addressOffset: 252 + size: 32 + fields: + - name: BLOCK5_W1 + description: Otp block5 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK5_W2 + description: Otp debuger block5 data register2. + addressOffset: 256 + size: 32 + fields: + - name: BLOCK5_W2 + description: Otp block5 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK5_W3 + description: Otp debuger block5 data register3. + addressOffset: 260 + size: 32 + fields: + - name: BLOCK5_W3 + description: Otp block5 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK5_W4 + description: Otp debuger block5 data register4. + addressOffset: 264 + size: 32 + fields: + - name: BLOCK5_W4 + description: Otp block5 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK5_W5 + description: Otp debuger block5 data register5. + addressOffset: 268 + size: 32 + fields: + - name: BLOCK5_W5 + description: Otp block5 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK5_W6 + description: Otp debuger block5 data register6. + addressOffset: 272 + size: 32 + fields: + - name: BLOCK5_W6 + description: Otp block5 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK5_W7 + description: Otp debuger block5 data register7. + addressOffset: 276 + size: 32 + fields: + - name: BLOCK5_W7 + description: Otp block5 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK5_W8 + description: Otp debuger block5 data register8. + addressOffset: 280 + size: 32 + fields: + - name: BLOCK5_W8 + description: Otp block5 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK5_W9 + description: Otp debuger block5 data register9. + addressOffset: 284 + size: 32 + fields: + - name: BLOCK5_W9 + description: Otp block5 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK5_W10 + description: Otp debuger block5 data register10. + addressOffset: 288 + size: 32 + fields: + - name: BLOCK5_W10 + description: Otp block5 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK5_W11 + description: Otp debuger block5 data register11. + addressOffset: 292 + size: 32 + fields: + - name: BLOCK5_W11 + description: Otp block5 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK6_W1 + description: Otp debuger block6 data register1. + addressOffset: 296 + size: 32 + fields: + - name: BLOCK6_W1 + description: Otp block6 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK6_W2 + description: Otp debuger block6 data register2. + addressOffset: 300 + size: 32 + fields: + - name: BLOCK6_W2 + description: Otp block6 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK6_W3 + description: Otp debuger block6 data register3. + addressOffset: 304 + size: 32 + fields: + - name: BLOCK6_W3 + description: Otp block6 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK6_W4 + description: Otp debuger block6 data register4. + addressOffset: 308 + size: 32 + fields: + - name: BLOCK6_W4 + description: Otp block6 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK6_W5 + description: Otp debuger block6 data register5. + addressOffset: 312 + size: 32 + fields: + - name: BLOCK6_W5 + description: Otp block6 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK6_W6 + description: Otp debuger block6 data register6. + addressOffset: 316 + size: 32 + fields: + - name: BLOCK6_W6 + description: Otp block6 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK6_W7 + description: Otp debuger block6 data register7. + addressOffset: 320 + size: 32 + fields: + - name: BLOCK6_W7 + description: Otp block6 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK6_W8 + description: Otp debuger block6 data register8. + addressOffset: 324 + size: 32 + fields: + - name: BLOCK6_W8 + description: Otp block6 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK6_W9 + description: Otp debuger block6 data register9. + addressOffset: 328 + size: 32 + fields: + - name: BLOCK6_W9 + description: Otp block6 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK6_W10 + description: Otp debuger block6 data register10. + addressOffset: 332 + size: 32 + fields: + - name: BLOCK6_W10 + description: Otp block6 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK6_W11 + description: Otp debuger block6 data register11. + addressOffset: 336 + size: 32 + fields: + - name: BLOCK6_W11 + description: Otp block6 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK7_W1 + description: Otp debuger block7 data register1. + addressOffset: 340 + size: 32 + fields: + - name: BLOCK7_W1 + description: Otp block7 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK7_W2 + description: Otp debuger block7 data register2. + addressOffset: 344 + size: 32 + fields: + - name: BLOCK7_W2 + description: Otp block7 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK7_W3 + description: Otp debuger block7 data register3. + addressOffset: 348 + size: 32 + fields: + - name: BLOCK7_W3 + description: Otp block7 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK7_W4 + description: Otp debuger block7 data register4. + addressOffset: 352 + size: 32 + fields: + - name: BLOCK7_W4 + description: Otp block7 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK7_W5 + description: Otp debuger block7 data register5. + addressOffset: 356 + size: 32 + fields: + - name: BLOCK7_W5 + description: Otp block7 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK7_W6 + description: Otp debuger block7 data register6. + addressOffset: 360 + size: 32 + fields: + - name: BLOCK7_W6 + description: Otp block7 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK7_W7 + description: Otp debuger block7 data register7. + addressOffset: 364 + size: 32 + fields: + - name: BLOCK7_W7 + description: Otp block7 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK7_W8 + description: Otp debuger block7 data register8. + addressOffset: 368 + size: 32 + fields: + - name: BLOCK7_W8 + description: Otp block7 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK7_W9 + description: Otp debuger block7 data register9. + addressOffset: 372 + size: 32 + fields: + - name: BLOCK7_W9 + description: Otp block7 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK7_W10 + description: Otp debuger block7 data register10. + addressOffset: 376 + size: 32 + fields: + - name: BLOCK7_W10 + description: Otp block7 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK7_W11 + description: Otp debuger block7 data register11. + addressOffset: 380 + size: 32 + fields: + - name: BLOCK7_W11 + description: Otp block7 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK8_W1 + description: Otp debuger block8 data register1. + addressOffset: 384 + size: 32 + fields: + - name: BLOCK8_W1 + description: Otp block8 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK8_W2 + description: Otp debuger block8 data register2. + addressOffset: 388 + size: 32 + fields: + - name: BLOCK8_W2 + description: Otp block8 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK8_W3 + description: Otp debuger block8 data register3. + addressOffset: 392 + size: 32 + fields: + - name: BLOCK8_W3 + description: Otp block8 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK8_W4 + description: Otp debuger block8 data register4. + addressOffset: 396 + size: 32 + fields: + - name: BLOCK8_W4 + description: Otp block8 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK8_W5 + description: Otp debuger block8 data register5. + addressOffset: 400 + size: 32 + fields: + - name: BLOCK8_W5 + description: Otp block8 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK8_W6 + description: Otp debuger block8 data register6. + addressOffset: 404 + size: 32 + fields: + - name: BLOCK8_W6 + description: Otp block8 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK8_W7 + description: Otp debuger block8 data register7. + addressOffset: 408 + size: 32 + fields: + - name: BLOCK8_W7 + description: Otp block8 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK8_W8 + description: Otp debuger block8 data register8. + addressOffset: 412 + size: 32 + fields: + - name: BLOCK8_W8 + description: Otp block8 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK8_W9 + description: Otp debuger block8 data register9. + addressOffset: 416 + size: 32 + fields: + - name: BLOCK8_W9 + description: Otp block8 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK8_W10 + description: Otp debuger block8 data register10. + addressOffset: 420 + size: 32 + fields: + - name: BLOCK8_W10 + description: Otp block8 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK8_W11 + description: Otp debuger block8 data register11. + addressOffset: 424 + size: 32 + fields: + - name: BLOCK8_W11 + description: Otp block8 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK9_W1 + description: Otp debuger block9 data register1. + addressOffset: 428 + size: 32 + fields: + - name: BLOCK9_W1 + description: Otp block9 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK9_W2 + description: Otp debuger block9 data register2. + addressOffset: 432 + size: 32 + fields: + - name: BLOCK9_W2 + description: Otp block9 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK9_W3 + description: Otp debuger block9 data register3. + addressOffset: 436 + size: 32 + fields: + - name: BLOCK9_W3 + description: Otp block9 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK9_W4 + description: Otp debuger block9 data register4. + addressOffset: 440 + size: 32 + fields: + - name: BLOCK9_W4 + description: Otp block9 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK9_W5 + description: Otp debuger block9 data register5. + addressOffset: 444 + size: 32 + fields: + - name: BLOCK9_W5 + description: Otp block9 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK9_W6 + description: Otp debuger block9 data register6. + addressOffset: 448 + size: 32 + fields: + - name: BLOCK9_W6 + description: Otp block9 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK9_W7 + description: Otp debuger block9 data register7. + addressOffset: 452 + size: 32 + fields: + - name: BLOCK9_W7 + description: Otp block9 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK9_W8 + description: Otp debuger block9 data register8. + addressOffset: 456 + size: 32 + fields: + - name: BLOCK9_W8 + description: Otp block9 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK9_W9 + description: Otp debuger block9 data register9. + addressOffset: 460 + size: 32 + fields: + - name: BLOCK9_W9 + description: Otp block9 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK9_W10 + description: Otp debuger block9 data register10. + addressOffset: 464 + size: 32 + fields: + - name: BLOCK9_W10 + description: Otp block9 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK9_W11 + description: Otp debuger block9 data register11. + addressOffset: 468 + size: 32 + fields: + - name: BLOCK9_W11 + description: Otp block9 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK10_W1 + description: Otp debuger block10 data register1. + addressOffset: 472 + size: 32 + fields: + - name: BLOCK10_W1 + description: Otp block10 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK10_W2 + description: Otp debuger block10 data register2. + addressOffset: 476 + size: 32 + fields: + - name: BLOCK10_W2 + description: Otp block10 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK10_W3 + description: Otp debuger block10 data register3. + addressOffset: 480 + size: 32 + fields: + - name: BLOCK10_W3 + description: Otp block10 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK10_W4 + description: Otp debuger block10 data register4. + addressOffset: 484 + size: 32 + fields: + - name: BLOCK10_W4 + description: Otp block10 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK10_W5 + description: Otp debuger block10 data register5. + addressOffset: 488 + size: 32 + fields: + - name: BLOCK10_W5 + description: Otp block10 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK10_W6 + description: Otp debuger block10 data register6. + addressOffset: 492 + size: 32 + fields: + - name: BLOCK10_W6 + description: Otp block10 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK10_W7 + description: Otp debuger block10 data register7. + addressOffset: 496 + size: 32 + fields: + - name: BLOCK10_W7 + description: Otp block10 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK10_W8 + description: Otp debuger block10 data register8. + addressOffset: 500 + size: 32 + fields: + - name: BLOCK10_W8 + description: Otp block10 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK10_W9 + description: Otp debuger block10 data register9. + addressOffset: 504 + size: 32 + fields: + - name: BLOCK10_W9 + description: Otp block10 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK10_W10 + description: Otp debuger block10 data register10. + addressOffset: 508 + size: 32 + fields: + - name: BLOCK19_W10 + description: Otp block10 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK10_W11 + description: Otp debuger block10 data register11. + addressOffset: 512 + size: 32 + fields: + - name: BLOCK10_W11 + description: Otp block10 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CLK + description: Otp debuger clk_en configuration register. + addressOffset: 516 + size: 32 + fields: + - name: EN + description: Force clock on for this register file. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: APB2OTP_EN + description: Otp_debuger apb2otp enable configuration register. + addressOffset: 520 + size: 32 + fields: + - name: APB2OTP_EN + description: Debug mode enable signal. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: eFuse version register. + addressOffset: 524 + size: 32 + resetValue: 539037736 + fields: + - name: DATE + description: Stores otp_debug version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: PARL_IO + description: Parallel IO Controller + groupName: PARL_IO + baseAddress: 1610698752 + addressBlock: + - offset: 0 + size: 44 + usage: registers + interrupt: + - name: PARL_IO + value: 63 + registers: + - register: + name: RX_CFG0 + description: Parallel RX module configuration register0. + addressOffset: 0 + size: 32 + fields: + - name: RX_EOF_GEN_SEL + description: Write 0 to select eof generated manchnism by configured data byte length. Write 1 to select eof generated manchnism by external enable signal. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_START + description: Write 1 to start rx global data sampling. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_DATA_BYTELEN + description: Configures rx receieved data byte length. + bitOffset: 2 + bitWidth: 16 + access: read-write + - name: RX_SW_EN + description: Write 1 to enable software data sampling. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RX_PULSE_SUBMODE_SEL + description: "Pulse submode selection. \n0000: positive pulse start(data bit included) && positive pulse end(data bit included)\n0001: positive pulse start(data bit included) && positive pulse end (data bit excluded)\n0010: positive pulse start(data bit excluded) && positive pulse end (data bit included)\n0011: positive pulse start(data bit excluded) && positive pulse end (data bit excluded)\n0100: positive pulse start(data bit included) && length end\n0101: positive pulse start(data bit excluded) && length end\n0110: negative pulse start(data bit included) && negative pulse end(data bit included)\n0111: negative pulse start(data bit included) && negative pulse end (data bit excluded)\n1000: negative pulse start(data bit excluded) && negative pulse end (data bit included)\n1001: negative pulse start(data bit excluded) && negative pulse end (data bit excluded)\n1010: negative pulse start(data bit included) && length end\n1011: negative pulse start(data bit excluded) && length end" + bitOffset: 19 + bitWidth: 4 + access: read-write + - name: RX_LEVEL_SUBMODE_SEL + description: Write 0 to sample data at high level of external enable signal. Write 1 to sample data at low level of external enable signal. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: RX_SMP_MODE_SEL + description: "Rx data sampling mode selection. \n000: external level enable mode\n001: external pulse enable mode \n010: internal software enable mode" + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: RX_CLK_EDGE_SEL + description: Write 0 to enable sampling data on the rising edge of rx clock. Write 0 to enable sampling data on the falling edge of rx clock. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RX_BIT_PACK_ORDER + description: Write 0 to pack bits into 1byte from MSB when data bus width is 4/2/1 bits. Write 0 to pack bits into 1byte from LSB when data bus width is 4/2/1 bits. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RX_BUS_WID_SEL + description: "Rx data bus width selection. \n100: bus width is 1 bit \n011: bus width is 2 bits \n010: bus width is 4 bits\n001: bus width is 8 bits\n000: bus width is 16 bits" + bitOffset: 28 + bitWidth: 3 + access: read-write + - name: RX_FIFO_SRST + description: Write 1 to enable soft reset of async fifo in rx module. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RX_CFG1 + description: Parallel RX module configuration register1. + addressOffset: 4 + size: 32 + resetValue: 268431368 + fields: + - name: RX_REG_UPDATE + description: Write 1 to update rx register configuration signals. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: RX_TIMEOUT_EN + description: Write 1 to enable timeout count to generate error eof. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_EXT_EN_SEL + description: Configures rx external enable signal selection from 16 data lines. + bitOffset: 12 + bitWidth: 4 + access: read-write + - name: RX_TIMEOUT_THRESHOLD + description: Configures rx threshold of timeout counter. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: TX_CFG0 + description: Parallel TX module configuration register0. + addressOffset: 8 + size: 32 + fields: + - name: TX_BYTELEN + description: Configures tx sending data byte length. + bitOffset: 2 + bitWidth: 16 + access: read-write + - name: TX_GATING_EN + description: Write 1 to enable output tx clock gating. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TX_START + description: Write 1 to start tx global data output. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: TX_HW_VALID_EN + description: Write 1 to enable tx hardware data valid signal. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TX_SMP_EDGE_SEL + description: Write 0 to enable sampling data on the rising edge of tx clock. Write 0 to enable sampling data on the falling edge of tx clock. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TX_BIT_UNPACK_ORDER + description: Write 0 to unpack bits from 1byte from MSB when data bus width is 4/2/1 bits. Write 0 to unpack bits from 1byte from LSB when data bus width is 4/2/1 bits. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TX_BUS_WID_SEL + description: "Tx data bus width selection. \n100: bus width is 1 bit\n011: bus width is 2 bits\n010: bus width is 4 bits\n001: bus width is 8 bits\n000: bus width is 16 bits" + bitOffset: 27 + bitWidth: 3 + access: read-write + - name: TX_FIFO_SRST + description: Write 1 to enable soft reset of async fifo in tx module. + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: TX_CFG1 + description: Parallel TX module configuration register1. + addressOffset: 12 + size: 32 + fields: + - name: TX_IDLE_VALUE + description: Configures data value on tx bus when IDLE state. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: ST + description: Parallel IO module status register0. + addressOffset: 16 + size: 32 + fields: + - name: TX_READY + description: Represents the status that tx is ready. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Parallel IO interrupt enable singal configuration register. + addressOffset: 20 + size: 32 + fields: + - name: TX_FIFO_REMPTY_INT_ENA + description: Write 1 to enable TX_FIFO_REMPTY_INTR. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_FIFO_WOVF_INT_ENA + description: Write 1 to enable RX_FIFO_WOVF_INTR. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TX_EOF_INT_ENA + description: Write 1 to enable TX_EOF_INTR. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: Parallel IO interrupt raw singal status register. + addressOffset: 24 + size: 32 + fields: + - name: TX_FIFO_REMPTY_INT_RAW + description: The raw interrupt status of TX_FIFO_REMPTY_INTR. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_FIFO_WOVF_INT_RAW + description: The raw interrupt status of RX_FIFO_WOVF_INTR. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TX_EOF_INT_RAW + description: The raw interrupt status of TX_EOF_INTR. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Parallel IO interrupt singal status register. + addressOffset: 28 + size: 32 + fields: + - name: TX_FIFO_REMPTY_INT_ST + description: The masked interrupt status of TX_FIFO_REMPTY_INTR. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RX_FIFO_WOVF_INT_ST + description: The masked interrupt status of RX_FIFO_WOVF_INTR. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TX_EOF_INT_ST + description: The masked interrupt status of TX_EOF_INTR. + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: Parallel IO interrupt clear singal configuration register. + addressOffset: 32 + size: 32 + fields: + - name: TX_FIFO_REMPTY_INT_CLR + description: Write 1 to clear TX_FIFO_REMPTY_INTR. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: RX_FIFO_WOVF_INT_CLR + description: Write 1 to clear RX_FIFO_WOVF_INTR. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TX_EOF_INT_CLR + description: Write 1 to clear TX_EOF_INTR. + bitOffset: 2 + bitWidth: 1 + access: write-only + - register: + name: CLK + description: Parallel IO clk configuration register + addressOffset: 288 + size: 32 + fields: + - name: EN + description: Force clock on for this register file + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: VERSION + description: Version register. + addressOffset: 1020 + size: 32 + resetValue: 35660352 + fields: + - name: DATE + description: Version of this register file + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: PAU + description: PAU Peripheral + groupName: PAU + baseAddress: 1611214848 + addressBlock: + - offset: 0 + size: 76 + usage: registers + interrupt: + - name: PAU + value: 32 + registers: + - register: + name: REGDMA_CONF + description: Peri backup control register + addressOffset: 0 + size: 32 + fields: + - name: FLOW_ERR + description: backup error type + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: START + description: backup start signal + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TO_MEM + description: backup direction(reg to mem / mem to reg) + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: LINK_SEL + description: Link select + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: START_MAC + description: mac sw backup start signal + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: TO_MEM_MAC + description: mac sw backup direction(reg to mem / mem to reg) + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SEL_MAC + description: mac hw/sw select + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: REGDMA_CLK_CONF + description: Clock control register + addressOffset: 4 + size: 32 + fields: + - name: CLK_EN + description: clock enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: REGDMA_ETM_CTRL + description: ETM start ctrl reg + addressOffset: 8 + size: 32 + fields: + - name: ETM_START_0 + description: etm_start_0 reg + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ETM_START_1 + description: etm_start_1 reg + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: ETM_START_2 + description: etm_start_2 reg + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: ETM_START_3 + description: etm_start_3 reg + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: REGDMA_LINK_0_ADDR + description: link_0_addr + addressOffset: 12 + size: 32 + fields: + - name: LINK_ADDR_0 + description: link_0_addr reg + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGDMA_LINK_1_ADDR + description: Link_1_addr + addressOffset: 16 + size: 32 + fields: + - name: LINK_ADDR_1 + description: Link_1_addr reg + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGDMA_LINK_2_ADDR + description: Link_2_addr + addressOffset: 20 + size: 32 + fields: + - name: LINK_ADDR_2 + description: Link_2_addr reg + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGDMA_LINK_3_ADDR + description: Link_3_addr + addressOffset: 24 + size: 32 + fields: + - name: LINK_ADDR_3 + description: Link_3_addr reg + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGDMA_LINK_MAC_ADDR + description: Link_mac_addr + addressOffset: 28 + size: 32 + fields: + - name: LINK_ADDR_MAC + description: Link_mac_addr reg + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGDMA_CURRENT_LINK_ADDR + description: current link addr + addressOffset: 32 + size: 32 + fields: + - name: CURRENT_LINK_ADDR + description: current link addr reg + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: REGDMA_BACKUP_ADDR + description: Backup addr + addressOffset: 36 + size: 32 + fields: + - name: BACKUP_ADDR + description: backup addr reg + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: REGDMA_MEM_ADDR + description: mem addr + addressOffset: 40 + size: 32 + fields: + - name: MEM_ADDR + description: mem addr reg + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: REGDMA_BKP_CONF + description: backup config + addressOffset: 44 + size: 32 + resetValue: 2098207008 + fields: + - name: READ_INTERVAL + description: Link read_interval + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: LINK_TOUT_THRES + description: link wait timeout threshold + bitOffset: 7 + bitWidth: 10 + access: read-write + - name: BURST_LIMIT + description: burst limit + bitOffset: 17 + bitWidth: 5 + access: read-write + - name: BACKUP_TOUT_THRES + description: Backup timeout threshold + bitOffset: 22 + bitWidth: 10 + access: read-write + - register: + name: RETENTION_LINK_BASE + description: retention dma link base + addressOffset: 48 + size: 32 + fields: + - name: LINK_BASE_ADDR + description: retention dma link base + bitOffset: 0 + bitWidth: 27 + access: read-write + - register: + name: RETENTION_CFG + description: retention_cfg + addressOffset: 52 + size: 32 + resetValue: 4294967295 + fields: + - name: RET_INV_CFG + description: retention inv scan out + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: INT_ENA + description: Read only register for error and done + addressOffset: 56 + size: 32 + fields: + - name: DONE_INT_ENA + description: backup done flag + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ERROR_INT_ENA + description: error flag + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: Read only register for error and done + addressOffset: 60 + size: 32 + fields: + - name: DONE_INT_RAW + description: backup done flag + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ERROR_INT_RAW + description: error flag + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Read only register for error and done + addressOffset: 64 + size: 32 + fields: + - name: DONE_INT_CLR + description: backup done flag + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ERROR_INT_CLR + description: error flag + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: INT_ST + description: Read only register for error and done + addressOffset: 68 + size: 32 + fields: + - name: DONE_INT_ST + description: backup done flag + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ERROR_INT_ST + description: error flag + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: Date register. + addressOffset: 1020 + size: 32 + resetValue: 35663984 + fields: + - name: DATE + description: REGDMA date information/ REGDMA version information. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: PCNT + description: Pulse Count Controller + groupName: PCNT + baseAddress: 1610686464 + addressBlock: + - offset: 0 + size: 104 + usage: registers + interrupt: + - name: PCNT + value: 62 + registers: + - register: + dim: 4 + dimIncrement: 12 + name: U%s_CONF0 + description: Configuration register 0 for unit %s + addressOffset: 0 + size: 32 + resetValue: 15376 + fields: + - name: FILTER_THRES + description: "This sets the maximum threshold, in APB_CLK cycles, for the filter.\n\nAny pulses with width less than this will be ignored when the filter is enabled." + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: FILTER_EN + description: "This is the enable bit for unit %s's input filter." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: THR_ZERO_EN + description: "This is the enable bit for unit %s's zero comparator." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: THR_H_LIM_EN + description: "This is the enable bit for unit %s's thr_h_lim comparator." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: THR_L_LIM_EN + description: "This is the enable bit for unit %s's thr_l_lim comparator." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: THR_THRES0_EN + description: "This is the enable bit for unit %s's thres0 comparator." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: THR_THRES1_EN + description: "This is the enable bit for unit %s's thres1 comparator." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CH0_NEG_MODE + description: "This register sets the behavior when the signal input of channel 0 detects a negative edge.\n\n1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter" + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CH0_POS_MODE + description: "This register sets the behavior when the signal input of channel 0 detects a positive edge.\n\n1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter" + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: CH0_HCTRL_MODE + description: "This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high.\n\n0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification" + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: CH0_LCTRL_MODE + description: "This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low.\n\n0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification" + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CH1_NEG_MODE + description: "This register sets the behavior when the signal input of channel 1 detects a negative edge.\n\n1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter" + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CH1_POS_MODE + description: "This register sets the behavior when the signal input of channel 1 detects a positive edge.\n\n1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter" + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CH1_HCTRL_MODE + description: "This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high.\n\n0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification" + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: CH1_LCTRL_MODE + description: "This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low.\n\n0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification" + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + dim: 4 + dimIncrement: 12 + name: U%s_CONF1 + description: Configuration register 1 for unit %s + addressOffset: 4 + size: 32 + fields: + - name: CNT_THRES0 + description: This register is used to configure the thres0 value for unit %s. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CNT_THRES1 + description: This register is used to configure the thres1 value for unit %s. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + dim: 4 + dimIncrement: 12 + name: U%s_CONF2 + description: Configuration register 2 for unit %s + addressOffset: 8 + size: 32 + fields: + - name: CNT_H_LIM + description: This register is used to configure the thr_h_lim value for unit %s. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CNT_L_LIM + description: This register is used to configure the thr_l_lim value for unit %s. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: U%s_CNT + description: Counter value for unit %s + addressOffset: 48 + size: 32 + fields: + - name: CNT + description: This register stores the current pulse count value for unit %s. + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: INT_RAW + description: Interrupt raw status register + addressOffset: 64 + size: 32 + fields: + - name: CNT_THR_EVENT_U0 + description: The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U1 + description: The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U2 + description: The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U3 + description: The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: Interrupt status register + addressOffset: 68 + size: 32 + fields: + - name: CNT_THR_EVENT_U0 + description: The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U1 + description: The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U2 + description: The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U3 + description: The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable register + addressOffset: 72 + size: 32 + fields: + - name: CNT_THR_EVENT_U0 + description: The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U1 + description: The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U2 + description: The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U3 + description: The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear register + addressOffset: 76 + size: 32 + fields: + - name: CNT_THR_EVENT_U0 + description: Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CNT_THR_EVENT_U1 + description: Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CNT_THR_EVENT_U2 + description: Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CNT_THR_EVENT_U3 + description: Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + dim: 4 + dimIncrement: 4 + name: U%s_STATUS + description: PNCT UNIT%s status register + addressOffset: 80 + size: 32 + fields: + - name: ZERO_MODE + description: "The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive." + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: THRES1 + description: "The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others" + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: THRES0 + description: "The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others" + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L_LIM + description: "The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others" + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: H_LIM + description: "The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ZERO + description: "The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others" + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: CTRL + description: Control register for all counters + addressOffset: 96 + size: 32 + resetValue: 1 + fields: + - name: CNT_RST_U0 + description: "Set this bit to clear unit 0's counter." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U0 + description: "Set this bit to freeze unit 0's counter." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CNT_RST_U1 + description: "Set this bit to clear unit 1's counter." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U1 + description: "Set this bit to freeze unit 1's counter." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CNT_RST_U2 + description: "Set this bit to clear unit 2's counter." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U2 + description: "Set this bit to freeze unit 2's counter." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CNT_RST_U3 + description: "Set this bit to clear unit 3's counter." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U3 + description: "Set this bit to freeze unit 3's counter." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application" + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: PCNT version control register + addressOffset: 252 + size: 32 + resetValue: 419898881 + fields: + - name: DATE + description: This is the PCNT version control register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: PCR + description: PCR Peripheral + groupName: PCR + baseAddress: 1611227136 + addressBlock: + - offset: 0 + size: 332 + usage: registers + registers: + - register: + name: UART0_CONF + description: UART0 configuration register + addressOffset: 0 + size: 32 + resetValue: 1 + fields: + - name: UART0_CLK_EN + description: Set 1 to enable uart0 apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: UART0_RST_EN + description: Set 0 to reset uart0 module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: UART0_SCLK_CONF + description: UART0_SCLK configuration register + addressOffset: 4 + size: 32 + resetValue: 7340032 + fields: + - name: UART0_SCLK_DIV_A + description: The denominator of the frequency divider factor of the uart0 function clock. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: UART0_SCLK_DIV_B + description: The numerator of the frequency divider factor of the uart0 function clock. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: UART0_SCLK_DIV_NUM + description: The integral part of the frequency divider factor of the uart0 function clock. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: UART0_SCLK_SEL + description: "set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: UART0_SCLK_EN + description: Set 1 to enable uart0 function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: UART0_PD_CTRL + description: UART0 power control register + addressOffset: 8 + size: 32 + resetValue: 2 + fields: + - name: UART0_MEM_FORCE_PU + description: Set this bit to force power down UART0 memory. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UART0_MEM_FORCE_PD + description: Set this bit to force power up UART0 memory. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: UART1_CONF + description: UART1 configuration register + addressOffset: 12 + size: 32 + resetValue: 1 + fields: + - name: UART1_CLK_EN + description: Set 1 to enable uart1 apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: UART1_RST_EN + description: Set 0 to reset uart1 module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: UART1_SCLK_CONF + description: UART1_SCLK configuration register + addressOffset: 16 + size: 32 + resetValue: 7340032 + fields: + - name: UART1_SCLK_DIV_A + description: The denominator of the frequency divider factor of the uart1 function clock. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: UART1_SCLK_DIV_B + description: The numerator of the frequency divider factor of the uart1 function clock. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: UART1_SCLK_DIV_NUM + description: The integral part of the frequency divider factor of the uart1 function clock. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: UART1_SCLK_SEL + description: "set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: UART1_SCLK_EN + description: Set 1 to enable uart0 function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: UART1_PD_CTRL + description: UART1 power control register + addressOffset: 20 + size: 32 + resetValue: 2 + fields: + - name: UART1_MEM_FORCE_PU + description: Set this bit to force power down UART1 memory. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UART1_MEM_FORCE_PD + description: Set this bit to force power up UART1 memory. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: MSPI_CONF + description: MSPI configuration register + addressOffset: 24 + size: 32 + resetValue: 5 + fields: + - name: MSPI_CLK_EN + description: "Set 1 to enable mspi clock, include mspi pll clock" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MSPI_RST_EN + description: Set 0 to reset mspi module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MSPI_PLL_CLK_EN + description: Set 1 to enable mspi pll clock + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: MSPI_CLK_CONF + description: MSPI_CLK configuration register + addressOffset: 28 + size: 32 + resetValue: 768 + fields: + - name: MSPI_FAST_LS_DIV_NUM + description: "Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a low-speed clock-source such as XTAL/FOSC." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: MSPI_FAST_HS_DIV_NUM + description: "Set as one within (3,4,5) to generate div4(default)/div5/div6 of high-speed clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a high-speed clock-source such as SPLL." + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: I2C0_CONF + description: I2C configuration register + addressOffset: 32 + size: 32 + resetValue: 1 + fields: + - name: I2C0_CLK_EN + description: Set 1 to enable i2c apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: I2C0_RST_EN + description: Set 0 to reset i2c module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: I2C_SCLK_CONF + description: I2C_SCLK configuration register + addressOffset: 36 + size: 32 + resetValue: 4194304 + fields: + - name: I2C_SCLK_DIV_A + description: The denominator of the frequency divider factor of the i2c function clock. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: I2C_SCLK_DIV_B + description: The numerator of the frequency divider factor of the i2c function clock. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: I2C_SCLK_DIV_NUM + description: The integral part of the frequency divider factor of the i2c function clock. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: I2C_SCLK_SEL + description: "set this field to select clock-source. 0(default): XTAL, 1: FOSC." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: I2C_SCLK_EN + description: Set 1 to enable i2c function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: UHCI_CONF + description: UHCI configuration register + addressOffset: 40 + size: 32 + resetValue: 1 + fields: + - name: UHCI_CLK_EN + description: Set 1 to enable uhci clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: UHCI_RST_EN + description: Set 0 to reset uhci module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: RMT_CONF + description: RMT configuration register + addressOffset: 44 + size: 32 + resetValue: 1 + fields: + - name: RMT_CLK_EN + description: Set 1 to enable rmt apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RMT_RST_EN + description: Set 0 to reset rmt module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: RMT_SCLK_CONF + description: RMT_SCLK configuration register + addressOffset: 48 + size: 32 + resetValue: 5246976 + fields: + - name: SCLK_DIV_A + description: The denominator of the frequency divider factor of the rmt function clock. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_B + description: The numerator of the frequency divider factor of the rmt function clock. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_NUM + description: The integral part of the frequency divider factor of the rmt function clock. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: SCLK_SEL + description: "set this field to select clock-source. 0: do not select anyone clock, 1(default): 80MHz, 2: FOSC, 3: XTAL." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: SCLK_EN + description: Set 1 to enable rmt function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: LEDC_CONF + description: LEDC configuration register + addressOffset: 52 + size: 32 + resetValue: 1 + fields: + - name: LEDC_CLK_EN + description: Set 1 to enable ledc apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LEDC_RST_EN + description: Set 0 to reset ledc module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: LEDC_SCLK_CONF + description: LEDC_SCLK configuration register + addressOffset: 56 + size: 32 + resetValue: 4194304 + fields: + - name: LEDC_SCLK_SEL + description: "set this field to select clock-source. 0(default): do not select anyone clock, 1: 80MHz, 2: FOSC, 3: XTAL." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: LEDC_SCLK_EN + description: Set 1 to enable ledc function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: TIMERGROUP0_CONF + description: TIMERGROUP0 configuration register + addressOffset: 60 + size: 32 + resetValue: 1 + fields: + - name: TG0_CLK_EN + description: Set 1 to enable timer_group0 apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TG0_RST_EN + description: Set 0 to reset timer_group0 module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: TIMERGROUP0_TIMER_CLK_CONF + description: TIMERGROUP0_TIMER_CLK configuration register + addressOffset: 64 + size: 32 + resetValue: 4194304 + fields: + - name: TG0_TIMER_CLK_SEL + description: "set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TG0_TIMER_CLK_EN + description: Set 1 to enable timer_group0 timer clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: TIMERGROUP0_WDT_CLK_CONF + description: TIMERGROUP0_WDT_CLK configuration register + addressOffset: 68 + size: 32 + resetValue: 4194304 + fields: + - name: TG0_WDT_CLK_SEL + description: "set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TG0_WDT_CLK_EN + description: Set 1 to enable timer_group0 wdt clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: TIMERGROUP1_CONF + description: TIMERGROUP1 configuration register + addressOffset: 72 + size: 32 + resetValue: 1 + fields: + - name: TG1_CLK_EN + description: Set 1 to enable timer_group1 apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TG1_RST_EN + description: Set 0 to reset timer_group1 module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: TIMERGROUP1_TIMER_CLK_CONF + description: TIMERGROUP1_TIMER_CLK configuration register + addressOffset: 76 + size: 32 + resetValue: 4194304 + fields: + - name: TG1_TIMER_CLK_SEL + description: "set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TG1_TIMER_CLK_EN + description: Set 1 to enable timer_group1 timer clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: TIMERGROUP1_WDT_CLK_CONF + description: TIMERGROUP1_WDT_CLK configuration register + addressOffset: 80 + size: 32 + resetValue: 4194304 + fields: + - name: TG1_WDT_CLK_SEL + description: "set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TG1_WDT_CLK_EN + description: Set 1 to enable timer_group0 wdt clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: SYSTIMER_CONF + description: SYSTIMER configuration register + addressOffset: 84 + size: 32 + resetValue: 1 + fields: + - name: SYSTIMER_CLK_EN + description: Set 1 to enable systimer apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SYSTIMER_RST_EN + description: Set 0 to reset systimer module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: SYSTIMER_FUNC_CLK_CONF + description: SYSTIMER_FUNC_CLK configuration register + addressOffset: 88 + size: 32 + resetValue: 4194304 + fields: + - name: SYSTIMER_FUNC_CLK_SEL + description: "set this field to select clock-source. 0(default): XTAL, 1: FOSC." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SYSTIMER_FUNC_CLK_EN + description: Set 1 to enable systimer function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: TWAI0_CONF + description: TWAI0 configuration register + addressOffset: 92 + size: 32 + resetValue: 1 + fields: + - name: TWAI0_CLK_EN + description: Set 1 to enable twai0 apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TWAI0_RST_EN + description: Set 0 to reset twai0 module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: TWAI0_FUNC_CLK_CONF + description: TWAI0_FUNC_CLK configuration register + addressOffset: 96 + size: 32 + resetValue: 4194304 + fields: + - name: TWAI0_FUNC_CLK_SEL + description: "set this field to select clock-source. 0(default): XTAL, 1: FOSC." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TWAI0_FUNC_CLK_EN + description: Set 1 to enable twai0 function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: TWAI1_CONF + description: TWAI1 configuration register + addressOffset: 100 + size: 32 + resetValue: 1 + fields: + - name: TWAI1_CLK_EN + description: Set 1 to enable twai1 apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TWAI1_RST_EN + description: Set 0 to reset twai1 module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: TWAI1_FUNC_CLK_CONF + description: TWAI1_FUNC_CLK configuration register + addressOffset: 104 + size: 32 + resetValue: 4194304 + fields: + - name: TWAI1_FUNC_CLK_SEL + description: "set this field to select clock-source. 0(default): XTAL, 1: FOSC." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TWAI1_FUNC_CLK_EN + description: Set 1 to enable twai1 function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: I2S_CONF + description: I2S configuration register + addressOffset: 108 + size: 32 + resetValue: 1 + fields: + - name: I2S_CLK_EN + description: Set 1 to enable i2s apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: I2S_RST_EN + description: Set 0 to reset i2s module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: I2S_TX_CLKM_CONF + description: I2S_TX_CLKM configuration register + addressOffset: 112 + size: 32 + resetValue: 4202496 + fields: + - name: I2S_TX_CLKM_DIV_NUM + description: "Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div." + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: I2S_TX_CLKM_SEL + description: "Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: I2S_TX_CLKM_EN + description: Set 1 to enable i2s_tx function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: I2S_TX_CLKM_DIV_CONF + description: I2S_TX_CLKM_DIV configuration register + addressOffset: 116 + size: 32 + resetValue: 512 + fields: + - name: I2S_TX_CLKM_DIV_Z + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: I2S_TX_CLKM_DIV_Y + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))." + bitOffset: 9 + bitWidth: 9 + access: read-write + - name: I2S_TX_CLKM_DIV_X + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1." + bitOffset: 18 + bitWidth: 9 + access: read-write + - name: I2S_TX_CLKM_DIV_YN1 + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1." + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: I2S_RX_CLKM_CONF + description: I2S_RX_CLKM configuration register + addressOffset: 120 + size: 32 + resetValue: 4202496 + fields: + - name: I2S_RX_CLKM_DIV_NUM + description: Integral I2S clock divider value + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: I2S_RX_CLKM_SEL + description: "Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: I2S_RX_CLKM_EN + description: Set 1 to enable i2s_rx function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: I2S_MCLK_SEL + description: "This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx" + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: I2S_RX_CLKM_DIV_CONF + description: I2S_RX_CLKM_DIV configuration register + addressOffset: 124 + size: 32 + resetValue: 512 + fields: + - name: I2S_RX_CLKM_DIV_Z + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: I2S_RX_CLKM_DIV_Y + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))." + bitOffset: 9 + bitWidth: 9 + access: read-write + - name: I2S_RX_CLKM_DIV_X + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1." + bitOffset: 18 + bitWidth: 9 + access: read-write + - name: I2S_RX_CLKM_DIV_YN1 + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1." + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: SARADC_CONF + description: SARADC configuration register + addressOffset: 128 + size: 32 + resetValue: 5 + fields: + - name: SARADC_CLK_EN + description: no use + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SARADC_RST_EN + description: Set 0 to reset function_register of saradc module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SARADC_REG_CLK_EN + description: Set 1 to enable saradc apb clock + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SARADC_REG_RST_EN + description: Set 0 to reset apb_register of saradc module + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: SARADC_CLKM_CONF + description: SARADC_CLKM configuration register + addressOffset: 132 + size: 32 + resetValue: 4210688 + fields: + - name: SARADC_CLKM_DIV_A + description: The denominator of the frequency divider factor of the saradc function clock. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: SARADC_CLKM_DIV_B + description: The numerator of the frequency divider factor of the saradc function clock. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: SARADC_CLKM_DIV_NUM + description: The integral part of the frequency divider factor of the saradc function clock. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: SARADC_CLKM_SEL + description: "set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: reserved." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: SARADC_CLKM_EN + description: Set 1 to enable saradc function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: TSENS_CLK_CONF + description: TSENS_CLK configuration register + addressOffset: 136 + size: 32 + resetValue: 4194304 + fields: + - name: TSENS_CLK_SEL + description: "set this field to select clock-source. 0(default): FOSC, 1: XTAL." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TSENS_CLK_EN + description: Set 1 to enable tsens clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TSENS_RST_EN + description: Set 0 to reset tsens module + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: USB_DEVICE_CONF + description: USB_DEVICE configuration register + addressOffset: 140 + size: 32 + resetValue: 1 + fields: + - name: USB_DEVICE_CLK_EN + description: Set 1 to enable usb_device clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: USB_DEVICE_RST_EN + description: Set 0 to reset usb_device module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INTMTX_CONF + description: INTMTX configuration register + addressOffset: 144 + size: 32 + resetValue: 1 + fields: + - name: INTMTX_CLK_EN + description: Set 1 to enable intmtx clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: INTMTX_RST_EN + description: Set 0 to reset intmtx module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: PCNT_CONF + description: PCNT configuration register + addressOffset: 148 + size: 32 + resetValue: 1 + fields: + - name: PCNT_CLK_EN + description: Set 1 to enable pcnt clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PCNT_RST_EN + description: Set 0 to reset pcnt module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: ETM_CONF + description: ETM configuration register + addressOffset: 152 + size: 32 + resetValue: 1 + fields: + - name: ETM_CLK_EN + description: Set 1 to enable etm clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_RST_EN + description: Set 0 to reset etm module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: PWM_CONF + description: PWM configuration register + addressOffset: 156 + size: 32 + resetValue: 1 + fields: + - name: PWM_CLK_EN + description: Set 1 to enable pwm clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PWM_RST_EN + description: Set 0 to reset pwm module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: PWM_CLK_CONF + description: PWM_CLK configuration register + addressOffset: 160 + size: 32 + resetValue: 4210688 + fields: + - name: PWM_DIV_NUM + description: The integral part of the frequency divider factor of the pwm function clock. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: PWM_CLKM_SEL + description: "set this field to select clock-source. 0(default): do not select anyone clock, 1: 160MHz, 2: XTAL, 3: FOSC." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: PWM_CLKM_EN + description: set this field as 1 to activate pwm clkm. + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: PARL_IO_CONF + description: PARL_IO configuration register + addressOffset: 164 + size: 32 + resetValue: 1 + fields: + - name: PARL_CLK_EN + description: Set 1 to enable parl apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PARL_RST_EN + description: Set 0 to reset parl apb reg + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: PARL_CLK_RX_CONF + description: PARL_CLK_RX configuration register + addressOffset: 168 + size: 32 + resetValue: 262144 + fields: + - name: PARL_CLK_RX_DIV_NUM + description: The integral part of the frequency divider factor of the parl rx clock. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: PARL_CLK_RX_SEL + description: "set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: user clock from pad." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: PARL_CLK_RX_EN + description: Set 1 to enable parl rx clock + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: PARL_RX_RST_EN + description: Set 0 to reset parl rx module + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: PARL_CLK_TX_CONF + description: PARL_CLK_TX configuration register + addressOffset: 172 + size: 32 + resetValue: 262144 + fields: + - name: PARL_CLK_TX_DIV_NUM + description: The integral part of the frequency divider factor of the parl tx clock. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: PARL_CLK_TX_SEL + description: "set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: user clock from pad." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: PARL_CLK_TX_EN + description: Set 1 to enable parl tx clock + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: PARL_TX_RST_EN + description: Set 0 to reset parl tx module + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: SDIO_SLAVE_CONF + description: SDIO_SLAVE configuration register + addressOffset: 176 + size: 32 + resetValue: 1 + fields: + - name: SDIO_SLAVE_CLK_EN + description: Set 1 to enable sdio_slave clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SDIO_SLAVE_RST_EN + description: Set 0 to reset sdio_slave module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: PVT_MONITOR_CONF + description: PVT_MONITOR configuration register + addressOffset: 180 + size: 32 + resetValue: 29 + fields: + - name: PVT_MONITOR_CLK_EN + description: Set 1 to enable apb clock of pvt module + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PVT_MONITOR_RST_EN + description: Set 0 to reset all pvt monitor module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PVT_MONITOR_SITE1_CLK_EN + description: Set 1 to enable function clock of modem pvt module + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PVT_MONITOR_SITE2_CLK_EN + description: Set 1 to enable function clock of cpu pvt module + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PVT_MONITOR_SITE3_CLK_EN + description: Set 1 to enable function clock of hp_peri pvt module + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: PVT_MONITOR_FUNC_CLK_CONF + description: PVT_MONITOR function clock configuration register + addressOffset: 184 + size: 32 + resetValue: 4194304 + fields: + - name: PVT_MONITOR_FUNC_CLK_DIV_NUM + description: The integral part of the frequency divider factor of the pvt_monitor function clock. + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: PVT_MONITOR_FUNC_CLK_SEL + description: "set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL divided by 3." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: PVT_MONITOR_FUNC_CLK_EN + description: Set 1 to enable source clock of pvt sitex + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: GDMA_CONF + description: GDMA configuration register + addressOffset: 188 + size: 32 + resetValue: 1 + fields: + - name: GDMA_CLK_EN + description: Set 1 to enable gdma clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: GDMA_RST_EN + description: Set 0 to reset gdma module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: SPI2_CONF + description: SPI2 configuration register + addressOffset: 192 + size: 32 + resetValue: 1 + fields: + - name: SPI2_CLK_EN + description: Set 1 to enable spi2 apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI2_RST_EN + description: Set 0 to reset spi2 module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: SPI2_CLKM_CONF + description: SPI2_CLKM configuration register + addressOffset: 196 + size: 32 + resetValue: 4194304 + fields: + - name: SPI2_CLKM_SEL + description: "set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: SPI2_CLKM_EN + description: Set 1 to enable spi2 function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: AES_CONF + description: AES configuration register + addressOffset: 200 + size: 32 + resetValue: 1 + fields: + - name: AES_CLK_EN + description: Set 1 to enable aes clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: AES_RST_EN + description: Set 0 to reset aes module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: SHA_CONF + description: SHA configuration register + addressOffset: 204 + size: 32 + resetValue: 1 + fields: + - name: SHA_CLK_EN + description: Set 1 to enable sha clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SHA_RST_EN + description: Set 0 to reset sha module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: RSA_CONF + description: RSA configuration register + addressOffset: 208 + size: 32 + resetValue: 1 + fields: + - name: RSA_CLK_EN + description: Set 1 to enable rsa clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RSA_RST_EN + description: Set 0 to reset rsa module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: RSA_PD_CTRL + description: RSA power control register + addressOffset: 212 + size: 32 + resetValue: 2 + fields: + - name: RSA_MEM_PD + description: Set this bit to power down rsa internal memory. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RSA_MEM_FORCE_PU + description: Set this bit to force power up rsa internal memory + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RSA_MEM_FORCE_PD + description: Set this bit to force power down rsa internal memory. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: ECC_CONF + description: ECC configuration register + addressOffset: 216 + size: 32 + resetValue: 1 + fields: + - name: ECC_CLK_EN + description: Set 1 to enable ecc clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ECC_RST_EN + description: Set 0 to reset ecc module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: ECC_PD_CTRL + description: ECC power control register + addressOffset: 220 + size: 32 + resetValue: 2 + fields: + - name: ECC_MEM_PD + description: Set this bit to power down ecc internal memory. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ECC_MEM_FORCE_PU + description: Set this bit to force power up ecc internal memory + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ECC_MEM_FORCE_PD + description: Set this bit to force power down ecc internal memory. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: DS_CONF + description: DS configuration register + addressOffset: 224 + size: 32 + resetValue: 1 + fields: + - name: DS_CLK_EN + description: Set 1 to enable ds clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DS_RST_EN + description: Set 0 to reset ds module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: HMAC_CONF + description: HMAC configuration register + addressOffset: 228 + size: 32 + resetValue: 1 + fields: + - name: HMAC_CLK_EN + description: Set 1 to enable hmac clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: HMAC_RST_EN + description: Set 0 to reset hmac module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: IOMUX_CONF + description: IOMUX configuration register + addressOffset: 232 + size: 32 + resetValue: 1 + fields: + - name: IOMUX_CLK_EN + description: Set 1 to enable iomux apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IOMUX_RST_EN + description: Set 0 to reset iomux module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: IOMUX_CLK_CONF + description: IOMUX_CLK configuration register + addressOffset: 236 + size: 32 + resetValue: 7340032 + fields: + - name: IOMUX_FUNC_CLK_SEL + description: "set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: IOMUX_FUNC_CLK_EN + description: Set 1 to enable iomux function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: MEM_MONITOR_CONF + description: MEM_MONITOR configuration register + addressOffset: 240 + size: 32 + resetValue: 1 + fields: + - name: MEM_MONITOR_CLK_EN + description: Set 1 to enable mem_monitor clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_MONITOR_RST_EN + description: Set 0 to reset mem_monitor module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: REGDMA_CONF + description: REGDMA configuration register + addressOffset: 244 + size: 32 + fields: + - name: REGDMA_CLK_EN + description: Set 1 to enable regdma clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGDMA_RST_EN + description: Set 0 to reset regdma module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: RETENTION_CONF + description: retention configuration register + addressOffset: 248 + size: 32 + fields: + - name: RETENTION_CLK_EN + description: Set 1 to enable retention clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RETENTION_RST_EN + description: Set 0 to reset retention module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: TRACE_CONF + description: TRACE configuration register + addressOffset: 252 + size: 32 + resetValue: 1 + fields: + - name: TRACE_CLK_EN + description: Set 1 to enable trace clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TRACE_RST_EN + description: Set 0 to reset trace module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: ASSIST_CONF + description: ASSIST configuration register + addressOffset: 256 + size: 32 + resetValue: 1 + fields: + - name: ASSIST_CLK_EN + description: Set 1 to enable assist clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ASSIST_RST_EN + description: Set 0 to reset assist module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CACHE_CONF + description: CACHE configuration register + addressOffset: 260 + size: 32 + resetValue: 1 + fields: + - name: CACHE_CLK_EN + description: Set 1 to enable cache clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CACHE_RST_EN + description: Set 0 to reset cache module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: MODEM_APB_CONF + description: MODEM_APB configuration register + addressOffset: 264 + size: 32 + resetValue: 1 + fields: + - name: MODEM_APB_CLK_EN + description: "This field indicates if modem_apb clock is enable. 0: disable, 1: enable(default)." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MODEM_RST_EN + description: Set this file as 1 to reset modem-subsystem. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: TIMEOUT_CONF + description: TIMEOUT configuration register + addressOffset: 268 + size: 32 + fields: + - name: CPU_TIMEOUT_RST_EN + description: Set 0 to reset cpu_peri timeout module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: HP_TIMEOUT_RST_EN + description: Set 0 to reset hp_peri timeout module and hp_modem timeout module + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: SYSCLK_CONF + description: SYSCLK configuration register + addressOffset: 272 + size: 32 + resetValue: 671089152 + fields: + - name: LS_DIV_NUM + description: clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed clock-source such as XTAL/FOSC. + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: HS_DIV_NUM + description: clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: SOC_CLK_SEL + description: "This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CLK_XTAL_FREQ + description: This field indicates the frequency(MHz) of XTAL. + bitOffset: 24 + bitWidth: 7 + access: read-only + - register: + name: CPU_WAITI_CONF + description: CPU_WAITI configuration register + addressOffset: 276 + size: 32 + resetValue: 13 + fields: + - name: CPUPERIOD_SEL + description: Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: PLL_FREQ_SEL + description: Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CPU_WAIT_MODE_FORCE_ON + description: Set 1 to force cpu_waiti_clk enable. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CPU_WAITI_DELAY_NUM + description: "This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close" + bitOffset: 4 + bitWidth: 4 + access: read-write + - register: + name: CPU_FREQ_CONF + description: CPU_FREQ configuration register + addressOffset: 280 + size: 32 + fields: + - name: CPU_LS_DIV_NUM + description: "Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_LS_DIV_NUM." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CPU_HS_DIV_NUM + description: "Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is div1(default)/div2/div4 of clk_hproot. This field is only avaliable for high-speed clock-source such as SPLL, and should be used together with PCR_AHB_HS_DIV_NUM." + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: CPU_HS_120M_FORCE + description: "Given that PCR_CPU_HS_DIV_NUM is 0, set this field as 1 to force clk_cpu at 120MHz. Only avaliable when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL." + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: AHB_FREQ_CONF + description: AHB_FREQ configuration register + addressOffset: 284 + size: 32 + resetValue: 768 + fields: + - name: AHB_LS_DIV_NUM + description: "Set as one within (0,1,3,7) to generate clk_ahb drived by clk_hproot. The clk_ahb is div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for low-speed clock-source such as XTAL/FOSC, and should be used together with PCR_CPU_LS_DIV_NUM." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: AHB_HS_DIV_NUM + description: "Set as one within (3,7,15) to generate clk_ahb drived by clk_hproot. The clk_ahb is div4(default)/div8/div16 of clk_hproot. This field is only avaliable for high-speed clock-source such as SPLL, and should be used together with PCR_CPU_HS_DIV_NUM." + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: APB_FREQ_CONF + description: APB_FREQ configuration register + addressOffset: 288 + size: 32 + fields: + - name: APB_DECREASE_DIV_NUM + description: "If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be automatically down to clk_apb_decrease only when no access is on apb-bus, and will recover to the previous frequency when a new access appears on apb-bus. Set as one within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note that enable this function will reduce performance. Users can set this field as zero to disable the auto-decrease-apb-freq function. By default, this function is disable." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: APB_DIV_NUM + description: "Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is div1(default)/div2/div4 of clk_ahb." + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: SYSCLK_FREQ_QUERY_0 + description: SYSCLK frequency query 0 register + addressOffset: 292 + size: 32 + resetValue: 122900 + fields: + - name: FOSC_FREQ + description: This field indicates the frequency(MHz) of FOSC. + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: PLL_FREQ + description: This field indicates the frequency(MHz) of SPLL. + bitOffset: 8 + bitWidth: 10 + access: read-only + - register: + name: PLL_DIV_CLK_EN + description: SPLL DIV clock-gating configuration register + addressOffset: 296 + size: 32 + resetValue: 127 + fields: + - name: PLL_240M_CLK_EN + description: "This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PLL_160M_CLK_EN + description: "This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PLL_120M_CLK_EN + description: "This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PLL_80M_CLK_EN + description: "This field is used to open 80 MHz clock (div6 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PLL_48M_CLK_EN + description: "This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: PLL_40M_CLK_EN + description: "This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: PLL_20M_CLK_EN + description: "This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active." + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: CTRL_CLK_OUT_EN + description: CLK_OUT_EN configuration register + addressOffset: 300 + size: 32 + resetValue: 2047 + fields: + - name: CLK20_OEN + description: Set 1 to enable 20m clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CLK22_OEN + description: Set 1 to enable 22m clock + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CLK44_OEN + description: Set 1 to enable 44m clock + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CLK_BB_OEN + description: Set 1 to enable bb clock + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CLK80_OEN + description: Set 1 to enable 80m clock + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CLK160_OEN + description: Set 1 to enable 160m clock + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CLK_320M_OEN + description: Set 1 to enable 320m clock + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CLK_ADC_INF_OEN + description: Reserved + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_DAC_CPU_OEN + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CLK40X_BB_OEN + description: Set 1 to enable 40x_bb clock + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CLK_XTAL_OEN + description: Set 1 to enable xtal clock + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: CTRL_TICK_CONF + description: TICK configuration register + addressOffset: 304 + size: 32 + resetValue: 67367 + fields: + - name: XTAL_TICK_NUM + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: FOSC_TICK_NUM + description: "******* Description ***********" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: TICK_ENABLE + description: "******* Description ***********" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RST_TICK_CNT + description: "******* Description ***********" + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: CTRL_32K_CONF + description: 32KHz clock configuration register + addressOffset: 308 + size: 32 + fields: + - name: CLK_32K_SEL + description: "This field indicates which one 32KHz clock will be used by MODEM_SYSTEM and timergroup. 0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0." + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SRAM_POWER_CONF + description: HP SRAM/ROM configuration register + addressOffset: 312 + size: 32 + resetValue: 28687 + fields: + - name: SRAM_FORCE_PU + description: Set this bit to force power up SRAM + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: SRAM_FORCE_PD + description: Set this bit to force power down SRAM. + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: SRAM_CLKGATE_FORCE_ON + description: "1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A gate-clock will be used when accessing the SRAM." + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: ROM_FORCE_PU + description: Set this bit to force power up ROM + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: ROM_FORCE_PD + description: Set this bit to force power down ROM. + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: ROM_CLKGATE_FORCE_ON + description: "1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A gate-clock will be used when accessing the ROM." + bitOffset: 18 + bitWidth: 3 + access: read-write + - register: + name: RESET_EVENT_BYPASS + description: reset event bypass backdoor configuration register + addressOffset: 4080 + size: 32 + resetValue: 2 + fields: + - name: APM + description: "This field is used to control reset event relationship for tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg will not only be reset by power-reset, but also some reset event." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RESET_EVENT_BYPASS + description: "This field is used to control reset event relationship for system-bus. 1: system bus (including arbiter/router) will only be reset by power-reset. some reset event will be bypass. 0: system bus (including arbiter/router) will not only be reset by power-reset, but also some reset event." + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: FPGA_DEBUG + description: fpga debug register + addressOffset: 4084 + size: 32 + resetValue: 4294967295 + fields: + - name: FPGA_DEBUG + description: Only used in fpga debug. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CLOCK_GATE + description: PCR clock gating configure register + addressOffset: 4088 + size: 32 + fields: + - name: CLK_EN + description: Set this bit as 1 to force on clock gating. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Date register. + addressOffset: 4092 + size: 32 + resetValue: 35676496 + fields: + - name: DATE + description: PCR version information. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: PMU + description: PMU Peripheral + groupName: PMU + baseAddress: 1611333632 + addressBlock: + - offset: 0 + size: 424 + usage: registers + interrupt: + - name: PMU + value: 13 + registers: + - register: + name: HP_ACTIVE_DIG_POWER + description: need_des + addressOffset: 0 + size: 32 + fields: + - name: HP_ACTIVE_VDD_SPI_PD_EN + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_HP_MEM_DSLP + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_PD_HP_MEM_PD_EN + description: need_des + bitOffset: 23 + bitWidth: 4 + access: read-write + - name: HP_ACTIVE_PD_HP_WIFI_PD_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_PD_HP_CPU_PD_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_PD_HP_AON_PD_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_PD_TOP_PD_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_ACTIVE_ICG_HP_FUNC + description: need_des + addressOffset: 4 + size: 32 + resetValue: 4294967295 + fields: + - name: HP_ACTIVE_DIG_ICG_FUNC_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_ACTIVE_ICG_HP_APB + description: need_des + addressOffset: 8 + size: 32 + resetValue: 4294967295 + fields: + - name: HP_ACTIVE_DIG_ICG_APB_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_ACTIVE_ICG_MODEM + description: need_des + addressOffset: 12 + size: 32 + fields: + - name: HP_ACTIVE_DIG_ICG_MODEM_CODE + description: need_des + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: HP_ACTIVE_HP_SYS_CNTL + description: need_des + addressOffset: 16 + size: 32 + fields: + - name: HP_ACTIVE_UART_WAKEUP_EN + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_LP_PAD_HOLD_ALL + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_HP_PAD_HOLD_ALL + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_DIG_PAD_SLP_SEL + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_DIG_PAUSE_WDT + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_DIG_CPU_STALL + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: HP_ACTIVE_HP_CK_POWER + description: need_des + addressOffset: 20 + size: 32 + fields: + - name: HP_ACTIVE_I2C_ISO_EN + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_I2C_RETENTION + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_XPD_BB_I2C + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_XPD_BBPLL_I2C + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_XPD_BBPLL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: HP_ACTIVE_BIAS + description: need_des + addressOffset: 24 + size: 32 + fields: + - name: HP_ACTIVE_XPD_BIAS + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_DBG_ATTEN + description: need_des + bitOffset: 26 + bitWidth: 4 + access: read-write + - name: HP_ACTIVE_PD_CUR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SLEEP + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_ACTIVE_BACKUP + description: need_des + addressOffset: 28 + size: 32 + fields: + - name: HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE + description: need_des + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE + description: need_des + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: HP_ACTIVE_RETENTION_MODE + description: need_des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: HP_SLEEP2ACTIVE_RETENTION_EN + description: need_des + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: HP_MODEM2ACTIVE_RETENTION_EN + description: need_des + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: HP_SLEEP2ACTIVE_BACKUP_CLK_SEL + description: need_des + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: HP_MODEM2ACTIVE_BACKUP_CLK_SEL + description: need_des + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: HP_SLEEP2ACTIVE_BACKUP_MODE + description: need_des + bitOffset: 20 + bitWidth: 3 + access: read-write + - name: HP_MODEM2ACTIVE_BACKUP_MODE + description: need_des + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: HP_SLEEP2ACTIVE_BACKUP_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_MODEM2ACTIVE_BACKUP_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: HP_ACTIVE_BACKUP_CLK + description: need_des + addressOffset: 32 + size: 32 + fields: + - name: HP_ACTIVE_BACKUP_ICG_FUNC_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_ACTIVE_SYSCLK + description: need_des + addressOffset: 36 + size: 32 + fields: + - name: HP_ACTIVE_DIG_SYS_CLK_NO_DIV + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_ICG_SYS_CLOCK_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_SYS_CLK_SLP_SEL + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_ICG_SLP_SEL + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_DIG_SYS_CLK_SEL + description: need_des + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: HP_ACTIVE_HP_REGULATOR0 + description: need_des + addressOffset: 40 + size: 32 + resetValue: 3328668032 + fields: + - name: LP_DBIAS_VOL + description: need_des + bitOffset: 4 + bitWidth: 5 + access: read-only + - name: HP_DBIAS_VOL + description: need_des + bitOffset: 9 + bitWidth: 5 + access: read-only + - name: DIG_REGULATOR0_DBIAS_SEL + description: need_des + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DIG_DBIAS_INIT + description: need_des + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD + description: need_des + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD + description: need_des + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_HP_REGULATOR_XPD + description: need_des + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS + description: need_des + bitOffset: 19 + bitWidth: 4 + access: read-write + - name: HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS + description: need_des + bitOffset: 23 + bitWidth: 4 + access: read-write + - name: HP_ACTIVE_HP_REGULATOR_DBIAS + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: HP_ACTIVE_HP_REGULATOR1 + description: need_des + addressOffset: 44 + size: 32 + fields: + - name: HP_ACTIVE_HP_REGULATOR_DRV_B + description: need_des + bitOffset: 8 + bitWidth: 24 + access: read-write + - register: + name: HP_ACTIVE_XTAL + description: need_des + addressOffset: 48 + size: 32 + resetValue: 2147483648 + fields: + - name: HP_ACTIVE_XPD_XTAL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_MODEM_DIG_POWER + description: need_des + addressOffset: 52 + size: 32 + fields: + - name: HP_MODEM_VDD_SPI_PD_EN + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: HP_MODEM_HP_MEM_DSLP + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: HP_MODEM_PD_HP_MEM_PD_EN + description: need_des + bitOffset: 23 + bitWidth: 4 + access: read-write + - name: HP_MODEM_PD_HP_WIFI_PD_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_MODEM_PD_HP_CPU_PD_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_MODEM_PD_HP_AON_PD_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HP_MODEM_PD_TOP_PD_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_MODEM_ICG_HP_FUNC + description: need_des + addressOffset: 56 + size: 32 + resetValue: 4294967295 + fields: + - name: HP_MODEM_DIG_ICG_FUNC_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_MODEM_ICG_HP_APB + description: need_des + addressOffset: 60 + size: 32 + resetValue: 4294967295 + fields: + - name: HP_MODEM_DIG_ICG_APB_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_MODEM_ICG_MODEM + description: need_des + addressOffset: 64 + size: 32 + fields: + - name: HP_MODEM_DIG_ICG_MODEM_CODE + description: need_des + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: HP_MODEM_HP_SYS_CNTL + description: need_des + addressOffset: 68 + size: 32 + fields: + - name: HP_MODEM_UART_WAKEUP_EN + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: HP_MODEM_LP_PAD_HOLD_ALL + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: HP_MODEM_HP_PAD_HOLD_ALL + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HP_MODEM_DIG_PAD_SLP_SEL + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_MODEM_DIG_PAUSE_WDT + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_MODEM_DIG_CPU_STALL + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: HP_MODEM_HP_CK_POWER + description: need_des + addressOffset: 72 + size: 32 + fields: + - name: HP_MODEM_I2C_ISO_EN + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HP_MODEM_I2C_RETENTION + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_MODEM_XPD_BB_I2C + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_MODEM_XPD_BBPLL_I2C + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_MODEM_XPD_BBPLL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: HP_MODEM_BIAS + description: need_des + addressOffset: 76 + size: 32 + fields: + - name: HP_MODEM_XPD_BIAS + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: HP_MODEM_DBG_ATTEN + description: need_des + bitOffset: 26 + bitWidth: 4 + access: read-write + - name: HP_MODEM_PD_CUR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SLEEP + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_MODEM_BACKUP + description: need_des + addressOffset: 80 + size: 32 + fields: + - name: HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE + description: need_des + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: HP_MODEM_RETENTION_MODE + description: need_des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: HP_SLEEP2MODEM_RETENTION_EN + description: need_des + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: HP_SLEEP2MODEM_BACKUP_CLK_SEL + description: need_des + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: HP_SLEEP2MODEM_BACKUP_MODE + description: need_des + bitOffset: 20 + bitWidth: 3 + access: read-write + - name: HP_SLEEP2MODEM_BACKUP_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: HP_MODEM_BACKUP_CLK + description: need_des + addressOffset: 84 + size: 32 + fields: + - name: HP_MODEM_BACKUP_ICG_FUNC_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_MODEM_SYSCLK + description: need_des + addressOffset: 88 + size: 32 + fields: + - name: HP_MODEM_DIG_SYS_CLK_NO_DIV + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HP_MODEM_ICG_SYS_CLOCK_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_MODEM_SYS_CLK_SLP_SEL + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_MODEM_ICG_SLP_SEL + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_MODEM_DIG_SYS_CLK_SEL + description: need_des + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: HP_MODEM_HP_REGULATOR0 + description: need_des + addressOffset: 92 + size: 32 + resetValue: 3328638976 + fields: + - name: HP_MODEM_HP_REGULATOR_SLP_MEM_XPD + description: need_des + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD + description: need_des + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: HP_MODEM_HP_REGULATOR_XPD + description: need_des + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS + description: need_des + bitOffset: 19 + bitWidth: 4 + access: read-write + - name: HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS + description: need_des + bitOffset: 23 + bitWidth: 4 + access: read-write + - name: HP_MODEM_HP_REGULATOR_DBIAS + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: HP_MODEM_HP_REGULATOR1 + description: need_des + addressOffset: 96 + size: 32 + fields: + - name: HP_MODEM_HP_REGULATOR_DRV_B + description: need_des + bitOffset: 8 + bitWidth: 24 + access: read-write + - register: + name: HP_MODEM_XTAL + description: need_des + addressOffset: 100 + size: 32 + resetValue: 2147483648 + fields: + - name: HP_MODEM_XPD_XTAL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_SLEEP_DIG_POWER + description: need_des + addressOffset: 104 + size: 32 + fields: + - name: HP_SLEEP_VDD_SPI_PD_EN + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_HP_MEM_DSLP + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_PD_HP_MEM_PD_EN + description: need_des + bitOffset: 23 + bitWidth: 4 + access: read-write + - name: HP_SLEEP_PD_HP_WIFI_PD_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_PD_HP_CPU_PD_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_PD_HP_AON_PD_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_PD_TOP_PD_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_SLEEP_ICG_HP_FUNC + description: need_des + addressOffset: 108 + size: 32 + resetValue: 4294967295 + fields: + - name: HP_SLEEP_DIG_ICG_FUNC_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_SLEEP_ICG_HP_APB + description: need_des + addressOffset: 112 + size: 32 + resetValue: 4294967295 + fields: + - name: HP_SLEEP_DIG_ICG_APB_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_SLEEP_ICG_MODEM + description: need_des + addressOffset: 116 + size: 32 + fields: + - name: HP_SLEEP_DIG_ICG_MODEM_CODE + description: need_des + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: HP_SLEEP_HP_SYS_CNTL + description: need_des + addressOffset: 120 + size: 32 + fields: + - name: HP_SLEEP_UART_WAKEUP_EN + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_LP_PAD_HOLD_ALL + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_HP_PAD_HOLD_ALL + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_DIG_PAD_SLP_SEL + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_DIG_PAUSE_WDT + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_DIG_CPU_STALL + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: HP_SLEEP_HP_CK_POWER + description: need_des + addressOffset: 124 + size: 32 + fields: + - name: HP_SLEEP_I2C_ISO_EN + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_I2C_RETENTION + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_XPD_BB_I2C + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_XPD_BBPLL_I2C + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_XPD_BBPLL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: HP_SLEEP_BIAS + description: need_des + addressOffset: 128 + size: 32 + fields: + - name: HP_SLEEP_XPD_BIAS + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_DBG_ATTEN + description: need_des + bitOffset: 26 + bitWidth: 4 + access: read-write + - name: HP_SLEEP_PD_CUR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SLEEP + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_SLEEP_BACKUP + description: need_des + addressOffset: 132 + size: 32 + fields: + - name: HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE + description: need_des + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE + description: need_des + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: HP_SLEEP_RETENTION_MODE + description: need_des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: HP_MODEM2SLEEP_RETENTION_EN + description: need_des + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE2SLEEP_RETENTION_EN + description: need_des + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: HP_MODEM2SLEEP_BACKUP_CLK_SEL + description: need_des + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: HP_ACTIVE2SLEEP_BACKUP_CLK_SEL + description: need_des + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: HP_MODEM2SLEEP_BACKUP_MODE + description: need_des + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: HP_ACTIVE2SLEEP_BACKUP_MODE + description: need_des + bitOffset: 26 + bitWidth: 3 + access: read-write + - name: HP_MODEM2SLEEP_BACKUP_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE2SLEEP_BACKUP_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_SLEEP_BACKUP_CLK + description: need_des + addressOffset: 136 + size: 32 + fields: + - name: HP_SLEEP_BACKUP_ICG_FUNC_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_SLEEP_SYSCLK + description: need_des + addressOffset: 140 + size: 32 + fields: + - name: HP_SLEEP_DIG_SYS_CLK_NO_DIV + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_ICG_SYS_CLOCK_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_SYS_CLK_SLP_SEL + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_ICG_SLP_SEL + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_DIG_SYS_CLK_SEL + description: need_des + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: HP_SLEEP_HP_REGULATOR0 + description: need_des + addressOffset: 144 + size: 32 + resetValue: 3328638976 + fields: + - name: HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD + description: need_des + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD + description: need_des + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_HP_REGULATOR_XPD + description: need_des + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS + description: need_des + bitOffset: 19 + bitWidth: 4 + access: read-write + - name: HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS + description: need_des + bitOffset: 23 + bitWidth: 4 + access: read-write + - name: HP_SLEEP_HP_REGULATOR_DBIAS + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: HP_SLEEP_HP_REGULATOR1 + description: need_des + addressOffset: 148 + size: 32 + fields: + - name: HP_SLEEP_HP_REGULATOR_DRV_B + description: need_des + bitOffset: 8 + bitWidth: 24 + access: read-write + - register: + name: HP_SLEEP_XTAL + description: need_des + addressOffset: 152 + size: 32 + resetValue: 2147483648 + fields: + - name: HP_SLEEP_XPD_XTAL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_SLEEP_LP_REGULATOR0 + description: need_des + addressOffset: 156 + size: 32 + resetValue: 3328180224 + fields: + - name: HP_SLEEP_LP_REGULATOR_SLP_XPD + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_LP_REGULATOR_XPD + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_LP_REGULATOR_SLP_DBIAS + description: need_des + bitOffset: 23 + bitWidth: 4 + access: read-write + - name: HP_SLEEP_LP_REGULATOR_DBIAS + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: HP_SLEEP_LP_REGULATOR1 + description: need_des + addressOffset: 160 + size: 32 + fields: + - name: HP_SLEEP_LP_REGULATOR_DRV_B + description: need_des + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: HP_SLEEP_LP_DCDC_RESERVE + description: need_des + addressOffset: 164 + size: 32 + fields: + - name: HP_SLEEP_LP_DCDC_RESERVE + description: need_des + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: HP_SLEEP_LP_DIG_POWER + description: need_des + addressOffset: 168 + size: 32 + fields: + - name: HP_SLEEP_LP_MEM_DSLP + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_PD_LP_PERI_PD_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_SLEEP_LP_CK_POWER + description: need_des + addressOffset: 172 + size: 32 + resetValue: 1073741824 + fields: + - name: HP_SLEEP_XPD_XTAL32K + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_XPD_RC32K + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_XPD_FOSC_CLK + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_PD_OSC_CLK + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_SLEEP_LP_BIAS_RESERVE + description: need_des + addressOffset: 176 + size: 32 + fields: + - name: LP_SLEEP_LP_BIAS_RESERVE + description: need_des + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: LP_SLEEP_LP_REGULATOR0 + description: need_des + addressOffset: 180 + size: 32 + resetValue: 3328180224 + fields: + - name: LP_SLEEP_LP_REGULATOR_SLP_XPD + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_LP_REGULATOR_XPD + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_LP_REGULATOR_SLP_DBIAS + description: need_des + bitOffset: 23 + bitWidth: 4 + access: read-write + - name: LP_SLEEP_LP_REGULATOR_DBIAS + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: LP_SLEEP_LP_REGULATOR1 + description: need_des + addressOffset: 184 + size: 32 + fields: + - name: LP_SLEEP_LP_REGULATOR_DRV_B + description: need_des + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: LP_SLEEP_XTAL + description: need_des + addressOffset: 188 + size: 32 + resetValue: 2147483648 + fields: + - name: LP_SLEEP_XPD_XTAL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_SLEEP_LP_DIG_POWER + description: need_des + addressOffset: 192 + size: 32 + fields: + - name: LP_SLEEP_LP_MEM_DSLP + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_PD_LP_PERI_PD_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_SLEEP_LP_CK_POWER + description: need_des + addressOffset: 196 + size: 32 + resetValue: 1073741824 + fields: + - name: LP_SLEEP_XPD_XTAL32K + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_XPD_RC32K + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_XPD_FOSC_CLK + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_PD_OSC_CLK + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_SLEEP_BIAS + description: need_des + addressOffset: 200 + size: 32 + fields: + - name: LP_SLEEP_XPD_BIAS + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_DBG_ATTEN + description: need_des + bitOffset: 26 + bitWidth: 4 + access: read-write + - name: LP_SLEEP_PD_CUR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SLEEP + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: IMM_HP_CK_POWER + description: need_des + addressOffset: 204 + size: 32 + access: read-write + fields: + - name: TIE_LOW_GLOBAL_BBPLL_ICG + description: need_des + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TIE_LOW_GLOBAL_XTAL_ICG + description: need_des + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TIE_LOW_I2C_RETENTION + description: need_des + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TIE_LOW_XPD_BB_I2C + description: need_des + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TIE_LOW_XPD_BBPLL_I2C + description: need_des + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: TIE_LOW_XPD_BBPLL + description: need_des + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TIE_LOW_XPD_XTAL + description: need_des + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_GLOBAL_BBPLL_ICG + description: need_des + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_GLOBAL_XTAL_ICG + description: need_des + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_I2C_RETENTION + description: need_des + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_XPD_BB_I2C + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_XPD_BBPLL_I2C + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_XPD_BBPLL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_XPD_XTAL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: IMM_SLEEP_SYSCLK + description: need_des + addressOffset: 208 + size: 32 + fields: + - name: UPDATE_DIG_ICG_SWITCH + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: TIE_LOW_ICG_SLP_SEL + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_ICG_SLP_SEL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: UPDATE_DIG_SYS_CLK_SEL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: IMM_HP_FUNC_ICG + description: need_des + addressOffset: 212 + size: 32 + fields: + - name: UPDATE_DIG_ICG_FUNC_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: IMM_HP_APB_ICG + description: need_des + addressOffset: 216 + size: 32 + fields: + - name: UPDATE_DIG_ICG_APB_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: IMM_MODEM_ICG + description: need_des + addressOffset: 220 + size: 32 + fields: + - name: UPDATE_DIG_ICG_MODEM_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: IMM_LP_ICG + description: need_des + addressOffset: 224 + size: 32 + fields: + - name: TIE_LOW_LP_ROOTCLK_SEL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_LP_ROOTCLK_SEL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: IMM_PAD_HOLD_ALL + description: need_des + addressOffset: 228 + size: 32 + fields: + - name: TIE_HIGH_LP_PAD_HOLD_ALL + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: TIE_LOW_LP_PAD_HOLD_ALL + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_HP_PAD_HOLD_ALL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: TIE_LOW_HP_PAD_HOLD_ALL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: IMM_I2C_ISO + description: need_des + addressOffset: 232 + size: 32 + fields: + - name: TIE_HIGH_I2C_ISO_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: TIE_LOW_I2C_ISO_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: POWER_WAIT_TIMER0 + description: need_des + addressOffset: 236 + size: 32 + resetValue: 2143281120 + fields: + - name: DG_HP_POWERDOWN_TIMER + description: need_des + bitOffset: 5 + bitWidth: 9 + access: read-write + - name: DG_HP_POWERUP_TIMER + description: need_des + bitOffset: 14 + bitWidth: 9 + access: read-write + - name: DG_HP_WAIT_TIMER + description: need_des + bitOffset: 23 + bitWidth: 9 + access: read-write + - register: + name: POWER_WAIT_TIMER1 + description: need_des + addressOffset: 240 + size: 32 + resetValue: 2147483136 + fields: + - name: DG_LP_POWERDOWN_TIMER + description: need_des + bitOffset: 9 + bitWidth: 7 + access: read-write + - name: DG_LP_POWERUP_TIMER + description: need_des + bitOffset: 16 + bitWidth: 7 + access: read-write + - name: DG_LP_WAIT_TIMER + description: need_des + bitOffset: 23 + bitWidth: 9 + access: read-write + - register: + name: POWER_PD_TOP_CNTL + description: need_des + addressOffset: 244 + size: 32 + resetValue: 28 + fields: + - name: FORCE_TOP_RESET + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FORCE_TOP_ISO + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FORCE_TOP_PU + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FORCE_TOP_NO_RESET + description: need_des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FORCE_TOP_NO_ISO + description: need_des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FORCE_TOP_PD + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: PD_TOP_MASK + description: need_des + bitOffset: 6 + bitWidth: 5 + access: read-write + - name: PD_TOP_PD_MASK + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: POWER_PD_HPAON_CNTL + description: need_des + addressOffset: 248 + size: 32 + resetValue: 28 + fields: + - name: FORCE_HP_AON_RESET + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FORCE_HP_AON_ISO + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FORCE_HP_AON_PU + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FORCE_HP_AON_NO_RESET + description: need_des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FORCE_HP_AON_NO_ISO + description: need_des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FORCE_HP_AON_PD + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: PD_HP_AON_MASK + description: need_des + bitOffset: 6 + bitWidth: 5 + access: read-write + - name: PD_HP_AON_PD_MASK + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: POWER_PD_HPCPU_CNTL + description: need_des + addressOffset: 252 + size: 32 + resetValue: 28 + fields: + - name: FORCE_HP_CPU_RESET + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FORCE_HP_CPU_ISO + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FORCE_HP_CPU_PU + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FORCE_HP_CPU_NO_RESET + description: need_des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FORCE_HP_CPU_NO_ISO + description: need_des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FORCE_HP_CPU_PD + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: PD_HP_CPU_MASK + description: need_des + bitOffset: 6 + bitWidth: 5 + access: read-write + - name: PD_HP_CPU_PD_MASK + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: POWER_PD_HPPERI_RESERVE + description: need_des + addressOffset: 256 + size: 32 + fields: + - name: HP_PERI_RESERVE + description: need_des + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: POWER_PD_HPWIFI_CNTL + description: need_des + addressOffset: 260 + size: 32 + resetValue: 28 + fields: + - name: FORCE_HP_WIFI_RESET + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FORCE_HP_WIFI_ISO + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FORCE_HP_WIFI_PU + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FORCE_HP_WIFI_NO_RESET + description: need_des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FORCE_HP_WIFI_NO_ISO + description: need_des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FORCE_HP_WIFI_PD + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: PD_HP_WIFI_MASK + description: need_des + bitOffset: 6 + bitWidth: 5 + access: read-write + - name: PD_HP_WIFI_PD_MASK + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: POWER_PD_LPPERI_CNTL + description: need_des + addressOffset: 264 + size: 32 + resetValue: 28 + fields: + - name: FORCE_LP_PERI_RESET + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FORCE_LP_PERI_ISO + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FORCE_LP_PERI_PU + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FORCE_LP_PERI_NO_RESET + description: need_des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FORCE_LP_PERI_NO_ISO + description: need_des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FORCE_LP_PERI_PD + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: POWER_PD_MEM_CNTL + description: need_des + addressOffset: 268 + size: 32 + resetValue: 4278190080 + fields: + - name: FORCE_HP_MEM_ISO + description: need_des + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: FORCE_HP_MEM_PD + description: need_des + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: FORCE_HP_MEM_NO_ISO + description: need_des + bitOffset: 24 + bitWidth: 4 + access: read-write + - name: FORCE_HP_MEM_PU + description: need_des + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: POWER_PD_MEM_MASK + description: need_des + addressOffset: 272 + size: 32 + fields: + - name: PD_HP_MEM2_PD_MASK + description: need_des + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: PD_HP_MEM1_PD_MASK + description: need_des + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: PD_HP_MEM0_PD_MASK + description: need_des + bitOffset: 10 + bitWidth: 5 + access: read-write + - name: PD_HP_MEM2_MASK + description: need_des + bitOffset: 17 + bitWidth: 5 + access: read-write + - name: PD_HP_MEM1_MASK + description: need_des + bitOffset: 22 + bitWidth: 5 + access: read-write + - name: PD_HP_MEM0_MASK + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: POWER_HP_PAD + description: need_des + addressOffset: 276 + size: 32 + fields: + - name: FORCE_HP_PAD_NO_ISO_ALL + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FORCE_HP_PAD_ISO_ALL + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: POWER_VDD_SPI_CNTL + description: need_des + addressOffset: 280 + size: 32 + resetValue: 1677459456 + fields: + - name: VDD_SPI_PWR_WAIT + description: need_des + bitOffset: 18 + bitWidth: 11 + access: read-write + - name: VDD_SPI_PWR_SW + description: need_des + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: VDD_SPI_PWR_SEL_SW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: POWER_CK_WAIT_CNTL + description: need_des + addressOffset: 284 + size: 32 + resetValue: 16777472 + fields: + - name: WAIT_XTL_STABLE + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: WAIT_PLL_STABLE + description: need_des + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SLP_WAKEUP_CNTL0 + description: need_des + addressOffset: 288 + size: 32 + fields: + - name: SLEEP_REQ + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SLP_WAKEUP_CNTL1 + description: need_des + addressOffset: 292 + size: 32 + fields: + - name: SLEEP_REJECT_ENA + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: SLP_REJECT_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SLP_WAKEUP_CNTL2 + description: need_des + addressOffset: 296 + size: 32 + fields: + - name: WAKEUP_ENA + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SLP_WAKEUP_CNTL3 + description: need_des + addressOffset: 300 + size: 32 + fields: + - name: LP_MIN_SLP_VAL + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HP_MIN_SLP_VAL + description: need_des + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SLEEP_PRT_SEL + description: need_des + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: SLP_WAKEUP_CNTL4 + description: need_des + addressOffset: 304 + size: 32 + fields: + - name: SLP_REJECT_CAUSE_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SLP_WAKEUP_CNTL5 + description: need_des + addressOffset: 308 + size: 32 + resetValue: 16777344 + fields: + - name: MODEM_WAIT_TARGET + description: need_des + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: LP_ANA_WAIT_TARGET + description: need_des + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: SLP_WAKEUP_CNTL6 + description: need_des + addressOffset: 312 + size: 32 + resetValue: 128 + fields: + - name: SOC_WAKEUP_WAIT + description: need_des + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: SOC_WAKEUP_WAIT_CFG + description: need_des + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: SLP_WAKEUP_CNTL7 + description: need_des + addressOffset: 316 + size: 32 + resetValue: 65536 + fields: + - name: ANA_WAIT_TARGET + description: need_des + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SLP_WAKEUP_STATUS0 + description: need_des + addressOffset: 320 + size: 32 + fields: + - name: WAKEUP_CAUSE + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SLP_WAKEUP_STATUS1 + description: need_des + addressOffset: 324 + size: 32 + fields: + - name: REJECT_CAUSE + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HP_CK_POWERON + description: need_des + addressOffset: 328 + size: 32 + resetValue: 50 + fields: + - name: I2C_POR_WAIT_TARGET + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: HP_CK_CNTL + description: need_des + addressOffset: 332 + size: 32 + resetValue: 2570 + fields: + - name: MODIFY_ICG_CNTL_WAIT + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SWITCH_ICG_CNTL_WAIT + description: need_des + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: POR_STATUS + description: need_des + addressOffset: 336 + size: 32 + resetValue: 2147483648 + fields: + - name: POR_DONE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: RF_PWC + description: need_des + addressOffset: 340 + size: 32 + resetValue: 134217728 + fields: + - name: PERIF_I2C_RSTB + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: XPD_PERIF_I2C + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: XPD_TXRF_I2C + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: XPD_RFRX_PBUS + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: XPD_CKGEN_I2C + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: XPD_PLL_I2C + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: BACKUP_CFG + description: need_des + addressOffset: 344 + size: 32 + resetValue: 2147483648 + fields: + - name: BACKUP_SYS_CLK_NO_DIV + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: need_des + addressOffset: 348 + size: 32 + fields: + - name: LP_CPU_EXC_INT_RAW + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SDIO_IDLE_INT_RAW + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SW_INT_RAW + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SOC_SLEEP_REJECT_INT_RAW + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SOC_WAKEUP_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_INT_ST + description: need_des + addressOffset: 352 + size: 32 + fields: + - name: LP_CPU_EXC_INT_ST + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: SDIO_IDLE_INT_ST + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SW_INT_ST + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: SOC_SLEEP_REJECT_INT_ST + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: SOC_WAKEUP_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: HP_INT_ENA + description: need_des + addressOffset: 356 + size: 32 + fields: + - name: LP_CPU_EXC_INT_ENA + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SDIO_IDLE_INT_ENA + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SW_INT_ENA + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SOC_SLEEP_REJECT_INT_ENA + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SOC_WAKEUP_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_INT_CLR + description: need_des + addressOffset: 360 + size: 32 + fields: + - name: LP_CPU_EXC_INT_CLR + description: need_des + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: SDIO_IDLE_INT_CLR + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: SW_INT_CLR + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: SOC_SLEEP_REJECT_INT_CLR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: SOC_WAKEUP_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: LP_INT_RAW + description: need_des + addressOffset: 364 + size: 32 + fields: + - name: LP_CPU_WAKEUP_INT_RAW + description: need_des + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: MODEM_SWITCH_ACTIVE_END_INT_RAW + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SLEEP_SWITCH_ACTIVE_END_INT_RAW + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SLEEP_SWITCH_MODEM_END_INT_RAW + description: need_des + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: MODEM_SWITCH_SLEEP_END_INT_RAW + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ACTIVE_SWITCH_SLEEP_END_INT_RAW + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: MODEM_SWITCH_ACTIVE_START_INT_RAW + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SLEEP_SWITCH_ACTIVE_START_INT_RAW + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SLEEP_SWITCH_MODEM_START_INT_RAW + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: MODEM_SWITCH_SLEEP_START_INT_RAW + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ACTIVE_SWITCH_SLEEP_START_INT_RAW + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HP_SW_TRIGGER_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_INT_ST + description: need_des + addressOffset: 368 + size: 32 + fields: + - name: LP_CPU_WAKEUP_INT_ST + description: need_des + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: MODEM_SWITCH_ACTIVE_END_INT_ST + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SLEEP_SWITCH_ACTIVE_END_INT_ST + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: SLEEP_SWITCH_MODEM_END_INT_ST + description: need_des + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: MODEM_SWITCH_SLEEP_END_INT_ST + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: ACTIVE_SWITCH_SLEEP_END_INT_ST + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: MODEM_SWITCH_ACTIVE_START_INT_ST + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: SLEEP_SWITCH_ACTIVE_START_INT_ST + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: SLEEP_SWITCH_MODEM_START_INT_ST + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: MODEM_SWITCH_SLEEP_START_INT_ST + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: ACTIVE_SWITCH_SLEEP_START_INT_ST + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: HP_SW_TRIGGER_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: LP_INT_ENA + description: need_des + addressOffset: 372 + size: 32 + fields: + - name: LP_CPU_WAKEUP_INT_ENA + description: need_des + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: MODEM_SWITCH_ACTIVE_END_INT_ENA + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SLEEP_SWITCH_ACTIVE_END_INT_ENA + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SLEEP_SWITCH_MODEM_END_INT_ENA + description: need_des + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: MODEM_SWITCH_SLEEP_END_INT_ENA + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ACTIVE_SWITCH_SLEEP_END_INT_ENA + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: MODEM_SWITCH_ACTIVE_START_INT_ENA + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SLEEP_SWITCH_ACTIVE_START_INT_ENA + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SLEEP_SWITCH_MODEM_START_INT_ENA + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: MODEM_SWITCH_SLEEP_START_INT_ENA + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ACTIVE_SWITCH_SLEEP_START_INT_ENA + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HP_SW_TRIGGER_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_INT_CLR + description: need_des + addressOffset: 376 + size: 32 + fields: + - name: LP_CPU_WAKEUP_INT_CLR + description: need_des + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: MODEM_SWITCH_ACTIVE_END_INT_CLR + description: need_des + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: SLEEP_SWITCH_ACTIVE_END_INT_CLR + description: need_des + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: SLEEP_SWITCH_MODEM_END_INT_CLR + description: need_des + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: MODEM_SWITCH_SLEEP_END_INT_CLR + description: need_des + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: ACTIVE_SWITCH_SLEEP_END_INT_CLR + description: need_des + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: MODEM_SWITCH_ACTIVE_START_INT_CLR + description: need_des + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: SLEEP_SWITCH_ACTIVE_START_INT_CLR + description: need_des + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: SLEEP_SWITCH_MODEM_START_INT_CLR + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: MODEM_SWITCH_SLEEP_START_INT_CLR + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: ACTIVE_SWITCH_SLEEP_START_INT_CLR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: HP_SW_TRIGGER_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: LP_CPU_PWR0 + description: need_des + addressOffset: 380 + size: 32 + resetValue: 535822336 + fields: + - name: LP_CPU_WAITI_RDY + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: LP_CPU_STALL_RDY + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: LP_CPU_FORCE_STALL + description: need_des + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: LP_CPU_SLP_WAITI_FLAG_EN + description: need_des + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: LP_CPU_SLP_STALL_FLAG_EN + description: need_des + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: LP_CPU_SLP_STALL_WAIT + description: need_des + bitOffset: 21 + bitWidth: 8 + access: read-write + - name: LP_CPU_SLP_STALL_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LP_CPU_SLP_RESET_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_CPU_SLP_BYPASS_INTR_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_CPU_PWR1 + description: need_des + addressOffset: 384 + size: 32 + fields: + - name: LP_CPU_WAKEUP_EN + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: LP_CPU_SLEEP_REQ + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: HP_LP_CPU_COMM + description: need_des + addressOffset: 388 + size: 32 + fields: + - name: LP_TRIGGER_HP + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: HP_TRIGGER_LP + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: HP_REGULATOR_CFG + description: need_des + addressOffset: 392 + size: 32 + fields: + - name: DIG_REGULATOR_EN_CAL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: MAIN_STATE + description: need_des + addressOffset: 396 + size: 32 + resetValue: 135268352 + fields: + - name: MAIN_LAST_ST_STATE + description: need_des + bitOffset: 11 + bitWidth: 7 + access: read-only + - name: MAIN_TAR_ST_STATE + description: need_des + bitOffset: 18 + bitWidth: 7 + access: read-only + - name: MAIN_CUR_ST_STATE + description: need_des + bitOffset: 25 + bitWidth: 7 + access: read-only + - register: + name: PWR_STATE + description: need_des + addressOffset: 400 + size: 32 + resetValue: 8396800 + fields: + - name: BACKUP_ST_STATE + description: need_des + bitOffset: 13 + bitWidth: 5 + access: read-only + - name: LP_PWR_ST_STATE + description: need_des + bitOffset: 18 + bitWidth: 5 + access: read-only + - name: HP_PWR_ST_STATE + description: need_des + bitOffset: 23 + bitWidth: 9 + access: read-only + - register: + name: CLK_STATE0 + description: need_des + addressOffset: 404 + size: 32 + resetValue: 3 + fields: + - name: STABLE_XPD_BBPLL_STATE + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: STABLE_XPD_XTAL_STATE + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SYS_CLK_SLP_SEL_STATE + description: need_des + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SYS_CLK_SEL_STATE + description: need_des + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: SYS_CLK_NO_DIV_STATE + description: need_des + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: ICG_SYS_CLK_EN_STATE + description: need_des + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: ICG_MODEM_SWITCH_STATE + description: need_des + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: ICG_MODEM_CODE_STATE + description: need_des + bitOffset: 21 + bitWidth: 2 + access: read-only + - name: ICG_SLP_SEL_STATE + description: need_des + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: ICG_GLOBAL_XTAL_STATE + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: ICG_GLOBAL_PLL_STATE + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: ANA_I2C_ISO_EN_STATE + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: ANA_I2C_RETENTION_STATE + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: ANA_XPD_BB_I2C_STATE + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: ANA_XPD_BBPLL_I2C_STATE + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: ANA_XPD_BBPLL_STATE + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: ANA_XPD_XTAL_STATE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CLK_STATE1 + description: need_des + addressOffset: 408 + size: 32 + resetValue: 4294967295 + fields: + - name: ICG_FUNC_EN_STATE + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CLK_STATE2 + description: need_des + addressOffset: 412 + size: 32 + resetValue: 4294967295 + fields: + - name: ICG_APB_EN_STATE + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: VDD_SPI_STATUS + description: need_des + addressOffset: 416 + size: 32 + fields: + - name: STABLE_VDD_SPI_PWR_DRV + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 35676752 + fields: + - name: PMU_DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: RMT + description: Remote Control + groupName: RMT + baseAddress: 1610637312 + addressBlock: + - offset: 0 + size: 120 + usage: registers + interrupt: + - name: RMT + value: 49 + registers: + - register: + dim: 4 + dimIncrement: 4 + name: CH%sDATA + description: The read and write data register for CHANNEL%s by apb fifo access. + addressOffset: 0 + size: 32 + fields: + - name: DATA + description: Read and write data for channel %s via APB FIFO. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 2 + dimIncrement: 4 + name: CH%s_TX_CONF0 + description: Channel %s configure register 0 + addressOffset: 16 + size: 32 + resetValue: 7406080 + fields: + - name: TX_START + description: Set this bit to start sending data on CHANNEL%s. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: MEM_RD_RST + description: Set this bit to reset read ram address for CHANNEL%s by accessing transmitter. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: APB_MEM_RST + description: Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TX_CONTI_MODE + description: Set this bit to restart transmission from the first data to the last data in CHANNEL%s. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MEM_TX_WRAP_EN + description: "This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IDLE_OUT_LV + description: This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: IDLE_OUT_EN + description: This is the output enable-control bit for CHANNEL%s in IDLE state. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_STOP + description: Set this bit to stop the transmitter of CHANNEL%s sending data out. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DIV_CNT + description: This register is used to configure the divider for clock of CHANNEL%s. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: MEM_SIZE + description: This register is used to configure the maximum size of memory allocated to CHANNEL%s. + bitOffset: 16 + bitWidth: 3 + access: read-write + - name: CARRIER_EFF_EN + description: "1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CARRIER_EN + description: "This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CARRIER_OUT_LV + description: "This bit is used to configure the position of carrier wave for CHANNEL%s.\n\n1'h0: add carrier wave on low level.\n\n1'h1: add carrier wave on high level." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: AFIFO_RST + description: Reserved + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: CONF_UPDATE + description: synchronization bit for CHANNEL%s + bitOffset: 24 + bitWidth: 1 + access: write-only + - register: + dim: 2 + dimIncrement: 8 + dimIndex: "2,3" + name: CH%s_RX_CONF0 + description: Channel %s configure register 0 + addressOffset: 24 + size: 32 + resetValue: 822083330 + fields: + - name: DIV_CNT + description: This register is used to configure the divider for clock of CHANNEL%s. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: IDLE_THRES + description: "When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished." + bitOffset: 8 + bitWidth: 15 + access: read-write + - name: MEM_SIZE + description: This register is used to configure the maximum size of memory allocated to CHANNEL%s. + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: CARRIER_EN + description: "This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CARRIER_OUT_LV + description: "This bit is used to configure the position of carrier wave for CHANNEL%s.\n\n1'h0: add carrier wave on low level.\n\n1'h1: add carrier wave on high level." + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + dim: 2 + dimIncrement: 8 + dimIndex: "2,3" + name: CH%s_RX_CONF1 + description: Channel %s configure register 1 + addressOffset: 28 + size: 32 + resetValue: 488 + fields: + - name: RX_EN + description: Set this bit to enable receiver to receive data on CHANNEL%s. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_WR_RST + description: Set this bit to reset write ram address for CHANNEL%s by accessing receiver. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: APB_MEM_RST + description: Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: MEM_OWNER + description: "This register marks the ownership of CHANNEL%s's ram block.\n\n1'h1: Receiver is using the ram. \n\n1'h0: APB bus is using the ram." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_FILTER_EN + description: "This is the receive filter's enable bit for CHANNEL%s." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_FILTER_THRES + description: Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode). + bitOffset: 5 + bitWidth: 8 + access: read-write + - name: MEM_RX_WRAP_EN + description: "This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: AFIFO_RST + description: Reserved + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: CONF_UPDATE + description: synchronization bit for CHANNEL%s + bitOffset: 15 + bitWidth: 1 + access: write-only + - register: + dim: 2 + dimIncrement: 4 + name: CH%s_TX_STATUS + description: Channel %s status register + addressOffset: 40 + size: 32 + fields: + - name: MEM_RADDR_EX + description: This register records the memory address offset when transmitter of CHANNEL%s is using the RAM. + bitOffset: 0 + bitWidth: 9 + access: read-only + - name: STATE + description: This register records the FSM status of CHANNEL%s. + bitOffset: 9 + bitWidth: 3 + access: read-only + - name: APB_MEM_WADDR + description: This register records the memory address offset when writes RAM over APB bus. + bitOffset: 12 + bitWidth: 9 + access: read-only + - name: APB_MEM_RD_ERR + description: This status bit will be set if the offset address out of memory size when reading via APB bus. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: MEM_EMPTY + description: This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled. + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: APB_MEM_WR_ERR + description: This status bit will be set if the offset address out of memory size when writes via APB bus. + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: APB_MEM_RADDR + description: This register records the memory address offset when reading RAM over APB bus. + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + dim: 2 + dimIncrement: 4 + name: CH%s_RX_STATUS + description: Channel %s status register + addressOffset: 48 + size: 32 + fields: + - name: MEM_WADDR_EX + description: This register records the memory address offset when receiver of CHANNEL%s is using the RAM. + bitOffset: 0 + bitWidth: 9 + access: read-only + - name: APB_MEM_RADDR + description: This register records the memory address offset when reads RAM over APB bus. + bitOffset: 12 + bitWidth: 9 + access: read-only + - name: STATE + description: This register records the FSM status of CHANNEL%s. + bitOffset: 22 + bitWidth: 3 + access: read-only + - name: MEM_OWNER_ERR + description: This status bit will be set when the ownership of memory block is wrong. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: MEM_FULL + description: This status bit will be set if the receiver receives more data than the memory size. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: APB_MEM_RD_ERR + description: This status bit will be set if the offset address out of memory size when reads via APB bus. + bitOffset: 27 + bitWidth: 1 + access: read-only + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 56 + size: 32 + fields: + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_END + description: The interrupt raw bit for CHANNEL%s. Triggered when transmission done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_END + description: The interrupt raw bit for CHANNEL2. Triggered when reception done. + bitOffset: 2 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_ERR + description: The interrupt raw bit for CHANNEL4. Triggered when error occurs. + bitOffset: 4 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_ERR + description: The interrupt raw bit for CHANNEL6. Triggered when error occurs. + bitOffset: 6 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_THR_EVENT + description: The interrupt raw bit for CHANNEL%s. Triggered when transmitter sent more data than configured value. + bitOffset: 8 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_THR_EVENT + description: The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than configured value. + bitOffset: 10 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_LOOP + description: The interrupt raw bit for CHANNEL%s. Triggered when the loop count reaches the configured threshold value. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 60 + size: 32 + fields: + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_END + description: The masked interrupt status bit for CH%s_TX_END_INT. + bitOffset: 0 + bitWidth: 1 + access: read-only + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_END + description: The masked interrupt status bit for CH2_RX_END_INT. + bitOffset: 2 + bitWidth: 1 + access: read-only + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_ERR + description: The masked interrupt status bit for CH4_ERR_INT. + bitOffset: 4 + bitWidth: 1 + access: read-only + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_ERR + description: The masked interrupt status bit for CH6_ERR_INT. + bitOffset: 6 + bitWidth: 1 + access: read-only + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_THR_EVENT + description: The masked interrupt status bit for CH%s_TX_THR_EVENT_INT. + bitOffset: 8 + bitWidth: 1 + access: read-only + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_THR_EVENT + description: The masked interrupt status bit for CH2_RX_THR_EVENT_INT. + bitOffset: 10 + bitWidth: 1 + access: read-only + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_X_LOOP + description: The masked interrupt status bit for CH%s_TX_LOOP_INT. + bitOffset: 12 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 64 + size: 32 + fields: + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_END + description: The interrupt enable bit for CH%s_TX_END_INT. + bitOffset: 0 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_END + description: The interrupt enable bit for CH2_RX_END_INT. + bitOffset: 2 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_ERR + description: The interrupt enable bit for CH4_ERR_INT. + bitOffset: 4 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_ERR + description: The interrupt enable bit for CH6_ERR_INT. + bitOffset: 6 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_THR_EVENT + description: The interrupt enable bit for CH%s_TX_THR_EVENT_INT. + bitOffset: 8 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_THR_EVENT + description: The interrupt enable bit for CH2_RX_THR_EVENT_INT. + bitOffset: 10 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_X_LOOP + description: The interrupt enable bit for CH%s_TX_LOOP_INT. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 68 + size: 32 + fields: + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_END + description: Set this bit to clear theCH%s_TX_END_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_END + description: Set this bit to clear theCH2_RX_END_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_ERR + description: Set this bit to clear theCH4_ERR_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_ERR + description: Set this bit to clear theCH6_ERR_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_THR_EVENT + description: Set this bit to clear theCH%s_TX_THR_EVENT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_THR_EVENT + description: Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_LOOP + description: Set this bit to clear theCH%s_TX_LOOP_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - register: + dim: 2 + dimIncrement: 4 + name: CH%sCARRIER_DUTY + description: Channel %s duty cycle configuration register + addressOffset: 72 + size: 32 + resetValue: 4194368 + fields: + - name: CARRIER_LOW + description: "This register is used to configure carrier wave 's low level clock period for CHANNEL%s." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CARRIER_HIGH + description: "This register is used to configure carrier wave 's high level clock period for CHANNEL%s." + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + dim: 2 + dimIncrement: 4 + name: CH%s_RX_CARRIER_RM + description: Channel %s carrier remove register + addressOffset: 80 + size: 32 + fields: + - name: CARRIER_LOW_THRES + description: The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CARRIER_HIGH_THRES + description: The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + dim: 2 + dimIncrement: 4 + name: CH%s_TX_LIM + description: Channel %s Tx event configuration register + addressOffset: 88 + size: 32 + resetValue: 128 + fields: + - name: TX_LIM + description: This register is used to configure the maximum entries that CHANNEL%s can send out. + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: TX_LOOP_NUM + description: This register is used to configure the maximum loop count when tx_conti_mode is valid. + bitOffset: 9 + bitWidth: 10 + access: read-write + - name: TX_LOOP_CNT_EN + description: This register is the enabled bit for loop count. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: LOOP_COUNT_RESET + description: This register is used to reset the loop count when tx_conti_mode is valid. + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: LOOP_STOP_EN + description: This bit is used to enable the loop send stop function after the loop counter counts to loop number for CHANNEL%s. + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + dim: 2 + dimIncrement: 4 + name: CH%s_RX_LIM + description: Channel %s Rx event configuration register + addressOffset: 96 + size: 32 + resetValue: 128 + fields: + - name: RMT_RX_LIM + description: This register is used to configure the maximum entries that CHANNEL%s can receive. + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SYS_CONF + description: RMT apb configuration register + addressOffset: 104 + size: 32 + resetValue: 83886096 + fields: + - name: APB_FIFO_MASK + description: "1'h1: access memory directly. 1'h0: access memory by FIFO." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_CLK_FORCE_ON + description: Set this bit to enable the clock for RMT memory. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PD + description: Set this bit to power down RMT memory. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PU + description: "1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SCLK_DIV_NUM + description: the integral part of the fractional divisor + bitOffset: 4 + bitWidth: 8 + access: read-write + - name: SCLK_DIV_A + description: the numerator of the fractional part of the fractional divisor + bitOffset: 12 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_B + description: the denominator of the fractional part of the fractional divisor + bitOffset: 18 + bitWidth: 6 + access: read-write + - name: SCLK_SEL + description: "choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL" + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: SCLK_ACTIVE + description: rmt_sclk switch + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TX_SIM + description: RMT TX synchronous register + addressOffset: 108 + size: 32 + fields: + - name: CH0 + description: Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CH1 + description: Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EN + description: This register is used to enable multiple of channels to start sending data synchronously. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: REF_CNT_RST + description: RMT clock divider reset register + addressOffset: 112 + size: 32 + fields: + - name: TX_REF_CNT_RST + description: This register is used to reset the clock divider of CHANNEL0. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TX_REF_CNT_RST_CH1 + description: This register is used to reset the clock divider of CHANNEL1. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_REF_CNT_RST_CH2 + description: This register is used to reset the clock divider of CHANNEL2. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: RX_REF_CNT_RST_CH3 + description: This register is used to reset the clock divider of CHANNEL3. + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: DATE + description: RMT version register + addressOffset: 204 + size: 32 + resetValue: 34636307 + fields: + - name: RMT_DATE + description: This is the version register. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: RNG + description: Hardware Random Number Generator + groupName: RNG + baseAddress: 1611343872 + addressBlock: + - offset: 0 + size: 4 + usage: registers + registers: + - register: + name: DATA + description: Random number data + addressOffset: 8 + size: 32 + access: read-only + - name: RSA + description: RSA (Rivest Shamir Adleman) Accelerator + groupName: RSA + baseAddress: 1611177984 + addressBlock: + - offset: 0 + size: 116 + usage: registers + interrupt: + - name: RSA + value: 75 + registers: + - register: + dim: 96 + dimIncrement: 4 + name: "M_MEM[%s]" + description: The memory that stores M + addressOffset: 0 + size: 32 + access: read-write + - register: + dim: 96 + dimIncrement: 4 + name: "Z_MEM[%s]" + description: The memory that stores Z + addressOffset: 512 + size: 32 + access: read-write + - register: + dim: 96 + dimIncrement: 4 + name: "Y_MEM[%s]" + description: The memory that stores Y + addressOffset: 1024 + size: 32 + access: read-write + - register: + dim: 96 + dimIncrement: 4 + name: "X_MEM[%s]" + description: The memory that stores X + addressOffset: 1536 + size: 32 + access: read-write + - register: + name: M_PRIME + description: RSA M_prime register + addressOffset: 2048 + size: 32 + fields: + - name: M_PRIME + description: "Those bits stores m'" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: MODE + description: RSA mode register + addressOffset: 2052 + size: 32 + fields: + - name: MODE + description: rsa mode (rsa length). + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: QUERY_CLEAN + description: RSA query clean register + addressOffset: 2056 + size: 32 + fields: + - name: QUERY_CLEAN + description: query clean + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: SET_START_MODEXP + description: RSA modular exponentiation trigger register. + addressOffset: 2060 + size: 32 + fields: + - name: SET_START_MODEXP + description: start modular exponentiation + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_START_MODMULT + description: RSA modular multiplication trigger register. + addressOffset: 2064 + size: 32 + fields: + - name: SET_START_MODMULT + description: start modular multiplication + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_START_MULT + description: RSA normal multiplication trigger register. + addressOffset: 2068 + size: 32 + fields: + - name: SET_START_MULT + description: start multiplicaiton + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: QUERY_IDLE + description: RSA query idle register + addressOffset: 2072 + size: 32 + fields: + - name: QUERY_IDLE + description: "query rsa idle. 1'b0: busy, 1'b1: idle" + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: RSA interrupt clear register + addressOffset: 2076 + size: 32 + fields: + - name: CLEAR_INTERRUPT + description: set this bit to clear RSA interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: CONSTANT_TIME + description: RSA constant time option register + addressOffset: 2080 + size: 32 + resetValue: 1 + fields: + - name: CONSTANT_TIME + description: "Configure this bit to 0 for acceleration. 0: with acceleration, 1: without acceleration(defalut)." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SEARCH_ENABLE + description: RSA search option + addressOffset: 2084 + size: 32 + fields: + - name: SEARCH_ENABLE + description: "Configure this bit to 1 for acceleration. 1: with acceleration, 0: without acceleration(default). This option should be used together with RSA_SEARCH_POS." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SEARCH_POS + description: RSA search position configure register + addressOffset: 2088 + size: 32 + fields: + - name: SEARCH_POS + description: Configure this field to set search position. This field should be used together with RSA_SEARCH_ENABLE. The field is only meaningful when RSA_SEARCH_ENABLE is high. + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: INT_ENA + description: RSA interrupt enable register + addressOffset: 2092 + size: 32 + fields: + - name: INT_ENA + description: "Set this bit to enable interrupt that occurs when rsa calculation is done. 1'b0: disable, 1'b1: enable(default)." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: RSA version control register + addressOffset: 2096 + size: 32 + resetValue: 538969624 + fields: + - name: DATE + description: rsa version information + bitOffset: 0 + bitWidth: 30 + access: read-write + - name: SHA + description: SHA (Secure Hash Algorithm) Accelerator + groupName: SHA + baseAddress: 1611173888 + addressBlock: + - offset: 0 + size: 176 + usage: registers + interrupt: + - name: SHA + value: 74 + registers: + - register: + name: MODE + description: Initial configuration register. + addressOffset: 0 + size: 32 + fields: + - name: MODE + description: Sha mode. + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: T_STRING + description: SHA 512/t configuration register 0. + addressOffset: 4 + size: 32 + fields: + - name: T_STRING + description: Sha t_string (used if and only if mode == SHA_512/t). + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: T_LENGTH + description: SHA 512/t configuration register 1. + addressOffset: 8 + size: 32 + fields: + - name: T_LENGTH + description: Sha t_length (used if and only if mode == SHA_512/t). + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: DMA_BLOCK_NUM + description: DMA configuration register 0. + addressOffset: 12 + size: 32 + fields: + - name: DMA_BLOCK_NUM + description: Dma-sha block number. + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: START + description: Typical SHA configuration register 0. + addressOffset: 16 + size: 32 + fields: + - name: START + description: Reserved. + bitOffset: 1 + bitWidth: 31 + access: write-only + - register: + name: CONTINUE + description: Typical SHA configuration register 1. + addressOffset: 20 + size: 32 + fields: + - name: CONTINUE + description: Reserved. + bitOffset: 1 + bitWidth: 31 + access: write-only + - register: + name: BUSY + description: Busy register. + addressOffset: 24 + size: 32 + fields: + - name: STATE + description: "Sha busy state. 1'b0: idle. 1'b1: busy." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: DMA_START + description: DMA configuration register 1. + addressOffset: 28 + size: 32 + fields: + - name: DMA_START + description: Start dma-sha. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: DMA_CONTINUE + description: DMA configuration register 2. + addressOffset: 32 + size: 32 + fields: + - name: DMA_CONTINUE + description: Continue dma-sha. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: CLEAR_IRQ + description: Interrupt clear register. + addressOffset: 36 + size: 32 + fields: + - name: CLEAR_INTERRUPT + description: Clear sha interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: IRQ_ENA + description: Interrupt enable register. + addressOffset: 40 + size: 32 + fields: + - name: INTERRUPT_ENA + description: "Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Date register. + addressOffset: 44 + size: 32 + resetValue: 538972713 + fields: + - name: DATE + description: Sha date information/ sha version information. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + name: "H_MEM[%s]" + description: Sha H memory which contains intermediate hash or finial hash. + addressOffset: 64 + size: 32 + - register: + dim: 16 + dimIncrement: 4 + name: "M_MEM[%s]" + description: Sha M memory which contains message. + addressOffset: 128 + size: 32 + - name: SLCHOST + description: SLCHOST Peripheral + groupName: SLCHOST + baseAddress: 1610706944 + addressBlock: + - offset: 0 + size: 260 + usage: registers + interrupt: + - name: SLC0 + value: 64 + - name: SLC1 + value: 65 + registers: + - register: + name: FUNC2_0 + description: "*******Description***********" + addressOffset: 16 + size: 32 + fields: + - name: SLC_FUNC2_INT + description: "*******Description***********" + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: FUNC2_1 + description: "*******Description***********" + addressOffset: 20 + size: 32 + fields: + - name: SLC_FUNC2_INT_EN + description: "*******Description***********" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: FUNC2_2 + description: "*******Description***********" + addressOffset: 32 + size: 32 + resetValue: 1 + fields: + - name: SLC_FUNC1_MDSTAT + description: "*******Description***********" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: GPIO_STATUS0 + description: "*******Description***********" + addressOffset: 52 + size: 32 + fields: + - name: GPIO_SDIO_INT0 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: GPIO_STATUS1 + description: "*******Description***********" + addressOffset: 56 + size: 32 + fields: + - name: GPIO_SDIO_INT1 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: GPIO_IN0 + description: "*******Description***********" + addressOffset: 60 + size: 32 + fields: + - name: GPIO_SDIO_IN0 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: GPIO_IN1 + description: "*******Description***********" + addressOffset: 64 + size: 32 + fields: + - name: GPIO_SDIO_IN1 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SLC0HOST_TOKEN_RDATA + description: "*******Description***********" + addressOffset: 68 + size: 32 + fields: + - name: SLC0_TOKEN0 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 12 + access: read-only + - name: SLC0_RX_PF_VALID + description: "*******Description***********" + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: HOSTSLCHOST_SLC0_TOKEN1 + description: "*******Description***********" + bitOffset: 16 + bitWidth: 12 + access: read-only + - name: SLC0_RX_PF_EOF + description: "*******Description***********" + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: SLC0_HOST_PF + description: "*******Description***********" + addressOffset: 72 + size: 32 + fields: + - name: SLC0_PF_DATA + description: "*******Description***********" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SLC1_HOST_PF + description: "*******Description***********" + addressOffset: 76 + size: 32 + fields: + - name: SLC1_PF_DATA + description: "*******Description***********" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SLC0HOST_INT_RAW + description: "*******Description***********" + addressOffset: 80 + size: 32 + fields: + - name: SLC0_TOHOST_BIT0_INT_RAW + description: "*******Description***********" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLC0_TOHOST_BIT1_INT_RAW + description: "*******Description***********" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SLC0_TOHOST_BIT2_INT_RAW + description: "*******Description***********" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLC0_TOHOST_BIT3_INT_RAW + description: "*******Description***********" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLC0_TOHOST_BIT4_INT_RAW + description: "*******Description***********" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SLC0_TOHOST_BIT5_INT_RAW + description: "*******Description***********" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SLC0_TOHOST_BIT6_INT_RAW + description: "*******Description***********" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SLC0_TOHOST_BIT7_INT_RAW + description: "*******Description***********" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SLC0_TOKEN0_1TO0_INT_RAW + description: "*******Description***********" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLC0_TOKEN1_1TO0_INT_RAW + description: "*******Description***********" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLC0_TOKEN0_0TO1_INT_RAW + description: "*******Description***********" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLC0_TOKEN1_0TO1_INT_RAW + description: "*******Description***********" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SLC0HOST_RX_SOF_INT_RAW + description: "*******Description***********" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SLC0HOST_RX_EOF_INT_RAW + description: "*******Description***********" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLC0HOST_RX_START_INT_RAW + description: "*******Description***********" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLC0HOST_TX_START_INT_RAW + description: "*******Description***********" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLC0_RX_UDF_INT_RAW + description: "*******Description***********" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SLC0_TX_OVF_INT_RAW + description: "*******Description***********" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SLC0_RX_PF_VALID_INT_RAW + description: "*******Description***********" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SLC0_EXT_BIT0_INT_RAW + description: "*******Description***********" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SLC0_EXT_BIT1_INT_RAW + description: "*******Description***********" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SLC0_EXT_BIT2_INT_RAW + description: "*******Description***********" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SLC0_EXT_BIT3_INT_RAW + description: "*******Description***********" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SLC0_RX_NEW_PACKET_INT_RAW + description: "*******Description***********" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SLC0_HOST_RD_RETRY_INT_RAW + description: "*******Description***********" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: GPIO_SDIO_INT_RAW + description: "*******Description***********" + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: SLC1HOST_INT_RAW + description: "*******Description***********" + addressOffset: 84 + size: 32 + fields: + - name: SLC1_TOHOST_BIT0_INT_RAW + description: "*******Description***********" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLC1_TOHOST_BIT1_INT_RAW + description: "*******Description***********" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SLC1_TOHOST_BIT2_INT_RAW + description: "*******Description***********" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLC1_TOHOST_BIT3_INT_RAW + description: "*******Description***********" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLC1_TOHOST_BIT4_INT_RAW + description: "*******Description***********" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SLC1_TOHOST_BIT5_INT_RAW + description: "*******Description***********" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SLC1_TOHOST_BIT6_INT_RAW + description: "*******Description***********" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SLC1_TOHOST_BIT7_INT_RAW + description: "*******Description***********" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SLC1_TOKEN0_1TO0_INT_RAW + description: "*******Description***********" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLC1_TOKEN1_1TO0_INT_RAW + description: "*******Description***********" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLC1_TOKEN0_0TO1_INT_RAW + description: "*******Description***********" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLC1_TOKEN1_0TO1_INT_RAW + description: "*******Description***********" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SLC1HOST_RX_SOF_INT_RAW + description: "*******Description***********" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SLC1HOST_RX_EOF_INT_RAW + description: "*******Description***********" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLC1HOST_RX_START_INT_RAW + description: "*******Description***********" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLC1HOST_TX_START_INT_RAW + description: "*******Description***********" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLC1_RX_UDF_INT_RAW + description: "*******Description***********" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SLC1_TX_OVF_INT_RAW + description: "*******Description***********" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SLC1_RX_PF_VALID_INT_RAW + description: "*******Description***********" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SLC1_EXT_BIT0_INT_RAW + description: "*******Description***********" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SLC1_EXT_BIT1_INT_RAW + description: "*******Description***********" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SLC1_EXT_BIT2_INT_RAW + description: "*******Description***********" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SLC1_EXT_BIT3_INT_RAW + description: "*******Description***********" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SLC1_WIFI_RX_NEW_PACKET_INT_RAW + description: "*******Description***********" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SLC1_HOST_RD_RETRY_INT_RAW + description: "*******Description***********" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SLC1_BT_RX_NEW_PACKET_INT_RAW + description: "*******Description***********" + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: SLC0HOST_INT_ST + description: "*******Description***********" + addressOffset: 88 + size: 32 + fields: + - name: SLC0_TOHOST_BIT0_INT_ST + description: "*******Description***********" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SLC0_TOHOST_BIT1_INT_ST + description: "*******Description***********" + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SLC0_TOHOST_BIT2_INT_ST + description: "*******Description***********" + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SLC0_TOHOST_BIT3_INT_ST + description: "*******Description***********" + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SLC0_TOHOST_BIT4_INT_ST + description: "*******Description***********" + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SLC0_TOHOST_BIT5_INT_ST + description: "*******Description***********" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SLC0_TOHOST_BIT6_INT_ST + description: "*******Description***********" + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SLC0_TOHOST_BIT7_INT_ST + description: "*******Description***********" + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SLC0_TOKEN0_1TO0_INT_ST + description: "*******Description***********" + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SLC0_TOKEN1_1TO0_INT_ST + description: "*******Description***********" + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SLC0_TOKEN0_0TO1_INT_ST + description: "*******Description***********" + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SLC0_TOKEN1_0TO1_INT_ST + description: "*******Description***********" + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: SLC0HOST_RX_SOF_INT_ST + description: "*******Description***********" + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SLC0HOST_RX_EOF_INT_ST + description: "*******Description***********" + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SLC0HOST_RX_START_INT_ST + description: "*******Description***********" + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SLC0HOST_TX_START_INT_ST + description: "*******Description***********" + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLC0_RX_UDF_INT_ST + description: "*******Description***********" + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: SLC0_TX_OVF_INT_ST + description: "*******Description***********" + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: SLC0_RX_PF_VALID_INT_ST + description: "*******Description***********" + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: SLC0_EXT_BIT0_INT_ST + description: "*******Description***********" + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: SLC0_EXT_BIT1_INT_ST + description: "*******Description***********" + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SLC0_EXT_BIT2_INT_ST + description: "*******Description***********" + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SLC0_EXT_BIT3_INT_ST + description: "*******Description***********" + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: SLC0_RX_NEW_PACKET_INT_ST + description: "*******Description***********" + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: SLC0_HOST_RD_RETRY_INT_ST + description: "*******Description***********" + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: GPIO_SDIO_INT_ST + description: "*******Description***********" + bitOffset: 25 + bitWidth: 1 + access: read-only + - register: + name: SLC1HOST_INT_ST + description: "*******Description***********" + addressOffset: 92 + size: 32 + fields: + - name: SLC1_TOHOST_BIT0_INT_ST + description: "*******Description***********" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SLC1_TOHOST_BIT1_INT_ST + description: "*******Description***********" + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SLC1_TOHOST_BIT2_INT_ST + description: "*******Description***********" + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SLC1_TOHOST_BIT3_INT_ST + description: "*******Description***********" + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SLC1_TOHOST_BIT4_INT_ST + description: "*******Description***********" + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SLC1_TOHOST_BIT5_INT_ST + description: "*******Description***********" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SLC1_TOHOST_BIT6_INT_ST + description: "*******Description***********" + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SLC1_TOHOST_BIT7_INT_ST + description: "*******Description***********" + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SLC1_TOKEN0_1TO0_INT_ST + description: "*******Description***********" + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SLC1_TOKEN1_1TO0_INT_ST + description: "*******Description***********" + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SLC1_TOKEN0_0TO1_INT_ST + description: "*******Description***********" + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SLC1_TOKEN1_0TO1_INT_ST + description: "*******Description***********" + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: SLC1HOST_RX_SOF_INT_ST + description: "*******Description***********" + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SLC1HOST_RX_EOF_INT_ST + description: "*******Description***********" + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SLC1HOST_RX_START_INT_ST + description: "*******Description***********" + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SLC1HOST_TX_START_INT_ST + description: "*******Description***********" + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLC1_RX_UDF_INT_ST + description: "*******Description***********" + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: SLC1_TX_OVF_INT_ST + description: "*******Description***********" + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: SLC1_RX_PF_VALID_INT_ST + description: "*******Description***********" + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: SLC1_EXT_BIT0_INT_ST + description: "*******Description***********" + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: SLC1_EXT_BIT1_INT_ST + description: "*******Description***********" + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SLC1_EXT_BIT2_INT_ST + description: "*******Description***********" + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SLC1_EXT_BIT3_INT_ST + description: "*******Description***********" + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: SLC1_WIFI_RX_NEW_PACKET_INT_ST + description: "*******Description***********" + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: SLC1_HOST_RD_RETRY_INT_ST + description: "*******Description***********" + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: SLC1_BT_RX_NEW_PACKET_INT_ST + description: "*******Description***********" + bitOffset: 25 + bitWidth: 1 + access: read-only + - register: + name: PKT_LEN + description: "*******Description***********" + addressOffset: 96 + size: 32 + fields: + - name: HOSTSLCHOST_SLC0_LEN + description: "*******Description***********" + bitOffset: 0 + bitWidth: 20 + access: read-only + - name: HOSTSLCHOST_SLC0_LEN_CHECK + description: "*******Description***********" + bitOffset: 20 + bitWidth: 12 + access: read-only + - register: + name: STATE_W0 + description: "*******Description***********" + addressOffset: 100 + size: 32 + fields: + - name: SLCHOST_STATE0 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: SLCHOST_STATE1 + description: "*******Description***********" + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: SLCHOST_STATE2 + description: "*******Description***********" + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: SLCHOST_STATE3 + description: "*******Description***********" + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: STATE_W1 + description: "*******Description***********" + addressOffset: 104 + size: 32 + fields: + - name: SLCHOST_STATE4 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: SLCHOST_STATE5 + description: "*******Description***********" + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: SLCHOST_STATE6 + description: "*******Description***********" + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: SLCHOST_STATE7 + description: "*******Description***********" + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: CONF_W0 + description: "*******Description***********" + addressOffset: 108 + size: 32 + fields: + - name: SLCHOST_CONF0 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF1 + description: "*******Description***********" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF2 + description: "*******Description***********" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF3 + description: "*******Description***********" + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: CONF_W1 + description: "*******Description***********" + addressOffset: 112 + size: 32 + fields: + - name: SLCHOST_CONF4 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF5 + description: "*******Description***********" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF6 + description: "*******Description***********" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF7 + description: "*******Description***********" + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: CONF_W2 + description: "*******Description***********" + addressOffset: 116 + size: 32 + fields: + - name: SLCHOST_CONF8 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF9 + description: "*******Description***********" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF10 + description: "*******Description***********" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF11 + description: "*******Description***********" + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: CONF_W3 + description: "*******Description***********" + addressOffset: 120 + size: 32 + resetValue: 192 + fields: + - name: SLCHOST_CONF12 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF13 + description: "*******Description***********" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF14 + description: "*******Description***********" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF15 + description: "*******Description***********" + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: CONF_W4 + description: "*******Description***********" + addressOffset: 124 + size: 32 + resetValue: 511 + fields: + - name: SLCHOST_CONF16 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF17 + description: "*******Description***********" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF18 + description: "*******Description***********" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF19 + description: "*******Description***********" + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: CONF_W5 + description: "*******Description***********" + addressOffset: 128 + size: 32 + fields: + - name: SLCHOST_CONF20 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF21 + description: "*******Description***********" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF22 + description: "*******Description***********" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF23 + description: "*******Description***********" + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: WIN_CMD + description: "*******Description***********" + addressOffset: 132 + size: 32 + fields: + - name: SLCHOST_WIN_CMD + description: "*******Description***********" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: CONF_W6 + description: "*******Description***********" + addressOffset: 136 + size: 32 + fields: + - name: SLCHOST_CONF24 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF25 + description: "*******Description***********" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF26 + description: "*******Description***********" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF27 + description: "*******Description***********" + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: CONF_W7 + description: "*******Description***********" + addressOffset: 140 + size: 32 + fields: + - name: SLCHOST_CONF28 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF29 + description: "*******Description***********" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF30 + description: "*******Description***********" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF31 + description: "*******Description***********" + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: PKT_LEN0 + description: "*******Description***********" + addressOffset: 144 + size: 32 + fields: + - name: HOSTSLCHOST_SLC0_LEN0 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 20 + access: read-only + - name: HOSTSLCHOST_SLC0_LEN0_CHECK + description: "*******Description***********" + bitOffset: 20 + bitWidth: 12 + access: read-only + - register: + name: PKT_LEN1 + description: "*******Description***********" + addressOffset: 148 + size: 32 + fields: + - name: HOSTSLCHOST_SLC0_LEN1 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 20 + access: read-only + - name: HOSTSLCHOST_SLC0_LEN1_CHECK + description: "*******Description***********" + bitOffset: 20 + bitWidth: 12 + access: read-only + - register: + name: PKT_LEN2 + description: "*******Description***********" + addressOffset: 152 + size: 32 + fields: + - name: HOSTSLCHOST_SLC0_LEN2 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 20 + access: read-only + - name: HOSTSLCHOST_SLC0_LEN2_CHECK + description: "*******Description***********" + bitOffset: 20 + bitWidth: 12 + access: read-only + - register: + name: CONF_W8 + description: "*******Description***********" + addressOffset: 156 + size: 32 + fields: + - name: SLCHOST_CONF32 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF33 + description: "*******Description***********" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF34 + description: "*******Description***********" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF35 + description: "*******Description***********" + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: CONF_W9 + description: "*******Description***********" + addressOffset: 160 + size: 32 + fields: + - name: SLCHOST_CONF36 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF37 + description: "*******Description***********" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF38 + description: "*******Description***********" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF39 + description: "*******Description***********" + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: CONF_W10 + description: "*******Description***********" + addressOffset: 164 + size: 32 + fields: + - name: SLCHOST_CONF40 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF41 + description: "*******Description***********" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF42 + description: "*******Description***********" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF43 + description: "*******Description***********" + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: CONF_W11 + description: "*******Description***********" + addressOffset: 168 + size: 32 + fields: + - name: SLCHOST_CONF44 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF45 + description: "*******Description***********" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF46 + description: "*******Description***********" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF47 + description: "*******Description***********" + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: CONF_W12 + description: "*******Description***********" + addressOffset: 172 + size: 32 + fields: + - name: SLCHOST_CONF48 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF49 + description: "*******Description***********" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF50 + description: "*******Description***********" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF51 + description: "*******Description***********" + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: CONF_W13 + description: "*******Description***********" + addressOffset: 176 + size: 32 + fields: + - name: SLCHOST_CONF52 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF53 + description: "*******Description***********" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF54 + description: "*******Description***********" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF55 + description: "*******Description***********" + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: CONF_W14 + description: "*******Description***********" + addressOffset: 180 + size: 32 + fields: + - name: SLCHOST_CONF56 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF57 + description: "*******Description***********" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF58 + description: "*******Description***********" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF59 + description: "*******Description***********" + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: CONF_W15 + description: "*******Description***********" + addressOffset: 184 + size: 32 + fields: + - name: SLCHOST_CONF60 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF61 + description: "*******Description***********" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF62 + description: "*******Description***********" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SLCHOST_CONF63 + description: "*******Description***********" + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: CHECK_SUM0 + description: "*******Description***********" + addressOffset: 188 + size: 32 + fields: + - name: SLCHOST_CHECK_SUM0 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CHECK_SUM1 + description: "*******Description***********" + addressOffset: 192 + size: 32 + resetValue: 319 + fields: + - name: SLCHOST_CHECK_SUM1 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SLC1HOST_TOKEN_RDATA + description: "*******Description***********" + addressOffset: 196 + size: 32 + fields: + - name: SLC1_TOKEN0 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 12 + access: read-only + - name: SLC1_RX_PF_VALID + description: "*******Description***********" + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: HOSTSLCHOST_SLC1_TOKEN1 + description: "*******Description***********" + bitOffset: 16 + bitWidth: 12 + access: read-only + - name: SLC1_RX_PF_EOF + description: "*******Description***********" + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: SLC0HOST_TOKEN_WDATA + description: "*******Description***********" + addressOffset: 200 + size: 32 + fields: + - name: SLC0HOST_TOKEN0_WD + description: "*******Description***********" + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: SLC0HOST_TOKEN1_WD + description: "*******Description***********" + bitOffset: 16 + bitWidth: 12 + access: read-write + - register: + name: SLC1HOST_TOKEN_WDATA + description: "*******Description***********" + addressOffset: 204 + size: 32 + fields: + - name: SLC1HOST_TOKEN0_WD + description: "*******Description***********" + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: SLC1HOST_TOKEN1_WD + description: "*******Description***********" + bitOffset: 16 + bitWidth: 12 + access: read-write + - register: + name: TOKEN_CON + description: "*******Description***********" + addressOffset: 208 + size: 32 + fields: + - name: SLC0HOST_TOKEN0_DEC + description: "*******Description***********" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SLC0HOST_TOKEN1_DEC + description: "*******Description***********" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SLC0HOST_TOKEN0_WR + description: "*******Description***********" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SLC0HOST_TOKEN1_WR + description: "*******Description***********" + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SLC1HOST_TOKEN0_DEC + description: "*******Description***********" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SLC1HOST_TOKEN1_DEC + description: "*******Description***********" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: SLC1HOST_TOKEN0_WR + description: "*******Description***********" + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: SLC1HOST_TOKEN1_WR + description: "*******Description***********" + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SLC0HOST_LEN_WR + description: "*******Description***********" + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: SLC0HOST_INT_CLR + description: "*******Description***********" + addressOffset: 212 + size: 32 + fields: + - name: SLC0_TOHOST_BIT0_INT_CLR + description: "*******Description***********" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SLC0_TOHOST_BIT1_INT_CLR + description: "*******Description***********" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SLC0_TOHOST_BIT2_INT_CLR + description: "*******Description***********" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SLC0_TOHOST_BIT3_INT_CLR + description: "*******Description***********" + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SLC0_TOHOST_BIT4_INT_CLR + description: "*******Description***********" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SLC0_TOHOST_BIT5_INT_CLR + description: "*******Description***********" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: SLC0_TOHOST_BIT6_INT_CLR + description: "*******Description***********" + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: SLC0_TOHOST_BIT7_INT_CLR + description: "*******Description***********" + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SLC0_TOKEN0_1TO0_INT_CLR + description: "*******Description***********" + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SLC0_TOKEN1_1TO0_INT_CLR + description: "*******Description***********" + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SLC0_TOKEN0_0TO1_INT_CLR + description: "*******Description***********" + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SLC0_TOKEN1_0TO1_INT_CLR + description: "*******Description***********" + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: SLC0HOST_RX_SOF_INT_CLR + description: "*******Description***********" + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: SLC0HOST_RX_EOF_INT_CLR + description: "*******Description***********" + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SLC0HOST_RX_START_INT_CLR + description: "*******Description***********" + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SLC0HOST_TX_START_INT_CLR + description: "*******Description***********" + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: SLC0_RX_UDF_INT_CLR + description: "*******Description***********" + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: SLC0_TX_OVF_INT_CLR + description: "*******Description***********" + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: SLC0_RX_PF_VALID_INT_CLR + description: "*******Description***********" + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: SLC0_EXT_BIT0_INT_CLR + description: "*******Description***********" + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: SLC0_EXT_BIT1_INT_CLR + description: "*******Description***********" + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: SLC0_EXT_BIT2_INT_CLR + description: "*******Description***********" + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: SLC0_EXT_BIT3_INT_CLR + description: "*******Description***********" + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: SLC0_RX_NEW_PACKET_INT_CLR + description: "*******Description***********" + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: SLC0_HOST_RD_RETRY_INT_CLR + description: "*******Description***********" + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: GPIO_SDIO_INT_CLR + description: "*******Description***********" + bitOffset: 25 + bitWidth: 1 + access: write-only + - register: + name: SLC1HOST_INT_CLR + description: "*******Description***********" + addressOffset: 216 + size: 32 + fields: + - name: SLC1_TOHOST_BIT0_INT_CLR + description: "*******Description***********" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SLC1_TOHOST_BIT1_INT_CLR + description: "*******Description***********" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SLC1_TOHOST_BIT2_INT_CLR + description: "*******Description***********" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SLC1_TOHOST_BIT3_INT_CLR + description: "*******Description***********" + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SLC1_TOHOST_BIT4_INT_CLR + description: "*******Description***********" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SLC1_TOHOST_BIT5_INT_CLR + description: "*******Description***********" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: SLC1_TOHOST_BIT6_INT_CLR + description: "*******Description***********" + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: SLC1_TOHOST_BIT7_INT_CLR + description: "*******Description***********" + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SLC1_TOKEN0_1TO0_INT_CLR + description: "*******Description***********" + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SLC1_TOKEN1_1TO0_INT_CLR + description: "*******Description***********" + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SLC1_TOKEN0_0TO1_INT_CLR + description: "*******Description***********" + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SLC1_TOKEN1_0TO1_INT_CLR + description: "*******Description***********" + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: SLC1HOST_RX_SOF_INT_CLR + description: "*******Description***********" + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: SLC1HOST_RX_EOF_INT_CLR + description: "*******Description***********" + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SLC1HOST_RX_START_INT_CLR + description: "*******Description***********" + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SLC1HOST_TX_START_INT_CLR + description: "*******Description***********" + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: SLC1_RX_UDF_INT_CLR + description: "*******Description***********" + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: SLC1_TX_OVF_INT_CLR + description: "*******Description***********" + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: SLC1_RX_PF_VALID_INT_CLR + description: "*******Description***********" + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: SLC1_EXT_BIT0_INT_CLR + description: "*******Description***********" + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: SLC1_EXT_BIT1_INT_CLR + description: "*******Description***********" + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: SLC1_EXT_BIT2_INT_CLR + description: "*******Description***********" + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: SLC1_EXT_BIT3_INT_CLR + description: "*******Description***********" + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: SLC1_WIFI_RX_NEW_PACKET_INT_CLR + description: "*******Description***********" + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: SLC1_HOST_RD_RETRY_INT_CLR + description: "*******Description***********" + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: SLC1_BT_RX_NEW_PACKET_INT_CLR + description: "*******Description***********" + bitOffset: 25 + bitWidth: 1 + access: write-only + - register: + name: SLC0HOST_FUNC1_INT_ENA + description: "*******Description***********" + addressOffset: 220 + size: 32 + fields: + - name: FN1_SLC0_TOHOST_BIT0_INT_ENA + description: "*******Description***********" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FN1_SLC0_TOHOST_BIT1_INT_ENA + description: "*******Description***********" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FN1_SLC0_TOHOST_BIT2_INT_ENA + description: "*******Description***********" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FN1_SLC0_TOHOST_BIT3_INT_ENA + description: "*******Description***********" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FN1_SLC0_TOHOST_BIT4_INT_ENA + description: "*******Description***********" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FN1_SLC0_TOHOST_BIT5_INT_ENA + description: "*******Description***********" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FN1_SLC0_TOHOST_BIT6_INT_ENA + description: "*******Description***********" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FN1_SLC0_TOHOST_BIT7_INT_ENA + description: "*******Description***********" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FN1_SLC0_TOKEN0_1TO0_INT_ENA + description: "*******Description***********" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FN1_SLC0_TOKEN1_1TO0_INT_ENA + description: "*******Description***********" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FN1_SLC0_TOKEN0_0TO1_INT_ENA + description: "*******Description***********" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FN1_SLC0_TOKEN1_0TO1_INT_ENA + description: "*******Description***********" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FN1_SLC0HOST_RX_SOF_INT_ENA + description: "*******Description***********" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FN1_SLC0HOST_RX_EOF_INT_ENA + description: "*******Description***********" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FN1_SLC0HOST_RX_START_INT_ENA + description: "*******Description***********" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: FN1_SLC0HOST_TX_START_INT_ENA + description: "*******Description***********" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: FN1_SLC0_RX_UDF_INT_ENA + description: "*******Description***********" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FN1_SLC0_TX_OVF_INT_ENA + description: "*******Description***********" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: FN1_SLC0_RX_PF_VALID_INT_ENA + description: "*******Description***********" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: FN1_SLC0_EXT_BIT0_INT_ENA + description: "*******Description***********" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: FN1_SLC0_EXT_BIT1_INT_ENA + description: "*******Description***********" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: FN1_SLC0_EXT_BIT2_INT_ENA + description: "*******Description***********" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: FN1_SLC0_EXT_BIT3_INT_ENA + description: "*******Description***********" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: FN1_SLC0_RX_NEW_PACKET_INT_ENA + description: "*******Description***********" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: FN1_SLC0_HOST_RD_RETRY_INT_ENA + description: "*******Description***********" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: FN1_GPIO_SDIO_INT_ENA + description: "*******Description***********" + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: SLC1HOST_FUNC1_INT_ENA + description: "*******Description***********" + addressOffset: 224 + size: 32 + fields: + - name: FN1_SLC1_TOHOST_BIT0_INT_ENA + description: "*******Description***********" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FN1_SLC1_TOHOST_BIT1_INT_ENA + description: "*******Description***********" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FN1_SLC1_TOHOST_BIT2_INT_ENA + description: "*******Description***********" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FN1_SLC1_TOHOST_BIT3_INT_ENA + description: "*******Description***********" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FN1_SLC1_TOHOST_BIT4_INT_ENA + description: "*******Description***********" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FN1_SLC1_TOHOST_BIT5_INT_ENA + description: "*******Description***********" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FN1_SLC1_TOHOST_BIT6_INT_ENA + description: "*******Description***********" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FN1_SLC1_TOHOST_BIT7_INT_ENA + description: "*******Description***********" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FN1_SLC1_TOKEN0_1TO0_INT_ENA + description: "*******Description***********" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FN1_SLC1_TOKEN1_1TO0_INT_ENA + description: "*******Description***********" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FN1_SLC1_TOKEN0_0TO1_INT_ENA + description: "*******Description***********" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FN1_SLC1_TOKEN1_0TO1_INT_ENA + description: "*******Description***********" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FN1_SLC1HOST_RX_SOF_INT_ENA + description: "*******Description***********" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FN1_SLC1HOST_RX_EOF_INT_ENA + description: "*******Description***********" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FN1_SLC1HOST_RX_START_INT_ENA + description: "*******Description***********" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: FN1_SLC1HOST_TX_START_INT_ENA + description: "*******Description***********" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: FN1_SLC1_RX_UDF_INT_ENA + description: "*******Description***********" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FN1_SLC1_TX_OVF_INT_ENA + description: "*******Description***********" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: FN1_SLC1_RX_PF_VALID_INT_ENA + description: "*******Description***********" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: FN1_SLC1_EXT_BIT0_INT_ENA + description: "*******Description***********" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: FN1_SLC1_EXT_BIT1_INT_ENA + description: "*******Description***********" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: FN1_SLC1_EXT_BIT2_INT_ENA + description: "*******Description***********" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: FN1_SLC1_EXT_BIT3_INT_ENA + description: "*******Description***********" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA + description: "*******Description***********" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: FN1_SLC1_HOST_RD_RETRY_INT_ENA + description: "*******Description***********" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA + description: "*******Description***********" + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: SLC0HOST_FUNC2_INT_ENA + description: "*******Description***********" + addressOffset: 228 + size: 32 + fields: + - name: FN2_SLC0_TOHOST_BIT0_INT_ENA + description: "*******Description***********" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FN2_SLC0_TOHOST_BIT1_INT_ENA + description: "*******Description***********" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FN2_SLC0_TOHOST_BIT2_INT_ENA + description: "*******Description***********" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FN2_SLC0_TOHOST_BIT3_INT_ENA + description: "*******Description***********" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FN2_SLC0_TOHOST_BIT4_INT_ENA + description: "*******Description***********" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FN2_SLC0_TOHOST_BIT5_INT_ENA + description: "*******Description***********" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FN2_SLC0_TOHOST_BIT6_INT_ENA + description: "*******Description***********" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FN2_SLC0_TOHOST_BIT7_INT_ENA + description: "*******Description***********" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FN2_SLC0_TOKEN0_1TO0_INT_ENA + description: "*******Description***********" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FN2_SLC0_TOKEN1_1TO0_INT_ENA + description: "*******Description***********" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FN2_SLC0_TOKEN0_0TO1_INT_ENA + description: "*******Description***********" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FN2_SLC0_TOKEN1_0TO1_INT_ENA + description: "*******Description***********" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FN2_SLC0HOST_RX_SOF_INT_ENA + description: "*******Description***********" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FN2_SLC0HOST_RX_EOF_INT_ENA + description: "*******Description***********" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FN2_SLC0HOST_RX_START_INT_ENA + description: "*******Description***********" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: FN2_SLC0HOST_TX_START_INT_ENA + description: "*******Description***********" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: FN2_SLC0_RX_UDF_INT_ENA + description: "*******Description***********" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FN2_SLC0_TX_OVF_INT_ENA + description: "*******Description***********" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: FN2_SLC0_RX_PF_VALID_INT_ENA + description: "*******Description***********" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: FN2_SLC0_EXT_BIT0_INT_ENA + description: "*******Description***********" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: FN2_SLC0_EXT_BIT1_INT_ENA + description: "*******Description***********" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: FN2_SLC0_EXT_BIT2_INT_ENA + description: "*******Description***********" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: FN2_SLC0_EXT_BIT3_INT_ENA + description: "*******Description***********" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: FN2_SLC0_RX_NEW_PACKET_INT_ENA + description: "*******Description***********" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: FN2_SLC0_HOST_RD_RETRY_INT_ENA + description: "*******Description***********" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: FN2_GPIO_SDIO_INT_ENA + description: "*******Description***********" + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: SLC1HOST_FUNC2_INT_ENA + description: "*******Description***********" + addressOffset: 232 + size: 32 + fields: + - name: FN2_SLC1_TOHOST_BIT0_INT_ENA + description: "*******Description***********" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FN2_SLC1_TOHOST_BIT1_INT_ENA + description: "*******Description***********" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FN2_SLC1_TOHOST_BIT2_INT_ENA + description: "*******Description***********" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FN2_SLC1_TOHOST_BIT3_INT_ENA + description: "*******Description***********" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FN2_SLC1_TOHOST_BIT4_INT_ENA + description: "*******Description***********" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FN2_SLC1_TOHOST_BIT5_INT_ENA + description: "*******Description***********" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FN2_SLC1_TOHOST_BIT6_INT_ENA + description: "*******Description***********" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FN2_SLC1_TOHOST_BIT7_INT_ENA + description: "*******Description***********" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FN2_SLC1_TOKEN0_1TO0_INT_ENA + description: "*******Description***********" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FN2_SLC1_TOKEN1_1TO0_INT_ENA + description: "*******Description***********" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FN2_SLC1_TOKEN0_0TO1_INT_ENA + description: "*******Description***********" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FN2_SLC1_TOKEN1_0TO1_INT_ENA + description: "*******Description***********" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FN2_SLC1HOST_RX_SOF_INT_ENA + description: "*******Description***********" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FN2_SLC1HOST_RX_EOF_INT_ENA + description: "*******Description***********" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FN2_SLC1HOST_RX_START_INT_ENA + description: "*******Description***********" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: FN2_SLC1HOST_TX_START_INT_ENA + description: "*******Description***********" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: FN2_SLC1_RX_UDF_INT_ENA + description: "*******Description***********" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FN2_SLC1_TX_OVF_INT_ENA + description: "*******Description***********" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: FN2_SLC1_RX_PF_VALID_INT_ENA + description: "*******Description***********" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: FN2_SLC1_EXT_BIT0_INT_ENA + description: "*******Description***********" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: FN2_SLC1_EXT_BIT1_INT_ENA + description: "*******Description***********" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: FN2_SLC1_EXT_BIT2_INT_ENA + description: "*******Description***********" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: FN2_SLC1_EXT_BIT3_INT_ENA + description: "*******Description***********" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA + description: "*******Description***********" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: FN2_SLC1_HOST_RD_RETRY_INT_ENA + description: "*******Description***********" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA + description: "*******Description***********" + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: SLC0HOST_INT_ENA + description: "*******Description***********" + addressOffset: 236 + size: 32 + fields: + - name: SLC0_TOHOST_BIT0_INT_ENA + description: "*******Description***********" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLC0_TOHOST_BIT1_INT_ENA + description: "*******Description***********" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SLC0_TOHOST_BIT2_INT_ENA + description: "*******Description***********" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLC0_TOHOST_BIT3_INT_ENA + description: "*******Description***********" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLC0_TOHOST_BIT4_INT_ENA + description: "*******Description***********" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SLC0_TOHOST_BIT5_INT_ENA + description: "*******Description***********" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SLC0_TOHOST_BIT6_INT_ENA + description: "*******Description***********" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SLC0_TOHOST_BIT7_INT_ENA + description: "*******Description***********" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SLC0_TOKEN0_1TO0_INT_ENA + description: "*******Description***********" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLC0_TOKEN1_1TO0_INT_ENA + description: "*******Description***********" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLC0_TOKEN0_0TO1_INT_ENA + description: "*******Description***********" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLC0_TOKEN1_0TO1_INT_ENA + description: "*******Description***********" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SLC0HOST_RX_SOF_INT_ENA + description: "*******Description***********" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SLC0HOST_RX_EOF_INT_ENA + description: "*******Description***********" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLC0HOST_RX_START_INT_ENA + description: "*******Description***********" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLC0HOST_TX_START_INT_ENA + description: "*******Description***********" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLC0_RX_UDF_INT_ENA + description: "*******Description***********" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SLC0_TX_OVF_INT_ENA + description: "*******Description***********" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SLC0_RX_PF_VALID_INT_ENA + description: "*******Description***********" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SLC0_EXT_BIT0_INT_ENA + description: "*******Description***********" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SLC0_EXT_BIT1_INT_ENA + description: "*******Description***********" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SLC0_EXT_BIT2_INT_ENA + description: "*******Description***********" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SLC0_EXT_BIT3_INT_ENA + description: "*******Description***********" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SLC0_RX_NEW_PACKET_INT_ENA + description: "*******Description***********" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SLC0_HOST_RD_RETRY_INT_ENA + description: "*******Description***********" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: GPIO_SDIO_INT_ENA + description: "*******Description***********" + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: SLC1HOST_INT_ENA + description: "*******Description***********" + addressOffset: 240 + size: 32 + fields: + - name: SLC1_TOHOST_BIT0_INT_ENA + description: "*******Description***********" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLC1_TOHOST_BIT1_INT_ENA + description: "*******Description***********" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SLC1_TOHOST_BIT2_INT_ENA + description: "*******Description***********" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLC1_TOHOST_BIT3_INT_ENA + description: "*******Description***********" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLC1_TOHOST_BIT4_INT_ENA + description: "*******Description***********" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SLC1_TOHOST_BIT5_INT_ENA + description: "*******Description***********" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SLC1_TOHOST_BIT6_INT_ENA + description: "*******Description***********" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SLC1_TOHOST_BIT7_INT_ENA + description: "*******Description***********" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SLC1_TOKEN0_1TO0_INT_ENA + description: "*******Description***********" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLC1_TOKEN1_1TO0_INT_ENA + description: "*******Description***********" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLC1_TOKEN0_0TO1_INT_ENA + description: "*******Description***********" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLC1_TOKEN1_0TO1_INT_ENA + description: "*******Description***********" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SLC1HOST_RX_SOF_INT_ENA + description: "*******Description***********" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SLC1HOST_RX_EOF_INT_ENA + description: "*******Description***********" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLC1HOST_RX_START_INT_ENA + description: "*******Description***********" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLC1HOST_TX_START_INT_ENA + description: "*******Description***********" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLC1_RX_UDF_INT_ENA + description: "*******Description***********" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SLC1_TX_OVF_INT_ENA + description: "*******Description***********" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SLC1_RX_PF_VALID_INT_ENA + description: "*******Description***********" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SLC1_EXT_BIT0_INT_ENA + description: "*******Description***********" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SLC1_EXT_BIT1_INT_ENA + description: "*******Description***********" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SLC1_EXT_BIT2_INT_ENA + description: "*******Description***********" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SLC1_EXT_BIT3_INT_ENA + description: "*******Description***********" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SLC1_WIFI_RX_NEW_PACKET_INT_ENA + description: "*******Description***********" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SLC1_HOST_RD_RETRY_INT_ENA + description: "*******Description***********" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SLC1_BT_RX_NEW_PACKET_INT_ENA + description: "*******Description***********" + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: SLC0HOST_RX_INFOR + description: "*******Description***********" + addressOffset: 244 + size: 32 + fields: + - name: SLC0HOST_RX_INFOR + description: "*******Description***********" + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: SLC1HOST_RX_INFOR + description: "*******Description***********" + addressOffset: 248 + size: 32 + fields: + - name: SLC1HOST_RX_INFOR + description: "*******Description***********" + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: SLC0HOST_LEN_WD + description: "*******Description***********" + addressOffset: 252 + size: 32 + fields: + - name: SLC0HOST_LEN_WD + description: "*******Description***********" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SLC_APBWIN_WDATA + description: "*******Description***********" + addressOffset: 256 + size: 32 + fields: + - name: SLC_APBWIN_WDATA + description: "*******Description***********" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SLC_APBWIN_CONF + description: "*******Description***********" + addressOffset: 260 + size: 32 + fields: + - name: SLC_APBWIN_ADDR + description: "*******Description***********" + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SLC_APBWIN_WR + description: "*******Description***********" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SLC_APBWIN_START + description: "*******Description***********" + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: SLC_APBWIN_RDATA + description: "*******Description***********" + addressOffset: 264 + size: 32 + fields: + - name: SLC_APBWIN_RDATA + description: "*******Description***********" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RDCLR0 + description: "*******Description***********" + addressOffset: 268 + size: 32 + resetValue: 245828 + fields: + - name: SLCHOST_SLC0_BIT7_CLRADDR + description: "*******Description***********" + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: SLCHOST_SLC0_BIT6_CLRADDR + description: "*******Description***********" + bitOffset: 9 + bitWidth: 9 + access: read-write + - register: + name: RDCLR1 + description: "*******Description***********" + addressOffset: 272 + size: 32 + resetValue: 246240 + fields: + - name: SLCHOST_SLC1_BIT7_CLRADDR + description: "*******Description***********" + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: SLCHOST_SLC1_BIT6_CLRADDR + description: "*******Description***********" + bitOffset: 9 + bitWidth: 9 + access: read-write + - register: + name: SLC0HOST_INT_ENA1 + description: "*******Description***********" + addressOffset: 276 + size: 32 + fields: + - name: SLC0_TOHOST_BIT0_INT_ENA1 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLC0_TOHOST_BIT1_INT_ENA1 + description: "*******Description***********" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SLC0_TOHOST_BIT2_INT_ENA1 + description: "*******Description***********" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLC0_TOHOST_BIT3_INT_ENA1 + description: "*******Description***********" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLC0_TOHOST_BIT4_INT_ENA1 + description: "*******Description***********" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SLC0_TOHOST_BIT5_INT_ENA1 + description: "*******Description***********" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SLC0_TOHOST_BIT6_INT_ENA1 + description: "*******Description***********" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SLC0_TOHOST_BIT7_INT_ENA1 + description: "*******Description***********" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SLC0_TOKEN0_1TO0_INT_ENA1 + description: "*******Description***********" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLC0_TOKEN1_1TO0_INT_ENA1 + description: "*******Description***********" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLC0_TOKEN0_0TO1_INT_ENA1 + description: "*******Description***********" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLC0_TOKEN1_0TO1_INT_ENA1 + description: "*******Description***********" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SLC0HOST_RX_SOF_INT_ENA1 + description: "*******Description***********" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SLC0HOST_RX_EOF_INT_ENA1 + description: "*******Description***********" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLC0HOST_RX_START_INT_ENA1 + description: "*******Description***********" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLC0HOST_TX_START_INT_ENA1 + description: "*******Description***********" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLC0_RX_UDF_INT_ENA1 + description: "*******Description***********" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SLC0_TX_OVF_INT_ENA1 + description: "*******Description***********" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SLC0_RX_PF_VALID_INT_ENA1 + description: "*******Description***********" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SLC0_EXT_BIT0_INT_ENA1 + description: "*******Description***********" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SLC0_EXT_BIT1_INT_ENA1 + description: "*******Description***********" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SLC0_EXT_BIT2_INT_ENA1 + description: "*******Description***********" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SLC0_EXT_BIT3_INT_ENA1 + description: "*******Description***********" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SLC0_RX_NEW_PACKET_INT_ENA1 + description: "*******Description***********" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SLC0_HOST_RD_RETRY_INT_ENA1 + description: "*******Description***********" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: GPIO_SDIO_INT_ENA1 + description: "*******Description***********" + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: SLC1HOST_INT_ENA1 + description: "*******Description***********" + addressOffset: 280 + size: 32 + fields: + - name: SLC1_TOHOST_BIT0_INT_ENA1 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLC1_TOHOST_BIT1_INT_ENA1 + description: "*******Description***********" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SLC1_TOHOST_BIT2_INT_ENA1 + description: "*******Description***********" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLC1_TOHOST_BIT3_INT_ENA1 + description: "*******Description***********" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLC1_TOHOST_BIT4_INT_ENA1 + description: "*******Description***********" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SLC1_TOHOST_BIT5_INT_ENA1 + description: "*******Description***********" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SLC1_TOHOST_BIT6_INT_ENA1 + description: "*******Description***********" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SLC1_TOHOST_BIT7_INT_ENA1 + description: "*******Description***********" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SLC1_TOKEN0_1TO0_INT_ENA1 + description: "*******Description***********" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLC1_TOKEN1_1TO0_INT_ENA1 + description: "*******Description***********" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLC1_TOKEN0_0TO1_INT_ENA1 + description: "*******Description***********" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLC1_TOKEN1_0TO1_INT_ENA1 + description: "*******Description***********" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SLC1HOST_RX_SOF_INT_ENA1 + description: "*******Description***********" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SLC1HOST_RX_EOF_INT_ENA1 + description: "*******Description***********" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLC1HOST_RX_START_INT_ENA1 + description: "*******Description***********" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLC1HOST_TX_START_INT_ENA1 + description: "*******Description***********" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLC1_RX_UDF_INT_ENA1 + description: "*******Description***********" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SLC1_TX_OVF_INT_ENA1 + description: "*******Description***********" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SLC1_RX_PF_VALID_INT_ENA1 + description: "*******Description***********" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SLC1_EXT_BIT0_INT_ENA1 + description: "*******Description***********" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SLC1_EXT_BIT1_INT_ENA1 + description: "*******Description***********" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SLC1_EXT_BIT2_INT_ENA1 + description: "*******Description***********" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SLC1_EXT_BIT3_INT_ENA1 + description: "*******Description***********" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 + description: "*******Description***********" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SLC1_HOST_RD_RETRY_INT_ENA1 + description: "*******Description***********" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SLC1_BT_RX_NEW_PACKET_INT_ENA1 + description: "*******Description***********" + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: SLCHOSTDATE + description: "*******Description***********" + addressOffset: 376 + size: 32 + resetValue: 554043136 + fields: + - name: SLCHOST_DATE + description: "*******Description***********" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SLCHOSTID + description: "*******Description***********" + addressOffset: 380 + size: 32 + resetValue: 1536 + fields: + - name: SLCHOST_ID + description: "*******Description***********" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CONF + description: "*******Description***********" + addressOffset: 496 + size: 32 + fields: + - name: FRC_SDIO11 + description: "*******Description***********" + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: FRC_SDIO20 + description: "*******Description***********" + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: FRC_NEG_SAMP + description: "*******Description***********" + bitOffset: 10 + bitWidth: 5 + access: read-write + - name: FRC_POS_SAMP + description: "*******Description***********" + bitOffset: 15 + bitWidth: 5 + access: read-write + - name: FRC_QUICK_IN + description: "*******Description***********" + bitOffset: 20 + bitWidth: 5 + access: read-write + - name: SDIO20_INT_DELAY + description: "*******Description***********" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: SDIO_PAD_PULLUP + description: "*******Description***********" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HSPEED_CON_EN + description: "*******Description***********" + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: INF_ST + description: "*******Description***********" + addressOffset: 500 + size: 32 + fields: + - name: SDIO20_MODE + description: "*******Description***********" + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: SDIO_NEG_SAMP + description: "*******Description***********" + bitOffset: 5 + bitWidth: 5 + access: read-only + - name: SDIO_QUICK_IN + description: "*******Description***********" + bitOffset: 10 + bitWidth: 5 + access: read-only + - name: DLL_ON_SW + description: dll is controlled by software + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DLL_ON + description: Software dll on + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CLK_MODE_SW + description: dll clock mode is controlled by software + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: CLK_MODE + description: Software set clock mode + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: SOC_ETM + description: Event Task Matrix + groupName: SOC_ETM + baseAddress: 1610690560 + addressBlock: + - offset: 0 + size: 432 + usage: registers + registers: + - register: + name: CH_ENA_AD0 + description: channel enable register + addressOffset: 0 + size: 32 + fields: + - name: CH_ENA0 + description: ch0 enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CH_ENA1 + description: ch1 enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CH_ENA2 + description: ch2 enable + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CH_ENA3 + description: ch3 enable + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CH_ENA4 + description: ch4 enable + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CH_ENA5 + description: ch5 enable + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CH_ENA6 + description: ch6 enable + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CH_ENA7 + description: ch7 enable + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CH_ENA8 + description: ch8 enable + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CH_ENA9 + description: ch9 enable + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CH_ENA10 + description: ch10 enable + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CH_ENA11 + description: ch11 enable + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CH_ENA12 + description: ch12 enable + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CH_ENA13 + description: ch13 enable + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: CH_ENA14 + description: ch14 enable + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CH_ENA15 + description: ch15 enable + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CH_ENA16 + description: ch16 enable + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CH_ENA17 + description: ch17 enable + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: CH_ENA18 + description: ch18 enable + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: CH_ENA19 + description: ch19 enable + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: CH_ENA20 + description: ch20 enable + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CH_ENA21 + description: ch21 enable + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CH_ENA22 + description: ch22 enable + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: CH_ENA23 + description: ch23 enable + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: CH_ENA24 + description: ch24 enable + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: CH_ENA25 + description: ch25 enable + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: CH_ENA26 + description: ch26 enable + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CH_ENA27 + description: ch27 enable + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: CH_ENA28 + description: ch28 enable + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CH_ENA29 + description: ch29 enable + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CH_ENA30 + description: ch30 enable + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CH_ENA31 + description: ch31 enable + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CH_ENA_AD0_SET + description: channel enable set register + addressOffset: 4 + size: 32 + fields: + - name: CH_SET0 + description: ch0 set + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CH_SET1 + description: ch1 set + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CH_SET2 + description: ch2 set + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CH_SET3 + description: ch3 set + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: CH_SET4 + description: ch4 set + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: CH_SET5 + description: ch5 set + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CH_SET6 + description: ch6 set + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: CH_SET7 + description: ch7 set + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: CH_SET8 + description: ch8 set + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: CH_SET9 + description: ch9 set + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: CH_SET10 + description: ch10 set + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: CH_SET11 + description: ch11 set + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: CH_SET12 + description: ch12 set + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: CH_SET13 + description: ch13 set + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: CH_SET14 + description: ch14 set + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: CH_SET15 + description: ch15 set + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: CH_SET16 + description: ch16 set + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: CH_SET17 + description: ch17 set + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: CH_SET18 + description: ch18 set + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: CH_SET19 + description: ch19 set + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: CH_SET20 + description: ch20 set + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: CH_SET21 + description: ch21 set + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: CH_SET22 + description: ch22 set + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: CH_SET23 + description: ch23 set + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: CH_SET24 + description: ch24 set + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: CH_SET25 + description: ch25 set + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: CH_SET26 + description: ch26 set + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: CH_SET27 + description: ch27 set + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: CH_SET28 + description: ch28 set + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: CH_SET29 + description: ch29 set + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: CH_SET30 + description: ch30 set + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: CH_SET31 + description: ch31 set + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: CH_ENA_AD0_CLR + description: channel enable clear register + addressOffset: 8 + size: 32 + fields: + - name: CH_CLR0 + description: ch0 clear + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CH_CLR1 + description: ch1 clear + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CH_CLR2 + description: ch2 clear + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CH_CLR3 + description: ch3 clear + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: CH_CLR4 + description: ch4 clear + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: CH_CLR5 + description: ch5 clear + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CH_CLR6 + description: ch6 clear + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: CH_CLR7 + description: ch7 clear + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: CH_CLR8 + description: ch8 clear + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: CH_CLR9 + description: ch9 clear + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: CH_CLR10 + description: ch10 clear + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: CH_CLR11 + description: ch11 clear + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: CH_CLR12 + description: ch12 clear + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: CH_CLR13 + description: ch13 clear + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: CH_CLR14 + description: ch14 clear + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: CH_CLR15 + description: ch15 clear + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: CH_CLR16 + description: ch16 clear + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: CH_CLR17 + description: ch17 clear + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: CH_CLR18 + description: ch18 clear + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: CH_CLR19 + description: ch19 clear + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: CH_CLR20 + description: ch20 clear + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: CH_CLR21 + description: ch21 clear + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: CH_CLR22 + description: ch22 clear + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: CH_CLR23 + description: ch23 clear + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: CH_CLR24 + description: ch24 clear + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: CH_CLR25 + description: ch25 clear + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: CH_CLR26 + description: ch26 clear + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: CH_CLR27 + description: ch27 clear + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: CH_CLR28 + description: ch28 clear + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: CH_CLR29 + description: ch29 clear + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: CH_CLR30 + description: ch30 clear + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: CH_CLR31 + description: ch31 clear + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: CH_ENA_AD1 + description: channel enable register + addressOffset: 12 + size: 32 + fields: + - name: CH_ENA32 + description: ch32 enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CH_ENA33 + description: ch33 enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CH_ENA34 + description: ch34 enable + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CH_ENA35 + description: ch35 enable + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CH_ENA36 + description: ch36 enable + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CH_ENA37 + description: ch37 enable + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CH_ENA38 + description: ch38 enable + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CH_ENA39 + description: ch39 enable + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CH_ENA40 + description: ch40 enable + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CH_ENA41 + description: ch41 enable + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CH_ENA42 + description: ch42 enable + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CH_ENA43 + description: ch43 enable + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CH_ENA44 + description: ch44 enable + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CH_ENA45 + description: ch45 enable + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: CH_ENA46 + description: ch46 enable + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CH_ENA47 + description: ch47 enable + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CH_ENA48 + description: ch48 enable + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CH_ENA49 + description: ch49 enable + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: CH_ENA_AD1_SET + description: channel enable set register + addressOffset: 16 + size: 32 + fields: + - name: CH_SET32 + description: ch32 set + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CH_SET33 + description: ch33 set + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CH_SET34 + description: ch34 set + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CH_SET35 + description: ch35 set + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: CH_SET36 + description: ch36 set + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: CH_SET37 + description: ch37 set + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CH_SET38 + description: ch38 set + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: CH_SET39 + description: ch39 set + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: CH_SET40 + description: ch40 set + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: CH_SET41 + description: ch41 set + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: CH_SET42 + description: ch42 set + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: CH_SET43 + description: ch43 set + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: CH_SET44 + description: ch44 set + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: CH_SET45 + description: ch45 set + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: CH_SET46 + description: ch46 set + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: CH_SET47 + description: ch47 set + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: CH_SET48 + description: ch48 set + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: CH_SET49 + description: ch49 set + bitOffset: 17 + bitWidth: 1 + access: write-only + - register: + name: CH_ENA_AD1_CLR + description: channel enable clear register + addressOffset: 20 + size: 32 + fields: + - name: CH_CLR32 + description: ch32 clear + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CH_CLR33 + description: ch33 clear + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CH_CLR34 + description: ch34 clear + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CH_CLR35 + description: ch35 clear + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: CH_CLR36 + description: ch36 clear + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: CH_CLR37 + description: ch37 clear + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CH_CLR38 + description: ch38 clear + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: CH_CLR39 + description: ch39 clear + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: CH_CLR40 + description: ch40 clear + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: CH_CLR41 + description: ch41 clear + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: CH_CLR42 + description: ch42 clear + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: CH_CLR43 + description: ch43 clear + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: CH_CLR44 + description: ch44 clear + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: CH_CLR45 + description: ch45 clear + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: CH_CLR46 + description: ch46 clear + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: CH_CLR47 + description: ch47 clear + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: CH_CLR48 + description: ch48 clear + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: CH_CLR49 + description: ch49 clear + bitOffset: 17 + bitWidth: 1 + access: write-only + - register: + name: CH0_EVT_ID + description: channel0 event id register + addressOffset: 24 + size: 32 + fields: + - name: CH0_EVT_ID + description: ch0_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH0_TASK_ID + description: channel0 task id register + addressOffset: 28 + size: 32 + fields: + - name: CH0_TASK_ID + description: ch0_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH1_EVT_ID + description: channel1 event id register + addressOffset: 32 + size: 32 + fields: + - name: CH1_EVT_ID + description: ch1_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH1_TASK_ID + description: channel1 task id register + addressOffset: 36 + size: 32 + fields: + - name: CH1_TASK_ID + description: ch1_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH2_EVT_ID + description: channel2 event id register + addressOffset: 40 + size: 32 + fields: + - name: CH2_EVT_ID + description: ch2_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH2_TASK_ID + description: channel2 task id register + addressOffset: 44 + size: 32 + fields: + - name: CH2_TASK_ID + description: ch2_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH3_EVT_ID + description: channel3 event id register + addressOffset: 48 + size: 32 + fields: + - name: CH3_EVT_ID + description: ch3_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH3_TASK_ID + description: channel3 task id register + addressOffset: 52 + size: 32 + fields: + - name: CH3_TASK_ID + description: ch3_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH4_EVT_ID + description: channel4 event id register + addressOffset: 56 + size: 32 + fields: + - name: CH4_EVT_ID + description: ch4_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH4_TASK_ID + description: channel4 task id register + addressOffset: 60 + size: 32 + fields: + - name: CH4_TASK_ID + description: ch4_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH5_EVT_ID + description: channel5 event id register + addressOffset: 64 + size: 32 + fields: + - name: CH5_EVT_ID + description: ch5_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH5_TASK_ID + description: channel5 task id register + addressOffset: 68 + size: 32 + fields: + - name: CH5_TASK_ID + description: ch5_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH6_EVT_ID + description: channel6 event id register + addressOffset: 72 + size: 32 + fields: + - name: CH6_EVT_ID + description: ch6_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH6_TASK_ID + description: channel6 task id register + addressOffset: 76 + size: 32 + fields: + - name: CH6_TASK_ID + description: ch6_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH7_EVT_ID + description: channel7 event id register + addressOffset: 80 + size: 32 + fields: + - name: CH7_EVT_ID + description: ch7_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH7_TASK_ID + description: channel7 task id register + addressOffset: 84 + size: 32 + fields: + - name: CH7_TASK_ID + description: ch7_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH8_EVT_ID + description: channel8 event id register + addressOffset: 88 + size: 32 + fields: + - name: CH8_EVT_ID + description: ch8_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH8_TASK_ID + description: channel8 task id register + addressOffset: 92 + size: 32 + fields: + - name: CH8_TASK_ID + description: ch8_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH9_EVT_ID + description: channel9 event id register + addressOffset: 96 + size: 32 + fields: + - name: CH9_EVT_ID + description: ch9_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH9_TASK_ID + description: channel9 task id register + addressOffset: 100 + size: 32 + fields: + - name: CH9_TASK_ID + description: ch9_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH10_EVT_ID + description: channel10 event id register + addressOffset: 104 + size: 32 + fields: + - name: CH10_EVT_ID + description: ch10_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH10_TASK_ID + description: channel10 task id register + addressOffset: 108 + size: 32 + fields: + - name: CH10_TASK_ID + description: ch10_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH11_EVT_ID + description: channel11 event id register + addressOffset: 112 + size: 32 + fields: + - name: CH11_EVT_ID + description: ch11_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH11_TASK_ID + description: channel11 task id register + addressOffset: 116 + size: 32 + fields: + - name: CH11_TASK_ID + description: ch11_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH12_EVT_ID + description: channel12 event id register + addressOffset: 120 + size: 32 + fields: + - name: CH12_EVT_ID + description: ch12_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH12_TASK_ID + description: channel12 task id register + addressOffset: 124 + size: 32 + fields: + - name: CH12_TASK_ID + description: ch12_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH13_EVT_ID + description: channel13 event id register + addressOffset: 128 + size: 32 + fields: + - name: CH13_EVT_ID + description: ch13_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH13_TASK_ID + description: channel13 task id register + addressOffset: 132 + size: 32 + fields: + - name: CH13_TASK_ID + description: ch13_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH14_EVT_ID + description: channel14 event id register + addressOffset: 136 + size: 32 + fields: + - name: CH14_EVT_ID + description: ch14_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH14_TASK_ID + description: channel14 task id register + addressOffset: 140 + size: 32 + fields: + - name: CH14_TASK_ID + description: ch14_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH15_EVT_ID + description: channel15 event id register + addressOffset: 144 + size: 32 + fields: + - name: CH15_EVT_ID + description: ch15_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH15_TASK_ID + description: channel15 task id register + addressOffset: 148 + size: 32 + fields: + - name: CH15_TASK_ID + description: ch15_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH16_EVT_ID + description: channel16 event id register + addressOffset: 152 + size: 32 + fields: + - name: CH16_EVT_ID + description: ch16_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH16_TASK_ID + description: channel16 task id register + addressOffset: 156 + size: 32 + fields: + - name: CH16_TASK_ID + description: ch16_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH17_EVT_ID + description: channel17 event id register + addressOffset: 160 + size: 32 + fields: + - name: CH17_EVT_ID + description: ch17_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH17_TASK_ID + description: channel17 task id register + addressOffset: 164 + size: 32 + fields: + - name: CH17_TASK_ID + description: ch17_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH18_EVT_ID + description: channel18 event id register + addressOffset: 168 + size: 32 + fields: + - name: CH18_EVT_ID + description: ch18_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH18_TASK_ID + description: channel18 task id register + addressOffset: 172 + size: 32 + fields: + - name: CH18_TASK_ID + description: ch18_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH19_EVT_ID + description: channel19 event id register + addressOffset: 176 + size: 32 + fields: + - name: CH19_EVT_ID + description: ch19_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH19_TASK_ID + description: channel19 task id register + addressOffset: 180 + size: 32 + fields: + - name: CH19_TASK_ID + description: ch19_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH20_EVT_ID + description: channel20 event id register + addressOffset: 184 + size: 32 + fields: + - name: CH20_EVT_ID + description: ch20_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH20_TASK_ID + description: channel20 task id register + addressOffset: 188 + size: 32 + fields: + - name: CH20_TASK_ID + description: ch20_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH21_EVT_ID + description: channel21 event id register + addressOffset: 192 + size: 32 + fields: + - name: CH21_EVT_ID + description: ch21_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH21_TASK_ID + description: channel21 task id register + addressOffset: 196 + size: 32 + fields: + - name: CH21_TASK_ID + description: ch21_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH22_EVT_ID + description: channel22 event id register + addressOffset: 200 + size: 32 + fields: + - name: CH22_EVT_ID + description: ch22_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH22_TASK_ID + description: channel22 task id register + addressOffset: 204 + size: 32 + fields: + - name: CH22_TASK_ID + description: ch22_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH23_EVT_ID + description: channel23 event id register + addressOffset: 208 + size: 32 + fields: + - name: CH23_EVT_ID + description: ch23_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH23_TASK_ID + description: channel23 task id register + addressOffset: 212 + size: 32 + fields: + - name: CH23_TASK_ID + description: ch23_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH24_EVT_ID + description: channel24 event id register + addressOffset: 216 + size: 32 + fields: + - name: CH24_EVT_ID + description: ch24_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH24_TASK_ID + description: channel24 task id register + addressOffset: 220 + size: 32 + fields: + - name: CH24_TASK_ID + description: ch24_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH25_EVT_ID + description: channel25 event id register + addressOffset: 224 + size: 32 + fields: + - name: CH25_EVT_ID + description: ch25_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH25_TASK_ID + description: channel25 task id register + addressOffset: 228 + size: 32 + fields: + - name: CH25_TASK_ID + description: ch25_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH26_EVT_ID + description: channel26 event id register + addressOffset: 232 + size: 32 + fields: + - name: CH26_EVT_ID + description: ch26_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH26_TASK_ID + description: channel26 task id register + addressOffset: 236 + size: 32 + fields: + - name: CH26_TASK_ID + description: ch26_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH27_EVT_ID + description: channel27 event id register + addressOffset: 240 + size: 32 + fields: + - name: CH27_EVT_ID + description: ch27_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH27_TASK_ID + description: channel27 task id register + addressOffset: 244 + size: 32 + fields: + - name: CH27_TASK_ID + description: ch27_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH28_EVT_ID + description: channel28 event id register + addressOffset: 248 + size: 32 + fields: + - name: CH28_EVT_ID + description: ch28_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH28_TASK_ID + description: channel28 task id register + addressOffset: 252 + size: 32 + fields: + - name: CH28_TASK_ID + description: ch28_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH29_EVT_ID + description: channel29 event id register + addressOffset: 256 + size: 32 + fields: + - name: CH29_EVT_ID + description: ch29_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH29_TASK_ID + description: channel29 task id register + addressOffset: 260 + size: 32 + fields: + - name: CH29_TASK_ID + description: ch29_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH30_EVT_ID + description: channel30 event id register + addressOffset: 264 + size: 32 + fields: + - name: CH30_EVT_ID + description: ch30_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH30_TASK_ID + description: channel30 task id register + addressOffset: 268 + size: 32 + fields: + - name: CH30_TASK_ID + description: ch30_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH31_EVT_ID + description: channel31 event id register + addressOffset: 272 + size: 32 + fields: + - name: CH31_EVT_ID + description: ch31_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH31_TASK_ID + description: channel31 task id register + addressOffset: 276 + size: 32 + fields: + - name: CH31_TASK_ID + description: ch31_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH32_EVT_ID + description: channel32 event id register + addressOffset: 280 + size: 32 + fields: + - name: CH32_EVT_ID + description: ch32_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH32_TASK_ID + description: channel32 task id register + addressOffset: 284 + size: 32 + fields: + - name: CH32_TASK_ID + description: ch32_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH33_EVT_ID + description: channel33 event id register + addressOffset: 288 + size: 32 + fields: + - name: CH33_EVT_ID + description: ch33_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH33_TASK_ID + description: channel33 task id register + addressOffset: 292 + size: 32 + fields: + - name: CH33_TASK_ID + description: ch33_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH34_EVT_ID + description: channel34 event id register + addressOffset: 296 + size: 32 + fields: + - name: CH34_EVT_ID + description: ch34_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH34_TASK_ID + description: channel34 task id register + addressOffset: 300 + size: 32 + fields: + - name: CH34_TASK_ID + description: ch34_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH35_EVT_ID + description: channel35 event id register + addressOffset: 304 + size: 32 + fields: + - name: CH35_EVT_ID + description: ch35_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH35_TASK_ID + description: channel35 task id register + addressOffset: 308 + size: 32 + fields: + - name: CH35_TASK_ID + description: ch35_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH36_EVT_ID + description: channel36 event id register + addressOffset: 312 + size: 32 + fields: + - name: CH36_EVT_ID + description: ch36_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH36_TASK_ID + description: channel36 task id register + addressOffset: 316 + size: 32 + fields: + - name: CH36_TASK_ID + description: ch36_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH37_EVT_ID + description: channel37 event id register + addressOffset: 320 + size: 32 + fields: + - name: CH37_EVT_ID + description: ch37_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH37_TASK_ID + description: channel37 task id register + addressOffset: 324 + size: 32 + fields: + - name: CH37_TASK_ID + description: ch37_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH38_EVT_ID + description: channel38 event id register + addressOffset: 328 + size: 32 + fields: + - name: CH38_EVT_ID + description: ch38_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH38_TASK_ID + description: channel38 task id register + addressOffset: 332 + size: 32 + fields: + - name: CH38_TASK_ID + description: ch38_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH39_EVT_ID + description: channel39 event id register + addressOffset: 336 + size: 32 + fields: + - name: CH39_EVT_ID + description: ch39_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH39_TASK_ID + description: channel39 task id register + addressOffset: 340 + size: 32 + fields: + - name: CH39_TASK_ID + description: ch39_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH40_EVT_ID + description: channel40 event id register + addressOffset: 344 + size: 32 + fields: + - name: CH40_EVT_ID + description: ch40_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH40_TASK_ID + description: channel40 task id register + addressOffset: 348 + size: 32 + fields: + - name: CH40_TASK_ID + description: ch40_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH41_EVT_ID + description: channel41 event id register + addressOffset: 352 + size: 32 + fields: + - name: CH41_EVT_ID + description: ch41_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH41_TASK_ID + description: channel41 task id register + addressOffset: 356 + size: 32 + fields: + - name: CH41_TASK_ID + description: ch41_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH42_EVT_ID + description: channel42 event id register + addressOffset: 360 + size: 32 + fields: + - name: CH42_EVT_ID + description: ch42_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH42_TASK_ID + description: channel42 task id register + addressOffset: 364 + size: 32 + fields: + - name: CH42_TASK_ID + description: ch42_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH43_EVT_ID + description: channel43 event id register + addressOffset: 368 + size: 32 + fields: + - name: CH43_EVT_ID + description: ch43_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH43_TASK_ID + description: channel43 task id register + addressOffset: 372 + size: 32 + fields: + - name: CH43_TASK_ID + description: ch43_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH44_EVT_ID + description: channel44 event id register + addressOffset: 376 + size: 32 + fields: + - name: CH44_EVT_ID + description: ch44_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH44_TASK_ID + description: channel44 task id register + addressOffset: 380 + size: 32 + fields: + - name: CH44_TASK_ID + description: ch44_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH45_EVT_ID + description: channel45 event id register + addressOffset: 384 + size: 32 + fields: + - name: CH45_EVT_ID + description: ch45_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH45_TASK_ID + description: channel45 task id register + addressOffset: 388 + size: 32 + fields: + - name: CH45_TASK_ID + description: ch45_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH46_EVT_ID + description: channel46 event id register + addressOffset: 392 + size: 32 + fields: + - name: CH46_EVT_ID + description: ch46_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH46_TASK_ID + description: channel46 task id register + addressOffset: 396 + size: 32 + fields: + - name: CH46_TASK_ID + description: ch46_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH47_EVT_ID + description: channel47 event id register + addressOffset: 400 + size: 32 + fields: + - name: CH47_EVT_ID + description: ch47_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH47_TASK_ID + description: channel47 task id register + addressOffset: 404 + size: 32 + fields: + - name: CH47_TASK_ID + description: ch47_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH48_EVT_ID + description: channel48 event id register + addressOffset: 408 + size: 32 + fields: + - name: CH48_EVT_ID + description: ch48_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH48_TASK_ID + description: channel48 task id register + addressOffset: 412 + size: 32 + fields: + - name: CH48_TASK_ID + description: ch48_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH49_EVT_ID + description: channel49 event id register + addressOffset: 416 + size: 32 + fields: + - name: CH49_EVT_ID + description: ch49_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH49_TASK_ID + description: channel49 task id register + addressOffset: 420 + size: 32 + fields: + - name: CH49_TASK_ID + description: ch49_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CLK_EN + description: etm clock enable register + addressOffset: 424 + size: 32 + fields: + - name: CLK_EN + description: clock enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: etm date register + addressOffset: 428 + size: 32 + resetValue: 35664018 + fields: + - name: DATE + description: date + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SPI0 + description: SPI (Serial Peripheral Interface) Controller 0 + groupName: SPI0 + baseAddress: 1610620928 + addressBlock: + - offset: 0 + size: 312 + usage: registers + registers: + - register: + name: SPI_MEM_CMD + description: SPI0 FSM status register + addressOffset: 0 + size: 32 + fields: + - name: SPI_MEM_MST_ST + description: "The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state." + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: SPI_MEM_SLV_ST + description: "The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state." + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: SPI_MEM_USR + description: "SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 18 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_CTRL + description: SPI0 control register. + addressOffset: 8 + size: 32 + resetValue: 2150375436 + fields: + - name: SPI_MEM_WDUMMY_DQS_ALWAYS_OUT + description: "In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_MEM_WDUMMY_ALWAYS_OUT + description: "In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDUMMY_RIN + description: "In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDUMMY_WOUT + description: "In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDOUT_OCT + description: "Apply 8 signals during write-data phase 1:enable 0: disable" + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SPI_MEM_FDIN_OCT + description: "Apply 8 signals during read-data phase 1:enable 0: disable" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SPI_MEM_FADDR_OCT + description: "Apply 8 signals during address phase 1:enable 0: disable" + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SPI_MEM_FCMD_QUAD + description: "Apply 4 signals during command phase 1:enable 0: disable" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FCMD_OCT + description: "Apply 8 signals during command phase 1:enable 0: disable" + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SPI_MEM_FASTRD_MODE + description: "This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FREAD_DUAL + description: "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SPI_MEM_Q_POL + description: "The bit is used to set MISO line polarity, 1: high 0, low" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SPI_MEM_D_POL + description: "The bit is used to set MOSI line polarity, 1: high 0, low" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FREAD_QUAD + description: "In the read operations read-data phase apply 4 signals. 1: enable 0: disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WP + description: "Write protect signal output when SPI is idle. 1: output high, 0: output low." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FREAD_DIO + description: "In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FREAD_QIO + description: "In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DQS_IE_ALWAYS_ON + description: "When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others." + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: SPI_MEM_DATA_IE_ALWAYS_ON + description: "When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_CTRL1 + description: SPI0 control1 register. + addressOffset: 12 + size: 32 + resetValue: 685768704 + fields: + - name: SPI_MEM_CLK_MODE + description: "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SPI_AR_SIZE0_1_SUPPORT_EN + description: "1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_AW_SIZE0_1_SUPPORT_EN + description: "1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SPI_AXI_RDATA_BACK_FAST + description: "1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available." + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: SPI_MEM_RRESP_ECC_ERR_EN + description: "1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AR_SPLICE_EN + description: Set this bit to enable AXI Read Splice-transfer. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: SPI_MEM_AW_SPLICE_EN + description: Set this bit to enable AXI Write Splice-transfer. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: SPI_MEM_RAM0_EN + description: "When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be accessed at the same time." + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: SPI_MEM_DUAL_RAM_EN + description: "Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time." + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SPI_MEM_FAST_WRITE_EN + description: "Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in tx_bus_fifo_l2." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SPI_MEM_RXFIFO_RST + description: The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI. Set this bit to reset these FIFO. + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: SPI_MEM_TXFIFO_RST + description: The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_CTRL2 + description: SPI0 control2 register. + addressOffset: 16 + size: 32 + resetValue: 11297 + fields: + - name: SPI_MEM_CS_SETUP_TIME + description: "(cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit." + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: SPI_MEM_CS_HOLD_TIME + description: "SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit." + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: SPI_MEM_ECC_CS_HOLD_TIME + description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash. + bitOffset: 10 + bitWidth: 3 + access: read-only + - name: SPI_MEM_ECC_SKIP_PAGE_CORNER + description: "1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash." + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SPI_MEM_ECC_16TO18_BYTE_EN + description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SPLIT_TRANS_EN + description: "Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not." + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: SPI_MEM_CS_HOLD_DELAY + description: "These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles." + bitOffset: 25 + bitWidth: 6 + access: read-write + - name: SPI_MEM_SYNC_RESET + description: The spi0_mst_st and spi0_slv_st will be reset. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_CLOCK + description: SPI clock division control register. + addressOffset: 20 + size: 32 + resetValue: 196867 + fields: + - name: SPI_MEM_CLKCNT_L + description: In the master mode it must be equal to spi_mem_clkcnt_N. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SPI_MEM_CLKCNT_H + description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SPI_MEM_CLKCNT_N + description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SPI_MEM_CLK_EQU_SYSCLK + description: "1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_USER + description: SPI0 user register. + addressOffset: 24 + size: 32 + fields: + - name: SPI_MEM_CS_HOLD + description: "spi cs keep low when spi is in done phase. 1: enable 0: disable." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CS_SETUP + description: "spi cs is enable when spi is in prepare phase. 1: enable 0: disable." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CK_OUT_EDGE + description: The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_DUMMY_IDLE + description: spi clock is disable in dummy phase when the bit is enable. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_DUMMY + description: This bit enable the dummy phase of an operation. + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_USER1 + description: SPI0 user1 register. + addressOffset: 28 + size: 32 + resetValue: 1543503943 + fields: + - name: SPI_MEM_USR_DUMMY_CYCLELEN + description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: SPI_MEM_USR_DBYTELEN + description: SPI0 USR_CMD read or write data byte length -1 + bitOffset: 6 + bitWidth: 3 + access: read-only + - name: SPI_MEM_USR_ADDR_BITLEN + description: The length in bits of address phase. The register value shall be (bit_num-1). + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: SPI_MEM_USER2 + description: SPI0 user2 register. + addressOffset: 32 + size: 32 + resetValue: 1879048192 + fields: + - name: SPI_MEM_USR_COMMAND_VALUE + description: The value of command. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SPI_MEM_USR_COMMAND_BITLEN + description: The length in bits of command phase. The register value shall be (bit_num-1) + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: SPI_MEM_RD_STATUS + description: SPI0 read control register. + addressOffset: 44 + size: 32 + fields: + - name: SPI_MEM_WB_MODE + description: Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: SPI_MEM_MISC + description: SPI0 misc register + addressOffset: 52 + size: 32 + fields: + - name: SPI_MEM_FSUB_PIN + description: "For SPI0, flash is connected to SUBPINs." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SSUB_PIN + description: "For SPI0, sram is connected to SUBPINs." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SPI_MEM_CK_IDLE_EDGE + description: "1: SPI_CLK line is high when idle 0: spi clk line is low when idle" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CS_KEEP_ACTIVE + description: SPI_CS line keep low when the bit is set. + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_CACHE_FCTRL + description: SPI0 bit mode control register. + addressOffset: 60 + size: 32 + resetValue: 3221225472 + fields: + - name: SPI_MEM_AXI_REQ_EN + description: "For SPI0, AXI master access enable, 1: enable, 0:disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CACHE_USR_ADDR_4BYTE + description: "For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CACHE_FLASH_USR_CMD + description: "For SPI0, cache read flash for user define command, 1: enable, 0:disable." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDIN_DUAL + description: "For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDOUT_DUAL + description: "For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FADDR_DUAL + description: "For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDIN_QUAD + description: "For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDOUT_QUAD + description: "For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FADDR_QUAD + description: "For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SPI_SAME_AW_AR_ADDR_CHK_EN + description: Set this bit to check AXI read/write the same address region. + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: SPI_CLOSE_AXI_INF_EN + description: "Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_CACHE_SCTRL + description: SPI0 external RAM control register + addressOffset: 64 + size: 32 + resetValue: 5619824 + fields: + - name: SPI_MEM_CACHE_USR_SADDR_4BYTE + description: "For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_MEM_USR_SRAM_DIO + description: "For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable" + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SPI_MEM_USR_SRAM_QIO + description: "For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable" + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SPI_MEM_USR_WR_SRAM_DUMMY + description: "For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SPI_MEM_USR_RD_SRAM_DUMMY + description: "For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SPI_MEM_CACHE_SRAM_USR_RCMD + description: "For SPI0, In the external RAM mode cache read external RAM for user define command." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SRAM_RDUMMY_CYCLELEN + description: "For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1)." + bitOffset: 6 + bitWidth: 6 + access: read-only + - name: SPI_MEM_SRAM_ADDR_BITLEN + description: "For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1)." + bitOffset: 14 + bitWidth: 6 + access: read-only + - name: SPI_MEM_CACHE_SRAM_USR_WCMD + description: "For SPI0, In the external RAM mode cache write sram for user define command" + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SRAM_OCT + description: reserved + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SRAM_WDUMMY_CYCLELEN + description: "For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1)." + bitOffset: 22 + bitWidth: 6 + access: read-only + - register: + name: SPI_MEM_SRAM_CMD + description: SPI0 external RAM mode control register + addressOffset: 68 + size: 32 + resetValue: 3225419776 + fields: + - name: SPI_MEM_SCLK_MODE + description: "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on." + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: SPI_MEM_SWB_MODE + description: Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit. + bitOffset: 2 + bitWidth: 8 + access: read-only + - name: SPI_MEM_SDIN_DUAL + description: "For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio." + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SDOUT_DUAL + description: "For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio." + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SADDR_DUAL + description: "For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio." + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SDIN_QUAD + description: "For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio." + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SDOUT_QUAD + description: "For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio." + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SADDR_QUAD + description: "For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio." + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SCMD_QUAD + description: "For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio." + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SDIN_OCT + description: "For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable." + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SDOUT_OCT + description: "For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable." + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SADDR_OCT + description: "For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable." + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SCMD_OCT + description: "For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable." + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SDUMMY_RIN + description: "In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SDUMMY_WOUT + description: "In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller." + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT + description: "In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller." + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_WDUMMY_ALWAYS_OUT + description: "In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller." + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_DQS_IE_ALWAYS_ON + description: "When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others." + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_DATA_IE_ALWAYS_ON + description: "When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_SRAM_DRD_CMD + description: SPI0 external RAM DDR read command control register + addressOffset: 72 + size: 32 + fields: + - name: SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE + description: "For SPI0,When cache mode is enable it is the read command value of command phase for sram." + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN + description: "For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1)." + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: SPI_MEM_SRAM_DWR_CMD + description: SPI0 external RAM DDR write command control register + addressOffset: 76 + size: 32 + fields: + - name: SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE + description: "For SPI0,When cache mode is enable it is the write command value of command phase for sram." + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN + description: "For SPI0,When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1)." + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: SPI_MEM_SRAM_CLK + description: SPI0 external RAM clock control register + addressOffset: 80 + size: 32 + resetValue: 196867 + fields: + - name: SPI_MEM_SCLKCNT_L + description: "For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N." + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: SPI_MEM_SCLKCNT_H + description: "For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1)." + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: SPI_MEM_SCLKCNT_N + description: "For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)" + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: SPI_MEM_SCLK_EQU_SYSCLK + description: "For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_FSM + description: SPI0 FSM status register + addressOffset: 84 + size: 32 + resetValue: 512 + fields: + - name: SPI_MEM_LOCK_DELAY_TIME + description: "The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1." + bitOffset: 7 + bitWidth: 5 + access: read-write + - register: + name: SPI_MEM_INT_ENA + description: SPI0 interrupt enable register + addressOffset: 192 + size: 32 + fields: + - name: SPI_MEM_SLV_ST_END_INT_ENA + description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_MST_ST_END_INT_ENA + description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_ECC_ERR_INT_ENA + description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SPI_MEM_PMS_REJECT_INT_ENA + description: The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AXI_RADDR_ERR_INT_ENA + description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA + description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SPI_MEM_AXI_WADDR_ERR_INT__ENA + description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_INT_CLR + description: SPI0 interrupt clear register + addressOffset: 196 + size: 32 + fields: + - name: SPI_MEM_SLV_ST_END_INT_CLR + description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SPI_MEM_MST_ST_END_INT_CLR + description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SPI_MEM_ECC_ERR_INT_CLR + description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SPI_MEM_PMS_REJECT_INT_CLR + description: The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: SPI_MEM_AXI_RADDR_ERR_INT_CLR + description: The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR + description: The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SPI_MEM_AXI_WADDR_ERR_INT_CLR + description: The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_INT_RAW + description: SPI0 interrupt raw register + addressOffset: 200 + size: 32 + fields: + - name: SPI_MEM_SLV_ST_END_INT_RAW + description: "The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_MST_ST_END_INT_RAW + description: "The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_ECC_ERR_INT_RAW + description: "The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SPI_MEM_PMS_REJECT_INT_RAW + description: "The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AXI_RADDR_ERR_INT_RAW + description: "The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW + description: "The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SPI_MEM_AXI_WADDR_ERR_INT_RAW + description: "The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others." + bitOffset: 9 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_INT_ST + description: SPI0 interrupt status register + addressOffset: 204 + size: 32 + fields: + - name: SPI_MEM_SLV_ST_END_INT_ST + description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SPI_MEM_MST_ST_END_INT_ST + description: The status bit for SPI_MEM_MST_ST_END_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SPI_MEM_ECC_ERR_INT_ST + description: The status bit for SPI_MEM_ECC_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SPI_MEM_PMS_REJECT_INT_ST + description: The status bit for SPI_MEM_PMS_REJECT_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SPI_MEM_AXI_RADDR_ERR_INT_ST + description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SPI_MEM_AXI_WR_FLASH_ERR_INT_ST + description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SPI_MEM_AXI_WADDR_ERR_INT_ST + description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_DDR + description: SPI0 flash DDR mode control register + addressOffset: 212 + size: 32 + resetValue: 12320 + fields: + - name: SPI_FMEM_DDR_EN + description: "1: in DDR mode, 0 in SDR mode" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_VAR_DUMMY + description: Set the bit to enable variable dummy cycle in spi DDR mode. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_DDR_RDAT_SWP + description: Set the bit to reorder rx data of the word in spi DDR mode. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_DDR_WDAT_SWP + description: Set the bit to reorder tx data of the word in spi DDR mode. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_DDR_CMD_DIS + description: the bit is used to disable dual edge in command phase when DDR mode. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_OUTMINBYTELEN + description: It is the minimum output data length in the panda device. + bitOffset: 5 + bitWidth: 7 + access: read-only + - name: SPI_FMEM_TX_DDR_MSK_EN + description: "Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash." + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_RX_DDR_MSK_EN + description: "Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash." + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_USR_DDR_DQS_THD + description: The delay number of data strobe which from memory based on SPI clock. + bitOffset: 14 + bitWidth: 7 + access: read-only + - name: SPI_FMEM_DDR_DQS_LOOP + description: "1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS." + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_CLK_DIFF_EN + description: "Set this bit to enable the differential SPI_CLK#." + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_DQS_CA_IN + description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_HYPERBUS_DUMMY_2X + description: "Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram." + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_CLK_DIFF_INV + description: Set this bit to invert SPI_DIFF when accesses to flash. . + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_OCTA_RAM_ADDR + description: "Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}." + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_HYPERBUS_CA + description: "Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}." + bitOffset: 30 + bitWidth: 1 + access: read-only + - register: + name: SPI_SMEM_DDR + description: SPI0 external RAM DDR mode control register + addressOffset: 216 + size: 32 + resetValue: 12320 + fields: + - name: EN + description: "1: in DDR mode, 0 in SDR mode" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_VAR_DUMMY + description: Set the bit to enable variable dummy cycle in spi DDR mode. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RDAT_SWP + description: Set the bit to reorder rx data of the word in spi DDR mode. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: WDAT_SWP + description: Set the bit to reorder tx data of the word in spi DDR mode. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: CMD_DIS + description: the bit is used to disable dual edge in command phase when DDR mode. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_OUTMINBYTELEN + description: It is the minimum output data length in the DDR psram. + bitOffset: 5 + bitWidth: 7 + access: read-only + - name: SPI_SMEM_TX_DDR_MSK_EN + description: "Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM." + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_RX_DDR_MSK_EN + description: "Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM." + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_USR_DDR_DQS_THD + description: The delay number of data strobe which from memory based on SPI clock. + bitOffset: 14 + bitWidth: 7 + access: read-only + - name: DQS_LOOP + description: "1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS." + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_CLK_DIFF_EN + description: "Set this bit to enable the differential SPI_CLK#." + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_DQS_CA_IN + description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_HYPERBUS_DUMMY_2X + description: "Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram." + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_CLK_DIFF_INV + description: Set this bit to invert SPI_DIFF when accesses to external RAM. . + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_OCTA_RAM_ADDR + description: "Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}." + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_HYPERBUS_CA + description: "Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}." + bitOffset: 30 + bitWidth: 1 + access: read-only + - register: + dim: 4 + dimIncrement: 4 + name: SPI_FMEM_PMS%s_ATTR + description: MSPI flash ACE section %s attribute register + addressOffset: 256 + size: 32 + resetValue: 3 + fields: + - name: SPI_FMEM_PMS_RD_ATTR + description: "1: SPI1 flash ACE section %s read accessible. 0: Not allowed." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_PMS_WR_ATTR + description: "1: SPI1 flash ACE section %s write accessible. 0: Not allowed." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_PMS_ECC + description: "SPI1 flash ACE section %s ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section %s is configured by registers SPI_FMEM_PMS%s_ADDR_REG and SPI_FMEM_PMS%s_SIZE_REG." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: SPI_FMEM_PMS%s_ADDR + description: SPI1 flash ACE section %s start address register + addressOffset: 272 + size: 32 + fields: + - name: S + description: SPI1 flash ACE section %s start address value + bitOffset: 0 + bitWidth: 26 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: SPI_FMEM_PMS%s_SIZE + description: SPI1 flash ACE section %s start address register + addressOffset: 288 + size: 32 + resetValue: 4096 + fields: + - name: SPI_FMEM_PMS_SIZE + description: "SPI1 flash ACE section %s address region is (SPI_FMEM_PMS%s_ADDR_S, SPI_FMEM_PMS%s_ADDR_S + SPI_FMEM_PMS%s_SIZE)" + bitOffset: 0 + bitWidth: 14 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: SPI_SMEM_PMS%s_ATTR + description: SPI1 flash ACE section %s start address register + addressOffset: 304 + size: 32 + resetValue: 3 + fields: + - name: SPI_SMEM_PMS_RD_ATTR + description: "1: SPI1 external RAM ACE section %s read accessible. 0: Not allowed." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_PMS_WR_ATTR + description: "1: SPI1 external RAM ACE section %s write accessible. 0: Not allowed." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_PMS_ECC + description: "SPI1 external RAM ACE section %s ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section %s is configured by registers SPI_SMEM_PMS%s_ADDR_REG and SPI_SMEM_PMS%s_SIZE_REG." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: SPI_SMEM_PMS%s_ADDR + description: SPI1 external RAM ACE section %s start address register + addressOffset: 320 + size: 32 + fields: + - name: S + description: SPI1 external RAM ACE section %s start address value + bitOffset: 0 + bitWidth: 26 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: SPI_SMEM_PMS%s_SIZE + description: SPI1 external RAM ACE section %s start address register + addressOffset: 336 + size: 32 + resetValue: 4096 + fields: + - name: SPI_SMEM_PMS_SIZE + description: "SPI1 external RAM ACE section %s address region is (SPI_SMEM_PMS%s_ADDR_S, SPI_SMEM_PMS%s_ADDR_S + SPI_SMEM_PMS%s_SIZE)" + bitOffset: 0 + bitWidth: 14 + access: read-write + - register: + name: SPI_MEM_PMS_REJECT + description: SPI1 access reject register + addressOffset: 356 + size: 32 + fields: + - name: SPI_MEM_REJECT_ADDR + description: This bits show the first SPI1 access error address. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + bitOffset: 0 + bitWidth: 26 + access: read-only + - name: SPI_MEM_PM_EN + description: Set this bit to enable SPI0/1 transfer permission control function. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI_MEM_PMS_LD + description: "1: SPI1 write access error. 0: No write access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set." + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SPI_MEM_PMS_ST + description: "1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set." + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: SPI_MEM_PMS_MULTI_HIT + description: "1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set." + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: SPI_MEM_PMS_IVD + description: "1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_ECC_CTRL + description: MSPI ECC control register + addressOffset: 360 + size: 32 + resetValue: 16797696 + fields: + - name: SPI_FMEM_ECC_ERR_INT_NUM + description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. + bitOffset: 11 + bitWidth: 6 + access: read-only + - name: SPI_FMEM_ECC_ERR_INT_EN + description: Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_PAGE_SIZE + description: "Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes." + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: SPI_FMEM_ECC_ADDR_EN + description: "Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1." + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SPI_MEM_USR_ECC_ADDR_EN + description: Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN + description: "1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information." + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: SPI_MEM_ECC_ERR_BITS + description: "Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7)" + bitOffset: 25 + bitWidth: 7 + access: read-only + - register: + name: SPI_MEM_ECC_ERR_ADDR + description: MSPI ECC error address register + addressOffset: 364 + size: 32 + fields: + - name: SPI_MEM_ECC_ERR_ADDR + description: This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + bitOffset: 0 + bitWidth: 26 + access: read-only + - name: SPI_MEM_ECC_ERR_CNT + description: This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + bitOffset: 26 + bitWidth: 6 + access: read-only + - register: + name: SPI_MEM_AXI_ERR_ADDR + description: SPI0 AXI request error address. + addressOffset: 368 + size: 32 + resetValue: 4227858432 + fields: + - name: SPI_MEM_AXI_ERR_ADDR + description: "This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set." + bitOffset: 0 + bitWidth: 26 + access: read-only + - name: SPI_MEM_ALL_FIFO_EMPTY + description: "The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others." + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: SPI_RDATA_AFIFO_REMPTY + description: "1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending." + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: SPI_RADDR_AFIFO_REMPTY + description: "1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending." + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SPI_WDATA_AFIFO_REMPTY + description: "1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending." + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: SPI_WBLEN_AFIFO_REMPTY + description: "1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending." + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: SPI_ALL_AXI_TRANS_AFIFO_EMPTY + description: "This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: SPI_SMEM_ECC_CTRL + description: MSPI ECC control register + addressOffset: 372 + size: 32 + resetValue: 524288 + fields: + - name: SPI_SMEM_ECC_ERR_INT_EN + description: Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_PAGE_SIZE + description: "Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes." + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: SPI_SMEM_ECC_ADDR_EN + description: "Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1." + bitOffset: 20 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_TIMING_CALI + description: SPI0 flash timing calibration register + addressOffset: 384 + size: 32 + resetValue: 1 + fields: + - name: SPI_MEM_TIMING_CLK_ENA + description: The bit is used to enable timing adjust clock for all reading operations. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_TIMING_CALI + description: The bit is used to enable timing auto-calibration for all reading operations. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_EXTRA_DUMMY_CYCLELEN + description: add extra dummy spi clock cycle length for spi clock calibration. + bitOffset: 2 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DLL_TIMING_CALI + description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: UPDATE + description: "Set this bit to update delay mode, delay num and extra dummy in MSPI." + bitOffset: 6 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_DIN_MODE + description: MSPI flash input timing delay mode control register + addressOffset: 388 + size: 32 + fields: + - name: SPI_MEM_DIN0_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DIN1_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DIN2_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DIN3_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DIN4_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk" + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DIN5_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk" + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DIN6_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk" + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DIN7_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk" + bitOffset: 21 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DINS_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk" + bitOffset: 24 + bitWidth: 3 + access: read-write + - register: + name: SPI_MEM_DIN_NUM + description: MSPI flash input timing delay number control register + addressOffset: 392 + size: 32 + fields: + - name: SPI_MEM_DIN0_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SPI_MEM_DIN1_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: SPI_MEM_DIN2_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: SPI_MEM_DIN3_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: SPI_MEM_DIN4_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: SPI_MEM_DIN5_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: SPI_MEM_DIN6_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: SPI_MEM_DIN7_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: SPI_MEM_DINS_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: SPI_MEM_DOUT_MODE + description: MSPI flash output timing adjustment control register + addressOffset: 396 + size: 32 + fields: + - name: SPI_MEM_DOUT0_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DOUT1_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DOUT2_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DOUT3_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DOUT4_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DOUT5_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DOUT6_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DOUT7_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DOUTS_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk" + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: SPI_SMEM_TIMING_CALI + description: MSPI external RAM timing calibration register + addressOffset: 400 + size: 32 + resetValue: 1 + fields: + - name: SPI_SMEM_TIMING_CLK_ENA + description: "For sram, the bit is used to enable timing adjust clock for all reading operations." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_TIMING_CALI + description: "For sram, the bit is used to enable timing auto-calibration for all reading operations." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_EXTRA_DUMMY_CYCLELEN + description: "For sram, add extra dummy spi clock cycle length for spi clock calibration." + bitOffset: 2 + bitWidth: 3 + access: read-only + - name: SPI_SMEM_DLL_TIMING_CALI + description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM. + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: SPI_SMEM_DIN_MODE + description: MSPI external RAM input timing delay mode control register + addressOffset: 404 + size: 32 + fields: + - name: SPI_SMEM_DIN0_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: SPI_SMEM_DIN1_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 3 + bitWidth: 3 + access: read-only + - name: SPI_SMEM_DIN2_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 6 + bitWidth: 3 + access: read-only + - name: SPI_SMEM_DIN3_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 9 + bitWidth: 3 + access: read-only + - name: SPI_SMEM_DIN4_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 12 + bitWidth: 3 + access: read-only + - name: SPI_SMEM_DIN5_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 15 + bitWidth: 3 + access: read-only + - name: SPI_SMEM_DIN6_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 18 + bitWidth: 3 + access: read-only + - name: SPI_SMEM_DIN7_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 21 + bitWidth: 3 + access: read-only + - name: SPI_SMEM_DINS_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 24 + bitWidth: 3 + access: read-only + - register: + name: SPI_SMEM_DIN_NUM + description: MSPI external RAM input timing delay number control register + addressOffset: 408 + size: 32 + fields: + - name: SPI_SMEM_DIN0_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: SPI_SMEM_DIN1_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 2 + bitWidth: 2 + access: read-only + - name: SPI_SMEM_DIN2_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 4 + bitWidth: 2 + access: read-only + - name: SPI_SMEM_DIN3_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: SPI_SMEM_DIN4_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 8 + bitWidth: 2 + access: read-only + - name: SPI_SMEM_DIN5_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 10 + bitWidth: 2 + access: read-only + - name: SPI_SMEM_DIN6_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 12 + bitWidth: 2 + access: read-only + - name: SPI_SMEM_DIN7_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 14 + bitWidth: 2 + access: read-only + - name: SPI_SMEM_DINS_NUM + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 16 + bitWidth: 2 + access: read-only + - register: + name: SPI_SMEM_DOUT_MODE + description: MSPI external RAM output timing adjustment control register + addressOffset: 412 + size: 32 + fields: + - name: SPI_SMEM_DOUT0_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_DOUT1_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_DOUT2_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_DOUT3_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_DOUT4_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_DOUT5_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_DOUT6_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_DOUT7_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_DOUTS_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: SPI_SMEM_AC + description: MSPI external RAM ECC and SPI CS timing control register + addressOffset: 416 + size: 32 + resetValue: 2147528836 + fields: + - name: SPI_SMEM_CS_SETUP + description: "For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_CS_HOLD + description: "For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_CS_SETUP_TIME + description: "For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit." + bitOffset: 2 + bitWidth: 5 + access: read-only + - name: SPI_SMEM_CS_HOLD_TIME + description: "For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit." + bitOffset: 7 + bitWidth: 5 + access: read-only + - name: SPI_SMEM_ECC_CS_HOLD_TIME + description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM. + bitOffset: 12 + bitWidth: 3 + access: read-only + - name: SPI_SMEM_ECC_SKIP_PAGE_CORNER + description: "1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM." + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_ECC_16TO18_BYTE_EN + description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_CS_HOLD_DELAY + description: "These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles." + bitOffset: 25 + bitWidth: 6 + access: read-only + - name: SPI_SMEM_SPLIT_TRANS_EN + description: "Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_CLOCK_GATE + description: SPI0 clock gate register + addressOffset: 512 + size: 32 + resetValue: 1 + fields: + - name: SPI_CLK_EN + description: "Register clock gate enable signal. 1: Enable. 0: Disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_XTS_PLAIN_BASE + description: The base address of the memory that stores plaintext in Manual Encryption + addressOffset: 768 + size: 32 + fields: + - name: SPI_XTS_PLAIN + description: This field is only used to generate include file in c case. This field is useless. Please do not use this field. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_XTS_LINESIZE + description: Manual Encryption Line-Size register + addressOffset: 832 + size: 32 + fields: + - name: SPI_XTS_LINESIZE + description: "This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved." + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SPI_MEM_XTS_DESTINATION + description: Manual Encryption destination register + addressOffset: 836 + size: 32 + fields: + - name: SPI_XTS_DESTINATION + description: "This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_XTS_PHYSICAL_ADDRESS + description: Manual Encryption physical address register + addressOffset: 840 + size: 32 + fields: + - name: SPI_XTS_PHYSICAL_ADDRESS + description: This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter. + bitOffset: 0 + bitWidth: 26 + access: read-write + - register: + name: SPI_MEM_XTS_TRIGGER + description: Manual Encryption physical address register + addressOffset: 844 + size: 32 + fields: + - name: SPI_XTS_TRIGGER + description: "Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2." + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_XTS_RELEASE + description: Manual Encryption physical address register + addressOffset: 848 + size: 32 + fields: + - name: SPI_XTS_RELEASE + description: "Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3." + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_XTS_DESTROY + description: Manual Encryption physical address register + addressOffset: 852 + size: 32 + fields: + - name: SPI_XTS_DESTROY + description: "Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0." + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_XTS_STATE + description: Manual Encryption physical address register + addressOffset: 856 + size: 32 + fields: + - name: SPI_XTS_STATE + description: "This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi." + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: SPI_MEM_XTS_DATE + description: Manual Encryption version register + addressOffset: 860 + size: 32 + resetValue: 538972176 + fields: + - name: SPI_XTS_DATE + description: This bits stores the last modified-time of manual encryption feature. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: SPI_MEM_MMU_ITEM_CONTENT + description: MSPI-MMU item content register + addressOffset: 892 + size: 32 + resetValue: 892 + fields: + - name: SPI_MMU_ITEM_CONTENT + description: MSPI-MMU item content + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_MMU_ITEM_INDEX + description: MSPI-MMU item index register + addressOffset: 896 + size: 32 + fields: + - name: SPI_MMU_ITEM_INDEX + description: MSPI-MMU item index + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_MMU_POWER_CTRL + description: MSPI MMU power control register + addressOffset: 900 + size: 32 + resetValue: 320864260 + fields: + - name: SPI_MMU_MEM_FORCE_ON + description: Set this bit to enable mmu-memory clock force on + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MMU_MEM_FORCE_PD + description: Set this bit to force mmu-memory powerdown + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MMU_MEM_FORCE_PU + description: "Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MMU_PAGE_SIZE + description: "0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8" + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: SPI_MEM_AUX_CTRL + description: MMU PSRAM aux control register + bitOffset: 16 + bitWidth: 14 + access: read-only + - name: SPI_MEM_RDN_ENA + description: ECO register enable bit + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: SPI_MEM_RDN_RESULT + description: MSPI module clock domain and AXI clock domain ECO register result register + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_DPA_CTRL + description: SPI memory cryption DPA register + addressOffset: 904 + size: 32 + resetValue: 15 + fields: + - name: SPI_CRYPT_SECURITY_LEVEL + description: "Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SPI_CRYPT_CALC_D_DPA_EN + description: "Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_CRYPT_DPA_SELECT_REGISTER + description: "1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits." + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_REGISTERRND_ECO_HIGH + description: MSPI ECO high register + addressOffset: 1008 + size: 32 + resetValue: 892 + fields: + - name: SPI_MEM_REGISTERRND_ECO_HIGH + description: ECO high register + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SPI_MEM_REGISTERRND_ECO_LOW + description: MSPI ECO low register + addressOffset: 1012 + size: 32 + resetValue: 892 + fields: + - name: SPI_MEM_REGISTERRND_ECO_LOW + description: ECO low register + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SPI_MEM_DATE + description: SPI0 version control register + addressOffset: 1020 + size: 32 + resetValue: 35663920 + fields: + - name: SPI_MEM_DATE + description: SPI0 register version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SPI1 + description: SPI (Serial Peripheral Interface) Controller 1 + groupName: SPI1 + baseAddress: 1610625024 + addressBlock: + - offset: 0 + size: 172 + usage: registers + registers: + - register: + name: SPI_MEM_CMD + description: SPI1 memory command register + addressOffset: 0 + size: 32 + fields: + - name: SPI_MEM_MST_ST + description: The current status of SPI1 master FSM. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: SPI_MEM_SLV_ST + description: "The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state." + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: SPI_MEM_FLASH_PE + description: "In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR + description: "User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_HPM + description: "Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_RES + description: "This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_DP + description: "Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_CE + description: "Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_BE + description: "Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_SE + description: "Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PP + description: "Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_WRSR + description: "Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_RDSR + description: "Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_RDID + description: "Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_WRDI + description: "Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_WREN + description: "Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_READ + description: "Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_ADDR + description: SPI1 address register + addressOffset: 4 + size: 32 + fields: + - name: SPI_MEM_USR_ADDR_VALUE + description: "In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_CTRL + description: SPI1 control register. + addressOffset: 8 + size: 32 + resetValue: 2924556 + fields: + - name: SPI_MEM_FDUMMY_RIN + description: "In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDUMMY_WOUT + description: "In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDOUT_OCT + description: "Apply 8 signals during write-data phase 1:enable 0: disable" + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SPI_MEM_FDIN_OCT + description: "Apply 8 signals during read-data phase 1:enable 0: disable" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SPI_MEM_FADDR_OCT + description: "Apply 8 signals during address phase 1:enable 0: disable" + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SPI_MEM_FCMD_QUAD + description: "Apply 4 signals during command phase 1:enable 0: disable" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FCMD_OCT + description: "Apply 8 signals during command phase 1:enable 0: disable" + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SPI_MEM_FCS_CRC_EN + description: "For SPI1, initialize crc32 module before writing encrypted data to flash. Active low." + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SPI_MEM_TX_CRC_EN + description: "For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable" + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: SPI_MEM_FASTRD_MODE + description: "This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FREAD_DUAL + description: "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SPI_MEM_RESANDRES + description: "The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI_MEM_Q_POL + description: "The bit is used to set MISO line polarity, 1: high 0, low" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SPI_MEM_D_POL + description: "The bit is used to set MOSI line polarity, 1: high 0, low" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FREAD_QUAD + description: "In the read operations read-data phase apply 4 signals. 1: enable 0: disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WP + description: "Write protect signal output when SPI is idle. 1: output high, 0: output low." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WRSR_2B + description: "two bytes data will be written to status register when it is set. 1: enable 0: disable." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FREAD_DIO + description: "In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FREAD_QIO + description: "In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_CTRL1 + description: SPI1 control1 register. + addressOffset: 12 + size: 32 + resetValue: 4092 + fields: + - name: SPI_MEM_CLK_MODE + description: "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SPI_MEM_CS_HOLD_DLY_RES + description: "After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles." + bitOffset: 2 + bitWidth: 10 + access: read-write + - register: + name: SPI_MEM_CTRL2 + description: SPI1 control2 register. + addressOffset: 16 + size: 32 + fields: + - name: SPI_MEM_SYNC_RESET + description: The FSM will be reset. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_CLOCK + description: SPI1 clock division control register. + addressOffset: 20 + size: 32 + resetValue: 196867 + fields: + - name: SPI_MEM_CLKCNT_L + description: In the master mode it must be equal to spi_mem_clkcnt_N. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SPI_MEM_CLKCNT_H + description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SPI_MEM_CLKCNT_N + description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SPI_MEM_CLK_EQU_SYSCLK + description: reserved + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_USER + description: SPI1 user register. + addressOffset: 24 + size: 32 + resetValue: 2147483648 + fields: + - name: SPI_MEM_CK_OUT_EDGE + description: the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FWRITE_DUAL + description: In the write operations read-data phase apply 2 signals + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FWRITE_QUAD + description: In the write operations read-data phase apply 4 signals + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FWRITE_DIO + description: In the write operations address phase and read-data phase apply 2 signals. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FWRITE_QIO + description: In the write operations address phase and read-data phase apply 4 signals. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_MISO_HIGHPART + description: "read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: SPI_MEM_USR_MOSI_HIGHPART + description: "write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable." + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: SPI_MEM_USR_DUMMY_IDLE + description: SPI clock is disable in dummy phase when the bit is enable. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_MOSI + description: This bit enable the write-data phase of an operation. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_MISO + description: This bit enable the read-data phase of an operation. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_DUMMY + description: This bit enable the dummy phase of an operation. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_ADDR + description: This bit enable the address phase of an operation. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_COMMAND + description: This bit enable the command phase of an operation. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_USER1 + description: SPI1 user1 register. + addressOffset: 28 + size: 32 + resetValue: 1543503879 + fields: + - name: SPI_MEM_USR_DUMMY_CYCLELEN + description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: SPI_MEM_USR_ADDR_BITLEN + description: The length in bits of address phase. The register value shall be (bit_num-1). + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: SPI_MEM_USER2 + description: SPI1 user2 register. + addressOffset: 32 + size: 32 + resetValue: 1879048192 + fields: + - name: SPI_MEM_USR_COMMAND_VALUE + description: The value of command. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SPI_MEM_USR_COMMAND_BITLEN + description: The length in bits of command phase. The register value shall be (bit_num-1) + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: SPI_MEM_MOSI_DLEN + description: SPI1 send data bit length control register. + addressOffset: 36 + size: 32 + fields: + - name: SPI_MEM_USR_MOSI_DBITLEN + description: The length in bits of write-data. The register value shall be (bit_num-1). + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: SPI_MEM_MISO_DLEN + description: SPI1 receive data bit length control register. + addressOffset: 40 + size: 32 + fields: + - name: SPI_MEM_USR_MISO_DBITLEN + description: The length in bits of read-data. The register value shall be (bit_num-1). + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: SPI_MEM_RD_STATUS + description: SPI1 status register. + addressOffset: 44 + size: 32 + fields: + - name: SPI_MEM_STATUS + description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SPI_MEM_WB_MODE + description: Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: SPI_MEM_MISC + description: SPI1 misc register + addressOffset: 52 + size: 32 + resetValue: 2 + fields: + - name: SPI_MEM_CS0_DIS + description: "SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CS1_DIS + description: "SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CK_IDLE_EDGE + description: "1: spi clk line is high when idle 0: spi clk line is low when idle" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CS_KEEP_ACTIVE + description: spi cs line keep low when the bit is set. + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_TX_CRC + description: SPI1 TX CRC data register. + addressOffset: 56 + size: 32 + resetValue: 4294967295 + fields: + - name: DATA + description: "For SPI1, the value of crc32." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SPI_MEM_CACHE_FCTRL + description: SPI1 bit mode control register. + addressOffset: 60 + size: 32 + fields: + - name: SPI_MEM_CACHE_USR_ADDR_4BYTE + description: "For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDIN_DUAL + description: "For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDOUT_DUAL + description: "For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FADDR_DUAL + description: "For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDIN_QUAD + description: "For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDOUT_QUAD + description: "For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FADDR_QUAD + description: "For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_W0 + description: SPI1 memory data buffer0 + addressOffset: 88 + size: 32 + fields: + - name: SPI_MEM_BUF0 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W1 + description: SPI1 memory data buffer1 + addressOffset: 92 + size: 32 + fields: + - name: SPI_MEM_BUF1 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W2 + description: SPI1 memory data buffer2 + addressOffset: 96 + size: 32 + fields: + - name: SPI_MEM_BUF2 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W3 + description: SPI1 memory data buffer3 + addressOffset: 100 + size: 32 + fields: + - name: SPI_MEM_BUF3 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W4 + description: SPI1 memory data buffer4 + addressOffset: 104 + size: 32 + fields: + - name: SPI_MEM_BUF4 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W5 + description: SPI1 memory data buffer5 + addressOffset: 108 + size: 32 + fields: + - name: SPI_MEM_BUF5 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W6 + description: SPI1 memory data buffer6 + addressOffset: 112 + size: 32 + fields: + - name: SPI_MEM_BUF6 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W7 + description: SPI1 memory data buffer7 + addressOffset: 116 + size: 32 + fields: + - name: SPI_MEM_BUF7 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W8 + description: SPI1 memory data buffer8 + addressOffset: 120 + size: 32 + fields: + - name: SPI_MEM_BUF8 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W9 + description: SPI1 memory data buffer9 + addressOffset: 124 + size: 32 + fields: + - name: SPI_MEM_BUF9 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W10 + description: SPI1 memory data buffer10 + addressOffset: 128 + size: 32 + fields: + - name: SPI_MEM_BUF10 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W11 + description: SPI1 memory data buffer11 + addressOffset: 132 + size: 32 + fields: + - name: SPI_MEM_BUF11 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W12 + description: SPI1 memory data buffer12 + addressOffset: 136 + size: 32 + fields: + - name: SPI_MEM_BUF12 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W13 + description: SPI1 memory data buffer13 + addressOffset: 140 + size: 32 + fields: + - name: SPI_MEM_BUF13 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W14 + description: SPI1 memory data buffer14 + addressOffset: 144 + size: 32 + fields: + - name: SPI_MEM_BUF14 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W15 + description: SPI1 memory data buffer15 + addressOffset: 148 + size: 32 + fields: + - name: SPI_MEM_BUF15 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_FLASH_WAITI_CTRL + description: SPI1 wait idle control register + addressOffset: 152 + size: 32 + resetValue: 327681 + fields: + - name: SPI_MEM_WAITI_EN + description: "1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WAITI_DUMMY + description: The dummy phase enable when wait flash idle (RDSR) + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WAITI_ADDR_EN + description: "1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WAITI_ADDR_CYCLELEN + description: "When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared." + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: SPI_MEM_WAITI_CMD_2B + description: "1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WAITI_DUMMY_CYCLELEN + description: The dummy cycle length when wait flash idle(RDSR). + bitOffset: 10 + bitWidth: 6 + access: read-write + - name: SPI_MEM_WAITI_CMD + description: The command value to wait flash idle(RDSR). + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SPI_MEM_FLASH_SUS_CTRL + description: SPI1 flash suspend control register + addressOffset: 156 + size: 32 + resetValue: 134225920 + fields: + - name: SPI_MEM_FLASH_PER + description: "program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PES + description: "program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PER_WAIT_EN + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PES_WAIT_EN + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_PES_PER_EN + description: "Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PES_EN + description: Set this bit to enable Auto-suspending function. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_MEM_PESR_END_MSK + description: "The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]." + bitOffset: 6 + bitWidth: 16 + access: read-write + - name: SPI_FMEM_RD_SUS_2B + description: "1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SPI_MEM_PER_END_EN + description: "1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SPI_MEM_PES_END_EN + description: "1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SUS_TIMEOUT_CNT + description: "When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass." + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: SPI_MEM_FLASH_SUS_CMD + description: SPI1 flash suspend command register + addressOffset: 160 + size: 32 + resetValue: 357749 + fields: + - name: SPI_MEM_FLASH_PES_COMMAND + description: Program/Erase suspend command. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SPI_MEM_WAIT_PESR_COMMAND + description: Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SPI_MEM_SUS_STATUS + description: SPI1 flash suspend status register + addressOffset: 164 + size: 32 + resetValue: 2054815744 + fields: + - name: SPI_MEM_FLASH_SUS + description: "The status of flash suspend, only used in SPI1." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WAIT_PESR_CMD_2B + description: "1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_HPM_DLY_128 + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_RES_DLY_128 + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_DP_DLY_128 + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PER_DLY_128 + description: "Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PES_DLY_128 + description: "Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SPI0_LOCK_EN + description: "1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PESR_CMD_2B + description: "1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PER_COMMAND + description: Program/Erase resume command. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SPI_MEM_INT_ENA + description: SPI1 interrupt enable register + addressOffset: 192 + size: 32 + fields: + - name: SPI_MEM_PER_END_INT_ENA + description: The enable bit for SPI_MEM_PER_END_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_PES_END_INT_ENA + description: The enable bit for SPI_MEM_PES_END_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WPE_END_INT_ENA + description: The enable bit for SPI_MEM_WPE_END_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SLV_ST_END_INT_ENA + description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_MST_ST_END_INT_ENA + description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_BROWN_OUT_INT_ENA + description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_INT_CLR + description: SPI1 interrupt clear register + addressOffset: 196 + size: 32 + fields: + - name: SPI_MEM_PER_END_INT_CLR + description: The clear bit for SPI_MEM_PER_END_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SPI_MEM_PES_END_INT_CLR + description: The clear bit for SPI_MEM_PES_END_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SPI_MEM_WPE_END_INT_CLR + description: The clear bit for SPI_MEM_WPE_END_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SPI_MEM_SLV_ST_END_INT_CLR + description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SPI_MEM_MST_ST_END_INT_CLR + description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SPI_MEM_BROWN_OUT_INT_CLR + description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_INT_RAW + description: SPI1 interrupt raw register + addressOffset: 200 + size: 32 + fields: + - name: SPI_MEM_PER_END_INT_RAW + description: "The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_PES_END_INT_RAW + description: "The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WPE_END_INT_RAW + description: "The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SLV_ST_END_INT_RAW + description: "The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_MST_ST_END_INT_RAW + description: "The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_BROWN_OUT_INT_RAW + description: "The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others." + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_INT_ST + description: SPI1 interrupt status register + addressOffset: 204 + size: 32 + fields: + - name: SPI_MEM_PER_END_INT_ST + description: The status bit for SPI_MEM_PER_END_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_MEM_PES_END_INT_ST + description: The status bit for SPI_MEM_PES_END_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SPI_MEM_WPE_END_INT_ST + description: The status bit for SPI_MEM_WPE_END_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SLV_ST_END_INT_ST + description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SPI_MEM_MST_ST_END_INT_ST + description: The status bit for SPI_MEM_MST_ST_END_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SPI_MEM_BROWN_OUT_INT_ST + description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_DDR + description: SPI1 DDR control register + addressOffset: 212 + size: 32 + resetValue: 32 + fields: + - name: SPI_FMEM_DDR_EN + description: "1: in ddr mode, 0 in sdr mode" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_VAR_DUMMY + description: Set the bit to enable variable dummy cycle in spi ddr mode. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_DDR_RDAT_SWP + description: Set the bit to reorder rx data of the word in spi ddr mode. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_DDR_WDAT_SWP + description: Set the bit to reorder tx data of the word in spi ddr mode. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_DDR_CMD_DIS + description: the bit is used to disable dual edge in command phase when ddr mode. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_OUTMINBYTELEN + description: It is the minimum output data length in the panda device. + bitOffset: 5 + bitWidth: 7 + access: read-only + - name: SPI_FMEM_USR_DDR_DQS_THD + description: The delay number of data strobe which from memory based on SPI clock. + bitOffset: 14 + bitWidth: 7 + access: read-only + - name: SPI_FMEM_DDR_DQS_LOOP + description: "1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS." + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_CLK_DIFF_EN + description: "Set this bit to enable the differential SPI_CLK#." + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_DQS_CA_IN + description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_HYPERBUS_DUMMY_2X + description: "Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram." + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_CLK_DIFF_INV + description: Set this bit to invert SPI_DIFF when accesses to flash. . + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_OCTA_RAM_ADDR + description: "Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}." + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_HYPERBUS_CA + description: "Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}." + bitOffset: 30 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_TIMING_CALI + description: SPI1 timing control register + addressOffset: 384 + size: 32 + fields: + - name: SPI_MEM_TIMING_CALI + description: The bit is used to enable timing auto-calibration for all reading operations. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_EXTRA_DUMMY_CYCLELEN + description: add extra dummy spi clock cycle length for spi clock calibration. + bitOffset: 2 + bitWidth: 3 + access: read-write + - register: + name: SPI_MEM_CLOCK_GATE + description: SPI1 clk_gate register + addressOffset: 512 + size: 32 + resetValue: 1 + fields: + - name: SPI_MEM_CLK_EN + description: "Register clock gate enable signal. 1: Enable. 0: Disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_DATE + description: Version control register + addressOffset: 1020 + size: 32 + resetValue: 35660128 + fields: + - name: SPI_MEM_DATE + description: Version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SPI2 + description: SPI (Serial Peripheral Interface) Controller 2 + groupName: SPI2 + baseAddress: 1611141120 + addressBlock: + - offset: 0 + size: 152 + usage: registers + interrupt: + - name: MSPI + value: 40 + - name: SPI2 + value: 72 + registers: + - register: + name: CMD + description: Command control register + addressOffset: 0 + size: 32 + fields: + - name: CONF_BITLEN + description: Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 18 + access: read-write + - name: UPDATE + description: "Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: USR + description: "User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf." + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: ADDR + description: Address value register + addressOffset: 4 + size: 32 + fields: + - name: USR_ADDR_VALUE + description: Address to slave. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CTRL + description: SPI control register + addressOffset: 8 + size: 32 + resetValue: 3932160 + fields: + - name: DUMMY_OUT + description: "0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FADDR_DUAL + description: "Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FADDR_QUAD + description: "Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FADDR_OCT + description: "Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: FCMD_DUAL + description: "Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FCMD_QUAD + description: "Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FCMD_OCT + description: "Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: FREAD_DUAL + description: "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: FREAD_QUAD + description: "In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: FREAD_OCT + description: "In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: Q_POL + description: "The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: D_POL + description: "The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: HOLD_POL + description: "SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: WP_POL + description: "Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: RD_BIT_ORDER + description: "In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state." + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: WR_BIT_ORDER + description: "In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state." + bitOffset: 25 + bitWidth: 2 + access: read-write + - register: + name: CLOCK + description: SPI clock control register + addressOffset: 12 + size: 32 + resetValue: 2147496003 + fields: + - name: CLKCNT_L + description: In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: CLKCNT_H + description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: CLKCNT_N + description: In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + bitOffset: 12 + bitWidth: 6 + access: read-write + - name: CLKDIV_PRE + description: In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + bitOffset: 18 + bitWidth: 4 + access: read-write + - name: CLK_EQU_SYSCLK + description: "In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USER + description: SPI USER control register + addressOffset: 16 + size: 32 + resetValue: 2147483840 + fields: + - name: DOUTDIN + description: "Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: QPI_MODE + description: "Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OPI_MODE + description: "Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TSCK_I_EDGE + description: "In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CS_HOLD + description: "spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CS_SETUP + description: "spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RSCK_I_EDGE + description: "In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CK_OUT_EDGE + description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FWRITE_DUAL + description: In the write operations read-data phase apply 2 signals. Can be configured in CONF state. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FWRITE_QUAD + description: In the write operations read-data phase apply 4 signals. Can be configured in CONF state. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FWRITE_OCT + description: In the write operations read-data phase apply 8 signals. Can be configured in CONF state. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: USR_CONF_NXT + description: "1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SIO + description: "Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: USR_MISO_HIGHPART + description: "read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: USR_MOSI_HIGHPART + description: "write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: USR_DUMMY_IDLE + description: spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: USR_MOSI + description: This bit enable the write-data phase of an operation. Can be configured in CONF state. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: USR_MISO + description: This bit enable the read-data phase of an operation. Can be configured in CONF state. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: USR_DUMMY + description: This bit enable the dummy phase of an operation. Can be configured in CONF state. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: USR_ADDR + description: This bit enable the address phase of an operation. Can be configured in CONF state. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: USR_COMMAND + description: This bit enable the command phase of an operation. Can be configured in CONF state. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USER1 + description: SPI USER control register 1 + addressOffset: 20 + size: 32 + resetValue: 3091267591 + fields: + - name: USR_DUMMY_CYCLELEN + description: The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: MST_WFULL_ERR_END_EN + description: "1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CS_SETUP_TIME + description: (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. + bitOffset: 17 + bitWidth: 5 + access: read-write + - name: CS_HOLD_TIME + description: delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. + bitOffset: 22 + bitWidth: 5 + access: read-write + - name: USR_ADDR_BITLEN + description: The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: USER2 + description: SPI USER control register 2 + addressOffset: 24 + size: 32 + resetValue: 2013265920 + fields: + - name: USR_COMMAND_VALUE + description: The value of command. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MST_REMPTY_ERR_END_EN + description: "1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: USR_COMMAND_BITLEN + description: The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: MS_DLEN + description: SPI data bit length control register + addressOffset: 28 + size: 32 + fields: + - name: MS_DATA_BITLEN + description: The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 0 + bitWidth: 18 + access: read-write + - register: + name: MISC + description: SPI misc register + addressOffset: 32 + size: 32 + resetValue: 62 + fields: + - name: CS0_DIS + description: "SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CS1_DIS + description: "SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CS2_DIS + description: "SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CS3_DIS + description: "SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CS4_DIS + description: "SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CS5_DIS + description: "SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CK_DIS + description: "1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: MASTER_CS_POL + description: "In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: CLK_DATA_DTR_EN + description: "1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19." + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: DATA_DTR_EN + description: "1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state." + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: ADDR_DTR_EN + description: "1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state." + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: CMD_DTR_EN + description: "1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state." + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: SLAVE_CS_POL + description: "spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: DQS_IDLE_EDGE + description: The default value of spi_dqs. Can be configured in CONF state. + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: CK_IDLE_EDGE + description: "1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CS_KEEP_ACTIVE + description: spi cs line keep low when the bit is set. Can be configured in CONF state. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: QUAD_DIN_PIN_SWAP + description: "1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DIN_MODE + description: SPI input delay mode configuration + addressOffset: 36 + size: 32 + fields: + - name: DIN0_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DIN1_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DIN2_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DIN3_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DIN4_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 8 + bitWidth: 2 + access: read-only + - name: DIN5_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 10 + bitWidth: 2 + access: read-only + - name: DIN6_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 12 + bitWidth: 2 + access: read-only + - name: DIN7_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 14 + bitWidth: 2 + access: read-only + - name: TIMING_HCLK_ACTIVE + description: "1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state." + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: DIN_NUM + description: SPI input delay number configuration + addressOffset: 40 + size: 32 + fields: + - name: DIN0_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DIN1_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DIN2_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DIN3_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DIN4_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 8 + bitWidth: 2 + access: read-only + - name: DIN5_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 10 + bitWidth: 2 + access: read-only + - name: DIN6_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 12 + bitWidth: 2 + access: read-only + - name: DIN7_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 14 + bitWidth: 2 + access: read-only + - register: + name: DOUT_MODE + description: SPI output delay mode configuration + addressOffset: 44 + size: 32 + fields: + - name: DOUT0_MODE + description: "The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DOUT1_MODE + description: "The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DOUT2_MODE + description: "The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DOUT3_MODE + description: "The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DOUT4_MODE + description: "The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DOUT5_MODE + description: "The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: DOUT6_MODE + description: "The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: DOUT7_MODE + description: "The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: D_DQS_MODE + description: "The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: DMA_CONF + description: SPI DMA control register + addressOffset: 48 + size: 32 + resetValue: 3 + fields: + - name: DMA_OUTFIFO_EMPTY + description: "Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DMA_INFIFO_FULL + description: "Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: DMA_SLV_SEG_TRANS_EN + description: "Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SLV_RX_SEG_TRANS_CLR_EN + description: "1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SLV_TX_SEG_TRANS_CLR_EN + description: "1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: RX_EOF_EN + description: "1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: DMA_RX_ENA + description: Set this bit to enable SPI DMA controlled receive data mode. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: DMA_TX_ENA + description: Set this bit to enable SPI DMA controlled send data mode. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: RX_AFIFO_RST + description: "Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer." + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: BUF_AFIFO_RST + description: "Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer." + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: DMA_AFIFO_RST + description: "Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer." + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: DMA_INT_ENA + description: SPI interrupt enable register + addressOffset: 52 + size: 32 + fields: + - name: DMA_INFIFO_FULL_ERR_INT_ENA + description: The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DMA_OUTFIFO_EMPTY_ERR_INT_ENA + description: The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SLV_EX_QPI_INT_ENA + description: The enable bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLV_EN_QPI_INT_ENA + description: The enable bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLV_CMD7_INT_ENA + description: The enable bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SLV_CMD8_INT_ENA + description: The enable bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SLV_CMD9_INT_ENA + description: The enable bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SLV_CMDA_INT_ENA + description: The enable bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SLV_RD_DMA_DONE_INT_ENA + description: The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLV_WR_DMA_DONE_INT_ENA + description: The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLV_RD_BUF_DONE_INT_ENA + description: The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLV_WR_BUF_DONE_INT_ENA + description: The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TRANS_DONE_INT_ENA + description: The enable bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DMA_SEG_TRANS_DONE_INT_ENA + description: The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SEG_MAGIC_ERR_INT_ENA + description: The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLV_BUF_ADDR_ERR_INT_ENA + description: The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLV_CMD_ERR_INT_ENA + description: The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: MST_RX_AFIFO_WFULL_ERR_INT_ENA + description: The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MST_TX_AFIFO_REMPTY_ERR_INT_ENA + description: The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: APP2_INT_ENA + description: The enable bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: APP1_INT_ENA + description: The enable bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: DMA_INT_CLR + description: SPI interrupt clear register + addressOffset: 56 + size: 32 + fields: + - name: DMA_INFIFO_FULL_ERR_INT_CLR + description: The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: DMA_OUTFIFO_EMPTY_ERR_INT_CLR + description: The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SLV_EX_QPI_INT_CLR + description: The clear bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SLV_EN_QPI_INT_CLR + description: The clear bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SLV_CMD7_INT_CLR + description: The clear bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SLV_CMD8_INT_CLR + description: The clear bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: SLV_CMD9_INT_CLR + description: The clear bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: SLV_CMDA_INT_CLR + description: The clear bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SLV_RD_DMA_DONE_INT_CLR + description: The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SLV_WR_DMA_DONE_INT_CLR + description: The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SLV_RD_BUF_DONE_INT_CLR + description: The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SLV_WR_BUF_DONE_INT_CLR + description: The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TRANS_DONE_INT_CLR + description: The clear bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: DMA_SEG_TRANS_DONE_INT_CLR + description: The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SEG_MAGIC_ERR_INT_CLR + description: The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SLV_BUF_ADDR_ERR_INT_CLR + description: The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: SLV_CMD_ERR_INT_CLR + description: The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: MST_RX_AFIFO_WFULL_ERR_INT_CLR + description: The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: MST_TX_AFIFO_REMPTY_ERR_INT_CLR + description: The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: APP2_INT_CLR + description: The clear bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: APP1_INT_CLR + description: The clear bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: write-only + - register: + name: DMA_INT_RAW + description: SPI interrupt raw register + addressOffset: 60 + size: 32 + fields: + - name: DMA_INFIFO_FULL_ERR_INT_RAW + description: "1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DMA_OUTFIFO_EMPTY_ERR_INT_RAW + description: "1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SLV_EX_QPI_INT_RAW + description: "The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLV_EN_QPI_INT_RAW + description: "The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLV_CMD7_INT_RAW + description: "The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SLV_CMD8_INT_RAW + description: "The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SLV_CMD9_INT_RAW + description: "The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SLV_CMDA_INT_RAW + description: "The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SLV_RD_DMA_DONE_INT_RAW + description: "The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLV_WR_DMA_DONE_INT_RAW + description: "The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLV_RD_BUF_DONE_INT_RAW + description: "The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLV_WR_BUF_DONE_INT_RAW + description: "The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TRANS_DONE_INT_RAW + description: "The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DMA_SEG_TRANS_DONE_INT_RAW + description: "The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SEG_MAGIC_ERR_INT_RAW + description: "The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLV_BUF_ADDR_ERR_INT_RAW + description: "The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLV_CMD_ERR_INT_RAW + description: "The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: MST_RX_AFIFO_WFULL_ERR_INT_RAW + description: "The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MST_TX_AFIFO_REMPTY_ERR_INT_RAW + description: "The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: APP2_INT_RAW + description: The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: APP1_INT_RAW + description: The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: DMA_INT_ST + description: SPI interrupt status register + addressOffset: 64 + size: 32 + fields: + - name: DMA_INFIFO_FULL_ERR_INT_ST + description: The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DMA_OUTFIFO_EMPTY_ERR_INT_ST + description: The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SLV_EX_QPI_INT_ST + description: The status bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SLV_EN_QPI_INT_ST + description: The status bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SLV_CMD7_INT_ST + description: The status bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SLV_CMD8_INT_ST + description: The status bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SLV_CMD9_INT_ST + description: The status bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SLV_CMDA_INT_ST + description: The status bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SLV_RD_DMA_DONE_INT_ST + description: The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SLV_WR_DMA_DONE_INT_ST + description: The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SLV_RD_BUF_DONE_INT_ST + description: The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SLV_WR_BUF_DONE_INT_ST + description: The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TRANS_DONE_INT_ST + description: The status bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: DMA_SEG_TRANS_DONE_INT_ST + description: The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SEG_MAGIC_ERR_INT_ST + description: The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SLV_BUF_ADDR_ERR_INT_ST + description: The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLV_CMD_ERR_INT_ST + description: The status bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: MST_RX_AFIFO_WFULL_ERR_INT_ST + description: The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: MST_TX_AFIFO_REMPTY_ERR_INT_ST + description: The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: APP2_INT_ST + description: The status bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: APP1_INT_ST + description: The status bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: read-only + - register: + name: DMA_INT_SET + description: SPI interrupt software set register + addressOffset: 68 + size: 32 + fields: + - name: DMA_INFIFO_FULL_ERR_INT_SET + description: The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: DMA_OUTFIFO_EMPTY_ERR_INT_SET + description: The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SLV_EX_QPI_INT_SET + description: The software set bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SLV_EN_QPI_INT_SET + description: The software set bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SLV_CMD7_INT_SET + description: The software set bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SLV_CMD8_INT_SET + description: The software set bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: SLV_CMD9_INT_SET + description: The software set bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: SLV_CMDA_INT_SET + description: The software set bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SLV_RD_DMA_DONE_INT_SET + description: The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SLV_WR_DMA_DONE_INT_SET + description: The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SLV_RD_BUF_DONE_INT_SET + description: The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SLV_WR_BUF_DONE_INT_SET + description: The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TRANS_DONE_INT_SET + description: The software set bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: DMA_SEG_TRANS_DONE_INT_SET + description: The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SEG_MAGIC_ERR_INT_SET + description: The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SLV_BUF_ADDR_ERR_INT_SET + description: The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: SLV_CMD_ERR_INT_SET + description: The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: MST_RX_AFIFO_WFULL_ERR_INT_SET + description: The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: MST_TX_AFIFO_REMPTY_ERR_INT_SET + description: The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: APP2_INT_SET + description: The software set bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: APP1_INT_SET + description: The software set bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: write-only + - register: + name: W0 + description: SPI CPU-controlled buffer0 + addressOffset: 152 + size: 32 + fields: + - name: BUF0 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W1 + description: SPI CPU-controlled buffer1 + addressOffset: 156 + size: 32 + fields: + - name: BUF1 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W2 + description: SPI CPU-controlled buffer2 + addressOffset: 160 + size: 32 + fields: + - name: BUF2 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W3 + description: SPI CPU-controlled buffer3 + addressOffset: 164 + size: 32 + fields: + - name: BUF3 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W4 + description: SPI CPU-controlled buffer4 + addressOffset: 168 + size: 32 + fields: + - name: BUF4 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W5 + description: SPI CPU-controlled buffer5 + addressOffset: 172 + size: 32 + fields: + - name: BUF5 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W6 + description: SPI CPU-controlled buffer6 + addressOffset: 176 + size: 32 + fields: + - name: BUF6 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W7 + description: SPI CPU-controlled buffer7 + addressOffset: 180 + size: 32 + fields: + - name: BUF7 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W8 + description: SPI CPU-controlled buffer8 + addressOffset: 184 + size: 32 + fields: + - name: BUF8 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W9 + description: SPI CPU-controlled buffer9 + addressOffset: 188 + size: 32 + fields: + - name: BUF9 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W10 + description: SPI CPU-controlled buffer10 + addressOffset: 192 + size: 32 + fields: + - name: BUF10 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W11 + description: SPI CPU-controlled buffer11 + addressOffset: 196 + size: 32 + fields: + - name: BUF11 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W12 + description: SPI CPU-controlled buffer12 + addressOffset: 200 + size: 32 + fields: + - name: BUF12 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W13 + description: SPI CPU-controlled buffer13 + addressOffset: 204 + size: 32 + fields: + - name: BUF13 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W14 + description: SPI CPU-controlled buffer14 + addressOffset: 208 + size: 32 + fields: + - name: BUF14 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W15 + description: SPI CPU-controlled buffer15 + addressOffset: 212 + size: 32 + fields: + - name: BUF15 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SLAVE + description: SPI slave control register + addressOffset: 224 + size: 32 + resetValue: 41943040 + fields: + - name: CLK_MODE + description: "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CLK_MODE_13 + description: "{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RSCK_DATA_OUT + description: "It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLV_RDDMA_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLV_WRDMA_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLV_RDBUF_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLV_WRBUF_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DMA_SEG_MAGIC_VALUE + description: The magic value of BM table in master DMA seg-trans. + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: MODE + description: "Set SPI work mode. 1: slave mode 0: master mode." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SOFT_RESET + description: "Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state." + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: USR_CONF + description: "1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: MST_FD_WAIT_DMA_TX_DATA + description: "In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer." + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: SLAVE1 + description: SPI slave control register 1 + addressOffset: 228 + size: 32 + fields: + - name: SLV_DATA_BITLEN + description: The transferred data bit length in SPI slave FD and HD mode. + bitOffset: 0 + bitWidth: 18 + access: read-write + - name: SLV_LAST_COMMAND + description: In the slave mode it is the value of command. + bitOffset: 18 + bitWidth: 8 + access: read-write + - name: SLV_LAST_ADDR + description: In the slave mode it is the value of address. + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: CLK_GATE + description: SPI module clock and register clock control + addressOffset: 232 + size: 32 + fields: + - name: CLK_EN + description: Set this bit to enable clk gate + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MST_CLK_ACTIVE + description: Set this bit to power on the SPI module clock. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MST_CLK_SEL + description: "This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control + addressOffset: 240 + size: 32 + resetValue: 35656448 + fields: + - name: DATE + description: SPI register version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SYSTIMER + description: System Timer + groupName: SYSTIMER + baseAddress: 1610653696 + addressBlock: + - offset: 0 + size: 144 + usage: registers + interrupt: + - name: SYSTIMER_TARGET0 + value: 57 + - name: SYSTIMER_TARGET1 + value: 58 + - name: SYSTIMER_TARGET2 + value: 59 + registers: + - register: + name: CONF + description: Configure system timer clock + addressOffset: 0 + size: 32 + resetValue: 1174405120 + fields: + - name: SYSTIMER_CLK_FO + description: systimer clock force on + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_EN + description: "enable systimer's etm task and event" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TARGET2_WORK_EN + description: target2 work enable + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TARGET1_WORK_EN + description: target1 work enable + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TARGET0_WORK_EN + description: target0 work enable + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT1_CORE1_STALL_EN + description: If timer unit1 is stalled when core1 stalled + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT1_CORE0_STALL_EN + description: If timer unit1 is stalled when core0 stalled + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT0_CORE1_STALL_EN + description: If timer unit0 is stalled when core1 stalled + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT0_CORE0_STALL_EN + description: If timer unit0 is stalled when core0 stalled + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT1_WORK_EN + description: timer unit1 work enable + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT0_WORK_EN + description: timer unit0 work enable + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: register file clk gating + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: UNIT0_OP + description: system timer unit0 value update register + addressOffset: 4 + size: 32 + fields: + - name: TIMER_UNIT0_VALUE_VALID + description: timer value is sync and valid + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: TIMER_UNIT0_UPDATE + description: update timer_unit0 + bitOffset: 30 + bitWidth: 1 + access: write-only + - register: + name: UNIT1_OP + description: system timer unit1 value update register + addressOffset: 8 + size: 32 + fields: + - name: TIMER_UNIT1_VALUE_VALID + description: timer value is sync and valid + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: TIMER_UNIT1_UPDATE + description: update timer unit1 + bitOffset: 30 + bitWidth: 1 + access: write-only + - register: + name: UNIT0_LOAD_HI + description: system timer unit0 value high load register + addressOffset: 12 + size: 32 + fields: + - name: TIMER_UNIT0_LOAD_HI + description: timer unit0 load high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: UNIT0_LOAD_LO + description: system timer unit0 value low load register + addressOffset: 16 + size: 32 + fields: + - name: TIMER_UNIT0_LOAD_LO + description: timer unit0 load low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: UNIT1_LOAD_HI + description: system timer unit1 value high load register + addressOffset: 20 + size: 32 + fields: + - name: TIMER_UNIT1_LOAD_HI + description: timer unit1 load high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: UNIT1_LOAD_LO + description: system timer unit1 value low load register + addressOffset: 24 + size: 32 + fields: + - name: TIMER_UNIT1_LOAD_LO + description: timer unit1 load low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET0_HI + description: system timer comp0 value high register + addressOffset: 28 + size: 32 + fields: + - name: TIMER_TARGET0_HI + description: timer taget0 high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: TARGET0_LO + description: system timer comp0 value low register + addressOffset: 32 + size: 32 + fields: + - name: TIMER_TARGET0_LO + description: timer taget0 low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET1_HI + description: system timer comp1 value high register + addressOffset: 36 + size: 32 + fields: + - name: TIMER_TARGET1_HI + description: timer taget1 high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: TARGET1_LO + description: system timer comp1 value low register + addressOffset: 40 + size: 32 + fields: + - name: TIMER_TARGET1_LO + description: timer taget1 low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET2_HI + description: system timer comp2 value high register + addressOffset: 44 + size: 32 + fields: + - name: TIMER_TARGET2_HI + description: timer taget2 high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: TARGET2_LO + description: system timer comp2 value low register + addressOffset: 48 + size: 32 + fields: + - name: TIMER_TARGET2_LO + description: timer taget2 low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET0_CONF + description: system timer comp0 target mode register + addressOffset: 52 + size: 32 + fields: + - name: TARGET0_PERIOD + description: target0 period + bitOffset: 0 + bitWidth: 26 + access: read-write + - name: TARGET0_PERIOD_MODE + description: Set target0 to period mode + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TARGET0_TIMER_UNIT_SEL + description: select which unit to compare + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TARGET1_CONF + description: system timer comp1 target mode register + addressOffset: 56 + size: 32 + fields: + - name: TARGET1_PERIOD + description: target1 period + bitOffset: 0 + bitWidth: 26 + access: read-write + - name: TARGET1_PERIOD_MODE + description: Set target1 to period mode + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TARGET1_TIMER_UNIT_SEL + description: select which unit to compare + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TARGET2_CONF + description: system timer comp2 target mode register + addressOffset: 60 + size: 32 + fields: + - name: TARGET2_PERIOD + description: target2 period + bitOffset: 0 + bitWidth: 26 + access: read-write + - name: TARGET2_PERIOD_MODE + description: Set target2 to period mode + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TARGET2_TIMER_UNIT_SEL + description: select which unit to compare + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: UNIT0_VALUE_HI + description: system timer unit0 value high register + addressOffset: 64 + size: 32 + fields: + - name: TIMER_UNIT0_VALUE_HI + description: timer read value high 20bits + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: UNIT0_VALUE_LO + description: system timer unit0 value low register + addressOffset: 68 + size: 32 + fields: + - name: TIMER_UNIT0_VALUE_LO + description: timer read value low 32bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: UNIT1_VALUE_HI + description: system timer unit1 value high register + addressOffset: 72 + size: 32 + fields: + - name: TIMER_UNIT1_VALUE_HI + description: timer read value high 20bits + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: UNIT1_VALUE_LO + description: system timer unit1 value low register + addressOffset: 76 + size: 32 + fields: + - name: TIMER_UNIT1_VALUE_LO + description: timer read value low 32bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: COMP0_LOAD + description: system timer comp0 conf sync register + addressOffset: 80 + size: 32 + fields: + - name: TIMER_COMP0_LOAD + description: timer comp0 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: COMP1_LOAD + description: system timer comp1 conf sync register + addressOffset: 84 + size: 32 + fields: + - name: TIMER_COMP1_LOAD + description: timer comp1 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: COMP2_LOAD + description: system timer comp2 conf sync register + addressOffset: 88 + size: 32 + fields: + - name: TIMER_COMP2_LOAD + description: timer comp2 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: UNIT0_LOAD + description: system timer unit0 conf sync register + addressOffset: 92 + size: 32 + fields: + - name: TIMER_UNIT0_LOAD + description: timer unit0 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: UNIT1_LOAD + description: system timer unit1 conf sync register + addressOffset: 96 + size: 32 + fields: + - name: TIMER_UNIT1_LOAD + description: timer unit1 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + description: systimer interrupt enable register + addressOffset: 100 + size: 32 + fields: + - name: TARGET0_INT_ENA + description: interupt0 enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TARGET1_INT_ENA + description: interupt1 enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TARGET2_INT_ENA + description: interupt2 enable + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: systimer interrupt raw register + addressOffset: 104 + size: 32 + fields: + - name: TARGET0_INT_RAW + description: interupt0 raw + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TARGET1_INT_RAW + description: interupt1 raw + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TARGET2_INT_RAW + description: interupt2 raw + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: systimer interrupt clear register + addressOffset: 108 + size: 32 + fields: + - name: TARGET0_INT_CLR + description: interupt0 clear + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TARGET1_INT_CLR + description: interupt1 clear + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TARGET2_INT_CLR + description: interupt2 clear + bitOffset: 2 + bitWidth: 1 + access: write-only + - register: + name: INT_ST + description: systimer interrupt status register + addressOffset: 112 + size: 32 + fields: + - name: TARGET0_INT_ST + description: interupt0 status + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TARGET1_INT_ST + description: interupt1 status + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TARGET2_INT_ST + description: interupt2 status + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: REAL_TARGET0_LO + description: system timer comp0 actual target value low register + addressOffset: 116 + size: 32 + fields: + - name: TARGET0_LO_RO + description: actual target value value low 32bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: REAL_TARGET0_HI + description: system timer comp0 actual target value high register + addressOffset: 120 + size: 32 + fields: + - name: TARGET0_HI_RO + description: actual target value value high 20bits + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: REAL_TARGET1_LO + description: system timer comp1 actual target value low register + addressOffset: 124 + size: 32 + fields: + - name: TARGET1_LO_RO + description: actual target value value low 32bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: REAL_TARGET1_HI + description: system timer comp1 actual target value high register + addressOffset: 128 + size: 32 + fields: + - name: TARGET1_HI_RO + description: actual target value value high 20bits + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: REAL_TARGET2_LO + description: system timer comp2 actual target value low register + addressOffset: 132 + size: 32 + fields: + - name: TARGET2_LO_RO + description: actual target value value low 32bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: REAL_TARGET2_HI + description: system timer comp2 actual target value high register + addressOffset: 136 + size: 32 + fields: + - name: TARGET2_HI_RO + description: actual target value value high 20bits + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: DATE + description: system timer version control register + addressOffset: 252 + size: 32 + resetValue: 35655795 + fields: + - name: DATE + description: systimer register version + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: TEE + description: TEE Peripheral + groupName: TEE + baseAddress: 1611235328 + addressBlock: + - offset: 0 + size: 136 + usage: registers + registers: + - register: + name: M0_MODE_CTRL + description: Tee mode control register + addressOffset: 0 + size: 32 + fields: + - name: M0_MODE + description: "M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M1_MODE_CTRL + description: Tee mode control register + addressOffset: 4 + size: 32 + resetValue: 3 + fields: + - name: M1_MODE + description: "M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M2_MODE_CTRL + description: Tee mode control register + addressOffset: 8 + size: 32 + fields: + - name: M2_MODE + description: "M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M3_MODE_CTRL + description: Tee mode control register + addressOffset: 12 + size: 32 + resetValue: 3 + fields: + - name: M3_MODE + description: "M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M4_MODE_CTRL + description: Tee mode control register + addressOffset: 16 + size: 32 + resetValue: 3 + fields: + - name: M4_MODE + description: "M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M5_MODE_CTRL + description: Tee mode control register + addressOffset: 20 + size: 32 + resetValue: 3 + fields: + - name: M5_MODE + description: "M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M6_MODE_CTRL + description: Tee mode control register + addressOffset: 24 + size: 32 + resetValue: 3 + fields: + - name: M6_MODE + description: "M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M7_MODE_CTRL + description: Tee mode control register + addressOffset: 28 + size: 32 + resetValue: 3 + fields: + - name: M7_MODE + description: "M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M8_MODE_CTRL + description: Tee mode control register + addressOffset: 32 + size: 32 + resetValue: 3 + fields: + - name: M8_MODE + description: "M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M9_MODE_CTRL + description: Tee mode control register + addressOffset: 36 + size: 32 + resetValue: 3 + fields: + - name: M9_MODE + description: "M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M10_MODE_CTRL + description: Tee mode control register + addressOffset: 40 + size: 32 + resetValue: 3 + fields: + - name: M10_MODE + description: "M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M11_MODE_CTRL + description: Tee mode control register + addressOffset: 44 + size: 32 + resetValue: 3 + fields: + - name: M11_MODE + description: "M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M12_MODE_CTRL + description: Tee mode control register + addressOffset: 48 + size: 32 + resetValue: 3 + fields: + - name: M12_MODE + description: "M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M13_MODE_CTRL + description: Tee mode control register + addressOffset: 52 + size: 32 + resetValue: 3 + fields: + - name: M13_MODE + description: "M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M14_MODE_CTRL + description: Tee mode control register + addressOffset: 56 + size: 32 + resetValue: 3 + fields: + - name: M14_MODE + description: "M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M15_MODE_CTRL + description: Tee mode control register + addressOffset: 60 + size: 32 + resetValue: 3 + fields: + - name: M15_MODE + description: "M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M16_MODE_CTRL + description: Tee mode control register + addressOffset: 64 + size: 32 + resetValue: 3 + fields: + - name: M16_MODE + description: "M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M17_MODE_CTRL + description: Tee mode control register + addressOffset: 68 + size: 32 + resetValue: 3 + fields: + - name: M17_MODE + description: "M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M18_MODE_CTRL + description: Tee mode control register + addressOffset: 72 + size: 32 + resetValue: 3 + fields: + - name: M18_MODE + description: "M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M19_MODE_CTRL + description: Tee mode control register + addressOffset: 76 + size: 32 + resetValue: 3 + fields: + - name: M19_MODE + description: "M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M20_MODE_CTRL + description: Tee mode control register + addressOffset: 80 + size: 32 + resetValue: 3 + fields: + - name: M20_MODE + description: "M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M21_MODE_CTRL + description: Tee mode control register + addressOffset: 84 + size: 32 + resetValue: 3 + fields: + - name: M21_MODE + description: "M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M22_MODE_CTRL + description: Tee mode control register + addressOffset: 88 + size: 32 + resetValue: 3 + fields: + - name: M22_MODE + description: "M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M23_MODE_CTRL + description: Tee mode control register + addressOffset: 92 + size: 32 + resetValue: 3 + fields: + - name: M23_MODE + description: "M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M24_MODE_CTRL + description: Tee mode control register + addressOffset: 96 + size: 32 + resetValue: 3 + fields: + - name: M24_MODE + description: "M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M25_MODE_CTRL + description: Tee mode control register + addressOffset: 100 + size: 32 + resetValue: 3 + fields: + - name: M25_MODE + description: "M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M26_MODE_CTRL + description: Tee mode control register + addressOffset: 104 + size: 32 + resetValue: 3 + fields: + - name: M26_MODE + description: "M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M27_MODE_CTRL + description: Tee mode control register + addressOffset: 108 + size: 32 + resetValue: 3 + fields: + - name: M27_MODE + description: "M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M28_MODE_CTRL + description: Tee mode control register + addressOffset: 112 + size: 32 + resetValue: 3 + fields: + - name: M28_MODE + description: "M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M29_MODE_CTRL + description: Tee mode control register + addressOffset: 116 + size: 32 + resetValue: 3 + fields: + - name: M29_MODE + description: "M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M30_MODE_CTRL + description: Tee mode control register + addressOffset: 120 + size: 32 + resetValue: 3 + fields: + - name: M30_MODE + description: "M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M31_MODE_CTRL + description: Tee mode control register + addressOffset: 124 + size: 32 + resetValue: 3 + fields: + - name: M31_MODE + description: "M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: CLOCK_GATE + description: Clock gating register + addressOffset: 128 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: reg_clk_en + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version register + addressOffset: 4092 + size: 32 + resetValue: 35672706 + fields: + - name: DATE + description: reg_tee_date + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: TIMG0 + description: Timer Group 0 + groupName: TIMG + baseAddress: 1610645504 + addressBlock: + - offset: 0 + size: 104 + usage: registers + interrupt: + - name: TG0_T0_LEVEL + value: 51 + - name: TG0_T1_LEVEL + value: 52 + - name: TG0_WDT_LEVEL + value: 53 + registers: + - register: + name: T0CONFIG + description: Timer %s configuration register + addressOffset: 0 + size: 32 + resetValue: 1610620928 + fields: + - name: USE_XTAL + description: "1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: ALARM_EN + description: "When set, the alarm is enabled. This bit is automatically cleared once an\nalarm occurs." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DIVCNT_RST + description: "When set, Timer %s 's clock divider counter will be reset." + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: DIVIDER + description: Timer %s clock (T%s_clk) prescaler value. + bitOffset: 13 + bitWidth: 16 + access: read-write + - name: AUTORELOAD + description: "When set, timer %s auto-reload at alarm is enabled." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: INCREASE + description: "When set, the timer %s time-base counter will increment every clock tick. When\ncleared, the timer %s time-base counter will decrement." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: EN + description: "When set, the timer %s time-base counter is enabled." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: T0LO + description: "Timer %s current value, low 32 bits" + addressOffset: 4 + size: 32 + fields: + - name: LO + description: "After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter\nof timer %s can be read here." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: T0HI + description: "Timer %s current value, high 22 bits" + addressOffset: 8 + size: 32 + fields: + - name: HI + description: "After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter\nof timer %s can be read here." + bitOffset: 0 + bitWidth: 22 + access: read-only + - register: + name: T0UPDATE + description: Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG + addressOffset: 12 + size: 32 + fields: + - name: UPDATE + description: "After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: T0ALARMLO + description: "Timer %s alarm value, low 32 bits" + addressOffset: 16 + size: 32 + fields: + - name: ALARM_LO + description: "Timer %s alarm trigger time-base counter value, low 32 bits." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: T0ALARMHI + description: "Timer %s alarm value, high bits" + addressOffset: 20 + size: 32 + fields: + - name: ALARM_HI + description: "Timer %s alarm trigger time-base counter value, high 22 bits." + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: T0LOADLO + description: "Timer %s reload value, low 32 bits" + addressOffset: 24 + size: 32 + fields: + - name: LOAD_LO + description: "Low 32 bits of the value that a reload will load onto timer %s time-base\nCounter." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: T0LOADHI + description: "Timer %s reload value, high 22 bits" + addressOffset: 28 + size: 32 + fields: + - name: LOAD_HI + description: "High 22 bits of the value that a reload will load onto timer %s time-base\ncounter." + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: T0LOAD + description: Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG + addressOffset: 32 + size: 32 + fields: + - name: LOAD + description: Write any value to trigger a timer %s time-base counter reload. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: WDTCONFIG0 + description: Watchdog timer configuration register + addressOffset: 72 + size: 32 + resetValue: 311296 + fields: + - name: WDT_APPCPU_RESET_EN + description: WDT reset CPU enable. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: WDT_PROCPU_RESET_EN + description: WDT reset CPU enable. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: WDT_FLASHBOOT_MOD_EN + description: "When set, Flash boot protection is enabled." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: WDT_SYS_RESET_LENGTH + description: "System reset signal length selection. 0: 100 ns, 1: 200 ns,\n2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us." + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: WDT_CPU_RESET_LENGTH + description: "CPU reset signal length selection. 0: 100 ns, 1: 200 ns,\n2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us." + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: WDT_USE_XTAL + description: "choose WDT clock:0-apb_clk, 1-xtal_clk." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: WDT_CONF_UPDATE_EN + description: update the WDT configuration registers + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: WDT_STG3 + description: "Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system." + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: WDT_STG2 + description: "Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system." + bitOffset: 25 + bitWidth: 2 + access: read-write + - name: WDT_STG1 + description: "Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system." + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: WDT_STG0 + description: "Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system." + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: WDT_EN + description: "When set, MWDT is enabled." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: WDTCONFIG1 + description: Watchdog timer prescaler register + addressOffset: 76 + size: 32 + resetValue: 65536 + fields: + - name: WDT_DIVCNT_RST + description: "When set, WDT 's clock divider counter will be reset." + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: WDT_CLK_PRESCALE + description: "MWDT clock prescaler value. MWDT clock period = 12.5 ns *\nTIMG_WDT_CLK_PRESCALE." + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: WDTCONFIG2 + description: Watchdog timer stage 0 timeout value + addressOffset: 80 + size: 32 + resetValue: 26000000 + fields: + - name: WDT_STG0_HOLD + description: "Stage 0 timeout value, in MWDT clock cycles." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG3 + description: Watchdog timer stage 1 timeout value + addressOffset: 84 + size: 32 + resetValue: 134217727 + fields: + - name: WDT_STG1_HOLD + description: "Stage 1 timeout value, in MWDT clock cycles." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG4 + description: Watchdog timer stage 2 timeout value + addressOffset: 88 + size: 32 + resetValue: 1048575 + fields: + - name: WDT_STG2_HOLD + description: "Stage 2 timeout value, in MWDT clock cycles." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG5 + description: Watchdog timer stage 3 timeout value + addressOffset: 92 + size: 32 + resetValue: 1048575 + fields: + - name: WDT_STG3_HOLD + description: "Stage 3 timeout value, in MWDT clock cycles." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTFEED + description: Write to feed the watchdog timer + addressOffset: 96 + size: 32 + fields: + - name: WDT_FEED + description: Write any value to feed the MWDT. (WO) + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: WDTWPROTECT + description: Watchdog write protect register + addressOffset: 100 + size: 32 + resetValue: 1356348065 + fields: + - name: WDT_WKEY + description: "If the register contains a different value than its reset value, write\nprotection is enabled." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RTCCALICFG + description: RTC calibration configure register + addressOffset: 104 + size: 32 + resetValue: 69632 + fields: + - name: RTC_CALI_START_CYCLING + description: "0: one-shot frequency calculation,1: periodic frequency calculation," + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RTC_CALI_CLK_SEL + description: "0:rtc slow clock. 1:clk_8m, 2:xtal_32k." + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: RTC_CALI_RDY + description: indicate one-shot frequency calculation is done. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: RTC_CALI_MAX + description: "Configure the time to calculate RTC slow clock's frequency." + bitOffset: 16 + bitWidth: 15 + access: read-write + - name: RTC_CALI_START + description: Set this bit to start one-shot frequency calculation. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RTCCALICFG1 + description: RTC calibration configure1 register + addressOffset: 108 + size: 32 + fields: + - name: RTC_CALI_CYCLING_DATA_VLD + description: indicate periodic frequency calculation is done. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RTC_CALI_VALUE + description: "When one-shot or periodic frequency calculation is done, read this value to calculate RTC slow clock's frequency." + bitOffset: 7 + bitWidth: 25 + access: read-only + - register: + name: INT_ENA_TIMERS + description: Interrupt enable bits + addressOffset: 112 + size: 32 + fields: + - name: T0_INT_ENA + description: The interrupt enable bit for the TIMG_T0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: WDT_INT_ENA + description: The interrupt enable bit for the TIMG_WDT_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW_TIMERS + description: Raw interrupt status + addressOffset: 116 + size: 32 + fields: + - name: T0_INT_RAW + description: The raw interrupt status bit for the TIMG_T0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: WDT_INT_RAW + description: The raw interrupt status bit for the TIMG_WDT_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_ST_TIMERS + description: Masked interrupt status + addressOffset: 120 + size: 32 + fields: + - name: T0_INT_ST + description: The masked interrupt status bit for the TIMG_T0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: WDT_INT_ST + description: The masked interrupt status bit for the TIMG_WDT_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR_TIMERS + description: Interrupt clear bits + addressOffset: 124 + size: 32 + fields: + - name: T0_INT_CLR + description: Set this bit to clear the TIMG_T0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: WDT_INT_CLR + description: Set this bit to clear the TIMG_WDT_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: RTCCALICFG2 + description: Timer group calibration register + addressOffset: 128 + size: 32 + resetValue: 4294967192 + fields: + - name: RTC_CALI_TIMEOUT + description: RTC calibration timeout indicator + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RTC_CALI_TIMEOUT_RST_CNT + description: Cycles that release calibration timeout reset + bitOffset: 3 + bitWidth: 4 + access: read-write + - name: RTC_CALI_TIMEOUT_THRES + description: "Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered." + bitOffset: 7 + bitWidth: 25 + access: read-write + - register: + name: NTIMERS_DATE + description: Timer version control register + addressOffset: 248 + size: 32 + resetValue: 35676274 + fields: + - name: NTIMGS_DATE + description: Timer version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + name: REGCLK + description: Timer group clock gate register + addressOffset: 252 + size: 32 + resetValue: 1879048192 + fields: + - name: ETM_EN + description: "enable timer's etm task and event" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: WDT_CLK_IS_ACTIVE + description: "enable WDT's clock" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TIMER_CLK_IS_ACTIVE + description: "enable Timer 30's clock" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software." + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: TIMG1 + description: Timer Group 1 + baseAddress: 1610649600 + interrupt: + - name: TG1_T0_LEVEL + value: 54 + - name: TG1_T1_LEVEL + value: 55 + - name: TG1_WDT_LEVEL + value: 56 + derivedFrom: TIMG0 + - name: TRACE + description: RISC-V Trace Encoder + groupName: TRACE + baseAddress: 1611399168 + addressBlock: + - offset: 0 + size: 48 + usage: registers + interrupt: + - name: TRACE + value: 27 + registers: + - register: + name: MEM_START_ADDR + description: mem start addr + addressOffset: 0 + size: 32 + fields: + - name: MEM_START_ADDR + description: The start address of trace memory + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: MEM_END_ADDR + description: mem end addr + addressOffset: 4 + size: 32 + resetValue: 4294967295 + fields: + - name: MEM_END_ADDR + description: The end address of trace memory + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: MEM_CURRENT_ADDR + description: mem current addr + addressOffset: 8 + size: 32 + fields: + - name: MEM_CURRENT_ADDR + description: "current_mem_addr,indicate that next writing addr" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: MEM_ADDR_UPDATE + description: mem addr update + addressOffset: 12 + size: 32 + fields: + - name: MEM_CURRENT_ADDR_UPDATE + description: "when set this reg, the current_mem_addr will update to start_addr" + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: FIFO_STATUS + description: fifo status register + addressOffset: 16 + size: 32 + resetValue: 1 + fields: + - name: FIFO_EMPTY + description: 1 indicate that fifo is empty + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: WORK_STATUS + description: mem_full interrupt status + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INTR_ENA + description: interrupt enable register + addressOffset: 20 + size: 32 + fields: + - name: FIFO_OVERFLOW_INTR_ENA + description: Set 1 enable fifo_overflow interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_FULL_INTR_ENA + description: Set 1 enable mem_full interrupt + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INTR_RAW + description: interrupt status register + addressOffset: 24 + size: 32 + fields: + - name: FIFO_OVERFLOW_INTR_RAW + description: fifo_overflow interrupt status + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: MEM_FULL_INTR_RAW + description: mem_full interrupt status + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INTR_CLR + description: interrupt clear register + addressOffset: 28 + size: 32 + fields: + - name: FIFO_OVERFLOW_INTR_CLR + description: Set 1 clr fifo overflow interrupt + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: MEM_FULL_INTR_CLR + description: Set 1 clr mem full interrupt + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: TRIGGER + description: trigger register + addressOffset: 32 + size: 32 + resetValue: 12 + fields: + - name: "ON" + description: "[0] set 1 start trace." + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: "OFF" + description: set 1 stop trace. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: MEM_LOOP + description: "if this reg is 1, trace will loop wrtie trace_mem. If is 0, when mem_current_addr at mem_end_addr, it will stop at the mem_end_addr" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RESTART_ENA + description: "enable encoder auto-restart, when lost package, the encoder will end, if enable auto-restart, when fifo empty, encoder will restart and send a sync package." + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: RESYNC_PROLONGED + description: resync configuration register + addressOffset: 36 + size: 32 + resetValue: 128 + fields: + - name: RESYNC_PROLONGED + description: "count number, when count to this value, send a sync package" + bitOffset: 0 + bitWidth: 24 + access: read-write + - name: RESYNC_MODE + description: "resyc mode sel: 0: default, cycle count 1: package num count" + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: CLOCK_GATE + description: Clock gate control register + addressOffset: 40 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: The bit is used to enable clock gate when access all registers in this module. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 1020 + size: 32 + resetValue: 35663920 + fields: + - name: DATE + description: version control register. Note that this default value stored is the latest date when the hardware logic was updated. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: TWAI0 + description: Two-Wire Automotive Interface + groupName: TWAI + baseAddress: 1610657792 + addressBlock: + - offset: 0 + size: 128 + usage: registers + interrupt: + - name: TWAI0 + value: 46 + registers: + - register: + name: MODE + description: TWAI mode register. + addressOffset: 0 + size: 32 + resetValue: 1 + fields: + - name: RESET_MODE + description: "1: reset, detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode. 0: normal, on the '1-to-0' transition of the reset mode bit, the TWAI controller returns to the operating mode." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LISTEN_ONLY_MODE + description: "1: listen only, in this mode the TWAI controller would give no acknowledge to the TWAI-bus, even if a message is received successfully. The error counters are stopped at the current value. 0: normal." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SELF_TEST_MODE + description: "1: self test, in this mode a full node test is possible without any other active node on the bus using the self reception request command. The TWAI controller will perform a successful transmission, even if there is no acknowledge received. 0: normal, an acknowledge is required for successful transmission." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_FILTER_MODE + description: "1:single, the single acceptance filter option is enabled (one filter with the length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled (two filters, each with the length of 16 bit are active)." + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: CMD + description: TWAI command register. + addressOffset: 4 + size: 32 + fields: + - name: TX_REQ + description: "1: present, a message shall be transmitted. 0: absent" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ABORT_TX + description: "1: present, if not already in progress, a pending transmission request is cancelled. 0: absent" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RELEASE_BUF + description: "1: released, the receive buffer, representing the message memory space in the RXFIFO is released. 0: no action" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CLEAR_DATA_OVERRUN + description: "1: clear, the data overrun status bit is cleared. 0: no action." + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SELF_RX_REQUEST + description: "1: present, a message shall be transmitted and received simultaneously. 0: absent." + bitOffset: 4 + bitWidth: 1 + access: write-only + - register: + name: STATUS + description: TWAI status register. + addressOffset: 8 + size: 32 + fields: + - name: RX_BUF_ST + description: "1: full, one or more complete messages are available in the RXFIFO. 0: empty, no message is available" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OVERRUN + description: "1: overrun, a message was lost because there was not enough space for that message in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data overrun command was given" + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TX_BUF_ST + description: "1: released, the CPU may write a message into the transmit buffer. 0: locked, the CPU cannot access the transmit buffer, a message is either waiting for transmission or is in the process of being transmitted" + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TRANSMISSION_COMPLETE + description: "1: complete, last requested transmission has been successfully completed. 0: incomplete, previously requested transmission is not yet completed" + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: RECEIVE + description: "1: receive, the TWAI controller is receiving a message. 0: idle" + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TRANSMIT + description: "1: transmit, the TWAI controller is transmitting a message. 0: idle" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ERR + description: "1: error, at least one of the error counters has reached or exceeded the CPU warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error counters are below the warning limit" + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BUS_OFF_ST + description: "1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the TWAI controller is involved in bus activities" + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: MISS_ST + description: "1: current message is destroyed because of FIFO overflow." + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INTERRUPT + description: "Interrupt signals' register." + addressOffset: 12 + size: 32 + fields: + - name: RECEIVE_INT_ST + description: "1: this bit is set while the receive FIFO is not empty and the RIE bit is set within the interrupt enable register. 0: reset" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TRANSMIT_INT_ST + description: "1: this bit is set whenever the transmit buffer status changes from '0-to-1' (released) and the TIE bit is set within the interrupt enable register. 0: reset" + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ERR_WARNING_INT_ST + description: "1: this bit is set on every change (set and clear) of either the error status or bus status bits and the EIE bit is set within the interrupt enable register. 0: reset" + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: DATA_OVERRUN_INT_ST + description: "1: this bit is set on a '0-to-1' transition of the data overrun status bit and the DOIE bit is set within the interrupt enable register. 0: reset" + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: ERR_PASSIVE_INT_ST + description: "1: this bit is set whenever the TWAI controller has reached the error passive status (at least one error counter exceeds the protocol-defined level of 127) or if the TWAI controller is in the error passive status and enters the error active status again and the EPIE bit is set within the interrupt enable register. 0: reset" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_ST + description: "1: this bit is set when the TWAI controller lost the arbitration and becomes a receiver and the ALIE bit is set within the interrupt enable register. 0: reset" + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BUS_ERR_INT_ST + description: "1: this bit is set when the TWAI controller detects an error on the TWAI-bus and the BEIE bit is set within the interrupt enable register. 0: reset" + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IDLE_INT_ST + description: "1: this bit is set when the TWAI controller detects state of TWAI become IDLE and this interrupt enable bit is set within the interrupt enable register. 0: reset" + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INTERRUPT_ENABLE + description: Interrupt enable register. + addressOffset: 16 + size: 32 + fields: + - name: EXT_RECEIVE_INT_ENA + description: "1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EXT_TRANSMIT_INT_ENA + description: "1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EXT_ERR_WARNING_INT_ENA + description: "1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EXT_DATA_OVERRUN_INT_ENA + description: "1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ERR_PASSIVE_INT_ENA + description: "1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: ARBITRATION_LOST_INT_ENA + description: "1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BUS_ERR_INT_ENA + description: "1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IDLE_INT_ENA + description: "1: enabled, if state of TWAI become IDLE, the TWAI controller requests the respective interrupt. 0: disable" + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: BUS_TIMING_0 + description: Bit timing configuration register 0. + addressOffset: 24 + size: 32 + fields: + - name: BAUD_PRESC + description: The period of the TWAI system clock is programmable and determines the individual bit timing. Software has R/W permission in reset mode and RO permission in operation mode. + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: SYNC_JUMP_WIDTH + description: The synchronization jump width defines the maximum number of clock cycles a bit period may be shortened or lengthened. Software has R/W permission in reset mode and RO in operation mode. + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: BUS_TIMING_1 + description: Bit timing configuration register 1. + addressOffset: 28 + size: 32 + fields: + - name: TIME_SEG1 + description: The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in reset mode and RO in operation mode. + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: TIME_SEG2 + description: The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in reset mode and RO in operation mode. + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: TIME_SAMP + description: "1: triple, the bus is sampled three times. 0: single, the bus is sampled once. Software has R/W permission in reset mode and RO in operation mode." + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: ARB_LOST_CAP + description: TWAI arbiter lost capture register. + addressOffset: 44 + size: 32 + fields: + - name: ARBITRATION_LOST_CAPTURE + description: This register contains information about the bit position of losing arbitration. + bitOffset: 0 + bitWidth: 5 + access: read-only + - register: + name: ERR_CODE_CAP + description: TWAI error info capture register. + addressOffset: 48 + size: 32 + fields: + - name: ERR_CAPTURE_CODE_SEGMENT + description: This register contains information about the location of errors on the bus. + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: ERR_CAPTURE_CODE_DIRECTION + description: "1: RX, error occurred during reception. 0: TX, error occurred during transmission." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ERR_CAPTURE_CODE_TYPE + description: "00: bit error. 01: form error. 10:stuff error. 11:other type of error." + bitOffset: 6 + bitWidth: 2 + access: read-only + - register: + name: ERR_WARNING_LIMIT + description: TWAI error threshold configuration register. + addressOffset: 52 + size: 32 + resetValue: 96 + fields: + - name: ERR_WARNING_LIMIT + description: The threshold that trigger error warning interrupt when this interrupt is enabled. Software has R/W permission in reset mode and RO in operation mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: RX_ERR_CNT + description: Rx error counter register. + addressOffset: 56 + size: 32 + fields: + - name: RX_ERR_CNT + description: The RX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: TX_ERR_CNT + description: Tx error counter register. + addressOffset: 60 + size: 32 + fields: + - name: TX_ERR_CNT + description: The TX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_0 + description: Data register 0. + addressOffset: 64 + size: 32 + fields: + - name: TX_BYTE_0 + description: "In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 0 and when software initiate read operation, it is rx data register 0." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_1 + description: Data register 1. + addressOffset: 68 + size: 32 + fields: + - name: TX_BYTE_1 + description: "In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 1 and when software initiate read operation, it is rx data register 1." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_2 + description: Data register 2. + addressOffset: 72 + size: 32 + fields: + - name: TX_BYTE_2 + description: "In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 2 and when software initiate read operation, it is rx data register 2." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_3 + description: Data register 3. + addressOffset: 76 + size: 32 + fields: + - name: TX_BYTE_3 + description: "In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 3 and when software initiate read operation, it is rx data register 3." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_4 + description: Data register 4. + addressOffset: 80 + size: 32 + fields: + - name: TX_BYTE_4 + description: "In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 4 and when software initiate read operation, it is rx data register 4." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_5 + description: Data register 5. + addressOffset: 84 + size: 32 + fields: + - name: TX_BYTE_5 + description: "In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 5 and when software initiate read operation, it is rx data register 5." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_6 + description: Data register 6. + addressOffset: 88 + size: 32 + fields: + - name: TX_BYTE_6 + description: "In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 6 and when software initiate read operation, it is rx data register 6." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_7 + description: Data register 7. + addressOffset: 92 + size: 32 + fields: + - name: TX_BYTE_7 + description: "In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 7 and when software initiate read operation, it is rx data register 7." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_8 + description: Data register 8. + addressOffset: 96 + size: 32 + fields: + - name: TX_BYTE_8 + description: "In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 8 and when software initiate read operation, it is rx data register 8." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_9 + description: Data register 9. + addressOffset: 100 + size: 32 + fields: + - name: DATA_9 + description: "In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 9 and when software initiate read operation, it is rx data register 9." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_10 + description: Data register 10. + addressOffset: 104 + size: 32 + fields: + - name: TX_BYTE_10 + description: "In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 10 and when software initiate read operation, it is rx data register 10." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_11 + description: Data register 11. + addressOffset: 108 + size: 32 + fields: + - name: TX_BYTE_11 + description: "In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 11 and when software initiate read operation, it is rx data register 11." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_12 + description: Data register 12. + addressOffset: 112 + size: 32 + fields: + - name: TX_BYTE_12 + description: "In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 12 and when software initiate read operation, it is rx data register 12." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: RX_MESSAGE_CNT + description: Received message counter register. + addressOffset: 116 + size: 32 + fields: + - name: RX_MESSAGE_COUNTER + description: Reflects the number of messages available within the RXFIFO. The value is incremented with each receive event and decremented by the release receive buffer command. + bitOffset: 0 + bitWidth: 7 + access: read-only + - register: + name: CLOCK_DIVIDER + description: Clock divider register. + addressOffset: 124 + size: 32 + fields: + - name: CD + description: These bits are used to define the frequency at the external CLKOUT pin. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CLOCK_OFF + description: "1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has R/W permission in reset mode and RO in operation mode." + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: SW_STANDBY_CFG + description: Software configure standby pin directly. + addressOffset: 128 + size: 32 + resetValue: 2 + fields: + - name: SW_STANDBY_EN + description: Enable standby pin. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SW_STANDBY_CLR + description: Clear standby pin. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: HW_CFG + description: Hardware configure standby pin. + addressOffset: 132 + size: 32 + fields: + - name: HW_STANDBY_EN + description: Enable function that hardware control standby pin. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: HW_STANDBY_CNT + description: Configure standby counter. + addressOffset: 136 + size: 32 + resetValue: 1 + fields: + - name: STANDBY_WAIT_CNT + description: Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN is enabled. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: IDLE_INTR_CNT + description: Configure idle interrupt counter. + addressOffset: 140 + size: 32 + resetValue: 1 + fields: + - name: IDLE_INTR_CNT + description: Configure the number of cycles before triggering idle interrupt. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ECO_CFG + description: ECO configuration register. + addressOffset: 144 + size: 32 + resetValue: 2 + fields: + - name: RDN_ENA + description: Enable eco module. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RDN_RESULT + description: Output of eco module. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TWAI1 + description: Two-Wire Automotive Interface + baseAddress: 1610665984 + interrupt: + - name: TWAI1 + value: 47 + derivedFrom: TWAI0 + - name: UART0 + description: UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + groupName: UART + baseAddress: 1610612736 + addressBlock: + - offset: 0 + size: 152 + usage: registers + interrupt: + - name: UART0 + value: 43 + registers: + - register: + name: FIFO + description: FIFO data register + addressOffset: 0 + size: 32 + fields: + - name: RXFIFO_RD_BYTE + description: UART 0 accesses FIFO via this register. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 4 + size: 32 + resetValue: 2 + fields: + - name: RXFIFO_FULL_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_EMPTY_INT_RAW + description: This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PARITY_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a parity error in the data. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FRM_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a data frame error . + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DSR_CHG_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CTS_CHG_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BRK_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RXFIFO_TOUT_INT_RAW + description: This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SW_XON_INT_RAW + description: This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SW_XOFF_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GLITCH_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_BRK_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_BRK_IDLE_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RS485_PARITY_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RS485_FRM_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RS485_CLASH_INT_RAW + description: This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: AT_CMD_CHAR_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: WAKEUP_INT_RAW + description: This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 8 + size: 32 + fields: + - name: RXFIFO_FULL_INT_ST + description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_EMPTY_INT_ST + description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: PARITY_ERR_INT_ST + description: This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FRM_ERR_INT_ST + description: This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_ST + description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DSR_CHG_INT_ST + description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CTS_CHG_INT_ST + description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BRK_DET_INT_ST + description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: RXFIFO_TOUT_INT_ST + description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SW_XON_INT_ST + description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SW_XOFF_INT_ST + description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: GLITCH_DET_INT_ST + description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TX_BRK_DONE_INT_ST + description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: TX_BRK_IDLE_DONE_INT_ST + description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_ST + description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: RS485_PARITY_ERR_INT_ST + description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: RS485_FRM_ERR_INT_ST + description: This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: RS485_CLASH_INT_ST + description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: AT_CMD_CHAR_DET_INT_ST + description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: WAKEUP_INT_ST + description: This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + bitOffset: 19 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 12 + size: 32 + fields: + - name: RXFIFO_FULL_INT_ENA + description: This is the enable bit for rxfifo_full_int_st register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_EMPTY_INT_ENA + description: This is the enable bit for txfifo_empty_int_st register. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PARITY_ERR_INT_ENA + description: This is the enable bit for parity_err_int_st register. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FRM_ERR_INT_ENA + description: This is the enable bit for frm_err_int_st register. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_ENA + description: This is the enable bit for rxfifo_ovf_int_st register. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DSR_CHG_INT_ENA + description: This is the enable bit for dsr_chg_int_st register. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CTS_CHG_INT_ENA + description: This is the enable bit for cts_chg_int_st register. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BRK_DET_INT_ENA + description: This is the enable bit for brk_det_int_st register. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RXFIFO_TOUT_INT_ENA + description: This is the enable bit for rxfifo_tout_int_st register. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SW_XON_INT_ENA + description: This is the enable bit for sw_xon_int_st register. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SW_XOFF_INT_ENA + description: This is the enable bit for sw_xoff_int_st register. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GLITCH_DET_INT_ENA + description: This is the enable bit for glitch_det_int_st register. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_BRK_DONE_INT_ENA + description: This is the enable bit for tx_brk_done_int_st register. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_BRK_IDLE_DONE_INT_ENA + description: This is the enable bit for tx_brk_idle_done_int_st register. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_ENA + description: This is the enable bit for tx_done_int_st register. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RS485_PARITY_ERR_INT_ENA + description: This is the enable bit for rs485_parity_err_int_st register. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RS485_FRM_ERR_INT_ENA + description: This is the enable bit for rs485_parity_err_int_st register. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RS485_CLASH_INT_ENA + description: This is the enable bit for rs485_clash_int_st register. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: AT_CMD_CHAR_DET_INT_ENA + description: This is the enable bit for at_cmd_char_det_int_st register. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: WAKEUP_INT_ENA + description: This is the enable bit for uart_wakeup_int_st register. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 16 + size: 32 + fields: + - name: RXFIFO_FULL_INT_CLR + description: Set this bit to clear the rxfifo_full_int_raw interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TXFIFO_EMPTY_INT_CLR + description: Set this bit to clear txfifo_empty_int_raw interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: PARITY_ERR_INT_CLR + description: Set this bit to clear parity_err_int_raw interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: FRM_ERR_INT_CLR + description: Set this bit to clear frm_err_int_raw interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: RXFIFO_OVF_INT_CLR + description: Set this bit to clear rxfifo_ovf_int_raw interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: DSR_CHG_INT_CLR + description: Set this bit to clear the dsr_chg_int_raw interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CTS_CHG_INT_CLR + description: Set this bit to clear the cts_chg_int_raw interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: BRK_DET_INT_CLR + description: Set this bit to clear the brk_det_int_raw interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: RXFIFO_TOUT_INT_CLR + description: Set this bit to clear the rxfifo_tout_int_raw interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SW_XON_INT_CLR + description: Set this bit to clear the sw_xon_int_raw interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SW_XOFF_INT_CLR + description: Set this bit to clear the sw_xoff_int_raw interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: GLITCH_DET_INT_CLR + description: Set this bit to clear the glitch_det_int_raw interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TX_BRK_DONE_INT_CLR + description: Set this bit to clear the tx_brk_done_int_raw interrupt.. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: TX_BRK_IDLE_DONE_INT_CLR + description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: TX_DONE_INT_CLR + description: Set this bit to clear the tx_done_int_raw interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: RS485_PARITY_ERR_INT_CLR + description: Set this bit to clear the rs485_parity_err_int_raw interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: RS485_FRM_ERR_INT_CLR + description: Set this bit to clear the rs485_frm_err_int_raw interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: RS485_CLASH_INT_CLR + description: Set this bit to clear the rs485_clash_int_raw interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: AT_CMD_CHAR_DET_INT_CLR + description: Set this bit to clear the at_cmd_char_det_int_raw interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: WAKEUP_INT_CLR + description: Set this bit to clear the uart_wakeup_int_raw interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - register: + name: CLKDIV + description: Clock divider configuration + addressOffset: 20 + size: 32 + resetValue: 694 + fields: + - name: CLKDIV + description: The integral part of the frequency divider factor. + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: FRAG + description: The decimal part of the frequency divider factor. + bitOffset: 20 + bitWidth: 4 + access: read-write + - register: + name: RX_FILT + description: Rx Filter configuration + addressOffset: 24 + size: 32 + resetValue: 8 + fields: + - name: GLITCH_FILT + description: when input pulse width is lower than this value the pulse is ignored. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GLITCH_FILT_EN + description: Set this bit to enable Rx signal filter. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: STATUS + description: UART status register + addressOffset: 28 + size: 32 + resetValue: 3758145536 + fields: + - name: RXFIFO_CNT + description: Stores the byte number of valid data in Rx-FIFO. + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: DSRN + description: The register represent the level value of the internal uart dsr signal. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: CTSN + description: This register represent the level value of the internal uart cts signal. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: RXD + description: This register represent the level value of the internal uart rxd signal. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TXFIFO_CNT + description: Stores the byte number of data in Tx-FIFO. + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: DTRN + description: This bit represents the level of the internal uart dtr signal. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: RTSN + description: This bit represents the level of the internal uart rts signal. + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: TXD + description: This bit represents the level of the internal uart txd signal. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CONF0 + description: a + addressOffset: 32 + size: 32 + resetValue: 1048604 + fields: + - name: PARITY + description: This register is used to configure the parity check mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PARITY_EN + description: Set this bit to enable uart parity check. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BIT_NUM + description: This register is used to set the length of data. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: STOP_BIT_NUM + description: This register is used to set the length of stop bit. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: TXD_BRK + description: Set this bit to enbale transmitter to send NULL when the process of sending data is done. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: IRDA_DPLX + description: Set this bit to enable IrDA loopback mode. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IRDA_TX_EN + description: This is the start enable bit for IrDA transmitter. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: IRDA_WCTL + description: "1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: IRDA_TX_INV + description: Set this bit to invert the level of IrDA transmitter. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: IRDA_RX_INV + description: Set this bit to invert the level of IrDA receiver. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: LOOPBACK + description: Set this bit to enable uart loopback test mode. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_FLOW_EN + description: Set this bit to enable flow control function for transmitter. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: IRDA_EN + description: Set this bit to enable IrDA protocol. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RXD_INV + description: Set this bit to inverse the level value of uart rxd signal. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TXD_INV + description: Set this bit to inverse the level value of uart txd signal. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DIS_RX_DAT_OVF + description: Disable UART Rx data overflow detect. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: ERR_WR_MASK + description: "1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: AUTOBAUD_EN + description: This is the enable bit for detecting baudrate. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: MEM_CLK_EN + description: UART memory clock gate enable signal. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SW_RTS + description: This register is used to configure the software rts signal which is used in software flow control. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: RXFIFO_RST + description: Set this bit to reset the uart receive-FIFO. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TXFIFO_RST + description: Set this bit to reset the uart transmit-FIFO. + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: CONF1 + description: Configuration register 1 + addressOffset: 36 + size: 32 + resetValue: 24672 + fields: + - name: RXFIFO_FULL_THRHD + description: It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TXFIFO_EMPTY_THRHD + description: It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: CTS_INV + description: Set this bit to inverse the level value of uart cts signal. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DSR_INV + description: Set this bit to inverse the level value of uart dsr signal. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: RTS_INV + description: Set this bit to inverse the level value of uart rts signal. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: DTR_INV + description: Set this bit to inverse the level value of uart dtr signal. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SW_DTR + description: This register is used to configure the software dtr signal which is used in software flow control. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers." + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + name: HWFC_CONF + description: Hardware flow-control configuration + addressOffset: 44 + size: 32 + fields: + - name: RX_FLOW_THRHD + description: This register is used to configure the maximum amount of data that can be received when hardware flow control works. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: RX_FLOW_EN + description: This is the flow enable bit for UART receiver. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: SLEEP_CONF0 + description: UART sleep configure register 0 + addressOffset: 48 + size: 32 + fields: + - name: WK_CHAR1 + description: This register restores the specified wake up char1 to wake up + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: WK_CHAR2 + description: This register restores the specified wake up char2 to wake up + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: WK_CHAR3 + description: This register restores the specified wake up char3 to wake up + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: WK_CHAR4 + description: This register restores the specified wake up char4 to wake up + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: SLEEP_CONF1 + description: UART sleep configure register 1 + addressOffset: 52 + size: 32 + fields: + - name: WK_CHAR0 + description: This register restores the specified char0 to wake up + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: SLEEP_CONF2 + description: UART sleep configure register 2 + addressOffset: 56 + size: 32 + resetValue: 1311984 + fields: + - name: ACTIVE_THRESHOLD + description: The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: RX_WAKE_UP_THRHD + description: In wake up mode 1 this field is used to set the received data number threshold to wake up chip. + bitOffset: 10 + bitWidth: 8 + access: read-write + - name: WK_CHAR_NUM + description: This register is used to select number of wake up char. + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: WK_CHAR_MASK + description: This register is used to mask wake up char. + bitOffset: 21 + bitWidth: 5 + access: read-write + - name: WK_MODE_SEL + description: "This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than" + bitOffset: 26 + bitWidth: 2 + access: read-write + - register: + name: SWFC_CONF0 + description: Software flow-control character configuration + addressOffset: 60 + size: 32 + resetValue: 4881 + fields: + - name: XON_CHAR + description: This register stores the Xon flow control char. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: XOFF_CHAR + description: This register stores the Xoff flow control char. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: XON_XOFF_STILL_SEND + description: "In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SW_FLOW_CON_EN + description: Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: XONOFF_DEL + description: Set this bit to remove flow control char from the received data. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: FORCE_XON + description: Set this bit to enable the transmitter to go on sending data. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: FORCE_XOFF + description: Set this bit to stop the transmitter from sending data. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SEND_XON + description: Set this bit to send Xon char. It is cleared by hardware automatically. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SEND_XOFF + description: Set this bit to send Xoff char. It is cleared by hardware automatically. + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: SWFC_CONF1 + description: Software flow-control character configuration + addressOffset: 64 + size: 32 + resetValue: 57344 + fields: + - name: XON_THRESHOLD + description: When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: XOFF_THRESHOLD + description: When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char. + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: TXBRK_CONF + description: Tx Break character configuration + addressOffset: 68 + size: 32 + resetValue: 10 + fields: + - name: TX_BRK_NUM + description: This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: IDLE_CONF + description: Frame-end idle configuration + addressOffset: 72 + size: 32 + resetValue: 262400 + fields: + - name: RX_IDLE_THRHD + description: It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: TX_IDLE_NUM + description: This register is used to configure the duration time between transfers. + bitOffset: 10 + bitWidth: 10 + access: read-write + - register: + name: RS485_CONF + description: RS485 mode configuration + addressOffset: 76 + size: 32 + fields: + - name: RS485_EN + description: Set this bit to choose the rs485 mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DL0_EN + description: Set this bit to delay the stop bit by 1 bit. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DL1_EN + description: Set this bit to delay the stop bit by 1 bit. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RS485TX_RX_EN + description: Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RS485RXBY_TX_EN + description: "1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RS485_RX_DLY_NUM + description: "This register is used to delay the receiver's internal data signal." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RS485_TX_DLY_NUM + description: "This register is used to delay the transmitter's internal data signal." + bitOffset: 6 + bitWidth: 4 + access: read-write + - register: + name: AT_CMD_PRECNT + description: Pre-sequence timing configuration + addressOffset: 80 + size: 32 + resetValue: 2305 + fields: + - name: PRE_IDLE_NUM + description: This register is used to configure the idle duration time before the first at_cmd is received by receiver. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_POSTCNT + description: Post-sequence timing configuration + addressOffset: 84 + size: 32 + resetValue: 2305 + fields: + - name: POST_IDLE_NUM + description: This register is used to configure the duration time between the last at_cmd and the next data. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_GAPTOUT + description: Timeout configuration + addressOffset: 88 + size: 32 + resetValue: 11 + fields: + - name: RX_GAP_TOUT + description: This register is used to configure the duration time between the at_cmd chars. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_CHAR + description: AT escape sequence detection configuration + addressOffset: 92 + size: 32 + resetValue: 811 + fields: + - name: AT_CMD_CHAR + description: This register is used to configure the content of at_cmd char. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CHAR_NUM + description: This register is used to configure the num of continuous at_cmd chars received by receiver. + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: MEM_CONF + description: UART memory power configuration + addressOffset: 96 + size: 32 + fields: + - name: MEM_FORCE_PD + description: Set this bit to force power down UART memory. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PU + description: Set this bit to force power up UART memory. + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: TOUT_CONF + description: UART threshold and allocation configuration + addressOffset: 100 + size: 32 + resetValue: 40 + fields: + - name: RX_TOUT_EN + description: "This is the enble bit for uart receiver's timeout function." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_TOUT_FLOW_DIS + description: Set this bit to stop accumulating idle_cnt when hardware flow control works. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_TOUT_THRHD + description: This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + bitOffset: 2 + bitWidth: 10 + access: read-write + - register: + name: MEM_TX_STATUS + description: Tx-SRAM write and read offset address. + addressOffset: 104 + size: 32 + fields: + - name: TX_SRAM_WADDR + description: This register stores the offset write address in Tx-SRAM. + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: TX_SRAM_RADDR + description: This register stores the offset read address in Tx-SRAM. + bitOffset: 9 + bitWidth: 8 + access: read-only + - register: + name: MEM_RX_STATUS + description: Rx-SRAM write and read offset address. + addressOffset: 108 + size: 32 + resetValue: 65664 + fields: + - name: RX_SRAM_RADDR + description: This register stores the offset read address in RX-SRAM. + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: RX_SRAM_WADDR + description: This register stores the offset write address in Rx-SRAM. + bitOffset: 9 + bitWidth: 8 + access: read-only + - register: + name: FSM_STATUS + description: UART transmit and receive status. + addressOffset: 112 + size: 32 + fields: + - name: ST_URX_OUT + description: This is the status register of receiver. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: ST_UTX_OUT + description: This is the status register of transmitter. + bitOffset: 4 + bitWidth: 4 + access: read-only + - register: + name: POSPULSE + description: Autobaud high pulse register + addressOffset: 116 + size: 32 + resetValue: 4095 + fields: + - name: POSEDGE_MIN_CNT + description: This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process. + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: NEGPULSE + description: Autobaud low pulse register + addressOffset: 120 + size: 32 + resetValue: 4095 + fields: + - name: NEGEDGE_MIN_CNT + description: This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process. + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: LOWPULSE + description: Autobaud minimum low pulse duration register + addressOffset: 124 + size: 32 + resetValue: 4095 + fields: + - name: MIN_CNT + description: This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process. + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: HIGHPULSE + description: Autobaud minimum high pulse duration register + addressOffset: 128 + size: 32 + resetValue: 4095 + fields: + - name: MIN_CNT + description: This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process. + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: RXD_CNT + description: Autobaud edge change count register + addressOffset: 132 + size: 32 + fields: + - name: RXD_EDGE_CNT + description: This register stores the count of rxd edge change. It is used in baud rate-detect process. + bitOffset: 0 + bitWidth: 10 + access: read-only + - register: + name: CLK_CONF + description: UART core clock configuration + addressOffset: 136 + size: 32 + resetValue: 57675776 + fields: + - name: SCLK_DIV_B + description: The denominator of the frequency divider factor. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_A + description: The numerator of the frequency divider factor. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_NUM + description: The integral part of the frequency divider factor. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: SCLK_SEL + description: "UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: SCLK_EN + description: Set this bit to enable UART Tx/Rx clock. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RST_CORE + description: Write 1 then write 0 to this bit to reset UART Tx/Rx. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TX_SCLK_EN + description: Set this bit to enable UART Tx clock. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: RX_SCLK_EN + description: Set this bit to enable UART Rx clock. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TX_RST_CORE + description: Write 1 then write 0 to this bit to reset UART Tx. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RX_RST_CORE + description: Write 1 then write 0 to this bit to reset UART Rx. + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: UART Version register + addressOffset: 140 + size: 32 + resetValue: 35656288 + fields: + - name: DATE + description: This is the version register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: AFIFO_STATUS + description: UART AFIFO Status + addressOffset: 144 + size: 32 + resetValue: 10 + fields: + - name: TX_AFIFO_FULL + description: Full signal of APB TX AFIFO. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_AFIFO_EMPTY + description: Empty signal of APB TX AFIFO. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_AFIFO_FULL + description: Full signal of APB RX AFIFO. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: RX_AFIFO_EMPTY + description: Empty signal of APB RX AFIFO. + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: REG_UPDATE + description: UART Registers Configuration Update register + addressOffset: 152 + size: 32 + fields: + - name: REG_UPDATE + description: Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: ID + description: UART ID register + addressOffset: 156 + size: 32 + resetValue: 1280 + fields: + - name: ID + description: This register is used to configure the uart_id. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: UART1 + description: UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + baseAddress: 1610616832 + interrupt: + - name: UART1 + value: 44 + derivedFrom: UART0 + - name: UHCI0 + description: Universal Host Controller Interface 0 + groupName: UHCI + baseAddress: 1610633216 + addressBlock: + - offset: 0 + size: 132 + usage: registers + interrupt: + - name: UHCI0 + value: 42 + registers: + - register: + name: CONF0 + description: UHCI Configuration Register0 + addressOffset: 0 + size: 32 + resetValue: 1760 + fields: + - name: TX_RST + description: Write 1 then write 0 to this bit to reset decode state machine. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_RST + description: Write 1 then write 0 to this bit to reset encode state machine. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UART0_CE + description: Set this bit to link up HCI and UART0. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: UART1_CE + description: Set this bit to link up HCI and UART1. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SEPER_EN + description: Set this bit to separate the data frame using a special char. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: HEAD_EN + description: Set this bit to encode the data packet with a formatting header. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CRC_REC_EN + description: Set this bit to enable UHCI to receive the 16 bit CRC. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: UART_IDLE_EOF_EN + description: If this bit is set to 1 UHCI will end the payload receiving process when UART has been in idle state. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: LEN_EOF_EN + description: If this bit is set to 1 UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: ENCODE_CRC_EN + description: Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: UART_RX_BRK_EOF_EN + description: If this bit is set to 1 UHCI will end payload receive process when NULL frame is received by UART. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: UHCI Interrupt Raw Register + addressOffset: 4 + size: 32 + fields: + - name: RX_START_INT_RAW + description: Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when delimiter is sent successfully. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_START_INT_RAW + description: Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when DMA detects delimiter. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_HUNG_INT_RAW + description: Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when the required time of DMA receiving data exceeds the configuration value. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_HUNG_INT_RAW + description: Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when the required time of DMA reading RAM data exceeds the configuration value. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SEND_S_REG_Q_INT_RAW + description: Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with single_send mode. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SEND_A_REG_Q_INT_RAW + description: Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with always_send mode. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUT_EOF_INT_RAW + description: Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when there are errors in EOF. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: APP_CTRL0_INT_RAW + description: Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when UHCI_APP_CTRL0_IN_SET is set to 1. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: APP_CTRL1_INT_RAW + description: Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when UHCI_APP_CTRL1_IN_SET is set to 1. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: UHCI Interrupt Status Register + addressOffset: 8 + size: 32 + fields: + - name: RX_START_INT_ST + description: Indicates the interrupt status of UHCI_RX_START_INT. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_START_INT_ST + description: Indicates the interrupt status of UHCI_TX_START_INT. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_ST + description: Indicates the interrupt status of UHCI_RX_HUNG_INT. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_ST + description: Indicates the interrupt status of UHCI_TX_HUNG_INT. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SEND_S_REG_Q_INT_ST + description: Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SEND_A_REG_Q_INT_ST + description: Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OUTLINK_EOF_ERR_INT_ST + description: Indicates the interrupt status of UHCI_OUT_EOF_INT. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: APP_CTRL0_INT_ST + description: Indicates the interrupt status of UHCI_APP_CTRL0_INT. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: APP_CTRL1_INT_ST + description: Indicates the interrupt status of UHCI_APP_CTRL1_INT. + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: UHCI Interrupt Enable Register + addressOffset: 12 + size: 32 + fields: + - name: RX_START_INT_ENA + description: Set this bit to enable the interrupt of UHCI_RX_START_INT. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_START_INT_ENA + description: Set this bit to enable the interrupt of UHCI_TX_START_INT. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_HUNG_INT_ENA + description: Set this bit to enable the interrupt of UHCI_RX_HUNG_INT. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_HUNG_INT_ENA + description: Set this bit to enable the interrupt of UHCI_TX_HUNG_INT. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SEND_S_REG_Q_INT_ENA + description: Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SEND_A_REG_Q_INT_ENA + description: Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUTLINK_EOF_ERR_INT_ENA + description: Set this bit to enable the interrupt of UHCI_OUT_EOF_INT. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: APP_CTRL0_INT_ENA + description: Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: APP_CTRL1_INT_ENA + description: Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: UHCI Interrupt Clear Register + addressOffset: 16 + size: 32 + fields: + - name: RX_START_INT_CLR + description: Set this bit to clear the raw interrupt of UHCI_RX_START_INT. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TX_START_INT_CLR + description: Set this bit to clear the raw interrupt of UHCI_TX_START_INT. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_HUNG_INT_CLR + description: Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TX_HUNG_INT_CLR + description: Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SEND_S_REG_Q_INT_CLR + description: Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SEND_A_REG_Q_INT_CLR + description: Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: OUTLINK_EOF_ERR_INT_CLR + description: Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: APP_CTRL0_INT_CLR + description: Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: APP_CTRL1_INT_CLR + description: Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT. + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: CONF1 + description: UHCI Configuration Register1 + addressOffset: 20 + size: 32 + resetValue: 51 + fields: + - name: CHECK_SUM_EN + description: Set this bit to enable head checksum check when receiving. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CHECK_SEQ_EN + description: Set this bit to enable sequence number check when receiving. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CRC_DISABLE + description: "Set this bit to support CRC calculation, and data integrity check bit should 1." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SAVE_HEAD + description: Set this bit to save data packet head when UHCI receive data. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_CHECK_SUM_RE + description: Set this bit to encode data packet with checksum. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TX_ACK_NUM_RE + description: Set this bit to encode data packet with ACK when reliable data packet is ready. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: WAIT_SW_START + description: Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SW_START + description: Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT. + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: STATE0 + description: UHCI Receive Status Register + addressOffset: 24 + size: 32 + fields: + - name: RX_ERR_CAUSE + description: "Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is not found, but received packet is completed. 3'b110: CRC check error." + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: DECODE_STATE + description: Indicates UHCI decoder status. + bitOffset: 3 + bitWidth: 3 + access: read-only + - register: + name: STATE1 + description: UHCI Transmit Status Register + addressOffset: 28 + size: 32 + fields: + - name: ENCODE_STATE + description: Indicates UHCI encoder status. + bitOffset: 0 + bitWidth: 3 + access: read-only + - register: + name: ESCAPE_CONF + description: UHCI Escapes Configuration Register0 + addressOffset: 32 + size: 32 + resetValue: 51 + fields: + - name: TX_C0_ESC_EN + description: Set this bit to enable resolve char 0xC0 when DMA receiving data. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_DB_ESC_EN + description: Set this bit to enable resolve char 0xDB when DMA receiving data. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TX_11_ESC_EN + description: Set this bit to enable resolve flow control char 0x11 when DMA receiving data. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_13_ESC_EN + description: Set this bit to enable resolve flow control char 0x13 when DMA receiving data. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_C0_ESC_EN + description: Set this bit to enable replacing 0xC0 with special char when DMA receiving data. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_DB_ESC_EN + description: Set this bit to enable replacing 0xDB with special char when DMA receiving data. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RX_11_ESC_EN + description: Set this bit to enable replacing 0x11 with special char when DMA receiving data. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_13_ESC_EN + description: Set this bit to enable replacing 0x13 with special char when DMA receiving data. + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: HUNG_CONF + description: UHCI Hung Configuration Register0 + addressOffset: 36 + size: 32 + resetValue: 8456208 + fields: + - name: TXFIFO_TIMEOUT + description: Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving data. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TXFIFO_TIMEOUT_SHIFT + description: Configures the maximum counter value. + bitOffset: 8 + bitWidth: 3 + access: read-write + - name: TXFIFO_TIMEOUT_ENA + description: Set this bit to enable TX FIFO timeout when receiving. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RXFIFO_TIMEOUT + description: Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading RAM data. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: RXFIFO_TIMEOUT_SHIFT + description: Configures the maximum counter value. + bitOffset: 20 + bitWidth: 3 + access: read-write + - name: RXFIFO_TIMEOUT_ENA + description: Set this bit to enable TX FIFO timeout when DMA sending data. + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: ACK_NUM + description: UHCI Ack Value Configuration Register0 + addressOffset: 40 + size: 32 + fields: + - name: ACK_NUM + description: Indicates the ACK number during software flow control. + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: LOAD + description: Set this bit to load the ACK value of UHCI_ACK_NUM. + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: RX_HEAD + description: UHCI Head Register + addressOffset: 44 + size: 32 + fields: + - name: RX_HEAD + description: Stores the head of received packet. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: QUICK_SENT + description: UCHI Quick send Register + addressOffset: 48 + size: 32 + fields: + - name: SINGLE_SEND_NUM + description: Configures single_send mode. + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SINGLE_SEND_EN + description: Set this bit to enable sending short packet with single_send mode. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: ALWAYS_SEND_NUM + description: Configures always_send mode. + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: ALWAYS_SEND_EN + description: Set this bit to enable sending short packet with always_send mode. + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: REG_Q0_WORD0 + description: UHCI Q0_WORD0 Quick Send Register + addressOffset: 52 + size: 32 + fields: + - name: SEND_Q0_WORD0 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q0_WORD1 + description: UHCI Q0_WORD1 Quick Send Register + addressOffset: 56 + size: 32 + fields: + - name: SEND_Q0_WORD1 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q1_WORD0 + description: UHCI Q1_WORD0 Quick Send Register + addressOffset: 60 + size: 32 + fields: + - name: SEND_Q1_WORD0 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q1_WORD1 + description: UHCI Q1_WORD1 Quick Send Register + addressOffset: 64 + size: 32 + fields: + - name: SEND_Q1_WORD1 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q2_WORD0 + description: UHCI Q2_WORD0 Quick Send Register + addressOffset: 68 + size: 32 + fields: + - name: SEND_Q2_WORD0 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q2_WORD1 + description: UHCI Q2_WORD1 Quick Send Register + addressOffset: 72 + size: 32 + fields: + - name: SEND_Q2_WORD1 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q3_WORD0 + description: UHCI Q3_WORD0 Quick Send Register + addressOffset: 76 + size: 32 + fields: + - name: SEND_Q3_WORD0 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q3_WORD1 + description: UHCI Q3_WORD1 Quick Send Register + addressOffset: 80 + size: 32 + fields: + - name: SEND_Q3_WORD1 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q4_WORD0 + description: UHCI Q4_WORD0 Quick Send Register + addressOffset: 84 + size: 32 + fields: + - name: SEND_Q4_WORD0 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q4_WORD1 + description: UHCI Q4_WORD1 Quick Send Register + addressOffset: 88 + size: 32 + fields: + - name: SEND_Q4_WORD1 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q5_WORD0 + description: UHCI Q5_WORD0 Quick Send Register + addressOffset: 92 + size: 32 + fields: + - name: SEND_Q5_WORD0 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q5_WORD1 + description: UHCI Q5_WORD1 Quick Send Register + addressOffset: 96 + size: 32 + fields: + - name: SEND_Q5_WORD1 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q6_WORD0 + description: UHCI Q6_WORD0 Quick Send Register + addressOffset: 100 + size: 32 + fields: + - name: SEND_Q6_WORD0 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q6_WORD1 + description: UHCI Q6_WORD1 Quick Send Register + addressOffset: 104 + size: 32 + fields: + - name: SEND_Q6_WORD1 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ESC_CONF0 + description: UHCI Escapes Sequence Configuration Register0 + addressOffset: 108 + size: 32 + resetValue: 14474176 + fields: + - name: SEPER_CHAR + description: "Configures the delimiter for encoding, default value is 0xC0." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SEPER_ESC_CHAR0 + description: "Configures the first char of SLIP escape character, default value is 0xDB." + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SEPER_ESC_CHAR1 + description: "Configures the second char of SLIP escape character, default value is 0xDC." + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: ESC_CONF1 + description: UHCI Escapes Sequence Configuration Register1 + addressOffset: 112 + size: 32 + resetValue: 14539739 + fields: + - name: ESC_SEQ0 + description: "Configures the char needing encoding, which is 0xDB as flow control char by default." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: ESC_SEQ0_CHAR0 + description: "Configures the first char of SLIP escape character, default value is 0xDB." + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: ESC_SEQ0_CHAR1 + description: "Configures the second char of SLIP escape character, default value is 0xDD." + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: ESC_CONF2 + description: UHCI Escapes Sequence Configuration Register2 + addressOffset: 116 + size: 32 + resetValue: 14605073 + fields: + - name: ESC_SEQ1 + description: "Configures the char needing encoding, which is 0x11 as flow control char by default." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: ESC_SEQ1_CHAR0 + description: "Configures the first char of SLIP escape character, default value is 0xDB." + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: ESC_SEQ1_CHAR1 + description: "Configures the second char of SLIP escape character, default value is 0xDE." + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: ESC_CONF3 + description: UHCI Escapes Sequence Configuration Register3 + addressOffset: 120 + size: 32 + resetValue: 14670611 + fields: + - name: ESC_SEQ2 + description: "Configures the char needing encoding, which is 0x13 as flow control char by default." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: ESC_SEQ2_CHAR0 + description: "Configures the first char of SLIP escape character, default value is 0xDB." + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: ESC_SEQ2_CHAR1 + description: "Configures the second char of SLIP escape character, default value is 0xDF." + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: PKT_THRES + description: UCHI Packet Length Configuration Register + addressOffset: 124 + size: 32 + resetValue: 128 + fields: + - name: PKT_THRS + description: "Configures the data packet's maximum length when UHCI_HEAD_EN is 0." + bitOffset: 0 + bitWidth: 13 + access: read-write + - register: + name: DATE + description: UHCI Version Register + addressOffset: 128 + size: 32 + resetValue: 35655936 + fields: + - name: DATE + description: Configures version. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: USB_DEVICE + description: Full-speed USB Serial/JTAG Controller + groupName: USB_DEVICE + baseAddress: 1610674176 + addressBlock: + - offset: 0 + size: 112 + usage: registers + interrupt: + - name: USB_DEVICE + value: 48 + registers: + - register: + name: EP1 + description: FIFO access for the CDC-ACM data IN and OUT endpoints. + addressOffset: 0 + size: 32 + fields: + - name: RDWR_BYTE + description: "Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: EP1_CONF + description: Configuration and control registers for the CDC-ACM FIFOs. + addressOffset: 4 + size: 32 + resetValue: 2 + fields: + - name: WR_DONE + description: Set this bit to indicate writing byte data to UART Tx FIFO is done. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SERIAL_IN_EP_DATA_FREE + description: "1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SERIAL_OUT_EP_DATA_AVAIL + description: "1'b1: Indicate there is data in UART Rx FIFO." + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: INT_RAW + description: Interrupt raw status register. + addressOffset: 8 + size: 32 + resetValue: 8 + fields: + - name: JTAG_IN_FLUSH_INT_RAW + description: The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SOF_INT_RAW + description: The raw interrupt bit turns to high level when SOF frame is received. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SERIAL_OUT_RECV_PKT_INT_RAW + description: The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SERIAL_IN_EMPTY_INT_RAW + description: The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PID_ERR_INT_RAW + description: The raw interrupt bit turns to high level when pid error is detected. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CRC5_ERR_INT_RAW + description: The raw interrupt bit turns to high level when CRC5 error is detected. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CRC16_ERR_INT_RAW + description: The raw interrupt bit turns to high level when CRC16 error is detected. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: STUFF_ERR_INT_RAW + description: The raw interrupt bit turns to high level when stuff error is detected. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IN_TOKEN_REC_IN_EP1_INT_RAW + description: The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: USB_BUS_RESET_INT_RAW + description: The raw interrupt bit turns to high level when usb bus reset is detected. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OUT_EP1_ZERO_PAYLOAD_INT_RAW + description: The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OUT_EP2_ZERO_PAYLOAD_INT_RAW + description: The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RTS_CHG_INT_RAW + description: The raw interrupt bit turns to high level when level of RTS from usb serial channel is changed. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DTR_CHG_INT_RAW + description: The raw interrupt bit turns to high level when level of DTR from usb serial channel is changed. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: GET_LINE_CODE_INT_RAW + description: The raw interrupt bit turns to high level when level of GET LINE CODING request is received. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SET_LINE_CODE_INT_RAW + description: The raw interrupt bit turns to high level when level of SET LINE CODING request is received. + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Interrupt status register. + addressOffset: 12 + size: 32 + fields: + - name: JTAG_IN_FLUSH_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SOF_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SERIAL_OUT_RECV_PKT_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SERIAL_IN_EMPTY_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: PID_ERR_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: CRC5_ERR_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CRC16_ERR_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: STUFF_ERR_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IN_TOKEN_REC_IN_EP1_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: USB_BUS_RESET_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: OUT_EP1_ZERO_PAYLOAD_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: OUT_EP2_ZERO_PAYLOAD_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: RTS_CHG_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: DTR_CHG_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: GET_LINE_CODE_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SET_LINE_CODE_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable status register. + addressOffset: 16 + size: 32 + fields: + - name: JTAG_IN_FLUSH_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SOF_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SERIAL_OUT_RECV_PKT_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SERIAL_IN_EMPTY_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PID_ERR_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CRC5_ERR_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CRC16_ERR_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: STUFF_ERR_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IN_TOKEN_REC_IN_EP1_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: USB_BUS_RESET_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OUT_EP1_ZERO_PAYLOAD_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OUT_EP2_ZERO_PAYLOAD_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RTS_CHG_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DTR_CHG_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: GET_LINE_CODE_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SET_LINE_CODE_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear status register. + addressOffset: 20 + size: 32 + fields: + - name: JTAG_IN_FLUSH_INT_CLR + description: Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SOF_INT_CLR + description: Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SERIAL_OUT_RECV_PKT_INT_CLR + description: Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SERIAL_IN_EMPTY_INT_CLR + description: Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: PID_ERR_INT_CLR + description: Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: CRC5_ERR_INT_CLR + description: Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CRC16_ERR_INT_CLR + description: Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: STUFF_ERR_INT_CLR + description: Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: IN_TOKEN_REC_IN_EP1_INT_CLR + description: Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: USB_BUS_RESET_INT_CLR + description: Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: OUT_EP1_ZERO_PAYLOAD_INT_CLR + description: Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: OUT_EP2_ZERO_PAYLOAD_INT_CLR + description: Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: RTS_CHG_INT_CLR + description: Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: DTR_CHG_INT_CLR + description: Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: GET_LINE_CODE_INT_CLR + description: Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SET_LINE_CODE_INT_CLR + description: Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - register: + name: CONF0 + description: PHY hardware configuration. + addressOffset: 24 + size: 32 + resetValue: 16896 + fields: + - name: PHY_SEL + description: Select internal/external PHY + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EXCHG_PINS_OVERRIDE + description: Enable software control USB D+ D- exchange + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EXCHG_PINS + description: USB D+ D- exchange + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: VREFH + description: "Control single-end input high threshold,1.76V to 2V, step 80mV" + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: VREFL + description: "Control single-end input low threshold,0.8V to 1.04V, step 80mV" + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: VREF_OVERRIDE + description: Enable software control input threshold + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: PAD_PULL_OVERRIDE + description: Enable software control USB D+ D- pullup pulldown + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DP_PULLUP + description: Control USB D+ pull up. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DP_PULLDOWN + description: Control USB D+ pull down. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DM_PULLUP + description: Control USB D- pull up. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DM_PULLDOWN + description: Control USB D- pull down. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PULLUP_VALUE + description: Control pull up value. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: USB_PAD_ENABLE + description: Enable USB pad function. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: USB_JTAG_BRIDGE_EN + description: "Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: TEST + description: Registers used for debugging the PHY. + addressOffset: 28 + size: 32 + resetValue: 48 + fields: + - name: TEST_ENABLE + description: Enable test of the USB pad + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TEST_USB_OE + description: USB pad oen in test + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TEST_TX_DP + description: USB D+ tx value in test + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TEST_TX_DM + description: USB D- tx value in test + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TEST_RX_RCV + description: USB RCV value in test + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TEST_RX_DP + description: USB D+ rx value in test + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: TEST_RX_DM + description: USB D- rx value in test + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: JFIFO_ST + description: JTAG FIFO status and control registers. + addressOffset: 32 + size: 32 + resetValue: 68 + fields: + - name: IN_FIFO_CNT + description: JTAT in fifo counter. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_FIFO_EMPTY + description: "1: JTAG in fifo is empty." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: IN_FIFO_FULL + description: "1: JTAG in fifo is full." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: OUT_FIFO_CNT + description: JTAT out fifo counter. + bitOffset: 4 + bitWidth: 2 + access: read-only + - name: OUT_FIFO_EMPTY + description: "1: JTAG out fifo is empty." + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUT_FIFO_FULL + description: "1: JTAG out fifo is full." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IN_FIFO_RESET + description: Write 1 to reset JTAG in fifo. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: OUT_FIFO_RESET + description: Write 1 to reset JTAG out fifo. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: FRAM_NUM + description: Last received SOF frame index register. + addressOffset: 36 + size: 32 + fields: + - name: SOF_FRAME_INDEX + description: Frame index of received SOF frame. + bitOffset: 0 + bitWidth: 11 + access: read-only + - register: + name: IN_EP0_ST + description: Control IN endpoint status information. + addressOffset: 40 + size: 32 + resetValue: 1 + fields: + - name: IN_EP0_STATE + description: State of IN Endpoint 0. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_EP0_WR_ADDR + description: Write data address of IN endpoint 0. + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: IN_EP0_RD_ADDR + description: Read data address of IN endpoint 0. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: IN_EP1_ST + description: CDC-ACM IN endpoint status information. + addressOffset: 44 + size: 32 + resetValue: 1 + fields: + - name: IN_EP1_STATE + description: State of IN Endpoint 1. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_EP1_WR_ADDR + description: Write data address of IN endpoint 1. + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: IN_EP1_RD_ADDR + description: Read data address of IN endpoint 1. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: IN_EP2_ST + description: CDC-ACM interrupt IN endpoint status information. + addressOffset: 48 + size: 32 + resetValue: 1 + fields: + - name: IN_EP2_STATE + description: State of IN Endpoint 2. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_EP2_WR_ADDR + description: Write data address of IN endpoint 2. + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: IN_EP2_RD_ADDR + description: Read data address of IN endpoint 2. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: IN_EP3_ST + description: JTAG IN endpoint status information. + addressOffset: 52 + size: 32 + resetValue: 1 + fields: + - name: IN_EP3_STATE + description: State of IN Endpoint 3. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_EP3_WR_ADDR + description: Write data address of IN endpoint 3. + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: IN_EP3_RD_ADDR + description: Read data address of IN endpoint 3. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: OUT_EP0_ST + description: Control OUT endpoint status information. + addressOffset: 56 + size: 32 + fields: + - name: OUT_EP0_STATE + description: State of OUT Endpoint 0. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: OUT_EP0_WR_ADDR + description: "Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0." + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: OUT_EP0_RD_ADDR + description: Read data address of OUT endpoint 0. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: OUT_EP1_ST + description: CDC-ACM OUT endpoint status information. + addressOffset: 60 + size: 32 + fields: + - name: OUT_EP1_STATE + description: State of OUT Endpoint 1. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: OUT_EP1_WR_ADDR + description: "Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1." + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: OUT_EP1_RD_ADDR + description: Read data address of OUT endpoint 1. + bitOffset: 9 + bitWidth: 7 + access: read-only + - name: OUT_EP1_REC_DATA_CNT + description: Data count in OUT endpoint 1 when one packet is received. + bitOffset: 16 + bitWidth: 7 + access: read-only + - register: + name: OUT_EP2_ST + description: JTAG OUT endpoint status information. + addressOffset: 64 + size: 32 + fields: + - name: OUT_EP2_STATE + description: State of OUT Endpoint 2. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: OUT_EP2_WR_ADDR + description: "Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2." + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: OUT_EP2_RD_ADDR + description: Read data address of OUT endpoint 2. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: MISC_CONF + description: Clock enable control + addressOffset: 68 + size: 32 + fields: + - name: CLK_EN + description: "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: MEM_CONF + description: Memory power control + addressOffset: 72 + size: 32 + resetValue: 2 + fields: + - name: USB_MEM_PD + description: "1: power down usb memory." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: USB_MEM_CLK_EN + description: "1: Force clock on for usb memory." + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CHIP_RST + description: CDC-ACM chip reset control. + addressOffset: 76 + size: 32 + fields: + - name: RTS + description: "1: Chip reset is detected from usb serial channel. Software write 1 to clear it." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DTR + description: "1: Chip reset is detected from usb jtag channel. Software write 1 to clear it." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: USB_UART_CHIP_RST_DIS + description: Set this bit to disable chip reset from usb serial channel to reset chip. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: SET_LINE_CODE_W0 + description: W0 of SET_LINE_CODING command. + addressOffset: 80 + size: 32 + fields: + - name: DW_DTE_RATE + description: The value of dwDTERate set by host through SET_LINE_CODING command. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SET_LINE_CODE_W1 + description: W1 of SET_LINE_CODING command. + addressOffset: 84 + size: 32 + fields: + - name: BCHAR_FORMAT + description: The value of bCharFormat set by host through SET_LINE_CODING command. + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: BPARITY_TYPE + description: The value of bParityTpye set by host through SET_LINE_CODING command. + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: BDATA_BITS + description: The value of bDataBits set by host through SET_LINE_CODING command. + bitOffset: 16 + bitWidth: 8 + access: read-only + - register: + name: GET_LINE_CODE_W0 + description: W0 of GET_LINE_CODING command. + addressOffset: 88 + size: 32 + fields: + - name: GET_DW_DTE_RATE + description: The value of dwDTERate set by software which is requested by GET_LINE_CODING command. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: GET_LINE_CODE_W1 + description: W1 of GET_LINE_CODING command. + addressOffset: 92 + size: 32 + fields: + - name: GET_BDATA_BITS + description: The value of bCharFormat set by software which is requested by GET_LINE_CODING command. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GET_BPARITY_TYPE + description: The value of bParityTpye set by software which is requested by GET_LINE_CODING command. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: GET_BCHAR_FORMAT + description: The value of bDataBits set by software which is requested by GET_LINE_CODING command. + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: CONFIG_UPDATE + description: "Configuration registers' value update" + addressOffset: 96 + size: 32 + fields: + - name: CONFIG_UPDATE + description: Write 1 to this register would update the value of configure registers from APB clock domain to 48MHz clock domain. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SER_AFIFO_CONFIG + description: Serial AFIFO configure register + addressOffset: 100 + size: 32 + resetValue: 16 + fields: + - name: SERIAL_IN_AFIFO_RESET_WR + description: Write 1 to reset CDC_ACM IN async FIFO write clock domain. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SERIAL_IN_AFIFO_RESET_RD + description: Write 1 to reset CDC_ACM IN async FIFO read clock domain. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SERIAL_OUT_AFIFO_RESET_WR + description: Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SERIAL_OUT_AFIFO_RESET_RD + description: Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SERIAL_OUT_AFIFO_REMPTY + description: CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SERIAL_IN_AFIFO_WFULL + description: CDC_ACM OUT IN async FIFO empty signal in write clock domain. + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: BUS_RESET_ST + description: USB Bus reset status register + addressOffset: 104 + size: 32 + resetValue: 1 + fields: + - name: USB_BUS_RESET_ST + description: "USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus reset is released." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: Date register + addressOffset: 128 + size: 32 + resetValue: 34640416 + fields: + - name: DATE + description: register version. + bitOffset: 0 + bitWidth: 32 + access: read-write diff --git a/esp32h2/svd/esp32h2.svd.yaml b/esp32h2/svd/esp32h2.svd.yaml new file mode 100644 index 0000000000..8cb33698ad --- /dev/null +++ b/esp32h2/svd/esp32h2.svd.yaml @@ -0,0 +1,37846 @@ +--- +vendor: "ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD." +vendorID: ESPRESSIF +name: ESP32-H2 +series: ESP32 H-Series +version: "10" +description: 32-bit RISC-V MCU & Bluetooth 5 (LE) & IEEE 802.15.4 +licenseText: "Copyright 2024 Espressif Systems (Shanghai) PTE LTD\n\n Licensed under the Apache License, Version 2.0 (the \"License\");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an \"AS IS\" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License." +cpu: + name: RV32IMAC + revision: r0p0 + endian: little + mpuPresent: false + fpuPresent: false + nvicPrioBits: 0 + vendorSystickConfig: false +addressUnitBits: 32 +width: 32 +resetValue: 0 +resetMask: 4294967295 +peripherals: + - name: AES + description: AES (Advanced Encryption Standard) Accelerator + groupName: AES + baseAddress: 1611169792 + addressBlock: + - offset: 0 + size: 188 + usage: registers + interrupt: + - name: AES + value: 60 + registers: + - register: + name: KEY_0 + description: Key material key_0 configure register + addressOffset: 0 + size: 32 + fields: + - name: KEY_0 + description: This bits stores key_0 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_1 + description: Key material key_1 configure register + addressOffset: 4 + size: 32 + fields: + - name: KEY_1 + description: This bits stores key_1 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_2 + description: Key material key_2 configure register + addressOffset: 8 + size: 32 + fields: + - name: KEY_2 + description: This bits stores key_2 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_3 + description: Key material key_3 configure register + addressOffset: 12 + size: 32 + fields: + - name: KEY_3 + description: This bits stores key_3 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_4 + description: Key material key_4 configure register + addressOffset: 16 + size: 32 + fields: + - name: KEY_4 + description: This bits stores key_4 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_5 + description: Key material key_5 configure register + addressOffset: 20 + size: 32 + fields: + - name: KEY_5 + description: This bits stores key_5 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_6 + description: Key material key_6 configure register + addressOffset: 24 + size: 32 + fields: + - name: KEY_6 + description: This bits stores key_6 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_7 + description: Key material key_7 configure register + addressOffset: 28 + size: 32 + fields: + - name: KEY_7 + description: This bits stores key_7 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_IN_0 + description: source text material text_in_0 configure register + addressOffset: 32 + size: 32 + fields: + - name: TEXT_IN_0 + description: This bits stores text_in_0 that is a part of source text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_IN_1 + description: source text material text_in_1 configure register + addressOffset: 36 + size: 32 + fields: + - name: TEXT_IN_1 + description: This bits stores text_in_1 that is a part of source text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_IN_2 + description: source text material text_in_2 configure register + addressOffset: 40 + size: 32 + fields: + - name: TEXT_IN_2 + description: This bits stores text_in_2 that is a part of source text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_IN_3 + description: source text material text_in_3 configure register + addressOffset: 44 + size: 32 + fields: + - name: TEXT_IN_3 + description: This bits stores text_in_3 that is a part of source text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_OUT_0 + description: result text material text_out_0 configure register + addressOffset: 48 + size: 32 + fields: + - name: TEXT_OUT_0 + description: This bits stores text_out_0 that is a part of result text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_OUT_1 + description: result text material text_out_1 configure register + addressOffset: 52 + size: 32 + fields: + - name: TEXT_OUT_1 + description: This bits stores text_out_1 that is a part of result text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_OUT_2 + description: result text material text_out_2 configure register + addressOffset: 56 + size: 32 + fields: + - name: TEXT_OUT_2 + description: This bits stores text_out_2 that is a part of result text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_OUT_3 + description: result text material text_out_3 configure register + addressOffset: 60 + size: 32 + fields: + - name: TEXT_OUT_3 + description: This bits stores text_out_3 that is a part of result text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: MODE + description: AES Mode register + addressOffset: 64 + size: 32 + fields: + - name: MODE + description: "This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256." + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: ENDIAN + description: AES Endian configure register + addressOffset: 68 + size: 32 + fields: + - name: ENDIAN + description: "endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out endian or out_stream endian" + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: TRIGGER + description: AES trigger register + addressOffset: 72 + size: 32 + fields: + - name: TRIGGER + description: Set this bit to start AES calculation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: STATE + description: AES state register + addressOffset: 76 + size: 32 + fields: + - name: STATE + description: "Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done." + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + dim: 4 + dimIncrement: 4 + name: "IV_MEM[%s]" + description: The memory that stores initialization vector + addressOffset: 80 + size: 32 + - register: + dim: 4 + dimIncrement: 4 + name: "H_MEM[%s]" + description: The memory that stores GCM hash subkey + addressOffset: 96 + size: 32 + - register: + dim: 4 + dimIncrement: 4 + name: "J0_MEM[%s]" + description: The memory that stores J0 + addressOffset: 112 + size: 32 + - register: + dim: 4 + dimIncrement: 4 + name: "T0_MEM[%s]" + description: The memory that stores T0 + addressOffset: 128 + size: 32 + - register: + name: DMA_ENABLE + description: DMA-AES working mode register + addressOffset: 144 + size: 32 + fields: + - name: DMA_ENABLE + description: "1'b0: typical AES working mode, 1'b1: DMA-AES working mode." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: BLOCK_MODE + description: AES cipher block mode register + addressOffset: 148 + size: 32 + fields: + - name: BLOCK_MODE + description: "Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved." + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: BLOCK_NUM + description: AES block number register + addressOffset: 152 + size: 32 + fields: + - name: BLOCK_NUM + description: Those bits stores the number of Plaintext/ciphertext block. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: INC_SEL + description: Standard incrementing function configure register + addressOffset: 156 + size: 32 + fields: + - name: INC_SEL + description: "This bit decides the standard incrementing function. 0: INC32. 1: INC128." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: AAD_BLOCK_NUM + description: Additional Authential Data block number register + addressOffset: 160 + size: 32 + fields: + - name: AAD_BLOCK_NUM + description: Those bits stores the number of AAD block. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REMAINDER_BIT_NUM + description: AES remainder bit number register + addressOffset: 164 + size: 32 + fields: + - name: REMAINDER_BIT_NUM + description: Those bits stores the number of remainder bit. + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: CONTINUE + description: AES continue register + addressOffset: 168 + size: 32 + fields: + - name: CONTINUE + description: Set this bit to continue GCM operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: INT_CLEAR + description: AES Interrupt clear register + addressOffset: 172 + size: 32 + fields: + - name: INT_CLEAR + description: Set this bit to clear the AES interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + description: AES Interrupt enable register + addressOffset: 176 + size: 32 + fields: + - name: INT_ENA + description: Set this bit to enable interrupt that occurs when DMA-AES calculation is done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: AES version control register + addressOffset: 180 + size: 32 + resetValue: 538513936 + fields: + - name: DATE + description: This bits stores the version information of AES. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: DMA_EXIT + description: AES-DMA exit config + addressOffset: 184 + size: 32 + fields: + - name: DMA_EXIT + description: "Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer." + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: APB_SARADC + description: SAR (Successive Approximation Register) Analog-to-Digital Converter + groupName: APB_SARADC + baseAddress: 1610670080 + addressBlock: + - offset: 0 + size: 112 + usage: registers + interrupt: + - name: APB_ADC + value: 48 + registers: + - register: + name: CTRL + description: digital saradc configure register + addressOffset: 0 + size: 32 + resetValue: 1073971776 + fields: + - name: SARADC_START_FORCE + description: select software enable saradc sample + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SARADC_START + description: software enable saradc sample + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SARADC_SAR_CLK_GATED + description: SAR clock gated + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SARADC_SAR_CLK_DIV + description: SAR clock divider + bitOffset: 7 + bitWidth: 8 + access: read-write + - name: SARADC_SAR_PATT_LEN + description: 0 ~ 15 means length 1 ~ 16 + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: SARADC_SAR_PATT_P_CLEAR + description: clear the pointer of pattern table for DIG ADC1 CTRL + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SARADC_XPD_SAR_FORCE + description: force option to xpd sar blocks + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: SARADC2_PWDET_DRV + description: enable saradc2 power detect driven func. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SARADC_WAIT_ARB_CYCLE + description: wait arbit signal stable after sar_done + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CTRL2 + description: digital saradc configure register + addressOffset: 4 + size: 32 + resetValue: 41470 + fields: + - name: SARADC_MEAS_NUM_LIMIT + description: enable max meas num + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SARADC_MAX_MEAS_NUM + description: max conversion number + bitOffset: 1 + bitWidth: 8 + access: read-write + - name: SARADC_SAR1_INV + description: "1: data to DIG ADC1 CTRL is inverted, otherwise not" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SARADC_SAR2_INV + description: "1: data to DIG ADC2 CTRL is inverted, otherwise not" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SARADC_TIMER_TARGET + description: to set saradc timer target + bitOffset: 12 + bitWidth: 12 + access: read-write + - name: SARADC_TIMER_EN + description: to enable saradc timer trigger + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: FILTER_CTRL1 + description: digital saradc configure register + addressOffset: 8 + size: 32 + fields: + - name: APB_SARADC_FILTER_FACTOR1 + description: Factor of saradc filter1 + bitOffset: 26 + bitWidth: 3 + access: read-write + - name: APB_SARADC_FILTER_FACTOR0 + description: Factor of saradc filter0 + bitOffset: 29 + bitWidth: 3 + access: read-write + - register: + name: FSM_WAIT + description: digital saradc configure register + addressOffset: 12 + size: 32 + resetValue: 16713736 + fields: + - name: SARADC_XPD_WAIT + description: saradc_xpd_wait + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SARADC_RSTB_WAIT + description: saradc_rstb_wait + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SARADC_STANDBY_WAIT + description: saradc_standby_wait + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: SAR1_STATUS + description: digital saradc configure register + addressOffset: 16 + size: 32 + resetValue: 536870912 + fields: + - name: SARADC_SAR1_STATUS + description: saradc1 status about data and channel + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SAR2_STATUS + description: digital saradc configure register + addressOffset: 20 + size: 32 + resetValue: 536870912 + fields: + - name: SARADC_SAR2_STATUS + description: saradc2 status about data and channel + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SAR_PATT_TAB1 + description: digital saradc configure register + addressOffset: 24 + size: 32 + resetValue: 16777215 + fields: + - name: SARADC_SAR_PATT_TAB1 + description: item 0 ~ 3 for pattern table 1 (each item one byte) + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: SAR_PATT_TAB2 + description: digital saradc configure register + addressOffset: 28 + size: 32 + resetValue: 16777215 + fields: + - name: SARADC_SAR_PATT_TAB2 + description: Item 4 ~ 7 for pattern table 1 (each item one byte) + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: ONETIME_SAMPLE + description: digital saradc configure register + addressOffset: 32 + size: 32 + resetValue: 436207616 + fields: + - name: SARADC_ONETIME_ATTEN + description: configure onetime atten + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: SARADC_ONETIME_CHANNEL + description: configure onetime channel + bitOffset: 25 + bitWidth: 4 + access: read-write + - name: SARADC_ONETIME_START + description: trigger adc onetime sample + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SARADC2_ONETIME_SAMPLE + description: enable adc2 onetime sample + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SARADC1_ONETIME_SAMPLE + description: enable adc1 onetime sample + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: ARB_CTRL + description: digital saradc configure register + addressOffset: 36 + size: 32 + resetValue: 2304 + fields: + - name: ADC_ARB_APB_FORCE + description: adc2 arbiter force to enableapb controller + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ADC_ARB_RTC_FORCE + description: adc2 arbiter force to enable rtc controller + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ADC_ARB_WIFI_FORCE + description: adc2 arbiter force to enable wifi controller + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ADC_ARB_GRANT_FORCE + description: adc2 arbiter force grant + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: ADC_ARB_APB_PRIORITY + description: Set adc2 arbiterapb priority + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: ADC_ARB_RTC_PRIORITY + description: Set adc2 arbiter rtc priority + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: ADC_ARB_WIFI_PRIORITY + description: Set adc2 arbiter wifi priority + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: ADC_ARB_FIX_PRIORITY + description: adc2 arbiter uses fixed priority + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: FILTER_CTRL0 + description: digital saradc configure register + addressOffset: 40 + size: 32 + resetValue: 57933824 + fields: + - name: APB_SARADC_FILTER_CHANNEL1 + description: configure filter1 to adc channel + bitOffset: 18 + bitWidth: 4 + access: read-write + - name: APB_SARADC_FILTER_CHANNEL0 + description: configure filter0 to adc channel + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: APB_SARADC_FILTER_RESET + description: enable apb_adc1_filter + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAR1DATA_STATUS + description: digital saradc configure register + addressOffset: 44 + size: 32 + fields: + - name: APB_SARADC1_DATA + description: saradc1 data + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: SAR2DATA_STATUS + description: digital saradc configure register + addressOffset: 48 + size: 32 + fields: + - name: APB_SARADC2_DATA + description: saradc2 data + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: THRES0_CTRL + description: digital saradc configure register + addressOffset: 52 + size: 32 + resetValue: 262125 + fields: + - name: APB_SARADC_THRES0_CHANNEL + description: configure thres0 to adc channel + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: APB_SARADC_THRES0_HIGH + description: saradc thres0 monitor thres + bitOffset: 5 + bitWidth: 13 + access: read-write + - name: APB_SARADC_THRES0_LOW + description: saradc thres0 monitor thres + bitOffset: 18 + bitWidth: 13 + access: read-write + - register: + name: THRES1_CTRL + description: digital saradc configure register + addressOffset: 56 + size: 32 + resetValue: 262125 + fields: + - name: APB_SARADC_THRES1_CHANNEL + description: configure thres1 to adc channel + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: APB_SARADC_THRES1_HIGH + description: saradc thres1 monitor thres + bitOffset: 5 + bitWidth: 13 + access: read-write + - name: APB_SARADC_THRES1_LOW + description: saradc thres1 monitor thres + bitOffset: 18 + bitWidth: 13 + access: read-write + - register: + name: THRES_CTRL + description: digital saradc configure register + addressOffset: 60 + size: 32 + fields: + - name: APB_SARADC_THRES_ALL_EN + description: enable thres to all channel + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES1_EN + description: enable thres1 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES0_EN + description: enable thres0 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_ENA + description: digital saradc int register + addressOffset: 64 + size: 32 + fields: + - name: APB_SARADC_TSENS_INT_ENA + description: tsens low interrupt enable + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES1_LOW_INT_ENA + description: saradc thres1 low interrupt enable + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES0_LOW_INT_ENA + description: saradc thres0 low interrupt enable + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES1_HIGH_INT_ENA + description: saradc thres1 high interrupt enable + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES0_HIGH_INT_ENA + description: saradc thres0 high interrupt enable + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: APB_SARADC2_DONE_INT_ENA + description: saradc2 done interrupt enable + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: APB_SARADC1_DONE_INT_ENA + description: saradc1 done interrupt enable + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: digital saradc int register + addressOffset: 68 + size: 32 + fields: + - name: APB_SARADC_TSENS_INT_RAW + description: saradc tsens interrupt raw + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES1_LOW_INT_RAW + description: saradc thres1 low interrupt raw + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES0_LOW_INT_RAW + description: saradc thres0 low interrupt raw + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES1_HIGH_INT_RAW + description: saradc thres1 high interrupt raw + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: APB_SARADC_THRES0_HIGH_INT_RAW + description: saradc thres0 high interrupt raw + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: APB_SARADC2_DONE_INT_RAW + description: saradc2 done interrupt raw + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: APB_SARADC1_DONE_INT_RAW + description: saradc1 done interrupt raw + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: digital saradc int register + addressOffset: 72 + size: 32 + fields: + - name: APB_SARADC_TSENS_INT_ST + description: saradc tsens interrupt state + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: APB_SARADC_THRES1_LOW_INT_ST + description: saradc thres1 low interrupt state + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: APB_SARADC_THRES0_LOW_INT_ST + description: saradc thres0 low interrupt state + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: APB_SARADC_THRES1_HIGH_INT_ST + description: saradc thres1 high interrupt state + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: APB_SARADC_THRES0_HIGH_INT_ST + description: saradc thres0 high interrupt state + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: APB_SARADC2_DONE_INT_ST + description: saradc2 done interrupt state + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: APB_SARADC1_DONE_INT_ST + description: saradc1 done interrupt state + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: digital saradc int register + addressOffset: 76 + size: 32 + fields: + - name: APB_SARADC_TSENS_INT_CLR + description: saradc tsens interrupt clear + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: APB_SARADC_THRES1_LOW_INT_CLR + description: saradc thres1 low interrupt clear + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: APB_SARADC_THRES0_LOW_INT_CLR + description: saradc thres0 low interrupt clear + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: APB_SARADC_THRES1_HIGH_INT_CLR + description: saradc thres1 high interrupt clear + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: APB_SARADC_THRES0_HIGH_INT_CLR + description: saradc thres0 high interrupt clear + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: APB_SARADC2_DONE_INT_CLR + description: saradc2 done interrupt clear + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: APB_SARADC1_DONE_INT_CLR + description: saradc1 done interrupt clear + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: DMA_CONF + description: digital saradc configure register + addressOffset: 80 + size: 32 + resetValue: 255 + fields: + - name: APB_ADC_EOF_NUM + description: the dma_in_suc_eof gen when sample cnt = spi_eof_num + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: APB_ADC_RESET_FSM + description: reset_apb_adc_state + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: APB_ADC_TRANS + description: enable apb_adc use spi_dma + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CLKM_CONF + description: digital saradc configure register + addressOffset: 84 + size: 32 + resetValue: 4 + fields: + - name: CLKM_DIV_NUM + description: Integral I2S clock divider value + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CLKM_DIV_B + description: Fractional clock divider numerator value + bitOffset: 8 + bitWidth: 6 + access: read-write + - name: CLKM_DIV_A + description: Fractional clock divider denominator value + bitOffset: 14 + bitWidth: 6 + access: read-write + - name: CLK_EN + description: reg clk en + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CLK_SEL + description: Set this bit to enable clk_apll + bitOffset: 21 + bitWidth: 2 + access: read-write + - register: + name: APB_TSENS_CTRL + description: digital tsens configure register + addressOffset: 88 + size: 32 + resetValue: 98432 + fields: + - name: TSENS_OUT + description: temperature sensor data out + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: TSENS_IN_INV + description: invert temperature sensor data + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TSENS_CLK_DIV + description: temperature sensor clock divider + bitOffset: 14 + bitWidth: 8 + access: read-write + - name: TSENS_PU + description: temperature sensor power up + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: TSENS_CTRL2 + description: digital tsens configure register + addressOffset: 92 + size: 32 + resetValue: 16386 + fields: + - name: TSENS_XPD_WAIT + description: the time that power up tsens need wait + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: TSENS_XPD_FORCE + description: force power up tsens + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: TSENS_CLK_INV + description: inv tsens clk + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TSENS_CLK_SEL + description: tsens clk select + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: CALI + description: digital saradc configure register + addressOffset: 96 + size: 32 + resetValue: 32768 + fields: + - name: APB_SARADC_CALI_CFG + description: saradc cali factor + bitOffset: 0 + bitWidth: 17 + access: read-write + - register: + name: APB_TSENS_WAKE + description: digital tsens configure register + addressOffset: 100 + size: 32 + resetValue: 65280 + fields: + - name: WAKEUP_TH_LOW + description: reg_wakeup_th_low + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: WAKEUP_TH_HIGH + description: reg_wakeup_th_high + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: WAKEUP_OVER_UPPER_TH + description: reg_wakeup_over_upper_th + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: WAKEUP_MODE + description: reg_wakeup_mode + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: WAKEUP_EN + description: reg_wakeup_en + bitOffset: 18 + bitWidth: 1 + access: read-write + - register: + name: APB_TSENS_SAMPLE + description: digital tsens configure register + addressOffset: 104 + size: 32 + resetValue: 20 + fields: + - name: TSENS_SAMPLE_RATE + description: HW sample rate + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: TSENS_SAMPLE_EN + description: HW sample en + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: CTRL_DATE + description: version + addressOffset: 1020 + size: 32 + resetValue: 35676736 + fields: + - name: DATE + description: version + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: ASSIST_DEBUG + description: Debug Assist + groupName: ASSIST_DEBUG + baseAddress: 1611407360 + addressBlock: + - offset: 0 + size: 128 + usage: registers + interrupt: + - name: ASSIST_DEBUG + value: 11 + registers: + - register: + name: CORE_0_MONTR_ENA + description: core0 monitor enable configuration register + addressOffset: 0 + size: 32 + fields: + - name: CORE_0_AREA_DRAM0_0_RD_ENA + description: Core0 dram0 area0 read monitor enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_0_WR_ENA + description: Core0 dram0 area0 write monitor enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_1_RD_ENA + description: Core0 dram0 area1 read monitor enable + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_1_WR_ENA + description: Core0 dram0 area1 write monitor enable + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_0_RD_ENA + description: Core0 PIF area0 read monitor enable + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_0_WR_ENA + description: Core0 PIF area0 write monitor enable + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_1_RD_ENA + description: Core0 PIF area1 read monitor enable + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_1_WR_ENA + description: Core0 PIF area1 write monitor enable + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CORE_0_SP_SPILL_MIN_ENA + description: Core0 stackpoint underflow monitor enable + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CORE_0_SP_SPILL_MAX_ENA + description: Core0 stackpoint overflow monitor enable + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CORE_0_IRAM0_EXCEPTION_MONITOR_ENA + description: IBUS busy monitor enable + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CORE_0_DRAM0_EXCEPTION_MONITOR_ENA + description: DBUS busy monitor enbale + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_INTR_RAW + description: core0 monitor interrupt status register + addressOffset: 4 + size: 32 + fields: + - name: CORE_0_AREA_DRAM0_0_RD_RAW + description: Core0 dram0 area0 read monitor interrupt status + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_DRAM0_0_WR_RAW + description: Core0 dram0 area0 write monitor interrupt status + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_DRAM0_1_RD_RAW + description: Core0 dram0 area1 read monitor interrupt status + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_DRAM0_1_WR_RAW + description: Core0 dram0 area1 write monitor interrupt status + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_PIF_0_RD_RAW + description: Core0 PIF area0 read monitor interrupt status + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_PIF_0_WR_RAW + description: Core0 PIF area0 write monitor interrupt status + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_PIF_1_RD_RAW + description: Core0 PIF area1 read monitor interrupt status + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_PIF_1_WR_RAW + description: Core0 PIF area1 write monitor interrupt status + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: CORE_0_SP_SPILL_MIN_RAW + description: Core0 stackpoint underflow monitor interrupt status + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: CORE_0_SP_SPILL_MAX_RAW + description: Core0 stackpoint overflow monitor interrupt status + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: CORE_0_IRAM0_EXCEPTION_MONITOR_RAW + description: IBUS busy monitor interrupt status + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: CORE_0_DRAM0_EXCEPTION_MONITOR_RAW + description: DBUS busy monitor initerrupt status + bitOffset: 11 + bitWidth: 1 + access: read-only + - register: + name: CORE_0_INTR_ENA + description: core0 monitor interrupt enable register + addressOffset: 8 + size: 32 + fields: + - name: CORE_0_AREA_DRAM0_0_RD_INTR_ENA + description: Core0 dram0 area0 read monitor interrupt enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_0_WR_INTR_ENA + description: Core0 dram0 area0 write monitor interrupt enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_1_RD_INTR_ENA + description: Core0 dram0 area1 read monitor interrupt enable + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_1_WR_INTR_ENA + description: Core0 dram0 area1 write monitor interrupt enable + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_0_RD_INTR_ENA + description: Core0 PIF area0 read monitor interrupt enable + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_0_WR_INTR_ENA + description: Core0 PIF area0 write monitor interrupt enable + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_1_RD_INTR_ENA + description: Core0 PIF area1 read monitor interrupt enable + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_1_WR_INTR_ENA + description: Core0 PIF area1 write monitor interrupt enable + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CORE_0_SP_SPILL_MIN_INTR_ENA + description: Core0 stackpoint underflow monitor interrupt enable + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CORE_0_SP_SPILL_MAX_INTR_ENA + description: Core0 stackpoint overflow monitor interrupt enable + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA + description: IBUS busy monitor interrupt enable + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA + description: DBUS busy monitor interrupt enbale + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_INTR_CLR + description: core0 monitor interrupt clr register + addressOffset: 12 + size: 32 + fields: + - name: CORE_0_AREA_DRAM0_0_RD_CLR + description: Core0 dram0 area0 read monitor interrupt clr + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CORE_0_AREA_DRAM0_0_WR_CLR + description: Core0 dram0 area0 write monitor interrupt clr + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CORE_0_AREA_DRAM0_1_RD_CLR + description: Core0 dram0 area1 read monitor interrupt clr + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CORE_0_AREA_DRAM0_1_WR_CLR + description: Core0 dram0 area1 write monitor interrupt clr + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: CORE_0_AREA_PIF_0_RD_CLR + description: Core0 PIF area0 read monitor interrupt clr + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: CORE_0_AREA_PIF_0_WR_CLR + description: Core0 PIF area0 write monitor interrupt clr + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CORE_0_AREA_PIF_1_RD_CLR + description: Core0 PIF area1 read monitor interrupt clr + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: CORE_0_AREA_PIF_1_WR_CLR + description: Core0 PIF area1 write monitor interrupt clr + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: CORE_0_SP_SPILL_MIN_CLR + description: Core0 stackpoint underflow monitor interrupt clr + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: CORE_0_SP_SPILL_MAX_CLR + description: Core0 stackpoint overflow monitor interrupt clr + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: CORE_0_IRAM0_EXCEPTION_MONITOR_CLR + description: IBUS busy monitor interrupt clr + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: CORE_0_DRAM0_EXCEPTION_MONITOR_CLR + description: DBUS busy monitor interrupt clr + bitOffset: 11 + bitWidth: 1 + access: write-only + - register: + name: CORE_0_AREA_DRAM0_0_MIN + description: core0 dram0 region0 addr configuration register + addressOffset: 16 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_AREA_DRAM0_0_MIN + description: Core0 dram0 region0 start addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_DRAM0_0_MAX + description: core0 dram0 region0 addr configuration register + addressOffset: 20 + size: 32 + fields: + - name: CORE_0_AREA_DRAM0_0_MAX + description: Core0 dram0 region0 end addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_DRAM0_1_MIN + description: core0 dram0 region1 addr configuration register + addressOffset: 24 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_AREA_DRAM0_1_MIN + description: Core0 dram0 region1 start addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_DRAM0_1_MAX + description: core0 dram0 region1 addr configuration register + addressOffset: 28 + size: 32 + fields: + - name: CORE_0_AREA_DRAM0_1_MAX + description: Core0 dram0 region1 end addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_PIF_0_MIN + description: core0 PIF region0 addr configuration register + addressOffset: 32 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_AREA_PIF_0_MIN + description: Core0 PIF region0 start addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_PIF_0_MAX + description: core0 PIF region0 addr configuration register + addressOffset: 36 + size: 32 + fields: + - name: CORE_0_AREA_PIF_0_MAX + description: Core0 PIF region0 end addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_PIF_1_MIN + description: core0 PIF region1 addr configuration register + addressOffset: 40 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_AREA_PIF_1_MIN + description: Core0 PIF region1 start addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_PIF_1_MAX + description: core0 PIF region1 addr configuration register + addressOffset: 44 + size: 32 + fields: + - name: CORE_0_AREA_PIF_1_MAX + description: Core0 PIF region1 end addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_PC + description: core0 area pc status register + addressOffset: 48 + size: 32 + fields: + - name: CORE_0_AREA_PC + description: the stackpointer when first touch region monitor interrupt + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_AREA_SP + description: core0 area sp status register + addressOffset: 52 + size: 32 + fields: + - name: CORE_0_AREA_SP + description: the PC when first touch region monitor interrupt + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_SP_MIN + description: stack min value + addressOffset: 56 + size: 32 + fields: + - name: CORE_0_SP_MIN + description: core0 sp region configuration regsiter + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_SP_MAX + description: stack max value + addressOffset: 60 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_SP_MAX + description: core0 sp pc status register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_SP_PC + description: stack monitor pc status register + addressOffset: 64 + size: 32 + fields: + - name: CORE_0_SP_PC + description: This regsiter stores the PC when trigger stack monitor. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_RCD_EN + description: record enable configuration register + addressOffset: 68 + size: 32 + fields: + - name: CORE_0_RCD_RECORDEN + description: Set 1 to enable record PC + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_RCD_PDEBUGEN + description: "Set 1 to enable cpu pdebug function, must set this bit can get cpu PC" + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_RCD_PDEBUGPC + description: record status regsiter + addressOffset: 72 + size: 32 + fields: + - name: CORE_0_RCD_PDEBUGPC + description: recorded PC + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_RCD_PDEBUGSP + description: record status regsiter + addressOffset: 76 + size: 32 + fields: + - name: CORE_0_RCD_PDEBUGSP + description: recorded sp + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_IRAM0_EXCEPTION_MONITOR_0 + description: exception monitor status register0 + addressOffset: 80 + size: 32 + fields: + - name: CORE_0_IRAM0_RECORDING_ADDR_0 + description: reg_core_0_iram0_recording_addr_0 + bitOffset: 0 + bitWidth: 24 + access: read-only + - name: CORE_0_IRAM0_RECORDING_WR_0 + description: reg_core_0_iram0_recording_wr_0 + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: CORE_0_IRAM0_RECORDING_LOADSTORE_0 + description: reg_core_0_iram0_recording_loadstore_0 + bitOffset: 25 + bitWidth: 1 + access: read-only + - register: + name: CORE_0_IRAM0_EXCEPTION_MONITOR_1 + description: exception monitor status register1 + addressOffset: 84 + size: 32 + fields: + - name: CORE_0_IRAM0_RECORDING_ADDR_1 + description: reg_core_0_iram0_recording_addr_1 + bitOffset: 0 + bitWidth: 24 + access: read-only + - name: CORE_0_IRAM0_RECORDING_WR_1 + description: reg_core_0_iram0_recording_wr_1 + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: CORE_0_IRAM0_RECORDING_LOADSTORE_1 + description: reg_core_0_iram0_recording_loadstore_1 + bitOffset: 25 + bitWidth: 1 + access: read-only + - register: + name: CORE_0_DRAM0_EXCEPTION_MONITOR_0 + description: exception monitor status register2 + addressOffset: 88 + size: 32 + fields: + - name: CORE_0_DRAM0_RECORDING_ADDR_0 + description: reg_core_0_dram0_recording_addr_0 + bitOffset: 0 + bitWidth: 24 + access: read-only + - name: CORE_0_DRAM0_RECORDING_WR_0 + description: reg_core_0_dram0_recording_wr_0 + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: CORE_0_DRAM0_RECORDING_BYTEEN_0 + description: reg_core_0_dram0_recording_byteen_0 + bitOffset: 25 + bitWidth: 4 + access: read-only + - register: + name: CORE_0_DRAM0_EXCEPTION_MONITOR_1 + description: exception monitor status register3 + addressOffset: 92 + size: 32 + fields: + - name: CORE_0_DRAM0_RECORDING_PC_0 + description: reg_core_0_dram0_recording_pc_0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_DRAM0_EXCEPTION_MONITOR_2 + description: exception monitor status register4 + addressOffset: 96 + size: 32 + fields: + - name: CORE_0_DRAM0_RECORDING_ADDR_1 + description: reg_core_0_dram0_recording_addr_1 + bitOffset: 0 + bitWidth: 24 + access: read-only + - name: CORE_0_DRAM0_RECORDING_WR_1 + description: reg_core_0_dram0_recording_wr_1 + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: CORE_0_DRAM0_RECORDING_BYTEEN_1 + description: reg_core_0_dram0_recording_byteen_1 + bitOffset: 25 + bitWidth: 4 + access: read-only + - register: + name: CORE_0_DRAM0_EXCEPTION_MONITOR_3 + description: exception monitor status register5 + addressOffset: 100 + size: 32 + fields: + - name: CORE_0_DRAM0_RECORDING_PC_1 + description: reg_core_0_dram0_recording_pc_1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 + description: exception monitor status register6 + addressOffset: 104 + size: 32 + fields: + - name: CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 + description: reg_core_x_iram0_dram0_limit_cycle_0 + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 + description: exception monitor status register7 + addressOffset: 108 + size: 32 + fields: + - name: CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 + description: reg_core_x_iram0_dram0_limit_cycle_1 + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: C0RE_0_LASTPC_BEFORE_EXCEPTION + description: cpu status register + addressOffset: 112 + size: 32 + fields: + - name: CORE_0_LASTPC_BEFORE_EXC + description: "cpu's lastpc before exception" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: C0RE_0_DEBUG_MODE + description: cpu status register + addressOffset: 116 + size: 32 + fields: + - name: CORE_0_DEBUG_MODE + description: "cpu debug mode status, 1 means cpu enter debug mode." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_0_DEBUG_MODULE_ACTIVE + description: cpu debug_module active status + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: CLOCK_GATE + description: clock register + addressOffset: 120 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: Set 1 force on the clock gate + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: version register + addressOffset: 1020 + size: 32 + resetValue: 34640176 + fields: + - name: ASSIST_DEBUG_DATE + description: version register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: DMA + description: DMA (Direct Memory Access) Controller + groupName: DMA + baseAddress: 1611137024 + addressBlock: + - offset: 0 + size: 420 + usage: registers + interrupt: + - name: DMA_IN_CH0 + value: 53 + - name: DMA_IN_CH1 + value: 54 + - name: DMA_IN_CH2 + value: 55 + - name: DMA_OUT_CH0 + value: 56 + - name: DMA_OUT_CH1 + value: 57 + - name: DMA_OUT_CH2 + value: 58 + registers: + - cluster: + dim: 3 + dimIncrement: 16 + dimIndex: "0,1,2" + name: IN_INT_CH%s + description: "Cluster IN_INT_CH%s, containing IN_INT_RAW_CH?, IN_INT_ST_CH?, IN_INT_ENA_CH?, IN_INT_CLR_CH?" + addressOffset: 0 + children: + - register: + name: RAW + description: Raw status interrupt of channel 0 + addressOffset: 0 + size: 32 + fields: + - name: IN_DONE + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF + description: The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR + description: The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY + description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF + description: This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF + description: This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: ST + description: Masked interrupt of channel 0 + addressOffset: 4 + size: 32 + fields: + - name: IN_DONE + description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: IN_SUC_EOF + description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: IN_ERR_EOF + description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: IN_DSCR_ERR + description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: IN_DSCR_EMPTY + description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: INFIFO_OVF + description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: INFIFO_UDF + description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: ENA + description: Interrupt enable bits of channel 0 + addressOffset: 8 + size: 32 + fields: + - name: IN_DONE + description: The interrupt enable bit for the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF + description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF + description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR + description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY + description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF + description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF + description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: CLR + description: Interrupt clear bits of channel 0 + addressOffset: 12 + size: 32 + fields: + - name: IN_DONE + description: Set this bit to clear the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: IN_SUC_EOF + description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: IN_ERR_EOF + description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: IN_DSCR_ERR + description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: IN_DSCR_EMPTY + description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: INFIFO_OVF + description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: INFIFO_UDF + description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - cluster: + dim: 3 + dimIncrement: 16 + dimIndex: "0,1,2" + name: OUT_INT_CH%s + description: "Cluster OUT_INT_CH%s, containing OUT_INT_RAW_CH?, OUT_INT_ST_CH?, OUT_INT_ENA_CH?, OUT_INT_CLR_CH?" + addressOffset: 48 + children: + - register: + name: RAW + description: Raw status interrupt of channel 0 + addressOffset: 0 + size: 32 + fields: + - name: OUT_DONE + description: The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_EOF + description: The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR + description: The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel 0. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF + description: The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF + description: This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF + description: This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: ST + description: Masked interrupt of channel 0 + addressOffset: 4 + size: 32 + fields: + - name: OUT_DONE + description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUT_EOF + description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: OUT_DSCR_ERR + description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: OUT_TOTAL_EOF + description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: OUTFIFO_OVF + description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: OUTFIFO_UDF + description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: ENA + description: Interrupt enable bits of channel 0 + addressOffset: 8 + size: 32 + fields: + - name: OUT_DONE + description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_EOF + description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR + description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF + description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF + description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF + description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: CLR + description: Interrupt clear bits of channel 0 + addressOffset: 12 + size: 32 + fields: + - name: OUT_DONE + description: Set this bit to clear the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: OUT_EOF + description: Set this bit to clear the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: OUT_DSCR_ERR + description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: OUT_TOTAL_EOF + description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: OUTFIFO_OVF + description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: OUTFIFO_UDF + description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: AHB_TEST + description: reserved + addressOffset: 96 + size: 32 + fields: + - name: AHB_TESTMODE + description: reserved + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: AHB_TESTADDR + description: reserved + bitOffset: 4 + bitWidth: 2 + access: read-write + - register: + name: MISC_CONF + description: MISC register + addressOffset: 100 + size: 32 + fields: + - name: AHBM_RST_INTER + description: Set this bit then clear this bit to reset the internal ahb FSM. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ARB_PRI_DIS + description: Set this bit to disable priority arbitration function. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers." + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 104 + size: 32 + resetValue: 35660368 + fields: + - name: DATE + description: register version. + bitOffset: 0 + bitWidth: 32 + access: read-write + - cluster: + dim: 3 + dimIncrement: 192 + dimIndex: "0,1,2" + name: CH%s + description: "Cluster CH%s, containing IN_CONF0_CH?, IN_CONF1_CH?, INFIFO_STATUS_CH?, IN_POP_CH?, IN_LINK_CH?, IN_STATE_CH?, IN_SUC_EOF_DES_ADDR_CH?, IN_ERR_EOF_DES_ADDR_CH?, IN_DSCR_CH?, IN_DSCR_BF0_CH?, IN_DSCR_BF1_CH?, IN_PRI_CH?, IN_PERI_SEL_CH?, OUT_CONF0_CH?, OUT_CONF1_CH?, OUTFIFO_STATUS_CH?, OUT_PUSH_CH?, OUT_LINK_CH?, OUT_STATE_CH?, OUT_EOF_DES_ADDR_CH?, OUT_EOF_BFR_DES_ADDR_CH?, OUT_DSCR_CH?, OUT_DSCR_BF0_CH?, OUT_DSCR_BF1_CH?, OUT_PRI_CH?, OUT_PERI_SEL_CH?" + addressOffset: 112 + children: + - register: + name: IN_CONF0 + description: Configure 0 register of Rx channel 0 + addressOffset: 0 + size: 32 + fields: + - name: IN_RST + description: This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_LOOP_TEST + description: reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: INDSCR_BURST_EN + description: Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DATA_BURST_EN + description: Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MEM_TRANS_EN + description: Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IN_ETM_EN + description: "Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task." + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: IN_CONF1 + description: Configure 1 register of Rx channel 0 + addressOffset: 4 + size: 32 + fields: + - name: IN_CHECK_OWNER + description: Set this bit to enable checking the owner attribute of the link descriptor. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: INFIFO_STATUS + description: Receive FIFO status of Rx channel 0 + addressOffset: 8 + size: 32 + resetValue: 125829123 + fields: + - name: INFIFO_FULL + description: L1 Rx FIFO full signal for Rx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: INFIFO_EMPTY + description: L1 Rx FIFO empty signal for Rx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: INFIFO_CNT + description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + bitOffset: 2 + bitWidth: 6 + access: read-only + - name: IN_REMAIN_UNDER_1B + description: reserved + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: IN_REMAIN_UNDER_2B + description: reserved + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: IN_REMAIN_UNDER_3B + description: reserved + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: IN_REMAIN_UNDER_4B + description: reserved + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: IN_BUF_HUNGRY + description: reserved + bitOffset: 27 + bitWidth: 1 + access: read-only + - register: + name: IN_POP + description: Pop control register of Rx channel 0 + addressOffset: 12 + size: 32 + resetValue: 2048 + fields: + - name: INFIFO_RDATA + description: This register stores the data popping from DMA FIFO. + bitOffset: 0 + bitWidth: 12 + access: read-only + - name: INFIFO_POP + description: Set this bit to pop data from DMA FIFO. + bitOffset: 12 + bitWidth: 1 + access: write-only + - register: + name: IN_LINK + description: Link descriptor configure and control register of Rx channel 0 + addressOffset: 16 + size: 32 + resetValue: 17825792 + fields: + - name: INLINK_ADDR + description: "This register stores the 20 least significant bits of the first inlink descriptor's address." + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: INLINK_AUTO_RET + description: "Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: INLINK_STOP + description: Set this bit to stop dealing with the inlink descriptors. + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: INLINK_START + description: Set this bit to start dealing with the inlink descriptors. + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: INLINK_RESTART + description: Set this bit to mount a new inlink descriptor. + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: INLINK_PARK + description: "1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working." + bitOffset: 24 + bitWidth: 1 + access: read-only + - register: + name: IN_STATE + description: Receive status of Rx channel 0 + addressOffset: 20 + size: 32 + fields: + - name: INLINK_DSCR_ADDR + description: "This register stores the current inlink descriptor's address." + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: IN_DSCR_STATE + description: reserved + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: IN_STATE + description: reserved + bitOffset: 20 + bitWidth: 3 + access: read-only + - register: + name: IN_SUC_EOF_DES_ADDR + description: Inlink descriptor address when EOF occurs of Rx channel 0 + addressOffset: 24 + size: 32 + fields: + - name: IN_SUC_EOF_DES_ADDR + description: This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_ERR_EOF_DES_ADDR + description: Inlink descriptor address when errors occur of Rx channel 0 + addressOffset: 28 + size: 32 + fields: + - name: IN_ERR_EOF_DES_ADDR + description: This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR + description: Current inlink descriptor address of Rx channel 0 + addressOffset: 32 + size: 32 + fields: + - name: INLINK_DSCR + description: The address of the current inlink descriptor x. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_BF0 + description: The last inlink descriptor address of Rx channel 0 + addressOffset: 36 + size: 32 + fields: + - name: INLINK_DSCR_BF0 + description: The address of the last inlink descriptor x-1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_BF1 + description: The second-to-last inlink descriptor address of Rx channel 0 + addressOffset: 40 + size: 32 + fields: + - name: INLINK_DSCR_BF1 + description: The address of the second-to-last inlink descriptor x-2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_PRI + description: Priority register of Rx channel 0 + addressOffset: 44 + size: 32 + fields: + - name: RX_PRI + description: The priority of Rx channel 0. The larger of the value the higher of the priority. + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: IN_PERI_SEL + description: Peripheral selection of Rx channel 0 + addressOffset: 48 + size: 32 + resetValue: 63 + fields: + - name: PERI_IN_SEL + description: "This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: Dummy. 2: UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. 10~15: Dummy" + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: OUT_CONF0 + description: Configure 0 register of Tx channel 1 + addressOffset: 96 + size: 32 + resetValue: 8 + fields: + - name: OUT_RST + description: This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_LOOP_TEST + description: reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_AUTO_WRBACK + description: Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_EOF_MODE + description: "EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTDSCR_BURST_EN + description: Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUT_DATA_BURST_EN + description: Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUT_ETM_EN + description: "Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm task." + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: OUT_CONF1 + description: Configure 1 register of Tx channel 0 + addressOffset: 100 + size: 32 + fields: + - name: OUT_CHECK_OWNER + description: Set this bit to enable checking the owner attribute of the link descriptor. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: OUTFIFO_STATUS + description: Transmit FIFO status of Tx channel 0 + addressOffset: 104 + size: 32 + resetValue: 125829122 + fields: + - name: OUTFIFO_FULL + description: L1 Tx FIFO full signal for Tx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY + description: L1 Tx FIFO empty signal for Tx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: OUTFIFO_CNT + description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + bitOffset: 2 + bitWidth: 6 + access: read-only + - name: OUT_REMAIN_UNDER_1B + description: reserved + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: OUT_REMAIN_UNDER_2B + description: reserved + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: OUT_REMAIN_UNDER_3B + description: reserved + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: OUT_REMAIN_UNDER_4B + description: reserved + bitOffset: 26 + bitWidth: 1 + access: read-only + - register: + name: OUT_PUSH + description: Push control register of Rx channel 0 + addressOffset: 108 + size: 32 + fields: + - name: OUTFIFO_WDATA + description: This register stores the data that need to be pushed into DMA FIFO. + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: OUTFIFO_PUSH + description: Set this bit to push data into DMA FIFO. + bitOffset: 9 + bitWidth: 1 + access: write-only + - register: + name: OUT_LINK + description: Link descriptor configure and control register of Tx channel 0 + addressOffset: 112 + size: 32 + resetValue: 8388608 + fields: + - name: OUTLINK_ADDR + description: "This register stores the 20 least significant bits of the first outlink descriptor's address." + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: OUTLINK_STOP + description: Set this bit to stop dealing with the outlink descriptors. + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: OUTLINK_START + description: Set this bit to start dealing with the outlink descriptors. + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: OUTLINK_RESTART + description: Set this bit to restart a new outlink from the last address. + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: OUTLINK_PARK + description: "1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working." + bitOffset: 23 + bitWidth: 1 + access: read-only + - register: + name: OUT_STATE + description: Transmit status of Tx channel 0 + addressOffset: 116 + size: 32 + fields: + - name: OUTLINK_DSCR_ADDR + description: "This register stores the current outlink descriptor's address." + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: OUT_DSCR_STATE + description: reserved + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: OUT_STATE + description: reserved + bitOffset: 20 + bitWidth: 3 + access: read-only + - register: + name: OUT_EOF_DES_ADDR + description: Outlink descriptor address when EOF occurs of Tx channel 0 + addressOffset: 120 + size: 32 + fields: + - name: OUT_EOF_DES_ADDR + description: This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_EOF_BFR_DES_ADDR + description: The last outlink descriptor address when EOF occurs of Tx channel 0 + addressOffset: 124 + size: 32 + fields: + - name: OUT_EOF_BFR_DES_ADDR + description: This register stores the address of the outlink descriptor before the last outlink descriptor. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR + description: Current inlink descriptor address of Tx channel 0 + addressOffset: 128 + size: 32 + fields: + - name: OUTLINK_DSCR + description: The address of the current outlink descriptor y. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_BF0 + description: The last inlink descriptor address of Tx channel 0 + addressOffset: 132 + size: 32 + fields: + - name: OUTLINK_DSCR_BF0 + description: The address of the last outlink descriptor y-1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_BF1 + description: The second-to-last inlink descriptor address of Tx channel 0 + addressOffset: 136 + size: 32 + fields: + - name: OUTLINK_DSCR_BF1 + description: The address of the second-to-last inlink descriptor x-2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_PRI + description: Priority register of Tx channel 0. + addressOffset: 140 + size: 32 + fields: + - name: TX_PRI + description: The priority of Tx channel 0. The larger of the value the higher of the priority. + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: OUT_PERI_SEL + description: Peripheral selection of Tx channel 0 + addressOffset: 144 + size: 32 + resetValue: 63 + fields: + - name: PERI_OUT_SEL + description: "This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: Dummy. 2: UHCI0. 3: I2S0. 4: Dummy. 5: Dummy. 6: AES. 7: SHA. 8: ADC_DAC. 9: Parallel_IO. 10~15: Dummy" + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: DS + description: Digital Signature + groupName: DS + baseAddress: 1611186176 + addressBlock: + - offset: 0 + size: 2652 + usage: registers + registers: + - register: + dim: 128 + dimIncrement: 4 + name: "Y_MEM[%s]" + description: memory that stores Y + addressOffset: 0 + size: 32 + - register: + dim: 128 + dimIncrement: 4 + name: "M_MEM[%s]" + description: memory that stores M + addressOffset: 512 + size: 32 + - register: + dim: 128 + dimIncrement: 4 + name: "RB_MEM[%s]" + description: memory that stores Rb + addressOffset: 1024 + size: 32 + - register: + dim: 12 + dimIncrement: 4 + name: "BOX_MEM[%s]" + description: memory that stores BOX + addressOffset: 1536 + size: 32 + - register: + dim: 4 + dimIncrement: 4 + name: "IV_MEM[%s]" + description: memory that stores IV + addressOffset: 1584 + size: 32 + - register: + dim: 128 + dimIncrement: 4 + name: "X_MEM[%s]" + description: memory that stores X + addressOffset: 2048 + size: 32 + - register: + dim: 128 + dimIncrement: 4 + name: "Z_MEM[%s]" + description: memory that stores Z + addressOffset: 2560 + size: 32 + - register: + name: SET_START + description: DS start control register + addressOffset: 3584 + size: 32 + fields: + - name: SET_START + description: set this bit to start DS operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_CONTINUE + description: DS continue control register + addressOffset: 3588 + size: 32 + fields: + - name: SET_CONTINUE + description: set this bit to continue DS operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_FINISH + description: DS finish control register + addressOffset: 3592 + size: 32 + fields: + - name: SET_FINISH + description: Set this bit to finish DS process. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: QUERY_BUSY + description: DS query busy register + addressOffset: 3596 + size: 32 + fields: + - name: QUERY_BUSY + description: "digital signature state. 1'b0: idle, 1'b1: busy" + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: QUERY_KEY_WRONG + description: DS query key-wrong counter register + addressOffset: 3600 + size: 32 + fields: + - name: QUERY_KEY_WRONG + description: digital signature key wrong counter + bitOffset: 0 + bitWidth: 4 + access: read-only + - register: + name: QUERY_CHECK + description: DS query check result register + addressOffset: 3604 + size: 32 + fields: + - name: MD_ERROR + description: "MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PADDING_BAD + description: "padding checkout result. 1'b0: a good padding, 1'b1: a bad padding" + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: DS version control register + addressOffset: 3616 + size: 32 + resetValue: 538969624 + fields: + - name: DATE + description: ds version information + bitOffset: 0 + bitWidth: 30 + access: read-write + - name: ECC + description: ECC (ECC Hardware Accelerator) + groupName: ECC + baseAddress: 1611182080 + addressBlock: + - offset: 0 + size: 120 + usage: registers + interrupt: + - name: ECC + value: 63 + registers: + - register: + name: MULT_INT_RAW + description: "ECC interrupt raw register, valid in level." + addressOffset: 12 + size: 32 + fields: + - name: CALC_DONE_INT_RAW + description: The raw interrupt status bit for the ecc_calc_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: MULT_INT_ST + description: ECC interrupt status register. + addressOffset: 16 + size: 32 + fields: + - name: CALC_DONE_INT_ST + description: The masked interrupt status bit for the ecc_calc_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: MULT_INT_ENA + description: ECC interrupt enable register. + addressOffset: 20 + size: 32 + fields: + - name: CALC_DONE_INT_ENA + description: The interrupt enable bit for the ecc_calc_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: MULT_INT_CLR + description: ECC interrupt clear register. + addressOffset: 24 + size: 32 + fields: + - name: CALC_DONE_INT_CLR + description: Set this bit to clear the ecc_calc_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: MULT_CONF + description: ECC configure register + addressOffset: 28 + size: 32 + resetValue: 2147483648 + fields: + - name: START + description: Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after the caculatrion is done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RESET + description: Write 1 to reset ECC Accelerator. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: KEY_LENGTH + description: "The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MOD_BASE + description: "The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve). 1: p(mod base of curve)" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: WORK_MODE + description: "The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: SECURITY_MODE + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: VERIFICATION_RESULT + description: "The verification result bit of ECC Accelerator, only valid when calculation is done." + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: CLK_EN + description: Write 1 to force on register clock gate. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: MEM_CLOCK_GATE_FORCE_ON + description: ECC memory clock gate force on register + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: MULT_DATE + description: Version control register + addressOffset: 252 + size: 32 + resetValue: 35680640 + fields: + - name: DATE + description: ECC mult version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + name: "K_MEM[%s]" + description: The memory that stores k. + addressOffset: 256 + size: 32 + - register: + dim: 8 + dimIncrement: 4 + name: "PX_MEM[%s]" + description: The memory that stores Px. + addressOffset: 288 + size: 32 + - register: + dim: 8 + dimIncrement: 4 + name: "PY_MEM[%s]" + description: The memory that stores Py. + addressOffset: 320 + size: 32 + - register: + dim: 8 + dimIncrement: 4 + name: QX_MEM%s + description: The memory that stores Qx + addressOffset: 352 + size: 32 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + name: QY_MEM%s + description: The memory that stores Qy + addressOffset: 384 + size: 32 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + name: QZ_MEM%s + description: The memory that stores Qz + addressOffset: 416 + size: 32 + access: read-write + - name: EFUSE + description: eFuse Controller + groupName: EFUSE + baseAddress: 1611335680 + addressBlock: + - offset: 0 + size: 464 + usage: registers + interrupt: + - name: EFUSE + value: 1 + registers: + - register: + name: PGM_DATA0 + description: Register 0 that stores data to be programmed. + addressOffset: 0 + size: 32 + fields: + - name: PGM_DATA_0 + description: Configures the 0th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA1 + description: Register 1 that stores data to be programmed. + addressOffset: 4 + size: 32 + fields: + - name: PGM_DATA_1 + description: Configures the 1st 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA2 + description: Register 2 that stores data to be programmed. + addressOffset: 8 + size: 32 + fields: + - name: PGM_DATA_2 + description: Configures the 2nd 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA3 + description: Register 3 that stores data to be programmed. + addressOffset: 12 + size: 32 + fields: + - name: PGM_DATA_3 + description: Configures the 3rd 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA4 + description: Register 4 that stores data to be programmed. + addressOffset: 16 + size: 32 + fields: + - name: PGM_DATA_4 + description: Configures the 4th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA5 + description: Register 5 that stores data to be programmed. + addressOffset: 20 + size: 32 + fields: + - name: PGM_DATA_5 + description: Configures the 5th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA6 + description: Register 6 that stores data to be programmed. + addressOffset: 24 + size: 32 + fields: + - name: PGM_DATA_6 + description: Configures the 6th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA7 + description: Register 7 that stores data to be programmed. + addressOffset: 28 + size: 32 + fields: + - name: PGM_DATA_7 + description: Configures the 7th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_CHECK_VALUE0 + description: Register 0 that stores the RS code to be programmed. + addressOffset: 32 + size: 32 + fields: + - name: PGM_RS_DATA_0 + description: Configures the 0th 32-bit RS code to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_CHECK_VALUE1 + description: Register 1 that stores the RS code to be programmed. + addressOffset: 36 + size: 32 + fields: + - name: PGM_RS_DATA_1 + description: Configures the 1st 32-bit RS code to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_CHECK_VALUE2 + description: Register 2 that stores the RS code to be programmed. + addressOffset: 40 + size: 32 + fields: + - name: PGM_RS_DATA_2 + description: Configures the 2nd 32-bit RS code to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RD_WR_DIS + description: BLOCK0 data register 0. + addressOffset: 44 + size: 32 + fields: + - name: WR_DIS + description: "Represents whether programming of individual eFuse memory bit is disabled or enabled. 1: Disabled. 0 Enabled." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_REPEAT_DATA0 + description: BLOCK0 data register 1. + addressOffset: 48 + size: 32 + fields: + - name: RD_DIS + description: "Represents whether reading of individual eFuse block(block4~block10) is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 0 + bitWidth: 7 + access: read-only + - name: RPT4_RESERVED0_4 + description: Reserved. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DIS_ICACHE + description: "Represents whether icache is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DIS_USB_JTAG + description: "Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: POWERGLITCH_EN + description: "Represents whether power glitch function is enabled. 1: enabled. 0: disabled." + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: DIS_USB_SERIAL_JTAG + description: "Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: DIS_FORCE_DOWNLOAD + description: "Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SPI_DOWNLOAD_MSPI_DIS + description: "Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: DIS_CAN + description: "Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: JTAG_SEL_ENABLE + description: "Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled." + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SOFT_DIS_JTAG + description: "Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled." + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: DIS_PAD_JTAG + description: "Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled." + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_MANUAL_ENCRYPT + description: "Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled." + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: USB_DREFH + description: "Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV." + bitOffset: 21 + bitWidth: 2 + access: read-only + - name: USB_DREFL + description: "Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV." + bitOffset: 23 + bitWidth: 2 + access: read-only + - name: USB_EXCHG_PINS + description: "Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged." + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: VDD_SPI_AS_GPIO + description: "Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned." + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED0_2 + description: Reserved. + bitOffset: 27 + bitWidth: 2 + access: read-only + - name: RPT4_RESERVED0_1 + description: Reserved. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED0_0 + description: Reserved. + bitOffset: 30 + bitWidth: 2 + access: read-only + - register: + name: RD_REPEAT_DATA1 + description: BLOCK0 data register 2. + addressOffset: 52 + size: 32 + fields: + - name: RPT4_RESERVED1_1 + description: Reserved. + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: WDT_DELAY_SEL + description: "Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected." + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: SPI_BOOT_CRYPT_CNT + description: "Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 1: enabled. Even number of 1: disabled." + bitOffset: 18 + bitWidth: 3 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE0 + description: "Represents whether revoking first secure boot key is enabled or disabled. 1: enabled. 0: disabled." + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE1 + description: "Represents whether revoking second secure boot key is enabled or disabled. 1: enabled. 0: disabled." + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE2 + description: "Represents whether revoking third secure boot key is enabled or disabled. 1: enabled. 0: disabled." + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: KEY_PURPOSE_0 + description: Represents the purpose of Key0. + bitOffset: 24 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_1 + description: Represents the purpose of Key1. + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_REPEAT_DATA2 + description: BLOCK0 data register 3. + addressOffset: 56 + size: 32 + resetValue: 786432 + fields: + - name: KEY_PURPOSE_2 + description: Represents the purpose of Key2. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_3 + description: Represents the purpose of Key3. + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_4 + description: Represents the purpose of Key4. + bitOffset: 8 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_5 + description: Represents the purpose of Key5. + bitOffset: 12 + bitWidth: 4 + access: read-only + - name: SEC_DPA_LEVEL + description: Represents the spa secure level by configuring the clock random divide mode. + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: ECDSA_FORCE_USE_HARDWARE_K + description: "Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used." + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: CRYPT_DPA_ENABLE + description: "Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled." + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_EN + description: "Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled." + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_AGGRESSIVE_REVOKE + description: "Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled." + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED2_0 + description: Reserved. + bitOffset: 22 + bitWidth: 6 + access: read-only + - name: FLASH_TPUW + description: "Represents the flash waiting time after power-up, in unit of ms. When the value less than 15, the waiting time is the programmed value. Otherwise, the waiting time is 2 times the programmed value." + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_REPEAT_DATA3 + description: BLOCK0 data register 4. + addressOffset: 60 + size: 32 + fields: + - name: DIS_DOWNLOAD_MODE + description: "Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DIS_DIRECT_BOOT + description: "Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: DIS_USB_PRINT + description: "Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED3_5 + description: Reserved. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + description: "Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ENABLE_SECURITY_DOWNLOAD + description: "Represents whether security download is enabled or disabled. 1: enabled. 0: disabled." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: UART_PRINT_CONTROL + description: "Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing." + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: FORCE_SEND_RESUME + description: "Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SECURE_VERSION + description: Represents the version used by ESP-IDF anti-rollback feature. + bitOffset: 9 + bitWidth: 16 + access: read-only + - name: SECURE_BOOT_DISABLE_FAST_WAKE + description: "Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled." + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: HYS_EN_PAD0 + description: "Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled." + bitOffset: 26 + bitWidth: 6 + access: read-only + - register: + name: RD_REPEAT_DATA4 + description: BLOCK0 data register 5. + addressOffset: 64 + size: 32 + fields: + - name: HYS_EN_PAD1 + description: "Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled." + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: RPT4_RESERVED4_1 + description: Reserved. + bitOffset: 22 + bitWidth: 2 + access: read-only + - name: RPT4_RESERVED4_0 + description: Reserved. + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: RD_MAC_SYS_0 + description: BLOCK1 data register $n. + addressOffset: 68 + size: 32 + fields: + - name: MAC_0 + description: Stores the low 32 bits of MAC address. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_MAC_SYS_1 + description: BLOCK1 data register $n. + addressOffset: 72 + size: 32 + fields: + - name: MAC_1 + description: Stores the high 16 bits of MAC address. + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: MAC_EXT + description: Stores the extended bits of MAC address. + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: RD_MAC_SYS_2 + description: BLOCK1 data register $n. + addressOffset: 76 + size: 32 + fields: + - name: RXIQ_VERSION + description: Stores RF Calibration data. RXIQ version. + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: RXIQ_0 + description: Stores RF Calibration data. RXIQ data 0. + bitOffset: 3 + bitWidth: 7 + access: read-only + - name: RXIQ_1 + description: Stores RF Calibration data. RXIQ data 1. + bitOffset: 10 + bitWidth: 7 + access: read-only + - name: ACTIVE_HP_DBIAS + description: Stores the PMU active hp dbias. + bitOffset: 17 + bitWidth: 5 + access: read-only + - name: ACTIVE_LP_DBIAS + description: Stores the PMU active lp dbias. + bitOffset: 22 + bitWidth: 5 + access: read-only + - name: DSLP_DBIAS + description: Stores the PMU sleep dbias. + bitOffset: 27 + bitWidth: 4 + access: read-only + - name: DBIAS_VOL_GAP_VALUE1 + description: Stores the low 1 bit of dbias_vol_gap. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: RD_MAC_SYS_3 + description: BLOCK1 data register $n. + addressOffset: 80 + size: 32 + fields: + - name: DBIAS_VOL_GAP_VALUE2 + description: Stores the high 3 bits of dbias_vol_gap. + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: DBIAS_VOL_GAP_SIGN + description: Stores the sign bit of dbias_vol_gap. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: MAC_RESERVED_2 + description: Reserved. + bitOffset: 4 + bitWidth: 14 + access: read-only + - name: WAFER_VERSION_MINOR + description: Stores the wafer version minor. + bitOffset: 18 + bitWidth: 3 + access: read-only + - name: WAFER_VERSION_MAJOR + description: Stores the wafer version major. + bitOffset: 21 + bitWidth: 2 + access: read-only + - name: DISABLE_WAFER_VERSION_MAJOR + description: Disables check of wafer version major. + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: FLASH_CAP + description: Stores the flash cap. + bitOffset: 24 + bitWidth: 3 + access: read-only + - name: FLASH_TEMP + description: Stores the flash temp. + bitOffset: 27 + bitWidth: 2 + access: read-only + - name: FLASH_VENDOR + description: Stores the flash vendor. + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: RD_MAC_SYS_4 + description: BLOCK1 data register $n. + addressOffset: 84 + size: 32 + fields: + - name: SYS_DATA_PART0_1 + description: Stores the first 32 bits of the zeroth part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_MAC_SYS_5 + description: BLOCK1 data register $n. + addressOffset: 88 + size: 32 + fields: + - name: SYS_DATA_PART0_2 + description: Stores the second 32 bits of the zeroth part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA0 + description: Register $n of BLOCK2 (system). + addressOffset: 92 + size: 32 + fields: + - name: SYS_DATA_PART1_0 + description: Stores the zeroth 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA1 + description: Register $n of BLOCK2 (system). + addressOffset: 96 + size: 32 + fields: + - name: SYS_DATA_PART1_1 + description: Stores the first 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA2 + description: Register $n of BLOCK2 (system). + addressOffset: 100 + size: 32 + fields: + - name: SYS_DATA_PART1_2 + description: Stores the second 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA3 + description: Register $n of BLOCK2 (system). + addressOffset: 104 + size: 32 + fields: + - name: SYS_DATA_PART1_3 + description: Stores the third 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA4 + description: Register $n of BLOCK2 (system). + addressOffset: 108 + size: 32 + fields: + - name: SYS_DATA_PART1_4 + description: Stores the fourth 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA5 + description: Register $n of BLOCK2 (system). + addressOffset: 112 + size: 32 + fields: + - name: SYS_DATA_PART1_5 + description: Stores the fifth 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA6 + description: Register $n of BLOCK2 (system). + addressOffset: 116 + size: 32 + fields: + - name: SYS_DATA_PART1_6 + description: Stores the sixth 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA7 + description: Register $n of BLOCK2 (system). + addressOffset: 120 + size: 32 + fields: + - name: SYS_DATA_PART1_7 + description: Stores the seventh 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA0 + description: Register $n of BLOCK3 (user). + addressOffset: 124 + size: 32 + fields: + - name: USR_DATA0 + description: Stores the zeroth 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA1 + description: Register $n of BLOCK3 (user). + addressOffset: 128 + size: 32 + fields: + - name: USR_DATA1 + description: Stores the first 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA2 + description: Register $n of BLOCK3 (user). + addressOffset: 132 + size: 32 + fields: + - name: USR_DATA2 + description: Stores the second 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA3 + description: Register $n of BLOCK3 (user). + addressOffset: 136 + size: 32 + fields: + - name: USR_DATA3 + description: Stores the third 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA4 + description: Register $n of BLOCK3 (user). + addressOffset: 140 + size: 32 + fields: + - name: USR_DATA4 + description: Stores the fourth 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA5 + description: Register $n of BLOCK3 (user). + addressOffset: 144 + size: 32 + fields: + - name: USR_DATA5 + description: Stores the fifth 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA6 + description: Register $n of BLOCK3 (user). + addressOffset: 148 + size: 32 + fields: + - name: USR_DATA6 + description: Stores the sixth 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA7 + description: Register $n of BLOCK3 (user). + addressOffset: 152 + size: 32 + fields: + - name: USR_DATA7 + description: Stores the seventh 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA0 + description: Register $n of BLOCK4 (KEY0). + addressOffset: 156 + size: 32 + fields: + - name: KEY0_DATA0 + description: Stores the zeroth 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA1 + description: Register $n of BLOCK4 (KEY0). + addressOffset: 160 + size: 32 + fields: + - name: KEY0_DATA1 + description: Stores the first 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA2 + description: Register $n of BLOCK4 (KEY0). + addressOffset: 164 + size: 32 + fields: + - name: KEY0_DATA2 + description: Stores the second 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA3 + description: Register $n of BLOCK4 (KEY0). + addressOffset: 168 + size: 32 + fields: + - name: KEY0_DATA3 + description: Stores the third 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA4 + description: Register $n of BLOCK4 (KEY0). + addressOffset: 172 + size: 32 + fields: + - name: KEY0_DATA4 + description: Stores the fourth 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA5 + description: Register $n of BLOCK4 (KEY0). + addressOffset: 176 + size: 32 + fields: + - name: KEY0_DATA5 + description: Stores the fifth 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA6 + description: Register $n of BLOCK4 (KEY0). + addressOffset: 180 + size: 32 + fields: + - name: KEY0_DATA6 + description: Stores the sixth 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA7 + description: Register $n of BLOCK4 (KEY0). + addressOffset: 184 + size: 32 + fields: + - name: KEY0_DATA7 + description: Stores the seventh 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA0 + description: Register $n of BLOCK5 (KEY1). + addressOffset: 188 + size: 32 + fields: + - name: KEY1_DATA0 + description: Stores the zeroth 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA1 + description: Register $n of BLOCK5 (KEY1). + addressOffset: 192 + size: 32 + fields: + - name: KEY1_DATA1 + description: Stores the first 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA2 + description: Register $n of BLOCK5 (KEY1). + addressOffset: 196 + size: 32 + fields: + - name: KEY1_DATA2 + description: Stores the second 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA3 + description: Register $n of BLOCK5 (KEY1). + addressOffset: 200 + size: 32 + fields: + - name: KEY1_DATA3 + description: Stores the third 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA4 + description: Register $n of BLOCK5 (KEY1). + addressOffset: 204 + size: 32 + fields: + - name: KEY1_DATA4 + description: Stores the fourth 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA5 + description: Register $n of BLOCK5 (KEY1). + addressOffset: 208 + size: 32 + fields: + - name: KEY1_DATA5 + description: Stores the fifth 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA6 + description: Register $n of BLOCK5 (KEY1). + addressOffset: 212 + size: 32 + fields: + - name: KEY1_DATA6 + description: Stores the sixth 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA7 + description: Register $n of BLOCK5 (KEY1). + addressOffset: 216 + size: 32 + fields: + - name: KEY1_DATA7 + description: Stores the seventh 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA0 + description: Register $n of BLOCK6 (KEY2). + addressOffset: 220 + size: 32 + fields: + - name: KEY2_DATA0 + description: Stores the zeroth 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA1 + description: Register $n of BLOCK6 (KEY2). + addressOffset: 224 + size: 32 + fields: + - name: KEY2_DATA1 + description: Stores the first 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA2 + description: Register $n of BLOCK6 (KEY2). + addressOffset: 228 + size: 32 + fields: + - name: KEY2_DATA2 + description: Stores the second 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA3 + description: Register $n of BLOCK6 (KEY2). + addressOffset: 232 + size: 32 + fields: + - name: KEY2_DATA3 + description: Stores the third 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA4 + description: Register $n of BLOCK6 (KEY2). + addressOffset: 236 + size: 32 + fields: + - name: KEY2_DATA4 + description: Stores the fourth 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA5 + description: Register $n of BLOCK6 (KEY2). + addressOffset: 240 + size: 32 + fields: + - name: KEY2_DATA5 + description: Stores the fifth 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA6 + description: Register $n of BLOCK6 (KEY2). + addressOffset: 244 + size: 32 + fields: + - name: KEY2_DATA6 + description: Stores the sixth 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA7 + description: Register $n of BLOCK6 (KEY2). + addressOffset: 248 + size: 32 + fields: + - name: KEY2_DATA7 + description: Stores the seventh 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA0 + description: Register $n of BLOCK7 (KEY3). + addressOffset: 252 + size: 32 + fields: + - name: KEY3_DATA0 + description: Stores the zeroth 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA1 + description: Register $n of BLOCK7 (KEY3). + addressOffset: 256 + size: 32 + fields: + - name: KEY3_DATA1 + description: Stores the first 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA2 + description: Register $n of BLOCK7 (KEY3). + addressOffset: 260 + size: 32 + fields: + - name: KEY3_DATA2 + description: Stores the second 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA3 + description: Register $n of BLOCK7 (KEY3). + addressOffset: 264 + size: 32 + fields: + - name: KEY3_DATA3 + description: Stores the third 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA4 + description: Register $n of BLOCK7 (KEY3). + addressOffset: 268 + size: 32 + fields: + - name: KEY3_DATA4 + description: Stores the fourth 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA5 + description: Register $n of BLOCK7 (KEY3). + addressOffset: 272 + size: 32 + fields: + - name: KEY3_DATA5 + description: Stores the fifth 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA6 + description: Register $n of BLOCK7 (KEY3). + addressOffset: 276 + size: 32 + fields: + - name: KEY3_DATA6 + description: Stores the sixth 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA7 + description: Register $n of BLOCK7 (KEY3). + addressOffset: 280 + size: 32 + fields: + - name: KEY3_DATA7 + description: Stores the seventh 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA0 + description: Register $n of BLOCK8 (KEY4). + addressOffset: 284 + size: 32 + fields: + - name: KEY4_DATA0 + description: Stores the zeroth 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA1 + description: Register $n of BLOCK8 (KEY4). + addressOffset: 288 + size: 32 + fields: + - name: KEY4_DATA1 + description: Stores the first 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA2 + description: Register $n of BLOCK8 (KEY4). + addressOffset: 292 + size: 32 + fields: + - name: KEY4_DATA2 + description: Stores the second 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA3 + description: Register $n of BLOCK8 (KEY4). + addressOffset: 296 + size: 32 + fields: + - name: KEY4_DATA3 + description: Stores the third 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA4 + description: Register $n of BLOCK8 (KEY4). + addressOffset: 300 + size: 32 + fields: + - name: KEY4_DATA4 + description: Stores the fourth 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA5 + description: Register $n of BLOCK8 (KEY4). + addressOffset: 304 + size: 32 + fields: + - name: KEY4_DATA5 + description: Stores the fifth 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA6 + description: Register $n of BLOCK8 (KEY4). + addressOffset: 308 + size: 32 + fields: + - name: KEY4_DATA6 + description: Stores the sixth 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA7 + description: Register $n of BLOCK8 (KEY4). + addressOffset: 312 + size: 32 + fields: + - name: KEY4_DATA7 + description: Stores the seventh 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA0 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 316 + size: 32 + fields: + - name: KEY5_DATA0 + description: Stores the zeroth 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA1 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 320 + size: 32 + fields: + - name: KEY5_DATA1 + description: Stores the first 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA2 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 324 + size: 32 + fields: + - name: KEY5_DATA2 + description: Stores the second 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA3 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 328 + size: 32 + fields: + - name: KEY5_DATA3 + description: Stores the third 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA4 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 332 + size: 32 + fields: + - name: KEY5_DATA4 + description: Stores the fourth 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA5 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 336 + size: 32 + fields: + - name: KEY5_DATA5 + description: Stores the fifth 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA6 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 340 + size: 32 + fields: + - name: KEY5_DATA6 + description: Stores the sixth 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA7 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 344 + size: 32 + fields: + - name: KEY5_DATA7 + description: Stores the seventh 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA0 + description: Register $n of BLOCK10 (system). + addressOffset: 348 + size: 32 + fields: + - name: SYS_DATA_PART2_0 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA1 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 352 + size: 32 + fields: + - name: SYS_DATA_PART2_1 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA2 + description: Register $n of BLOCK10 (system). + addressOffset: 356 + size: 32 + fields: + - name: SYS_DATA_PART2_2 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA3 + description: Register $n of BLOCK10 (system). + addressOffset: 360 + size: 32 + fields: + - name: SYS_DATA_PART2_3 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA4 + description: Register $n of BLOCK10 (system). + addressOffset: 364 + size: 32 + fields: + - name: SYS_DATA_PART2_4 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA5 + description: Register $n of BLOCK10 (system). + addressOffset: 368 + size: 32 + fields: + - name: SYS_DATA_PART2_5 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA6 + description: Register $n of BLOCK10 (system). + addressOffset: 372 + size: 32 + fields: + - name: SYS_DATA_PART2_6 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA7 + description: Register $n of BLOCK10 (system). + addressOffset: 376 + size: 32 + fields: + - name: SYS_DATA_PART2_7 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_REPEAT_ERR0 + description: Programming error record register 0 of BLOCK0. + addressOffset: 380 + size: 32 + fields: + - name: RD_DIS_ERR + description: Indicates a programming error of RD_DIS. + bitOffset: 0 + bitWidth: 7 + access: read-only + - name: RPT4_RESERVED0_ERR_4 + description: Reserved. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DIS_ICACHE_ERR + description: Indicates a programming error of DIS_ICACHE. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DIS_USB_JTAG_ERR + description: Indicates a programming error of DIS_USB_JTAG. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: POWERGLITCH_EN_ERR + description: Indicates a programming error of POWERGLITCH_EN. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: DIS_USB_SERIAL_JTAG_ERR + description: Indicates a programming error of DIS_USB_DEVICE. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: DIS_FORCE_DOWNLOAD_ERR + description: Indicates a programming error of DIS_FORCE_DOWNLOAD. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SPI_DOWNLOAD_MSPI_DIS_ERR + description: Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: DIS_TWAI_ERR + description: Indicates a programming error of DIS_CAN. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: JTAG_SEL_ENABLE_ERR + description: Indicates a programming error of JTAG_SEL_ENABLE. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SOFT_DIS_JTAG_ERR + description: Indicates a programming error of SOFT_DIS_JTAG. + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: DIS_PAD_JTAG_ERR + description: Indicates a programming error of DIS_PAD_JTAG. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR + description: Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: USB_DREFH_ERR + description: Indicates a programming error of USB_DREFH. + bitOffset: 21 + bitWidth: 2 + access: read-only + - name: USB_DREFL_ERR + description: Indicates a programming error of USB_DREFL. + bitOffset: 23 + bitWidth: 2 + access: read-only + - name: USB_EXCHG_PINS_ERR + description: Indicates a programming error of USB_EXCHG_PINS. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: VDD_SPI_AS_GPIO_ERR + description: Indicates a programming error of VDD_SPI_AS_GPIO. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED0_ERR_2 + description: Reserved. + bitOffset: 27 + bitWidth: 2 + access: read-only + - name: RPT4_RESERVED0_ERR_1 + description: Reserved. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED0_ERR_0 + description: Reserved. + bitOffset: 30 + bitWidth: 2 + access: read-only + - register: + name: RD_REPEAT_ERR1 + description: Programming error record register 1 of BLOCK0. + addressOffset: 384 + size: 32 + fields: + - name: RPT4_RESERVED1_ERR_0 + description: Reserved. + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: WDT_DELAY_SEL_ERR + description: Indicates a programming error of WDT_DELAY_SEL. + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: SPI_BOOT_CRYPT_CNT_ERR + description: Indicates a programming error of SPI_BOOT_CRYPT_CNT. + bitOffset: 18 + bitWidth: 3 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE0_ERR + description: Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE1_ERR + description: Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE2_ERR + description: Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: KEY_PURPOSE_0_ERR + description: Indicates a programming error of KEY_PURPOSE_0. + bitOffset: 24 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_1_ERR + description: Indicates a programming error of KEY_PURPOSE_1. + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_REPEAT_ERR2 + description: Programming error record register 2 of BLOCK0. + addressOffset: 388 + size: 32 + fields: + - name: KEY_PURPOSE_2_ERR + description: Indicates a programming error of KEY_PURPOSE_2. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_3_ERR + description: Indicates a programming error of KEY_PURPOSE_3. + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_4_ERR + description: Indicates a programming error of KEY_PURPOSE_4. + bitOffset: 8 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_5_ERR + description: Indicates a programming error of KEY_PURPOSE_5. + bitOffset: 12 + bitWidth: 4 + access: read-only + - name: SEC_DPA_LEVEL_ERR + description: Indicates a programming error of SEC_DPA_LEVEL. + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: RPT4_RESERVED2_ERR_1 + description: Reserved. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: CRYPT_DPA_ENABLE_ERR + description: Indicates a programming error of CRYPT_DPA_ENABLE. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_EN_ERR + description: Indicates a programming error of SECURE_BOOT_EN. + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_AGGRESSIVE_REVOKE_ERR + description: Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED2_ERR_0 + description: Reserved. + bitOffset: 22 + bitWidth: 6 + access: read-only + - name: FLASH_TPUW_ERR + description: Indicates a programming error of FLASH_TPUW. + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_REPEAT_ERR3 + description: Programming error record register 3 of BLOCK0. + addressOffset: 392 + size: 32 + fields: + - name: DIS_DOWNLOAD_MODE_ERR + description: Indicates a programming error of DIS_DOWNLOAD_MODE. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DIS_DIRECT_BOOT_ERR + description: Indicates a programming error of DIS_DIRECT_BOOT. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: USB_PRINT_ERR + description: Indicates a programming error of UART_PRINT_CHANNEL. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED3_ERR_5 + description: Reserved. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR + description: Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ENABLE_SECURITY_DOWNLOAD_ERR + description: Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: UART_PRINT_CONTROL_ERR + description: Indicates a programming error of UART_PRINT_CONTROL. + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: FORCE_SEND_RESUME_ERR + description: Indicates a programming error of FORCE_SEND_RESUME. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SECURE_VERSION_ERR + description: Indicates a programming error of SECURE VERSION. + bitOffset: 9 + bitWidth: 16 + access: read-only + - name: SECURE_BOOT_DISABLE_FAST_WAKE_ERR + description: Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: HYS_EN_PAD0_ERR + description: Indicates a programming error of HYS_EN_PAD0. + bitOffset: 26 + bitWidth: 6 + access: read-only + - register: + name: RD_REPEAT_ERR4 + description: Programming error record register 4 of BLOCK0. + addressOffset: 396 + size: 32 + fields: + - name: HYS_EN_PAD1_ERR + description: Indicates a programming error of HYS_EN_PAD1. + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: RPT4_RESERVED4_ERR_1 + description: Reserved. + bitOffset: 22 + bitWidth: 2 + access: read-only + - name: RPT4_RESERVED4_ERR_0 + description: Reserved. + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: RD_RS_ERR0 + description: Programming error record register 0 of BLOCK1-10. + addressOffset: 448 + size: 32 + fields: + - name: MAC_SPI_8M_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: MAC_SPI_8M_FAIL + description: "0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SYS_PART1_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 4 + bitWidth: 3 + access: read-only + - name: SYS_PART1_FAIL + description: "0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: USR_DATA_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 8 + bitWidth: 3 + access: read-only + - name: USR_DATA_FAIL + description: "0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: KEY0_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 12 + bitWidth: 3 + access: read-only + - name: KEY0_FAIL + description: "0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6." + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: KEY1_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: KEY1_FAIL + description: "0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6." + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: KEY2_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 20 + bitWidth: 3 + access: read-only + - name: KEY2_FAIL + description: "0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6." + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: KEY3_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 24 + bitWidth: 3 + access: read-only + - name: KEY3_FAIL + description: "0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6." + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: KEY4_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 28 + bitWidth: 3 + access: read-only + - name: KEY4_FAIL + description: "0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: RD_RS_ERR1 + description: Programming error record register 1 of BLOCK1-10. + addressOffset: 452 + size: 32 + fields: + - name: KEY5_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: KEY5_FAIL + description: "0: Means no failure and that the data of key5 is reliable 1: Means that programming key5 failed and the number of error bytes is over 6." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SYS_PART2_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 4 + bitWidth: 3 + access: read-only + - name: SYS_PART2_FAIL + description: "0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 7 + bitWidth: 1 + access: read-only + - register: + name: CLK + description: eFuse clcok configuration register. + addressOffset: 456 + size: 32 + resetValue: 2 + fields: + - name: MEM_FORCE_PD + description: Set this bit to force eFuse SRAM into power-saving mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_CLK_FORCE_ON + description: Set this bit and force to activate clock signal of eFuse SRAM. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PU + description: Set this bit to force eFuse SRAM into working mode. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EN + description: Set this bit to force enable eFuse register configuration clock signal. + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: CONF + description: eFuse operation mode configuraiton register + addressOffset: 460 + size: 32 + fields: + - name: OP_CODE + description: "0x5A5A: programming operation command 0x5AA5: read operation command." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CFG_ECDSA_BLK + description: Configures which block to use for ECDSA key output. + bitOffset: 16 + bitWidth: 4 + access: read-write + - register: + name: STATUS + description: eFuse status register. + addressOffset: 464 + size: 32 + fields: + - name: STATE + description: Indicates the state of the eFuse state machine. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: OTP_LOAD_SW + description: The value of OTP_LOAD_SW. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: OTP_VDDQ_C_SYNC2 + description: The value of OTP_VDDQ_C_SYNC2. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OTP_STROBE_SW + description: The value of OTP_STROBE_SW. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OTP_CSB_SW + description: The value of OTP_CSB_SW. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OTP_PGENB_SW + description: The value of OTP_PGENB_SW. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: OTP_VDDQ_IS_SW + description: The value of OTP_VDDQ_IS_SW. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: BLK0_VALID_BIT_CNT + description: Indicates the number of block valid bit. + bitOffset: 10 + bitWidth: 10 + access: read-only + - name: CUR_ECDSA_BLK + description: Indicates which block is used for ECDSA key output. + bitOffset: 20 + bitWidth: 4 + access: read-only + - register: + name: CMD + description: eFuse command register. + addressOffset: 468 + size: 32 + fields: + - name: READ_CMD + description: Set this bit to send read command. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PGM_CMD + description: Set this bit to send programming command. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BLK_NUM + description: "The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively." + bitOffset: 2 + bitWidth: 4 + access: read-write + - register: + name: INT_RAW + description: eFuse raw interrupt register. + addressOffset: 472 + size: 32 + fields: + - name: READ_DONE_INT_RAW + description: The raw bit signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PGM_DONE_INT_RAW + description: The raw bit signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: eFuse interrupt status register. + addressOffset: 476 + size: 32 + fields: + - name: READ_DONE_INT_ST + description: The status signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PGM_DONE_INT_ST + description: The status signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: eFuse interrupt enable register. + addressOffset: 480 + size: 32 + fields: + - name: READ_DONE_INT_ENA + description: The enable signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PGM_DONE_INT_ENA + description: The enable signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: eFuse interrupt clear register. + addressOffset: 484 + size: 32 + fields: + - name: READ_DONE_INT_CLR + description: The clear signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: PGM_DONE_INT_CLR + description: The clear signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: DAC_CONF + description: Controls the eFuse programming voltage. + addressOffset: 488 + size: 32 + resetValue: 130583 + fields: + - name: DAC_CLK_DIV + description: Controls the division factor of the rising clock of the programming voltage. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: DAC_CLK_PAD_SEL + description: "Don't care." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DAC_NUM + description: Controls the rising period of the programming voltage. + bitOffset: 9 + bitWidth: 8 + access: read-write + - name: OE_CLR + description: Reduces the power supply of the programming voltage. + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: RD_TIM_CONF + description: Configures read timing parameters. + addressOffset: 492 + size: 32 + resetValue: 251724289 + fields: + - name: THR_A + description: Configures the read hold time. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TRD + description: Configures the read time. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: TSUR_A + description: Configures the read setup time. + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: READ_INIT_NUM + description: Configures the waiting time of reading eFuse memory. + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: WR_TIM_CONF1 + description: Configurarion register 1 of eFuse programming timing parameters. + addressOffset: 496 + size: 32 + resetValue: 19293953 + fields: + - name: TSUP_A + description: Configures the programming setup time. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: PWR_ON_NUM + description: Configures the power up time for VDDQ. + bitOffset: 8 + bitWidth: 16 + access: read-write + - name: THP_A + description: Configures the programming hold time. + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: WR_TIM_CONF2 + description: Configurarion register 2 of eFuse programming timing parameters. + addressOffset: 500 + size: 32 + resetValue: 10486080 + fields: + - name: PWR_OFF_NUM + description: Configures the power outage time for VDDQ. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: TPGM + description: Configures the active programming time. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: WR_TIM_CONF0_RS_BYPASS + description: Configurarion register0 of eFuse programming time parameters and rs bypass operation. + addressOffset: 504 + size: 32 + resetValue: 8192 + fields: + - name: BYPASS_RS_CORRECTION + description: Set this bit to bypass reed solomon correction step. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: BYPASS_RS_BLK_NUM + description: Configures block number of programming twice operation. + bitOffset: 1 + bitWidth: 11 + access: read-write + - name: UPDATE + description: Set this bit to update multi-bit register signals. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: TPGM_INACTIVE + description: Configures the inactive programming time. + bitOffset: 13 + bitWidth: 8 + access: read-write + - register: + name: DATE + description: eFuse version register. + addressOffset: 508 + size: 32 + resetValue: 35684640 + fields: + - name: DATE + description: Stores eFuse version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: GPIO + description: General Purpose Input/Output + groupName: GPIO + baseAddress: 1611206656 + addressBlock: + - offset: 0 + size: 844 + usage: registers + interrupt: + - name: GPIO + value: 22 + - name: GPIO_NMI + value: 23 + registers: + - register: + name: BT_SELECT + description: GPIO bit select register + addressOffset: 0 + size: 32 + fields: + - name: BT_SEL + description: GPIO bit select register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: OUT + description: GPIO output register for GPIO0-31 + addressOffset: 4 + size: 32 + fields: + - name: DATA_ORIG + description: GPIO output register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: OUT_W1TS + description: GPIO output set register for GPIO0-31 + addressOffset: 8 + size: 32 + fields: + - name: OUT_W1TS + description: GPIO output set register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: OUT_W1TC + description: GPIO output clear register for GPIO0-31 + addressOffset: 12 + size: 32 + fields: + - name: OUT_W1TC + description: GPIO output clear register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: SDIO_SELECT + description: GPIO sdio select register + addressOffset: 28 + size: 32 + fields: + - name: SDIO_SEL + description: GPIO sdio select register + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: ENABLE + description: GPIO output enable register for GPIO0-31 + addressOffset: 32 + size: 32 + fields: + - name: DATA + description: GPIO output enable register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ENABLE_W1TS + description: GPIO output enable set register for GPIO0-31 + addressOffset: 36 + size: 32 + fields: + - name: ENABLE_W1TS + description: GPIO output enable set register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: ENABLE_W1TC + description: GPIO output enable clear register for GPIO0-31 + addressOffset: 40 + size: 32 + fields: + - name: ENABLE_W1TC + description: GPIO output enable clear register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: STRAP + description: pad strapping register + addressOffset: 56 + size: 32 + fields: + - name: STRAPPING + description: pad strapping register + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: IN + description: GPIO input register for GPIO0-31 + addressOffset: 60 + size: 32 + fields: + - name: DATA_NEXT + description: GPIO input register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: STATUS + description: GPIO interrupt status register for GPIO0-31 + addressOffset: 68 + size: 32 + fields: + - name: INTERRUPT + description: GPIO interrupt status register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STATUS_W1TS + description: GPIO interrupt status set register for GPIO0-31 + addressOffset: 72 + size: 32 + fields: + - name: STATUS_W1TS + description: GPIO interrupt status set register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: STATUS_W1TC + description: GPIO interrupt status clear register for GPIO0-31 + addressOffset: 76 + size: 32 + fields: + - name: STATUS_W1TC + description: GPIO interrupt status clear register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: PCPU_INT + description: GPIO PRO_CPU interrupt status register for GPIO0-31 + addressOffset: 92 + size: 32 + fields: + - name: PROCPU_INT + description: GPIO PRO_CPU interrupt status register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PCPU_NMI_INT + description: GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + addressOffset: 96 + size: 32 + fields: + - name: PROCPU_NMI_INT + description: GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CPUSDIO_INT + description: GPIO CPUSDIO interrupt status register for GPIO0-31 + addressOffset: 100 + size: 32 + fields: + - name: SDIO_INT + description: GPIO CPUSDIO interrupt status register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + dim: 32 + dimIncrement: 4 + name: PIN%s + description: GPIO pin configuration register + addressOffset: 116 + size: 32 + fields: + - name: SYNC2_BYPASS + description: "set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: PAD_DRIVER + description: "set this bit to select pad driver. 1:open-drain. 0:normal." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SYNC1_BYPASS + description: "set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge." + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: INT_TYPE + description: "set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CONFIG + description: reserved + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: INT_ENA + description: set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. + bitOffset: 13 + bitWidth: 5 + access: read-write + - register: + name: STATUS_NEXT + description: GPIO interrupt source register for GPIO0-31 + addressOffset: 332 + size: 32 + fields: + - name: STATUS_INTERRUPT_NEXT + description: GPIO interrupt source register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + dim: 128 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127" + name: FUNC%s_IN_SEL_CFG + description: GPIO input function configuration register + addressOffset: 340 + size: 32 + resetValue: 60 + fields: + - name: IN_SEL + description: "set this value: s=0-34: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level." + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: IN_INV_SEL + description: "set this bit to invert input signal. 1:invert. 0:not invert." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SEL + description: "set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO." + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + dim: 30 + dimIncrement: 4 + name: FUNC%s_OUT_SEL_CFG + description: GPIO output function select register + addressOffset: 1364 + size: 32 + resetValue: 128 + fields: + - name: OUT_SEL + description: "The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals GPIO_OUT_REG[n]." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: INV_SEL + description: "set this bit to invert output signal.1:invert.0:not invert." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: OEN_SEL + description: "set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OEN_INV_SEL + description: "set this bit to invert output enable signal.1:invert.0:not invert." + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: CLOCK_GATE + description: GPIO clock gate register + addressOffset: 1580 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: set this bit to enable GPIO clock gate + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: GPIO version register + addressOffset: 1788 + size: 32 + resetValue: 35655968 + fields: + - name: DATE + description: version register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: GPIO_SD + description: Sigma-Delta Modulation + groupName: GPIOSD + baseAddress: 1611210496 + addressBlock: + - offset: 0 + size: 144 + usage: registers + registers: + - register: + dim: 4 + dimIncrement: 4 + name: SIGMADELTA%s + description: Duty Cycle Configure Register of SDM%s + addressOffset: 0 + size: 32 + resetValue: 65280 + fields: + - name: SD_IN + description: This field is used to configure the duty cycle of sigma delta modulation output. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SD_PRESCALE + description: This field is used to set a divider value to divide APB clock. + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: CLOCK_GATE + description: Clock Gating Configure Register + addressOffset: 32 + size: 32 + fields: + - name: CLK_EN + description: Clock enable bit of configuration registers for sigma delta modulation. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SIGMADELTA_MISC + description: MISC Register + addressOffset: 36 + size: 32 + fields: + - name: FUNCTION_CLK_EN + description: Clock enable bit of sigma delta modulation. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI_SWAP + description: Reserved. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: PAD_COMP_CONFIG + description: PAD Compare configure Register + addressOffset: 40 + size: 32 + fields: + - name: XPD_COMP + description: Pad compare enable bit. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MODE_COMP + description: "1 to enable external reference from PAD[0]. 0 to enable internal reference, meanwhile PAD[0] can be used as a regular GPIO." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DREF_COMP + description: internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST. + bitOffset: 2 + bitWidth: 3 + access: read-write + - name: ZERO_DET_MODE + description: Zero Detect mode select. + bitOffset: 5 + bitWidth: 2 + access: read-write + - register: + name: PAD_COMP_FILTER + description: Zero Detect filter Register + addressOffset: 44 + size: 32 + fields: + - name: ZERO_DET_FILTER_CNT + description: Zero Detect filter cycle length + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + name: GLITCH_FILTER_CH%s + description: Glitch Filter Configure Register of Channel%s + addressOffset: 48 + size: 32 + fields: + - name: FILTER_CH0_EN + description: Glitch Filter channel enable bit. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FILTER_CH0_INPUT_IO_NUM + description: Glitch Filter input io number. + bitOffset: 1 + bitWidth: 6 + access: read-write + - name: FILTER_CH0_WINDOW_THRES + description: Glitch Filter window threshold. + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: FILTER_CH0_WINDOW_WIDTH + description: Glitch Filter window width. + bitOffset: 13 + bitWidth: 6 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + name: ETM_EVENT_CH%s_CFG + description: Etm Config register of Channel%s + addressOffset: 96 + size: 32 + fields: + - name: ETM_CH0_EVENT_SEL + description: Etm event channel select gpio. + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: ETM_CH0_EVENT_EN + description: Etm event send enable bit. + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: ETM_TASK_P0_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 160 + size: 32 + fields: + - name: ETM_TASK_GPIO0_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO0_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO1_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO1_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO2_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO2_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO3_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO3_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P1_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 164 + size: 32 + fields: + - name: ETM_TASK_GPIO4_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO4_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO5_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO5_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO6_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO6_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO7_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO7_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P2_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 168 + size: 32 + fields: + - name: ETM_TASK_GPIO8_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO8_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO9_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO9_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO10_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO10_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO11_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO11_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P3_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 172 + size: 32 + fields: + - name: ETM_TASK_GPIO12_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO12_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO13_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO13_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO14_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO14_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO15_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO15_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P4_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 176 + size: 32 + fields: + - name: ETM_TASK_GPIO16_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO16_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO17_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO17_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO18_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO18_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO19_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO19_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P5_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 180 + size: 32 + fields: + - name: ETM_TASK_GPIO20_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO20_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO21_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO21_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO22_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO22_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO23_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO23_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P6_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 184 + size: 32 + fields: + - name: ETM_TASK_GPIO24_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO24_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO25_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO25_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO26_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO26_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO27_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO27_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: INT_RAW + description: GPIOSD interrupt raw register + addressOffset: 224 + size: 32 + fields: + - name: PAD_COMP_INT_RAW + description: Pad compare raw interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: GPIOSD interrupt masked register + addressOffset: 228 + size: 32 + fields: + - name: PAD_COMP_INT_ST + description: Pad compare masked interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: GPIOSD interrupt enable register + addressOffset: 232 + size: 32 + fields: + - name: PAD_COMP_INT_ENA + description: Pad compare interrupt enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: GPIOSD interrupt clear register + addressOffset: 236 + size: 32 + fields: + - name: PAD_COMP_INT_CLR + description: Pad compare interrupt clear + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: VERSION + description: Version Control Register + addressOffset: 252 + size: 32 + resetValue: 35684640 + fields: + - name: GPIO_SD_DATE + description: Version control register. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: HMAC + description: HMAC (Hash-based Message Authentication Code) Accelerator + groupName: HMAC + baseAddress: 1611190272 + addressBlock: + - offset: 0 + size: 164 + usage: registers + registers: + - register: + name: SET_START + description: Process control register 0. + addressOffset: 64 + size: 32 + fields: + - name: SET_START + description: Start hmac operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_PARA_PURPOSE + description: Configure purpose. + addressOffset: 68 + size: 32 + fields: + - name: PURPOSE_SET + description: Set hmac parameter purpose. + bitOffset: 0 + bitWidth: 4 + access: write-only + - register: + name: SET_PARA_KEY + description: Configure key. + addressOffset: 72 + size: 32 + fields: + - name: KEY_SET + description: Set hmac parameter key. + bitOffset: 0 + bitWidth: 3 + access: write-only + - register: + name: SET_PARA_FINISH + description: Finish initial configuration. + addressOffset: 76 + size: 32 + fields: + - name: SET_PARA_END + description: Finish hmac configuration. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_MESSAGE_ONE + description: Process control register 1. + addressOffset: 80 + size: 32 + fields: + - name: SET_TEXT_ONE + description: Call SHA to calculate one message block. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_MESSAGE_ING + description: Process control register 2. + addressOffset: 84 + size: 32 + fields: + - name: SET_TEXT_ING + description: Continue typical hmac. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_MESSAGE_END + description: Process control register 3. + addressOffset: 88 + size: 32 + fields: + - name: SET_TEXT_END + description: Start hardware padding. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_RESULT_FINISH + description: Process control register 4. + addressOffset: 92 + size: 32 + fields: + - name: SET_RESULT_END + description: "After read result from upstream, then let hmac back to idle." + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_INVALIDATE_JTAG + description: Invalidate register 0. + addressOffset: 96 + size: 32 + fields: + - name: SET_INVALIDATE_JTAG + description: Clear result from hmac downstream JTAG. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_INVALIDATE_DS + description: Invalidate register 1. + addressOffset: 100 + size: 32 + fields: + - name: SET_INVALIDATE_DS + description: Clear result from hmac downstream DS. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: QUERY_ERROR + description: Error register. + addressOffset: 104 + size: 32 + fields: + - name: QUERY_CHECK + description: "Hmac configuration state. 0: key are agree with purpose. 1: error" + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: QUERY_BUSY + description: Busy register. + addressOffset: 108 + size: 32 + fields: + - name: BUSY_STATE + description: "Hmac state. 1'b0: idle. 1'b1: busy" + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + dim: 16 + dimIncrement: 4 + name: "WR_MESSAGE_MEM[%s]" + description: Message block memory. + addressOffset: 128 + size: 32 + - register: + dim: 8 + dimIncrement: 4 + name: "RD_RESULT_MEM[%s]" + description: Result from upstream. + addressOffset: 192 + size: 32 + - register: + name: SET_MESSAGE_PAD + description: Process control register 5. + addressOffset: 240 + size: 32 + fields: + - name: SET_TEXT_PAD + description: Start software padding. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: ONE_BLOCK + description: Process control register 6. + addressOffset: 244 + size: 32 + fields: + - name: SET_ONE_BLOCK + description: "Don't have to do padding." + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SOFT_JTAG_CTRL + description: Jtag register 0. + addressOffset: 248 + size: 32 + fields: + - name: SOFT_JTAG_CTRL + description: Turn on JTAG verification. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: WR_JTAG + description: Jtag register 1. + addressOffset: 252 + size: 32 + fields: + - name: WR_JTAG + description: 32-bit of key to be compared. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: DATE + description: Date register. + addressOffset: 508 + size: 32 + resetValue: 538969624 + fields: + - name: DATE + description: Hmac date information/ hmac version information. + bitOffset: 0 + bitWidth: 30 + access: read-write + - name: HP_APM + description: HP_APM Peripheral + groupName: HP_APM + baseAddress: 1611239424 + addressBlock: + - offset: 0 + size: 276 + usage: registers + interrupt: + - name: HP_APM_M0 + value: 26 + - name: HP_APM_M1 + value: 27 + - name: HP_APM_M2 + value: 28 + - name: HP_APM_M3 + value: 29 + registers: + - register: + name: REGION_FILTER_EN + description: Region filter enable register + addressOffset: 0 + size: 32 + resetValue: 1 + fields: + - name: REGION_FILTER_EN + description: Region filter enable + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: REGION0_ADDR_START + description: Region address register + addressOffset: 4 + size: 32 + fields: + - name: REGION0_ADDR_START + description: Start address of region0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION0_ADDR_END + description: Region address register + addressOffset: 8 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION0_ADDR_END + description: End address of region0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION0_PMS_ATTR + description: Region access authority attribute register + addressOffset: 12 + size: 32 + fields: + - name: REGION0_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION0_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION0_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION0_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION0_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION0_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION0_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION0_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION0_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION1_ADDR_START + description: Region address register + addressOffset: 16 + size: 32 + fields: + - name: REGION1_ADDR_START + description: Start address of region1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION1_ADDR_END + description: Region address register + addressOffset: 20 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION1_ADDR_END + description: End address of region1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION1_PMS_ATTR + description: Region access authority attribute register + addressOffset: 24 + size: 32 + fields: + - name: REGION1_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION1_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION1_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION1_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION1_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION1_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION1_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION1_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION1_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION2_ADDR_START + description: Region address register + addressOffset: 28 + size: 32 + fields: + - name: REGION2_ADDR_START + description: Start address of region2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION2_ADDR_END + description: Region address register + addressOffset: 32 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION2_ADDR_END + description: End address of region2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION2_PMS_ATTR + description: Region access authority attribute register + addressOffset: 36 + size: 32 + fields: + - name: REGION2_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION2_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION2_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION2_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION2_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION2_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION2_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION2_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION2_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION3_ADDR_START + description: Region address register + addressOffset: 40 + size: 32 + fields: + - name: REGION3_ADDR_START + description: Start address of region3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION3_ADDR_END + description: Region address register + addressOffset: 44 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION3_ADDR_END + description: End address of region3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION3_PMS_ATTR + description: Region access authority attribute register + addressOffset: 48 + size: 32 + fields: + - name: REGION3_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION3_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION3_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION3_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION3_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION3_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION3_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION3_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION3_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION4_ADDR_START + description: Region address register + addressOffset: 52 + size: 32 + fields: + - name: REGION4_ADDR_START + description: Start address of region4 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION4_ADDR_END + description: Region address register + addressOffset: 56 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION4_ADDR_END + description: End address of region4 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION4_PMS_ATTR + description: Region access authority attribute register + addressOffset: 60 + size: 32 + fields: + - name: REGION4_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION4_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION4_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION4_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION4_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION4_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION4_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION4_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION4_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION5_ADDR_START + description: Region address register + addressOffset: 64 + size: 32 + fields: + - name: REGION5_ADDR_START + description: Start address of region5 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION5_ADDR_END + description: Region address register + addressOffset: 68 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION5_ADDR_END + description: End address of region5 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION5_PMS_ATTR + description: Region access authority attribute register + addressOffset: 72 + size: 32 + fields: + - name: REGION5_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION5_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION5_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION5_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION5_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION5_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION5_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION5_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION5_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION6_ADDR_START + description: Region address register + addressOffset: 76 + size: 32 + fields: + - name: REGION6_ADDR_START + description: Start address of region6 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION6_ADDR_END + description: Region address register + addressOffset: 80 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION6_ADDR_END + description: End address of region6 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION6_PMS_ATTR + description: Region access authority attribute register + addressOffset: 84 + size: 32 + fields: + - name: REGION6_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION6_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION6_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION6_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION6_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION6_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION6_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION6_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION6_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION7_ADDR_START + description: Region address register + addressOffset: 88 + size: 32 + fields: + - name: REGION7_ADDR_START + description: Start address of region7 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION7_ADDR_END + description: Region address register + addressOffset: 92 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION7_ADDR_END + description: End address of region7 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION7_PMS_ATTR + description: Region access authority attribute register + addressOffset: 96 + size: 32 + fields: + - name: REGION7_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION7_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION7_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION7_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION7_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION7_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION7_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION7_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION7_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION8_ADDR_START + description: Region address register + addressOffset: 100 + size: 32 + fields: + - name: REGION8_ADDR_START + description: Start address of region8 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION8_ADDR_END + description: Region address register + addressOffset: 104 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION8_ADDR_END + description: End address of region8 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION8_PMS_ATTR + description: Region access authority attribute register + addressOffset: 108 + size: 32 + fields: + - name: REGION8_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION8_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION8_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION8_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION8_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION8_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION8_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION8_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION8_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION9_ADDR_START + description: Region address register + addressOffset: 112 + size: 32 + fields: + - name: REGION9_ADDR_START + description: Start address of region9 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION9_ADDR_END + description: Region address register + addressOffset: 116 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION9_ADDR_END + description: End address of region9 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION9_PMS_ATTR + description: Region access authority attribute register + addressOffset: 120 + size: 32 + fields: + - name: REGION9_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION9_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION9_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION9_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION9_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION9_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION9_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION9_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION9_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION10_ADDR_START + description: Region address register + addressOffset: 124 + size: 32 + fields: + - name: REGION10_ADDR_START + description: Start address of region10 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION10_ADDR_END + description: Region address register + addressOffset: 128 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION10_ADDR_END + description: End address of region10 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION10_PMS_ATTR + description: Region access authority attribute register + addressOffset: 132 + size: 32 + fields: + - name: REGION10_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION10_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION10_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION10_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION10_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION10_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION10_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION10_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION10_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION11_ADDR_START + description: Region address register + addressOffset: 136 + size: 32 + fields: + - name: REGION11_ADDR_START + description: Start address of region11 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION11_ADDR_END + description: Region address register + addressOffset: 140 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION11_ADDR_END + description: End address of region11 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION11_PMS_ATTR + description: Region access authority attribute register + addressOffset: 144 + size: 32 + fields: + - name: REGION11_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION11_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION11_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION11_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION11_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION11_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION11_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION11_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION11_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION12_ADDR_START + description: Region address register + addressOffset: 148 + size: 32 + fields: + - name: REGION12_ADDR_START + description: Start address of region12 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION12_ADDR_END + description: Region address register + addressOffset: 152 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION12_ADDR_END + description: End address of region12 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION12_PMS_ATTR + description: Region access authority attribute register + addressOffset: 156 + size: 32 + fields: + - name: REGION12_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION12_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION12_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION12_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION12_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION12_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION12_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION12_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION12_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION13_ADDR_START + description: Region address register + addressOffset: 160 + size: 32 + fields: + - name: REGION13_ADDR_START + description: Start address of region13 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION13_ADDR_END + description: Region address register + addressOffset: 164 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION13_ADDR_END + description: End address of region13 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION13_PMS_ATTR + description: Region access authority attribute register + addressOffset: 168 + size: 32 + fields: + - name: REGION13_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION13_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION13_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION13_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION13_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION13_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION13_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION13_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION13_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION14_ADDR_START + description: Region address register + addressOffset: 172 + size: 32 + fields: + - name: REGION14_ADDR_START + description: Start address of region14 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION14_ADDR_END + description: Region address register + addressOffset: 176 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION14_ADDR_END + description: End address of region14 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION14_PMS_ATTR + description: Region access authority attribute register + addressOffset: 180 + size: 32 + fields: + - name: REGION14_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION14_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION14_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION14_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION14_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION14_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION14_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION14_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION14_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION15_ADDR_START + description: Region address register + addressOffset: 184 + size: 32 + fields: + - name: REGION15_ADDR_START + description: Start address of region15 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION15_ADDR_END + description: Region address register + addressOffset: 188 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION15_ADDR_END + description: End address of region15 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION15_PMS_ATTR + description: Region access authority attribute register + addressOffset: 192 + size: 32 + fields: + - name: REGION15_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION15_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION15_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION15_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION15_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION15_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION15_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION15_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION15_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: FUNC_CTRL + description: PMS function control register + addressOffset: 196 + size: 32 + resetValue: 15 + fields: + - name: M0_PMS_FUNC_EN + description: PMS M0 function enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: M1_PMS_FUNC_EN + description: PMS M1 function enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: M2_PMS_FUNC_EN + description: PMS M2 function enable + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: M3_PMS_FUNC_EN + description: PMS M3 function enable + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: M0_STATUS + description: M0 status register + addressOffset: 200 + size: 32 + fields: + - name: M0_EXCEPTION_STATUS + description: Exception status + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: M0_STATUS_CLR + description: M0 status clear register + addressOffset: 204 + size: 32 + fields: + - name: M0_REGION_STATUS_CLR + description: Clear exception status + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: M0_EXCEPTION_INFO0 + description: M0 exception_info0 register + addressOffset: 208 + size: 32 + fields: + - name: M0_EXCEPTION_REGION + description: Exception region + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: M0_EXCEPTION_MODE + description: Exception mode + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: M0_EXCEPTION_ID + description: Exception id information + bitOffset: 18 + bitWidth: 5 + access: read-only + - register: + name: M0_EXCEPTION_INFO1 + description: M0 exception_info1 register + addressOffset: 212 + size: 32 + fields: + - name: M0_EXCEPTION_ADDR + description: Exception addr + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: M1_STATUS + description: M1 status register + addressOffset: 216 + size: 32 + fields: + - name: M1_EXCEPTION_STATUS + description: Exception status + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: M1_STATUS_CLR + description: M1 status clear register + addressOffset: 220 + size: 32 + fields: + - name: M1_REGION_STATUS_CLR + description: Clear exception status + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: M1_EXCEPTION_INFO0 + description: M1 exception_info0 register + addressOffset: 224 + size: 32 + fields: + - name: M1_EXCEPTION_REGION + description: Exception region + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: M1_EXCEPTION_MODE + description: Exception mode + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: M1_EXCEPTION_ID + description: Exception id information + bitOffset: 18 + bitWidth: 5 + access: read-only + - register: + name: M1_EXCEPTION_INFO1 + description: M1 exception_info1 register + addressOffset: 228 + size: 32 + fields: + - name: M1_EXCEPTION_ADDR + description: Exception addr + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: M2_STATUS + description: M2 status register + addressOffset: 232 + size: 32 + fields: + - name: M2_EXCEPTION_STATUS + description: Exception status + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: M2_STATUS_CLR + description: M2 status clear register + addressOffset: 236 + size: 32 + fields: + - name: M2_REGION_STATUS_CLR + description: Clear exception status + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: M2_EXCEPTION_INFO0 + description: M2 exception_info0 register + addressOffset: 240 + size: 32 + fields: + - name: M2_EXCEPTION_REGION + description: Exception region + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: M2_EXCEPTION_MODE + description: Exception mode + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: M2_EXCEPTION_ID + description: Exception id information + bitOffset: 18 + bitWidth: 5 + access: read-only + - register: + name: M2_EXCEPTION_INFO1 + description: M2 exception_info1 register + addressOffset: 244 + size: 32 + fields: + - name: M2_EXCEPTION_ADDR + description: Exception addr + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: M3_STATUS + description: M3 status register + addressOffset: 248 + size: 32 + fields: + - name: M3_EXCEPTION_STATUS + description: Exception status + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: M3_STATUS_CLR + description: M3 status clear register + addressOffset: 252 + size: 32 + fields: + - name: M3_REGION_STATUS_CLR + description: Clear exception status + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: M3_EXCEPTION_INFO0 + description: M3 exception_info0 register + addressOffset: 256 + size: 32 + fields: + - name: M3_EXCEPTION_REGION + description: Exception region + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: M3_EXCEPTION_MODE + description: Exception mode + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: M3_EXCEPTION_ID + description: Exception id information + bitOffset: 18 + bitWidth: 5 + access: read-only + - register: + name: M3_EXCEPTION_INFO1 + description: M3 exception_info1 register + addressOffset: 260 + size: 32 + fields: + - name: M3_EXCEPTION_ADDR + description: Exception addr + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INT_EN + description: APM interrupt enable register + addressOffset: 264 + size: 32 + fields: + - name: M0_APM_INT_EN + description: APM M0 interrupt enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: M1_APM_INT_EN + description: APM M1 interrupt enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: M2_APM_INT_EN + description: APM M2 interrupt enable + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: M3_APM_INT_EN + description: APM M3 interrupt enable + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: CLOCK_GATE + description: clock gating register + addressOffset: 268 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: reg_clk_en + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version register + addressOffset: 2044 + size: 32 + resetValue: 35672640 + fields: + - name: DATE + description: reg_date + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: HP_SYS + description: High-Power System + groupName: HP_SYS + baseAddress: 1611223040 + addressBlock: + - offset: 0 + size: 68 + usage: registers + interrupt: + - name: HP_PERI_TIMEOUT + value: 25 + registers: + - register: + name: EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL + description: EXTERNAL DEVICE ENCRYPTION/DECRYPTION configuration register + addressOffset: 0 + size: 32 + fields: + - name: ENABLE_SPI_MANUAL_ENCRYPT + description: Set this bit as 1 to enable mspi xts manual encrypt in spi boot mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ENABLE_DOWNLOAD_DB_ENCRYPT + description: reserved + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ENABLE_DOWNLOAD_G0CB_DECRYPT + description: Set this bit as 1 to enable mspi xts auto decrypt in download boot mode. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ENABLE_DOWNLOAD_MANUAL_ENCRYPT + description: Set this bit as 1 to enable mspi xts manual encrypt in download boot mode. + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: SRAM_USAGE_CONF + description: HP memory usage configuration register + addressOffset: 4 + size: 32 + fields: + - name: SRAM_USAGE + description: "0: cpu use hp-memory. 1: mac-dump accessing hp-memory." + bitOffset: 10 + bitWidth: 5 + access: read-write + - name: MAC_DUMP_ALLOC + description: reserved. + bitOffset: 20 + bitWidth: 5 + access: read-write + - name: CACHE_USAGE + description: reserved + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: SEC_DPA_CONF + description: HP anti-DPA security configuration register + addressOffset: 8 + size: 32 + fields: + - name: SEC_DPA_LEVEL + description: "0: anti-DPA disable. 1~3: anti-DPA enable with different security level. The larger the number, the stronger the ability to resist DPA attacks and the higher the security level, but it will increase the computational overhead of the hardware crypto-accelerators. Only avaliable if HP_SYS_SEC_DPA_CFG_SEL is 0." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SEC_DPA_CFG_SEL + description: "This field is used to select either HP_SYS_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from efuse) to control dpa_level. 0: EFUSE_SEC_DPA_LEVEL, 1: HP_SYS_SEC_DPA_LEVEL." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: CPU_PERI_TIMEOUT_CONF + description: CPU_PERI_TIMEOUT configuration register + addressOffset: 12 + size: 32 + resetValue: 196607 + fields: + - name: CPU_PERI_TIMEOUT_THRES + description: "Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CPU_PERI_TIMEOUT_INT_CLEAR + description: Set this bit as 1 to clear timeout interrupt + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: CPU_PERI_TIMEOUT_PROTECT_EN + description: Set this bit as 1 to enable timeout protection for accessing cpu peripheral registers + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: CPU_PERI_TIMEOUT_ADDR + description: CPU_PERI_TIMEOUT_ADDR register + addressOffset: 16 + size: 32 + fields: + - name: CPU_PERI_TIMEOUT_ADDR + description: Record the address information of abnormal access + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CPU_PERI_TIMEOUT_UID + description: CPU_PERI_TIMEOUT_UID register + addressOffset: 20 + size: 32 + fields: + - name: CPU_PERI_TIMEOUT_UID + description: "Record master id[4:0] & master permission[6:5] when trigger timeout. This register will be cleared after the interrupt is cleared." + bitOffset: 0 + bitWidth: 7 + access: read-only + - register: + name: HP_PERI_TIMEOUT_CONF + description: HP_PERI_TIMEOUT configuration register + addressOffset: 24 + size: 32 + resetValue: 196607 + fields: + - name: HP_PERI_TIMEOUT_THRES + description: "Set the timeout threshold for bus access, corresponding to the number of clock cycles of the clock domain." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: HP_PERI_TIMEOUT_INT_CLEAR + description: Set this bit as 1 to clear timeout interrupt + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: HP_PERI_TIMEOUT_PROTECT_EN + description: Set this bit as 1 to enable timeout protection for accessing hp peripheral registers + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: HP_PERI_TIMEOUT_ADDR + description: HP_PERI_TIMEOUT_ADDR register + addressOffset: 28 + size: 32 + fields: + - name: HP_PERI_TIMEOUT_ADDR + description: Record the address information of abnormal access + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HP_PERI_TIMEOUT_UID + description: HP_PERI_TIMEOUT_UID register + addressOffset: 32 + size: 32 + fields: + - name: HP_PERI_TIMEOUT_UID + description: "Record master id[4:0] & master permission[6:5] when trigger timeout. This register will be cleared after the interrupt is cleared." + bitOffset: 0 + bitWidth: 7 + access: read-only + - register: + name: ROM_TABLE_LOCK + description: Rom-Table lock register + addressOffset: 36 + size: 32 + fields: + - name: ROM_TABLE_LOCK + description: XXXX + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: ROM_TABLE + description: Rom-Table register + addressOffset: 40 + size: 32 + fields: + - name: ROM_TABLE + description: XXXX + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: MEM_TEST_CONF + description: MEM_TEST configuration register + addressOffset: 44 + size: 32 + resetValue: 8744 + fields: + - name: HP_MEM_WPULSE + description: This field controls hp system memory WPULSE parameter. 0b000 for 1.1V/1.0V/0.9V operating Voltage. + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: HP_MEM_WA + description: "This field controls hp system memory WA parameter. 0b100 for 1.1V operating Voltage, 0b101 for 1.0V, 0b110 for 0.9V." + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: HP_MEM_RA + description: "This field controls hp system memory RA parameter. 0b00 for 1.1V/1.0V operating Voltage, 0b01 for 0.9V." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: HP_MEM_RM + description: "This field controls hp system memory RM parameter. 0b0011 for 1.1V operating Voltage, 0b0010 for 1.0V, 0b0000 for 0.9V." + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: ROM_RM + description: "This field controls rom RM parameter. 0b0011 for 1.1V operating Voltage, 0b0010 for 1.0V, 0b0010(default) or 0b0001(slow) for 0.9V." + bitOffset: 12 + bitWidth: 4 + access: read-write + - register: + name: RND_ECO + description: redcy eco register. + addressOffset: 992 + size: 32 + fields: + - name: REDCY_ENA + description: Only reserved for ECO. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REDCY_RESULT + description: Only reserved for ECO. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: RND_ECO_LOW + description: redcy eco low register. + addressOffset: 996 + size: 32 + fields: + - name: REDCY_LOW + description: Only reserved for ECO. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RND_ECO_HIGH + description: redcy eco high register. + addressOffset: 1000 + size: 32 + resetValue: 4294967295 + fields: + - name: REDCY_HIGH + description: Only reserved for ECO. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CLOCK_GATE + description: HP-SYSTEM clock gating configure register + addressOffset: 1016 + size: 32 + fields: + - name: CLK_EN + description: Set this bit as 1 to force on clock gating. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Date register. + addressOffset: 1020 + size: 32 + resetValue: 35689073 + fields: + - name: DATE + description: HP-SYSTEM date information/ HP-SYSTEM version information. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: I2C0 + description: I2C (Inter-Integrated Circuit) Controller 0 + groupName: I2C + baseAddress: 1610629120 + addressBlock: + - offset: 0 + size: 144 + usage: registers + interrupt: + - name: I2C_EXT0 + value: 39 + registers: + - register: + name: SCL_LOW_PERIOD + description: "Configures the low level width of the SCL\nClock" + addressOffset: 0 + size: 32 + fields: + - name: SCL_LOW_PERIOD + description: "This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: CTR + description: Transmission setting + addressOffset: 4 + size: 32 + resetValue: 520 + fields: + - name: SDA_FORCE_OUT + description: "1: direct output, 0: open drain output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_FORCE_OUT + description: "1: direct output, 0: open drain output." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SAMPLE_SCL_LEVEL + description: "This register is used to select the sample mode.\n1: sample SDA data on the SCL low level.\n0: sample SDA data on the SCL high level." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_FULL_ACK_LEVEL + description: This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MS_MODE + description: "Set this bit to configure the module as an I2C Master. Clear this bit to configure the\nmodule as an I2C Slave." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TRANS_START + description: Set this bit to start sending the data in txfifo. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TX_LSB_FIRST + description: "This bit is used to control the sending mode for data needing to be sent. \n1: send data from the least significant bit,\n0: send data from the most significant bit." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_LSB_FIRST + description: "This bit is used to control the storage mode for received data.\n1: receive data from the least significant bit,\n0: receive data from the most significant bit." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ARBITRATION_EN + description: This is the enable bit for arbitration_lost. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FSM_RST + description: This register is used to reset the scl FMS. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: CONF_UPGATE + description: synchronization bit + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: SLV_TX_AUTO_START_EN + description: This is the enable bit for slave to send data automatically + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: ADDR_10BIT_RW_CHECK_EN + description: This is the enable bit to check if the r/w bit of 10bit addressing consists with I2C protocol + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: ADDR_BROADCASTING_EN + description: This is the enable bit to support the 7bit general call function. + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: SR + description: Describe I2C work status. + addressOffset: 8 + size: 32 + resetValue: 49152 + fields: + - name: RESP_REC + description: "The received ACK value in master mode or slave mode. 0: ACK, 1: NACK." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SLAVE_RW + description: "When in slave mode, 1: master reads from slave, 0: master writes to slave." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ARB_LOST + description: "When the I2C controller loses control of SCL line, this register changes to 1." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BUS_BUSY + description: "1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SLAVE_ADDRESSED + description: "When configured as an I2C Slave, and the address sent by the master is\nequal to the address of the slave, then this bit will be of high level." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: RXFIFO_CNT + description: This field represents the amount of data needed to be sent. + bitOffset: 8 + bitWidth: 6 + access: read-only + - name: STRETCH_CAUSE + description: "The cause of stretching SCL low in slave mode. 0: stretching SCL low at the beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode." + bitOffset: 14 + bitWidth: 2 + access: read-only + - name: TXFIFO_CNT + description: This field stores the amount of received data in RAM. + bitOffset: 18 + bitWidth: 6 + access: read-only + - name: SCL_MAIN_STATE_LAST + description: "This field indicates the states of the I2C module state machine. \n0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK" + bitOffset: 24 + bitWidth: 3 + access: read-only + - name: SCL_STATE_LAST + description: "This field indicates the states of the state machine used to produce SCL.\n0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop" + bitOffset: 28 + bitWidth: 3 + access: read-only + - register: + name: TO + description: Setting time out control for receiving data. + addressOffset: 12 + size: 32 + resetValue: 16 + fields: + - name: TIME_OUT_VALUE + description: "This register is used to configure the timeout for receiving a data bit in APB\nclock cycles." + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: TIME_OUT_EN + description: This is the enable bit for time out control. + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: SLAVE_ADDR + description: Local slave address setting + addressOffset: 16 + size: 32 + fields: + - name: SLAVE_ADDR + description: "When configured as an I2C Slave, this field is used to configure the slave address." + bitOffset: 0 + bitWidth: 15 + access: read-write + - name: ADDR_10BIT_EN + description: This field is used to enable the slave 10-bit addressing mode in master mode. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: FIFO_ST + description: FIFO status register. + addressOffset: 20 + size: 32 + fields: + - name: RXFIFO_RADDR + description: This is the offset address of the APB reading from rxfifo + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: RXFIFO_WADDR + description: This is the offset address of i2c module receiving data and writing to rxfifo. + bitOffset: 5 + bitWidth: 5 + access: read-only + - name: TXFIFO_RADDR + description: This is the offset address of i2c module reading from txfifo. + bitOffset: 10 + bitWidth: 5 + access: read-only + - name: TXFIFO_WADDR + description: This is the offset address of APB bus writing to txfifo. + bitOffset: 15 + bitWidth: 5 + access: read-only + - name: SLAVE_RW_POINT + description: The received data in I2C slave mode. + bitOffset: 22 + bitWidth: 8 + access: read-only + - register: + name: FIFO_CONF + description: FIFO configuration register. + addressOffset: 24 + size: 32 + resetValue: 16523 + fields: + - name: RXFIFO_WM_THRHD + description: "The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid." + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: TXFIFO_WM_THRHD + description: "The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid." + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: NONFIFO_EN + description: Set this bit to enable APB nonfifo access. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FIFO_ADDR_CFG_EN + description: "When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RX_FIFO_RST + description: Set this bit to reset rx-fifo. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_FIFO_RST + description: Set this bit to reset tx-fifo. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FIFO_PRT_EN + description: "The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty." + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DATA + description: Rx FIFO read data. + addressOffset: 28 + size: 32 + fields: + - name: FIFO_RDATA + description: The value of rx FIFO read data. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 32 + size: 32 + resetValue: 2 + fields: + - name: RXFIFO_WM_INT_RAW + description: The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_WM_INT_RAW + description: The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_RAW + description: The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: END_DETECT_INT_RAW + description: The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS_DONE_INT_RAW + description: The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_RAW + description: The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: MST_TXFIFO_UDF_INT_RAW + description: The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_RAW + description: The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_RAW + description: The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TRANS_START_INT_RAW + description: The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: NACK_INT_RAW + description: The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: TXFIFO_OVF_INT_RAW + description: The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: RXFIFO_UDF_INT_RAW + description: The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SCL_ST_TO_INT_RAW + description: The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SCL_MAIN_ST_TO_INT_RAW + description: The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DET_START_INT_RAW + description: The raw interrupt bit for I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLAVE_STRETCH_INT_RAW + description: The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: GENERAL_CALL_INT_RAW + description: The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: SLAVE_ADDR_UNMATCH_INT_RAW + description: The raw interrupt bit for I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 36 + size: 32 + fields: + - name: RXFIFO_WM_INT_CLR + description: Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TXFIFO_WM_INT_CLR + description: Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RXFIFO_OVF_INT_CLR + description: Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: END_DETECT_INT_CLR + description: Set this bit to clear the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: BYTE_TRANS_DONE_INT_CLR + description: Set this bit to clear the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: ARBITRATION_LOST_INT_CLR + description: Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: MST_TXFIFO_UDF_INT_CLR + description: Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TRANS_COMPLETE_INT_CLR + description: Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: TIME_OUT_INT_CLR + description: Set this bit to clear the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: TRANS_START_INT_CLR + description: Set this bit to clear the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: NACK_INT_CLR + description: Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: TXFIFO_OVF_INT_CLR + description: Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: RXFIFO_UDF_INT_CLR + description: Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: SCL_ST_TO_INT_CLR + description: Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SCL_MAIN_ST_TO_INT_CLR + description: Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: DET_START_INT_CLR + description: Set this bit to clear I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: SLAVE_STRETCH_INT_CLR + description: Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: GENERAL_CALL_INT_CLR + description: Set this bit to clear I2C_GENARAL_CALL_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: SLAVE_ADDR_UNMATCH_INT_CLR + description: Set this bit to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 40 + size: 32 + fields: + - name: RXFIFO_WM_INT_ENA + description: The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_WM_INT_ENA + description: The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_ENA + description: The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: END_DETECT_INT_ENA + description: The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: BYTE_TRANS_DONE_INT_ENA + description: The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ARBITRATION_LOST_INT_ENA + description: The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: MST_TXFIFO_UDF_INT_ENA + description: The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TRANS_COMPLETE_INT_ENA + description: The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TIME_OUT_INT_ENA + description: The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TRANS_START_INT_ENA + description: The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: NACK_INT_ENA + description: The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TXFIFO_OVF_INT_ENA + description: The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RXFIFO_UDF_INT_ENA + description: The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SCL_ST_TO_INT_ENA + description: The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SCL_MAIN_ST_TO_INT_ENA + description: The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DET_START_INT_ENA + description: The interrupt enable bit for I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLAVE_STRETCH_INT_ENA + description: The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: GENERAL_CALL_INT_ENA + description: The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SLAVE_ADDR_UNMATCH_INT_ENA + description: The interrupt enable bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-write + - register: + name: INT_STATUS + description: Status of captured I2C communication events + addressOffset: 44 + size: 32 + fields: + - name: RXFIFO_WM_INT_ST + description: The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_WM_INT_ST + description: The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_ST + description: The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: END_DETECT_INT_ST + description: The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS_DONE_INT_ST + description: The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_ST + description: The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: MST_TXFIFO_UDF_INT_ST + description: The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_ST + description: The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_ST + description: The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TRANS_START_INT_ST + description: The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: NACK_INT_ST + description: The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: TXFIFO_OVF_INT_ST + description: The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: RXFIFO_UDF_INT_ST + description: The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SCL_ST_TO_INT_ST + description: The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SCL_MAIN_ST_TO_INT_ST + description: The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DET_START_INT_ST + description: The masked interrupt status bit for I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLAVE_STRETCH_INT_ST + description: The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: GENERAL_CALL_INT_ST + description: The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: SLAVE_ADDR_UNMATCH_INT_ST + description: The masked interrupt status bit for I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-only + - register: + name: SDA_HOLD + description: Configures the hold time after a negative SCL edge. + addressOffset: 48 + size: 32 + fields: + - name: TIME + description: "This register is used to configure the time to hold the data after the negative\nedge of SCL, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SDA_SAMPLE + description: Configures the sample time after a positive SCL edge. + addressOffset: 52 + size: 32 + fields: + - name: TIME + description: "This register is used to configure for how long SDA is sampled, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_HIGH_PERIOD + description: Configures the high level width of SCL + addressOffset: 56 + size: 32 + fields: + - name: SCL_HIGH_PERIOD + description: "This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: SCL_WAIT_HIGH_PERIOD + description: "This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles." + bitOffset: 9 + bitWidth: 7 + access: read-write + - register: + name: SCL_START_HOLD + description: Configures the delay between the SDA and SCL negative edge for a start condition + addressOffset: 64 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the time between the negative edge\nof SDA and the negative edge of SCL for a START condition, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_RSTART_SETUP + description: "Configures the delay between the positive\nedge of SCL and the negative edge of SDA" + addressOffset: 68 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the time between the positive\nedge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_STOP_HOLD + description: "Configures the delay after the SCL clock\nedge for a stop condition" + addressOffset: 72 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the delay after the STOP condition,\nin I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_STOP_SETUP + description: "Configures the delay between the SDA and\nSCL positive edge for a stop condition" + addressOffset: 76 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the time between the positive edge\nof SCL and the positive edge of SDA, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: FILTER_CFG + description: SCL and SDA filter configuration register + addressOffset: 80 + size: 32 + resetValue: 768 + fields: + - name: SCL_FILTER_THRES + description: "When a pulse on the SCL input has smaller width than this register value\nin I2C module clock cycles, the I2C controller will ignore that pulse." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: SDA_FILTER_THRES + description: "When a pulse on the SDA input has smaller width than this register value\nin I2C module clock cycles, the I2C controller will ignore that pulse." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: SCL_FILTER_EN + description: This is the filter enable bit for SCL. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SDA_FILTER_EN + description: This is the filter enable bit for SDA. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: CLK_CONF + description: I2C CLK configuration register + addressOffset: 84 + size: 32 + resetValue: 2097152 + fields: + - name: SCLK_DIV_NUM + description: the integral part of the fractional divisor for i2c module + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SCLK_DIV_A + description: the numerator of the fractional part of the fractional divisor for i2c module + bitOffset: 8 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_B + description: the denominator of the fractional part of the fractional divisor for i2c module + bitOffset: 14 + bitWidth: 6 + access: read-write + - name: SCLK_SEL + description: "The clock selection for i2c module:0-XTAL,1-CLK_8MHz." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SCLK_ACTIVE + description: The clock switch for i2c module + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7" + name: COMD%s + description: I2C command register %s + addressOffset: 88 + size: 32 + fields: + - name: COMMAND + description: "This is the content of command 0. It consists of three parts: \nop_code is the command, 0: RSTART, 1: WRITE, 2: READ, 3: STOP, 4: END.\nByte_num represents the number of bytes that need to be sent or received.\nack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more\nInformation." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND_DONE + description: "When command 0 is done in I2C Master mode, this bit changes to high\nlevel." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SCL_ST_TIME_OUT + description: SCL status time out register + addressOffset: 120 + size: 32 + resetValue: 16 + fields: + - name: SCL_ST_TO_I2C + description: The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SCL_MAIN_ST_TIME_OUT + description: SCL main status time out register + addressOffset: 124 + size: 32 + resetValue: 16 + fields: + - name: SCL_MAIN_ST_TO_I2C + description: The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23 + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SCL_SP_CONF + description: Power configuration register + addressOffset: 128 + size: 32 + fields: + - name: SCL_RST_SLV_EN + description: "When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_RST_SLV_NUM + description: Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. + bitOffset: 1 + bitWidth: 5 + access: read-write + - name: SCL_PD_EN + description: "The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SDA_PD_EN + description: "The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low." + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: SCL_STRETCH_CONF + description: Set SCL stretch of I2C slave + addressOffset: 132 + size: 32 + fields: + - name: STRETCH_PROTECT_NUM + description: Configure the period of I2C slave stretching SCL line. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: SLAVE_SCL_STRETCH_EN + description: "The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLAVE_SCL_STRETCH_CLR + description: Set this bit to clear the I2C slave SCL stretch function. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: SLAVE_BYTE_ACK_CTL_EN + description: The enable bit for slave to control ACK level function. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SLAVE_BYTE_ACK_LVL + description: Set the ACK level when slave controlling ACK level function enables. + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version register + addressOffset: 248 + size: 32 + resetValue: 35656050 + fields: + - name: DATE + description: This is the the version register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TXFIFO_START_ADDR + description: I2C TXFIFO base address register + addressOffset: 256 + size: 32 + fields: + - name: TXFIFO_START_ADDR + description: This is the I2C txfifo first address. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RXFIFO_START_ADDR + description: I2C RXFIFO base address register + addressOffset: 384 + size: 32 + fields: + - name: RXFIFO_START_ADDR + description: This is the I2C rxfifo first address. + bitOffset: 0 + bitWidth: 32 + access: read-only + - name: I2C1 + description: I2C (Inter-Integrated Circuit) Controller 1 + baseAddress: 1610633216 + interrupt: + - name: I2C_EXT1 + value: 40 + derivedFrom: I2C0 + - name: I2S0 + description: I2S (Inter-IC Sound) Controller 0 + groupName: I2S + baseAddress: 1610665984 + addressBlock: + - offset: 0 + size: 96 + usage: registers + interrupt: + - name: I2S0 + value: 31 + registers: + - register: + name: INT_RAW + description: "I2S interrupt raw register, valid in level." + addressOffset: 12 + size: 32 + fields: + - name: RX_DONE_INT_RAW + description: The raw interrupt status bit for the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_RAW + description: The raw interrupt status bit for the i2s_tx_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_RAW + description: The raw interrupt status bit for the i2s_rx_hung_int interrupt + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_RAW + description: The raw interrupt status bit for the i2s_tx_hung_int interrupt + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: I2S interrupt status register. + addressOffset: 16 + size: 32 + fields: + - name: RX_DONE_INT_ST + description: The masked interrupt status bit for the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_ST + description: The masked interrupt status bit for the i2s_tx_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_ST + description: The masked interrupt status bit for the i2s_rx_hung_int interrupt + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_ST + description: The masked interrupt status bit for the i2s_tx_hung_int interrupt + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: I2S interrupt enable register. + addressOffset: 20 + size: 32 + fields: + - name: RX_DONE_INT_ENA + description: The interrupt enable bit for the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_ENA + description: The interrupt enable bit for the i2s_tx_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_HUNG_INT_ENA + description: The interrupt enable bit for the i2s_rx_hung_int interrupt + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_HUNG_INT_ENA + description: The interrupt enable bit for the i2s_tx_hung_int interrupt + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: I2S interrupt clear register. + addressOffset: 24 + size: 32 + fields: + - name: RX_DONE_INT_CLR + description: Set this bit to clear the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TX_DONE_INT_CLR + description: Set this bit to clear the i2s_tx_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_HUNG_INT_CLR + description: Set this bit to clear the i2s_rx_hung_int interrupt + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TX_HUNG_INT_CLR + description: Set this bit to clear the i2s_tx_hung_int interrupt + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: RX_CONF + description: I2S RX configure register + addressOffset: 32 + size: 32 + resetValue: 12629504 + fields: + - name: RX_RESET + description: Set this bit to reset receiver + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: RX_FIFO_RESET + description: Set this bit to reset Rx AFIFO + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_START + description: Set this bit to start receiving data + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_SLAVE_MOD + description: Set this bit to enable slave receiver mode + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_STOP_MODE + description: "0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: RX_MONO + description: Set this bit to enable receiver in mono mode + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_BIG_ENDIAN + description: "I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RX_UPDATE + description: Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RX_MONO_FST_VLD + description: "1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RX_PCM_CONF + description: "I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: RX_PCM_BYPASS + description: Set this bit to bypass Compress/Decompress module for received data. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RX_MSB_SHIFT + description: Set this bit to enable receiver in Phillips standard mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: RX_LEFT_ALIGN + description: "1: I2S RX left alignment mode. 0: I2S RX right alignment mode." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RX_24_FILL_EN + description: "1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RX_WS_IDLE_POL + description: "0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: RX_BIT_ORDER + description: "I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RX_TDM_EN + description: "1: Enable I2S TDM Rx mode . 0: Disable." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RX_PDM_EN + description: "1: Enable I2S PDM Rx mode . 0: Disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: RX_BCK_DIV_NUM + description: Bit clock configuration bits in receiver mode. + bitOffset: 21 + bitWidth: 6 + access: read-write + - register: + name: TX_CONF + description: I2S TX configure register + addressOffset: 36 + size: 32 + resetValue: 12644880 + fields: + - name: TX_RESET + description: Set this bit to reset transmitter + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TX_FIFO_RESET + description: Set this bit to reset Tx AFIFO + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TX_START + description: Set this bit to start transmitting data + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_SLAVE_MOD + description: Set this bit to enable slave transmitter mode + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_STOP_EN + description: Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TX_CHAN_EQUAL + description: "1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TX_MONO + description: Set this bit to enable transmitter in mono mode + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_BIG_ENDIAN + description: "I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TX_UPDATE + description: Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TX_MONO_FST_VLD + description: "1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TX_PCM_CONF + description: "I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: TX_PCM_BYPASS + description: Set this bit to bypass Compress/Decompress module for transmitted data. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_MSB_SHIFT + description: Set this bit to enable transmitter in Phillips standard mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_BCK_NO_DLY + description: "1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TX_LEFT_ALIGN + description: "1: I2S TX left alignment mode. 0: I2S TX right alignment mode." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TX_24_FILL_EN + description: "1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: TX_WS_IDLE_POL + description: "0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: TX_BIT_ORDER + description: "I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TX_TDM_EN + description: "1: Enable I2S TDM Tx mode . 0: Disable." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: TX_PDM_EN + description: "1: Enable I2S PDM Tx mode . 0: Disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TX_BCK_DIV_NUM + description: Bit clock configuration bits in transmitter mode. + bitOffset: 21 + bitWidth: 6 + access: read-write + - name: TX_CHAN_MOD + description: I2S transmitter channel mode configuration bits. + bitOffset: 27 + bitWidth: 3 + access: read-write + - name: SIG_LOOPBACK + description: Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: RX_CONF1 + description: I2S RX configure register 1 + addressOffset: 40 + size: 32 + resetValue: 2021376000 + fields: + - name: RX_TDM_WS_WIDTH + description: "The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * T_bck" + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: RX_BITS_MOD + description: "Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode." + bitOffset: 14 + bitWidth: 5 + access: read-write + - name: RX_HALF_SAMPLE_BITS + description: I2S Rx half sample bits -1. + bitOffset: 19 + bitWidth: 8 + access: read-write + - name: RX_TDM_CHAN_BITS + description: The Rx bit number for each channel minus 1in TDM mode. + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: TX_CONF1 + description: I2S TX configure register 1 + addressOffset: 44 + size: 32 + resetValue: 2021376000 + fields: + - name: TX_TDM_WS_WIDTH + description: "The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * T_bck" + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: TX_BITS_MOD + description: "Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode." + bitOffset: 14 + bitWidth: 5 + access: read-write + - name: TX_HALF_SAMPLE_BITS + description: I2S Tx half sample bits -1. + bitOffset: 19 + bitWidth: 8 + access: read-write + - name: TX_TDM_CHAN_BITS + description: The Tx bit number for each channel minus 1in TDM mode. + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: RX_CLKM_CONF + description: I2S RX clock configure register + addressOffset: 48 + size: 32 + resetValue: 2 + fields: + - name: RX_CLKM_DIV_NUM + description: Integral I2S clock divider value + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: RX_CLK_ACTIVE + description: I2S Rx module clock enable signal. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RX_CLK_SEL + description: "Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in." + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: MCLK_SEL + description: "0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT." + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: TX_CLKM_CONF + description: I2S TX clock configure register + addressOffset: 52 + size: 32 + resetValue: 2 + fields: + - name: TX_CLKM_DIV_NUM + description: "Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TX_CLK_ACTIVE + description: I2S Tx module clock enable signal. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TX_CLK_SEL + description: "Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in." + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: CLK_EN + description: Set this bit to enable clk gate + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: RX_CLKM_DIV_CONF + description: I2S RX module clock divider configure register + addressOffset: 56 + size: 32 + resetValue: 512 + fields: + - name: RX_CLKM_DIV_Z + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: RX_CLKM_DIV_Y + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))." + bitOffset: 9 + bitWidth: 9 + access: read-write + - name: RX_CLKM_DIV_X + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1." + bitOffset: 18 + bitWidth: 9 + access: read-write + - name: RX_CLKM_DIV_YN1 + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1." + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: TX_CLKM_DIV_CONF + description: I2S TX module clock divider configure register + addressOffset: 60 + size: 32 + resetValue: 512 + fields: + - name: TX_CLKM_DIV_Z + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: TX_CLKM_DIV_Y + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))." + bitOffset: 9 + bitWidth: 9 + access: read-write + - name: TX_CLKM_DIV_X + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1." + bitOffset: 18 + bitWidth: 9 + access: read-write + - name: TX_CLKM_DIV_YN1 + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1." + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: TX_PCM2PDM_CONF + description: I2S TX PCM2PDM configuration register + addressOffset: 64 + size: 32 + resetValue: 4890628 + fields: + - name: TX_PDM_HP_BYPASS + description: I2S TX PDM bypass hp filter or not. The option has been removed. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_PDM_SINC_OSR2 + description: I2S TX PDM OSR2 value + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: TX_PDM_PRESCALE + description: I2S TX PDM prescale for sigmadelta + bitOffset: 5 + bitWidth: 8 + access: read-write + - name: TX_PDM_HP_IN_SHIFT + description: "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4" + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: TX_PDM_LP_IN_SHIFT + description: "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4" + bitOffset: 15 + bitWidth: 2 + access: read-write + - name: TX_PDM_SINC_IN_SHIFT + description: "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4" + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: TX_PDM_SIGMADELTA_IN_SHIFT + description: "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4" + bitOffset: 19 + bitWidth: 2 + access: read-write + - name: TX_PDM_SIGMADELTA_DITHER2 + description: I2S TX PDM sigmadelta dither2 value + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: TX_PDM_SIGMADELTA_DITHER + description: I2S TX PDM sigmadelta dither value + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TX_PDM_DAC_2OUT_EN + description: I2S TX PDM dac mode enable + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TX_PDM_DAC_MODE_EN + description: I2S TX PDM dac 2channel enable + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PCM2PDM_CONV_EN + description: I2S TX PDM Converter enable + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: TX_PCM2PDM_CONF1 + description: I2S TX PCM2PDM configuration register + addressOffset: 68 + size: 32 + resetValue: 66552768 + fields: + - name: TX_PDM_FP + description: I2S TX PDM Fp + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: TX_PDM_FS + description: I2S TX PDM Fs + bitOffset: 10 + bitWidth: 10 + access: read-write + - name: TX_IIR_HP_MULT12_5 + description: "The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])" + bitOffset: 20 + bitWidth: 3 + access: read-write + - name: TX_IIR_HP_MULT12_0 + description: "The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])" + bitOffset: 23 + bitWidth: 3 + access: read-write + - register: + name: RX_TDM_CTRL + description: I2S TX TDM mode control register + addressOffset: 80 + size: 32 + resetValue: 65535 + fields: + - name: RX_TDM_PDM_CHAN0_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN1_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN2_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN3_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN4_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN5_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN6_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN7_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN8_EN + description: "1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN9_EN + description: "1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN10_EN + description: "1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN11_EN + description: "1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN12_EN + description: "1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN13_EN + description: "1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN14_EN + description: "1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN15_EN + description: "1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RX_TDM_TOT_CHAN_NUM + description: The total channel number of I2S TX TDM mode. + bitOffset: 16 + bitWidth: 4 + access: read-write + - register: + name: TX_TDM_CTRL + description: I2S TX TDM mode control register + addressOffset: 84 + size: 32 + resetValue: 65535 + fields: + - name: TX_TDM_CHAN0_EN + description: "1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN1_EN + description: "1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN2_EN + description: "1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN3_EN + description: "1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN4_EN + description: "1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN5_EN + description: "1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN6_EN + description: "1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN7_EN + description: "1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN8_EN + description: "1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN9_EN + description: "1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN10_EN + description: "1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN11_EN + description: "1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN12_EN + description: "1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN13_EN + description: "1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN14_EN + description: "1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN15_EN + description: "1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TX_TDM_TOT_CHAN_NUM + description: The total channel number of I2S TX TDM mode. + bitOffset: 16 + bitWidth: 4 + access: read-write + - name: TX_TDM_SKIP_MSK_EN + description: "When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels." + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: RX_TIMING + description: I2S RX timing control register + addressOffset: 88 + size: 32 + fields: + - name: RX_SD_IN_DM + description: "The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: RX_WS_OUT_DM + description: "The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: RX_BCK_OUT_DM + description: "The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: RX_WS_IN_DM + description: "The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: RX_BCK_IN_DM + description: "The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 28 + bitWidth: 2 + access: read-write + - register: + name: TX_TIMING + description: I2S TX timing control register + addressOffset: 92 + size: 32 + fields: + - name: TX_SD_OUT_DM + description: "The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: TX_SD1_OUT_DM + description: "The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: TX_WS_OUT_DM + description: "The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: TX_BCK_OUT_DM + description: "The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TX_WS_IN_DM + description: "The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: TX_BCK_IN_DM + description: "The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 28 + bitWidth: 2 + access: read-write + - register: + name: LC_HUNG_CONF + description: I2S HUNG configure register. + addressOffset: 96 + size: 32 + resetValue: 2064 + fields: + - name: LC_FIFO_TIMEOUT + description: the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: LC_FIFO_TIMEOUT_SHIFT + description: The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + bitOffset: 8 + bitWidth: 3 + access: read-write + - name: LC_FIFO_TIMEOUT_ENA + description: The enable bit for FIFO timeout + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: RXEOF_NUM + description: I2S RX data number control register. + addressOffset: 100 + size: 32 + resetValue: 64 + fields: + - name: RX_EOF_NUM + description: "The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel." + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: CONF_SIGLE_DATA + description: I2S signal data register + addressOffset: 104 + size: 32 + fields: + - name: SINGLE_DATA + description: The configured constant channel data to be sent out. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STATE + description: I2S TX status register + addressOffset: 108 + size: 32 + resetValue: 1 + fields: + - name: TX_IDLE + description: "1: i2s_tx is idle state. 0: i2s_tx is working." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: ETM_CONF + description: I2S ETM configure register + addressOffset: 112 + size: 32 + resetValue: 65600 + fields: + - name: ETM_TX_SEND_WORD_NUM + description: "I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event." + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: ETM_RX_RECEIVE_WORD_NUM + description: "I2S ETM receive x words event. When receiving word number of reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event." + bitOffset: 10 + bitWidth: 10 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 128 + size: 32 + resetValue: 35684944 + fields: + - name: DATE + description: I2S version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: INTERRUPT_CORE0 + description: Interrupt Controller (Core 0) + groupName: INTMTX_CORE0 + baseAddress: 1610678272 + addressBlock: + - offset: 0 + size: 280 + usage: registers + interrupt: + - name: FROM_CPU_INTR0 + value: 7 + - name: FROM_CPU_INTR1 + value: 8 + - name: FROM_CPU_INTR2 + value: 9 + - name: FROM_CPU_INTR3 + value: 10 + - name: CACHE + value: 13 + - name: CPU_PERI_TIMEOUT + value: 14 + - name: BT_MAC + value: 15 + - name: BT_BB + value: 16 + - name: BT_BB_NMI + value: 17 + - name: COEX + value: 18 + - name: BLE_TIMER + value: 19 + - name: BLE_SEC + value: 20 + - name: ZB_MAC + value: 21 + - name: ECDSA + value: 64 + registers: + - register: + name: PMU_INTR_MAP + description: register description + addressOffset: 0 + size: 32 + fields: + - name: PMU_INTR_MAP + description: CORE0_PMU_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: EFUSE_INTR_MAP + description: register description + addressOffset: 4 + size: 32 + fields: + - name: EFUSE_INTR_MAP + description: CORE0_EFUSE_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: LP_RTC_TIMER_INTR_MAP + description: register description + addressOffset: 8 + size: 32 + fields: + - name: LP_RTC_TIMER_INTR_MAP + description: CORE0_LP_RTC_TIMER_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: LP_BLE_TIMER_INTR_MAP + description: register description + addressOffset: 12 + size: 32 + fields: + - name: LP_BLE_TIMER_INTR_MAP + description: CORE0_LP_BLE_TIMER_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: LP_WDT_INTR_MAP + description: register description + addressOffset: 16 + size: 32 + fields: + - name: LP_WDT_INTR_MAP + description: CORE0_LP_WDT_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: LP_PERI_TIMEOUT_INTR_MAP + description: register description + addressOffset: 20 + size: 32 + fields: + - name: LP_PERI_TIMEOUT_INTR_MAP + description: CORE0_LP_PERI_TIMEOUT_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: LP_APM_M0_INTR_MAP + description: register description + addressOffset: 24 + size: 32 + fields: + - name: LP_APM_M0_INTR_MAP + description: CORE0_LP_APM_M0_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_0_MAP + description: register description + addressOffset: 28 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_0_MAP + description: CORE0_CPU_INTR_FROM_CPU_0 mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_1_MAP + description: register description + addressOffset: 32 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_1_MAP + description: CORE0_CPU_INTR_FROM_CPU_1 mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_2_MAP + description: register description + addressOffset: 36 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_2_MAP + description: CORE0_CPU_INTR_FROM_CPU_2 mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_3_MAP + description: register description + addressOffset: 40 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_3_MAP + description: CORE0_CPU_INTR_FROM_CPU_3 mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: ASSIST_DEBUG_INTR_MAP + description: register description + addressOffset: 44 + size: 32 + fields: + - name: ASSIST_DEBUG_INTR_MAP + description: CORE0_ASSIST_DEBUG_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TRACE_INTR_MAP + description: register description + addressOffset: 48 + size: 32 + fields: + - name: TRACE_INTR_MAP + description: CORE0_TRACE_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CACHE_INTR_MAP + description: register description + addressOffset: 52 + size: 32 + fields: + - name: CACHE_INTR_MAP + description: CORE0_CACHE_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_PERI_TIMEOUT_INTR_MAP + description: register description + addressOffset: 56 + size: 32 + fields: + - name: CPU_PERI_TIMEOUT_INTR_MAP + description: CORE0_CPU_PERI_TIMEOUT_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BT_MAC_INTR_MAP + description: register description + addressOffset: 60 + size: 32 + fields: + - name: BT_MAC_INTR_MAP + description: CORE0_BT_MAC_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BT_BB_INTR_MAP + description: register description + addressOffset: 64 + size: 32 + fields: + - name: BT_BB_INTR_MAP + description: CORE0_BT_BB_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BT_BB_NMI_MAP + description: register description + addressOffset: 68 + size: 32 + fields: + - name: BT_BB_NMI_MAP + description: CORE0_BT_BB_NMI mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: COEX_INTR_MAP + description: register description + addressOffset: 72 + size: 32 + fields: + - name: COEX_INTR_MAP + description: CORE0_COEX_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BLE_TIMER_INTR_MAP + description: register description + addressOffset: 76 + size: 32 + fields: + - name: BLE_TIMER_INTR_MAP + description: CORE0_BLE_TIMER_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BLE_SEC_INTR_MAP + description: register description + addressOffset: 80 + size: 32 + fields: + - name: BLE_SEC_INTR_MAP + description: CORE0_BLE_SEC_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: ZB_MAC_INTR_MAP + description: register description + addressOffset: 84 + size: 32 + fields: + - name: ZB_MAC_INTR_MAP + description: CORE0_ZB_MAC_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: GPIO_INTERRUPT_PRO_MAP + description: register description + addressOffset: 88 + size: 32 + fields: + - name: GPIO_INTERRUPT_PRO_MAP + description: CORE0_GPIO_INTERRUPT_PRO mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: GPIO_INTERRUPT_PRO_NMI_MAP + description: register description + addressOffset: 92 + size: 32 + fields: + - name: GPIO_INTERRUPT_PRO_NMI_MAP + description: CORE0_GPIO_INTERRUPT_PRO_NMI mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PAU_INTR_MAP + description: register description + addressOffset: 96 + size: 32 + fields: + - name: PAU_INTR_MAP + description: CORE0_PAU_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: HP_PERI_TIMEOUT_INTR_MAP + description: register description + addressOffset: 100 + size: 32 + fields: + - name: HP_PERI_TIMEOUT_INTR_MAP + description: CORE0_HP_PERI_TIMEOUT_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: HP_APM_M0_INTR_MAP + description: register description + addressOffset: 104 + size: 32 + fields: + - name: HP_APM_M0_INTR_MAP + description: CORE0_HP_APM_M0_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: HP_APM_M1_INTR_MAP + description: register description + addressOffset: 108 + size: 32 + fields: + - name: HP_APM_M1_INTR_MAP + description: CORE0_HP_APM_M1_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: HP_APM_M2_INTR_MAP + description: register description + addressOffset: 112 + size: 32 + fields: + - name: HP_APM_M2_INTR_MAP + description: CORE0_HP_APM_M2_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: HP_APM_M3_INTR_MAP + description: register description + addressOffset: 116 + size: 32 + fields: + - name: HP_APM_M3_INTR_MAP + description: CORE0_HP_APM_M3_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: MSPI_INTR_MAP + description: register description + addressOffset: 120 + size: 32 + fields: + - name: MSPI_INTR_MAP + description: CORE0_MSPI_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: I2S1_INTR_MAP + description: register description + addressOffset: 124 + size: 32 + fields: + - name: I2S1_INTR_MAP + description: CORE0_I2S1_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: UHCI0_INTR_MAP + description: register description + addressOffset: 128 + size: 32 + fields: + - name: UHCI0_INTR_MAP + description: CORE0_UHCI0_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: UART0_INTR_MAP + description: register description + addressOffset: 132 + size: 32 + fields: + - name: UART0_INTR_MAP + description: CORE0_UART0_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: UART1_INTR_MAP + description: register description + addressOffset: 136 + size: 32 + fields: + - name: UART1_INTR_MAP + description: CORE0_UART1_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: LEDC_INTR_MAP + description: register description + addressOffset: 140 + size: 32 + fields: + - name: LEDC_INTR_MAP + description: CORE0_LEDC_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CAN0_INTR_MAP + description: register description + addressOffset: 144 + size: 32 + fields: + - name: CAN0_INTR_MAP + description: CORE0_CAN0_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: USB_INTR_MAP + description: register description + addressOffset: 148 + size: 32 + fields: + - name: USB_INTR_MAP + description: CORE0_USB_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RMT_INTR_MAP + description: register description + addressOffset: 152 + size: 32 + fields: + - name: RMT_INTR_MAP + description: CORE0_RMT_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: I2C_EXT0_INTR_MAP + description: register description + addressOffset: 156 + size: 32 + fields: + - name: I2C_EXT0_INTR_MAP + description: CORE0_I2C_EXT0_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: I2C_EXT1_INTR_MAP + description: register description + addressOffset: 160 + size: 32 + fields: + - name: I2C_EXT1_INTR_MAP + description: CORE0_I2C_EXT1_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG0_T0_INTR_MAP + description: register description + addressOffset: 164 + size: 32 + fields: + - name: TG0_T0_INTR_MAP + description: CORE0_TG0_T0_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG0_WDT_INTR_MAP + description: register description + addressOffset: 168 + size: 32 + fields: + - name: TG0_WDT_INTR_MAP + description: CORE0_TG0_WDT_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG1_T0_INTR_MAP + description: register description + addressOffset: 172 + size: 32 + fields: + - name: TG1_T0_INTR_MAP + description: CORE0_TG1_T0_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG1_WDT_INTR_MAP + description: register description + addressOffset: 176 + size: 32 + fields: + - name: TG1_WDT_INTR_MAP + description: CORE0_TG1_WDT_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SYSTIMER_TARGET0_INTR_MAP + description: register description + addressOffset: 180 + size: 32 + fields: + - name: SYSTIMER_TARGET0_INTR_MAP + description: CORE0_SYSTIMER_TARGET0_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SYSTIMER_TARGET1_INTR_MAP + description: register description + addressOffset: 184 + size: 32 + fields: + - name: SYSTIMER_TARGET1_INTR_MAP + description: CORE0_SYSTIMER_TARGET1_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SYSTIMER_TARGET2_INTR_MAP + description: register description + addressOffset: 188 + size: 32 + fields: + - name: SYSTIMER_TARGET2_INTR_MAP + description: CORE0_SYSTIMER_TARGET2_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APB_ADC_INTR_MAP + description: register description + addressOffset: 192 + size: 32 + fields: + - name: APB_ADC_INTR_MAP + description: CORE0_APB_ADC_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PWM_INTR_MAP + description: register description + addressOffset: 196 + size: 32 + fields: + - name: PWM_INTR_MAP + description: CORE0_PWM_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PCNT_INTR_MAP + description: register description + addressOffset: 200 + size: 32 + fields: + - name: PCNT_INTR_MAP + description: CORE0_PCNT_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PARL_IO_TX_INTR_MAP + description: register description + addressOffset: 204 + size: 32 + fields: + - name: PARL_IO_TX_INTR_MAP + description: CORE0_PARL_IO_TX_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PARL_IO_RX_INTR_MAP + description: register description + addressOffset: 208 + size: 32 + fields: + - name: PARL_IO_RX_INTR_MAP + description: CORE0_PARL_IO_RX_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_IN_CH0_INTR_MAP + description: register description + addressOffset: 212 + size: 32 + fields: + - name: DMA_IN_CH0_INTR_MAP + description: CORE0_DMA_IN_CH0_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_IN_CH1_INTR_MAP + description: register description + addressOffset: 216 + size: 32 + fields: + - name: DMA_IN_CH1_INTR_MAP + description: CORE0_DMA_IN_CH1_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_IN_CH2_INTR_MAP + description: register description + addressOffset: 220 + size: 32 + fields: + - name: DMA_IN_CH2_INTR_MAP + description: CORE0_DMA_IN_CH2_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_OUT_CH0_INTR_MAP + description: register description + addressOffset: 224 + size: 32 + fields: + - name: DMA_OUT_CH0_INTR_MAP + description: CORE0_DMA_OUT_CH0_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_OUT_CH1_INTR_MAP + description: register description + addressOffset: 228 + size: 32 + fields: + - name: DMA_OUT_CH1_INTR_MAP + description: CORE0_DMA_OUT_CH1_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_OUT_CH2_INTR_MAP + description: register description + addressOffset: 232 + size: 32 + fields: + - name: DMA_OUT_CH2_INTR_MAP + description: CORE0_DMA_OUT_CH2_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: GPSPI2_INTR_MAP + description: register description + addressOffset: 236 + size: 32 + fields: + - name: GPSPI2_INTR_MAP + description: CORE0_GPSPI2_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: AES_INTR_MAP + description: register description + addressOffset: 240 + size: 32 + fields: + - name: AES_INTR_MAP + description: CORE0_AES_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SHA_INTR_MAP + description: register description + addressOffset: 244 + size: 32 + fields: + - name: SHA_INTR_MAP + description: CORE0_SHA_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RSA_INTR_MAP + description: register description + addressOffset: 248 + size: 32 + fields: + - name: RSA_INTR_MAP + description: CORE0_RSA_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: ECC_INTR_MAP + description: register description + addressOffset: 252 + size: 32 + fields: + - name: ECC_INTR_MAP + description: CORE0_ECC_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: ECDSA_INTR_MAP + description: register description + addressOffset: 256 + size: 32 + fields: + - name: ECDSA_INTR_MAP + description: CORE0_ECDSA_INTR mapping register + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: INTR_STATUS_REG_0 + description: register description + addressOffset: 260 + size: 32 + fields: + - name: INTR_STATUS_0 + description: Status register for interrupt sources 0~31 mapping register + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INTR_STATUS_REG_1 + description: register description + addressOffset: 264 + size: 32 + fields: + - name: INTR_STATUS_1 + description: Status register for interrupt sources 32~63 mapping register + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INT_STATUS_REG_2 + description: register description + addressOffset: 268 + size: 32 + fields: + - name: INT_STATUS_2 + description: Status register for interrupt sources 64~95 mapping register + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CLOCK_GATE + description: register description + addressOffset: 272 + size: 32 + resetValue: 1 + fields: + - name: REG_CLK_EN + description: Clock register + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: INTERRUPT_REG_DATE + description: register description + addressOffset: 2044 + size: 32 + resetValue: 35688784 + fields: + - name: INTERRUPT_REG_DATE + description: Version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: INTPRI + description: INTPRI Peripheral + groupName: INTPRI + baseAddress: 1611419648 + addressBlock: + - offset: 0 + size: 184 + usage: registers + registers: + - register: + name: CPU_INT_ENABLE + description: register description + addressOffset: 0 + size: 32 + fields: + - name: CPU_INT_ENABLE + description: Need add description + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CPU_INT_TYPE + description: register description + addressOffset: 4 + size: 32 + fields: + - name: CPU_INT_TYPE + description: Need add description + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CPU_INT_EIP_STATUS + description: register description + addressOffset: 8 + size: 32 + fields: + - name: CPU_INT_EIP_STATUS + description: Need add description + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CPU_INT_PRI_0 + description: register description + addressOffset: 12 + size: 32 + fields: + - name: CPU_PRI_0_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_1 + description: register description + addressOffset: 16 + size: 32 + fields: + - name: CPU_PRI_1_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_2 + description: register description + addressOffset: 20 + size: 32 + fields: + - name: CPU_PRI_2_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_3 + description: register description + addressOffset: 24 + size: 32 + fields: + - name: CPU_PRI_3_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_4 + description: register description + addressOffset: 28 + size: 32 + fields: + - name: CPU_PRI_4_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_5 + description: register description + addressOffset: 32 + size: 32 + fields: + - name: CPU_PRI_5_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_6 + description: register description + addressOffset: 36 + size: 32 + fields: + - name: CPU_PRI_6_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_7 + description: register description + addressOffset: 40 + size: 32 + fields: + - name: CPU_PRI_7_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_8 + description: register description + addressOffset: 44 + size: 32 + fields: + - name: CPU_PRI_8_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_9 + description: register description + addressOffset: 48 + size: 32 + fields: + - name: CPU_PRI_9_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_10 + description: register description + addressOffset: 52 + size: 32 + fields: + - name: CPU_PRI_10_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_11 + description: register description + addressOffset: 56 + size: 32 + fields: + - name: CPU_PRI_11_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_12 + description: register description + addressOffset: 60 + size: 32 + fields: + - name: CPU_PRI_12_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_13 + description: register description + addressOffset: 64 + size: 32 + fields: + - name: CPU_PRI_13_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_14 + description: register description + addressOffset: 68 + size: 32 + fields: + - name: CPU_PRI_14_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_15 + description: register description + addressOffset: 72 + size: 32 + fields: + - name: CPU_PRI_15_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_16 + description: register description + addressOffset: 76 + size: 32 + fields: + - name: CPU_PRI_16_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_17 + description: register description + addressOffset: 80 + size: 32 + fields: + - name: CPU_PRI_17_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_18 + description: register description + addressOffset: 84 + size: 32 + fields: + - name: CPU_PRI_18_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_19 + description: register description + addressOffset: 88 + size: 32 + fields: + - name: CPU_PRI_19_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_20 + description: register description + addressOffset: 92 + size: 32 + fields: + - name: CPU_PRI_20_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_21 + description: register description + addressOffset: 96 + size: 32 + fields: + - name: CPU_PRI_21_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_22 + description: register description + addressOffset: 100 + size: 32 + fields: + - name: CPU_PRI_22_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_23 + description: register description + addressOffset: 104 + size: 32 + fields: + - name: CPU_PRI_23_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_24 + description: register description + addressOffset: 108 + size: 32 + fields: + - name: CPU_PRI_24_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_25 + description: register description + addressOffset: 112 + size: 32 + fields: + - name: CPU_PRI_25_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_26 + description: register description + addressOffset: 116 + size: 32 + fields: + - name: CPU_PRI_26_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_27 + description: register description + addressOffset: 120 + size: 32 + fields: + - name: CPU_PRI_27_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_28 + description: register description + addressOffset: 124 + size: 32 + fields: + - name: CPU_PRI_28_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_29 + description: register description + addressOffset: 128 + size: 32 + fields: + - name: CPU_PRI_29_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_30 + description: register description + addressOffset: 132 + size: 32 + fields: + - name: CPU_PRI_30_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_PRI_31 + description: register description + addressOffset: 136 + size: 32 + fields: + - name: CPU_PRI_31_MAP + description: Need add description + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CPU_INT_THRESH + description: register description + addressOffset: 140 + size: 32 + fields: + - name: CPU_INT_THRESH + description: Need add description + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_0 + description: register description + addressOffset: 144 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_0 + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_1 + description: register description + addressOffset: 148 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_1 + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_2 + description: register description + addressOffset: 152 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_2 + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_3 + description: register description + addressOffset: 156 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_3 + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: register description + addressOffset: 160 + size: 32 + resetValue: 35655824 + fields: + - name: DATE + description: Need add description + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + name: CLOCK_GATE + description: register description + addressOffset: 164 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: Need add description + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INT_CLEAR + description: register description + addressOffset: 168 + size: 32 + fields: + - name: CPU_INT_CLEAR + description: Need add description + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RND_ECO + description: redcy eco register. + addressOffset: 172 + size: 32 + fields: + - name: REDCY_ENA + description: Only reserved for ECO. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REDCY_RESULT + description: Only reserved for ECO. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: RND_ECO_LOW + description: redcy eco low register. + addressOffset: 176 + size: 32 + fields: + - name: REDCY_LOW + description: Only reserved for ECO. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RND_ECO_HIGH + description: redcy eco high register. + addressOffset: 1020 + size: 32 + resetValue: 4294967295 + fields: + - name: REDCY_HIGH + description: Only reserved for ECO. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: IO_MUX + description: Input/Output Multiplexer + groupName: IO_MUX + baseAddress: 1611202560 + addressBlock: + - offset: 0 + size: 124 + usage: registers + registers: + - register: + name: PIN_CTRL + description: Clock Output Configuration Register + addressOffset: 0 + size: 32 + resetValue: 7663 + fields: + - name: CLK_OUT1 + description: "If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals." + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: CLK_OUT2 + description: "If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals." + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: CLK_OUT3 + description: "If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals." + bitOffset: 10 + bitWidth: 5 + access: read-write + - register: + dim: 28 + dimIncrement: 4 + name: GPIO%s + description: IO MUX Configure Register for pad GPIO0 + addressOffset: 4 + size: 32 + resetValue: 2048 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCU_DRV + description: "Select the drive strength of the pad during sleep mode. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA." + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled. 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. 0: ~5 mA. 1: ~10mA. 2: ~20mA. 3: ~40mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: HYS_EN + description: "Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: Hysteresis disabled." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: HYS_SEL + description: "Select enabling signals of the pad from software and efuse hardware. 1: Select enabling siganl from slftware. 0: Select enabling signal from efuse hardware." + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: MODEM_DIAG_EN + description: GPIO MATRIX Configure Register for modem diag + addressOffset: 188 + size: 32 + fields: + - name: MODEM_DIAG_EN + description: "bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i] into gpio matrix. 0:enable other signals into gpio matrix" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DATE + description: IO MUX Version Control Register + addressOffset: 252 + size: 32 + resetValue: 35680880 + fields: + - name: REG_DATE + description: Version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: LEDC + description: LED Control PWM (Pulse Width Modulation) + groupName: LEDC + baseAddress: 1610645504 + addressBlock: + - offset: 0 + size: 340 + usage: registers + interrupt: + - name: LEDC + value: 35 + registers: + - register: + dim: 6 + dimIncrement: 20 + name: CH%s_CONF0 + description: Configuration register 0 for channel %s + addressOffset: 0 + size: 32 + fields: + - name: TIMER_SEL + description: "This field is used to select one of timers for channel %s.\n\n0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SIG_OUT_EN + description: Set this bit to enable signal output on channel %s. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IDLE_LV + description: This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0). + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PARA_UP + description: "This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware." + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: OVF_NUM + description: "This register is used to configure the maximum times of overflow minus 1.\n\nThe LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times." + bitOffset: 5 + bitWidth: 10 + access: read-write + - name: OVF_CNT_EN + description: This bit is used to enable the ovf_cnt of channel %s. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: OVF_CNT_RESET + description: Set this bit to reset the ovf_cnt of channel %s. + bitOffset: 16 + bitWidth: 1 + access: write-only + - register: + dim: 6 + dimIncrement: 20 + name: CH%s_HPOINT + description: High point register for channel %s + addressOffset: 4 + size: 32 + fields: + - name: HPOINT + description: The output value changes to high when the selected timers has reached the value specified by this register. + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + dim: 6 + dimIncrement: 20 + name: CH%s_DUTY + description: Initial duty cycle for channel %s + addressOffset: 8 + size: 32 + fields: + - name: DUTY + description: "This register is used to change the output duty by controlling the Lpoint.\n\nThe output value turns to low when the selected timers has reached the Lpoint." + bitOffset: 0 + bitWidth: 25 + access: read-write + - register: + dim: 6 + dimIncrement: 20 + name: CH%s_CONF1 + description: Configuration register 1 for channel %s + addressOffset: 12 + size: 32 + fields: + - name: DUTY_START + description: Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + dim: 6 + dimIncrement: 20 + name: CH%s_DUTY_R + description: Current duty cycle for channel %s + addressOffset: 16 + size: 32 + fields: + - name: DUTY_CH_R + description: This register stores the current duty of output signal on channel %s. + bitOffset: 0 + bitWidth: 25 + access: read-only + - register: + dim: 4 + dimIncrement: 8 + name: TIMER%s_CONF + description: Timer %s configuration + addressOffset: 160 + size: 32 + resetValue: 16777216 + fields: + - name: DUTY_RES + description: This register is used to control the range of the counter in timer %s. + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: CLK_DIV + description: "This register is used to configure the divisor for the divider in timer %s.\n\nThe least significant eight bits represent the fractional part." + bitOffset: 5 + bitWidth: 18 + access: read-write + - name: PAUSE + description: This bit is used to suspend the counter in timer %s. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: RST + description: This bit is used to reset timer %s. The counter will show 0 after reset. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TICK_SEL + description: "This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate.\n\n1'h0: SLOW_CLK 1'h1: REF_TICK" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PARA_UP + description: Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES. + bitOffset: 26 + bitWidth: 1 + access: write-only + - register: + dim: 4 + dimIncrement: 8 + name: TIMER%s_VALUE + description: Timer %s current counter value + addressOffset: 164 + size: 32 + fields: + - name: TIMER_CNT + description: This register stores the current counter value of timer %s. + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 192 + size: 32 + fields: + - name: TIMER0_OVF_INT_RAW + description: Triggered when the timer0 has reached its maximum counter value. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMER1_OVF_INT_RAW + description: Triggered when the timer1 has reached its maximum counter value. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER2_OVF_INT_RAW + description: Triggered when the timer2 has reached its maximum counter value. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TIMER3_OVF_INT_RAW + description: Triggered when the timer3 has reached its maximum counter value. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH0_INT_RAW + description: Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH1_INT_RAW + description: Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH2_INT_RAW + description: Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH3_INT_RAW + description: Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH4_INT_RAW + description: Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH5_INT_RAW + description: Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH0_INT_RAW + description: Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH1_INT_RAW + description: Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH2_INT_RAW + description: Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH3_INT_RAW + description: Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH4_INT_RAW + description: Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH5_INT_RAW + description: Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 196 + size: 32 + fields: + - name: TIMER0_OVF_INT_ST + description: This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TIMER1_OVF_INT_ST + description: This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TIMER2_OVF_INT_ST + description: This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TIMER3_OVF_INT_ST + description: This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH0_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH1_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH2_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH3_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH4_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH5_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH0_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH1_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH2_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH3_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH4_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH5_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + bitOffset: 17 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 200 + size: 32 + fields: + - name: TIMER0_OVF_INT_ENA + description: The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMER1_OVF_INT_ENA + description: The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER2_OVF_INT_ENA + description: The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TIMER3_OVF_INT_ENA + description: The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH0_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH1_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH2_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH3_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH4_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH5_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH0_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH1_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH2_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH3_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH4_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH5_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 204 + size: 32 + fields: + - name: TIMER0_OVF_INT_CLR + description: Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TIMER1_OVF_INT_CLR + description: Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TIMER2_OVF_INT_CLR + description: Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TIMER3_OVF_INT_CLR + description: Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH0_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH1_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH2_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH3_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH4_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH5_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH0_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH1_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH2_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH3_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH4_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH5_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - register: + dim: 6 + dimIncrement: 16 + name: CH%s_GAMMA_WR + description: Ledc ch%s gamma ram write register. + addressOffset: 256 + size: 32 + fields: + - name: CH_GAMMA_DUTY_INC + description: "Ledc ch%s gamma duty inc of current ram write address.This register is used to increase or decrease the duty of output signal on channel %s. \n\n1: Increase 0: Decrease." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CH_GAMMA_DUTY_CYCLE + description: Ledc ch%s gamma duty cycle of current ram write address.The duty will change every LEDC_CH%s_GAMMA_DUTY_CYCLE on channel %s. + bitOffset: 1 + bitWidth: 10 + access: read-write + - name: CH_GAMMA_SCALE + description: Ledc ch%s gamma scale of current ram write address.This register is used to configure the changing step scale of duty on channel %s. + bitOffset: 11 + bitWidth: 10 + access: read-write + - name: CH_GAMMA_DUTY_NUM + description: Ledc ch%s gamma duty num of current ram write address.This register is used to control the number of times the duty cycle will be changed. + bitOffset: 21 + bitWidth: 10 + access: read-write + - register: + dim: 6 + dimIncrement: 16 + name: CH%s_GAMMA_WR_ADDR + description: Ledc ch%s gamma ram write address register. + addressOffset: 260 + size: 32 + fields: + - name: CH_GAMMA_WR_ADDR + description: Ledc ch%s gamma ram write address. + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + dim: 6 + dimIncrement: 16 + name: CH%s_GAMMA_RD_ADDR + description: Ledc ch%s gamma ram read address register. + addressOffset: 264 + size: 32 + fields: + - name: CH_GAMMA_RD_ADDR + description: Ledc ch%s gamma ram read address. + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + dim: 6 + dimIncrement: 16 + name: CH%s_GAMMA_RD_DATA + description: Ledc ch%s gamma ram read data register. + addressOffset: 268 + size: 32 + fields: + - name: CH_GAMMA_RD_DATA + description: Ledc ch%s gamma ram read data. + bitOffset: 0 + bitWidth: 31 + access: read-only + - register: + dim: 6 + dimIncrement: 4 + name: CH%s_GAMMA_CONF + description: Ledc ch%s gamma config register. + addressOffset: 384 + size: 32 + fields: + - name: CH_GAMMA_ENTRY_NUM + description: Ledc ch%s gamma entry num. + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: CH_GAMMA_PAUSE + description: "Ledc ch%s gamma pause, write 1 to pause." + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CH_GAMMA_RESUME + description: "Ledc ch%s gamma resume, write 1 to resume." + bitOffset: 6 + bitWidth: 1 + access: write-only + - register: + name: EVT_TASK_EN0 + description: Ledc event task enable bit register0. + addressOffset: 416 + size: 32 + fields: + - name: EVT_DUTY_CHNG_END_CH0_EN + description: "Ledc ch0 duty change end event enable register, write 1 to enable this event." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EVT_DUTY_CHNG_END_CH1_EN + description: "Ledc ch1 duty change end event enable register, write 1 to enable this event." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EVT_DUTY_CHNG_END_CH2_EN + description: "Ledc ch2 duty change end event enable register, write 1 to enable this event." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EVT_DUTY_CHNG_END_CH3_EN + description: "Ledc ch3 duty change end event enable register, write 1 to enable this event." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: EVT_DUTY_CHNG_END_CH4_EN + description: "Ledc ch4 duty change end event enable register, write 1 to enable this event." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: EVT_DUTY_CHNG_END_CH5_EN + description: "Ledc ch5 duty change end event enable register, write 1 to enable this event." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: EVT_OVF_CNT_PLS_CH0_EN + description: "Ledc ch0 overflow count pulse event enable register, write 1 to enable this event." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: EVT_OVF_CNT_PLS_CH1_EN + description: "Ledc ch1 overflow count pulse event enable register, write 1 to enable this event." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: EVT_OVF_CNT_PLS_CH2_EN + description: "Ledc ch2 overflow count pulse event enable register, write 1 to enable this event." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: EVT_OVF_CNT_PLS_CH3_EN + description: "Ledc ch3 overflow count pulse event enable register, write 1 to enable this event." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: EVT_OVF_CNT_PLS_CH4_EN + description: "Ledc ch4 overflow count pulse event enable register, write 1 to enable this event." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: EVT_OVF_CNT_PLS_CH5_EN + description: "Ledc ch5 overflow count pulse event enable register, write 1 to enable this event." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: EVT_TIME_OVF_TIMER0_EN + description: "Ledc timer0 overflow event enable register, write 1 to enable this event." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: EVT_TIME_OVF_TIMER1_EN + description: "Ledc timer1 overflow event enable register, write 1 to enable this event." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: EVT_TIME_OVF_TIMER2_EN + description: "Ledc timer2 overflow event enable register, write 1 to enable this event." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: EVT_TIME_OVF_TIMER3_EN + description: "Ledc timer3 overflow event enable register, write 1 to enable this event." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: EVT_TIME0_CMP_EN + description: "Ledc timer0 compare event enable register, write 1 to enable this event." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: EVT_TIME1_CMP_EN + description: "Ledc timer1 compare event enable register, write 1 to enable this event." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: EVT_TIME2_CMP_EN + description: "Ledc timer2 compare event enable register, write 1 to enable this event." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: EVT_TIME3_CMP_EN + description: "Ledc timer3 compare event enable register, write 1 to enable this event." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TASK_DUTY_SCALE_UPDATE_CH0_EN + description: "Ledc ch0 duty scale update task enable register, write 1 to enable this task." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TASK_DUTY_SCALE_UPDATE_CH1_EN + description: "Ledc ch1 duty scale update task enable register, write 1 to enable this task." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TASK_DUTY_SCALE_UPDATE_CH2_EN + description: "Ledc ch2 duty scale update task enable register, write 1 to enable this task." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TASK_DUTY_SCALE_UPDATE_CH3_EN + description: "Ledc ch3 duty scale update task enable register, write 1 to enable this task." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: TASK_DUTY_SCALE_UPDATE_CH4_EN + description: "Ledc ch4 duty scale update task enable register, write 1 to enable this task." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: TASK_DUTY_SCALE_UPDATE_CH5_EN + description: "Ledc ch5 duty scale update task enable register, write 1 to enable this task." + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: EVT_TASK_EN1 + description: Ledc event task enable bit register1. + addressOffset: 420 + size: 32 + fields: + - name: TASK_TIMER0_RES_UPDATE_EN + description: "Ledc timer0 res update task enable register, write 1 to enable this task." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TASK_TIMER1_RES_UPDATE_EN + description: "Ledc timer1 res update task enable register, write 1 to enable this task." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TASK_TIMER2_RES_UPDATE_EN + description: "Ledc timer2 res update task enable register, write 1 to enable this task." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TASK_TIMER3_RES_UPDATE_EN + description: "Ledc timer3 res update task enable register, write 1 to enable this task." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TASK_TIMER0_CAP_EN + description: "Ledc timer0 capture task enable register, write 1 to enable this task." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TASK_TIMER1_CAP_EN + description: "Ledc timer1 capture task enable register, write 1 to enable this task." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TASK_TIMER2_CAP_EN + description: "Ledc timer2 capture task enable register, write 1 to enable this task." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TASK_TIMER3_CAP_EN + description: "Ledc timer3 capture task enable register, write 1 to enable this task." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TASK_SIG_OUT_DIS_CH0_EN + description: "Ledc ch0 signal out disable task enable register, write 1 to enable this task." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TASK_SIG_OUT_DIS_CH1_EN + description: "Ledc ch1 signal out disable task enable register, write 1 to enable this task." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TASK_SIG_OUT_DIS_CH2_EN + description: "Ledc ch2 signal out disable task enable register, write 1 to enable this task." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TASK_SIG_OUT_DIS_CH3_EN + description: "Ledc ch3 signal out disable task enable register, write 1 to enable this task." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TASK_SIG_OUT_DIS_CH4_EN + description: "Ledc ch4 signal out disable task enable register, write 1 to enable this task." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TASK_SIG_OUT_DIS_CH5_EN + description: "Ledc ch5 signal out disable task enable register, write 1 to enable this task." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TASK_OVF_CNT_RST_CH0_EN + description: "Ledc ch0 overflow count reset task enable register, write 1 to enable this task." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: TASK_OVF_CNT_RST_CH1_EN + description: "Ledc ch1 overflow count reset task enable register, write 1 to enable this task." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: TASK_OVF_CNT_RST_CH2_EN + description: "Ledc ch2 overflow count reset task enable register, write 1 to enable this task." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TASK_OVF_CNT_RST_CH3_EN + description: "Ledc ch3 overflow count reset task enable register, write 1 to enable this task." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: TASK_OVF_CNT_RST_CH4_EN + description: "Ledc ch4 overflow count reset task enable register, write 1 to enable this task." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TASK_OVF_CNT_RST_CH5_EN + description: "Ledc ch5 overflow count reset task enable register, write 1 to enable this task." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: TASK_TIMER0_RST_EN + description: "Ledc timer0 reset task enable register, write 1 to enable this task." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TASK_TIMER1_RST_EN + description: "Ledc timer1 reset task enable register, write 1 to enable this task." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TASK_TIMER2_RST_EN + description: "Ledc timer2 reset task enable register, write 1 to enable this task." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TASK_TIMER3_RST_EN + description: "Ledc timer3 reset task enable register, write 1 to enable this task." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: TASK_TIMER0_PAUSE_RESUME_EN + description: "Ledc timer0 pause resume task enable register, write 1 to enable this task." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: TASK_TIMER1_PAUSE_RESUME_EN + description: "Ledc timer1 pause resume task enable register, write 1 to enable this task." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TASK_TIMER2_PAUSE_RESUME_EN + description: "Ledc timer2 pause resume task enable register, write 1 to enable this task." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TASK_TIMER3_PAUSE_RESUME_EN + description: "Ledc timer3 pause resume task enable register, write 1 to enable this task." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EVT_TASK_EN2 + description: Ledc event task enable bit register2. + addressOffset: 424 + size: 32 + fields: + - name: TASK_GAMMA_RESTART_CH0_EN + description: "Ledc ch0 gamma restart task enable register, write 1 to enable this task." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESTART_CH1_EN + description: "Ledc ch1 gamma restart task enable register, write 1 to enable this task." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESTART_CH2_EN + description: "Ledc ch2 gamma restart task enable register, write 1 to enable this task." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESTART_CH3_EN + description: "Ledc ch3 gamma restart task enable register, write 1 to enable this task." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESTART_CH4_EN + description: "Ledc ch4 gamma restart task enable register, write 1 to enable this task." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESTART_CH5_EN + description: "Ledc ch5 gamma restart task enable register, write 1 to enable this task." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_PAUSE_CH0_EN + description: "Ledc ch0 gamma pause task enable register, write 1 to enable this task." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_PAUSE_CH1_EN + description: "Ledc ch1 gamma pause task enable register, write 1 to enable this task." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_PAUSE_CH2_EN + description: "Ledc ch2 gamma pause task enable register, write 1 to enable this task." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_PAUSE_CH3_EN + description: "Ledc ch3 gamma pause task enable register, write 1 to enable this task." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_PAUSE_CH4_EN + description: "Ledc ch4 gamma pause task enable register, write 1 to enable this task." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_PAUSE_CH5_EN + description: "Ledc ch5 gamma pause task enable register, write 1 to enable this task." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESUME_CH0_EN + description: "Ledc ch0 gamma resume task enable register, write 1 to enable this task." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESUME_CH1_EN + description: "Ledc ch1 gamma resume task enable register, write 1 to enable this task." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESUME_CH2_EN + description: "Ledc ch2 gamma resume task enable register, write 1 to enable this task." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESUME_CH3_EN + description: "Ledc ch3 gamma resume task enable register, write 1 to enable this task." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESUME_CH4_EN + description: "Ledc ch4 gamma resume task enable register, write 1 to enable this task." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESUME_CH5_EN + description: "Ledc ch5 gamma resume task enable register, write 1 to enable this task." + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: TIMER%s_CMP + description: Ledc timer%s compare value register. + addressOffset: 432 + size: 32 + fields: + - name: TIMER_CMP + description: This register stores ledc timer%s compare value. + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: TIMER%s_CNT_CAP + description: Ledc timer%s count value capture register. + addressOffset: 448 + size: 32 + fields: + - name: TIMER_CNT_CAP + description: This register stores ledc timer%s count value. + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: CONF + description: Global ledc configuration register + addressOffset: 496 + size: 32 + fields: + - name: APB_CLK_SEL + description: "This bit is used to select clock source for the 4 timers .\n\n2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: GAMMA_RAM_CLK_EN_CH0 + description: "This bit is used to control clock.\n\n1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: GAMMA_RAM_CLK_EN_CH1 + description: "This bit is used to control clock.\n\n1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: GAMMA_RAM_CLK_EN_CH2 + description: "This bit is used to control clock.\n\n1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: GAMMA_RAM_CLK_EN_CH3 + description: "This bit is used to control clock.\n\n1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: GAMMA_RAM_CLK_EN_CH4 + description: "This bit is used to control clock.\n\n1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: GAMMA_RAM_CLK_EN_CH5 + description: "This bit is used to control clock.\n\n1'b1: Force clock on for gamma ram. 1'h0: Support clock only when application writes or read gamma ram." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "This bit is used to control clock.\n\n1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 508 + size: 32 + resetValue: 34672976 + fields: + - name: LEDC_DATE + description: This is the version control register. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: LP_PERI + description: LP_PERI Peripheral + groupName: LPPERI + baseAddress: 1611343872 + addressBlock: + - offset: 0 + size: 48 + usage: registers + interrupt: + - name: LP_PERI_TIMEOUT + value: 5 + registers: + - register: + name: CLK_EN + description: need_des + addressOffset: 0 + size: 32 + resetValue: 2130706432 + fields: + - name: RNG_CK_EN + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: OTP_DBG_CK_EN + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LP_UART_CK_EN + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LP_IO_CK_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LP_EXT_I2C_CK_EN + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_ANA_I2C_CK_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: EFUSE_CK_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_CPU_CK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RESET_EN + description: need_des + addressOffset: 4 + size: 32 + fields: + - name: BUS_RESET_EN + description: need_des + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: LP_BLE_TIMER_RESET_EN + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: OTP_DBG_RESET_EN + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LP_UART_RESET_EN + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LP_IO_RESET_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LP_EXT_I2C_RESET_EN + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_ANA_I2C_RESET_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: EFUSE_RESET_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_CPU_RESET_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: RNG_DATA + description: need_des + addressOffset: 8 + size: 32 + fields: + - name: RND_DATA + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CPU + description: need_des + addressOffset: 12 + size: 32 + resetValue: 2147483648 + fields: + - name: LPCORE_DBGM_UNAVALIABLE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: BUS_TIMEOUT + description: need_des + addressOffset: 16 + size: 32 + resetValue: 3221209088 + fields: + - name: LP_PERI_TIMEOUT_THRES + description: need_des + bitOffset: 14 + bitWidth: 16 + access: read-write + - name: LP_PERI_TIMEOUT_INT_CLEAR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: LP_PERI_TIMEOUT_PROTECT_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: BUS_TIMEOUT_ADDR + description: need_des + addressOffset: 20 + size: 32 + fields: + - name: LP_PERI_TIMEOUT_ADDR + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BUS_TIMEOUT_UID + description: need_des + addressOffset: 24 + size: 32 + fields: + - name: LP_PERI_TIMEOUT_UID + description: need_des + bitOffset: 0 + bitWidth: 7 + access: read-only + - register: + name: MEM_CTRL + description: need_des + addressOffset: 28 + size: 32 + resetValue: 2147483648 + fields: + - name: UART_WAKEUP_FLAG_CLR + description: need_des + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: UART_WAKEUP_FLAG + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UART_WAKEUP_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: UART_MEM_FORCE_PD + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: UART_MEM_FORCE_PU + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INTERRUPT_SOURCE + description: need_des + addressOffset: 32 + size: 32 + fields: + - name: LP_INTERRUPT_SOURCE + description: "BIT5~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_uart_int, lp_i2c_int, lp_io_int" + bitOffset: 0 + bitWidth: 6 + access: read-only + - register: + name: DEBUG_SEL0 + description: need des + addressOffset: 36 + size: 32 + fields: + - name: DEBUG_SEL0 + description: need des + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: DEBUG_SEL1 + description: need des + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: DEBUG_SEL2 + description: need des + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: DEBUG_SEL3 + description: need des + bitOffset: 21 + bitWidth: 7 + access: read-write + - register: + name: DEBUG_SEL1 + description: need des + addressOffset: 40 + size: 32 + fields: + - name: DEBUG_SEL4 + description: need des + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 35676464 + fields: + - name: LPPERI_DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: LP_ANA + description: LP_ANA Peripheral + groupName: LP_ANA + baseAddress: 1611344896 + addressBlock: + - offset: 0 + size: 68 + usage: registers + registers: + - register: + name: BOD_MODE0_CNTL + description: need_des + addressOffset: 0 + size: 32 + resetValue: 268173568 + fields: + - name: BOD_MODE0_CLOSE_FLASH_ENA + description: need_des + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BOD_MODE0_PD_RF_ENA + description: need_des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: BOD_MODE0_INTR_WAIT + description: need_des + bitOffset: 8 + bitWidth: 10 + access: read-write + - name: BOD_MODE0_RESET_WAIT + description: need_des + bitOffset: 18 + bitWidth: 10 + access: read-write + - name: BOD_MODE0_CNT_CLR + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: BOD_MODE0_INTR_ENA + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: BOD_MODE0_RESET_SEL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: BOD_MODE0_RESET_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: BOD_MODE1_CNTL + description: need_des + addressOffset: 4 + size: 32 + fields: + - name: BOD_MODE1_RESET_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: VDD_SOURCE_CNTL + description: need_des + addressOffset: 8 + size: 32 + resetValue: 67109119 + fields: + - name: DETMODE_SEL + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: VGOOD_EVENT_RECORD + description: need_des + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: VBAT_EVENT_RECORD_CLR + description: need_des + bitOffset: 16 + bitWidth: 8 + access: write-only + - name: BOD_SOURCE_ENA + description: need_des + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: VDDBAT_BOD_CNTL + description: need_des + addressOffset: 12 + size: 32 + resetValue: 4290772992 + fields: + - name: VDDBAT_UNDERVOLTAGE_FLAG + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: VDDBAT_CHARGER + description: need_des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: VDDBAT_CNT_CLR + description: need_des + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: VDDBAT_UPVOLTAGE_TARGET + description: need_des + bitOffset: 12 + bitWidth: 10 + access: read-write + - name: VDDBAT_UNDERVOLTAGE_TARGET + description: need_des + bitOffset: 22 + bitWidth: 10 + access: read-write + - register: + name: VDDBAT_CHARGE_CNTL + description: need_des + addressOffset: 16 + size: 32 + resetValue: 4290772992 + fields: + - name: VDDBAT_CHARGE_UNDERVOLTAGE_FLAG + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: VDDBAT_CHARGE_CHARGER + description: need_des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: VDDBAT_CHARGE_CNT_CLR + description: need_des + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: VDDBAT_CHARGE_UPVOLTAGE_TARGET + description: need_des + bitOffset: 12 + bitWidth: 10 + access: read-write + - name: VDDBAT_CHARGE_UNDERVOLTAGE_TARGET + description: need_des + bitOffset: 22 + bitWidth: 10 + access: read-write + - register: + name: CK_GLITCH_CNTL + description: need_des + addressOffset: 20 + size: 32 + fields: + - name: CK_GLITCH_RESET_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: PG_GLITCH_CNTL + description: need_des + addressOffset: 24 + size: 32 + fields: + - name: POWER_GLITCH_RESET_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: FIB_ENABLE + description: need_des + addressOffset: 28 + size: 32 + resetValue: 4294967295 + fields: + - name: ANA_FIB_ENA + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: INT_RAW + description: need_des + addressOffset: 32 + size: 32 + fields: + - name: VDDBAT_CHARGE_UPVOLTAGE_INT_RAW + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: VDDBAT_UPVOLTAGE_INT_RAW + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: VDDBAT_UNDERVOLTAGE_INT_RAW + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: BOD_MODE0_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: need_des + addressOffset: 36 + size: 32 + fields: + - name: VDDBAT_CHARGE_UPVOLTAGE_INT_ST + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: VDDBAT_UPVOLTAGE_INT_ST + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: VDDBAT_UNDERVOLTAGE_INT_ST + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: BOD_MODE0_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: need_des + addressOffset: 40 + size: 32 + fields: + - name: VDDBAT_CHARGE_UPVOLTAGE_INT_ENA + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: VDDBAT_UPVOLTAGE_INT_ENA + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: VDDBAT_UNDERVOLTAGE_INT_ENA + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: BOD_MODE0_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: need_des + addressOffset: 44 + size: 32 + fields: + - name: VDDBAT_CHARGE_UPVOLTAGE_INT_CLR + description: need_des + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: VDDBAT_UPVOLTAGE_INT_CLR + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: VDDBAT_UNDERVOLTAGE_INT_CLR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: BOD_MODE0_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: LP_INT_RAW + description: need_des + addressOffset: 48 + size: 32 + fields: + - name: BOD_MODE0_LP_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_INT_ST + description: need_des + addressOffset: 52 + size: 32 + fields: + - name: BOD_MODE0_LP_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: LP_INT_ENA + description: need_des + addressOffset: 56 + size: 32 + fields: + - name: BOD_MODE0_LP_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_INT_CLR + description: need_des + addressOffset: 60 + size: 32 + fields: + - name: BOD_MODE0_LP_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 35684944 + fields: + - name: LP_ANA_DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: LP_AON + description: LP_AON Peripheral + groupName: LP_AON + baseAddress: 1611337728 + addressBlock: + - offset: 0 + size: 96 + usage: registers + registers: + - register: + name: STORE0 + description: need_des + addressOffset: 0 + size: 32 + fields: + - name: LP_AON_STORE0 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE1 + description: need_des + addressOffset: 4 + size: 32 + fields: + - name: LP_AON_STORE1 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE2 + description: need_des + addressOffset: 8 + size: 32 + fields: + - name: LP_AON_STORE2 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE3 + description: need_des + addressOffset: 12 + size: 32 + fields: + - name: LP_AON_STORE3 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE4 + description: need_des + addressOffset: 16 + size: 32 + fields: + - name: LP_AON_STORE4 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE5 + description: need_des + addressOffset: 20 + size: 32 + fields: + - name: LP_AON_STORE5 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE6 + description: need_des + addressOffset: 24 + size: 32 + fields: + - name: LP_AON_STORE6 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE7 + description: need_des + addressOffset: 28 + size: 32 + fields: + - name: LP_AON_STORE7 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE8 + description: need_des + addressOffset: 32 + size: 32 + fields: + - name: LP_AON_STORE8 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE9 + description: need_des + addressOffset: 36 + size: 32 + fields: + - name: LP_AON_STORE9 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: GPIO_MUX + description: need_des + addressOffset: 40 + size: 32 + fields: + - name: SEL + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: GPIO_HOLD0 + description: need_des + addressOffset: 44 + size: 32 + fields: + - name: GPIO_HOLD0 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: GPIO_HOLD1 + description: need_des + addressOffset: 48 + size: 32 + fields: + - name: GPIO_HOLD1 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SYS_CFG + description: need_des + addressOffset: 52 + size: 32 + resetValue: 7 + fields: + - name: ANA_FIB_SWD_ENABLE + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ANA_FIB_CK_GLITCH_ENABLE + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ANA_FIB_BOD_ENABLE + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FORCE_DOWNLOAD_BOOT + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HPSYS_SW_RESET + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: CPUCORE0_CFG + description: need_des + addressOffset: 56 + size: 32 + resetValue: 1073741824 + fields: + - name: CPU_CORE0_SW_STALL + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CPU_CORE0_SW_RESET + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: CPU_CORE0_OCD_HALT_ON_RESET + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CPU_CORE0_STAT_VECTOR_SEL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CPU_CORE0_DRESET_MASK + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: IO_MUX + description: need_des + addressOffset: 60 + size: 32 + fields: + - name: PULL_LDO + description: need_des + bitOffset: 28 + bitWidth: 3 + access: read-write + - name: RESET_DISABLE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EXT_WAKEUP_CNTL + description: need_des + addressOffset: 64 + size: 32 + fields: + - name: EXT_WAKEUP_STATUS + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: EXT_WAKEUP_STATUS_CLR + description: need_des + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: EXT_WAKEUP_SEL + description: need_des + bitOffset: 15 + bitWidth: 8 + access: read-write + - name: EXT_WAKEUP_LV + description: need_des + bitOffset: 23 + bitWidth: 8 + access: read-write + - name: EXT_WAKEUP_FILTER + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USB + description: need_des + addressOffset: 68 + size: 32 + fields: + - name: RESET_DISABLE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LPBUS + description: need_des + addressOffset: 72 + size: 32 + resetValue: 36175872 + fields: + - name: FAST_MEM_WPULSE + description: This field controls fast memory WPULSE parameter. 0b000 for 1.1V/1.0V/0.9V operating Voltage. + bitOffset: 16 + bitWidth: 3 + access: read-write + - name: FAST_MEM_WA + description: "This field controls fast memory WA parameter. 0b100 for 1.1V operating Voltage, 0b101 for 1.0V, 0b110 for 0.9V." + bitOffset: 19 + bitWidth: 3 + access: read-write + - name: FAST_MEM_RA + description: "This field controls fast memory RA parameter. 0b00 for 1.1V/1.0V operating Voltage, 0b01 for 0.9V." + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: FAST_MEM_RM + description: "This field controls fast memory RM parameter. 0b0011 for 1.1V operating Voltage, 0b0010 for 1.0V, 0b0000 for 0.9V." + bitOffset: 24 + bitWidth: 4 + access: read-write + - name: FAST_MEM_MUX_FSM_IDLE + description: reserved + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: FAST_MEM_MUX_SEL_STATUS + description: reserved + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: FAST_MEM_MUX_SEL_UPDATE + description: reserved + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: FAST_MEM_MUX_SEL + description: reserved + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: SDIO_ACTIVE + description: need_des + addressOffset: 76 + size: 32 + resetValue: 41943040 + fields: + - name: SDIO_ACT_DNUM + description: need_des + bitOffset: 22 + bitWidth: 10 + access: read-write + - register: + name: LPCORE + description: need_des + addressOffset: 80 + size: 32 + fields: + - name: ETM_WAKEUP_FLAG_CLR + description: need_des + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ETM_WAKEUP_FLAG + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DISABLE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAR_CCT + description: need_des + addressOffset: 84 + size: 32 + fields: + - name: SAR2_PWDET_CCT + description: need_des + bitOffset: 29 + bitWidth: 3 + access: read-write + - register: + name: JTAG_SEL + description: need_des + addressOffset: 88 + size: 32 + resetValue: 2147483648 + fields: + - name: SOFT + description: "If strapping_sel_jtag feature is disabled by efuse, and if neither pad_jtag or usb_jtag is disabled by efuse, this field determines which one jtag between usb_jtag and pad_jtag will be used. 1'b1(default): usb_jtag, 1'b0: pad_jtag." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 35717264 + fields: + - name: DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: LP_APM + description: Low-power Access Permission Management Controller + groupName: LP_APM + baseAddress: 1611347968 + addressBlock: + - offset: 0 + size: 60 + usage: registers + interrupt: + - name: LP_APM_M0 + value: 6 + registers: + - register: + name: REGION_FILTER_EN + description: Region filter enable register + addressOffset: 0 + size: 32 + resetValue: 1 + fields: + - name: REGION_FILTER_EN + description: Region filter enable + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: REGION0_ADDR_START + description: Region address register + addressOffset: 4 + size: 32 + fields: + - name: REGION0_ADDR_START + description: Start address of region0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION0_ADDR_END + description: Region address register + addressOffset: 8 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION0_ADDR_END + description: End address of region0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION0_PMS_ATTR + description: Region access authority attribute register + addressOffset: 12 + size: 32 + fields: + - name: REGION0_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION0_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION0_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION0_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION0_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION0_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION0_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION0_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION0_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: REGION1_ADDR_START + description: Region address register + addressOffset: 16 + size: 32 + fields: + - name: REGION1_ADDR_START + description: Start address of region1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION1_ADDR_END + description: Region address register + addressOffset: 20 + size: 32 + resetValue: 4294967295 + fields: + - name: REGION1_ADDR_END + description: End address of region1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGION1_PMS_ATTR + description: Region access authority attribute register + addressOffset: 24 + size: 32 + fields: + - name: REGION1_R0_PMS_X + description: Region execute authority in REE_MODE0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGION1_R0_PMS_W + description: Region write authority in REE_MODE0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGION1_R0_PMS_R + description: Region read authority in REE_MODE0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGION1_R1_PMS_X + description: Region execute authority in REE_MODE1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REGION1_R1_PMS_W + description: Region write authority in REE_MODE1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REGION1_R1_PMS_R + description: Region read authority in REE_MODE1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REGION1_R2_PMS_X + description: Region execute authority in REE_MODE2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REGION1_R2_PMS_W + description: Region write authority in REE_MODE2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REGION1_R2_PMS_R + description: Region read authority in REE_MODE2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: FUNC_CTRL + description: PMS function control register + addressOffset: 196 + size: 32 + resetValue: 1 + fields: + - name: M0_PMS_FUNC_EN + description: PMS M0 function enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: M0_STATUS + description: M0 status register + addressOffset: 200 + size: 32 + fields: + - name: M0_EXCEPTION_STATUS + description: Exception status + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: M0_STATUS_CLR + description: M0 status clear register + addressOffset: 204 + size: 32 + fields: + - name: M0_REGION_STATUS_CLR + description: Clear exception status + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: M0_EXCEPTION_INFO0 + description: M0 exception_info0 register + addressOffset: 208 + size: 32 + fields: + - name: M0_EXCEPTION_REGION + description: Exception region + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: M0_EXCEPTION_MODE + description: Exception mode + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: M0_EXCEPTION_ID + description: Exception id information + bitOffset: 18 + bitWidth: 5 + access: read-only + - register: + name: M0_EXCEPTION_INFO1 + description: M0 exception_info1 register + addressOffset: 212 + size: 32 + fields: + - name: M0_EXCEPTION_ADDR + description: Exception addr + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INT_EN + description: APM interrupt enable register + addressOffset: 232 + size: 32 + fields: + - name: M0_APM_INT_EN + description: APM M0 interrupt enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CLOCK_GATE + description: clock gating register + addressOffset: 236 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: reg_clk_en + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version register + addressOffset: 252 + size: 32 + resetValue: 35680864 + fields: + - name: DATE + description: reg_date + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: LP_CLKRST + description: LP_CLKRST Peripheral + groupName: LP_CLKRST + baseAddress: 1611334656 + addressBlock: + - offset: 0 + size: 52 + usage: registers + registers: + - register: + name: LP_CLK_CONF + description: need_des + addressOffset: 0 + size: 32 + resetValue: 4 + fields: + - name: SLOW_CLK_SEL + description: need_des + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: FAST_CLK_SEL + description: need_des + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: LP_PERI_DIV_NUM + description: need_des + bitOffset: 4 + bitWidth: 8 + access: read-write + - register: + name: LP_CLK_PO_EN + description: need_des + addressOffset: 4 + size: 32 + resetValue: 2047 + fields: + - name: AON_SLOW_OEN + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: AON_FAST_OEN + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SOSC_OEN + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FOSC_OEN + description: need_des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OSC32K_OEN + description: need_des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: XTAL32K_OEN + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CORE_EFUSE_OEN + description: need_des + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SLOW_OEN + description: need_des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FAST_OEN + description: need_des + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RNG_OEN + description: need_des + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: LPBUS_OEN + description: need_des + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: LP_CLK_EN + description: need_des + addressOffset: 8 + size: 32 + fields: + - name: FAST_ORI_GATE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_RST_EN + description: need_des + addressOffset: 12 + size: 32 + fields: + - name: AON_EFUSE_CORE_RESET_EN + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_TIMER_RESET_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: WDT_RESET_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: ANA_PERI_RESET_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RESET_CAUSE + description: need_des + addressOffset: 16 + size: 32 + resetValue: 32 + fields: + - name: RESET_CAUSE + description: need_des + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: CORE0_RESET_FLAG + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CORE0_RESET_CAUSE_CLR + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: CORE0_RESET_FLAG_SET + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: CORE0_RESET_FLAG_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: CPU_RESET + description: need_des + addressOffset: 20 + size: 32 + resetValue: 71303168 + fields: + - name: RTC_WDT_CPU_RESET_LENGTH + description: need_des + bitOffset: 22 + bitWidth: 3 + access: read-write + - name: RTC_WDT_CPU_RESET_EN + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: CPU_STALL_WAIT + description: need_des + bitOffset: 26 + bitWidth: 5 + access: read-write + - name: CPU_STALL_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: FOSC_CNTL + description: need_des + addressOffset: 24 + size: 32 + resetValue: 2516582400 + fields: + - name: FOSC_DFREQ + description: need_des + bitOffset: 22 + bitWidth: 10 + access: read-write + - register: + name: RC32K_CNTL + description: need_des + addressOffset: 28 + size: 32 + resetValue: 2726297600 + fields: + - name: RC32K_DFREQ + description: need_des + bitOffset: 22 + bitWidth: 10 + access: read-write + - register: + name: CLK_TO_HP + description: need_des + addressOffset: 32 + size: 32 + resetValue: 4026531840 + fields: + - name: ICG_HP_XTAL32K + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: ICG_HP_SOSC + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ICG_HP_OSC32K + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: ICG_HP_FOSC + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LPMEM_FORCE + description: need_des + addressOffset: 36 + size: 32 + fields: + - name: LPMEM_CLK_FORCE_ON + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LPPERI + description: need_des + addressOffset: 40 + size: 32 + resetValue: 536870912 + fields: + - name: LP_BLETIMER_DIV_NUM + description: need_des + bitOffset: 12 + bitWidth: 12 + access: read-write + - name: LP_BLETIMER_32K_SEL + description: need_des + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: LP_SEL_OSC_SLOW + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LP_SEL_OSC_FAST + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LP_SEL_XTAL + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_SEL_XTAL32K + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LP_I2C_CLK_SEL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_UART_CLK_SEL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: XTAL32K + description: need_des + addressOffset: 44 + size: 32 + resetValue: 1723858944 + fields: + - name: DRES_XTAL32K + description: need_des + bitOffset: 22 + bitWidth: 3 + access: read-write + - name: DGM_XTAL32K + description: need_des + bitOffset: 25 + bitWidth: 3 + access: read-write + - name: DBUF_XTAL32K + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DAC_XTAL32K + description: need_des + bitOffset: 29 + bitWidth: 3 + access: read-write + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 35680896 + fields: + - name: CLKRST_DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: LP_TIMER + description: Low-power Timer + groupName: LP_TIMER + baseAddress: 1611336704 + addressBlock: + - offset: 0 + size: 52 + usage: registers + interrupt: + - name: LP_RTC_TIMER + value: 2 + - name: LP_BLE_TIMER + value: 3 + registers: + - register: + name: TAR0_LOW + description: need_des + addressOffset: 0 + size: 32 + fields: + - name: MAIN_TIMER_TAR_LOW0 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TAR0_HIGH + description: need_des + addressOffset: 4 + size: 32 + fields: + - name: MAIN_TIMER_TAR_HIGH0 + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MAIN_TIMER_TAR_EN0 + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: UPDATE + description: need_des + addressOffset: 16 + size: 32 + fields: + - name: MAIN_TIMER_UPDATE + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: MAIN_TIMER_XTAL_OFF + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: MAIN_TIMER_SYS_STALL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: MAIN_TIMER_SYS_RST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: MAIN_BUF0_LOW + description: need_des + addressOffset: 20 + size: 32 + fields: + - name: MAIN_TIMER_BUF0_LOW + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: MAIN_BUF0_HIGH + description: need_des + addressOffset: 24 + size: 32 + fields: + - name: MAIN_TIMER_BUF0_HIGH + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: MAIN_BUF1_LOW + description: need_des + addressOffset: 28 + size: 32 + fields: + - name: MAIN_TIMER_BUF1_LOW + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: MAIN_BUF1_HIGH + description: need_des + addressOffset: 32 + size: 32 + fields: + - name: MAIN_TIMER_BUF1_HIGH + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: MAIN_OVERFLOW + description: need_des + addressOffset: 36 + size: 32 + fields: + - name: MAIN_TIMER_ALARM_LOAD + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: INT_RAW + description: need_des + addressOffset: 40 + size: 32 + fields: + - name: OVERFLOW_RAW + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SOC_WAKEUP_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: need_des + addressOffset: 44 + size: 32 + fields: + - name: OVERFLOW_ST + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: SOC_WAKEUP_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: need_des + addressOffset: 48 + size: 32 + fields: + - name: OVERFLOW_ENA + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SOC_WAKEUP_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: need_des + addressOffset: 52 + size: 32 + fields: + - name: OVERFLOW_CLR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: SOC_WAKEUP_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 34672976 + fields: + - name: DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: LP_WDT + description: Low-power Watchdog Timer + groupName: LP_WDT + baseAddress: 1611340800 + addressBlock: + - offset: 0 + size: 60 + usage: registers + interrupt: + - name: LP_WDT + value: 4 + registers: + - register: + name: WDTCONFIG0 + description: need_des + addressOffset: 0 + size: 32 + resetValue: 78336 + fields: + - name: WDT_PAUSE_IN_SLP + description: need_des + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: WDT_APPCPU_RESET_EN + description: need_des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: WDT_PROCPU_RESET_EN + description: need_des + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: WDT_FLASHBOOT_MOD_EN + description: need_des + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: WDT_SYS_RESET_LENGTH + description: need_des + bitOffset: 13 + bitWidth: 3 + access: read-write + - name: WDT_CPU_RESET_LENGTH + description: need_des + bitOffset: 16 + bitWidth: 3 + access: read-write + - name: WDT_STG3 + description: need_des + bitOffset: 19 + bitWidth: 3 + access: read-write + - name: WDT_STG2 + description: need_des + bitOffset: 22 + bitWidth: 3 + access: read-write + - name: WDT_STG1 + description: need_des + bitOffset: 25 + bitWidth: 3 + access: read-write + - name: WDT_STG0 + description: need_des + bitOffset: 28 + bitWidth: 3 + access: read-write + - name: WDT_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CONFIG1 + description: need_des + addressOffset: 4 + size: 32 + resetValue: 200000 + fields: + - name: WDT_STG0_HOLD + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CONFIG2 + description: need_des + addressOffset: 8 + size: 32 + resetValue: 80000 + fields: + - name: WDT_STG1_HOLD + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CONFIG3 + description: need_des + addressOffset: 12 + size: 32 + resetValue: 4095 + fields: + - name: WDT_STG2_HOLD + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CONFIG4 + description: need_des + addressOffset: 16 + size: 32 + resetValue: 4095 + fields: + - name: WDT_STG3_HOLD + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CONFIG5 + description: need_des + addressOffset: 20 + size: 32 + resetValue: 255 + fields: + - name: CHIP_RESET_TARGET + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CHIP_RESET_EN + description: need_des + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CHIP_RESET_KEY + description: need_des + bitOffset: 9 + bitWidth: 8 + access: read-write + - register: + name: WDTFEED + description: need_des + addressOffset: 24 + size: 32 + fields: + - name: RTC_WDT_FEED + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: WDTWPROTECT + description: need_des + addressOffset: 28 + size: 32 + fields: + - name: WDT_WKEY + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SWD_CONF + description: need_des + addressOffset: 32 + size: 32 + resetValue: 314572800 + fields: + - name: SWD_RESET_FLAG + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SWD_AUTO_FEED_EN + description: need_des + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SWD_RST_FLAG_CLR + description: need_des + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: SWD_SIGNAL_WIDTH + description: need_des + bitOffset: 20 + bitWidth: 10 + access: read-write + - name: SWD_DISABLE + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SWD_FEED + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SWD_WPROTECT + description: need_des + addressOffset: 36 + size: 32 + fields: + - name: SWD_WKEY + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: INT_RAW + description: need_des + addressOffset: 40 + size: 32 + fields: + - name: SUPER_WDT_INT_RAW + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_WDT_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_ST_RTC + description: need_des + addressOffset: 44 + size: 32 + fields: + - name: SUPER_WDT_INT_ST + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: WDT_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA_RTC + description: need_des + addressOffset: 48 + size: 32 + fields: + - name: SUPER_WDT_INT_ENA + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: WDT_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR_RTC + description: need_des + addressOffset: 52 + size: 32 + fields: + - name: SUPER_WDT_INT_CLR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: WDT_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 34676864 + fields: + - name: LP_WDT_DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: MCPWM0 + description: Motor Control Pulse-Width Modulation 0 + groupName: MCPWM + baseAddress: 1610694656 + addressBlock: + - offset: 0 + size: 304 + usage: registers + interrupt: + - name: MCPWM0 + value: 49 + registers: + - register: + name: CLK_CFG + description: PWM clock prescaler register. + addressOffset: 0 + size: 32 + fields: + - name: CLK_PRESCALE + description: Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1) + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: TIMER0_CFG0 + description: PWM timer0 period and update method configuration register. + addressOffset: 4 + size: 32 + resetValue: 65280 + fields: + - name: TIMER0_PRESCALE + description: period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1) + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TIMER0_PERIOD + description: period shadow register of PWM timer0 + bitOffset: 8 + bitWidth: 16 + access: read-write + - name: TIMER0_PERIOD_UPMETHOD + description: "Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event" + bitOffset: 24 + bitWidth: 2 + access: read-write + - register: + name: TIMER0_CFG1 + description: PWM timer0 working mode and start/stop control configuration register. + addressOffset: 8 + size: 32 + fields: + - name: TIMER0_START + description: "PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: TIMER0_MOD + description: "PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode" + bitOffset: 3 + bitWidth: 2 + access: read-write + - register: + name: TIMER0_SYNC + description: PWM timer0 sync function configuration register. + addressOffset: 12 + size: 32 + fields: + - name: TIMER0_SYNCI_EN + description: "When set, timer reloading with phase on sync input event is enabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SW + description: Toggling this bit will trigger a software sync. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER0_SYNCO_SEL + description: "PWM timer0 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always generate when toggling the reg_timer0_sync_sw bit" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: TIMER0_PHASE + description: phase for timer reload on sync event + bitOffset: 4 + bitWidth: 16 + access: read-write + - name: TIMER0_PHASE_DIRECTION + description: "Configure the PWM timer0's direction when timer0 mode is up-down mode: 0-increase,1-decrease" + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: TIMER0_STATUS + description: PWM timer0 status register. + addressOffset: 16 + size: 32 + fields: + - name: TIMER0_VALUE + description: current PWM timer0 counter value + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: TIMER0_DIRECTION + description: "current PWM timer0 counter direction, 0: increment 1: decrement" + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: TIMER1_CFG0 + description: PWM timer1 period and update method configuration register. + addressOffset: 20 + size: 32 + resetValue: 65280 + fields: + - name: TIMER1_PRESCALE + description: period of PT0_clk = Period of PWM_clk * (PWM_timer1_PRESCALE + 1) + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TIMER1_PERIOD + description: period shadow register of PWM timer1 + bitOffset: 8 + bitWidth: 16 + access: read-write + - name: TIMER1_PERIOD_UPMETHOD + description: "Update method for active register of PWM timer1 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event" + bitOffset: 24 + bitWidth: 2 + access: read-write + - register: + name: TIMER1_CFG1 + description: PWM timer1 working mode and start/stop control configuration register. + addressOffset: 24 + size: 32 + fields: + - name: TIMER1_START + description: "PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at TEZ, 1: if timer1 starts, then stops at TEP, 2: PWM timer1 starts and runs on, 3: timer1 starts and stops at the next TEZ, 4: timer1 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: TIMER1_MOD + description: "PWM timer1 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode" + bitOffset: 3 + bitWidth: 2 + access: read-write + - register: + name: TIMER1_SYNC + description: PWM timer1 sync function configuration register. + addressOffset: 28 + size: 32 + fields: + - name: TIMER1_SYNCI_EN + description: "When set, timer reloading with phase on sync input event is enabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SW + description: Toggling this bit will trigger a software sync. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER1_SYNCO_SEL + description: "PWM timer1 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always generate when toggling the reg_timer1_sync_sw bit" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: TIMER1_PHASE + description: phase for timer reload on sync event + bitOffset: 4 + bitWidth: 16 + access: read-write + - name: TIMER1_PHASE_DIRECTION + description: "Configure the PWM timer1's direction when timer1 mode is up-down mode: 0-increase,1-decrease" + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: TIMER1_STATUS + description: PWM timer1 status register. + addressOffset: 32 + size: 32 + fields: + - name: TIMER1_VALUE + description: current PWM timer1 counter value + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: TIMER1_DIRECTION + description: "current PWM timer1 counter direction, 0: increment 1: decrement" + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: TIMER2_CFG0 + description: PWM timer2 period and update method configuration register. + addressOffset: 36 + size: 32 + resetValue: 65280 + fields: + - name: TIMER2_PRESCALE + description: period of PT0_clk = Period of PWM_clk * (PWM_timer2_PRESCALE + 1) + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TIMER2_PERIOD + description: period shadow register of PWM timer2 + bitOffset: 8 + bitWidth: 16 + access: read-write + - name: TIMER2_PERIOD_UPMETHOD + description: "Update method for active register of PWM timer2 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event" + bitOffset: 24 + bitWidth: 2 + access: read-write + - register: + name: TIMER2_CFG1 + description: PWM timer2 working mode and start/stop control configuration register. + addressOffset: 40 + size: 32 + fields: + - name: TIMER2_START + description: "PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at TEZ, 1: if timer2 starts, then stops at TEP, 2: PWM timer2 starts and runs on, 3: timer2 starts and stops at the next TEZ, 4: timer2 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: TIMER2_MOD + description: "PWM timer2 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode" + bitOffset: 3 + bitWidth: 2 + access: read-write + - register: + name: TIMER2_SYNC + description: PWM timer2 sync function configuration register. + addressOffset: 44 + size: 32 + fields: + - name: TIMER2_SYNCI_EN + description: "When set, timer reloading with phase on sync input event is enabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SW + description: Toggling this bit will trigger a software sync. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER2_SYNCO_SEL + description: "PWM timer2 sync_out selection, 0: sync_in, 1: TEZ, 2: TEP, and sync out will always generate when toggling the reg_timer0_sync_sw bit" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: TIMER2_PHASE + description: phase for timer reload on sync event + bitOffset: 4 + bitWidth: 16 + access: read-write + - name: TIMER2_PHASE_DIRECTION + description: "Configure the PWM timer2's direction when timer2 mode is up-down mode: 0-increase,1-decrease" + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: TIMER2_STATUS + description: PWM timer2 status register. + addressOffset: 48 + size: 32 + fields: + - name: TIMER2_VALUE + description: current PWM timer2 counter value + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: TIMER2_DIRECTION + description: "current PWM timer2 counter direction, 0: increment 1: decrement" + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: TIMER_SYNCI_CFG + description: Synchronization input selection for three PWM timers. + addressOffset: 52 + size: 32 + fields: + - name: TIMER0_SYNCISEL + description: "select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: TIMER1_SYNCISEL + description: "select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected" + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: TIMER2_SYNCISEL + description: "select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: EXTERNAL_SYNCI0_INVERT + description: invert SYNC0 from GPIO matrix + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: EXTERNAL_SYNCI1_INVERT + description: invert SYNC1 from GPIO matrix + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: EXTERNAL_SYNCI2_INVERT + description: invert SYNC2 from GPIO matrix + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: OPERATOR_TIMERSEL + description: Select specific timer for PWM operators. + addressOffset: 56 + size: 32 + fields: + - name: OPERATOR0_TIMERSEL + description: "Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: OPERATOR1_TIMERSEL + description: "Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: OPERATOR2_TIMERSEL + description: "Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2" + bitOffset: 4 + bitWidth: 2 + access: read-write + - register: + name: GEN0_STMP_CFG + description: Transfer status and update method for time stamp registers A and B + addressOffset: 60 + size: 32 + fields: + - name: CMPR0_A_UPMETHOD + description: "Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: CMPR0_B_UPMETHOD + description: "Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: CMPR0_A_SHDW_FULL + description: "Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CMPR0_B_SHDW_FULL + description: "Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value" + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: GEN0_TSTMP_A + description: Shadow register for register A. + addressOffset: 64 + size: 32 + fields: + - name: CMPR0_A + description: "PWM generator 0 time stamp A's shadow register" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: GEN0_TSTMP_B + description: Shadow register for register B. + addressOffset: 68 + size: 32 + fields: + - name: CMPR0_B + description: "PWM generator 0 time stamp B's shadow register" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: GEN0_CFG0 + description: Fault event T0 and T1 handling + addressOffset: 72 + size: 32 + fields: + - name: GEN0_CFG_UPMETHOD + description: "Update method for PWM generator 0's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:TEP,when bit2 is set to 1:sync,when bit3 is set to 1:disable the update" + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: GEN0_T0_SEL + description: "Source selection for PWM generator 0 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none" + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: GEN0_T1_SEL + description: "Source selection for PWM generator 0 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none" + bitOffset: 7 + bitWidth: 3 + access: read-write + - register: + name: GEN0_FORCE + description: Permissives to force PWM0A and PWM0B outputs by software + addressOffset: 76 + size: 32 + resetValue: 32 + fields: + - name: GEN0_CNTUFORCE_UPMETHOD + description: "Updating method for continuous software force of PWM generator0. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.)" + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: GEN0_A_CNTUFORCE_MODE + description: "Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: GEN0_B_CNTUFORCE_MODE + description: "Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: GEN0_A_NCIFORCE + description: "Trigger of non-continuous immediate software-force event for PWM0A, a toggle will trigger a force event." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GEN0_A_NCIFORCE_MODE + description: "non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: GEN0_B_NCIFORCE + description: "Trigger of non-continuous immediate software-force event for PWM0B, a toggle will trigger a force event." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: GEN0_B_NCIFORCE_MODE + description: "non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: GEN0_A + description: Actions triggered by events on PWM0A + addressOffset: 80 + size: 32 + fields: + - name: UTEZ + description: Action on PWM0A triggered by event TEZ when timer increasing + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + description: Action on PWM0A triggered by event TEP when timer increasing + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + description: Action on PWM0A triggered by event TEA when timer increasing + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + description: Action on PWM0A triggered by event TEB when timer increasing + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + description: Action on PWM0A triggered by event_t0 when timer increasing + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + description: Action on PWM0A triggered by event_t1 when timer increasing + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + description: Action on PWM0A triggered by event TEZ when timer decreasing + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + description: Action on PWM0A triggered by event TEP when timer decreasing + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + description: Action on PWM0A triggered by event TEA when timer decreasing + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + description: Action on PWM0A triggered by event TEB when timer decreasing + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + description: Action on PWM0A triggered by event_t0 when timer decreasing + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + description: "Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: GEN0_B + description: Actions triggered by events on PWM0B + addressOffset: 84 + size: 32 + fields: + - name: UTEZ + description: Action on PWM0B triggered by event TEZ when timer increasing + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + description: Action on PWM0B triggered by event TEP when timer increasing + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + description: Action on PWM0B triggered by event TEA when timer increasing + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + description: Action on PWM0B triggered by event TEB when timer increasing + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + description: Action on PWM0B triggered by event_t0 when timer increasing + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + description: Action on PWM0B triggered by event_t1 when timer increasing + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + description: Action on PWM0B triggered by event TEZ when timer decreasing + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + description: Action on PWM0B triggered by event TEP when timer decreasing + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + description: Action on PWM0B triggered by event TEA when timer decreasing + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + description: Action on PWM0B triggered by event TEB when timer decreasing + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + description: Action on PWM0B triggered by event_t0 when timer decreasing + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + description: "Action on PWM0B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: DT0_CFG + description: dead time type selection and configuration + addressOffset: 88 + size: 32 + resetValue: 98304 + fields: + - name: DB0_FED_UPMETHOD + description: "Update method for FED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update" + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: DB0_RED_UPMETHOD + description: "Update method for RED (rising edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update" + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: DB0_DEB_MODE + description: "S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DB0_A_OUTSWAP + description: S6 in table + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DB0_B_OUTSWAP + description: S7 in table + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DB0_RED_INSEL + description: S4 in table + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DB0_FED_INSEL + description: S5 in table + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DB0_RED_OUTINVERT + description: S2 in table + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DB0_FED_OUTINVERT + description: S3 in table + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DB0_A_OUTBYPASS + description: S1 in table + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DB0_B_OUTBYPASS + description: S0 in table + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DB0_CLK_SEL + description: "Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk" + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: DT0_FED_CFG + description: Shadow register for falling edge delay (FED). + addressOffset: 92 + size: 32 + fields: + - name: DB0_FED + description: Shadow register for FED + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: DT0_RED_CFG + description: Shadow register for rising edge delay (RED). + addressOffset: 96 + size: 32 + fields: + - name: DB0_RED + description: Shadow register for RED + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: CARRIER0_CFG + description: Carrier enable and configuratoin + addressOffset: 100 + size: 32 + fields: + - name: CHOPPER0_EN + description: "When set, carrier0 function is enabled. When cleared, carrier0 is bypassed" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CHOPPER0_PRESCALE + description: PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CHOPPER0_DUTY + description: carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + bitOffset: 5 + bitWidth: 3 + access: read-write + - name: CHOPPER0_OSHTWTH + description: width of the first pulse in number of periods of the carrier + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: CHOPPER0_OUT_INVERT + description: "when set, invert the output of PWM0A and PWM0B for this submodule" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CHOPPER0_IN_INVERT + description: "when set, invert the input of PWM0A and PWM0B for this submodule" + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: FH0_CFG0 + description: Actions on PWM0A and PWM0B trip events + addressOffset: 104 + size: 32 + fields: + - name: TZ0_SW_CBC + description: "Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TZ0_F2_CBC + description: "event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TZ0_F1_CBC + description: "event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TZ0_F0_CBC + description: "event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TZ0_SW_OST + description: "Enable register for software force one-shot mode action. 0: disable, 1: enable" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TZ0_F2_OST + description: "event_f2 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TZ0_F1_OST + description: "event_f1 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TZ0_F0_OST + description: "event_f0 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TZ0_A_CBC_D + description: "Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: TZ0_A_CBC_U + description: "Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: TZ0_A_OST_D + description: "One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: TZ0_A_OST_U + description: "One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: TZ0_B_CBC_D + description: "Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: TZ0_B_CBC_U + description: "Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing,1: force low, 2: force high, 3: toggle" + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: TZ0_B_OST_D + description: "One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TZ0_B_OST_U + description: "One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: FH0_CFG1 + description: Software triggers for fault handler actions + addressOffset: 108 + size: 32 + fields: + - name: TZ0_CLR_OST + description: a rising edge will clear on going one-shot mode action + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TZ0_CBCPULSE + description: "cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP" + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: TZ0_FORCE_CBC + description: a toggle trigger a cycle-by-cycle mode action + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TZ0_FORCE_OST + description: a toggle (software negate its value) triggers a one-shot mode action + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: FH0_STATUS + description: Status of fault events. + addressOffset: 112 + size: 32 + fields: + - name: TZ0_CBC_ON + description: "Set and reset by hardware. If set, a cycle-by-cycle mode action is on going" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TZ0_OST_ON + description: "Set and reset by hardware. If set, an one-shot mode action is on going" + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: GEN1_STMP_CFG + description: Transfer status and update method for time stamp registers A and B + addressOffset: 116 + size: 32 + fields: + - name: CMPR1_A_UPMETHOD + description: "Update method for PWM generator 1 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: CMPR1_B_UPMETHOD + description: "Update method for PWM generator 1 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: CMPR1_A_SHDW_FULL + description: "Set and reset by hardware. If set, PWM generator 1 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CMPR1_B_SHDW_FULL + description: "Set and reset by hardware. If set, PWM generator 1 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value" + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: GEN1_TSTMP_A + description: Shadow register for register A. + addressOffset: 120 + size: 32 + fields: + - name: CMPR1_A + description: "PWM generator 1 time stamp A's shadow register" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: GEN1_TSTMP_B + description: Shadow register for register B. + addressOffset: 124 + size: 32 + fields: + - name: CMPR1_B + description: "PWM generator 1 time stamp B's shadow register" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: GEN1_CFG0 + description: Fault event T0 and T1 handling + addressOffset: 128 + size: 32 + fields: + - name: GEN1_CFG_UPMETHOD + description: "Update method for PWM generator 1's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:sync;when bit3 is set to 1:disable the update." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: GEN1_T0_SEL + description: "Source selection for PWM generator 1 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none" + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: GEN1_T1_SEL + description: "Source selection for PWM generator 1 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none" + bitOffset: 7 + bitWidth: 3 + access: read-write + - register: + name: GEN1_FORCE + description: Permissives to force PWM1A and PWM1B outputs by software + addressOffset: 132 + size: 32 + resetValue: 32 + fields: + - name: GEN1_CNTUFORCE_UPMETHOD + description: "Updating method for continuous software force of PWM generator 1. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.)" + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: GEN1_A_CNTUFORCE_MODE + description: "Continuous software force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: GEN1_B_CNTUFORCE_MODE + description: "Continuous software force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: GEN1_A_NCIFORCE + description: "Trigger of non-continuous immediate software-force event for PWM1A, a toggle will trigger a force event." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GEN1_A_NCIFORCE_MODE + description: "non-continuous immediate software force mode for PWM1A, 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: GEN1_B_NCIFORCE + description: "Trigger of non-continuous immediate software-force event for PWM1B, a toggle will trigger a force event." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: GEN1_B_NCIFORCE_MODE + description: "non-continuous immediate software force mode for PWM1B, 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: GEN1_A + description: Actions triggered by events on PWM1A + addressOffset: 136 + size: 32 + fields: + - name: UTEZ + description: Action on PWM1A triggered by event TEZ when timer increasing + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + description: Action on PWM1A triggered by event TEP when timer increasing + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + description: Action on PWM1A triggered by event TEA when timer increasing + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + description: Action on PWM1A triggered by event TEB when timer increasing + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + description: Action on PWM1A triggered by event_t0 when timer increasing + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + description: Action on PWM1A triggered by event_t1 when timer increasing + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + description: Action on PWM1A triggered by event TEZ when timer decreasing + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + description: Action on PWM1A triggered by event TEP when timer decreasing + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + description: Action on PWM1A triggered by event TEA when timer decreasing + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + description: Action on PWM1A triggered by event TEB when timer decreasing + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + description: Action on PWM1A triggered by event_t0 when timer decreasing + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + description: "Action on PWM1A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: GEN1_B + description: Actions triggered by events on PWM1B + addressOffset: 140 + size: 32 + fields: + - name: UTEZ + description: Action on PWM1B triggered by event TEZ when timer increasing + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + description: Action on PWM1B triggered by event TEP when timer increasing + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + description: Action on PWM1B triggered by event TEA when timer increasing + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + description: Action on PWM1B triggered by event TEB when timer increasing + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + description: Action on PWM1B triggered by event_t0 when timer increasing + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + description: Action on PWM1B triggered by event_t1 when timer increasing + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + description: Action on PWM1B triggered by event TEZ when timer decreasing + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + description: Action on PWM1B triggered by event TEP when timer decreasing + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + description: Action on PWM1B triggered by event TEA when timer decreasing + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + description: Action on PWM1B triggered by event TEB when timer decreasing + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + description: Action on PWM1B triggered by event_t0 when timer decreasing + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + description: "Action on PWM1B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: DT1_CFG + description: dead time type selection and configuration + addressOffset: 144 + size: 32 + resetValue: 98304 + fields: + - name: DB1_FED_UPMETHOD + description: "Update method for FED (falling edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update" + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: DB1_RED_UPMETHOD + description: "Update method for RED (rising edge delay) active register. 0: immediate,when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update" + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: DB1_DEB_MODE + description: "S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DB1_A_OUTSWAP + description: S6 in table + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DB1_B_OUTSWAP + description: S7 in table + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DB1_RED_INSEL + description: S4 in table + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DB1_FED_INSEL + description: S5 in table + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DB1_RED_OUTINVERT + description: S2 in table + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DB1_FED_OUTINVERT + description: S3 in table + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DB1_A_OUTBYPASS + description: S1 in table + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DB1_B_OUTBYPASS + description: S0 in table + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DB1_CLK_SEL + description: "Dead time generator 1 clock selection. 0: PWM_clk, 1: PT_clk" + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: DT1_FED_CFG + description: Shadow register for falling edge delay (FED). + addressOffset: 148 + size: 32 + fields: + - name: DB1_FED + description: Shadow register for FED + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: DT1_RED_CFG + description: Shadow register for rising edge delay (RED). + addressOffset: 152 + size: 32 + fields: + - name: DB1_RED + description: Shadow register for RED + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: CARRIER1_CFG + description: Carrier enable and configuratoin + addressOffset: 156 + size: 32 + fields: + - name: CHOPPER1_EN + description: "When set, carrier1 function is enabled. When cleared, carrier1 is bypassed" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CHOPPER1_PRESCALE + description: PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CHOPPER1_DUTY + description: carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + bitOffset: 5 + bitWidth: 3 + access: read-write + - name: CHOPPER1_OSHTWTH + description: width of the first pulse in number of periods of the carrier + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: CHOPPER1_OUT_INVERT + description: "when set, invert the output of PWM1A and PWM1B for this submodule" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CHOPPER1_IN_INVERT + description: "when set, invert the input of PWM1A and PWM1B for this submodule" + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: FH1_CFG0 + description: Actions on PWM1A and PWM1B trip events + addressOffset: 160 + size: 32 + fields: + - name: TZ1_SW_CBC + description: "Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TZ1_F2_CBC + description: "event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TZ1_F1_CBC + description: "event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TZ1_F0_CBC + description: "event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TZ1_SW_OST + description: "Enable register for software force one-shot mode action. 0: disable, 1: enable" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TZ1_F2_OST + description: "event_f2 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TZ1_F1_OST + description: "event_f1 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TZ1_F0_OST + description: "event_f0 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TZ1_A_CBC_D + description: "Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: TZ1_A_CBC_U + description: "Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: TZ1_A_OST_D + description: "One-shot mode action on PWM1A when fault event occurs and timer is decreasing. 0: do nothing,1: force low, 2: force high, 3: toggle" + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: TZ1_A_OST_U + description: "One-shot mode action on PWM1A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: TZ1_B_CBC_D + description: "Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: TZ1_B_CBC_U + description: "Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: TZ1_B_OST_D + description: "One-shot mode action on PWM1B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TZ1_B_OST_U + description: "One-shot mode action on PWM1B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: FH1_CFG1 + description: Software triggers for fault handler actions + addressOffset: 164 + size: 32 + fields: + - name: TZ1_CLR_OST + description: a rising edge will clear on going one-shot mode action + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TZ1_CBCPULSE + description: "cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP" + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: TZ1_FORCE_CBC + description: a toggle trigger a cycle-by-cycle mode action + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TZ1_FORCE_OST + description: a toggle (software negate its value) triggers a one-shot mode action + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: FH1_STATUS + description: Status of fault events. + addressOffset: 168 + size: 32 + fields: + - name: TZ1_CBC_ON + description: "Set and reset by hardware. If set, a cycle-by-cycle mode action is on going" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TZ1_OST_ON + description: "Set and reset by hardware. If set, an one-shot mode action is on going" + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: GEN2_STMP_CFG + description: Transfer status and update method for time stamp registers A and B + addressOffset: 172 + size: 32 + fields: + - name: CMPR2_A_UPMETHOD + description: "Update method for PWM generator 2 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: CMPR2_B_UPMETHOD + description: "Update method for PWM generator 2 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: CMPR2_A_SHDW_FULL + description: "Set and reset by hardware. If set, PWM generator 2 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CMPR2_B_SHDW_FULL + description: "Set and reset by hardware. If set, PWM generator 2 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value" + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: GEN2_TSTMP_A + description: Shadow register for register A. + addressOffset: 176 + size: 32 + fields: + - name: CMPR2_A + description: "PWM generator 2 time stamp A's shadow register" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: GEN2_TSTMP_B + description: Shadow register for register B. + addressOffset: 180 + size: 32 + fields: + - name: CMPR2_B + description: "PWM generator 2 time stamp B's shadow register" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: GEN2_CFG0 + description: Fault event T0 and T1 handling + addressOffset: 184 + size: 32 + fields: + - name: GEN2_CFG_UPMETHOD + description: "Update method for PWM generator 2's active register of configuration. 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:sync;when bit3 is set to 1:disable the update." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: GEN2_T0_SEL + description: "Source selection for PWM generator 2 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none" + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: GEN2_T1_SEL + description: "Source selection for PWM generator 2 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none" + bitOffset: 7 + bitWidth: 3 + access: read-write + - register: + name: GEN2_FORCE + description: Permissives to force PWM2A and PWM2B outputs by software + addressOffset: 188 + size: 32 + resetValue: 32 + fields: + - name: GEN2_CNTUFORCE_UPMETHOD + description: "Updating method for continuous software force of PWM generator 2. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.)" + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: GEN2_A_CNTUFORCE_MODE + description: "Continuous software force mode for PWM2A. 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: GEN2_B_CNTUFORCE_MODE + description: "Continuous software force mode for PWM2B. 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: GEN2_A_NCIFORCE + description: "Trigger of non-continuous immediate software-force event for PWM2A, a toggle will trigger a force event." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GEN2_A_NCIFORCE_MODE + description: "non-continuous immediate software force mode for PWM2A, 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: GEN2_B_NCIFORCE + description: "Trigger of non-continuous immediate software-force event for PWM2B, a toggle will trigger a force event." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: GEN2_B_NCIFORCE_MODE + description: "non-continuous immediate software force mode for PWM2B, 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: GEN2_A + description: Actions triggered by events on PWM2A + addressOffset: 192 + size: 32 + fields: + - name: UTEZ + description: Action on PWM2A triggered by event TEZ when timer increasing + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + description: Action on PWM2A triggered by event TEP when timer increasing + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + description: Action on PWM2A triggered by event TEA when timer increasing + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + description: Action on PWM2A triggered by event TEB when timer increasing + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + description: Action on PWM2A triggered by event_t0 when timer increasing + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + description: Action on PWM2A triggered by event_t1 when timer increasing + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + description: Action on PWM2A triggered by event TEZ when timer decreasing + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + description: Action on PWM2A triggered by event TEP when timer decreasing + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + description: Action on PWM2A triggered by event TEA when timer decreasing + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + description: Action on PWM2A triggered by event TEB when timer decreasing + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + description: Action on PWM2A triggered by event_t0 when timer decreasing + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + description: "Action on PWM2A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: GEN2_B + description: Actions triggered by events on PWM2B + addressOffset: 196 + size: 32 + fields: + - name: UTEZ + description: Action on PWM2B triggered by event TEZ when timer increasing + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + description: Action on PWM2B triggered by event TEP when timer increasing + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + description: Action on PWM2B triggered by event TEA when timer increasing + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + description: Action on PWM2B triggered by event TEB when timer increasing + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + description: Action on PWM2B triggered by event_t0 when timer increasing + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + description: Action on PWM2B triggered by event_t1 when timer increasing + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + description: Action on PWM2B triggered by event TEZ when timer decreasing + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + description: Action on PWM2B triggered by event TEP when timer decreasing + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + description: Action on PWM2B triggered by event TEA when timer decreasing + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + description: Action on PWM2B triggered by event TEB when timer decreasing + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + description: Action on PWM2B triggered by event_t0 when timer decreasing + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + description: "Action on PWM2B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: DT2_CFG + description: dead time type selection and configuration + addressOffset: 200 + size: 32 + resetValue: 98304 + fields: + - name: DB2_FED_UPMETHOD + description: "Update method for FED (falling edge delay) active register. 0: immediate,when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update" + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: DB2_RED_UPMETHOD + description: "Update method for RED (rising edge delay) active register. 0: immediate,when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update" + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: DB2_DEB_MODE + description: "S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DB2_A_OUTSWAP + description: S6 in table + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DB2_B_OUTSWAP + description: S7 in table + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DB2_RED_INSEL + description: S4 in table + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DB2_FED_INSEL + description: S5 in table + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DB2_RED_OUTINVERT + description: S2 in table + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DB2_FED_OUTINVERT + description: S3 in table + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DB2_A_OUTBYPASS + description: S1 in table + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DB2_B_OUTBYPASS + description: S0 in table + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DB2_CLK_SEL + description: "Dead time generator 2 clock selection. 0: PWM_clk, 1: PT_clk" + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: DT2_FED_CFG + description: Shadow register for falling edge delay (FED). + addressOffset: 204 + size: 32 + fields: + - name: DB2_FED + description: Shadow register for FED + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: DT2_RED_CFG + description: Shadow register for rising edge delay (RED). + addressOffset: 208 + size: 32 + fields: + - name: DB2_RED + description: Shadow register for RED + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: CARRIER2_CFG + description: Carrier enable and configuratoin + addressOffset: 212 + size: 32 + fields: + - name: CHOPPER2_EN + description: "When set, carrier2 function is enabled. When cleared, carrier2 is bypassed" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CHOPPER2_PRESCALE + description: PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CHOPPER2_DUTY + description: carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + bitOffset: 5 + bitWidth: 3 + access: read-write + - name: CHOPPER2_OSHTWTH + description: width of the first pulse in number of periods of the carrier + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: CHOPPER2_OUT_INVERT + description: "when set, invert the output of PWM2A and PWM2B for this submodule" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CHOPPER2_IN_INVERT + description: "when set, invert the input of PWM2A and PWM2B for this submodule" + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: FH2_CFG0 + description: Actions on PWM2A and PWM2B trip events + addressOffset: 216 + size: 32 + fields: + - name: TZ2_SW_CBC + description: "Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TZ2_F2_CBC + description: "event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TZ2_F1_CBC + description: "event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TZ2_F0_CBC + description: "event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TZ2_SW_OST + description: "Enable register for software force one-shot mode action. 0: disable, 1: enable" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TZ2_F2_OST + description: "event_f2 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TZ2_F1_OST + description: "event_f1 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TZ2_F0_OST + description: "event_f0 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TZ2_A_CBC_D + description: "Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: TZ2_A_CBC_U + description: "Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: TZ2_A_OST_D + description: "One-shot mode action on PWM2A when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: TZ2_A_OST_U + description: "One-shot mode action on PWM2A when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: TZ2_B_CBC_D + description: "Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: TZ2_B_CBC_U + description: "Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: TZ2_B_OST_D + description: "One-shot mode action on PWM2B when fault event occurs and timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TZ2_B_OST_U + description: "One-shot mode action on PWM2B when fault event occurs and timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: FH2_CFG1 + description: Software triggers for fault handler actions + addressOffset: 220 + size: 32 + fields: + - name: TZ2_CLR_OST + description: a rising edge will clear on going one-shot mode action + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TZ2_CBCPULSE + description: "cycle-by-cycle mode action refresh moment selection. When bit0 is set to 1: TEZ, when bit1 is set to 1:TEP" + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: TZ2_FORCE_CBC + description: a toggle trigger a cycle-by-cycle mode action + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TZ2_FORCE_OST + description: a toggle (software negate its value) triggers a one-shot mode action + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: FH2_STATUS + description: Status of fault events. + addressOffset: 224 + size: 32 + fields: + - name: TZ2_CBC_ON + description: "Set and reset by hardware. If set, a cycle-by-cycle mode action is on going" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TZ2_OST_ON + description: "Set and reset by hardware. If set, an one-shot mode action is on going" + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: FAULT_DETECT + description: Fault detection configuration and status + addressOffset: 228 + size: 32 + fields: + - name: F0_EN + description: "When set, event_f0 generation is enabled" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: F1_EN + description: "When set, event_f1 generation is enabled" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: F2_EN + description: "When set, event_f2 generation is enabled" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: F0_POLE + description: "Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: F1_POLE + description: "Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: F2_POLE + description: "Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: EVENT_F0 + description: "Set and reset by hardware. If set, event_f0 is on going" + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: EVENT_F1 + description: "Set and reset by hardware. If set, event_f1 is on going" + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: EVENT_F2 + description: "Set and reset by hardware. If set, event_f2 is on going" + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: CAP_TIMER_CFG + description: Configure capture timer + addressOffset: 232 + size: 32 + fields: + - name: CAP_TIMER_EN + description: "When set, capture timer incrementing under APB_clk is enabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CAP_SYNCI_EN + description: "When set, capture timer sync is enabled." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CAP_SYNCI_SEL + description: "capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix" + bitOffset: 2 + bitWidth: 3 + access: read-write + - name: CAP_SYNC_SW + description: "When reg_cap_synci_en is 1, write 1 will trigger a capture timer sync, capture timer is loaded with value in phase register." + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: CAP_TIMER_PHASE + description: Phase for capture timer sync + addressOffset: 236 + size: 32 + fields: + - name: CAP_PHASE + description: Phase value for capture timer sync operation. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CAP_CH0_CFG + description: Capture channel 0 configuration and enable + addressOffset: 240 + size: 32 + fields: + - name: CAP0_EN + description: "When set, capture on channel 0 is enabled" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CAP0_MODE + description: "Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge." + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: CAP0_PRESCALE + description: Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1 + bitOffset: 3 + bitWidth: 8 + access: read-write + - name: CAP0_IN_INVERT + description: "when set, CAP0 form GPIO matrix is inverted before prescale" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CAP0_SW + description: Write 1 will trigger a software forced capture on channel 0 + bitOffset: 12 + bitWidth: 1 + access: write-only + - register: + name: CAP_CH1_CFG + description: Capture channel 1 configuration and enable + addressOffset: 244 + size: 32 + fields: + - name: CAP1_EN + description: "When set, capture on channel 2 is enabled" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CAP1_MODE + description: "Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge." + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: CAP1_PRESCALE + description: Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE + 1 + bitOffset: 3 + bitWidth: 8 + access: read-write + - name: CAP1_IN_INVERT + description: "when set, CAP1 form GPIO matrix is inverted before prescale" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CAP1_SW + description: Write 1 will trigger a software forced capture on channel 1 + bitOffset: 12 + bitWidth: 1 + access: write-only + - register: + name: CAP_CH2_CFG + description: Capture channel 2 configuration and enable + addressOffset: 248 + size: 32 + fields: + - name: CAP2_EN + description: "When set, capture on channel 2 is enabled" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CAP2_MODE + description: "Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge." + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: CAP2_PRESCALE + description: Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE + 1 + bitOffset: 3 + bitWidth: 8 + access: read-write + - name: CAP2_IN_INVERT + description: "when set, CAP2 form GPIO matrix is inverted before prescale" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CAP2_SW + description: Write 1 will trigger a software forced capture on channel 2 + bitOffset: 12 + bitWidth: 1 + access: write-only + - register: + name: CAP_CH0 + description: ch0 capture value status register + addressOffset: 252 + size: 32 + fields: + - name: CAP0_VALUE + description: Value of last capture on channel 0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CAP_CH1 + description: ch1 capture value status register + addressOffset: 256 + size: 32 + fields: + - name: CAP1_VALUE + description: Value of last capture on channel 1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CAP_CH2 + description: ch2 capture value status register + addressOffset: 260 + size: 32 + fields: + - name: CAP2_VALUE + description: Value of last capture on channel 2 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CAP_STATUS + description: Edge of last capture trigger + addressOffset: 264 + size: 32 + fields: + - name: CAP0_EDGE + description: "Edge of last capture trigger on channel 0, 0: posedge, 1: negedge" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CAP1_EDGE + description: "Edge of last capture trigger on channel 1, 0: posedge, 1: negedge" + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CAP2_EDGE + description: "Edge of last capture trigger on channel 2, 0: posedge, 1: negedge" + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: UPDATE_CFG + description: Enable update. + addressOffset: 268 + size: 32 + resetValue: 85 + fields: + - name: GLOBAL_UP_EN + description: The global enable of update of all active registers in MCPWM module + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: GLOBAL_FORCE_UP + description: a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OP0_UP_EN + description: "When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 are enabled" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OP0_FORCE_UP + description: a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OP1_UP_EN + description: "When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 are enabled" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OP1_FORCE_UP + description: a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OP2_UP_EN + description: "When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 are enabled" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OP2_FORCE_UP + description: a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2 + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 272 + size: 32 + fields: + - name: TIMER0_STOP_INT_ENA + description: The enable bit for the interrupt triggered when the timer 0 stops. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMER1_STOP_INT_ENA + description: The enable bit for the interrupt triggered when the timer 1 stops. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER2_STOP_INT_ENA + description: The enable bit for the interrupt triggered when the timer 2 stops. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TIMER0_TEZ_INT_ENA + description: The enable bit for the interrupt triggered by a PWM timer 0 TEZ event. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TIMER1_TEZ_INT_ENA + description: The enable bit for the interrupt triggered by a PWM timer 1 TEZ event. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TIMER2_TEZ_INT_ENA + description: The enable bit for the interrupt triggered by a PWM timer 2 TEZ event. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TIMER0_TEP_INT_ENA + description: The enable bit for the interrupt triggered by a PWM timer 0 TEP event. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TIMER1_TEP_INT_ENA + description: The enable bit for the interrupt triggered by a PWM timer 1 TEP event. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TIMER2_TEP_INT_ENA + description: The enable bit for the interrupt triggered by a PWM timer 2 TEP event. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FAULT0_INT_ENA + description: The enable bit for the interrupt triggered when event_f0 starts. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FAULT1_INT_ENA + description: The enable bit for the interrupt triggered when event_f1 starts. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FAULT2_INT_ENA + description: The enable bit for the interrupt triggered when event_f2 starts. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FAULT0_CLR_INT_ENA + description: The enable bit for the interrupt triggered when event_f0 ends. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FAULT1_CLR_INT_ENA + description: The enable bit for the interrupt triggered when event_f1 ends. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FAULT2_CLR_INT_ENA + description: The enable bit for the interrupt triggered when event_f2 ends. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CMPR0_TEA_INT_ENA + description: The enable bit for the interrupt triggered by a PWM operator 0 TEA event + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CMPR1_TEA_INT_ENA + description: The enable bit for the interrupt triggered by a PWM operator 1 TEA event + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CMPR2_TEA_INT_ENA + description: The enable bit for the interrupt triggered by a PWM operator 2 TEA event + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: CMPR0_TEB_INT_ENA + description: The enable bit for the interrupt triggered by a PWM operator 0 TEB event + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: CMPR1_TEB_INT_ENA + description: The enable bit for the interrupt triggered by a PWM operator 1 TEB event + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: CMPR2_TEB_INT_ENA + description: The enable bit for the interrupt triggered by a PWM operator 2 TEB event + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TZ0_CBC_INT_ENA + description: The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: TZ1_CBC_INT_ENA + description: The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TZ2_CBC_INT_ENA + description: The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TZ0_OST_INT_ENA + description: The enable bit for the interrupt triggered by a one-shot mode action on PWM0. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TZ1_OST_INT_ENA + description: The enable bit for the interrupt triggered by a one-shot mode action on PWM1. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TZ2_OST_INT_ENA + description: The enable bit for the interrupt triggered by a one-shot mode action on PWM2. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CAP0_INT_ENA + description: The enable bit for the interrupt triggered by capture on channel 0. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: CAP1_INT_ENA + description: The enable bit for the interrupt triggered by capture on channel 1. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CAP2_INT_ENA + description: The enable bit for the interrupt triggered by capture on channel 2. + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 276 + size: 32 + fields: + - name: TIMER0_STOP_INT_RAW + description: The raw status bit for the interrupt triggered when the timer 0 stops. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMER1_STOP_INT_RAW + description: The raw status bit for the interrupt triggered when the timer 1 stops. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER2_STOP_INT_RAW + description: The raw status bit for the interrupt triggered when the timer 2 stops. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TIMER0_TEZ_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TIMER1_TEZ_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TIMER2_TEZ_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TIMER0_TEP_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM timer 0 TEP event. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TIMER1_TEP_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM timer 1 TEP event. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TIMER2_TEP_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM timer 2 TEP event. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FAULT0_INT_RAW + description: The raw status bit for the interrupt triggered when event_f0 starts. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FAULT1_INT_RAW + description: The raw status bit for the interrupt triggered when event_f1 starts. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FAULT2_INT_RAW + description: The raw status bit for the interrupt triggered when event_f2 starts. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FAULT0_CLR_INT_RAW + description: The raw status bit for the interrupt triggered when event_f0 ends. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FAULT1_CLR_INT_RAW + description: The raw status bit for the interrupt triggered when event_f1 ends. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FAULT2_CLR_INT_RAW + description: The raw status bit for the interrupt triggered when event_f2 ends. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CMPR0_TEA_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM operator 0 TEA event + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CMPR1_TEA_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM operator 1 TEA event + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CMPR2_TEA_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM operator 2 TEA event + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: CMPR0_TEB_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM operator 0 TEB event + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: CMPR1_TEB_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM operator 1 TEB event + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: CMPR2_TEB_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM operator 2 TEB event + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TZ0_CBC_INT_RAW + description: The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: TZ1_CBC_INT_RAW + description: The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TZ2_CBC_INT_RAW + description: The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TZ0_OST_INT_RAW + description: The raw status bit for the interrupt triggered by a one-shot mode action on PWM0. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TZ1_OST_INT_RAW + description: The raw status bit for the interrupt triggered by a one-shot mode action on PWM1. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TZ2_OST_INT_RAW + description: The raw status bit for the interrupt triggered by a one-shot mode action on PWM2. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CAP0_INT_RAW + description: The raw status bit for the interrupt triggered by capture on channel 0. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: CAP1_INT_RAW + description: The raw status bit for the interrupt triggered by capture on channel 1. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CAP2_INT_RAW + description: The raw status bit for the interrupt triggered by capture on channel 2. + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 280 + size: 32 + fields: + - name: TIMER0_STOP_INT_ST + description: The masked status bit for the interrupt triggered when the timer 0 stops. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TIMER1_STOP_INT_ST + description: The masked status bit for the interrupt triggered when the timer 1 stops. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TIMER2_STOP_INT_ST + description: The masked status bit for the interrupt triggered when the timer 2 stops. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TIMER0_TEZ_INT_ST + description: The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TIMER1_TEZ_INT_ST + description: The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TIMER2_TEZ_INT_ST + description: The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: TIMER0_TEP_INT_ST + description: The masked status bit for the interrupt triggered by a PWM timer 0 TEP event. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TIMER1_TEP_INT_ST + description: The masked status bit for the interrupt triggered by a PWM timer 1 TEP event. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIMER2_TEP_INT_ST + description: The masked status bit for the interrupt triggered by a PWM timer 2 TEP event. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: FAULT0_INT_ST + description: The masked status bit for the interrupt triggered when event_f0 starts. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: FAULT1_INT_ST + description: The masked status bit for the interrupt triggered when event_f1 starts. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: FAULT2_INT_ST + description: The masked status bit for the interrupt triggered when event_f2 starts. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: FAULT0_CLR_INT_ST + description: The masked status bit for the interrupt triggered when event_f0 ends. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: FAULT1_CLR_INT_ST + description: The masked status bit for the interrupt triggered when event_f1 ends. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: FAULT2_CLR_INT_ST + description: The masked status bit for the interrupt triggered when event_f2 ends. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: CMPR0_TEA_INT_ST + description: The masked status bit for the interrupt triggered by a PWM operator 0 TEA event + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: CMPR1_TEA_INT_ST + description: The masked status bit for the interrupt triggered by a PWM operator 1 TEA event + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: CMPR2_TEA_INT_ST + description: The masked status bit for the interrupt triggered by a PWM operator 2 TEA event + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: CMPR0_TEB_INT_ST + description: The masked status bit for the interrupt triggered by a PWM operator 0 TEB event + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: CMPR1_TEB_INT_ST + description: The masked status bit for the interrupt triggered by a PWM operator 1 TEB event + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: CMPR2_TEB_INT_ST + description: The masked status bit for the interrupt triggered by a PWM operator 2 TEB event + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: TZ0_CBC_INT_ST + description: The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: TZ1_CBC_INT_ST + description: The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: TZ2_CBC_INT_ST + description: The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: TZ0_OST_INT_ST + description: The masked status bit for the interrupt triggered by a one-shot mode action on PWM0. + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: TZ1_OST_INT_ST + description: The masked status bit for the interrupt triggered by a one-shot mode action on PWM1. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: TZ2_OST_INT_ST + description: The masked status bit for the interrupt triggered by a one-shot mode action on PWM2. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: CAP0_INT_ST + description: The masked status bit for the interrupt triggered by capture on channel 0. + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: CAP1_INT_ST + description: The masked status bit for the interrupt triggered by capture on channel 1. + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: CAP2_INT_ST + description: The masked status bit for the interrupt triggered by capture on channel 2. + bitOffset: 29 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 284 + size: 32 + fields: + - name: TIMER0_STOP_INT_CLR + description: Set this bit to clear the interrupt triggered when the timer 0 stops. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TIMER1_STOP_INT_CLR + description: Set this bit to clear the interrupt triggered when the timer 1 stops. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TIMER2_STOP_INT_CLR + description: Set this bit to clear the interrupt triggered when the timer 2 stops. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TIMER0_TEZ_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TIMER1_TEZ_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: TIMER2_TEZ_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TIMER0_TEP_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TIMER1_TEP_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: TIMER2_TEP_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: FAULT0_INT_CLR + description: Set this bit to clear the interrupt triggered when event_f0 starts. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: FAULT1_INT_CLR + description: Set this bit to clear the interrupt triggered when event_f1 starts. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: FAULT2_INT_CLR + description: Set this bit to clear the interrupt triggered when event_f2 starts. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: FAULT0_CLR_INT_CLR + description: Set this bit to clear the interrupt triggered when event_f0 ends. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: FAULT1_CLR_INT_CLR + description: Set this bit to clear the interrupt triggered when event_f1 ends. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: FAULT2_CLR_INT_CLR + description: Set this bit to clear the interrupt triggered when event_f2 ends. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: CMPR0_TEA_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: CMPR1_TEA_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: CMPR2_TEA_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: CMPR0_TEB_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: CMPR1_TEB_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: CMPR2_TEB_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: TZ0_CBC_INT_CLR + description: Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0. + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: TZ1_CBC_INT_CLR + description: Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1. + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: TZ2_CBC_INT_CLR + description: Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2. + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: TZ0_OST_INT_CLR + description: Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0. + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: TZ1_OST_INT_CLR + description: Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1. + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: TZ2_OST_INT_CLR + description: Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2. + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: CAP0_INT_CLR + description: Set this bit to clear the interrupt triggered by capture on channel 0. + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: CAP1_INT_CLR + description: Set this bit to clear the interrupt triggered by capture on channel 1. + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: CAP2_INT_CLR + description: Set this bit to clear the interrupt triggered by capture on channel 2. + bitOffset: 29 + bitWidth: 1 + access: write-only + - register: + name: EVT_EN + description: MCPWM event enable register + addressOffset: 288 + size: 32 + fields: + - name: EVT_TIMER0_STOP_EN + description: set this bit high to enable timer0 stop event generate + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EVT_TIMER1_STOP_EN + description: set this bit high to enable timer1 stop event generate + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EVT_TIMER2_STOP_EN + description: set this bit high to enable timer2 stop event generate + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EVT_TIMER0_TEZ_EN + description: set this bit high to enable timer0 equal zero event generate + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: EVT_TIMER1_TEZ_EN + description: set this bit high to enable timer1 equal zero event generate + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: EVT_TIMER2_TEZ_EN + description: set this bit high to enable timer2 equal zero event generate + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: EVT_TIMER0_TEP_EN + description: set this bit high to enable timer0 equal period event generate + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: EVT_TIMER1_TEP_EN + description: set this bit high to enable timer1 equal period event generate + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: EVT_TIMER2_TEP_EN + description: set this bit high to enable timer2 equal period event generate + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: EVT_OP0_TEA_EN + description: set this bit high to enable PWM generator0 timer equal a event generate + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: EVT_OP1_TEA_EN + description: set this bit high to enable PWM generator1 timer equal a event generate + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: EVT_OP2_TEA_EN + description: set this bit high to enable PWM generator2 timer equal a event generate + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: EVT_OP0_TEB_EN + description: set this bit high to enable PWM generator0 timer equal b event generate + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: EVT_OP1_TEB_EN + description: set this bit high to enable PWM generator1 timer equal b event generate + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: EVT_OP2_TEB_EN + description: set this bit high to enable PWM generator2 timer equal b event generate + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: EVT_F0_EN + description: set this bit high to enable fault0 event generate + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: EVT_F1_EN + description: set this bit high to enable fault1 event generate + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: EVT_F2_EN + description: set this bit high to enable fault2 event generate + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: EVT_F0_CLR_EN + description: set this bit high to enable fault0 clear event generate + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: EVT_F1_CLR_EN + description: set this bit high to enable fault1 clear event generate + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: EVT_F2_CLR_EN + description: set this bit high to enable fault2 clear event generate + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: EVT_TZ0_CBC_EN + description: set this bit high to enable cycle by cycle trip0 event generate + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: EVT_TZ1_CBC_EN + description: set this bit high to enable cycle by cycle trip1 event generate + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: EVT_TZ2_CBC_EN + description: set this bit high to enable cycle by cycle trip2 event generate + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: EVT_TZ0_OST_EN + description: set this bit high to enable one shot trip0 event generate + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: EVT_TZ1_OST_EN + description: set this bit high to enable one shot trip1 event generate + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: EVT_TZ2_OST_EN + description: set this bit high to enable one shot trip2 event generate + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: EVT_CAP0_EN + description: set this bit high to enable capture0 event generate + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: EVT_CAP1_EN + description: set this bit high to enable capture1 event generate + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: EVT_CAP2_EN + description: set this bit high to enable capture2 event generate + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: TASK_EN + description: MCPWM task enable register + addressOffset: 292 + size: 32 + fields: + - name: TASK_CMPR0_A_UP_EN + description: "set this bit high to enable PWM generator0 timer stamp A's shadow register update task receive" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TASK_CMPR1_A_UP_EN + description: "set this bit high to enable PWM generator1 timer stamp A's shadow register update task receive" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TASK_CMPR2_A_UP_EN + description: "set this bit high to enable PWM generator2 timer stamp A's shadow register update task receive" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TASK_CMPR0_B_UP_EN + description: "set this bit high to enable PWM generator0 timer stamp B's shadow register update task receive" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TASK_CMPR1_B_UP_EN + description: "set this bit high to enable PWM generator1 timer stamp B's shadow register update task receive" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TASK_CMPR2_B_UP_EN + description: "set this bit high to enable PWM generator2 timer stamp B's shadow register update task receive" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TASK_GEN_STOP_EN + description: set this bit high to enable all PWM generate stop task receive + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TASK_TIMER0_SYNC_EN + description: set this bit high to enable timer0 sync task receive + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TASK_TIMER1_SYNC_EN + description: set this bit high to enable timer1 sync task receive + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TASK_TIMER2_SYNC_EN + description: set this bit high to enable timer2 sync task receive + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TASK_TIMER0_PERIOD_UP_EN + description: set this bit high to enable timer0 period update task receive + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TASK_TIMER1_PERIOD_UP_EN + description: set this bit high to enable timer1 period update task receive + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TASK_TIMER2_PERIOD_UP_EN + description: set this bit high to enable timer2 period update task receive + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TASK_TZ0_OST_EN + description: set this bit high to enable one shot trip0 task receive + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TASK_TZ1_OST_EN + description: set this bit high to enable one shot trip1 task receive + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TASK_TZ2_OST_EN + description: set this bit high to enable one shot trip2 task receive + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TASK_CLR0_OST_EN + description: set this bit high to enable one shot trip0 clear task receive + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: TASK_CLR1_OST_EN + description: set this bit high to enable one shot trip1 clear task receive + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: TASK_CLR2_OST_EN + description: set this bit high to enable one shot trip2 clear task receive + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TASK_CAP0_EN + description: set this bit high to enable capture0 task receive + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: TASK_CAP1_EN + description: set this bit high to enable capture1 task receive + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TASK_CAP2_EN + description: set this bit high to enable capture2 task receive + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + name: CLK + description: MCPWM APB configuration register + addressOffset: 296 + size: 32 + fields: + - name: EN + description: Force clock on for this register file + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: VERSION + description: Version register. + addressOffset: 300 + size: 32 + resetValue: 35656256 + fields: + - name: DATE + description: Version of this register file + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: MEM_MONITOR + description: MEM_MONITOR Peripheral + groupName: MEM_MONITOR + baseAddress: 1611210752 + addressBlock: + - offset: 0 + size: 48 + usage: registers + registers: + - register: + name: LOG_SETTING + description: log config regsiter + addressOffset: 0 + size: 32 + resetValue: 128 + fields: + - name: LOG_ENA + description: "enable bus log. BIT0: hp-cpu, BIT1: lp-cpu, BIT2: DMA.823 don't support lp-cpu" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: LOG_MODE + description: "This field must be onehot. 4'b0001 : WR monitor, 4'b0010: WORD monitor, 4'b0100: HALFWORD monitor, 4'b1000: BYTE monitor." + bitOffset: 3 + bitWidth: 4 + access: read-write + - name: LOG_MEM_LOOP_ENABLE + description: "Set 1 enable mem_loop, it will loop write at the range of MEM_START and MEM_END" + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: LOG_CHECK_DATA + description: check data regsiter + addressOffset: 4 + size: 32 + fields: + - name: LOG_CHECK_DATA + description: "The special check data, when write this special data, it will trigger logging." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOG_DATA_MASK + description: check data mask register + addressOffset: 8 + size: 32 + fields: + - name: LOG_DATA_MASK + description: "byte mask enable, BIT0 mask the first byte of MEM_MONITOR_LOG_CHECK_DATA, and BIT1 mask second byte, and so on." + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: LOG_MIN + description: log boundary regsiter + addressOffset: 12 + size: 32 + fields: + - name: LOG_MIN + description: the min address of log range + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOG_MAX + description: log boundary regsiter + addressOffset: 16 + size: 32 + fields: + - name: LOG_MAX + description: the max address of log range + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOG_MEM_START + description: log message store range register + addressOffset: 20 + size: 32 + fields: + - name: LOG_MEM_START + description: the start address of writing logging message + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOG_MEM_END + description: log message store range register + addressOffset: 24 + size: 32 + fields: + - name: LOG_MEM_END + description: the end address of writing logging message + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOG_MEM_CURRENT_ADDR + description: current writing address. + addressOffset: 28 + size: 32 + fields: + - name: LOG_MEM_CURRENT_ADDR + description: means next writing address + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: LOG_MEM_ADDR_UPDATE + description: writing address update + addressOffset: 32 + size: 32 + fields: + - name: LOG_MEM_ADDR_UPDATE + description: "Set 1 to updata MEM_MONITOR_LOG_MEM_CURRENT_ADDR, when set 1, MEM_MONITOR_LOG_MEM_CURRENT_ADDR will update to MEM_MONITOR_LOG_MEM_START" + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: LOG_MEM_FULL_FLAG + description: full flag status register + addressOffset: 36 + size: 32 + fields: + - name: LOG_MEM_FULL_FLAG + description: 1 means memory write loop at least one time at the range of MEM_START and MEM_END + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CLR_LOG_MEM_FULL_FLAG + description: Set 1 to clr MEM_MONITOR_LOG_MEM_FULL_FLAG + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: CLOCK_GATE + description: clock gate force on register + addressOffset: 40 + size: 32 + fields: + - name: CLK_EN + description: Set 1 to force on the clk of mem_monitor register + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: version register + addressOffset: 1020 + size: 32 + resetValue: 35660096 + fields: + - name: DATE + description: version register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: MODEM_LPCON + description: MODEM_LPCON Peripheral + groupName: MODEM_LPCON + baseAddress: 1611321344 + addressBlock: + - offset: 0 + size: 32 + usage: registers + registers: + - register: + name: TEST_CONF + addressOffset: 0 + size: 32 + fields: + - name: CLK_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: COEX_LP_CLK_CONF + addressOffset: 4 + size: 32 + fields: + - name: CLK_COEX_LP_SEL_OSC_SLOW + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CLK_COEX_LP_SEL_OSC_FAST + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CLK_COEX_LP_SEL_XTAL + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CLK_COEX_LP_SEL_XTAL32K + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CLK_COEX_LP_DIV_NUM + bitOffset: 4 + bitWidth: 12 + access: read-write + - register: + name: CLK_CONF + addressOffset: 8 + size: 32 + fields: + - name: CLK_COEX_EN + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CLK_I2C_MST_EN + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CLK_FE_MEM_EN + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: CLK_CONF_FORCE_ON + addressOffset: 12 + size: 32 + fields: + - name: CLK_COEX_FO + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CLK_I2C_MST_FO + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CLK_FE_MEM_FO + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: TICK_CONF + addressOffset: 16 + size: 32 + resetValue: 31 + fields: + - name: PWR_TICK_TARGET + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: RST_CONF + addressOffset: 20 + size: 32 + fields: + - name: RST_COEX + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RST_I2C_MST + bitOffset: 2 + bitWidth: 1 + access: write-only + - register: + name: MEM_CONF + addressOffset: 24 + size: 32 + resetValue: 2261012 + fields: + - name: AGC_MEM_FORCE_PU + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: AGC_MEM_FORCE_PD + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PBUS_MEM_FORCE_PU + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: PBUS_MEM_FORCE_PD + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: I2C_MST_MEM_FORCE_PU + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: I2C_MST_MEM_FORCE_PD + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CHAN_FREQ_MEM_FORCE_PU + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CHAN_FREQ_MEM_FORCE_PD + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: MODEM_PWR_MEM_WP + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: MODEM_PWR_MEM_WA + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: MODEM_PWR_MEM_RA + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: MODEM_PWR_MEM_RM + bitOffset: 20 + bitWidth: 4 + access: read-write + - register: + name: DATE + addressOffset: 28 + size: 32 + resetValue: 35689088 + fields: + - name: DATE + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: MODEM_SYSCON + description: MODEM_SYSCON Peripheral + groupName: MODEM_SYSCON + baseAddress: 1611289600 + addressBlock: + - offset: 0 + size: 32 + usage: registers + registers: + - register: + name: TEST_CONF + addressOffset: 0 + size: 32 + fields: + - name: CLK_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CLK_CONF + addressOffset: 4 + size: 32 + fields: + - name: CLK_ETM_EN + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CLK_ZB_APB_EN + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: CLK_ZB_MAC_EN + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: CLK_MODEM_SEC_ECB_EN + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: CLK_MODEM_SEC_CCM_EN + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: CLK_MODEM_SEC_BAH_EN + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CLK_MODEM_SEC_APB_EN + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: CLK_MODEM_SEC_EN + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CLK_BLE_TIMER_APB_EN + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CLK_BLE_TIMER_EN + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CLK_DATA_DUMP_EN + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CLK_CONF_FORCE_ON + addressOffset: 8 + size: 32 + fields: + - name: CLK_ETM_FO + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: CLK_ZB_FO + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: CLK_MODEM_SEC_FO + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CLK_BLE_TIMER_FO + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CLK_DATA_DUMP_FO + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: MODEM_RST_CONF + addressOffset: 12 + size: 32 + fields: + - name: RST_FE + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RST_BTMAC_APB + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RST_BTMAC + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RST_BTBB_APB + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: RST_BTBB + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RST_ETM + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RST_ZBMAC + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: RST_MODEM_ECB + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: RST_MODEM_CCM + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RST_MODEM_BAH + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RST_MODEM_SEC + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: RST_BLE_TIMER + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: RST_DATA_DUMP + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CLK_CONF1 + addressOffset: 16 + size: 32 + fields: + - name: CLK_FE_16M_EN + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CLK_FE_32M_EN + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: CLK_FE_SDM_EN + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CLK_FE_ADC_EN + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CLK_FE_APB_EN + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CLK_BT_APB_EN + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: CLK_BT_EN + bitOffset: 18 + bitWidth: 1 + access: read-write + - register: + name: CLK_CONF1_FORCE_ON + addressOffset: 20 + size: 32 + fields: + - name: CLK_FE_FO + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CLK_BT_FO + bitOffset: 18 + bitWidth: 1 + access: read-write + - register: + name: MEM_CONF + addressOffset: 24 + size: 32 + resetValue: 32 + fields: + - name: MODEM_MEM_WP + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: MODEM_MEM_WA + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: MODEM_MEM_RA + bitOffset: 6 + bitWidth: 2 + access: read-write + - register: + name: DATE + addressOffset: 28 + size: 32 + resetValue: 35685120 + fields: + - name: DATE + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: OTP_DEBUG + description: OTP_DEBUG Peripheral + groupName: OTP_DEBUG + baseAddress: 1611348992 + addressBlock: + - offset: 0 + size: 528 + usage: registers + registers: + - register: + name: WR_DIS + description: Otp debuger block0 data register1. + addressOffset: 0 + size: 32 + fields: + - name: BLOCK0_WR_DIS + description: Otp block0 write disable data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP1_W1 + description: Otp debuger block0 data register2. + addressOffset: 4 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP1_W1 + description: Otp block0 backup1 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP1_W2 + description: Otp debuger block0 data register3. + addressOffset: 8 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP1_W2 + description: Otp block0 backup1 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP1_W3 + description: Otp debuger block0 data register4. + addressOffset: 12 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP1_W3 + description: Otp block0 backup1 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP1_W4 + description: Otp debuger block0 data register5. + addressOffset: 16 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP1_W4 + description: Otp block0 backup1 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP1_W5 + description: Otp debuger block0 data register6. + addressOffset: 20 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP1_W5 + description: Otp block0 backup1 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP2_W1 + description: Otp debuger block0 data register7. + addressOffset: 24 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP2_W1 + description: Otp block0 backup2 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP2_W2 + description: Otp debuger block0 data register8. + addressOffset: 28 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP2_W2 + description: Otp block0 backup2 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP2_W3 + description: Otp debuger block0 data register9. + addressOffset: 32 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP2_W3 + description: Otp block0 backup2 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP2_W4 + description: Otp debuger block0 data register10. + addressOffset: 36 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP2_W4 + description: Otp block0 backup2 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP2_W5 + description: Otp debuger block0 data register11. + addressOffset: 40 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP2_W5 + description: Otp block0 backup2 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP3_W1 + description: Otp debuger block0 data register12. + addressOffset: 44 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP3_W1 + description: Otp block0 backup3 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP3_W2 + description: Otp debuger block0 data register13. + addressOffset: 48 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP3_W2 + description: Otp block0 backup3 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP3_W3 + description: Otp debuger block0 data register14. + addressOffset: 52 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP3_W3 + description: Otp block0 backup3 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP3_W4 + description: Otp debuger block0 data register15. + addressOffset: 56 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP3_W4 + description: Otp block0 backup3 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP3_W5 + description: Otp debuger block0 data register16. + addressOffset: 60 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP3_W5 + description: Otp block0 backup3 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP4_W1 + description: Otp debuger block0 data register17. + addressOffset: 64 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP4_W1 + description: Otp block0 backup4 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP4_W2 + description: Otp debuger block0 data register18. + addressOffset: 68 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP4_W2 + description: Otp block0 backup4 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP4_W3 + description: Otp debuger block0 data register19. + addressOffset: 72 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP4_W3 + description: Otp block0 backup4 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP4_W4 + description: Otp debuger block0 data register20. + addressOffset: 76 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP4_W4 + description: Otp block0 backup4 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK0_BACKUP4_W5 + description: Otp debuger block0 data register21. + addressOffset: 80 + size: 32 + fields: + - name: OTP_BEBUG_BLOCK0_BACKUP4_W5 + description: Otp block0 backup4 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_W1 + description: Otp debuger block1 data register1. + addressOffset: 84 + size: 32 + fields: + - name: BLOCK1_W1 + description: Otp block1 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_W2 + description: Otp debuger block1 data register2. + addressOffset: 88 + size: 32 + fields: + - name: BLOCK1_W2 + description: Otp block1 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_W3 + description: Otp debuger block1 data register3. + addressOffset: 92 + size: 32 + fields: + - name: BLOCK1_W3 + description: Otp block1 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_W4 + description: Otp debuger block1 data register4. + addressOffset: 96 + size: 32 + fields: + - name: BLOCK1_W4 + description: Otp block1 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_W5 + description: Otp debuger block1 data register5. + addressOffset: 100 + size: 32 + fields: + - name: BLOCK1_W5 + description: Otp block1 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_W6 + description: Otp debuger block1 data register6. + addressOffset: 104 + size: 32 + fields: + - name: BLOCK1_W6 + description: Otp block1 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_W7 + description: Otp debuger block1 data register7. + addressOffset: 108 + size: 32 + fields: + - name: BLOCK1_W7 + description: Otp block1 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_W8 + description: Otp debuger block1 data register8. + addressOffset: 112 + size: 32 + fields: + - name: BLOCK1_W8 + description: Otp block1 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK1_W9 + description: Otp debuger block1 data register9. + addressOffset: 116 + size: 32 + fields: + - name: BLOCK1_W9 + description: Otp block1 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_W1 + description: Otp debuger block2 data register1. + addressOffset: 120 + size: 32 + fields: + - name: BLOCK2_W1 + description: Otp block2 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_W2 + description: Otp debuger block2 data register2. + addressOffset: 124 + size: 32 + fields: + - name: BLOCK2_W2 + description: Otp block2 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_W3 + description: Otp debuger block2 data register3. + addressOffset: 128 + size: 32 + fields: + - name: BLOCK2_W3 + description: Otp block2 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_W4 + description: Otp debuger block2 data register4. + addressOffset: 132 + size: 32 + fields: + - name: BLOCK2_W4 + description: Otp block2 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_W5 + description: Otp debuger block2 data register5. + addressOffset: 136 + size: 32 + fields: + - name: BLOCK2_W5 + description: Otp block2 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_W6 + description: Otp debuger block2 data register6. + addressOffset: 140 + size: 32 + fields: + - name: BLOCK2_W6 + description: Otp block2 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_W7 + description: Otp debuger block2 data register7. + addressOffset: 144 + size: 32 + fields: + - name: BLOCK2_W7 + description: Otp block2 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_W8 + description: Otp debuger block2 data register8. + addressOffset: 148 + size: 32 + fields: + - name: BLOCK2_W8 + description: Otp block2 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_W9 + description: Otp debuger block2 data register9. + addressOffset: 152 + size: 32 + fields: + - name: BLOCK2_W9 + description: Otp block2 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_W10 + description: Otp debuger block2 data register10. + addressOffset: 156 + size: 32 + fields: + - name: BLOCK2_W10 + description: Otp block2 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK2_W11 + description: Otp debuger block2 data register11. + addressOffset: 160 + size: 32 + fields: + - name: BLOCK2_W11 + description: Otp block2 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_W1 + description: Otp debuger block3 data register1. + addressOffset: 164 + size: 32 + fields: + - name: BLOCK3_W1 + description: Otp block3 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_W2 + description: Otp debuger block3 data register2. + addressOffset: 168 + size: 32 + fields: + - name: BLOCK3_W2 + description: Otp block3 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_W3 + description: Otp debuger block3 data register3. + addressOffset: 172 + size: 32 + fields: + - name: BLOCK3_W3 + description: Otp block3 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_W4 + description: Otp debuger block3 data register4. + addressOffset: 176 + size: 32 + fields: + - name: BLOCK3_W4 + description: Otp block3 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_W5 + description: Otp debuger block3 data register5. + addressOffset: 180 + size: 32 + fields: + - name: BLOCK3_W5 + description: Otp block3 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_W6 + description: Otp debuger block3 data register6. + addressOffset: 184 + size: 32 + fields: + - name: BLOCK3_W6 + description: Otp block3 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_W7 + description: Otp debuger block3 data register7. + addressOffset: 188 + size: 32 + fields: + - name: BLOCK3_W7 + description: Otp block3 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_W8 + description: Otp debuger block3 data register8. + addressOffset: 192 + size: 32 + fields: + - name: BLOCK3_W8 + description: Otp block3 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_W9 + description: Otp debuger block3 data register9. + addressOffset: 196 + size: 32 + fields: + - name: BLOCK3_W9 + description: Otp block3 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_W10 + description: Otp debuger block3 data register10. + addressOffset: 200 + size: 32 + fields: + - name: BLOCK3_W10 + description: Otp block3 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK3_W11 + description: Otp debuger block3 data register11. + addressOffset: 204 + size: 32 + fields: + - name: BLOCK3_W11 + description: Otp block3 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK4_W1 + description: Otp debuger block4 data register1. + addressOffset: 208 + size: 32 + fields: + - name: BLOCK4_W1 + description: Otp block4 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK4_W2 + description: Otp debuger block4 data register2. + addressOffset: 212 + size: 32 + fields: + - name: BLOCK4_W2 + description: Otp block4 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK4_W3 + description: Otp debuger block4 data register3. + addressOffset: 216 + size: 32 + fields: + - name: BLOCK4_W3 + description: Otp block4 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK4_W4 + description: Otp debuger block4 data register4. + addressOffset: 220 + size: 32 + fields: + - name: BLOCK4_W4 + description: Otp block4 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK4_W5 + description: Otp debuger block4 data register5. + addressOffset: 224 + size: 32 + fields: + - name: BLOCK4_W5 + description: Otp block4 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK4_W6 + description: Otp debuger block4 data register6. + addressOffset: 228 + size: 32 + fields: + - name: BLOCK4_W6 + description: Otp block4 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK4_W7 + description: Otp debuger block4 data register7. + addressOffset: 232 + size: 32 + fields: + - name: BLOCK4_W7 + description: Otp block4 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK4_W8 + description: Otp debuger block4 data register8. + addressOffset: 236 + size: 32 + fields: + - name: BLOCK4_W8 + description: Otp block4 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK4_W9 + description: Otp debuger block4 data register9. + addressOffset: 240 + size: 32 + fields: + - name: BLOCK4_W9 + description: Otp block4 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK4_W10 + description: Otp debuger block4 data registe10. + addressOffset: 244 + size: 32 + fields: + - name: BLOCK4_W10 + description: Otp block4 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK4_W11 + description: Otp debuger block4 data register11. + addressOffset: 248 + size: 32 + fields: + - name: BLOCK4_W11 + description: Otp block4 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK5_W1 + description: Otp debuger block5 data register1. + addressOffset: 252 + size: 32 + fields: + - name: BLOCK5_W1 + description: Otp block5 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK5_W2 + description: Otp debuger block5 data register2. + addressOffset: 256 + size: 32 + fields: + - name: BLOCK5_W2 + description: Otp block5 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK5_W3 + description: Otp debuger block5 data register3. + addressOffset: 260 + size: 32 + fields: + - name: BLOCK5_W3 + description: Otp block5 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK5_W4 + description: Otp debuger block5 data register4. + addressOffset: 264 + size: 32 + fields: + - name: BLOCK5_W4 + description: Otp block5 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK5_W5 + description: Otp debuger block5 data register5. + addressOffset: 268 + size: 32 + fields: + - name: BLOCK5_W5 + description: Otp block5 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK5_W6 + description: Otp debuger block5 data register6. + addressOffset: 272 + size: 32 + fields: + - name: BLOCK5_W6 + description: Otp block5 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK5_W7 + description: Otp debuger block5 data register7. + addressOffset: 276 + size: 32 + fields: + - name: BLOCK5_W7 + description: Otp block5 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK5_W8 + description: Otp debuger block5 data register8. + addressOffset: 280 + size: 32 + fields: + - name: BLOCK5_W8 + description: Otp block5 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK5_W9 + description: Otp debuger block5 data register9. + addressOffset: 284 + size: 32 + fields: + - name: BLOCK5_W9 + description: Otp block5 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK5_W10 + description: Otp debuger block5 data register10. + addressOffset: 288 + size: 32 + fields: + - name: BLOCK5_W10 + description: Otp block5 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK5_W11 + description: Otp debuger block5 data register11. + addressOffset: 292 + size: 32 + fields: + - name: BLOCK5_W11 + description: Otp block5 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK6_W1 + description: Otp debuger block6 data register1. + addressOffset: 296 + size: 32 + fields: + - name: BLOCK6_W1 + description: Otp block6 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK6_W2 + description: Otp debuger block6 data register2. + addressOffset: 300 + size: 32 + fields: + - name: BLOCK6_W2 + description: Otp block6 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK6_W3 + description: Otp debuger block6 data register3. + addressOffset: 304 + size: 32 + fields: + - name: BLOCK6_W3 + description: Otp block6 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK6_W4 + description: Otp debuger block6 data register4. + addressOffset: 308 + size: 32 + fields: + - name: BLOCK6_W4 + description: Otp block6 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK6_W5 + description: Otp debuger block6 data register5. + addressOffset: 312 + size: 32 + fields: + - name: BLOCK6_W5 + description: Otp block6 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK6_W6 + description: Otp debuger block6 data register6. + addressOffset: 316 + size: 32 + fields: + - name: BLOCK6_W6 + description: Otp block6 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK6_W7 + description: Otp debuger block6 data register7. + addressOffset: 320 + size: 32 + fields: + - name: BLOCK6_W7 + description: Otp block6 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK6_W8 + description: Otp debuger block6 data register8. + addressOffset: 324 + size: 32 + fields: + - name: BLOCK6_W8 + description: Otp block6 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK6_W9 + description: Otp debuger block6 data register9. + addressOffset: 328 + size: 32 + fields: + - name: BLOCK6_W9 + description: Otp block6 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK6_W10 + description: Otp debuger block6 data register10. + addressOffset: 332 + size: 32 + fields: + - name: BLOCK6_W10 + description: Otp block6 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK6_W11 + description: Otp debuger block6 data register11. + addressOffset: 336 + size: 32 + fields: + - name: BLOCK6_W11 + description: Otp block6 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK7_W1 + description: Otp debuger block7 data register1. + addressOffset: 340 + size: 32 + fields: + - name: BLOCK7_W1 + description: Otp block7 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK7_W2 + description: Otp debuger block7 data register2. + addressOffset: 344 + size: 32 + fields: + - name: BLOCK7_W2 + description: Otp block7 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK7_W3 + description: Otp debuger block7 data register3. + addressOffset: 348 + size: 32 + fields: + - name: BLOCK7_W3 + description: Otp block7 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK7_W4 + description: Otp debuger block7 data register4. + addressOffset: 352 + size: 32 + fields: + - name: BLOCK7_W4 + description: Otp block7 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK7_W5 + description: Otp debuger block7 data register5. + addressOffset: 356 + size: 32 + fields: + - name: BLOCK7_W5 + description: Otp block7 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK7_W6 + description: Otp debuger block7 data register6. + addressOffset: 360 + size: 32 + fields: + - name: BLOCK7_W6 + description: Otp block7 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK7_W7 + description: Otp debuger block7 data register7. + addressOffset: 364 + size: 32 + fields: + - name: BLOCK7_W7 + description: Otp block7 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK7_W8 + description: Otp debuger block7 data register8. + addressOffset: 368 + size: 32 + fields: + - name: BLOCK7_W8 + description: Otp block7 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK7_W9 + description: Otp debuger block7 data register9. + addressOffset: 372 + size: 32 + fields: + - name: BLOCK7_W9 + description: Otp block7 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK7_W10 + description: Otp debuger block7 data register10. + addressOffset: 376 + size: 32 + fields: + - name: BLOCK7_W10 + description: Otp block7 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK7_W11 + description: Otp debuger block7 data register11. + addressOffset: 380 + size: 32 + fields: + - name: BLOCK7_W11 + description: Otp block7 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK8_W1 + description: Otp debuger block8 data register1. + addressOffset: 384 + size: 32 + fields: + - name: BLOCK8_W1 + description: Otp block8 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK8_W2 + description: Otp debuger block8 data register2. + addressOffset: 388 + size: 32 + fields: + - name: BLOCK8_W2 + description: Otp block8 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK8_W3 + description: Otp debuger block8 data register3. + addressOffset: 392 + size: 32 + fields: + - name: BLOCK8_W3 + description: Otp block8 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK8_W4 + description: Otp debuger block8 data register4. + addressOffset: 396 + size: 32 + fields: + - name: BLOCK8_W4 + description: Otp block8 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK8_W5 + description: Otp debuger block8 data register5. + addressOffset: 400 + size: 32 + fields: + - name: BLOCK8_W5 + description: Otp block8 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK8_W6 + description: Otp debuger block8 data register6. + addressOffset: 404 + size: 32 + fields: + - name: BLOCK8_W6 + description: Otp block8 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK8_W7 + description: Otp debuger block8 data register7. + addressOffset: 408 + size: 32 + fields: + - name: BLOCK8_W7 + description: Otp block8 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK8_W8 + description: Otp debuger block8 data register8. + addressOffset: 412 + size: 32 + fields: + - name: BLOCK8_W8 + description: Otp block8 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK8_W9 + description: Otp debuger block8 data register9. + addressOffset: 416 + size: 32 + fields: + - name: BLOCK8_W9 + description: Otp block8 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK8_W10 + description: Otp debuger block8 data register10. + addressOffset: 420 + size: 32 + fields: + - name: BLOCK8_W10 + description: Otp block8 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK8_W11 + description: Otp debuger block8 data register11. + addressOffset: 424 + size: 32 + fields: + - name: BLOCK8_W11 + description: Otp block8 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK9_W1 + description: Otp debuger block9 data register1. + addressOffset: 428 + size: 32 + fields: + - name: BLOCK9_W1 + description: Otp block9 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK9_W2 + description: Otp debuger block9 data register2. + addressOffset: 432 + size: 32 + fields: + - name: BLOCK9_W2 + description: Otp block9 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK9_W3 + description: Otp debuger block9 data register3. + addressOffset: 436 + size: 32 + fields: + - name: BLOCK9_W3 + description: Otp block9 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK9_W4 + description: Otp debuger block9 data register4. + addressOffset: 440 + size: 32 + fields: + - name: BLOCK9_W4 + description: Otp block9 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK9_W5 + description: Otp debuger block9 data register5. + addressOffset: 444 + size: 32 + fields: + - name: BLOCK9_W5 + description: Otp block9 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK9_W6 + description: Otp debuger block9 data register6. + addressOffset: 448 + size: 32 + fields: + - name: BLOCK9_W6 + description: Otp block9 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK9_W7 + description: Otp debuger block9 data register7. + addressOffset: 452 + size: 32 + fields: + - name: BLOCK9_W7 + description: Otp block9 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK9_W8 + description: Otp debuger block9 data register8. + addressOffset: 456 + size: 32 + fields: + - name: BLOCK9_W8 + description: Otp block9 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK9_W9 + description: Otp debuger block9 data register9. + addressOffset: 460 + size: 32 + fields: + - name: BLOCK9_W9 + description: Otp block9 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK9_W10 + description: Otp debuger block9 data register10. + addressOffset: 464 + size: 32 + fields: + - name: BLOCK9_W10 + description: Otp block9 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK9_W11 + description: Otp debuger block9 data register11. + addressOffset: 468 + size: 32 + fields: + - name: BLOCK9_W11 + description: Otp block9 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK10_W1 + description: Otp debuger block10 data register1. + addressOffset: 472 + size: 32 + fields: + - name: BLOCK10_W1 + description: Otp block10 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK10_W2 + description: Otp debuger block10 data register2. + addressOffset: 476 + size: 32 + fields: + - name: BLOCK10_W2 + description: Otp block10 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK10_W3 + description: Otp debuger block10 data register3. + addressOffset: 480 + size: 32 + fields: + - name: BLOCK10_W3 + description: Otp block10 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK10_W4 + description: Otp debuger block10 data register4. + addressOffset: 484 + size: 32 + fields: + - name: BLOCK10_W4 + description: Otp block10 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK10_W5 + description: Otp debuger block10 data register5. + addressOffset: 488 + size: 32 + fields: + - name: BLOCK10_W5 + description: Otp block10 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK10_W6 + description: Otp debuger block10 data register6. + addressOffset: 492 + size: 32 + fields: + - name: BLOCK10_W6 + description: Otp block10 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK10_W7 + description: Otp debuger block10 data register7. + addressOffset: 496 + size: 32 + fields: + - name: BLOCK10_W7 + description: Otp block10 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK10_W8 + description: Otp debuger block10 data register8. + addressOffset: 500 + size: 32 + fields: + - name: BLOCK10_W8 + description: Otp block10 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK10_W9 + description: Otp debuger block10 data register9. + addressOffset: 504 + size: 32 + fields: + - name: BLOCK10_W9 + description: Otp block10 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK10_W10 + description: Otp debuger block10 data register10. + addressOffset: 508 + size: 32 + fields: + - name: BLOCK19_W10 + description: Otp block10 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BLK10_W11 + description: Otp debuger block10 data register11. + addressOffset: 512 + size: 32 + fields: + - name: BLOCK10_W11 + description: Otp block10 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CLK + description: Otp debuger clk_en configuration register. + addressOffset: 516 + size: 32 + fields: + - name: EN + description: Force clock on for this register file. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: APB2OTP_EN + description: Otp_debuger apb2otp enable configuration register. + addressOffset: 520 + size: 32 + fields: + - name: APB2OTP_EN + description: Debug mode enable signal. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: eFuse version register. + addressOffset: 524 + size: 32 + resetValue: 539037736 + fields: + - name: DATE + description: Stores otp_debug version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: PARL_IO + description: Parallel IO Controller + groupName: PARL_IO + baseAddress: 1610698752 + addressBlock: + - offset: 0 + size: 84 + usage: registers + interrupt: + - name: PARL_IO_TX + value: 51 + - name: PARL_IO_RX + value: 52 + registers: + - register: + name: RX_MODE_CFG + description: Parallel RX Sampling mode configuration register. + addressOffset: 0 + size: 32 + resetValue: 14680064 + fields: + - name: RX_EXT_EN_SEL + description: Configures rx external enable signal selection from IO PAD. + bitOffset: 21 + bitWidth: 4 + access: read-write + - name: RX_SW_EN + description: Set this bit to enable data sampling by software. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: RX_EXT_EN_INV + description: Set this bit to invert the external enable signal. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RX_PULSE_SUBMODE_SEL + description: "Configures the rxd pulse sampling submode. \n4'd0: positive pulse start(data bit included) && positive pulse end(data bit included)\n4'd1: positive pulse start(data bit included) && positive pulse end (data bit excluded)\n4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit included)\n4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded)\n4'd4: positive pulse start(data bit included) && length end\n4'd5: positive pulse start(data bit excluded) && length end" + bitOffset: 27 + bitWidth: 3 + access: read-write + - name: RX_SMP_MODE_SEL + description: "Configures the rxd sampling mode. \n2'b00: external level enable mode\n2'b01: external pulse enable mode \n2'b10: internal software enable mode" + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: RX_DATA_CFG + description: Parallel RX data configuration register. + addressOffset: 4 + size: 32 + resetValue: 1610612736 + fields: + - name: RX_BITLEN + description: Configures expected byte number of received data. + bitOffset: 9 + bitWidth: 19 + access: read-write + - name: RX_DATA_ORDER_INV + description: Set this bit to invert bit order of one byte sent from RX_FIFO to DMA. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: RX_BUS_WID_SEL + description: "Configures the rxd bus width. \n3'd0: bus width is 1.\n3'd1: bus width is 2.\n3'd2: bus width is 4.\n3'd3: bus width is 8." + bitOffset: 29 + bitWidth: 3 + access: read-write + - register: + name: RX_GENRL_CFG + description: Parallel RX general configuration register. + addressOffset: 8 + size: 32 + resetValue: 570417152 + fields: + - name: RX_GATING_EN + description: Set this bit to enable the clock gating of output rx clock. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RX_TIMEOUT_THRES + description: Configures threshold of timeout counter. + bitOffset: 13 + bitWidth: 16 + access: read-write + - name: RX_TIMEOUT_EN + description: Set this bit to enable timeout function to generate error eof. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: RX_EOF_GEN_SEL + description: "Configures the DMA eof generated mechanism. 1'b0: eof generated by data byte length. 1'b1: eof generated by external enable signal." + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: RX_START_CFG + description: Parallel RX Start configuration register. + addressOffset: 12 + size: 32 + fields: + - name: RX_START + description: Set this bit to start rx data sampling. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TX_DATA_CFG + description: Parallel TX data configuration register. + addressOffset: 16 + size: 32 + resetValue: 1610612736 + fields: + - name: TX_BITLEN + description: Configures expected byte number of sent data. + bitOffset: 9 + bitWidth: 19 + access: read-write + - name: TX_DATA_ORDER_INV + description: Set this bit to invert bit order of one byte sent from TX_FIFO to IO data. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: TX_BUS_WID_SEL + description: "Configures the txd bus width. \n3'd0: bus width is 1.\n3'd1: bus width is 2.\n3'd2: bus width is 4.\n3'd3: bus width is 8." + bitOffset: 29 + bitWidth: 3 + access: read-write + - register: + name: TX_START_CFG + description: Parallel TX Start configuration register. + addressOffset: 20 + size: 32 + fields: + - name: TX_START + description: Set this bit to start tx data transmit. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TX_GENRL_CFG + description: Parallel TX general configuration register. + addressOffset: 24 + size: 32 + fields: + - name: TX_IDLE_VALUE + description: Configures bus value of transmitter in IDLE state. + bitOffset: 14 + bitWidth: 16 + access: read-write + - name: TX_GATING_EN + description: Set this bit to enable the clock gating of output tx clock. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TX_VALID_OUTPUT_EN + description: Set this bit to enable the output of tx data valid signal. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: FIFO_CFG + description: Parallel IO FIFO configuration register. + addressOffset: 28 + size: 32 + fields: + - name: TX_FIFO_SRST + description: Set this bit to reset async fifo in tx module. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: RX_FIFO_SRST + description: Set this bit to reset async fifo in rx module. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: REG_UPDATE + description: Parallel IO FIFO configuration register. + addressOffset: 32 + size: 32 + fields: + - name: RX_REG_UPDATE + description: Set this bit to update rx register configuration. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: ST + description: Parallel IO module status register0. + addressOffset: 36 + size: 32 + fields: + - name: TX_READY + description: Represents the status that tx is ready to transmit. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Parallel IO interrupt enable singal configuration register. + addressOffset: 40 + size: 32 + fields: + - name: TX_FIFO_REMPTY_INT_ENA + description: Set this bit to enable TX_FIFO_REMPTY_INT. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_FIFO_WOVF_INT_ENA + description: Set this bit to enable RX_FIFO_WOVF_INT. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TX_EOF_INT_ENA + description: Set this bit to enable TX_EOF_INT. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: Parallel IO interrupt raw singal status register. + addressOffset: 44 + size: 32 + fields: + - name: TX_FIFO_REMPTY_INT_RAW + description: The raw interrupt status of TX_FIFO_REMPTY_INT. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_FIFO_WOVF_INT_RAW + description: The raw interrupt status of RX_FIFO_WOVF_INT. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TX_EOF_INT_RAW + description: The raw interrupt status of TX_EOF_INT. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Parallel IO interrupt singal status register. + addressOffset: 48 + size: 32 + fields: + - name: TX_FIFO_REMPTY_INT_ST + description: The masked interrupt status of TX_FIFO_REMPTY_INT. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RX_FIFO_WOVF_INT_ST + description: The masked interrupt status of RX_FIFO_WOVF_INT. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TX_EOF_INT_ST + description: The masked interrupt status of TX_EOF_INT. + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: Parallel IO interrupt clear singal configuration register. + addressOffset: 52 + size: 32 + fields: + - name: TX_FIFO_REMPTY_INT_CLR + description: Set this bit to clear TX_FIFO_REMPTY_INT. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: RX_FIFO_WOVF_INT_CLR + description: Set this bit to clear RX_FIFO_WOVF_INT. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TX_EOF_INT_CLR + description: Set this bit to clear TX_EOF_INT. + bitOffset: 2 + bitWidth: 1 + access: write-only + - register: + name: RX_ST0 + description: Parallel IO RX status register0 + addressOffset: 56 + size: 32 + fields: + - name: RX_CNT + description: Indicates the cycle number of reading Rx FIFO. + bitOffset: 9 + bitWidth: 4 + access: read-only + - name: RX_FIFO_WR_BIT_CNT + description: Indicates the current written bit number into Rx FIFO. + bitOffset: 13 + bitWidth: 19 + access: read-only + - register: + name: RX_ST1 + description: Parallel IO RX status register1 + addressOffset: 60 + size: 32 + fields: + - name: RX_FIFO_RD_BIT_CNT + description: Indicates the current read bit number from Rx FIFO. + bitOffset: 13 + bitWidth: 19 + access: read-only + - register: + name: TX_ST0 + description: Parallel IO TX status register0 + addressOffset: 64 + size: 32 + fields: + - name: TX_CNT + description: Indicates the cycle number of reading Tx FIFO. + bitOffset: 6 + bitWidth: 7 + access: read-only + - name: TX_FIFO_RD_BIT_CNT + description: Indicates the current read bit number from Tx FIFO. + bitOffset: 13 + bitWidth: 19 + access: read-only + - register: + name: RX_CLK_CFG + description: Parallel IO RX clk configuration register + addressOffset: 68 + size: 32 + fields: + - name: RX_CLK_I_INV + description: Set this bit to invert the input Rx core clock. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: RX_CLK_O_INV + description: Set this bit to invert the output Rx core clock. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TX_CLK_CFG + description: Parallel IO TX clk configuration register + addressOffset: 72 + size: 32 + fields: + - name: TX_CLK_I_INV + description: Set this bit to invert the input Tx core clock. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TX_CLK_O_INV + description: Set this bit to invert the output Tx core clock. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CLK + description: Parallel IO clk configuration register + addressOffset: 288 + size: 32 + fields: + - name: EN + description: Force clock on for this register file + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: VERSION + description: Version register. + addressOffset: 1020 + size: 32 + resetValue: 35684928 + fields: + - name: DATE + description: Version of this register file + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: PAU + description: PAU Peripheral + groupName: PAU + baseAddress: 1611214848 + addressBlock: + - offset: 0 + size: 76 + usage: registers + interrupt: + - name: PAU + value: 24 + registers: + - register: + name: REGDMA_CONF + description: Peri backup control register + addressOffset: 0 + size: 32 + fields: + - name: FLOW_ERR + description: backup error type + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: START + description: backup start signal + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TO_MEM + description: backup direction(reg to mem / mem to reg) + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: LINK_SEL + description: Link select + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: START_MAC + description: mac sw backup start signal + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: TO_MEM_MAC + description: mac sw backup direction(reg to mem / mem to reg) + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SEL_MAC + description: mac hw/sw select + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: REGDMA_CLK_CONF + description: Clock control register + addressOffset: 4 + size: 32 + fields: + - name: CLK_EN + description: clock enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: REGDMA_ETM_CTRL + description: ETM start ctrl reg + addressOffset: 8 + size: 32 + fields: + - name: ETM_START_0 + description: etm_start_0 reg + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ETM_START_1 + description: etm_start_1 reg + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: ETM_START_2 + description: etm_start_2 reg + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: ETM_START_3 + description: etm_start_3 reg + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: REGDMA_LINK_0_ADDR + description: link_0_addr + addressOffset: 12 + size: 32 + fields: + - name: LINK_ADDR_0 + description: link_0_addr reg + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGDMA_LINK_1_ADDR + description: Link_1_addr + addressOffset: 16 + size: 32 + fields: + - name: LINK_ADDR_1 + description: Link_1_addr reg + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGDMA_LINK_2_ADDR + description: Link_2_addr + addressOffset: 20 + size: 32 + fields: + - name: LINK_ADDR_2 + description: Link_2_addr reg + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGDMA_LINK_3_ADDR + description: Link_3_addr + addressOffset: 24 + size: 32 + fields: + - name: LINK_ADDR_3 + description: Link_3_addr reg + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGDMA_LINK_MAC_ADDR + description: Link_mac_addr + addressOffset: 28 + size: 32 + fields: + - name: LINK_ADDR_MAC + description: Link_mac_addr reg + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGDMA_CURRENT_LINK_ADDR + description: current link addr + addressOffset: 32 + size: 32 + fields: + - name: CURRENT_LINK_ADDR + description: current link addr reg + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: REGDMA_BACKUP_ADDR + description: Backup addr + addressOffset: 36 + size: 32 + fields: + - name: BACKUP_ADDR + description: backup addr reg + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: REGDMA_MEM_ADDR + description: mem addr + addressOffset: 40 + size: 32 + fields: + - name: MEM_ADDR + description: mem addr reg + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: REGDMA_BKP_CONF + description: backup config + addressOffset: 44 + size: 32 + resetValue: 2098207008 + fields: + - name: READ_INTERVAL + description: Link read_interval + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: LINK_TOUT_THRES + description: link wait timeout threshold + bitOffset: 7 + bitWidth: 10 + access: read-write + - name: BURST_LIMIT + description: burst limit + bitOffset: 17 + bitWidth: 5 + access: read-write + - name: BACKUP_TOUT_THRES + description: Backup timeout threshold + bitOffset: 22 + bitWidth: 10 + access: read-write + - register: + name: RETENTION_LINK_BASE + description: retention dma link base + addressOffset: 48 + size: 32 + fields: + - name: LINK_BASE_ADDR + description: retention dma link base + bitOffset: 0 + bitWidth: 27 + access: read-write + - register: + name: RETENTION_CFG + description: retention_cfg + addressOffset: 52 + size: 32 + resetValue: 4294967295 + fields: + - name: RET_INV_CFG + description: retention inv scan out + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: INT_ENA + description: Read only register for error and done + addressOffset: 56 + size: 32 + fields: + - name: DONE_INT_ENA + description: backup done flag + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ERROR_INT_ENA + description: error flag + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: Read only register for error and done + addressOffset: 60 + size: 32 + fields: + - name: DONE_INT_RAW + description: backup done flag + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ERROR_INT_RAW + description: error flag + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Read only register for error and done + addressOffset: 64 + size: 32 + fields: + - name: DONE_INT_CLR + description: backup done flag + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ERROR_INT_CLR + description: error flag + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: INT_ST + description: Read only register for error and done + addressOffset: 68 + size: 32 + fields: + - name: DONE_INT_ST + description: backup done flag + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ERROR_INT_ST + description: error flag + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: Date register. + addressOffset: 1020 + size: 32 + resetValue: 35663984 + fields: + - name: DATE + description: REGDMA date information/ REGDMA version information. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: PCNT + description: Pulse Count Controller + groupName: PCNT + baseAddress: 1610686464 + addressBlock: + - offset: 0 + size: 104 + usage: registers + interrupt: + - name: PCNT + value: 50 + registers: + - register: + dim: 4 + dimIncrement: 12 + name: U%s_CONF0 + description: Configuration register 0 for unit %s + addressOffset: 0 + size: 32 + resetValue: 15376 + fields: + - name: FILTER_THRES + description: "This sets the maximum threshold, in APB_CLK cycles, for the filter.\n\nAny pulses with width less than this will be ignored when the filter is enabled." + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: FILTER_EN + description: "This is the enable bit for unit %s's input filter." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: THR_ZERO_EN + description: "This is the enable bit for unit %s's zero comparator." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: THR_H_LIM_EN + description: "This is the enable bit for unit %s's thr_h_lim comparator. Configures it to enable the high limit interrupt." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: THR_L_LIM_EN + description: "This is the enable bit for unit %s's thr_l_lim comparator. Configures it to enable the low limit interrupt." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: THR_THRES0_EN + description: "This is the enable bit for unit %s's thres0 comparator." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: THR_THRES1_EN + description: "This is the enable bit for unit %s's thres1 comparator." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CH0_NEG_MODE + description: "This register sets the behavior when the signal input of channel 0 detects a negative edge.\n\n1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter" + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CH0_POS_MODE + description: "This register sets the behavior when the signal input of channel 0 detects a positive edge.\n\n1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter" + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: CH0_HCTRL_MODE + description: "This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high.\n\n0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification" + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: CH0_LCTRL_MODE + description: "This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low.\n\n0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification" + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CH1_NEG_MODE + description: "This register sets the behavior when the signal input of channel 1 detects a negative edge.\n\n1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter" + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CH1_POS_MODE + description: "This register sets the behavior when the signal input of channel 1 detects a positive edge.\n\n1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter" + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CH1_HCTRL_MODE + description: "This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high.\n\n0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification" + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: CH1_LCTRL_MODE + description: "This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low.\n\n0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification" + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + dim: 4 + dimIncrement: 12 + name: U%s_CONF1 + description: Configuration register 1 for unit %s + addressOffset: 4 + size: 32 + fields: + - name: CNT_THRES0 + description: This register is used to configure the thres0 value for unit %s. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CNT_THRES1 + description: This register is used to configure the thres1 value for unit %s. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + dim: 4 + dimIncrement: 12 + name: U%s_CONF2 + description: Configuration register 2 for unit %s + addressOffset: 8 + size: 32 + fields: + - name: CNT_H_LIM + description: "This register is used to configure the thr_h_lim value for unit %s. When pluse_cnt reaches this value, the counter will be cleared to 0." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CNT_L_LIM + description: "This register is used to configure the thr_l_lim value for unit %s. When pluse_cnt reaches this value, the counter will be cleared to 0." + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: U%s_CNT + description: Counter value for unit %s + addressOffset: 48 + size: 32 + fields: + - name: CNT + description: This register stores the current pulse count value for unit %s. + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: INT_RAW + description: Interrupt raw status register + addressOffset: 64 + size: 32 + fields: + - name: CNT_THR_EVENT_U0 + description: The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U1 + description: The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U2 + description: The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U3 + description: The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Interrupt status register + addressOffset: 68 + size: 32 + fields: + - name: CNT_THR_EVENT_U0 + description: The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U1 + description: The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U2 + description: The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U3 + description: The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable register + addressOffset: 72 + size: 32 + fields: + - name: CNT_THR_EVENT_U0 + description: The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U1 + description: The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U2 + description: The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U3 + description: The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear register + addressOffset: 76 + size: 32 + fields: + - name: CNT_THR_EVENT_U0 + description: Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CNT_THR_EVENT_U1 + description: Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CNT_THR_EVENT_U2 + description: Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CNT_THR_EVENT_U3 + description: Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + dim: 4 + dimIncrement: 4 + name: U%s_STATUS + description: PNCT UNIT%s status register + addressOffset: 80 + size: 32 + fields: + - name: ZERO_MODE + description: "The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive." + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: THRES1 + description: "The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others" + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: THRES0 + description: "The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others" + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L_LIM + description: "The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others" + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: H_LIM + description: "The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ZERO + description: "The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others" + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: CTRL + description: Control register for all counters + addressOffset: 96 + size: 32 + resetValue: 1 + fields: + - name: CNT_RST_U0 + description: "Set this bit to clear unit 0's counter." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U0 + description: "Set this bit to freeze unit 0's counter." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CNT_RST_U1 + description: "Set this bit to clear unit 1's counter." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U1 + description: "Set this bit to freeze unit 1's counter." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CNT_RST_U2 + description: "Set this bit to clear unit 2's counter." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U2 + description: "Set this bit to freeze unit 2's counter." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CNT_RST_U3 + description: "Set this bit to clear unit 3's counter." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U3 + description: "Set this bit to freeze unit 3's counter." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application" + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: PCNT version control register + addressOffset: 252 + size: 32 + resetValue: 403121664 + fields: + - name: DATE + description: This is the PCNT version control register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: PCR + description: PCR Peripheral + groupName: PCR + baseAddress: 1611227136 + addressBlock: + - offset: 0 + size: 356 + usage: registers + registers: + - register: + name: UART0_CONF + description: UART0 configuration register + addressOffset: 0 + size: 32 + resetValue: 5 + fields: + - name: UART0_CLK_EN + description: Set 1 to enable uart0 apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: UART0_RST_EN + description: Set 0 to reset uart0 module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UART0_READY + description: Query this field after reset uart0 module + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: UART0_SCLK_CONF + description: UART0_SCLK configuration register + addressOffset: 4 + size: 32 + resetValue: 7340032 + fields: + - name: UART0_SCLK_DIV_A + description: The denominator of the frequency divider factor of the uart0 function clock. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: UART0_SCLK_DIV_B + description: The numerator of the frequency divider factor of the uart0 function clock. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: UART0_SCLK_DIV_NUM + description: The integral part of the frequency divider factor of the uart0 function clock. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: UART0_SCLK_SEL + description: "set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: UART0_SCLK_EN + description: Set 1 to enable uart0 function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: UART0_PD_CTRL + description: UART0 power control register + addressOffset: 8 + size: 32 + resetValue: 2 + fields: + - name: UART0_MEM_FORCE_PU + description: Set this bit to force power down UART0 memory. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UART0_MEM_FORCE_PD + description: Set this bit to force power up UART0 memory. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: UART1_CONF + description: UART1 configuration register + addressOffset: 12 + size: 32 + resetValue: 5 + fields: + - name: UART1_CLK_EN + description: Set 1 to enable uart1 apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: UART1_RST_EN + description: Set 0 to reset uart1 module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UART1_READY + description: Query this field after reset uart1 module + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: UART1_SCLK_CONF + description: UART1_SCLK configuration register + addressOffset: 16 + size: 32 + resetValue: 7340032 + fields: + - name: UART1_SCLK_DIV_A + description: The denominator of the frequency divider factor of the uart1 function clock. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: UART1_SCLK_DIV_B + description: The numerator of the frequency divider factor of the uart1 function clock. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: UART1_SCLK_DIV_NUM + description: The integral part of the frequency divider factor of the uart1 function clock. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: UART1_SCLK_SEL + description: "set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: UART1_SCLK_EN + description: Set 1 to enable uart0 function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: UART1_PD_CTRL + description: UART1 power control register + addressOffset: 20 + size: 32 + resetValue: 2 + fields: + - name: UART1_MEM_FORCE_PU + description: Set this bit to force power down UART1 memory. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UART1_MEM_FORCE_PD + description: Set this bit to force power up UART1 memory. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: MSPI_CONF + description: MSPI configuration register + addressOffset: 24 + size: 32 + resetValue: 37 + fields: + - name: MSPI_CLK_EN + description: "Set 1 to enable mspi clock, include mspi pll clock" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MSPI_RST_EN + description: Set 0 to reset mspi module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MSPI_PLL_CLK_EN + description: Set 1 to enable mspi pll clock + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MSPI_CLK_SEL + description: set this field to select clock-source. + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: MSPI_READY + description: Query this field after reset mspi module + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: MSPI_CLK_CONF + description: MSPI_CLK configuration register + addressOffset: 28 + size: 32 + fields: + - name: MSPI_FAST_DIV_NUM + description: "Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a low-speed clock-source such as XTAL/FOSC." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: I2C0_CONF + description: I2C configuration register + addressOffset: 32 + size: 32 + resetValue: 5 + fields: + - name: I2C0_CLK_EN + description: Set 1 to enable i2c apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: I2C0_RST_EN + description: Set 0 to reset i2c module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: I2C0_READY + description: Query this field after reset i2c0 module + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: I2C0_SCLK_CONF + description: I2C_SCLK configuration register + addressOffset: 36 + size: 32 + resetValue: 4194304 + fields: + - name: I2C0_SCLK_DIV_A + description: The denominator of the frequency divider factor of the i2c function clock. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: I2C0_SCLK_DIV_B + description: The numerator of the frequency divider factor of the i2c function clock. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: I2C0_SCLK_DIV_NUM + description: The integral part of the frequency divider factor of the i2c function clock. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: I2C0_SCLK_SEL + description: "set this field to select clock-source. 0(default): XTAL, 1: FOSC." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: I2C0_SCLK_EN + description: Set 1 to enable i2c function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: I2C1_CONF + description: I2C configuration register + addressOffset: 40 + size: 32 + resetValue: 5 + fields: + - name: I2C1_CLK_EN + description: Set 1 to enable i2c apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: I2C1_RST_EN + description: Set 0 to reset i2c module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: I2C1_READY + description: Query this field after reset i2c1 module + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: I2C1_SCLK_CONF + description: I2C_SCLK configuration register + addressOffset: 44 + size: 32 + resetValue: 4194304 + fields: + - name: I2C1_SCLK_DIV_A + description: The denominator of the frequency divider factor of the i2c function clock. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: I2C1_SCLK_DIV_B + description: The numerator of the frequency divider factor of the i2c function clock. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: I2C1_SCLK_DIV_NUM + description: The integral part of the frequency divider factor of the i2c function clock. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: I2C1_SCLK_SEL + description: "set this field to select clock-source. 0(default): XTAL, 1: FOSC." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: I2C1_SCLK_EN + description: Set 1 to enable i2c function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: UHCI_CONF + description: UHCI configuration register + addressOffset: 48 + size: 32 + resetValue: 5 + fields: + - name: UHCI_CLK_EN + description: Set 1 to enable uhci clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: UHCI_RST_EN + description: Set 0 to reset uhci module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UHCI_READY + description: Query this field after reset uhci module + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: RMT_CONF + description: RMT configuration register + addressOffset: 52 + size: 32 + resetValue: 5 + fields: + - name: RMT_CLK_EN + description: Set 1 to enable rmt apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RMT_RST_EN + description: Set 0 to reset rmt module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RMT_READY + description: Query this field after reset rmt module + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: RMT_SCLK_CONF + description: RMT_SCLK configuration register + addressOffset: 56 + size: 32 + resetValue: 3149824 + fields: + - name: SCLK_DIV_A + description: The denominator of the frequency divider factor of the rmt function clock. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_B + description: The numerator of the frequency divider factor of the rmt function clock. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_NUM + description: The integral part of the frequency divider factor of the rmt function clock. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: SCLK_SEL + description: "set this field to select clock-source. 0: do not select anyone clock, 1(default): 80MHz, 2: FOSC, 3: XTAL." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SCLK_EN + description: Set 1 to enable rmt function clock + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + name: LEDC_CONF + description: LEDC configuration register + addressOffset: 60 + size: 32 + resetValue: 5 + fields: + - name: LEDC_CLK_EN + description: Set 1 to enable ledc apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LEDC_RST_EN + description: Set 0 to reset ledc module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: LEDC_READY + description: Query this field after reset ledc module + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: LEDC_SCLK_CONF + description: LEDC_SCLK configuration register + addressOffset: 64 + size: 32 + resetValue: 4194304 + fields: + - name: LEDC_SCLK_SEL + description: "set this field to select clock-source. 0(default): do not select anyone clock, 1: 80MHz, 2: FOSC, 3: XTAL." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: LEDC_SCLK_EN + description: Set 1 to enable ledc function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: TIMERGROUP0_CONF + description: TIMERGROUP0 configuration register + addressOffset: 68 + size: 32 + resetValue: 29 + fields: + - name: TG0_CLK_EN + description: Set 1 to enable timer_group0 apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TG0_RST_EN + description: Set 0 to reset timer_group0 module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TG0_WDT_READY + description: Query this field after reset timer_group0 wdt module + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TG0_TIMER0_READY + description: Query this field after reset timer_group0 timer0 module + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TG0_TIMER1_READY + description: reserved + bitOffset: 4 + bitWidth: 1 + access: read-only + - register: + name: TIMERGROUP0_TIMER_CLK_CONF + description: TIMERGROUP0_TIMER_CLK configuration register + addressOffset: 72 + size: 32 + resetValue: 4194304 + fields: + - name: TG0_TIMER_CLK_SEL + description: "set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TG0_TIMER_CLK_EN + description: Set 1 to enable timer_group0 timer clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: TIMERGROUP0_WDT_CLK_CONF + description: TIMERGROUP0_WDT_CLK configuration register + addressOffset: 76 + size: 32 + resetValue: 4194304 + fields: + - name: TG0_WDT_CLK_SEL + description: "set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TG0_WDT_CLK_EN + description: Set 1 to enable timer_group0 wdt clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: TIMERGROUP1_CONF + description: TIMERGROUP1 configuration register + addressOffset: 80 + size: 32 + resetValue: 29 + fields: + - name: TG1_CLK_EN + description: Set 1 to enable timer_group1 apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TG1_RST_EN + description: Set 0 to reset timer_group1 module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TG1_WDT_READY + description: Query this field after reset timer_group1 wdt module + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TG1_TIMER0_READY + description: Query this field after reset timer_group1 timer0 module + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TG1_TIMER1_READY + description: reserved + bitOffset: 4 + bitWidth: 1 + access: read-only + - register: + name: TIMERGROUP1_TIMER_CLK_CONF + description: TIMERGROUP1_TIMER_CLK configuration register + addressOffset: 84 + size: 32 + resetValue: 4194304 + fields: + - name: TG1_TIMER_CLK_SEL + description: "set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TG1_TIMER_CLK_EN + description: Set 1 to enable timer_group1 timer clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: TIMERGROUP1_WDT_CLK_CONF + description: TIMERGROUP1_WDT_CLK configuration register + addressOffset: 88 + size: 32 + resetValue: 4194304 + fields: + - name: TG1_WDT_CLK_SEL + description: "set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TG1_WDT_CLK_EN + description: Set 1 to enable timer_group0 wdt clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: SYSTIMER_CONF + description: SYSTIMER configuration register + addressOffset: 92 + size: 32 + resetValue: 5 + fields: + - name: SYSTIMER_CLK_EN + description: Set 1 to enable systimer apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SYSTIMER_RST_EN + description: Set 0 to reset systimer module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SYSTIMER_READY + description: Query this field after reset systimer module + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: SYSTIMER_FUNC_CLK_CONF + description: SYSTIMER_FUNC_CLK configuration register + addressOffset: 96 + size: 32 + resetValue: 4194304 + fields: + - name: SYSTIMER_FUNC_CLK_SEL + description: "set this field to select clock-source. 0(default): XTAL, 1: FOSC." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SYSTIMER_FUNC_CLK_EN + description: Set 1 to enable systimer function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: TWAI0_CONF + description: TWAI0 configuration register + addressOffset: 100 + size: 32 + resetValue: 5 + fields: + - name: TWAI0_CLK_EN + description: Set 1 to enable twai0 apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TWAI0_RST_EN + description: Set 0 to reset twai0 module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TWAI0_READY + description: Query this field after reset twai0 module + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: TWAI0_FUNC_CLK_CONF + description: TWAI0_FUNC_CLK configuration register + addressOffset: 104 + size: 32 + resetValue: 4194304 + fields: + - name: TWAI0_FUNC_CLK_SEL + description: "set this field to select clock-source. 0(default): XTAL, 1: FOSC." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TWAI0_FUNC_CLK_EN + description: Set 1 to enable twai0 function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: I2S_CONF + description: I2S configuration register + addressOffset: 108 + size: 32 + resetValue: 13 + fields: + - name: I2S_CLK_EN + description: Set 1 to enable i2s apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: I2S_RST_EN + description: Set 0 to reset i2s module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: I2S_RX_READY + description: "Query this field before using i2s rx function, after reset i2s module" + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: I2S_TX_READY + description: "Query this field before using i2s tx function, after reset i2s module" + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: I2S_TX_CLKM_CONF + description: I2S_TX_CLKM configuration register + addressOffset: 112 + size: 32 + resetValue: 4202496 + fields: + - name: I2S_TX_CLKM_DIV_NUM + description: "Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div." + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: I2S_TX_CLKM_SEL + description: "Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: I2S_TX_CLKM_EN + description: Set 1 to enable i2s_tx function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: I2S_TX_CLKM_DIV_CONF + description: I2S_TX_CLKM_DIV configuration register + addressOffset: 116 + size: 32 + resetValue: 512 + fields: + - name: I2S_TX_CLKM_DIV_Z + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: I2S_TX_CLKM_DIV_Y + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))." + bitOffset: 9 + bitWidth: 9 + access: read-write + - name: I2S_TX_CLKM_DIV_X + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1." + bitOffset: 18 + bitWidth: 9 + access: read-write + - name: I2S_TX_CLKM_DIV_YN1 + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1." + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: I2S_RX_CLKM_CONF + description: I2S_RX_CLKM configuration register + addressOffset: 120 + size: 32 + resetValue: 4202496 + fields: + - name: I2S_RX_CLKM_DIV_NUM + description: Integral I2S clock divider value + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: I2S_RX_CLKM_SEL + description: "Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: I2S_RX_CLKM_EN + description: Set 1 to enable i2s_rx function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: I2S_MCLK_SEL + description: "This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx" + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: I2S_RX_CLKM_DIV_CONF + description: I2S_RX_CLKM_DIV configuration register + addressOffset: 124 + size: 32 + resetValue: 512 + fields: + - name: I2S_RX_CLKM_DIV_Z + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: I2S_RX_CLKM_DIV_Y + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))." + bitOffset: 9 + bitWidth: 9 + access: read-write + - name: I2S_RX_CLKM_DIV_X + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1." + bitOffset: 18 + bitWidth: 9 + access: read-write + - name: I2S_RX_CLKM_DIV_YN1 + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1." + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: SARADC_CONF + description: SARADC configuration register + addressOffset: 128 + size: 32 + resetValue: 5 + fields: + - name: SARADC_CLK_EN + description: no use + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SARADC_RST_EN + description: Set 0 to reset function_register of saradc module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SARADC_REG_CLK_EN + description: Set 1 to enable saradc apb clock + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SARADC_REG_RST_EN + description: Set 0 to reset apb_register of saradc module + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: SARADC_CLKM_CONF + description: SARADC_CLKM configuration register + addressOffset: 132 + size: 32 + resetValue: 4210688 + fields: + - name: SARADC_CLKM_DIV_A + description: The denominator of the frequency divider factor of the saradc function clock. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: SARADC_CLKM_DIV_B + description: The numerator of the frequency divider factor of the saradc function clock. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: SARADC_CLKM_DIV_NUM + description: The integral part of the frequency divider factor of the saradc function clock. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: SARADC_CLKM_SEL + description: "set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: reserved." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: SARADC_CLKM_EN + description: Set 1 to enable saradc function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: TSENS_CLK_CONF + description: TSENS_CLK configuration register + addressOffset: 136 + size: 32 + resetValue: 4194304 + fields: + - name: TSENS_CLK_SEL + description: "set this field to select clock-source. 0(default): FOSC, 1: XTAL." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TSENS_CLK_EN + description: Set 1 to enable tsens clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TSENS_RST_EN + description: Set 0 to reset tsens module + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: USB_DEVICE_CONF + description: USB_DEVICE configuration register + addressOffset: 140 + size: 32 + resetValue: 5 + fields: + - name: USB_DEVICE_CLK_EN + description: Set 1 to enable usb_device clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: USB_DEVICE_RST_EN + description: Set 0 to reset usb_device module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: USB_DEVICE_READY + description: Query this field after reset usb_device module + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: INTMTX_CONF + description: INTMTX configuration register + addressOffset: 144 + size: 32 + resetValue: 5 + fields: + - name: INTMTX_CLK_EN + description: Set 1 to enable intmtx clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: INTMTX_RST_EN + description: Set 0 to reset intmtx module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: INTMTX_READY + description: Query this field after reset intmtx module + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: PCNT_CONF + description: PCNT configuration register + addressOffset: 148 + size: 32 + resetValue: 5 + fields: + - name: PCNT_CLK_EN + description: Set 1 to enable pcnt clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PCNT_RST_EN + description: Set 0 to reset pcnt module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PCNT_READY + description: Query this field after reset pcnt module + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: ETM_CONF + description: ETM configuration register + addressOffset: 152 + size: 32 + resetValue: 5 + fields: + - name: ETM_CLK_EN + description: Set 1 to enable etm clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_RST_EN + description: Set 0 to reset etm module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ETM_READY + description: Query this field after reset etm module + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: PWM_CONF + description: PWM configuration register + addressOffset: 156 + size: 32 + resetValue: 5 + fields: + - name: PWM_CLK_EN + description: Set 1 to enable pwm clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PWM_RST_EN + description: Set 0 to reset pwm module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PWM_READY + description: Query this field after reset pwm module + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: PWM_CLK_CONF + description: PWM_CLK configuration register + addressOffset: 160 + size: 32 + resetValue: 4210688 + fields: + - name: PWM_DIV_NUM + description: The integral part of the frequency divider factor of the pwm function clock. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: PWM_CLKM_SEL + description: "set this field to select clock-source. 0(default): do not select anyone clock, 1: 160MHz, 2: XTAL, 3: FOSC." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: PWM_CLKM_EN + description: set this field as 1 to activate pwm clkm. + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: PARL_IO_CONF + description: PARL_IO configuration register + addressOffset: 164 + size: 32 + resetValue: 5 + fields: + - name: PARL_CLK_EN + description: Set 1 to enable parl apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PARL_RST_EN + description: Set 0 to reset parl apb reg + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PARL_READY + description: Query this field after reset parl module + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: PARL_CLK_RX_CONF + description: PARL_CLK_RX configuration register + addressOffset: 168 + size: 32 + resetValue: 262144 + fields: + - name: PARL_CLK_RX_DIV_NUM + description: The integral part of the frequency divider factor of the parl rx clock. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: PARL_CLK_RX_SEL + description: "set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: user clock from pad." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: PARL_CLK_RX_EN + description: Set 1 to enable parl rx clock + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: PARL_RX_RST_EN + description: Set 0 to reset parl rx module + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: PARL_CLK_TX_CONF + description: PARL_CLK_TX configuration register + addressOffset: 172 + size: 32 + resetValue: 262144 + fields: + - name: PARL_CLK_TX_DIV_NUM + description: The integral part of the frequency divider factor of the parl tx clock. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: PARL_CLK_TX_SEL + description: "set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: user clock from pad." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: PARL_CLK_TX_EN + description: Set 1 to enable parl tx clock + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: PARL_TX_RST_EN + description: Set 0 to reset parl tx module + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: PVT_MONITOR_CONF + description: PVT_MONITOR configuration register + addressOffset: 176 + size: 32 + resetValue: 29 + fields: + - name: PVT_MONITOR_CLK_EN + description: Set 1 to enable apb clock of pvt module + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PVT_MONITOR_RST_EN + description: Set 0 to reset all pvt monitor module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PVT_MONITOR_SITE1_CLK_EN + description: Set 1 to enable function clock of modem pvt module + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PVT_MONITOR_SITE2_CLK_EN + description: Set 1 to enable function clock of cpu pvt module + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PVT_MONITOR_SITE3_CLK_EN + description: Set 1 to enable function clock of hp_peri pvt module + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: PVT_MONITOR_FUNC_CLK_CONF + description: PVT_MONITOR function clock configuration register + addressOffset: 180 + size: 32 + resetValue: 4194304 + fields: + - name: PVT_MONITOR_FUNC_CLK_DIV_NUM + description: The integral part of the frequency divider factor of the pvt_monitor function clock. + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: PVT_MONITOR_FUNC_CLK_SEL + description: "set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL divided by 3." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: PVT_MONITOR_FUNC_CLK_EN + description: Set 1 to enable source clock of pvt sitex + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: GDMA_CONF + description: GDMA configuration register + addressOffset: 184 + size: 32 + resetValue: 1 + fields: + - name: GDMA_CLK_EN + description: Set 1 to enable gdma clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: GDMA_RST_EN + description: Set 0 to reset gdma module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: SPI2_CONF + description: SPI2 configuration register + addressOffset: 188 + size: 32 + resetValue: 5 + fields: + - name: SPI2_CLK_EN + description: Set 1 to enable spi2 apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI2_RST_EN + description: Set 0 to reset spi2 module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI2_READY + description: Query this field after reset spi2 module + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: SPI2_CLKM_CONF + description: SPI2_CLKM configuration register + addressOffset: 192 + size: 32 + resetValue: 4194304 + fields: + - name: SPI2_CLKM_SEL + description: "set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: reserved." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: SPI2_CLKM_EN + description: Set 1 to enable spi2 function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: AES_CONF + description: AES configuration register + addressOffset: 196 + size: 32 + resetValue: 5 + fields: + - name: AES_CLK_EN + description: Set 1 to enable aes clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: AES_RST_EN + description: Set 0 to reset aes module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AES_READY + description: Query this field after reset aes module + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: SHA_CONF + description: SHA configuration register + addressOffset: 200 + size: 32 + resetValue: 5 + fields: + - name: SHA_CLK_EN + description: Set 1 to enable sha clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SHA_RST_EN + description: Set 0 to reset sha module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SHA_READY + description: Query this field after reset sha module + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: RSA_CONF + description: RSA configuration register + addressOffset: 204 + size: 32 + resetValue: 5 + fields: + - name: RSA_CLK_EN + description: Set 1 to enable rsa clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RSA_RST_EN + description: Set 0 to reset rsa module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RSA_READY + description: Query this field after reset rsa module + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: RSA_PD_CTRL + description: RSA power control register + addressOffset: 208 + size: 32 + resetValue: 2 + fields: + - name: RSA_MEM_PD + description: Set this bit to power down rsa internal memory. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RSA_MEM_FORCE_PU + description: Set this bit to force power up rsa internal memory + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RSA_MEM_FORCE_PD + description: Set this bit to force power down rsa internal memory. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: ECC_CONF + description: ECC configuration register + addressOffset: 212 + size: 32 + resetValue: 5 + fields: + - name: ECC_CLK_EN + description: Set 1 to enable ecc clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ECC_RST_EN + description: Set 0 to reset ecc module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ECC_READY + description: Query this field after reset ecc module + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: ECC_PD_CTRL + description: ECC power control register + addressOffset: 216 + size: 32 + resetValue: 2 + fields: + - name: ECC_MEM_PD + description: Set this bit to power down ecc internal memory. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ECC_MEM_FORCE_PU + description: Set this bit to force power up ecc internal memory + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ECC_MEM_FORCE_PD + description: Set this bit to force power down ecc internal memory. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: DS_CONF + description: DS configuration register + addressOffset: 220 + size: 32 + resetValue: 5 + fields: + - name: DS_CLK_EN + description: Set 1 to enable ds clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DS_RST_EN + description: Set 0 to reset ds module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DS_READY + description: Query this field after reset ds module + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: HMAC_CONF + description: HMAC configuration register + addressOffset: 224 + size: 32 + resetValue: 5 + fields: + - name: HMAC_CLK_EN + description: Set 1 to enable hmac clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: HMAC_RST_EN + description: Set 0 to reset hmac module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: HMAC_READY + description: Query this field after reset hmac module + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: ECDSA_CONF + description: ECDSA configuration register + addressOffset: 228 + size: 32 + resetValue: 5 + fields: + - name: ECDSA_CLK_EN + description: Set 1 to enable ecdsa clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ECDSA_RST_EN + description: Set 0 to reset ecdsa module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ECDSA_READY + description: Query this field after reset ecdsa module + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: IOMUX_CONF + description: IOMUX configuration register + addressOffset: 232 + size: 32 + resetValue: 1 + fields: + - name: IOMUX_CLK_EN + description: Set 1 to enable iomux apb clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IOMUX_RST_EN + description: Set 0 to reset iomux module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: IOMUX_CLK_CONF + description: IOMUX_CLK configuration register + addressOffset: 236 + size: 32 + resetValue: 4194304 + fields: + - name: IOMUX_FUNC_CLK_SEL + description: "set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: FOSC, 3(default): XTAL." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: IOMUX_FUNC_CLK_EN + description: Set 1 to enable iomux function clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: MEM_MONITOR_CONF + description: MEM_MONITOR configuration register + addressOffset: 240 + size: 32 + resetValue: 5 + fields: + - name: MEM_MONITOR_CLK_EN + description: Set 1 to enable mem_monitor clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_MONITOR_RST_EN + description: Set 0 to reset mem_monitor module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MEM_MONITOR_READY + description: Query this field after reset mem_monitor module + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: REGDMA_CONF + description: REGDMA configuration register + addressOffset: 244 + size: 32 + fields: + - name: REGDMA_CLK_EN + description: Set 1 to enable regdma clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGDMA_RST_EN + description: Set 0 to reset regdma module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: TRACE_CONF + description: TRACE configuration register + addressOffset: 248 + size: 32 + resetValue: 1 + fields: + - name: TRACE_CLK_EN + description: Set 1 to enable trace clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TRACE_RST_EN + description: Set 0 to reset trace module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: ASSIST_CONF + description: ASSIST configuration register + addressOffset: 252 + size: 32 + resetValue: 1 + fields: + - name: ASSIST_CLK_EN + description: Set 1 to enable assist clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ASSIST_RST_EN + description: Set 0 to reset assist module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CACHE_CONF + description: CACHE configuration register + addressOffset: 256 + size: 32 + resetValue: 1 + fields: + - name: CACHE_CLK_EN + description: Set 1 to enable cache clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CACHE_RST_EN + description: Set 0 to reset cache module + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: MODEM_CONF + description: MODEM_APB configuration register + addressOffset: 260 + size: 32 + resetValue: 2 + fields: + - name: MODEM_CLK_SEL + description: xxxx + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MODEM_CLK_EN + description: xxxx + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MODEM_RST_EN + description: Set this file as 1 to reset modem-subsystem. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: TIMEOUT_CONF + description: TIMEOUT configuration register + addressOffset: 264 + size: 32 + fields: + - name: CPU_TIMEOUT_RST_EN + description: Set 0 to reset cpu_peri timeout module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: HP_TIMEOUT_RST_EN + description: Set 0 to reset hp_peri timeout module and hp_modem timeout module + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: SYSCLK_CONF + description: SYSCLK configuration register + addressOffset: 268 + size: 32 + resetValue: 536871424 + fields: + - name: LS_DIV_NUM + description: clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed clock-source such as XTAL/FOSC. + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: HS_DIV_NUM + description: clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: SOC_CLK_SEL + description: "This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CLK_XTAL_FREQ + description: This field indicates the frequency(MHz) of XTAL. + bitOffset: 24 + bitWidth: 7 + access: read-only + - register: + name: CPU_WAITI_CONF + description: CPU_WAITI configuration register + addressOffset: 272 + size: 32 + resetValue: 13 + fields: + - name: CPUPERIOD_SEL + description: Reserved. This filed has been replaced by PCR_CPU_DIV_NUM + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: PLL_FREQ_SEL + description: Reserved. This filed has been replaced by PCR_CPU_DIV_NUM + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CPU_WAIT_MODE_FORCE_ON + description: Set 1 to force cpu_waiti_clk enable. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CPU_WAITI_DELAY_NUM + description: "This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close" + bitOffset: 4 + bitWidth: 4 + access: read-write + - register: + name: CPU_FREQ_CONF + description: CPU_FREQ configuration register + addressOffset: 276 + size: 32 + fields: + - name: CPU_DIV_NUM + description: "Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: AHB_FREQ_CONF + description: AHB_FREQ configuration register + addressOffset: 280 + size: 32 + fields: + - name: AHB_DIV_NUM + description: "Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for low-speed clock-source such as XTAL/FOSC, and should be used together with PCR_CPU_DIV_NUM." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: APB_FREQ_CONF + description: APB_FREQ configuration register + addressOffset: 284 + size: 32 + fields: + - name: APB_DECREASE_DIV_NUM + description: "If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be automatically down to clk_apb_decrease only when no access is on apb-bus, and will recover to the previous frequency when a new access appears on apb-bus. Set as one within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note that enable this function will reduce performance. Users can set this field as zero to disable the auto-decrease-apb-freq function. By default, this function is disable." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: APB_DIV_NUM + description: "Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is div1(default)/div2/div4 of clk_ahb." + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: SYSCLK_FREQ_QUERY_0 + description: SYSCLK frequency query 0 register + addressOffset: 288 + size: 32 + resetValue: 24584 + fields: + - name: FOSC_FREQ + description: This field indicates the frequency(MHz) of FOSC. + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: PLL_FREQ + description: This field indicates the frequency(MHz) of SPLL. + bitOffset: 8 + bitWidth: 10 + access: read-only + - register: + name: PLL_DIV_CLK_EN + description: SPLL DIV clock-gating configuration register + addressOffset: 292 + size: 32 + resetValue: 63 + fields: + - name: PLL_240M_CLK_EN + description: "This field is used to open 96 MHz clock (SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PLL_160M_CLK_EN + description: "This field is used to open 64 MHz clock (div3 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PLL_120M_CLK_EN + description: "This field is used to open 48 MHz clock (div4 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PLL_80M_CLK_EN + description: "This field is used to open 32 MHz clock (div6 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PLL_48M_CLK_EN + description: "This field is used to open 16 MHz clock (div10 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: PLL_40M_CLK_EN + description: "This field is used to open 8 MHz clock (div12 of SPLL) drived from SPLL. 0: close, 1: open(default). Only avaliable when high-speed clock-source SPLL is active." + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: CTRL_CLK_OUT_EN + description: CLK_OUT_EN configuration register + addressOffset: 296 + size: 32 + resetValue: 127 + fields: + - name: CLK8_OEN + description: Set 1 to enable 8m clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CLK16_OEN + description: Set 1 to enable 16m clock + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CLK32_OEN + description: Set 1 to enable 32m clock + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CLK_ADC_INF_OEN + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CLK_DFM_INF_OEN + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CLK_SDM_MOD_OEN + description: Reserved + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CLK_XTAL_OEN + description: Set 1 to enable xtal clock + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: CTRL_TICK_CONF + description: TICK configuration register + addressOffset: 300 + size: 32 + resetValue: 67367 + fields: + - name: XTAL_TICK_NUM + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: FOSC_TICK_NUM + description: "******* Description ***********" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: TICK_ENABLE + description: "******* Description ***********" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RST_TICK_CNT + description: "******* Description ***********" + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: CTRL_32K_CONF + description: 32KHz clock configuration register + addressOffset: 304 + size: 32 + fields: + - name: CLK_32K_SEL + description: "This field indicates which one 32KHz clock will be used by timergroup. 0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: _32K_MODEM_SEL + description: "This field indicates which one 32KHz clock will be used by MODEM_SYSTEM. 0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0." + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: SRAM_POWER_CONF_0 + description: HP SRAM/ROM configuration register + addressOffset: 308 + size: 32 + resetValue: 24576 + fields: + - name: ROM_FORCE_PU + description: Set this bit to force power up ROM + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: ROM_FORCE_PD + description: Set this bit to force power down ROM. + bitOffset: 15 + bitWidth: 2 + access: read-write + - name: ROM_CLKGATE_FORCE_ON + description: "1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A gate-clock will be used when accessing the ROM." + bitOffset: 17 + bitWidth: 2 + access: read-write + - register: + name: SRAM_POWER_CONF_1 + description: HP SRAM/ROM configuration register + addressOffset: 312 + size: 32 + resetValue: 31 + fields: + - name: SRAM_FORCE_PU + description: Set this bit to force power up SRAM + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: SRAM_FORCE_PD + description: Set this bit to force power down SRAM. + bitOffset: 10 + bitWidth: 5 + access: read-write + - name: SRAM_CLKGATE_FORCE_ON + description: "1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A gate-clock will be used when accessing the SRAM." + bitOffset: 25 + bitWidth: 5 + access: read-write + - register: + name: SEC_CONF + description: xxxx + addressOffset: 316 + size: 32 + fields: + - name: SEC_CLK_SEL + description: xxxx + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: ADC_INV_PHASE_CONF + description: xxxx + addressOffset: 320 + size: 32 + fields: + - name: CLK_ADC_INV_PHASE_ENA + description: xxxx + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SDM_INV_PHASE_CONF + description: xxxx + addressOffset: 324 + size: 32 + fields: + - name: CLK_SDM_INV_PHASE_ENA + description: xxxx + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CLK_SDM_INV_PHASE_SEL + description: xxxx + bitOffset: 1 + bitWidth: 3 + access: read-write + - register: + name: BUS_CLK_UPDATE + description: xxxx + addressOffset: 328 + size: 32 + fields: + - name: BUS_CLOCK_UPDATE + description: xxxx + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SAR_CLK_DIV + description: xxxx + addressOffset: 332 + size: 32 + resetValue: 1028 + fields: + - name: SAR2_CLK_DIV_NUM + description: xxxx + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SAR1_CLK_DIV_NUM + description: xxxx + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: PWDET_SAR_CLK_CONF + description: xxxx + addressOffset: 336 + size: 32 + resetValue: 263 + fields: + - name: PWDET_SAR_CLK_DIV_NUM + description: xxxx + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: PWDET_SAR_READER_EN + description: xxxx + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: RESET_EVENT_BYPASS + description: reset event bypass backdoor configuration register + addressOffset: 4080 + size: 32 + resetValue: 2 + fields: + - name: APM + description: "This field is used to control reset event relationship for tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg will not only be reset by power-reset, but also some reset event." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RESET_EVENT_BYPASS + description: "This field is used to control reset event relationship for system-bus. 1: system bus (including arbiter/router) will only be reset by power-reset. some reset event will be bypass. 0: system bus (including arbiter/router) will not only be reset by power-reset, but also some reset event." + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: FPGA_DEBUG + description: fpga debug register + addressOffset: 4084 + size: 32 + resetValue: 4294967295 + fields: + - name: FPGA_DEBUG + description: Only used in fpga debug. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CLOCK_GATE + description: PCR clock gating configure register + addressOffset: 4088 + size: 32 + fields: + - name: CLK_EN + description: Set this bit as 1 to force on clock gating. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Date register. + addressOffset: 4092 + size: 32 + resetValue: 35717248 + fields: + - name: DATE + description: PCR version information. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: PMU + description: PMU Peripheral + groupName: PMU + baseAddress: 1611333632 + addressBlock: + - offset: 0 + size: 428 + usage: registers + interrupt: + - name: PMU + value: 0 + registers: + - register: + name: HP_ACTIVE_DIG_POWER + description: need_des + addressOffset: 0 + size: 32 + fields: + - name: HP_ACTIVE_VDD_SPI_PD_EN + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_HP_MEM_DSLP + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_PD_HP_MEM_PD_EN + description: need_des + bitOffset: 23 + bitWidth: 4 + access: read-write + - name: HP_ACTIVE_PD_HP_WIFI_PD_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_PD_HP_CPU_PD_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_PD_HP_AON_PD_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_PD_TOP_PD_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_ACTIVE_ICG_HP_FUNC + description: need_des + addressOffset: 4 + size: 32 + resetValue: 4294967295 + fields: + - name: HP_ACTIVE_DIG_ICG_FUNC_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_ACTIVE_ICG_HP_APB + description: need_des + addressOffset: 8 + size: 32 + resetValue: 4294967295 + fields: + - name: HP_ACTIVE_DIG_ICG_APB_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_ACTIVE_ICG_MODEM + description: need_des + addressOffset: 12 + size: 32 + fields: + - name: HP_ACTIVE_DIG_ICG_MODEM_CODE + description: need_des + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: HP_ACTIVE_HP_SYS_CNTL + description: need_des + addressOffset: 16 + size: 32 + fields: + - name: HP_ACTIVE_UART_WAKEUP_EN + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_LP_PAD_HOLD_ALL + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_HP_PAD_HOLD_ALL + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_DIG_PAD_SLP_SEL + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_DIG_PAUSE_WDT + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_DIG_CPU_STALL + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: HP_ACTIVE_HP_CK_POWER + description: need_des + addressOffset: 20 + size: 32 + fields: + - name: HP_ACTIVE_I2C_ISO_EN + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_I2C_RETENTION + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_XPD_BB_I2C + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_XPD_BBPLL_I2C + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_XPD_BBPLL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: HP_ACTIVE_BIAS + description: need_des + addressOffset: 24 + size: 32 + resetValue: 16777216 + fields: + - name: HP_ACTIVE_XPD_TRX + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_XPD_BIAS + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_PD_CUR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SLEEP + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_ACTIVE_BACKUP + description: need_des + addressOffset: 28 + size: 32 + fields: + - name: HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE + description: need_des + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE + description: need_des + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: HP_ACTIVE_RETENTION_MODE + description: need_des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: HP_SLEEP2ACTIVE_RETENTION_EN + description: need_des + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: HP_MODEM2ACTIVE_RETENTION_EN + description: need_des + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: HP_SLEEP2ACTIVE_BACKUP_CLK_SEL + description: need_des + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: HP_MODEM2ACTIVE_BACKUP_CLK_SEL + description: need_des + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: HP_SLEEP2ACTIVE_BACKUP_MODE + description: need_des + bitOffset: 20 + bitWidth: 3 + access: read-write + - name: HP_MODEM2ACTIVE_BACKUP_MODE + description: need_des + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: HP_SLEEP2ACTIVE_BACKUP_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_MODEM2ACTIVE_BACKUP_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: HP_ACTIVE_BACKUP_CLK + description: need_des + addressOffset: 32 + size: 32 + fields: + - name: HP_ACTIVE_BACKUP_ICG_FUNC_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_ACTIVE_SYSCLK + description: need_des + addressOffset: 36 + size: 32 + fields: + - name: HP_ACTIVE_DIG_SYS_CLK_NO_DIV + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_ICG_SYS_CLOCK_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_SYS_CLK_SLP_SEL + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_ICG_SLP_SEL + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_DIG_SYS_CLK_SEL + description: need_des + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: HP_ACTIVE_HP_REGULATOR0 + description: need_des + addressOffset: 40 + size: 32 + resetValue: 2219270416 + fields: + - name: HP_ACTIVE_HP_POWER_DET_BYPASS + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LP_DBIAS_VOL + description: need_des + bitOffset: 4 + bitWidth: 5 + access: read-only + - name: HP_DBIAS_VOL + description: need_des + bitOffset: 9 + bitWidth: 5 + access: read-only + - name: DIG_REGULATOR0_DBIAS_SEL + description: need_des + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DIG_DBIAS_INIT + description: need_des + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD + description: need_des + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD + description: need_des + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_HP_REGULATOR_XPD + description: need_des + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS + description: need_des + bitOffset: 19 + bitWidth: 4 + access: read-write + - name: HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS + description: need_des + bitOffset: 23 + bitWidth: 4 + access: read-write + - name: HP_ACTIVE_HP_REGULATOR_DBIAS + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: HP_ACTIVE_HP_REGULATOR1 + description: need_des + addressOffset: 44 + size: 32 + fields: + - name: HP_ACTIVE_HP_REGULATOR_DRV_B + description: need_des + bitOffset: 8 + bitWidth: 24 + access: read-write + - register: + name: HP_ACTIVE_XTAL + description: need_des + addressOffset: 48 + size: 32 + resetValue: 2147483648 + fields: + - name: HP_ACTIVE_XPD_XTAL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_MODEM_DIG_POWER + description: need_des + addressOffset: 52 + size: 32 + fields: + - name: HP_MODEM_VDD_SPI_PD_EN + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: HP_MODEM_HP_MEM_DSLP + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: HP_MODEM_PD_HP_MEM_PD_EN + description: need_des + bitOffset: 23 + bitWidth: 4 + access: read-write + - name: HP_MODEM_PD_HP_WIFI_PD_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_MODEM_PD_HP_CPU_PD_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_MODEM_PD_HP_AON_PD_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HP_MODEM_PD_TOP_PD_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_MODEM_ICG_HP_FUNC + description: need_des + addressOffset: 56 + size: 32 + resetValue: 4294967295 + fields: + - name: HP_MODEM_DIG_ICG_FUNC_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_MODEM_ICG_HP_APB + description: need_des + addressOffset: 60 + size: 32 + resetValue: 4294967295 + fields: + - name: HP_MODEM_DIG_ICG_APB_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_MODEM_ICG_MODEM + description: need_des + addressOffset: 64 + size: 32 + fields: + - name: HP_MODEM_DIG_ICG_MODEM_CODE + description: need_des + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: HP_MODEM_HP_SYS_CNTL + description: need_des + addressOffset: 68 + size: 32 + fields: + - name: HP_MODEM_UART_WAKEUP_EN + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: HP_MODEM_LP_PAD_HOLD_ALL + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: HP_MODEM_HP_PAD_HOLD_ALL + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HP_MODEM_DIG_PAD_SLP_SEL + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_MODEM_DIG_PAUSE_WDT + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_MODEM_DIG_CPU_STALL + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: HP_MODEM_HP_CK_POWER + description: need_des + addressOffset: 72 + size: 32 + fields: + - name: HP_MODEM_I2C_ISO_EN + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HP_MODEM_I2C_RETENTION + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_MODEM_XPD_BB_I2C + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_MODEM_XPD_BBPLL_I2C + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_MODEM_XPD_BBPLL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: HP_MODEM_BIAS + description: need_des + addressOffset: 76 + size: 32 + resetValue: 16777216 + fields: + - name: HP_MODEM_XPD_TRX + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: HP_MODEM_XPD_BIAS + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: HP_MODEM_PD_CUR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SLEEP + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_MODEM_BACKUP + description: need_des + addressOffset: 80 + size: 32 + fields: + - name: HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE + description: need_des + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: HP_MODEM_RETENTION_MODE + description: need_des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: HP_SLEEP2MODEM_RETENTION_EN + description: need_des + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: HP_SLEEP2MODEM_BACKUP_CLK_SEL + description: need_des + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: HP_SLEEP2MODEM_BACKUP_MODE + description: need_des + bitOffset: 20 + bitWidth: 3 + access: read-write + - name: HP_SLEEP2MODEM_BACKUP_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: HP_MODEM_BACKUP_CLK + description: need_des + addressOffset: 84 + size: 32 + fields: + - name: HP_MODEM_BACKUP_ICG_FUNC_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_MODEM_SYSCLK + description: need_des + addressOffset: 88 + size: 32 + fields: + - name: HP_MODEM_DIG_SYS_CLK_NO_DIV + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HP_MODEM_ICG_SYS_CLOCK_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_MODEM_SYS_CLK_SLP_SEL + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_MODEM_ICG_SLP_SEL + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_MODEM_DIG_SYS_CLK_SEL + description: need_des + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: HP_MODEM_HP_REGULATOR0 + description: need_des + addressOffset: 92 + size: 32 + resetValue: 2219245568 + fields: + - name: HP_MODEM_HP_POWER_DET_BYPASS + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: HP_MODEM_HP_REGULATOR_SLP_MEM_XPD + description: need_des + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD + description: need_des + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: HP_MODEM_HP_REGULATOR_XPD + description: need_des + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS + description: need_des + bitOffset: 19 + bitWidth: 4 + access: read-write + - name: HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS + description: need_des + bitOffset: 23 + bitWidth: 4 + access: read-write + - name: HP_MODEM_HP_REGULATOR_DBIAS + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: HP_MODEM_HP_REGULATOR1 + description: need_des + addressOffset: 96 + size: 32 + fields: + - name: HP_MODEM_HP_REGULATOR_DRV_B + description: need_des + bitOffset: 8 + bitWidth: 24 + access: read-write + - register: + name: HP_MODEM_XTAL + description: need_des + addressOffset: 100 + size: 32 + resetValue: 2147483648 + fields: + - name: HP_MODEM_XPD_XTAL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_SLEEP_DIG_POWER + description: need_des + addressOffset: 104 + size: 32 + fields: + - name: HP_SLEEP_VDD_SPI_PD_EN + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_HP_MEM_DSLP + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_PD_HP_MEM_PD_EN + description: need_des + bitOffset: 23 + bitWidth: 4 + access: read-write + - name: HP_SLEEP_PD_HP_WIFI_PD_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_PD_HP_CPU_PD_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_PD_HP_AON_PD_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_PD_TOP_PD_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_SLEEP_ICG_HP_FUNC + description: need_des + addressOffset: 108 + size: 32 + resetValue: 4294967295 + fields: + - name: HP_SLEEP_DIG_ICG_FUNC_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_SLEEP_ICG_HP_APB + description: need_des + addressOffset: 112 + size: 32 + resetValue: 4294967295 + fields: + - name: HP_SLEEP_DIG_ICG_APB_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_SLEEP_ICG_MODEM + description: need_des + addressOffset: 116 + size: 32 + fields: + - name: HP_SLEEP_DIG_ICG_MODEM_CODE + description: need_des + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: HP_SLEEP_HP_SYS_CNTL + description: need_des + addressOffset: 120 + size: 32 + fields: + - name: HP_SLEEP_UART_WAKEUP_EN + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_LP_PAD_HOLD_ALL + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_HP_PAD_HOLD_ALL + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_DIG_PAD_SLP_SEL + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_DIG_PAUSE_WDT + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_DIG_CPU_STALL + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: HP_SLEEP_HP_CK_POWER + description: need_des + addressOffset: 124 + size: 32 + fields: + - name: HP_SLEEP_I2C_ISO_EN + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_I2C_RETENTION + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_XPD_BB_I2C + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_XPD_BBPLL_I2C + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_XPD_BBPLL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: HP_SLEEP_BIAS + description: need_des + addressOffset: 128 + size: 32 + resetValue: 16777216 + fields: + - name: HP_SLEEP_XPD_TRX + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_XPD_BIAS + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_PD_CUR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SLEEP + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_SLEEP_BACKUP + description: need_des + addressOffset: 132 + size: 32 + fields: + - name: HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE + description: need_des + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE + description: need_des + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: HP_SLEEP_RETENTION_MODE + description: need_des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: HP_MODEM2SLEEP_RETENTION_EN + description: need_des + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE2SLEEP_RETENTION_EN + description: need_des + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: HP_MODEM2SLEEP_BACKUP_CLK_SEL + description: need_des + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: HP_ACTIVE2SLEEP_BACKUP_CLK_SEL + description: need_des + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: HP_MODEM2SLEEP_BACKUP_MODE + description: need_des + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: HP_ACTIVE2SLEEP_BACKUP_MODE + description: need_des + bitOffset: 26 + bitWidth: 3 + access: read-write + - name: HP_MODEM2SLEEP_BACKUP_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE2SLEEP_BACKUP_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_SLEEP_BACKUP_CLK + description: need_des + addressOffset: 136 + size: 32 + fields: + - name: HP_SLEEP_BACKUP_ICG_FUNC_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_SLEEP_SYSCLK + description: need_des + addressOffset: 140 + size: 32 + fields: + - name: HP_SLEEP_DIG_SYS_CLK_NO_DIV + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_ICG_SYS_CLOCK_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_SYS_CLK_SLP_SEL + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_ICG_SLP_SEL + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_DIG_SYS_CLK_SEL + description: need_des + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: HP_SLEEP_HP_REGULATOR0 + description: need_des + addressOffset: 144 + size: 32 + resetValue: 2219245568 + fields: + - name: HP_SLEEP_HP_POWER_DET_BYPASS + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD + description: need_des + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD + description: need_des + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_HP_REGULATOR_XPD + description: need_des + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS + description: need_des + bitOffset: 19 + bitWidth: 4 + access: read-write + - name: HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS + description: need_des + bitOffset: 23 + bitWidth: 4 + access: read-write + - name: HP_SLEEP_HP_REGULATOR_DBIAS + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: HP_SLEEP_HP_REGULATOR1 + description: need_des + addressOffset: 148 + size: 32 + fields: + - name: HP_SLEEP_HP_REGULATOR_DRV_B + description: need_des + bitOffset: 8 + bitWidth: 24 + access: read-write + - register: + name: HP_SLEEP_XTAL + description: need_des + addressOffset: 152 + size: 32 + resetValue: 2147483648 + fields: + - name: HP_SLEEP_XPD_XTAL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_SLEEP_LP_REGULATOR0 + description: need_des + addressOffset: 156 + size: 32 + resetValue: 2355101696 + fields: + - name: HP_SLEEP_LP_REGULATOR_SLP_XPD + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_LP_REGULATOR_XPD + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_LP_REGULATOR_SLP_DBIAS + description: need_des + bitOffset: 23 + bitWidth: 4 + access: read-write + - name: HP_SLEEP_LP_REGULATOR_DBIAS + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: HP_SLEEP_LP_REGULATOR1 + description: need_des + addressOffset: 160 + size: 32 + fields: + - name: HP_SLEEP_LP_REGULATOR_DRV_B + description: need_des + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: HP_SLEEP_LP_DCDC_RESERVE + description: need_des + addressOffset: 164 + size: 32 + fields: + - name: HP_SLEEP_LP_DCDC_RESERVE + description: need_des + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: HP_SLEEP_LP_DIG_POWER + description: need_des + addressOffset: 168 + size: 32 + fields: + - name: HP_SLEEP_BOD_SOURCE_SEL + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_VDDBAT_MODE + description: need_des + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: HP_SLEEP_LP_MEM_DSLP + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_PD_LP_PERI_PD_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_SLEEP_LP_CK_POWER + description: need_des + addressOffset: 172 + size: 32 + resetValue: 1073741824 + fields: + - name: HP_SLEEP_XPD_LPPLL + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_XPD_XTAL32K + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_XPD_RC32K + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_XPD_FOSC_CLK + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_PD_OSC_CLK + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_SLEEP_LP_BIAS_RESERVE + description: need_des + addressOffset: 176 + size: 32 + fields: + - name: LP_SLEEP_LP_BIAS_RESERVE + description: need_des + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: LP_SLEEP_LP_REGULATOR0 + description: need_des + addressOffset: 180 + size: 32 + resetValue: 2355101696 + fields: + - name: LP_SLEEP_LP_REGULATOR_SLP_XPD + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_LP_REGULATOR_XPD + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_LP_REGULATOR_SLP_DBIAS + description: need_des + bitOffset: 23 + bitWidth: 4 + access: read-write + - name: LP_SLEEP_LP_REGULATOR_DBIAS + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: LP_SLEEP_LP_REGULATOR1 + description: need_des + addressOffset: 184 + size: 32 + fields: + - name: LP_SLEEP_LP_REGULATOR_DRV_B + description: need_des + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: LP_SLEEP_XTAL + description: need_des + addressOffset: 188 + size: 32 + resetValue: 2147483648 + fields: + - name: LP_SLEEP_XPD_XTAL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_SLEEP_LP_DIG_POWER + description: need_des + addressOffset: 192 + size: 32 + fields: + - name: LP_SLEEP_BOD_SOURCE_SEL + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_VDDBAT_MODE + description: need_des + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: LP_SLEEP_LP_MEM_DSLP + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_PD_LP_PERI_PD_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_SLEEP_LP_CK_POWER + description: need_des + addressOffset: 196 + size: 32 + resetValue: 1073741824 + fields: + - name: LP_SLEEP_XPD_LPPLL + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_XPD_XTAL32K + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_XPD_RC32K + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_XPD_FOSC_CLK + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_PD_OSC_CLK + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_SLEEP_BIAS + description: need_des + addressOffset: 200 + size: 32 + fields: + - name: LP_SLEEP_XPD_BIAS + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_PD_CUR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SLEEP + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: IMM_HP_CK_POWER + description: need_des + addressOffset: 204 + size: 32 + access: read-write + fields: + - name: TIE_LOW_GLOBAL_BBPLL_ICG + description: need_des + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TIE_LOW_GLOBAL_XTAL_ICG + description: need_des + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TIE_LOW_I2C_RETENTION + description: need_des + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TIE_LOW_XPD_BB_I2C + description: need_des + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TIE_LOW_XPD_BBPLL_I2C + description: need_des + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: TIE_LOW_XPD_BBPLL + description: need_des + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TIE_LOW_XPD_XTAL + description: need_des + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_GLOBAL_BBPLL_ICG + description: need_des + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_GLOBAL_XTAL_ICG + description: need_des + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_I2C_RETENTION + description: need_des + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_XPD_BB_I2C + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_XPD_BBPLL_I2C + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_XPD_BBPLL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_XPD_XTAL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: IMM_SLEEP_SYSCLK + description: need_des + addressOffset: 208 + size: 32 + fields: + - name: UPDATE_DIG_ICG_SWITCH + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: TIE_LOW_ICG_SLP_SEL + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_ICG_SLP_SEL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: UPDATE_DIG_SYS_CLK_SEL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: IMM_HP_FUNC_ICG + description: need_des + addressOffset: 212 + size: 32 + fields: + - name: UPDATE_DIG_ICG_FUNC_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: IMM_HP_APB_ICG + description: need_des + addressOffset: 216 + size: 32 + fields: + - name: UPDATE_DIG_ICG_APB_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: IMM_MODEM_ICG + description: need_des + addressOffset: 220 + size: 32 + fields: + - name: UPDATE_DIG_ICG_MODEM_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: IMM_LP_ICG + description: need_des + addressOffset: 224 + size: 32 + fields: + - name: TIE_LOW_LP_ROOTCLK_SEL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_LP_ROOTCLK_SEL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: IMM_PAD_HOLD_ALL + description: need_des + addressOffset: 228 + size: 32 + fields: + - name: TIE_HIGH_LP_PAD_HOLD_ALL + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: TIE_LOW_LP_PAD_HOLD_ALL + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_HP_PAD_HOLD_ALL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: TIE_LOW_HP_PAD_HOLD_ALL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: IMM_I2C_ISO + description: need_des + addressOffset: 232 + size: 32 + fields: + - name: TIE_HIGH_I2C_ISO_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: TIE_LOW_I2C_ISO_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: POWER_WAIT_TIMER0 + description: need_des + addressOffset: 236 + size: 32 + resetValue: 2143281120 + fields: + - name: DG_HP_POWERDOWN_TIMER + description: need_des + bitOffset: 5 + bitWidth: 9 + access: read-write + - name: DG_HP_POWERUP_TIMER + description: need_des + bitOffset: 14 + bitWidth: 9 + access: read-write + - name: DG_HP_WAIT_TIMER + description: need_des + bitOffset: 23 + bitWidth: 9 + access: read-write + - register: + name: POWER_WAIT_TIMER1 + description: need_des + addressOffset: 240 + size: 32 + resetValue: 2147483136 + fields: + - name: DG_LP_POWERDOWN_TIMER + description: need_des + bitOffset: 9 + bitWidth: 7 + access: read-write + - name: DG_LP_POWERUP_TIMER + description: need_des + bitOffset: 16 + bitWidth: 7 + access: read-write + - name: DG_LP_WAIT_TIMER + description: need_des + bitOffset: 23 + bitWidth: 9 + access: read-write + - register: + name: POWER_PD_TOP_CNTL + description: need_des + addressOffset: 244 + size: 32 + resetValue: 28 + fields: + - name: FORCE_TOP_RESET + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FORCE_TOP_ISO + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FORCE_TOP_PU + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FORCE_TOP_NO_RESET + description: need_des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FORCE_TOP_NO_ISO + description: need_des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FORCE_TOP_PD + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: PD_TOP_MASK + description: need_des + bitOffset: 6 + bitWidth: 5 + access: read-write + - name: PD_TOP_PD_MASK + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: POWER_PD_HPAON_CNTL + description: need_des + addressOffset: 248 + size: 32 + resetValue: 28 + fields: + - name: FORCE_HP_AON_RESET + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FORCE_HP_AON_ISO + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FORCE_HP_AON_PU + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FORCE_HP_AON_NO_RESET + description: need_des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FORCE_HP_AON_NO_ISO + description: need_des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FORCE_HP_AON_PD + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: PD_HP_AON_MASK + description: need_des + bitOffset: 6 + bitWidth: 5 + access: read-write + - name: PD_HP_AON_PD_MASK + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: POWER_PD_HPCPU_CNTL + description: need_des + addressOffset: 252 + size: 32 + resetValue: 28 + fields: + - name: FORCE_HP_CPU_RESET + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FORCE_HP_CPU_ISO + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FORCE_HP_CPU_PU + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FORCE_HP_CPU_NO_RESET + description: need_des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FORCE_HP_CPU_NO_ISO + description: need_des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FORCE_HP_CPU_PD + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: PD_HP_CPU_MASK + description: need_des + bitOffset: 6 + bitWidth: 5 + access: read-write + - name: PD_HP_CPU_PD_MASK + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: POWER_PD_HPPERI_RESERVE + description: need_des + addressOffset: 256 + size: 32 + fields: + - name: HP_PERI_RESERVE + description: need_des + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: POWER_PD_HPWIFI_CNTL + description: need_des + addressOffset: 260 + size: 32 + resetValue: 28 + fields: + - name: FORCE_HP_WIFI_RESET + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FORCE_HP_WIFI_ISO + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FORCE_HP_WIFI_PU + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FORCE_HP_WIFI_NO_RESET + description: need_des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FORCE_HP_WIFI_NO_ISO + description: need_des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FORCE_HP_WIFI_PD + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: PD_HP_WIFI_MASK + description: need_des + bitOffset: 6 + bitWidth: 5 + access: read-write + - name: PD_HP_WIFI_PD_MASK + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: POWER_PD_LPPERI_CNTL + description: need_des + addressOffset: 264 + size: 32 + resetValue: 28 + fields: + - name: FORCE_LP_PERI_RESET + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FORCE_LP_PERI_ISO + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FORCE_LP_PERI_PU + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FORCE_LP_PERI_NO_RESET + description: need_des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FORCE_LP_PERI_NO_ISO + description: need_des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FORCE_LP_PERI_PD + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: POWER_PD_MEM_CNTL + description: need_des + addressOffset: 268 + size: 32 + resetValue: 4278190080 + fields: + - name: FORCE_HP_MEM_ISO + description: need_des + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: FORCE_HP_MEM_PD + description: need_des + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: FORCE_HP_MEM_NO_ISO + description: need_des + bitOffset: 24 + bitWidth: 4 + access: read-write + - name: FORCE_HP_MEM_PU + description: need_des + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: POWER_PD_MEM_MASK + description: need_des + addressOffset: 272 + size: 32 + fields: + - name: PD_HP_MEM2_PD_MASK + description: need_des + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: PD_HP_MEM1_PD_MASK + description: need_des + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: PD_HP_MEM0_PD_MASK + description: need_des + bitOffset: 10 + bitWidth: 5 + access: read-write + - name: PD_HP_MEM2_MASK + description: need_des + bitOffset: 17 + bitWidth: 5 + access: read-write + - name: PD_HP_MEM1_MASK + description: need_des + bitOffset: 22 + bitWidth: 5 + access: read-write + - name: PD_HP_MEM0_MASK + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: POWER_HP_PAD + description: need_des + addressOffset: 276 + size: 32 + fields: + - name: FORCE_HP_PAD_NO_ISO_ALL + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FORCE_HP_PAD_ISO_ALL + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: POWER_VDD_SPI_CNTL + description: need_des + addressOffset: 280 + size: 32 + resetValue: 1677459456 + fields: + - name: VDD_SPI_PWR_WAIT + description: need_des + bitOffset: 18 + bitWidth: 11 + access: read-write + - name: VDD_SPI_PWR_SW + description: need_des + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: VDD_SPI_PWR_SEL_SW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: POWER_CK_WAIT_CNTL + description: need_des + addressOffset: 284 + size: 32 + resetValue: 16777472 + fields: + - name: WAIT_XTL_STABLE + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: WAIT_PLL_STABLE + description: need_des + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SLP_WAKEUP_CNTL0 + description: need_des + addressOffset: 288 + size: 32 + fields: + - name: SLEEP_REQ + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SLP_WAKEUP_CNTL1 + description: need_des + addressOffset: 292 + size: 32 + fields: + - name: SLEEP_REJECT_ENA + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: SLP_REJECT_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SLP_WAKEUP_CNTL2 + description: need_des + addressOffset: 296 + size: 32 + fields: + - name: WAKEUP_ENA + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SLP_WAKEUP_CNTL3 + description: need_des + addressOffset: 300 + size: 32 + fields: + - name: LP_MIN_SLP_VAL + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HP_MIN_SLP_VAL + description: need_des + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SLEEP_PRT_SEL + description: need_des + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: SLP_WAKEUP_CNTL4 + description: need_des + addressOffset: 304 + size: 32 + fields: + - name: SLP_REJECT_CAUSE_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SLP_WAKEUP_CNTL5 + description: need_des + addressOffset: 308 + size: 32 + resetValue: 16777344 + fields: + - name: MODEM_WAIT_TARGET + description: need_des + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: LP_ANA_WAIT_TARGET + description: need_des + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: SLP_WAKEUP_CNTL6 + description: need_des + addressOffset: 312 + size: 32 + resetValue: 128 + fields: + - name: SOC_WAKEUP_WAIT + description: need_des + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: SOC_WAKEUP_WAIT_CFG + description: need_des + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: SLP_WAKEUP_CNTL7 + description: need_des + addressOffset: 316 + size: 32 + resetValue: 65536 + fields: + - name: ANA_WAIT_TARGET + description: need_des + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SLP_WAKEUP_STATUS0 + description: need_des + addressOffset: 320 + size: 32 + fields: + - name: WAKEUP_CAUSE + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SLP_WAKEUP_STATUS1 + description: need_des + addressOffset: 324 + size: 32 + fields: + - name: REJECT_CAUSE + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HP_CK_POWERON + description: need_des + addressOffset: 328 + size: 32 + resetValue: 50 + fields: + - name: I2C_POR_WAIT_TARGET + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: HP_CK_CNTL + description: need_des + addressOffset: 332 + size: 32 + resetValue: 2570 + fields: + - name: MODIFY_ICG_CNTL_WAIT + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SWITCH_ICG_CNTL_WAIT + description: need_des + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: POR_STATUS + description: need_des + addressOffset: 336 + size: 32 + resetValue: 2147483648 + fields: + - name: POR_DONE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: RF_PWC + description: need_des + addressOffset: 340 + size: 32 + resetValue: 134217728 + fields: + - name: XPD_PERIF_I2C + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: XPD_RFTX_I2C + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: XPD_RFRX_I2C + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: XPD_RFPLL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: XPD_FORCE_RFPLL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: VDDBAT_CFG + description: need_des + addressOffset: 344 + size: 32 + fields: + - name: VDDBAT_MODE + description: need_des + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: VDDBAT_SW_UPDATE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: BACKUP_CFG + description: need_des + addressOffset: 348 + size: 32 + resetValue: 2147483648 + fields: + - name: BACKUP_SYS_CLK_NO_DIV + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: need_des + addressOffset: 352 + size: 32 + fields: + - name: LP_CPU_EXC_INT_RAW + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SDIO_IDLE_INT_RAW + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SW_INT_RAW + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SOC_SLEEP_REJECT_INT_RAW + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SOC_WAKEUP_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_INT_ST + description: need_des + addressOffset: 356 + size: 32 + fields: + - name: LP_CPU_EXC_INT_ST + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: SDIO_IDLE_INT_ST + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SW_INT_ST + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: SOC_SLEEP_REJECT_INT_ST + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: SOC_WAKEUP_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: HP_INT_ENA + description: need_des + addressOffset: 360 + size: 32 + fields: + - name: LP_CPU_EXC_INT_ENA + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SDIO_IDLE_INT_ENA + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SW_INT_ENA + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SOC_SLEEP_REJECT_INT_ENA + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SOC_WAKEUP_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_INT_CLR + description: need_des + addressOffset: 364 + size: 32 + fields: + - name: LP_CPU_EXC_INT_CLR + description: need_des + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: SDIO_IDLE_INT_CLR + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: SW_INT_CLR + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: SOC_SLEEP_REJECT_INT_CLR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: SOC_WAKEUP_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: LP_INT_RAW + description: need_des + addressOffset: 368 + size: 32 + fields: + - name: LP_CPU_WAKEUP_INT_RAW + description: need_des + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: MODEM_SWITCH_ACTIVE_END_INT_RAW + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SLEEP_SWITCH_ACTIVE_END_INT_RAW + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SLEEP_SWITCH_MODEM_END_INT_RAW + description: need_des + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: MODEM_SWITCH_SLEEP_END_INT_RAW + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ACTIVE_SWITCH_SLEEP_END_INT_RAW + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: MODEM_SWITCH_ACTIVE_START_INT_RAW + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SLEEP_SWITCH_ACTIVE_START_INT_RAW + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SLEEP_SWITCH_MODEM_START_INT_RAW + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: MODEM_SWITCH_SLEEP_START_INT_RAW + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ACTIVE_SWITCH_SLEEP_START_INT_RAW + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HP_SW_TRIGGER_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_INT_ST + description: need_des + addressOffset: 372 + size: 32 + fields: + - name: LP_CPU_WAKEUP_INT_ST + description: need_des + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: MODEM_SWITCH_ACTIVE_END_INT_ST + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SLEEP_SWITCH_ACTIVE_END_INT_ST + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: SLEEP_SWITCH_MODEM_END_INT_ST + description: need_des + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: MODEM_SWITCH_SLEEP_END_INT_ST + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: ACTIVE_SWITCH_SLEEP_END_INT_ST + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: MODEM_SWITCH_ACTIVE_START_INT_ST + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: SLEEP_SWITCH_ACTIVE_START_INT_ST + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: SLEEP_SWITCH_MODEM_START_INT_ST + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: MODEM_SWITCH_SLEEP_START_INT_ST + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: ACTIVE_SWITCH_SLEEP_START_INT_ST + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: HP_SW_TRIGGER_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: LP_INT_ENA + description: need_des + addressOffset: 376 + size: 32 + fields: + - name: LP_CPU_WAKEUP_INT_ENA + description: need_des + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: MODEM_SWITCH_ACTIVE_END_INT_ENA + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SLEEP_SWITCH_ACTIVE_END_INT_ENA + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SLEEP_SWITCH_MODEM_END_INT_ENA + description: need_des + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: MODEM_SWITCH_SLEEP_END_INT_ENA + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ACTIVE_SWITCH_SLEEP_END_INT_ENA + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: MODEM_SWITCH_ACTIVE_START_INT_ENA + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SLEEP_SWITCH_ACTIVE_START_INT_ENA + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SLEEP_SWITCH_MODEM_START_INT_ENA + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: MODEM_SWITCH_SLEEP_START_INT_ENA + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ACTIVE_SWITCH_SLEEP_START_INT_ENA + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HP_SW_TRIGGER_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_INT_CLR + description: need_des + addressOffset: 380 + size: 32 + fields: + - name: LP_CPU_WAKEUP_INT_CLR + description: need_des + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: MODEM_SWITCH_ACTIVE_END_INT_CLR + description: need_des + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: SLEEP_SWITCH_ACTIVE_END_INT_CLR + description: need_des + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: SLEEP_SWITCH_MODEM_END_INT_CLR + description: need_des + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: MODEM_SWITCH_SLEEP_END_INT_CLR + description: need_des + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: ACTIVE_SWITCH_SLEEP_END_INT_CLR + description: need_des + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: MODEM_SWITCH_ACTIVE_START_INT_CLR + description: need_des + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: SLEEP_SWITCH_ACTIVE_START_INT_CLR + description: need_des + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: SLEEP_SWITCH_MODEM_START_INT_CLR + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: MODEM_SWITCH_SLEEP_START_INT_CLR + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: ACTIVE_SWITCH_SLEEP_START_INT_CLR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: HP_SW_TRIGGER_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: LP_CPU_PWR0 + description: need_des + addressOffset: 384 + size: 32 + resetValue: 535822336 + fields: + - name: LP_CPU_WAITI_RDY + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: LP_CPU_STALL_RDY + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: LP_CPU_FORCE_STALL + description: need_des + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: LP_CPU_SLP_WAITI_FLAG_EN + description: need_des + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: LP_CPU_SLP_STALL_FLAG_EN + description: need_des + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: LP_CPU_SLP_STALL_WAIT + description: need_des + bitOffset: 21 + bitWidth: 8 + access: read-write + - name: LP_CPU_SLP_STALL_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LP_CPU_SLP_RESET_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_CPU_SLP_BYPASS_INTR_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_CPU_PWR1 + description: need_des + addressOffset: 388 + size: 32 + fields: + - name: LP_CPU_WAKEUP_EN + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: LP_CPU_SLEEP_REQ + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: HP_LP_CPU_COMM + description: need_des + addressOffset: 392 + size: 32 + fields: + - name: LP_TRIGGER_HP + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: HP_TRIGGER_LP + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: HP_REGULATOR_CFG + description: need_des + addressOffset: 396 + size: 32 + fields: + - name: DIG_REGULATOR_EN_CAL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: MAIN_STATE + description: need_des + addressOffset: 400 + size: 32 + resetValue: 135268352 + fields: + - name: MAIN_LAST_ST_STATE + description: need_des + bitOffset: 11 + bitWidth: 7 + access: read-only + - name: MAIN_TAR_ST_STATE + description: need_des + bitOffset: 18 + bitWidth: 7 + access: read-only + - name: MAIN_CUR_ST_STATE + description: need_des + bitOffset: 25 + bitWidth: 7 + access: read-only + - register: + name: PWR_STATE + description: need_des + addressOffset: 404 + size: 32 + resetValue: 8396800 + fields: + - name: BACKUP_ST_STATE + description: need_des + bitOffset: 13 + bitWidth: 5 + access: read-only + - name: LP_PWR_ST_STATE + description: need_des + bitOffset: 18 + bitWidth: 5 + access: read-only + - name: HP_PWR_ST_STATE + description: need_des + bitOffset: 23 + bitWidth: 9 + access: read-only + - register: + name: CLK_STATE0 + description: need_des + addressOffset: 408 + size: 32 + resetValue: 3 + fields: + - name: STABLE_XPD_BBPLL_STATE + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: STABLE_XPD_XTAL_STATE + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SYS_CLK_SLP_SEL_STATE + description: need_des + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SYS_CLK_SEL_STATE + description: need_des + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: SYS_CLK_NO_DIV_STATE + description: need_des + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: ICG_SYS_CLK_EN_STATE + description: need_des + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: ICG_MODEM_SWITCH_STATE + description: need_des + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: ICG_MODEM_CODE_STATE + description: need_des + bitOffset: 21 + bitWidth: 2 + access: read-only + - name: ICG_SLP_SEL_STATE + description: need_des + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: ICG_GLOBAL_XTAL_STATE + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: ICG_GLOBAL_PLL_STATE + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: ANA_I2C_ISO_EN_STATE + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: ANA_I2C_RETENTION_STATE + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: ANA_XPD_BB_I2C_STATE + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: ANA_XPD_BBPLL_I2C_STATE + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: ANA_XPD_BBPLL_STATE + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: ANA_XPD_XTAL_STATE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CLK_STATE1 + description: need_des + addressOffset: 412 + size: 32 + resetValue: 4294967295 + fields: + - name: ICG_FUNC_EN_STATE + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CLK_STATE2 + description: need_des + addressOffset: 416 + size: 32 + resetValue: 4294967295 + fields: + - name: ICG_APB_EN_STATE + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: VDD_SPI_STATUS + description: need_des + addressOffset: 420 + size: 32 + fields: + - name: STABLE_VDD_SPI_PWR_DRV + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 35688960 + fields: + - name: PMU_DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: RMT + description: Remote Control + groupName: RMT + baseAddress: 1610641408 + addressBlock: + - offset: 0 + size: 120 + usage: registers + interrupt: + - name: RMT + value: 38 + registers: + - register: + dim: 4 + dimIncrement: 4 + name: CH%sDATA + description: The read and write data register for CHANNEL%s by apb fifo access. + addressOffset: 0 + size: 32 + fields: + - name: DATA + description: Read and write data for channel %s via APB FIFO. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 2 + dimIncrement: 4 + name: CH%s_TX_CONF0 + description: Channel %s configure register 0 + addressOffset: 16 + size: 32 + resetValue: 7406080 + fields: + - name: TX_START + description: Set this bit to start sending data on CHANNEL%s. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: MEM_RD_RST + description: Set this bit to reset read ram address for CHANNEL%s by accessing transmitter. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: APB_MEM_RST + description: Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TX_CONTI_MODE + description: Set this bit to restart transmission from the first data to the last data in CHANNEL%s. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MEM_TX_WRAP_EN + description: "This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IDLE_OUT_LV + description: This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: IDLE_OUT_EN + description: This is the output enable-control bit for CHANNEL%s in IDLE state. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_STOP + description: Set this bit to stop the transmitter of CHANNEL%s sending data out. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DIV_CNT + description: This register is used to configure the divider for clock of CHANNEL%s. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: MEM_SIZE + description: This register is used to configure the maximum size of memory allocated to CHANNEL%s. + bitOffset: 16 + bitWidth: 3 + access: read-write + - name: CARRIER_EFF_EN + description: "1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CARRIER_EN + description: "This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CARRIER_OUT_LV + description: "This bit is used to configure the position of carrier wave for CHANNEL%s.\n\n1'h0: add carrier wave on low level.\n\n1'h1: add carrier wave on high level." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: AFIFO_RST + description: Reserved + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: CONF_UPDATE + description: synchronization bit for CHANNEL%s + bitOffset: 24 + bitWidth: 1 + access: write-only + - register: + dim: 2 + dimIncrement: 8 + dimIndex: "2,3" + name: CH%s_RX_CONF0 + description: Channel %s configure register 0 + addressOffset: 24 + size: 32 + resetValue: 822083330 + fields: + - name: DIV_CNT + description: This register is used to configure the divider for clock of CHANNEL%s. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: IDLE_THRES + description: "When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished." + bitOffset: 8 + bitWidth: 15 + access: read-write + - name: MEM_SIZE + description: This register is used to configure the maximum size of memory allocated to CHANNEL%s. + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: CARRIER_EN + description: "This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CARRIER_OUT_LV + description: "This bit is used to configure the position of carrier wave for CHANNEL%s.\n\n1'h0: add carrier wave on low level.\n\n1'h1: add carrier wave on high level." + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + dim: 2 + dimIncrement: 8 + dimIndex: "2,3" + name: CH%s_RX_CONF1 + description: Channel %s configure register 1 + addressOffset: 28 + size: 32 + resetValue: 488 + fields: + - name: RX_EN + description: Set this bit to enable receiver to receive data on CHANNEL%s. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_WR_RST + description: Set this bit to reset write ram address for CHANNEL%s by accessing receiver. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: APB_MEM_RST + description: Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: MEM_OWNER + description: "This register marks the ownership of CHANNEL%s's ram block.\n\n1'h1: Receiver is using the ram. \n\n1'h0: APB bus is using the ram." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_FILTER_EN + description: "This is the receive filter's enable bit for CHANNEL%s." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_FILTER_THRES + description: Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode). + bitOffset: 5 + bitWidth: 8 + access: read-write + - name: MEM_RX_WRAP_EN + description: "This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: AFIFO_RST + description: Reserved + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: CONF_UPDATE + description: synchronization bit for CHANNEL%s + bitOffset: 15 + bitWidth: 1 + access: write-only + - register: + dim: 2 + dimIncrement: 4 + name: CH%s_TX_STATUS + description: Channel %s status register + addressOffset: 40 + size: 32 + fields: + - name: MEM_RADDR_EX + description: This register records the memory address offset when transmitter of CHANNEL%s is using the RAM. + bitOffset: 0 + bitWidth: 9 + access: read-only + - name: STATE + description: This register records the FSM status of CHANNEL%s. + bitOffset: 9 + bitWidth: 3 + access: read-only + - name: APB_MEM_WADDR + description: This register records the memory address offset when writes RAM over APB bus. + bitOffset: 12 + bitWidth: 9 + access: read-only + - name: APB_MEM_RD_ERR + description: This status bit will be set if the offset address out of memory size when reading via APB bus. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: MEM_EMPTY + description: This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled. + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: APB_MEM_WR_ERR + description: This status bit will be set if the offset address out of memory size when writes via APB bus. + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: APB_MEM_RADDR + description: This register records the memory address offset when reading RAM over APB bus. + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + dim: 2 + dimIncrement: 4 + name: CH%s_RX_STATUS + description: Channel %s status register + addressOffset: 48 + size: 32 + fields: + - name: MEM_WADDR_EX + description: This register records the memory address offset when receiver of CHANNEL%s is using the RAM. + bitOffset: 0 + bitWidth: 9 + access: read-only + - name: APB_MEM_RADDR + description: This register records the memory address offset when reads RAM over APB bus. + bitOffset: 12 + bitWidth: 9 + access: read-only + - name: STATE + description: This register records the FSM status of CHANNEL%s. + bitOffset: 22 + bitWidth: 3 + access: read-only + - name: MEM_OWNER_ERR + description: This status bit will be set when the ownership of memory block is wrong. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: MEM_FULL + description: This status bit will be set if the receiver receives more data than the memory size. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: APB_MEM_RD_ERR + description: This status bit will be set if the offset address out of memory size when reads via APB bus. + bitOffset: 27 + bitWidth: 1 + access: read-only + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 56 + size: 32 + fields: + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_END + description: The interrupt raw bit for CHANNEL%s. Triggered when transmission done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_END + description: The interrupt raw bit for CHANNEL2. Triggered when reception done. + bitOffset: 2 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_ERR + description: The interrupt raw bit for CHANNEL4. Triggered when error occurs. + bitOffset: 4 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_ERR + description: The interrupt raw bit for CHANNEL6. Triggered when error occurs. + bitOffset: 6 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_THR_EVENT + description: The interrupt raw bit for CHANNEL%s. Triggered when transmitter sent more data than configured value. + bitOffset: 8 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_THR_EVENT + description: The interrupt raw bit for CHANNEL2. Triggered when receiver receive more data than configured value. + bitOffset: 10 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_LOOP + description: The interrupt raw bit for CHANNEL%s. Triggered when the loop count reaches the configured threshold value. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 60 + size: 32 + fields: + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_END + description: The masked interrupt status bit for CH%s_TX_END_INT. + bitOffset: 0 + bitWidth: 1 + access: read-only + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_END + description: The masked interrupt status bit for CH2_RX_END_INT. + bitOffset: 2 + bitWidth: 1 + access: read-only + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_ERR + description: The masked interrupt status bit for CH4_ERR_INT. + bitOffset: 4 + bitWidth: 1 + access: read-only + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_ERR + description: The masked interrupt status bit for CH6_ERR_INT. + bitOffset: 6 + bitWidth: 1 + access: read-only + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_THR_EVENT + description: The masked interrupt status bit for CH%s_TX_THR_EVENT_INT. + bitOffset: 8 + bitWidth: 1 + access: read-only + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_THR_EVENT + description: The masked interrupt status bit for CH2_RX_THR_EVENT_INT. + bitOffset: 10 + bitWidth: 1 + access: read-only + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_X_LOOP + description: The masked interrupt status bit for CH%s_TX_LOOP_INT. + bitOffset: 12 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 64 + size: 32 + fields: + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_END + description: The interrupt enable bit for CH%s_TX_END_INT. + bitOffset: 0 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_END + description: The interrupt enable bit for CH2_RX_END_INT. + bitOffset: 2 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_ERR + description: The interrupt enable bit for CH4_ERR_INT. + bitOffset: 4 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_ERR + description: The interrupt enable bit for CH6_ERR_INT. + bitOffset: 6 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_THR_EVENT + description: The interrupt enable bit for CH%s_TX_THR_EVENT_INT. + bitOffset: 8 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_THR_EVENT + description: The interrupt enable bit for CH2_RX_THR_EVENT_INT. + bitOffset: 10 + bitWidth: 1 + access: read-write + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_X_LOOP + description: The interrupt enable bit for CH%s_TX_LOOP_INT. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 68 + size: 32 + fields: + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_END + description: Set this bit to clear theCH%s_TX_END_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_END + description: Set this bit to clear theCH2_RX_END_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_ERR + description: Set this bit to clear theCH4_ERR_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_ERR + description: Set this bit to clear theCH6_ERR_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_THR_EVENT + description: Set this bit to clear theCH%s_TX_THR_EVENT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - dim: 2 + dimIncrement: 1 + dimIndex: "2,3" + name: CH%s_RX_THR_EVENT + description: Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - dim: 2 + dimIncrement: 1 + dimIndex: "0,1" + name: CH%s_TX_LOOP + description: Set this bit to clear theCH%s_TX_LOOP_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - register: + dim: 2 + dimIncrement: 4 + name: CH%sCARRIER_DUTY + description: Channel %s duty cycle configuration register + addressOffset: 72 + size: 32 + resetValue: 4194368 + fields: + - name: CARRIER_LOW + description: "This register is used to configure carrier wave 's low level clock period for CHANNEL%s." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CARRIER_HIGH + description: "This register is used to configure carrier wave 's high level clock period for CHANNEL%s." + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + dim: 2 + dimIncrement: 4 + name: CH%s_RX_CARRIER_RM + description: Channel %s carrier remove register + addressOffset: 80 + size: 32 + fields: + - name: CARRIER_LOW_THRES + description: The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CARRIER_HIGH_THRES + description: The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + dim: 2 + dimIncrement: 4 + name: CH%s_TX_LIM + description: Channel %s Tx event configuration register + addressOffset: 88 + size: 32 + resetValue: 128 + fields: + - name: TX_LIM + description: This register is used to configure the maximum entries that CHANNEL%s can send out. + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: TX_LOOP_NUM + description: This register is used to configure the maximum loop count when tx_conti_mode is valid. + bitOffset: 9 + bitWidth: 10 + access: read-write + - name: TX_LOOP_CNT_EN + description: This register is the enabled bit for loop count. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: LOOP_COUNT_RESET + description: This register is used to reset the loop count when tx_conti_mode is valid. + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: LOOP_STOP_EN + description: This bit is used to enable the loop send stop function after the loop counter counts to loop number for CHANNEL%s. + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + dim: 2 + dimIncrement: 4 + name: CH%s_RX_LIM + description: Channel %s Rx event configuration register + addressOffset: 96 + size: 32 + resetValue: 128 + fields: + - name: RMT_RX_LIM + description: This register is used to configure the maximum entries that CHANNEL%s can receive. + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SYS_CONF + description: RMT apb configuration register + addressOffset: 104 + size: 32 + resetValue: 83886096 + fields: + - name: APB_FIFO_MASK + description: "1'h1: access memory directly. 1'h0: access memory by FIFO." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_CLK_FORCE_ON + description: Set this bit to enable the clock for RMT memory. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PD + description: Set this bit to power down RMT memory. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PU + description: "1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SCLK_DIV_NUM + description: the integral part of the fractional divisor + bitOffset: 4 + bitWidth: 8 + access: read-write + - name: SCLK_DIV_A + description: the numerator of the fractional part of the fractional divisor + bitOffset: 12 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_B + description: the denominator of the fractional part of the fractional divisor + bitOffset: 18 + bitWidth: 6 + access: read-write + - name: SCLK_SEL + description: "choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL" + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: SCLK_ACTIVE + description: rmt_sclk switch + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TX_SIM + description: RMT TX synchronous register + addressOffset: 108 + size: 32 + fields: + - name: CH0 + description: Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CH1 + description: Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EN + description: This register is used to enable multiple of channels to start sending data synchronously. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: REF_CNT_RST + description: RMT clock divider reset register + addressOffset: 112 + size: 32 + fields: + - name: TX_REF_CNT_RST + description: This register is used to reset the clock divider of CHANNEL0. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TX_REF_CNT_RST_CH1 + description: This register is used to reset the clock divider of CHANNEL1. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_REF_CNT_RST_CH2 + description: This register is used to reset the clock divider of CHANNEL2. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: RX_REF_CNT_RST_CH3 + description: This register is used to reset the clock divider of CHANNEL3. + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: DATE + description: RMT version register + addressOffset: 204 + size: 32 + resetValue: 34636307 + fields: + - name: RMT_DATE + description: This is the version register. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: RNG + description: Hardware Random Number Generator + groupName: RNG + baseAddress: 1611343872 + addressBlock: + - offset: 0 + size: 4 + usage: registers + registers: + - register: + name: DATA + description: Random number data + addressOffset: 8 + size: 32 + access: read-only + - name: RSA + description: RSA (Rivest Shamir Adleman) Accelerator + groupName: RSA + baseAddress: 1611177984 + addressBlock: + - offset: 0 + size: 116 + usage: registers + interrupt: + - name: RSA + value: 62 + registers: + - register: + dim: 96 + dimIncrement: 4 + name: "M_MEM[%s]" + description: Represents M + addressOffset: 0 + size: 32 + access: read-write + - register: + dim: 96 + dimIncrement: 4 + name: "Z_MEM[%s]" + description: Represents Z + addressOffset: 512 + size: 32 + access: read-write + - register: + dim: 96 + dimIncrement: 4 + name: "Y_MEM[%s]" + description: Represents Y + addressOffset: 1024 + size: 32 + access: read-write + - register: + dim: 96 + dimIncrement: 4 + name: "X_MEM[%s]" + description: Represents X + addressOffset: 1536 + size: 32 + access: read-write + - register: + name: M_PRIME + description: Represents M’ + addressOffset: 2048 + size: 32 + fields: + - name: M_PRIME + description: Represents M’ + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: MODE + description: Configures RSA length + addressOffset: 2052 + size: 32 + fields: + - name: MODE + description: Configures the RSA length. + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: QUERY_CLEAN + description: RSA clean register + addressOffset: 2056 + size: 32 + fields: + - name: QUERY_CLEAN + description: "Represents whether or not the RSA memory completes initialization.\n\n0: Not complete\n\n1: Completed" + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: SET_START_MODEXP + description: Starts modular exponentiation + addressOffset: 2060 + size: 32 + fields: + - name: SET_START_MODEXP + description: "Configure whether or not to start the modular exponentiation.\n\n0: No effect\n\n1: Start" + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_START_MODMULT + description: Starts modular multiplication + addressOffset: 2064 + size: 32 + fields: + - name: SET_START_MODMULT + description: "Configure whether or not to start the modular multiplication.\n\n0: No effect\n\n1: Start" + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_START_MULT + description: Starts multiplication + addressOffset: 2068 + size: 32 + fields: + - name: SET_START_MULT + description: "Configure whether or not to start the multiplication.\n\n0: No effect\n\n1: Start" + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: QUERY_IDLE + description: Represents the RSA status + addressOffset: 2072 + size: 32 + fields: + - name: QUERY_IDLE + description: "Represents the RSA status.\n\n0: Busy\n\n1: Idle" + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: Clears RSA interrupt + addressOffset: 2076 + size: 32 + fields: + - name: CLEAR_INTERRUPT + description: Write 1 to clear the RSA interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: CONSTANT_TIME + description: Configures the constant_time option + addressOffset: 2080 + size: 32 + resetValue: 1 + fields: + - name: CONSTANT_TIME + description: "Configures the constant_time option. \n\n0: Acceleration\n\n1: No acceleration (default)" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SEARCH_ENABLE + description: Configures the search option + addressOffset: 2084 + size: 32 + fields: + - name: SEARCH_ENABLE + description: "Configure the search option. \n\n0: No acceleration (default)\n\n1: Acceleration\n\nThis option should be used together with RSA_SEARCH_POS." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SEARCH_POS + description: Configures the search position + addressOffset: 2088 + size: 32 + fields: + - name: SEARCH_POS + description: Configures the starting address to start search. This field should be used together with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high. + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: INT_ENA + description: Enables the RSA interrupt + addressOffset: 2092 + size: 32 + fields: + - name: INT_ENA + description: Write 1 to enable the RSA interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 2096 + size: 32 + resetValue: 538969624 + fields: + - name: DATE + description: Version control register. + bitOffset: 0 + bitWidth: 30 + access: read-write + - name: SHA + description: SHA (Secure Hash Algorithm) Accelerator + groupName: SHA + baseAddress: 1611173888 + addressBlock: + - offset: 0 + size: 176 + usage: registers + interrupt: + - name: SHA + value: 61 + registers: + - register: + name: MODE + description: Initial configuration register. + addressOffset: 0 + size: 32 + fields: + - name: MODE + description: Sha mode. + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: T_STRING + description: SHA 512/t configuration register 0. + addressOffset: 4 + size: 32 + fields: + - name: T_STRING + description: Sha t_string (used if and only if mode == SHA_512/t). + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: T_LENGTH + description: SHA 512/t configuration register 1. + addressOffset: 8 + size: 32 + fields: + - name: T_LENGTH + description: Sha t_length (used if and only if mode == SHA_512/t). + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: DMA_BLOCK_NUM + description: DMA configuration register 0. + addressOffset: 12 + size: 32 + fields: + - name: DMA_BLOCK_NUM + description: Dma-sha block number. + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: START + description: Typical SHA configuration register 0. + addressOffset: 16 + size: 32 + fields: + - name: START + description: Reserved. + bitOffset: 1 + bitWidth: 31 + access: write-only + - register: + name: CONTINUE + description: Typical SHA configuration register 1. + addressOffset: 20 + size: 32 + fields: + - name: CONTINUE + description: Reserved. + bitOffset: 1 + bitWidth: 31 + access: write-only + - register: + name: BUSY + description: Busy register. + addressOffset: 24 + size: 32 + fields: + - name: STATE + description: "Sha busy state. 1'b0: idle. 1'b1: busy." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: DMA_START + description: DMA configuration register 1. + addressOffset: 28 + size: 32 + fields: + - name: DMA_START + description: Start dma-sha. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: DMA_CONTINUE + description: DMA configuration register 2. + addressOffset: 32 + size: 32 + fields: + - name: DMA_CONTINUE + description: Continue dma-sha. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: CLEAR_IRQ + description: Interrupt clear register. + addressOffset: 36 + size: 32 + fields: + - name: CLEAR_INTERRUPT + description: Clear sha interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: IRQ_ENA + description: Interrupt enable register. + addressOffset: 40 + size: 32 + fields: + - name: INTERRUPT_ENA + description: "Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Date register. + addressOffset: 44 + size: 32 + resetValue: 538972713 + fields: + - name: DATE + description: Sha date information/ sha version information. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + name: "H_MEM[%s]" + description: Sha H memory which contains intermediate hash or finial hash. + addressOffset: 64 + size: 32 + - register: + dim: 16 + dimIncrement: 4 + name: "M_MEM[%s]" + description: Sha M memory which contains message. + addressOffset: 128 + size: 32 + - name: SOC_ETM + description: Event Task Matrix + groupName: SOC_ETM + baseAddress: 1610690560 + addressBlock: + - offset: 0 + size: 432 + usage: registers + registers: + - register: + name: CH_ENA_AD0 + description: channel enable register + addressOffset: 0 + size: 32 + fields: + - name: CH_ENA0 + description: ch0 enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CH_ENA1 + description: ch1 enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CH_ENA2 + description: ch2 enable + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CH_ENA3 + description: ch3 enable + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CH_ENA4 + description: ch4 enable + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CH_ENA5 + description: ch5 enable + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CH_ENA6 + description: ch6 enable + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CH_ENA7 + description: ch7 enable + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CH_ENA8 + description: ch8 enable + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CH_ENA9 + description: ch9 enable + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CH_ENA10 + description: ch10 enable + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CH_ENA11 + description: ch11 enable + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CH_ENA12 + description: ch12 enable + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CH_ENA13 + description: ch13 enable + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: CH_ENA14 + description: ch14 enable + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CH_ENA15 + description: ch15 enable + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CH_ENA16 + description: ch16 enable + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CH_ENA17 + description: ch17 enable + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: CH_ENA18 + description: ch18 enable + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: CH_ENA19 + description: ch19 enable + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: CH_ENA20 + description: ch20 enable + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CH_ENA21 + description: ch21 enable + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CH_ENA22 + description: ch22 enable + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: CH_ENA23 + description: ch23 enable + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: CH_ENA24 + description: ch24 enable + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: CH_ENA25 + description: ch25 enable + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: CH_ENA26 + description: ch26 enable + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CH_ENA27 + description: ch27 enable + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: CH_ENA28 + description: ch28 enable + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CH_ENA29 + description: ch29 enable + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CH_ENA30 + description: ch30 enable + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CH_ENA31 + description: ch31 enable + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CH_ENA_AD0_SET + description: channel enable set register + addressOffset: 4 + size: 32 + fields: + - name: CH_SET0 + description: ch0 set + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CH_SET1 + description: ch1 set + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CH_SET2 + description: ch2 set + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CH_SET3 + description: ch3 set + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: CH_SET4 + description: ch4 set + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: CH_SET5 + description: ch5 set + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CH_SET6 + description: ch6 set + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: CH_SET7 + description: ch7 set + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: CH_SET8 + description: ch8 set + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: CH_SET9 + description: ch9 set + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: CH_SET10 + description: ch10 set + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: CH_SET11 + description: ch11 set + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: CH_SET12 + description: ch12 set + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: CH_SET13 + description: ch13 set + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: CH_SET14 + description: ch14 set + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: CH_SET15 + description: ch15 set + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: CH_SET16 + description: ch16 set + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: CH_SET17 + description: ch17 set + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: CH_SET18 + description: ch18 set + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: CH_SET19 + description: ch19 set + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: CH_SET20 + description: ch20 set + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: CH_SET21 + description: ch21 set + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: CH_SET22 + description: ch22 set + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: CH_SET23 + description: ch23 set + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: CH_SET24 + description: ch24 set + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: CH_SET25 + description: ch25 set + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: CH_SET26 + description: ch26 set + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: CH_SET27 + description: ch27 set + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: CH_SET28 + description: ch28 set + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: CH_SET29 + description: ch29 set + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: CH_SET30 + description: ch30 set + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: CH_SET31 + description: ch31 set + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: CH_ENA_AD0_CLR + description: channel enable clear register + addressOffset: 8 + size: 32 + fields: + - name: CH_CLR0 + description: ch0 clear + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CH_CLR1 + description: ch1 clear + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CH_CLR2 + description: ch2 clear + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CH_CLR3 + description: ch3 clear + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: CH_CLR4 + description: ch4 clear + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: CH_CLR5 + description: ch5 clear + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CH_CLR6 + description: ch6 clear + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: CH_CLR7 + description: ch7 clear + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: CH_CLR8 + description: ch8 clear + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: CH_CLR9 + description: ch9 clear + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: CH_CLR10 + description: ch10 clear + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: CH_CLR11 + description: ch11 clear + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: CH_CLR12 + description: ch12 clear + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: CH_CLR13 + description: ch13 clear + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: CH_CLR14 + description: ch14 clear + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: CH_CLR15 + description: ch15 clear + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: CH_CLR16 + description: ch16 clear + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: CH_CLR17 + description: ch17 clear + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: CH_CLR18 + description: ch18 clear + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: CH_CLR19 + description: ch19 clear + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: CH_CLR20 + description: ch20 clear + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: CH_CLR21 + description: ch21 clear + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: CH_CLR22 + description: ch22 clear + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: CH_CLR23 + description: ch23 clear + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: CH_CLR24 + description: ch24 clear + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: CH_CLR25 + description: ch25 clear + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: CH_CLR26 + description: ch26 clear + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: CH_CLR27 + description: ch27 clear + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: CH_CLR28 + description: ch28 clear + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: CH_CLR29 + description: ch29 clear + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: CH_CLR30 + description: ch30 clear + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: CH_CLR31 + description: ch31 clear + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: CH_ENA_AD1 + description: channel enable register + addressOffset: 12 + size: 32 + fields: + - name: CH_ENA32 + description: ch32 enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CH_ENA33 + description: ch33 enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CH_ENA34 + description: ch34 enable + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CH_ENA35 + description: ch35 enable + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CH_ENA36 + description: ch36 enable + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CH_ENA37 + description: ch37 enable + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CH_ENA38 + description: ch38 enable + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CH_ENA39 + description: ch39 enable + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CH_ENA40 + description: ch40 enable + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CH_ENA41 + description: ch41 enable + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CH_ENA42 + description: ch42 enable + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CH_ENA43 + description: ch43 enable + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CH_ENA44 + description: ch44 enable + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CH_ENA45 + description: ch45 enable + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: CH_ENA46 + description: ch46 enable + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CH_ENA47 + description: ch47 enable + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CH_ENA48 + description: ch48 enable + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CH_ENA49 + description: ch49 enable + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: CH_ENA_AD1_SET + description: channel enable set register + addressOffset: 16 + size: 32 + fields: + - name: CH_SET32 + description: ch32 set + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CH_SET33 + description: ch33 set + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CH_SET34 + description: ch34 set + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CH_SET35 + description: ch35 set + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: CH_SET36 + description: ch36 set + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: CH_SET37 + description: ch37 set + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CH_SET38 + description: ch38 set + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: CH_SET39 + description: ch39 set + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: CH_SET40 + description: ch40 set + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: CH_SET41 + description: ch41 set + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: CH_SET42 + description: ch42 set + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: CH_SET43 + description: ch43 set + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: CH_SET44 + description: ch44 set + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: CH_SET45 + description: ch45 set + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: CH_SET46 + description: ch46 set + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: CH_SET47 + description: ch47 set + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: CH_SET48 + description: ch48 set + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: CH_SET49 + description: ch49 set + bitOffset: 17 + bitWidth: 1 + access: write-only + - register: + name: CH_ENA_AD1_CLR + description: channel enable clear register + addressOffset: 20 + size: 32 + fields: + - name: CH_CLR32 + description: ch32 clear + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CH_CLR33 + description: ch33 clear + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CH_CLR34 + description: ch34 clear + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CH_CLR35 + description: ch35 clear + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: CH_CLR36 + description: ch36 clear + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: CH_CLR37 + description: ch37 clear + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CH_CLR38 + description: ch38 clear + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: CH_CLR39 + description: ch39 clear + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: CH_CLR40 + description: ch40 clear + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: CH_CLR41 + description: ch41 clear + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: CH_CLR42 + description: ch42 clear + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: CH_CLR43 + description: ch43 clear + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: CH_CLR44 + description: ch44 clear + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: CH_CLR45 + description: ch45 clear + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: CH_CLR46 + description: ch46 clear + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: CH_CLR47 + description: ch47 clear + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: CH_CLR48 + description: ch48 clear + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: CH_CLR49 + description: ch49 clear + bitOffset: 17 + bitWidth: 1 + access: write-only + - register: + name: CH0_EVT_ID + description: channel0 event id register + addressOffset: 24 + size: 32 + fields: + - name: CH0_EVT_ID + description: ch0_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH0_TASK_ID + description: channel0 task id register + addressOffset: 28 + size: 32 + fields: + - name: CH0_TASK_ID + description: ch0_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH1_EVT_ID + description: channel1 event id register + addressOffset: 32 + size: 32 + fields: + - name: CH1_EVT_ID + description: ch1_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH1_TASK_ID + description: channel1 task id register + addressOffset: 36 + size: 32 + fields: + - name: CH1_TASK_ID + description: ch1_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH2_EVT_ID + description: channel2 event id register + addressOffset: 40 + size: 32 + fields: + - name: CH2_EVT_ID + description: ch2_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH2_TASK_ID + description: channel2 task id register + addressOffset: 44 + size: 32 + fields: + - name: CH2_TASK_ID + description: ch2_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH3_EVT_ID + description: channel3 event id register + addressOffset: 48 + size: 32 + fields: + - name: CH3_EVT_ID + description: ch3_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH3_TASK_ID + description: channel3 task id register + addressOffset: 52 + size: 32 + fields: + - name: CH3_TASK_ID + description: ch3_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH4_EVT_ID + description: channel4 event id register + addressOffset: 56 + size: 32 + fields: + - name: CH4_EVT_ID + description: ch4_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH4_TASK_ID + description: channel4 task id register + addressOffset: 60 + size: 32 + fields: + - name: CH4_TASK_ID + description: ch4_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH5_EVT_ID + description: channel5 event id register + addressOffset: 64 + size: 32 + fields: + - name: CH5_EVT_ID + description: ch5_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH5_TASK_ID + description: channel5 task id register + addressOffset: 68 + size: 32 + fields: + - name: CH5_TASK_ID + description: ch5_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH6_EVT_ID + description: channel6 event id register + addressOffset: 72 + size: 32 + fields: + - name: CH6_EVT_ID + description: ch6_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH6_TASK_ID + description: channel6 task id register + addressOffset: 76 + size: 32 + fields: + - name: CH6_TASK_ID + description: ch6_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH7_EVT_ID + description: channel7 event id register + addressOffset: 80 + size: 32 + fields: + - name: CH7_EVT_ID + description: ch7_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH7_TASK_ID + description: channel7 task id register + addressOffset: 84 + size: 32 + fields: + - name: CH7_TASK_ID + description: ch7_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH8_EVT_ID + description: channel8 event id register + addressOffset: 88 + size: 32 + fields: + - name: CH8_EVT_ID + description: ch8_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH8_TASK_ID + description: channel8 task id register + addressOffset: 92 + size: 32 + fields: + - name: CH8_TASK_ID + description: ch8_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH9_EVT_ID + description: channel9 event id register + addressOffset: 96 + size: 32 + fields: + - name: CH9_EVT_ID + description: ch9_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH9_TASK_ID + description: channel9 task id register + addressOffset: 100 + size: 32 + fields: + - name: CH9_TASK_ID + description: ch9_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH10_EVT_ID + description: channel10 event id register + addressOffset: 104 + size: 32 + fields: + - name: CH10_EVT_ID + description: ch10_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH10_TASK_ID + description: channel10 task id register + addressOffset: 108 + size: 32 + fields: + - name: CH10_TASK_ID + description: ch10_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH11_EVT_ID + description: channel11 event id register + addressOffset: 112 + size: 32 + fields: + - name: CH11_EVT_ID + description: ch11_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH11_TASK_ID + description: channel11 task id register + addressOffset: 116 + size: 32 + fields: + - name: CH11_TASK_ID + description: ch11_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH12_EVT_ID + description: channel12 event id register + addressOffset: 120 + size: 32 + fields: + - name: CH12_EVT_ID + description: ch12_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH12_TASK_ID + description: channel12 task id register + addressOffset: 124 + size: 32 + fields: + - name: CH12_TASK_ID + description: ch12_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH13_EVT_ID + description: channel13 event id register + addressOffset: 128 + size: 32 + fields: + - name: CH13_EVT_ID + description: ch13_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH13_TASK_ID + description: channel13 task id register + addressOffset: 132 + size: 32 + fields: + - name: CH13_TASK_ID + description: ch13_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH14_EVT_ID + description: channel14 event id register + addressOffset: 136 + size: 32 + fields: + - name: CH14_EVT_ID + description: ch14_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH14_TASK_ID + description: channel14 task id register + addressOffset: 140 + size: 32 + fields: + - name: CH14_TASK_ID + description: ch14_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH15_EVT_ID + description: channel15 event id register + addressOffset: 144 + size: 32 + fields: + - name: CH15_EVT_ID + description: ch15_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH15_TASK_ID + description: channel15 task id register + addressOffset: 148 + size: 32 + fields: + - name: CH15_TASK_ID + description: ch15_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH16_EVT_ID + description: channel16 event id register + addressOffset: 152 + size: 32 + fields: + - name: CH16_EVT_ID + description: ch16_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH16_TASK_ID + description: channel16 task id register + addressOffset: 156 + size: 32 + fields: + - name: CH16_TASK_ID + description: ch16_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH17_EVT_ID + description: channel17 event id register + addressOffset: 160 + size: 32 + fields: + - name: CH17_EVT_ID + description: ch17_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH17_TASK_ID + description: channel17 task id register + addressOffset: 164 + size: 32 + fields: + - name: CH17_TASK_ID + description: ch17_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH18_EVT_ID + description: channel18 event id register + addressOffset: 168 + size: 32 + fields: + - name: CH18_EVT_ID + description: ch18_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH18_TASK_ID + description: channel18 task id register + addressOffset: 172 + size: 32 + fields: + - name: CH18_TASK_ID + description: ch18_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH19_EVT_ID + description: channel19 event id register + addressOffset: 176 + size: 32 + fields: + - name: CH19_EVT_ID + description: ch19_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH19_TASK_ID + description: channel19 task id register + addressOffset: 180 + size: 32 + fields: + - name: CH19_TASK_ID + description: ch19_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH20_EVT_ID + description: channel20 event id register + addressOffset: 184 + size: 32 + fields: + - name: CH20_EVT_ID + description: ch20_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH20_TASK_ID + description: channel20 task id register + addressOffset: 188 + size: 32 + fields: + - name: CH20_TASK_ID + description: ch20_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH21_EVT_ID + description: channel21 event id register + addressOffset: 192 + size: 32 + fields: + - name: CH21_EVT_ID + description: ch21_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH21_TASK_ID + description: channel21 task id register + addressOffset: 196 + size: 32 + fields: + - name: CH21_TASK_ID + description: ch21_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH22_EVT_ID + description: channel22 event id register + addressOffset: 200 + size: 32 + fields: + - name: CH22_EVT_ID + description: ch22_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH22_TASK_ID + description: channel22 task id register + addressOffset: 204 + size: 32 + fields: + - name: CH22_TASK_ID + description: ch22_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH23_EVT_ID + description: channel23 event id register + addressOffset: 208 + size: 32 + fields: + - name: CH23_EVT_ID + description: ch23_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH23_TASK_ID + description: channel23 task id register + addressOffset: 212 + size: 32 + fields: + - name: CH23_TASK_ID + description: ch23_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH24_EVT_ID + description: channel24 event id register + addressOffset: 216 + size: 32 + fields: + - name: CH24_EVT_ID + description: ch24_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH24_TASK_ID + description: channel24 task id register + addressOffset: 220 + size: 32 + fields: + - name: CH24_TASK_ID + description: ch24_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH25_EVT_ID + description: channel25 event id register + addressOffset: 224 + size: 32 + fields: + - name: CH25_EVT_ID + description: ch25_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH25_TASK_ID + description: channel25 task id register + addressOffset: 228 + size: 32 + fields: + - name: CH25_TASK_ID + description: ch25_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH26_EVT_ID + description: channel26 event id register + addressOffset: 232 + size: 32 + fields: + - name: CH26_EVT_ID + description: ch26_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH26_TASK_ID + description: channel26 task id register + addressOffset: 236 + size: 32 + fields: + - name: CH26_TASK_ID + description: ch26_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH27_EVT_ID + description: channel27 event id register + addressOffset: 240 + size: 32 + fields: + - name: CH27_EVT_ID + description: ch27_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH27_TASK_ID + description: channel27 task id register + addressOffset: 244 + size: 32 + fields: + - name: CH27_TASK_ID + description: ch27_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH28_EVT_ID + description: channel28 event id register + addressOffset: 248 + size: 32 + fields: + - name: CH28_EVT_ID + description: ch28_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH28_TASK_ID + description: channel28 task id register + addressOffset: 252 + size: 32 + fields: + - name: CH28_TASK_ID + description: ch28_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH29_EVT_ID + description: channel29 event id register + addressOffset: 256 + size: 32 + fields: + - name: CH29_EVT_ID + description: ch29_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH29_TASK_ID + description: channel29 task id register + addressOffset: 260 + size: 32 + fields: + - name: CH29_TASK_ID + description: ch29_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH30_EVT_ID + description: channel30 event id register + addressOffset: 264 + size: 32 + fields: + - name: CH30_EVT_ID + description: ch30_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH30_TASK_ID + description: channel30 task id register + addressOffset: 268 + size: 32 + fields: + - name: CH30_TASK_ID + description: ch30_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH31_EVT_ID + description: channel31 event id register + addressOffset: 272 + size: 32 + fields: + - name: CH31_EVT_ID + description: ch31_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH31_TASK_ID + description: channel31 task id register + addressOffset: 276 + size: 32 + fields: + - name: CH31_TASK_ID + description: ch31_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH32_EVT_ID + description: channel32 event id register + addressOffset: 280 + size: 32 + fields: + - name: CH32_EVT_ID + description: ch32_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH32_TASK_ID + description: channel32 task id register + addressOffset: 284 + size: 32 + fields: + - name: CH32_TASK_ID + description: ch32_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH33_EVT_ID + description: channel33 event id register + addressOffset: 288 + size: 32 + fields: + - name: CH33_EVT_ID + description: ch33_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH33_TASK_ID + description: channel33 task id register + addressOffset: 292 + size: 32 + fields: + - name: CH33_TASK_ID + description: ch33_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH34_EVT_ID + description: channel34 event id register + addressOffset: 296 + size: 32 + fields: + - name: CH34_EVT_ID + description: ch34_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH34_TASK_ID + description: channel34 task id register + addressOffset: 300 + size: 32 + fields: + - name: CH34_TASK_ID + description: ch34_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH35_EVT_ID + description: channel35 event id register + addressOffset: 304 + size: 32 + fields: + - name: CH35_EVT_ID + description: ch35_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH35_TASK_ID + description: channel35 task id register + addressOffset: 308 + size: 32 + fields: + - name: CH35_TASK_ID + description: ch35_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH36_EVT_ID + description: channel36 event id register + addressOffset: 312 + size: 32 + fields: + - name: CH36_EVT_ID + description: ch36_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH36_TASK_ID + description: channel36 task id register + addressOffset: 316 + size: 32 + fields: + - name: CH36_TASK_ID + description: ch36_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH37_EVT_ID + description: channel37 event id register + addressOffset: 320 + size: 32 + fields: + - name: CH37_EVT_ID + description: ch37_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH37_TASK_ID + description: channel37 task id register + addressOffset: 324 + size: 32 + fields: + - name: CH37_TASK_ID + description: ch37_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH38_EVT_ID + description: channel38 event id register + addressOffset: 328 + size: 32 + fields: + - name: CH38_EVT_ID + description: ch38_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH38_TASK_ID + description: channel38 task id register + addressOffset: 332 + size: 32 + fields: + - name: CH38_TASK_ID + description: ch38_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH39_EVT_ID + description: channel39 event id register + addressOffset: 336 + size: 32 + fields: + - name: CH39_EVT_ID + description: ch39_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH39_TASK_ID + description: channel39 task id register + addressOffset: 340 + size: 32 + fields: + - name: CH39_TASK_ID + description: ch39_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH40_EVT_ID + description: channel40 event id register + addressOffset: 344 + size: 32 + fields: + - name: CH40_EVT_ID + description: ch40_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH40_TASK_ID + description: channel40 task id register + addressOffset: 348 + size: 32 + fields: + - name: CH40_TASK_ID + description: ch40_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH41_EVT_ID + description: channel41 event id register + addressOffset: 352 + size: 32 + fields: + - name: CH41_EVT_ID + description: ch41_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH41_TASK_ID + description: channel41 task id register + addressOffset: 356 + size: 32 + fields: + - name: CH41_TASK_ID + description: ch41_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH42_EVT_ID + description: channel42 event id register + addressOffset: 360 + size: 32 + fields: + - name: CH42_EVT_ID + description: ch42_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH42_TASK_ID + description: channel42 task id register + addressOffset: 364 + size: 32 + fields: + - name: CH42_TASK_ID + description: ch42_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH43_EVT_ID + description: channel43 event id register + addressOffset: 368 + size: 32 + fields: + - name: CH43_EVT_ID + description: ch43_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH43_TASK_ID + description: channel43 task id register + addressOffset: 372 + size: 32 + fields: + - name: CH43_TASK_ID + description: ch43_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH44_EVT_ID + description: channel44 event id register + addressOffset: 376 + size: 32 + fields: + - name: CH44_EVT_ID + description: ch44_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH44_TASK_ID + description: channel44 task id register + addressOffset: 380 + size: 32 + fields: + - name: CH44_TASK_ID + description: ch44_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH45_EVT_ID + description: channel45 event id register + addressOffset: 384 + size: 32 + fields: + - name: CH45_EVT_ID + description: ch45_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH45_TASK_ID + description: channel45 task id register + addressOffset: 388 + size: 32 + fields: + - name: CH45_TASK_ID + description: ch45_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH46_EVT_ID + description: channel46 event id register + addressOffset: 392 + size: 32 + fields: + - name: CH46_EVT_ID + description: ch46_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH46_TASK_ID + description: channel46 task id register + addressOffset: 396 + size: 32 + fields: + - name: CH46_TASK_ID + description: ch46_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH47_EVT_ID + description: channel47 event id register + addressOffset: 400 + size: 32 + fields: + - name: CH47_EVT_ID + description: ch47_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH47_TASK_ID + description: channel47 task id register + addressOffset: 404 + size: 32 + fields: + - name: CH47_TASK_ID + description: ch47_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH48_EVT_ID + description: channel48 event id register + addressOffset: 408 + size: 32 + fields: + - name: CH48_EVT_ID + description: ch48_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH48_TASK_ID + description: channel48 task id register + addressOffset: 412 + size: 32 + fields: + - name: CH48_TASK_ID + description: ch48_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH49_EVT_ID + description: channel49 event id register + addressOffset: 416 + size: 32 + fields: + - name: CH49_EVT_ID + description: ch49_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH49_TASK_ID + description: channel49 task id register + addressOffset: 420 + size: 32 + fields: + - name: CH49_TASK_ID + description: ch49_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CLK_EN + description: etm clock enable register + addressOffset: 424 + size: 32 + fields: + - name: CLK_EN + description: clock enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: etm date register + addressOffset: 428 + size: 32 + resetValue: 35664018 + fields: + - name: DATE + description: date + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SPI0 + description: SPI (Serial Peripheral Interface) Controller 0 + groupName: SPI0 + baseAddress: 1610620928 + addressBlock: + - offset: 0 + size: 312 + usage: registers + registers: + - register: + name: SPI_MEM_CMD + description: SPI0 FSM status register + addressOffset: 0 + size: 32 + fields: + - name: SPI_MEM_MST_ST + description: "The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state." + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: SPI_MEM_SLV_ST + description: "The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state." + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: SPI_MEM_USR + description: "SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 18 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_CTRL + description: SPI0 control register. + addressOffset: 8 + size: 32 + resetValue: 2150375436 + fields: + - name: SPI_MEM_WDUMMY_DQS_ALWAYS_OUT + description: "In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_MEM_WDUMMY_ALWAYS_OUT + description: "In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDUMMY_RIN + description: "In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDUMMY_WOUT + description: "In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDOUT_OCT + description: "Apply 8 signals during write-data phase 1:enable 0: disable" + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SPI_MEM_FDIN_OCT + description: "Apply 8 signals during read-data phase 1:enable 0: disable" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SPI_MEM_FADDR_OCT + description: "Apply 8 signals during address phase 1:enable 0: disable" + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SPI_MEM_FCMD_QUAD + description: "Apply 4 signals during command phase 1:enable 0: disable" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FCMD_OCT + description: "Apply 8 signals during command phase 1:enable 0: disable" + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SPI_MEM_FASTRD_MODE + description: "This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FREAD_DUAL + description: "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SPI_MEM_Q_POL + description: "The bit is used to set MISO line polarity, 1: high 0, low" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SPI_MEM_D_POL + description: "The bit is used to set MOSI line polarity, 1: high 0, low" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FREAD_QUAD + description: "In the read operations read-data phase apply 4 signals. 1: enable 0: disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WP + description: "Write protect signal output when SPI is idle. 1: output high, 0: output low." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FREAD_DIO + description: "In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FREAD_QIO + description: "In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DQS_IE_ALWAYS_ON + description: "When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others." + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: SPI_MEM_DATA_IE_ALWAYS_ON + description: "When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_CTRL1 + description: SPI0 control1 register. + addressOffset: 12 + size: 32 + resetValue: 685768704 + fields: + - name: SPI_MEM_CLK_MODE + description: "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SPI_AR_SIZE0_1_SUPPORT_EN + description: "1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_AW_SIZE0_1_SUPPORT_EN + description: "1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SPI_AXI_RDATA_BACK_FAST + description: "1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available." + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: SPI_MEM_RRESP_ECC_ERR_EN + description: "1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AR_SPLICE_EN + description: Set this bit to enable AXI Read Splice-transfer. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: SPI_MEM_AW_SPLICE_EN + description: Set this bit to enable AXI Write Splice-transfer. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: SPI_MEM_RAM0_EN + description: "When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be accessed at the same time." + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: SPI_MEM_DUAL_RAM_EN + description: "Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time." + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SPI_MEM_FAST_WRITE_EN + description: "Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in tx_bus_fifo_l2." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SPI_MEM_RXFIFO_RST + description: The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI. Set this bit to reset these FIFO. + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: SPI_MEM_TXFIFO_RST + description: The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_CTRL2 + description: SPI0 control2 register. + addressOffset: 16 + size: 32 + resetValue: 11297 + fields: + - name: SPI_MEM_CS_SETUP_TIME + description: "(cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit." + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: SPI_MEM_CS_HOLD_TIME + description: "SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit." + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: SPI_MEM_ECC_CS_HOLD_TIME + description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash. + bitOffset: 10 + bitWidth: 3 + access: read-only + - name: SPI_MEM_ECC_SKIP_PAGE_CORNER + description: "1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash." + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SPI_MEM_ECC_16TO18_BYTE_EN + description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SPLIT_TRANS_EN + description: "Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not." + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: SPI_MEM_CS_HOLD_DELAY + description: "These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles." + bitOffset: 25 + bitWidth: 6 + access: read-write + - name: SPI_MEM_SYNC_RESET + description: The spi0_mst_st and spi0_slv_st will be reset. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_CLOCK + description: SPI clock division control register. + addressOffset: 20 + size: 32 + resetValue: 196867 + fields: + - name: SPI_MEM_CLKCNT_L + description: In the master mode it must be equal to spi_mem_clkcnt_N. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SPI_MEM_CLKCNT_H + description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SPI_MEM_CLKCNT_N + description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SPI_MEM_CLK_EQU_SYSCLK + description: "1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_USER + description: SPI0 user register. + addressOffset: 24 + size: 32 + fields: + - name: SPI_MEM_CS_HOLD + description: "spi cs keep low when spi is in done phase. 1: enable 0: disable." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CS_SETUP + description: "spi cs is enable when spi is in prepare phase. 1: enable 0: disable." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CK_OUT_EDGE + description: The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_DUMMY_IDLE + description: spi clock is disable in dummy phase when the bit is enable. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_DUMMY + description: This bit enable the dummy phase of an operation. + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_USER1 + description: SPI0 user1 register. + addressOffset: 28 + size: 32 + resetValue: 1543503943 + fields: + - name: SPI_MEM_USR_DUMMY_CYCLELEN + description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: SPI_MEM_USR_DBYTELEN + description: SPI0 USR_CMD read or write data byte length -1 + bitOffset: 6 + bitWidth: 3 + access: read-only + - name: SPI_MEM_USR_ADDR_BITLEN + description: The length in bits of address phase. The register value shall be (bit_num-1). + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: SPI_MEM_USER2 + description: SPI0 user2 register. + addressOffset: 32 + size: 32 + resetValue: 1879048192 + fields: + - name: SPI_MEM_USR_COMMAND_VALUE + description: The value of command. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SPI_MEM_USR_COMMAND_BITLEN + description: The length in bits of command phase. The register value shall be (bit_num-1) + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: SPI_MEM_RD_STATUS + description: SPI0 read control register. + addressOffset: 44 + size: 32 + fields: + - name: SPI_MEM_WB_MODE + description: Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: SPI_MEM_MISC + description: SPI0 misc register + addressOffset: 52 + size: 32 + fields: + - name: SPI_MEM_FSUB_PIN + description: "For SPI0, flash is connected to SUBPINs." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SSUB_PIN + description: "For SPI0, sram is connected to SUBPINs." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SPI_MEM_CK_IDLE_EDGE + description: "1: SPI_CLK line is high when idle 0: spi clk line is low when idle" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CS_KEEP_ACTIVE + description: SPI_CS line keep low when the bit is set. + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_CACHE_FCTRL + description: SPI0 bit mode control register. + addressOffset: 60 + size: 32 + resetValue: 3221225472 + fields: + - name: SPI_MEM_AXI_REQ_EN + description: "For SPI0, AXI master access enable, 1: enable, 0:disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CACHE_USR_ADDR_4BYTE + description: "For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CACHE_FLASH_USR_CMD + description: "For SPI0, cache read flash for user define command, 1: enable, 0:disable." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDIN_DUAL + description: "For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDOUT_DUAL + description: "For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FADDR_DUAL + description: "For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDIN_QUAD + description: "For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDOUT_QUAD + description: "For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FADDR_QUAD + description: "For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SPI_SAME_AW_AR_ADDR_CHK_EN + description: Set this bit to check AXI read/write the same address region. + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: SPI_CLOSE_AXI_INF_EN + description: "Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_CACHE_SCTRL + description: SPI0 external RAM control register + addressOffset: 64 + size: 32 + resetValue: 5619824 + fields: + - name: SPI_MEM_CACHE_USR_SADDR_4BYTE + description: "For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_MEM_USR_SRAM_DIO + description: "For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable" + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SPI_MEM_USR_SRAM_QIO + description: "For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable" + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SPI_MEM_USR_WR_SRAM_DUMMY + description: "For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SPI_MEM_USR_RD_SRAM_DUMMY + description: "For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SPI_MEM_CACHE_SRAM_USR_RCMD + description: "For SPI0, In the external RAM mode cache read external RAM for user define command." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SRAM_RDUMMY_CYCLELEN + description: "For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1)." + bitOffset: 6 + bitWidth: 6 + access: read-only + - name: SPI_MEM_SRAM_ADDR_BITLEN + description: "For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1)." + bitOffset: 14 + bitWidth: 6 + access: read-only + - name: SPI_MEM_CACHE_SRAM_USR_WCMD + description: "For SPI0, In the external RAM mode cache write sram for user define command" + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SRAM_OCT + description: reserved + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SRAM_WDUMMY_CYCLELEN + description: "For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1)." + bitOffset: 22 + bitWidth: 6 + access: read-only + - register: + name: SPI_MEM_SRAM_CMD + description: SPI0 external RAM mode control register + addressOffset: 68 + size: 32 + resetValue: 3225419776 + fields: + - name: SPI_MEM_SCLK_MODE + description: "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on." + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: SPI_MEM_SWB_MODE + description: Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit. + bitOffset: 2 + bitWidth: 8 + access: read-only + - name: SPI_MEM_SDIN_DUAL + description: "For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio." + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SDOUT_DUAL + description: "For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio." + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SADDR_DUAL + description: "For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio." + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SDIN_QUAD + description: "For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio." + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SDOUT_QUAD + description: "For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio." + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SADDR_QUAD + description: "For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio." + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SCMD_QUAD + description: "For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio." + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SDIN_OCT + description: "For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable." + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SDOUT_OCT + description: "For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable." + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SADDR_OCT + description: "For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable." + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SCMD_OCT + description: "For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable." + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SDUMMY_RIN + description: "In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SDUMMY_WOUT + description: "In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller." + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT + description: "In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller." + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_WDUMMY_ALWAYS_OUT + description: "In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller." + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_DQS_IE_ALWAYS_ON + description: "When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others." + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_DATA_IE_ALWAYS_ON + description: "When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_SRAM_DRD_CMD + description: SPI0 external RAM DDR read command control register + addressOffset: 72 + size: 32 + fields: + - name: SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE + description: "For SPI0,When cache mode is enable it is the read command value of command phase for sram." + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN + description: "For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1)." + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: SPI_MEM_SRAM_DWR_CMD + description: SPI0 external RAM DDR write command control register + addressOffset: 76 + size: 32 + fields: + - name: SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE + description: "For SPI0,When cache mode is enable it is the write command value of command phase for sram." + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN + description: "For SPI0,When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1)." + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: SPI_MEM_SRAM_CLK + description: SPI0 external RAM clock control register + addressOffset: 80 + size: 32 + resetValue: 196867 + fields: + - name: SPI_MEM_SCLKCNT_L + description: "For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N." + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: SPI_MEM_SCLKCNT_H + description: "For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1)." + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: SPI_MEM_SCLKCNT_N + description: "For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)" + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: SPI_MEM_SCLK_EQU_SYSCLK + description: "For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_FSM + description: SPI0 FSM status register + addressOffset: 84 + size: 32 + resetValue: 512 + fields: + - name: SPI_MEM_LOCK_DELAY_TIME + description: "The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1." + bitOffset: 7 + bitWidth: 5 + access: read-write + - register: + name: SPI_MEM_INT_ENA + description: SPI0 interrupt enable register + addressOffset: 192 + size: 32 + fields: + - name: SPI_MEM_SLV_ST_END_INT_ENA + description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_MST_ST_END_INT_ENA + description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_ECC_ERR_INT_ENA + description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SPI_MEM_PMS_REJECT_INT_ENA + description: The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AXI_RADDR_ERR_INT_ENA + description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA + description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SPI_MEM_AXI_WADDR_ERR_INT__ENA + description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_INT_CLR + description: SPI0 interrupt clear register + addressOffset: 196 + size: 32 + fields: + - name: SPI_MEM_SLV_ST_END_INT_CLR + description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SPI_MEM_MST_ST_END_INT_CLR + description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SPI_MEM_ECC_ERR_INT_CLR + description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SPI_MEM_PMS_REJECT_INT_CLR + description: The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: SPI_MEM_AXI_RADDR_ERR_INT_CLR + description: The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR + description: The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SPI_MEM_AXI_WADDR_ERR_INT_CLR + description: The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_INT_RAW + description: SPI0 interrupt raw register + addressOffset: 200 + size: 32 + fields: + - name: SPI_MEM_SLV_ST_END_INT_RAW + description: "The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_MST_ST_END_INT_RAW + description: "The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_ECC_ERR_INT_RAW + description: "The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SPI_MEM_PMS_REJECT_INT_RAW + description: "The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AXI_RADDR_ERR_INT_RAW + description: "The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW + description: "The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SPI_MEM_AXI_WADDR_ERR_INT_RAW + description: "The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others." + bitOffset: 9 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_INT_ST + description: SPI0 interrupt status register + addressOffset: 204 + size: 32 + fields: + - name: SPI_MEM_SLV_ST_END_INT_ST + description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SPI_MEM_MST_ST_END_INT_ST + description: The status bit for SPI_MEM_MST_ST_END_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SPI_MEM_ECC_ERR_INT_ST + description: The status bit for SPI_MEM_ECC_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SPI_MEM_PMS_REJECT_INT_ST + description: The status bit for SPI_MEM_PMS_REJECT_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SPI_MEM_AXI_RADDR_ERR_INT_ST + description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SPI_MEM_AXI_WR_FLASH_ERR_INT_ST + description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SPI_MEM_AXI_WADDR_ERR_INT_ST + description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_DDR + description: SPI0 flash DDR mode control register + addressOffset: 212 + size: 32 + resetValue: 12320 + fields: + - name: SPI_FMEM_DDR_EN + description: "1: in DDR mode, 0 in SDR mode" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_VAR_DUMMY + description: Set the bit to enable variable dummy cycle in spi DDR mode. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_DDR_RDAT_SWP + description: Set the bit to reorder rx data of the word in spi DDR mode. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_DDR_WDAT_SWP + description: Set the bit to reorder tx data of the word in spi DDR mode. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_DDR_CMD_DIS + description: the bit is used to disable dual edge in command phase when DDR mode. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_OUTMINBYTELEN + description: It is the minimum output data length in the panda device. + bitOffset: 5 + bitWidth: 7 + access: read-only + - name: SPI_FMEM_TX_DDR_MSK_EN + description: "Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash." + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_RX_DDR_MSK_EN + description: "Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash." + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_USR_DDR_DQS_THD + description: The delay number of data strobe which from memory based on SPI clock. + bitOffset: 14 + bitWidth: 7 + access: read-only + - name: SPI_FMEM_DDR_DQS_LOOP + description: "1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS." + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_CLK_DIFF_EN + description: "Set this bit to enable the differential SPI_CLK#." + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_DQS_CA_IN + description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_HYPERBUS_DUMMY_2X + description: "Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram." + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_CLK_DIFF_INV + description: Set this bit to invert SPI_DIFF when accesses to flash. . + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_OCTA_RAM_ADDR + description: "Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}." + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_HYPERBUS_CA + description: "Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}." + bitOffset: 30 + bitWidth: 1 + access: read-only + - register: + name: SPI_SMEM_DDR + description: SPI0 external RAM DDR mode control register + addressOffset: 216 + size: 32 + resetValue: 12320 + fields: + - name: EN + description: "1: in DDR mode, 0 in SDR mode" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_VAR_DUMMY + description: Set the bit to enable variable dummy cycle in spi DDR mode. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RDAT_SWP + description: Set the bit to reorder rx data of the word in spi DDR mode. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: WDAT_SWP + description: Set the bit to reorder tx data of the word in spi DDR mode. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: CMD_DIS + description: the bit is used to disable dual edge in command phase when DDR mode. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_OUTMINBYTELEN + description: It is the minimum output data length in the DDR psram. + bitOffset: 5 + bitWidth: 7 + access: read-only + - name: SPI_SMEM_TX_DDR_MSK_EN + description: "Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM." + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_RX_DDR_MSK_EN + description: "Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM." + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_USR_DDR_DQS_THD + description: The delay number of data strobe which from memory based on SPI clock. + bitOffset: 14 + bitWidth: 7 + access: read-only + - name: DQS_LOOP + description: "1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS." + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_CLK_DIFF_EN + description: "Set this bit to enable the differential SPI_CLK#." + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_DQS_CA_IN + description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_HYPERBUS_DUMMY_2X + description: "Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram." + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_CLK_DIFF_INV + description: Set this bit to invert SPI_DIFF when accesses to external RAM. . + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_OCTA_RAM_ADDR + description: "Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}." + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_HYPERBUS_CA + description: "Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}." + bitOffset: 30 + bitWidth: 1 + access: read-only + - register: + dim: 4 + dimIncrement: 4 + name: SPI_FMEM_PMS%s_ATTR + description: MSPI flash ACE section %s attribute register + addressOffset: 256 + size: 32 + resetValue: 3 + fields: + - name: SPI_FMEM_PMS_RD_ATTR + description: "1: SPI1 flash ACE section %s read accessible. 0: Not allowed." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_PMS_WR_ATTR + description: "1: SPI1 flash ACE section %s write accessible. 0: Not allowed." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_PMS_ECC + description: "SPI1 flash ACE section %s ECC mode, 1: enable ECC mode. 0: Disable it. The flash ACE section %s is configured by registers SPI_FMEM_PMS%s_ADDR_REG and SPI_FMEM_PMS%s_SIZE_REG." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: SPI_FMEM_PMS%s_ADDR + description: SPI1 flash ACE section %s start address register + addressOffset: 272 + size: 32 + fields: + - name: S + description: SPI1 flash ACE section %s start address value + bitOffset: 0 + bitWidth: 26 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: SPI_FMEM_PMS%s_SIZE + description: SPI1 flash ACE section %s start address register + addressOffset: 288 + size: 32 + resetValue: 4096 + fields: + - name: SPI_FMEM_PMS_SIZE + description: "SPI1 flash ACE section %s address region is (SPI_FMEM_PMS%s_ADDR_S, SPI_FMEM_PMS%s_ADDR_S + SPI_FMEM_PMS%s_SIZE)" + bitOffset: 0 + bitWidth: 14 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: SPI_SMEM_PMS%s_ATTR + description: SPI1 flash ACE section %s start address register + addressOffset: 304 + size: 32 + resetValue: 3 + fields: + - name: SPI_SMEM_PMS_RD_ATTR + description: "1: SPI1 external RAM ACE section %s read accessible. 0: Not allowed." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_PMS_WR_ATTR + description: "1: SPI1 external RAM ACE section %s write accessible. 0: Not allowed." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_PMS_ECC + description: "SPI1 external RAM ACE section %s ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section %s is configured by registers SPI_SMEM_PMS%s_ADDR_REG and SPI_SMEM_PMS%s_SIZE_REG." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: SPI_SMEM_PMS%s_ADDR + description: SPI1 external RAM ACE section %s start address register + addressOffset: 320 + size: 32 + fields: + - name: S + description: SPI1 external RAM ACE section %s start address value + bitOffset: 0 + bitWidth: 26 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: SPI_SMEM_PMS%s_SIZE + description: SPI1 external RAM ACE section %s start address register + addressOffset: 336 + size: 32 + resetValue: 4096 + fields: + - name: SPI_SMEM_PMS_SIZE + description: "SPI1 external RAM ACE section %s address region is (SPI_SMEM_PMS%s_ADDR_S, SPI_SMEM_PMS%s_ADDR_S + SPI_SMEM_PMS%s_SIZE)" + bitOffset: 0 + bitWidth: 14 + access: read-write + - register: + name: SPI_MEM_PMS_REJECT + description: SPI1 access reject register + addressOffset: 356 + size: 32 + fields: + - name: SPI_MEM_REJECT_ADDR + description: This bits show the first SPI1 access error address. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + bitOffset: 0 + bitWidth: 26 + access: read-only + - name: SPI_MEM_PM_EN + description: Set this bit to enable SPI0/1 transfer permission control function. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI_MEM_PMS_LD + description: "1: SPI1 write access error. 0: No write access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set." + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SPI_MEM_PMS_ST + description: "1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set." + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: SPI_MEM_PMS_MULTI_HIT + description: "1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set." + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: SPI_MEM_PMS_IVD + description: "1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_ECC_CTRL + description: MSPI ECC control register + addressOffset: 360 + size: 32 + resetValue: 16797696 + fields: + - name: SPI_FMEM_ECC_ERR_INT_NUM + description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. + bitOffset: 11 + bitWidth: 6 + access: read-only + - name: SPI_FMEM_ECC_ERR_INT_EN + description: Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_PAGE_SIZE + description: "Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes." + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: SPI_FMEM_ECC_ADDR_EN + description: "Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1." + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SPI_MEM_USR_ECC_ADDR_EN + description: Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN + description: "1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information." + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: SPI_MEM_ECC_ERR_BITS + description: "Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7)" + bitOffset: 25 + bitWidth: 7 + access: read-only + - register: + name: SPI_MEM_ECC_ERR_ADDR + description: MSPI ECC error address register + addressOffset: 364 + size: 32 + fields: + - name: SPI_MEM_ECC_ERR_ADDR + description: This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + bitOffset: 0 + bitWidth: 26 + access: read-only + - name: SPI_MEM_ECC_ERR_CNT + description: This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + bitOffset: 26 + bitWidth: 6 + access: read-only + - register: + name: SPI_MEM_AXI_ERR_ADDR + description: SPI0 AXI request error address. + addressOffset: 368 + size: 32 + resetValue: 4227858432 + fields: + - name: SPI_MEM_AXI_ERR_ADDR + description: "This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set." + bitOffset: 0 + bitWidth: 26 + access: read-only + - name: SPI_MEM_ALL_FIFO_EMPTY + description: "The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others." + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: SPI_RDATA_AFIFO_REMPTY + description: "1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending." + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: SPI_RADDR_AFIFO_REMPTY + description: "1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending." + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SPI_WDATA_AFIFO_REMPTY + description: "1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending." + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: SPI_WBLEN_AFIFO_REMPTY + description: "1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending." + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: SPI_ALL_AXI_TRANS_AFIFO_EMPTY + description: "This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: SPI_SMEM_ECC_CTRL + description: MSPI ECC control register + addressOffset: 372 + size: 32 + resetValue: 524288 + fields: + - name: SPI_SMEM_ECC_ERR_INT_EN + description: Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_PAGE_SIZE + description: "Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes." + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: SPI_SMEM_ECC_ADDR_EN + description: "Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1." + bitOffset: 20 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_TIMING_CALI + description: SPI0 flash timing calibration register + addressOffset: 384 + size: 32 + resetValue: 1 + fields: + - name: SPI_MEM_TIMING_CLK_ENA + description: The bit is used to enable timing adjust clock for all reading operations. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_TIMING_CALI + description: The bit is used to enable timing auto-calibration for all reading operations. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_EXTRA_DUMMY_CYCLELEN + description: add extra dummy spi clock cycle length for spi clock calibration. + bitOffset: 2 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DLL_TIMING_CALI + description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: UPDATE + description: "Set this bit to update delay mode, delay num and extra dummy in MSPI." + bitOffset: 6 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_DIN_MODE + description: MSPI flash input timing delay mode control register + addressOffset: 388 + size: 32 + fields: + - name: SPI_MEM_DIN0_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DIN1_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DIN2_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DIN3_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DIN4_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk" + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DIN5_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk" + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DIN6_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk" + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DIN7_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk" + bitOffset: 21 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DINS_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk" + bitOffset: 24 + bitWidth: 3 + access: read-write + - register: + name: SPI_MEM_DIN_NUM + description: MSPI flash input timing delay number control register + addressOffset: 392 + size: 32 + fields: + - name: SPI_MEM_DIN0_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SPI_MEM_DIN1_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: SPI_MEM_DIN2_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: SPI_MEM_DIN3_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: SPI_MEM_DIN4_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: SPI_MEM_DIN5_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: SPI_MEM_DIN6_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: SPI_MEM_DIN7_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: SPI_MEM_DINS_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: SPI_MEM_DOUT_MODE + description: MSPI flash output timing adjustment control register + addressOffset: 396 + size: 32 + fields: + - name: SPI_MEM_DOUT0_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DOUT1_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DOUT2_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DOUT3_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DOUT4_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DOUT5_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DOUT6_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DOUT7_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DOUTS_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk" + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: SPI_SMEM_TIMING_CALI + description: MSPI external RAM timing calibration register + addressOffset: 400 + size: 32 + resetValue: 1 + fields: + - name: SPI_SMEM_TIMING_CLK_ENA + description: "For sram, the bit is used to enable timing adjust clock for all reading operations." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_TIMING_CALI + description: "For sram, the bit is used to enable timing auto-calibration for all reading operations." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_EXTRA_DUMMY_CYCLELEN + description: "For sram, add extra dummy spi clock cycle length for spi clock calibration." + bitOffset: 2 + bitWidth: 3 + access: read-only + - name: SPI_SMEM_DLL_TIMING_CALI + description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM. + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: SPI_SMEM_DIN_MODE + description: MSPI external RAM input timing delay mode control register + addressOffset: 404 + size: 32 + fields: + - name: SPI_SMEM_DIN0_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: SPI_SMEM_DIN1_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 3 + bitWidth: 3 + access: read-only + - name: SPI_SMEM_DIN2_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 6 + bitWidth: 3 + access: read-only + - name: SPI_SMEM_DIN3_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 9 + bitWidth: 3 + access: read-only + - name: SPI_SMEM_DIN4_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 12 + bitWidth: 3 + access: read-only + - name: SPI_SMEM_DIN5_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 15 + bitWidth: 3 + access: read-only + - name: SPI_SMEM_DIN6_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 18 + bitWidth: 3 + access: read-only + - name: SPI_SMEM_DIN7_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 21 + bitWidth: 3 + access: read-only + - name: SPI_SMEM_DINS_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 24 + bitWidth: 3 + access: read-only + - register: + name: SPI_SMEM_DIN_NUM + description: MSPI external RAM input timing delay number control register + addressOffset: 408 + size: 32 + fields: + - name: SPI_SMEM_DIN0_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: SPI_SMEM_DIN1_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 2 + bitWidth: 2 + access: read-only + - name: SPI_SMEM_DIN2_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 4 + bitWidth: 2 + access: read-only + - name: SPI_SMEM_DIN3_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: SPI_SMEM_DIN4_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 8 + bitWidth: 2 + access: read-only + - name: SPI_SMEM_DIN5_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 10 + bitWidth: 2 + access: read-only + - name: SPI_SMEM_DIN6_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 12 + bitWidth: 2 + access: read-only + - name: SPI_SMEM_DIN7_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 14 + bitWidth: 2 + access: read-only + - name: SPI_SMEM_DINS_NUM + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 16 + bitWidth: 2 + access: read-only + - register: + name: SPI_SMEM_DOUT_MODE + description: MSPI external RAM output timing adjustment control register + addressOffset: 412 + size: 32 + fields: + - name: SPI_SMEM_DOUT0_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_DOUT1_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_DOUT2_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_DOUT3_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_DOUT4_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_DOUT5_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_DOUT6_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_DOUT7_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_DOUTS_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: SPI_SMEM_AC + description: MSPI external RAM ECC and SPI CS timing control register + addressOffset: 416 + size: 32 + resetValue: 2147528836 + fields: + - name: SPI_SMEM_CS_SETUP + description: "For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_CS_HOLD + description: "For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_CS_SETUP_TIME + description: "For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit." + bitOffset: 2 + bitWidth: 5 + access: read-only + - name: SPI_SMEM_CS_HOLD_TIME + description: "For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit." + bitOffset: 7 + bitWidth: 5 + access: read-only + - name: SPI_SMEM_ECC_CS_HOLD_TIME + description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM. + bitOffset: 12 + bitWidth: 3 + access: read-only + - name: SPI_SMEM_ECC_SKIP_PAGE_CORNER + description: "1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM." + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_ECC_16TO18_BYTE_EN + description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: SPI_SMEM_CS_HOLD_DELAY + description: "These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles." + bitOffset: 25 + bitWidth: 6 + access: read-only + - name: SPI_SMEM_SPLIT_TRANS_EN + description: "Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_CLOCK_GATE + description: SPI0 clock gate register + addressOffset: 512 + size: 32 + resetValue: 1 + fields: + - name: SPI_CLK_EN + description: "Register clock gate enable signal. 1: Enable. 0: Disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_XTS_PLAIN_BASE + description: The base address of the memory that stores plaintext in Manual Encryption + addressOffset: 768 + size: 32 + fields: + - name: SPI_XTS_PLAIN + description: This field is only used to generate include file in c case. This field is useless. Please do not use this field. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_XTS_LINESIZE + description: Manual Encryption Line-Size register + addressOffset: 832 + size: 32 + fields: + - name: SPI_XTS_LINESIZE + description: "This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved." + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SPI_MEM_XTS_DESTINATION + description: Manual Encryption destination register + addressOffset: 836 + size: 32 + fields: + - name: SPI_XTS_DESTINATION + description: "This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_XTS_PHYSICAL_ADDRESS + description: Manual Encryption physical address register + addressOffset: 840 + size: 32 + fields: + - name: SPI_XTS_PHYSICAL_ADDRESS + description: This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter. + bitOffset: 0 + bitWidth: 26 + access: read-write + - register: + name: SPI_MEM_XTS_TRIGGER + description: Manual Encryption physical address register + addressOffset: 844 + size: 32 + fields: + - name: SPI_XTS_TRIGGER + description: "Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2." + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_XTS_RELEASE + description: Manual Encryption physical address register + addressOffset: 848 + size: 32 + fields: + - name: SPI_XTS_RELEASE + description: "Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3." + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_XTS_DESTROY + description: Manual Encryption physical address register + addressOffset: 852 + size: 32 + fields: + - name: SPI_XTS_DESTROY + description: "Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0." + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_XTS_STATE + description: Manual Encryption physical address register + addressOffset: 856 + size: 32 + fields: + - name: SPI_XTS_STATE + description: "This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi." + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: SPI_MEM_XTS_DATE + description: Manual Encryption version register + addressOffset: 860 + size: 32 + resetValue: 538972176 + fields: + - name: SPI_XTS_DATE + description: This bits stores the last modified-time of manual encryption feature. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: SPI_MEM_MMU_ITEM_CONTENT + description: MSPI-MMU item content register + addressOffset: 892 + size: 32 + resetValue: 892 + fields: + - name: SPI_MMU_ITEM_CONTENT + description: MSPI-MMU item content + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_MMU_ITEM_INDEX + description: MSPI-MMU item index register + addressOffset: 896 + size: 32 + fields: + - name: SPI_MMU_ITEM_INDEX + description: MSPI-MMU item index + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_MMU_POWER_CTRL + description: MSPI MMU power control register + addressOffset: 900 + size: 32 + resetValue: 320864260 + fields: + - name: SPI_MMU_MEM_FORCE_ON + description: Set this bit to enable mmu-memory clock force on + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MMU_MEM_FORCE_PD + description: Set this bit to force mmu-memory powerdown + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MMU_MEM_FORCE_PU + description: "Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MMU_PAGE_SIZE + description: "0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8" + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: SPI_MEM_AUX_CTRL + description: MMU PSRAM aux control register + bitOffset: 16 + bitWidth: 14 + access: read-only + - name: SPI_MEM_RDN_ENA + description: ECO register enable bit + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: SPI_MEM_RDN_RESULT + description: MSPI module clock domain and AXI clock domain ECO register result register + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_DPA_CTRL + description: SPI memory cryption DPA register + addressOffset: 904 + size: 32 + resetValue: 15 + fields: + - name: SPI_CRYPT_SECURITY_LEVEL + description: "Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SPI_CRYPT_CALC_D_DPA_EN + description: "Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_CRYPT_DPA_SELECT_REGISTER + description: "1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits." + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_REGISTERRND_ECO_HIGH + description: MSPI ECO high register + addressOffset: 1008 + size: 32 + resetValue: 892 + fields: + - name: SPI_MEM_REGISTERRND_ECO_HIGH + description: ECO high register + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SPI_MEM_REGISTERRND_ECO_LOW + description: MSPI ECO low register + addressOffset: 1012 + size: 32 + resetValue: 892 + fields: + - name: SPI_MEM_REGISTERRND_ECO_LOW + description: ECO low register + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SPI_MEM_DATE + description: SPI0 version control register + addressOffset: 1020 + size: 32 + resetValue: 35663920 + fields: + - name: SPI_MEM_DATE + description: SPI0 register version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SPI1 + description: SPI (Serial Peripheral Interface) Controller 1 + groupName: SPI1 + baseAddress: 1610625024 + addressBlock: + - offset: 0 + size: 172 + usage: registers + registers: + - register: + name: SPI_MEM_CMD + description: SPI1 memory command register + addressOffset: 0 + size: 32 + fields: + - name: SPI_MEM_MST_ST + description: The current status of SPI1 master FSM. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: SPI_MEM_SLV_ST + description: "The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state." + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: SPI_MEM_FLASH_PE + description: "In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR + description: "User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_HPM + description: "Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_RES + description: "This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_DP + description: "Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_CE + description: "Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_BE + description: "Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_SE + description: "Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PP + description: "Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_WRSR + description: "Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_RDSR + description: "Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_RDID + description: "Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_WRDI + description: "Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_WREN + description: "Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_READ + description: "Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_ADDR + description: SPI1 address register + addressOffset: 4 + size: 32 + fields: + - name: SPI_MEM_USR_ADDR_VALUE + description: "In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_CTRL + description: SPI1 control register. + addressOffset: 8 + size: 32 + resetValue: 2924556 + fields: + - name: SPI_MEM_FDUMMY_RIN + description: "In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDUMMY_WOUT + description: "In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDOUT_OCT + description: "Apply 8 signals during write-data phase 1:enable 0: disable" + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SPI_MEM_FDIN_OCT + description: "Apply 8 signals during read-data phase 1:enable 0: disable" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SPI_MEM_FADDR_OCT + description: "Apply 8 signals during address phase 1:enable 0: disable" + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SPI_MEM_FCMD_QUAD + description: "Apply 4 signals during command phase 1:enable 0: disable" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FCMD_OCT + description: "Apply 8 signals during command phase 1:enable 0: disable" + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SPI_MEM_FCS_CRC_EN + description: "For SPI1, initialize crc32 module before writing encrypted data to flash. Active low." + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SPI_MEM_TX_CRC_EN + description: "For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable" + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: SPI_MEM_FASTRD_MODE + description: "This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FREAD_DUAL + description: "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SPI_MEM_RESANDRES + description: "The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI_MEM_Q_POL + description: "The bit is used to set MISO line polarity, 1: high 0, low" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SPI_MEM_D_POL + description: "The bit is used to set MOSI line polarity, 1: high 0, low" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FREAD_QUAD + description: "In the read operations read-data phase apply 4 signals. 1: enable 0: disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WP + description: "Write protect signal output when SPI is idle. 1: output high, 0: output low." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WRSR_2B + description: "two bytes data will be written to status register when it is set. 1: enable 0: disable." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FREAD_DIO + description: "In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FREAD_QIO + description: "In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_CTRL1 + description: SPI1 control1 register. + addressOffset: 12 + size: 32 + resetValue: 4092 + fields: + - name: SPI_MEM_CLK_MODE + description: "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SPI_MEM_CS_HOLD_DLY_RES + description: "After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles." + bitOffset: 2 + bitWidth: 10 + access: read-write + - register: + name: SPI_MEM_CTRL2 + description: SPI1 control2 register. + addressOffset: 16 + size: 32 + fields: + - name: SPI_MEM_SYNC_RESET + description: The FSM will be reset. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_CLOCK + description: SPI1 clock division control register. + addressOffset: 20 + size: 32 + resetValue: 196867 + fields: + - name: SPI_MEM_CLKCNT_L + description: In the master mode it must be equal to spi_mem_clkcnt_N. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SPI_MEM_CLKCNT_H + description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SPI_MEM_CLKCNT_N + description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SPI_MEM_CLK_EQU_SYSCLK + description: reserved + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_USER + description: SPI1 user register. + addressOffset: 24 + size: 32 + resetValue: 2147483648 + fields: + - name: SPI_MEM_CK_OUT_EDGE + description: the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FWRITE_DUAL + description: In the write operations read-data phase apply 2 signals + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FWRITE_QUAD + description: In the write operations read-data phase apply 4 signals + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FWRITE_DIO + description: In the write operations address phase and read-data phase apply 2 signals. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FWRITE_QIO + description: In the write operations address phase and read-data phase apply 4 signals. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_MISO_HIGHPART + description: "read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: SPI_MEM_USR_MOSI_HIGHPART + description: "write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable." + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: SPI_MEM_USR_DUMMY_IDLE + description: SPI clock is disable in dummy phase when the bit is enable. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_MOSI + description: This bit enable the write-data phase of an operation. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_MISO + description: This bit enable the read-data phase of an operation. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_DUMMY + description: This bit enable the dummy phase of an operation. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_ADDR + description: This bit enable the address phase of an operation. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_COMMAND + description: This bit enable the command phase of an operation. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_USER1 + description: SPI1 user1 register. + addressOffset: 28 + size: 32 + resetValue: 1543503879 + fields: + - name: SPI_MEM_USR_DUMMY_CYCLELEN + description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: SPI_MEM_USR_ADDR_BITLEN + description: The length in bits of address phase. The register value shall be (bit_num-1). + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: SPI_MEM_USER2 + description: SPI1 user2 register. + addressOffset: 32 + size: 32 + resetValue: 1879048192 + fields: + - name: SPI_MEM_USR_COMMAND_VALUE + description: The value of command. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SPI_MEM_USR_COMMAND_BITLEN + description: The length in bits of command phase. The register value shall be (bit_num-1) + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: SPI_MEM_MOSI_DLEN + description: SPI1 send data bit length control register. + addressOffset: 36 + size: 32 + fields: + - name: SPI_MEM_USR_MOSI_DBITLEN + description: The length in bits of write-data. The register value shall be (bit_num-1). + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: SPI_MEM_MISO_DLEN + description: SPI1 receive data bit length control register. + addressOffset: 40 + size: 32 + fields: + - name: SPI_MEM_USR_MISO_DBITLEN + description: The length in bits of read-data. The register value shall be (bit_num-1). + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: SPI_MEM_RD_STATUS + description: SPI1 status register. + addressOffset: 44 + size: 32 + fields: + - name: SPI_MEM_STATUS + description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SPI_MEM_WB_MODE + description: Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: SPI_MEM_MISC + description: SPI1 misc register + addressOffset: 52 + size: 32 + resetValue: 2 + fields: + - name: SPI_MEM_CS0_DIS + description: "SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CS1_DIS + description: "SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CK_IDLE_EDGE + description: "1: spi clk line is high when idle 0: spi clk line is low when idle" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CS_KEEP_ACTIVE + description: spi cs line keep low when the bit is set. + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_TX_CRC + description: SPI1 TX CRC data register. + addressOffset: 56 + size: 32 + resetValue: 4294967295 + fields: + - name: DATA + description: "For SPI1, the value of crc32." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SPI_MEM_CACHE_FCTRL + description: SPI1 bit mode control register. + addressOffset: 60 + size: 32 + fields: + - name: SPI_MEM_CACHE_USR_ADDR_4BYTE + description: "For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDIN_DUAL + description: "For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDOUT_DUAL + description: "For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FADDR_DUAL + description: "For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDIN_QUAD + description: "For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDOUT_QUAD + description: "For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FADDR_QUAD + description: "For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_W0 + description: SPI1 memory data buffer0 + addressOffset: 88 + size: 32 + fields: + - name: SPI_MEM_BUF0 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W1 + description: SPI1 memory data buffer1 + addressOffset: 92 + size: 32 + fields: + - name: SPI_MEM_BUF1 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W2 + description: SPI1 memory data buffer2 + addressOffset: 96 + size: 32 + fields: + - name: SPI_MEM_BUF2 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W3 + description: SPI1 memory data buffer3 + addressOffset: 100 + size: 32 + fields: + - name: SPI_MEM_BUF3 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W4 + description: SPI1 memory data buffer4 + addressOffset: 104 + size: 32 + fields: + - name: SPI_MEM_BUF4 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W5 + description: SPI1 memory data buffer5 + addressOffset: 108 + size: 32 + fields: + - name: SPI_MEM_BUF5 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W6 + description: SPI1 memory data buffer6 + addressOffset: 112 + size: 32 + fields: + - name: SPI_MEM_BUF6 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W7 + description: SPI1 memory data buffer7 + addressOffset: 116 + size: 32 + fields: + - name: SPI_MEM_BUF7 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W8 + description: SPI1 memory data buffer8 + addressOffset: 120 + size: 32 + fields: + - name: SPI_MEM_BUF8 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W9 + description: SPI1 memory data buffer9 + addressOffset: 124 + size: 32 + fields: + - name: SPI_MEM_BUF9 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W10 + description: SPI1 memory data buffer10 + addressOffset: 128 + size: 32 + fields: + - name: SPI_MEM_BUF10 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W11 + description: SPI1 memory data buffer11 + addressOffset: 132 + size: 32 + fields: + - name: SPI_MEM_BUF11 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W12 + description: SPI1 memory data buffer12 + addressOffset: 136 + size: 32 + fields: + - name: SPI_MEM_BUF12 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W13 + description: SPI1 memory data buffer13 + addressOffset: 140 + size: 32 + fields: + - name: SPI_MEM_BUF13 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W14 + description: SPI1 memory data buffer14 + addressOffset: 144 + size: 32 + fields: + - name: SPI_MEM_BUF14 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W15 + description: SPI1 memory data buffer15 + addressOffset: 148 + size: 32 + fields: + - name: SPI_MEM_BUF15 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_FLASH_WAITI_CTRL + description: SPI1 wait idle control register + addressOffset: 152 + size: 32 + resetValue: 327681 + fields: + - name: SPI_MEM_WAITI_EN + description: "1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WAITI_DUMMY + description: The dummy phase enable when wait flash idle (RDSR) + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WAITI_ADDR_EN + description: "1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WAITI_ADDR_CYCLELEN + description: "When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared." + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: SPI_MEM_WAITI_CMD_2B + description: "1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WAITI_DUMMY_CYCLELEN + description: The dummy cycle length when wait flash idle(RDSR). + bitOffset: 10 + bitWidth: 6 + access: read-write + - name: SPI_MEM_WAITI_CMD + description: The command value to wait flash idle(RDSR). + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SPI_MEM_FLASH_SUS_CTRL + description: SPI1 flash suspend control register + addressOffset: 156 + size: 32 + resetValue: 134225920 + fields: + - name: SPI_MEM_FLASH_PER + description: "program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PES + description: "program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PER_WAIT_EN + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PES_WAIT_EN + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_PES_PER_EN + description: "Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PES_EN + description: Set this bit to enable Auto-suspending function. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_MEM_PESR_END_MSK + description: "The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]." + bitOffset: 6 + bitWidth: 16 + access: read-write + - name: SPI_FMEM_RD_SUS_2B + description: "1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SPI_MEM_PER_END_EN + description: "1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SPI_MEM_PES_END_EN + description: "1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SUS_TIMEOUT_CNT + description: "When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass." + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: SPI_MEM_FLASH_SUS_CMD + description: SPI1 flash suspend command register + addressOffset: 160 + size: 32 + resetValue: 357749 + fields: + - name: SPI_MEM_FLASH_PES_COMMAND + description: Program/Erase suspend command. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SPI_MEM_WAIT_PESR_COMMAND + description: Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SPI_MEM_SUS_STATUS + description: SPI1 flash suspend status register + addressOffset: 164 + size: 32 + resetValue: 2054815744 + fields: + - name: SPI_MEM_FLASH_SUS + description: "The status of flash suspend, only used in SPI1." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WAIT_PESR_CMD_2B + description: "1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_HPM_DLY_128 + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_RES_DLY_128 + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_DP_DLY_128 + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PER_DLY_128 + description: "Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PES_DLY_128 + description: "Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SPI0_LOCK_EN + description: "1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PESR_CMD_2B + description: "1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PER_COMMAND + description: Program/Erase resume command. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SPI_MEM_INT_ENA + description: SPI1 interrupt enable register + addressOffset: 192 + size: 32 + fields: + - name: SPI_MEM_PER_END_INT_ENA + description: The enable bit for SPI_MEM_PER_END_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_PES_END_INT_ENA + description: The enable bit for SPI_MEM_PES_END_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WPE_END_INT_ENA + description: The enable bit for SPI_MEM_WPE_END_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SLV_ST_END_INT_ENA + description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_MST_ST_END_INT_ENA + description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_BROWN_OUT_INT_ENA + description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_INT_CLR + description: SPI1 interrupt clear register + addressOffset: 196 + size: 32 + fields: + - name: SPI_MEM_PER_END_INT_CLR + description: The clear bit for SPI_MEM_PER_END_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SPI_MEM_PES_END_INT_CLR + description: The clear bit for SPI_MEM_PES_END_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SPI_MEM_WPE_END_INT_CLR + description: The clear bit for SPI_MEM_WPE_END_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SPI_MEM_SLV_ST_END_INT_CLR + description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SPI_MEM_MST_ST_END_INT_CLR + description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SPI_MEM_BROWN_OUT_INT_CLR + description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_INT_RAW + description: SPI1 interrupt raw register + addressOffset: 200 + size: 32 + fields: + - name: SPI_MEM_PER_END_INT_RAW + description: "The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_PES_END_INT_RAW + description: "The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WPE_END_INT_RAW + description: "The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SLV_ST_END_INT_RAW + description: "The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_MST_ST_END_INT_RAW + description: "The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_BROWN_OUT_INT_RAW + description: "The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others." + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_INT_ST + description: SPI1 interrupt status register + addressOffset: 204 + size: 32 + fields: + - name: SPI_MEM_PER_END_INT_ST + description: The status bit for SPI_MEM_PER_END_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_MEM_PES_END_INT_ST + description: The status bit for SPI_MEM_PES_END_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SPI_MEM_WPE_END_INT_ST + description: The status bit for SPI_MEM_WPE_END_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SLV_ST_END_INT_ST + description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SPI_MEM_MST_ST_END_INT_ST + description: The status bit for SPI_MEM_MST_ST_END_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SPI_MEM_BROWN_OUT_INT_ST + description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_DDR + description: SPI1 DDR control register + addressOffset: 212 + size: 32 + resetValue: 32 + fields: + - name: SPI_FMEM_DDR_EN + description: "1: in ddr mode, 0 in sdr mode" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_VAR_DUMMY + description: Set the bit to enable variable dummy cycle in spi ddr mode. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_DDR_RDAT_SWP + description: Set the bit to reorder rx data of the word in spi ddr mode. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_DDR_WDAT_SWP + description: Set the bit to reorder tx data of the word in spi ddr mode. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_DDR_CMD_DIS + description: the bit is used to disable dual edge in command phase when ddr mode. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_OUTMINBYTELEN + description: It is the minimum output data length in the panda device. + bitOffset: 5 + bitWidth: 7 + access: read-only + - name: SPI_FMEM_USR_DDR_DQS_THD + description: The delay number of data strobe which from memory based on SPI clock. + bitOffset: 14 + bitWidth: 7 + access: read-only + - name: SPI_FMEM_DDR_DQS_LOOP + description: "1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS." + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_CLK_DIFF_EN + description: "Set this bit to enable the differential SPI_CLK#." + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_DQS_CA_IN + description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_HYPERBUS_DUMMY_2X + description: "Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram." + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_CLK_DIFF_INV + description: Set this bit to invert SPI_DIFF when accesses to flash. . + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_OCTA_RAM_ADDR + description: "Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}." + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: SPI_FMEM_HYPERBUS_CA + description: "Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}." + bitOffset: 30 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_TIMING_CALI + description: SPI1 timing control register + addressOffset: 384 + size: 32 + fields: + - name: SPI_MEM_TIMING_CALI + description: The bit is used to enable timing auto-calibration for all reading operations. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_EXTRA_DUMMY_CYCLELEN + description: add extra dummy spi clock cycle length for spi clock calibration. + bitOffset: 2 + bitWidth: 3 + access: read-write + - register: + name: SPI_MEM_CLOCK_GATE + description: SPI1 clk_gate register + addressOffset: 512 + size: 32 + resetValue: 1 + fields: + - name: SPI_MEM_CLK_EN + description: "Register clock gate enable signal. 1: Enable. 0: Disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_DATE + description: Version control register + addressOffset: 1020 + size: 32 + resetValue: 35660128 + fields: + - name: SPI_MEM_DATE + description: Version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SPI2 + description: SPI (Serial Peripheral Interface) Controller 2 + groupName: SPI2 + baseAddress: 1611141120 + addressBlock: + - offset: 0 + size: 152 + usage: registers + interrupt: + - name: MSPI + value: 30 + - name: SPI2 + value: 59 + registers: + - register: + name: CMD + description: Command control register + addressOffset: 0 + size: 32 + fields: + - name: CONF_BITLEN + description: Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 18 + access: read-write + - name: UPDATE + description: "Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: USR + description: "User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf." + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: ADDR + description: Address value register + addressOffset: 4 + size: 32 + fields: + - name: USR_ADDR_VALUE + description: Address to slave. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CTRL + description: SPI control register + addressOffset: 8 + size: 32 + resetValue: 3932160 + fields: + - name: DUMMY_OUT + description: "0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FADDR_DUAL + description: "Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FADDR_QUAD + description: "Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FADDR_OCT + description: "Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: FCMD_DUAL + description: "Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FCMD_QUAD + description: "Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FCMD_OCT + description: "Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: FREAD_DUAL + description: "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: FREAD_QUAD + description: "In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: FREAD_OCT + description: "In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: Q_POL + description: "The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: D_POL + description: "The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: HOLD_POL + description: "SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: WP_POL + description: "Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: RD_BIT_ORDER + description: "In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state." + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: WR_BIT_ORDER + description: "In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state." + bitOffset: 25 + bitWidth: 2 + access: read-write + - register: + name: CLOCK + description: SPI clock control register + addressOffset: 12 + size: 32 + resetValue: 2147496003 + fields: + - name: CLKCNT_L + description: In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: CLKCNT_H + description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: CLKCNT_N + description: In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + bitOffset: 12 + bitWidth: 6 + access: read-write + - name: CLKDIV_PRE + description: In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + bitOffset: 18 + bitWidth: 4 + access: read-write + - name: CLK_EQU_SYSCLK + description: "In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USER + description: SPI USER control register + addressOffset: 16 + size: 32 + resetValue: 2147483840 + fields: + - name: DOUTDIN + description: "Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: QPI_MODE + description: "Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OPI_MODE + description: "Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TSCK_I_EDGE + description: "In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CS_HOLD + description: "spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CS_SETUP + description: "spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RSCK_I_EDGE + description: "In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CK_OUT_EDGE + description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FWRITE_DUAL + description: In the write operations read-data phase apply 2 signals. Can be configured in CONF state. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FWRITE_QUAD + description: In the write operations read-data phase apply 4 signals. Can be configured in CONF state. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FWRITE_OCT + description: In the write operations read-data phase apply 8 signals. Can be configured in CONF state. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: USR_CONF_NXT + description: "1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SIO + description: "Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: USR_MISO_HIGHPART + description: "read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: USR_MOSI_HIGHPART + description: "write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: USR_DUMMY_IDLE + description: spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: USR_MOSI + description: This bit enable the write-data phase of an operation. Can be configured in CONF state. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: USR_MISO + description: This bit enable the read-data phase of an operation. Can be configured in CONF state. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: USR_DUMMY + description: This bit enable the dummy phase of an operation. Can be configured in CONF state. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: USR_ADDR + description: This bit enable the address phase of an operation. Can be configured in CONF state. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: USR_COMMAND + description: This bit enable the command phase of an operation. Can be configured in CONF state. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USER1 + description: SPI USER control register 1 + addressOffset: 20 + size: 32 + resetValue: 3091267591 + fields: + - name: USR_DUMMY_CYCLELEN + description: The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: MST_WFULL_ERR_END_EN + description: "1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CS_SETUP_TIME + description: (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. + bitOffset: 17 + bitWidth: 5 + access: read-write + - name: CS_HOLD_TIME + description: delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. + bitOffset: 22 + bitWidth: 5 + access: read-write + - name: USR_ADDR_BITLEN + description: The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: USER2 + description: SPI USER control register 2 + addressOffset: 24 + size: 32 + resetValue: 2013265920 + fields: + - name: USR_COMMAND_VALUE + description: The value of command. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MST_REMPTY_ERR_END_EN + description: "1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: USR_COMMAND_BITLEN + description: The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: MS_DLEN + description: SPI data bit length control register + addressOffset: 28 + size: 32 + fields: + - name: MS_DATA_BITLEN + description: The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 0 + bitWidth: 18 + access: read-write + - register: + name: MISC + description: SPI misc register + addressOffset: 32 + size: 32 + resetValue: 62 + fields: + - name: CS0_DIS + description: "SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CS1_DIS + description: "SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CS2_DIS + description: "SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CS3_DIS + description: "SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CS4_DIS + description: "SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CS5_DIS + description: "SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CK_DIS + description: "1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: MASTER_CS_POL + description: "In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: CLK_DATA_DTR_EN + description: "1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19." + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: DATA_DTR_EN + description: "1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state." + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: ADDR_DTR_EN + description: "1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state." + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: CMD_DTR_EN + description: "1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state." + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: SLAVE_CS_POL + description: "spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: DQS_IDLE_EDGE + description: The default value of spi_dqs. Can be configured in CONF state. + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: CK_IDLE_EDGE + description: "1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CS_KEEP_ACTIVE + description: spi cs line keep low when the bit is set. Can be configured in CONF state. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: QUAD_DIN_PIN_SWAP + description: "1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DIN_MODE + description: SPI input delay mode configuration + addressOffset: 36 + size: 32 + fields: + - name: DIN0_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DIN1_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DIN2_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DIN3_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DIN4_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 8 + bitWidth: 2 + access: read-only + - name: DIN5_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input at the (SPI_DIN5_NUM+1)th falling edge of clk_spi_mst,2 input at the (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, 3: input at the (SPI_DIN5_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle. Can be configured in CONF state." + bitOffset: 10 + bitWidth: 2 + access: read-only + - name: DIN6_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input at the (SPI_DIN6_NUM+1)th falling edge of clk_spi_mst,2 input at the (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, 3: input at the (SPI_DIN6_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle. Can be configured in CONF state." + bitOffset: 12 + bitWidth: 2 + access: read-only + - name: DIN7_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input at the (SPI_DIN7_NUM+1)th falling edge of clk_spi_mst,2 input at the (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst rising edge cycle, 3: input at the (SPI_DIN7_NUM+1)th rising edge of clk_hclk plus one clk_spi_mst falling edge cycle. Can be configured in CONF state." + bitOffset: 14 + bitWidth: 2 + access: read-only + - name: TIMING_HCLK_ACTIVE + description: "1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state." + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: DIN_NUM + description: SPI input delay number configuration + addressOffset: 40 + size: 32 + fields: + - name: DIN0_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DIN1_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DIN2_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DIN3_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DIN4_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 8 + bitWidth: 2 + access: read-only + - name: DIN5_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 10 + bitWidth: 2 + access: read-only + - name: DIN6_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 12 + bitWidth: 2 + access: read-only + - name: DIN7_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 14 + bitWidth: 2 + access: read-only + - register: + name: DOUT_MODE + description: SPI output delay mode configuration + addressOffset: 44 + size: 32 + fields: + - name: DOUT0_MODE + description: "The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DOUT1_MODE + description: "The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DOUT2_MODE + description: "The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DOUT3_MODE + description: "The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DOUT4_MODE + description: "The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DOUT5_MODE + description: "The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: DOUT6_MODE + description: "The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: DOUT7_MODE + description: "The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: D_DQS_MODE + description: "The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: DMA_CONF + description: SPI DMA control register + addressOffset: 48 + size: 32 + resetValue: 3 + fields: + - name: DMA_OUTFIFO_EMPTY + description: "Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DMA_INFIFO_FULL + description: "Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: DMA_SLV_SEG_TRANS_EN + description: "Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SLV_RX_SEG_TRANS_CLR_EN + description: "1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SLV_TX_SEG_TRANS_CLR_EN + description: "1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: RX_EOF_EN + description: "1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: DMA_RX_ENA + description: Set this bit to enable SPI DMA controlled receive data mode. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: DMA_TX_ENA + description: Set this bit to enable SPI DMA controlled send data mode. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: RX_AFIFO_RST + description: "Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer." + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: BUF_AFIFO_RST + description: "Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer." + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: DMA_AFIFO_RST + description: "Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer." + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: DMA_INT_ENA + description: SPI interrupt enable register + addressOffset: 52 + size: 32 + fields: + - name: DMA_INFIFO_FULL_ERR_INT_ENA + description: The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DMA_OUTFIFO_EMPTY_ERR_INT_ENA + description: The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SLV_EX_QPI_INT_ENA + description: The enable bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLV_EN_QPI_INT_ENA + description: The enable bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLV_CMD7_INT_ENA + description: The enable bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SLV_CMD8_INT_ENA + description: The enable bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SLV_CMD9_INT_ENA + description: The enable bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SLV_CMDA_INT_ENA + description: The enable bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SLV_RD_DMA_DONE_INT_ENA + description: The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLV_WR_DMA_DONE_INT_ENA + description: The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLV_RD_BUF_DONE_INT_ENA + description: The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLV_WR_BUF_DONE_INT_ENA + description: The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TRANS_DONE_INT_ENA + description: The enable bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DMA_SEG_TRANS_DONE_INT_ENA + description: The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SEG_MAGIC_ERR_INT_ENA + description: The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLV_BUF_ADDR_ERR_INT_ENA + description: The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLV_CMD_ERR_INT_ENA + description: The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: MST_RX_AFIFO_WFULL_ERR_INT_ENA + description: The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MST_TX_AFIFO_REMPTY_ERR_INT_ENA + description: The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: APP2_INT_ENA + description: The enable bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: APP1_INT_ENA + description: The enable bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: DMA_INT_CLR + description: SPI interrupt clear register + addressOffset: 56 + size: 32 + fields: + - name: DMA_INFIFO_FULL_ERR_INT_CLR + description: The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: DMA_OUTFIFO_EMPTY_ERR_INT_CLR + description: The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SLV_EX_QPI_INT_CLR + description: The clear bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SLV_EN_QPI_INT_CLR + description: The clear bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SLV_CMD7_INT_CLR + description: The clear bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SLV_CMD8_INT_CLR + description: The clear bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: SLV_CMD9_INT_CLR + description: The clear bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: SLV_CMDA_INT_CLR + description: The clear bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SLV_RD_DMA_DONE_INT_CLR + description: The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SLV_WR_DMA_DONE_INT_CLR + description: The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SLV_RD_BUF_DONE_INT_CLR + description: The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SLV_WR_BUF_DONE_INT_CLR + description: The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TRANS_DONE_INT_CLR + description: The clear bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: DMA_SEG_TRANS_DONE_INT_CLR + description: The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SEG_MAGIC_ERR_INT_CLR + description: The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SLV_BUF_ADDR_ERR_INT_CLR + description: The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: SLV_CMD_ERR_INT_CLR + description: The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: MST_RX_AFIFO_WFULL_ERR_INT_CLR + description: The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: MST_TX_AFIFO_REMPTY_ERR_INT_CLR + description: The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: APP2_INT_CLR + description: The clear bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: APP1_INT_CLR + description: The clear bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: write-only + - register: + name: DMA_INT_RAW + description: SPI interrupt raw register + addressOffset: 60 + size: 32 + fields: + - name: DMA_INFIFO_FULL_ERR_INT_RAW + description: "1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DMA_OUTFIFO_EMPTY_ERR_INT_RAW + description: "1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SLV_EX_QPI_INT_RAW + description: "The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLV_EN_QPI_INT_RAW + description: "The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLV_CMD7_INT_RAW + description: "The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SLV_CMD8_INT_RAW + description: "The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SLV_CMD9_INT_RAW + description: "The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SLV_CMDA_INT_RAW + description: "The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SLV_RD_DMA_DONE_INT_RAW + description: "The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLV_WR_DMA_DONE_INT_RAW + description: "The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLV_RD_BUF_DONE_INT_RAW + description: "The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLV_WR_BUF_DONE_INT_RAW + description: "The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TRANS_DONE_INT_RAW + description: "The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DMA_SEG_TRANS_DONE_INT_RAW + description: "The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SEG_MAGIC_ERR_INT_RAW + description: "The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLV_BUF_ADDR_ERR_INT_RAW + description: "The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLV_CMD_ERR_INT_RAW + description: "The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: MST_RX_AFIFO_WFULL_ERR_INT_RAW + description: "The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MST_TX_AFIFO_REMPTY_ERR_INT_RAW + description: "The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: APP2_INT_RAW + description: The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: APP1_INT_RAW + description: The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: DMA_INT_ST + description: SPI interrupt status register + addressOffset: 64 + size: 32 + fields: + - name: DMA_INFIFO_FULL_ERR_INT_ST + description: The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DMA_OUTFIFO_EMPTY_ERR_INT_ST + description: The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SLV_EX_QPI_INT_ST + description: The status bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SLV_EN_QPI_INT_ST + description: The status bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SLV_CMD7_INT_ST + description: The status bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SLV_CMD8_INT_ST + description: The status bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SLV_CMD9_INT_ST + description: The status bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SLV_CMDA_INT_ST + description: The status bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SLV_RD_DMA_DONE_INT_ST + description: The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SLV_WR_DMA_DONE_INT_ST + description: The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SLV_RD_BUF_DONE_INT_ST + description: The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SLV_WR_BUF_DONE_INT_ST + description: The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TRANS_DONE_INT_ST + description: The status bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: DMA_SEG_TRANS_DONE_INT_ST + description: The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SEG_MAGIC_ERR_INT_ST + description: The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SLV_BUF_ADDR_ERR_INT_ST + description: The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLV_CMD_ERR_INT_ST + description: The status bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: MST_RX_AFIFO_WFULL_ERR_INT_ST + description: The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: MST_TX_AFIFO_REMPTY_ERR_INT_ST + description: The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: APP2_INT_ST + description: The status bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: APP1_INT_ST + description: The status bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: read-only + - register: + name: DMA_INT_SET + description: SPI interrupt software set register + addressOffset: 68 + size: 32 + fields: + - name: DMA_INFIFO_FULL_ERR_INT_SET + description: The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: DMA_OUTFIFO_EMPTY_ERR_INT_SET + description: The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SLV_EX_QPI_INT_SET + description: The software set bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SLV_EN_QPI_INT_SET + description: The software set bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SLV_CMD7_INT_SET + description: The software set bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SLV_CMD8_INT_SET + description: The software set bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: SLV_CMD9_INT_SET + description: The software set bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: SLV_CMDA_INT_SET + description: The software set bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SLV_RD_DMA_DONE_INT_SET + description: The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SLV_WR_DMA_DONE_INT_SET + description: The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SLV_RD_BUF_DONE_INT_SET + description: The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SLV_WR_BUF_DONE_INT_SET + description: The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TRANS_DONE_INT_SET + description: The software set bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: DMA_SEG_TRANS_DONE_INT_SET + description: The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SEG_MAGIC_ERR_INT_SET + description: The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SLV_BUF_ADDR_ERR_INT_SET + description: The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: SLV_CMD_ERR_INT_SET + description: The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: MST_RX_AFIFO_WFULL_ERR_INT_SET + description: The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: MST_TX_AFIFO_REMPTY_ERR_INT_SET + description: The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: APP2_INT_SET + description: The software set bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: APP1_INT_SET + description: The software set bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: write-only + - register: + name: W0 + description: SPI CPU-controlled buffer0 + addressOffset: 152 + size: 32 + fields: + - name: BUF0 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W1 + description: SPI CPU-controlled buffer1 + addressOffset: 156 + size: 32 + fields: + - name: BUF1 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W2 + description: SPI CPU-controlled buffer2 + addressOffset: 160 + size: 32 + fields: + - name: BUF2 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W3 + description: SPI CPU-controlled buffer3 + addressOffset: 164 + size: 32 + fields: + - name: BUF3 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W4 + description: SPI CPU-controlled buffer4 + addressOffset: 168 + size: 32 + fields: + - name: BUF4 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W5 + description: SPI CPU-controlled buffer5 + addressOffset: 172 + size: 32 + fields: + - name: BUF5 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W6 + description: SPI CPU-controlled buffer6 + addressOffset: 176 + size: 32 + fields: + - name: BUF6 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W7 + description: SPI CPU-controlled buffer7 + addressOffset: 180 + size: 32 + fields: + - name: BUF7 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W8 + description: SPI CPU-controlled buffer8 + addressOffset: 184 + size: 32 + fields: + - name: BUF8 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W9 + description: SPI CPU-controlled buffer9 + addressOffset: 188 + size: 32 + fields: + - name: BUF9 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W10 + description: SPI CPU-controlled buffer10 + addressOffset: 192 + size: 32 + fields: + - name: BUF10 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W11 + description: SPI CPU-controlled buffer11 + addressOffset: 196 + size: 32 + fields: + - name: BUF11 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W12 + description: SPI CPU-controlled buffer12 + addressOffset: 200 + size: 32 + fields: + - name: BUF12 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W13 + description: SPI CPU-controlled buffer13 + addressOffset: 204 + size: 32 + fields: + - name: BUF13 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W14 + description: SPI CPU-controlled buffer14 + addressOffset: 208 + size: 32 + fields: + - name: BUF14 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W15 + description: SPI CPU-controlled buffer15 + addressOffset: 212 + size: 32 + fields: + - name: BUF15 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SLAVE + description: SPI slave control register + addressOffset: 224 + size: 32 + resetValue: 41943040 + fields: + - name: CLK_MODE + description: "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CLK_MODE_13 + description: "{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RSCK_DATA_OUT + description: "It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLV_RDDMA_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLV_WRDMA_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLV_RDBUF_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLV_WRBUF_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DMA_SEG_MAGIC_VALUE + description: The magic value of BM table in master DMA seg-trans. + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: MODE + description: "Set SPI work mode. 1: slave mode 0: master mode." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SOFT_RESET + description: "Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state." + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: USR_CONF + description: "1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: MST_FD_WAIT_DMA_TX_DATA + description: "In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer." + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: SLAVE1 + description: SPI slave control register 1 + addressOffset: 228 + size: 32 + fields: + - name: SLV_DATA_BITLEN + description: The transferred data bit length in SPI slave FD and HD mode. + bitOffset: 0 + bitWidth: 18 + access: read-write + - name: SLV_LAST_COMMAND + description: In the slave mode it is the value of command. + bitOffset: 18 + bitWidth: 8 + access: read-write + - name: SLV_LAST_ADDR + description: In the slave mode it is the value of address. + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: CLK_GATE + description: SPI module clock and register clock control + addressOffset: 232 + size: 32 + fields: + - name: CLK_EN + description: Set this bit to enable clk gate + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MST_CLK_ACTIVE + description: Set this bit to power on the SPI module clock. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MST_CLK_SEL + description: "This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control + addressOffset: 240 + size: 32 + resetValue: 35656448 + fields: + - name: DATE + description: SPI register version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SYSTIMER + description: System Timer + groupName: SYSTIMER + baseAddress: 1610657792 + addressBlock: + - offset: 0 + size: 144 + usage: registers + interrupt: + - name: SYSTIMER_TARGET0 + value: 45 + - name: SYSTIMER_TARGET1 + value: 46 + - name: SYSTIMER_TARGET2 + value: 47 + registers: + - register: + name: CONF + description: Configure system timer clock + addressOffset: 0 + size: 32 + resetValue: 1174405120 + fields: + - name: SYSTIMER_CLK_FO + description: systimer clock force on + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_EN + description: "enable systimer's etm task and event" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TARGET2_WORK_EN + description: target2 work enable + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TARGET1_WORK_EN + description: target1 work enable + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TARGET0_WORK_EN + description: target0 work enable + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT1_CORE1_STALL_EN + description: If timer unit1 is stalled when core1 stalled + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT1_CORE0_STALL_EN + description: If timer unit1 is stalled when core0 stalled + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT0_CORE1_STALL_EN + description: If timer unit0 is stalled when core1 stalled + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT0_CORE0_STALL_EN + description: If timer unit0 is stalled when core0 stalled + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT1_WORK_EN + description: timer unit1 work enable + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT0_WORK_EN + description: timer unit0 work enable + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: register file clk gating + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: UNIT0_OP + description: system timer unit0 value update register + addressOffset: 4 + size: 32 + fields: + - name: TIMER_UNIT0_VALUE_VALID + description: timer value is sync and valid + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: TIMER_UNIT0_UPDATE + description: update timer_unit0 + bitOffset: 30 + bitWidth: 1 + access: write-only + - register: + name: UNIT1_OP + description: system timer unit1 value update register + addressOffset: 8 + size: 32 + fields: + - name: TIMER_UNIT1_VALUE_VALID + description: timer value is sync and valid + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: TIMER_UNIT1_UPDATE + description: update timer unit1 + bitOffset: 30 + bitWidth: 1 + access: write-only + - register: + name: UNIT0_LOAD_HI + description: system timer unit0 value high load register + addressOffset: 12 + size: 32 + fields: + - name: TIMER_UNIT0_LOAD_HI + description: timer unit0 load high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: UNIT0_LOAD_LO + description: system timer unit0 value low load register + addressOffset: 16 + size: 32 + fields: + - name: TIMER_UNIT0_LOAD_LO + description: timer unit0 load low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: UNIT1_LOAD_HI + description: system timer unit1 value high load register + addressOffset: 20 + size: 32 + fields: + - name: TIMER_UNIT1_LOAD_HI + description: timer unit1 load high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: UNIT1_LOAD_LO + description: system timer unit1 value low load register + addressOffset: 24 + size: 32 + fields: + - name: TIMER_UNIT1_LOAD_LO + description: timer unit1 load low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET0_HI + description: system timer comp0 value high register + addressOffset: 28 + size: 32 + fields: + - name: TIMER_TARGET0_HI + description: timer taget0 high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: TARGET0_LO + description: system timer comp0 value low register + addressOffset: 32 + size: 32 + fields: + - name: TIMER_TARGET0_LO + description: timer taget0 low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET1_HI + description: system timer comp1 value high register + addressOffset: 36 + size: 32 + fields: + - name: TIMER_TARGET1_HI + description: timer taget1 high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: TARGET1_LO + description: system timer comp1 value low register + addressOffset: 40 + size: 32 + fields: + - name: TIMER_TARGET1_LO + description: timer taget1 low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET2_HI + description: system timer comp2 value high register + addressOffset: 44 + size: 32 + fields: + - name: TIMER_TARGET2_HI + description: timer taget2 high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: TARGET2_LO + description: system timer comp2 value low register + addressOffset: 48 + size: 32 + fields: + - name: TIMER_TARGET2_LO + description: timer taget2 low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET0_CONF + description: system timer comp0 target mode register + addressOffset: 52 + size: 32 + fields: + - name: TARGET0_PERIOD + description: target0 period + bitOffset: 0 + bitWidth: 26 + access: read-write + - name: TARGET0_PERIOD_MODE + description: Set target0 to period mode + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TARGET0_TIMER_UNIT_SEL + description: select which unit to compare + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TARGET1_CONF + description: system timer comp1 target mode register + addressOffset: 56 + size: 32 + fields: + - name: TARGET1_PERIOD + description: target1 period + bitOffset: 0 + bitWidth: 26 + access: read-write + - name: TARGET1_PERIOD_MODE + description: Set target1 to period mode + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TARGET1_TIMER_UNIT_SEL + description: select which unit to compare + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TARGET2_CONF + description: system timer comp2 target mode register + addressOffset: 60 + size: 32 + fields: + - name: TARGET2_PERIOD + description: target2 period + bitOffset: 0 + bitWidth: 26 + access: read-write + - name: TARGET2_PERIOD_MODE + description: Set target2 to period mode + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TARGET2_TIMER_UNIT_SEL + description: select which unit to compare + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: UNIT0_VALUE_HI + description: system timer unit0 value high register + addressOffset: 64 + size: 32 + fields: + - name: TIMER_UNIT0_VALUE_HI + description: timer read value high 20bits + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: UNIT0_VALUE_LO + description: system timer unit0 value low register + addressOffset: 68 + size: 32 + fields: + - name: TIMER_UNIT0_VALUE_LO + description: timer read value low 32bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: UNIT1_VALUE_HI + description: system timer unit1 value high register + addressOffset: 72 + size: 32 + fields: + - name: TIMER_UNIT1_VALUE_HI + description: timer read value high 20bits + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: UNIT1_VALUE_LO + description: system timer unit1 value low register + addressOffset: 76 + size: 32 + fields: + - name: TIMER_UNIT1_VALUE_LO + description: timer read value low 32bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: COMP0_LOAD + description: system timer comp0 conf sync register + addressOffset: 80 + size: 32 + fields: + - name: TIMER_COMP0_LOAD + description: timer comp0 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: COMP1_LOAD + description: system timer comp1 conf sync register + addressOffset: 84 + size: 32 + fields: + - name: TIMER_COMP1_LOAD + description: timer comp1 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: COMP2_LOAD + description: system timer comp2 conf sync register + addressOffset: 88 + size: 32 + fields: + - name: TIMER_COMP2_LOAD + description: timer comp2 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: UNIT0_LOAD + description: system timer unit0 conf sync register + addressOffset: 92 + size: 32 + fields: + - name: TIMER_UNIT0_LOAD + description: timer unit0 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: UNIT1_LOAD + description: system timer unit1 conf sync register + addressOffset: 96 + size: 32 + fields: + - name: TIMER_UNIT1_LOAD + description: timer unit1 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + description: systimer interrupt enable register + addressOffset: 100 + size: 32 + fields: + - name: TARGET0_INT_ENA + description: interupt0 enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TARGET1_INT_ENA + description: interupt1 enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TARGET2_INT_ENA + description: interupt2 enable + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: systimer interrupt raw register + addressOffset: 104 + size: 32 + fields: + - name: TARGET0_INT_RAW + description: interupt0 raw + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TARGET1_INT_RAW + description: interupt1 raw + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TARGET2_INT_RAW + description: interupt2 raw + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: systimer interrupt clear register + addressOffset: 108 + size: 32 + fields: + - name: TARGET0_INT_CLR + description: interupt0 clear + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TARGET1_INT_CLR + description: interupt1 clear + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TARGET2_INT_CLR + description: interupt2 clear + bitOffset: 2 + bitWidth: 1 + access: write-only + - register: + name: INT_ST + description: systimer interrupt status register + addressOffset: 112 + size: 32 + fields: + - name: TARGET0_INT_ST + description: interupt0 status + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TARGET1_INT_ST + description: interupt1 status + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TARGET2_INT_ST + description: interupt2 status + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: REAL_TARGET0_LO + description: system timer comp0 actual target value low register + addressOffset: 116 + size: 32 + fields: + - name: TARGET0_LO_RO + description: actual target value value low 32bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: REAL_TARGET0_HI + description: system timer comp0 actual target value high register + addressOffset: 120 + size: 32 + fields: + - name: TARGET0_HI_RO + description: actual target value value high 20bits + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: REAL_TARGET1_LO + description: system timer comp1 actual target value low register + addressOffset: 124 + size: 32 + fields: + - name: TARGET1_LO_RO + description: actual target value value low 32bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: REAL_TARGET1_HI + description: system timer comp1 actual target value high register + addressOffset: 128 + size: 32 + fields: + - name: TARGET1_HI_RO + description: actual target value value high 20bits + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: REAL_TARGET2_LO + description: system timer comp2 actual target value low register + addressOffset: 132 + size: 32 + fields: + - name: TARGET2_LO_RO + description: actual target value value low 32bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: REAL_TARGET2_HI + description: system timer comp2 actual target value high register + addressOffset: 136 + size: 32 + fields: + - name: TARGET2_HI_RO + description: actual target value value high 20bits + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: DATE + description: system timer version control register + addressOffset: 252 + size: 32 + resetValue: 35655795 + fields: + - name: DATE + description: systimer register version + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: TEE + description: TEE Peripheral + groupName: TEE + baseAddress: 1611235328 + addressBlock: + - offset: 0 + size: 136 + usage: registers + registers: + - register: + name: M0_MODE_CTRL + description: Tee mode control register + addressOffset: 0 + size: 32 + fields: + - name: M0_MODE + description: "M0 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M1_MODE_CTRL + description: Tee mode control register + addressOffset: 4 + size: 32 + resetValue: 3 + fields: + - name: M1_MODE + description: "M1 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M2_MODE_CTRL + description: Tee mode control register + addressOffset: 8 + size: 32 + fields: + - name: M2_MODE + description: "M2 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M3_MODE_CTRL + description: Tee mode control register + addressOffset: 12 + size: 32 + resetValue: 3 + fields: + - name: M3_MODE + description: "M3 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M4_MODE_CTRL + description: Tee mode control register + addressOffset: 16 + size: 32 + resetValue: 3 + fields: + - name: M4_MODE + description: "M4 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M5_MODE_CTRL + description: Tee mode control register + addressOffset: 20 + size: 32 + resetValue: 3 + fields: + - name: M5_MODE + description: "M5 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M6_MODE_CTRL + description: Tee mode control register + addressOffset: 24 + size: 32 + resetValue: 3 + fields: + - name: M6_MODE + description: "M6 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M7_MODE_CTRL + description: Tee mode control register + addressOffset: 28 + size: 32 + resetValue: 3 + fields: + - name: M7_MODE + description: "M7 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M8_MODE_CTRL + description: Tee mode control register + addressOffset: 32 + size: 32 + resetValue: 3 + fields: + - name: M8_MODE + description: "M8 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M9_MODE_CTRL + description: Tee mode control register + addressOffset: 36 + size: 32 + resetValue: 3 + fields: + - name: M9_MODE + description: "M9 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M10_MODE_CTRL + description: Tee mode control register + addressOffset: 40 + size: 32 + resetValue: 3 + fields: + - name: M10_MODE + description: "M10 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M11_MODE_CTRL + description: Tee mode control register + addressOffset: 44 + size: 32 + resetValue: 3 + fields: + - name: M11_MODE + description: "M11 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M12_MODE_CTRL + description: Tee mode control register + addressOffset: 48 + size: 32 + resetValue: 3 + fields: + - name: M12_MODE + description: "M12 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M13_MODE_CTRL + description: Tee mode control register + addressOffset: 52 + size: 32 + resetValue: 3 + fields: + - name: M13_MODE + description: "M13 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M14_MODE_CTRL + description: Tee mode control register + addressOffset: 56 + size: 32 + resetValue: 3 + fields: + - name: M14_MODE + description: "M14 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M15_MODE_CTRL + description: Tee mode control register + addressOffset: 60 + size: 32 + resetValue: 3 + fields: + - name: M15_MODE + description: "M15 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M16_MODE_CTRL + description: Tee mode control register + addressOffset: 64 + size: 32 + resetValue: 3 + fields: + - name: M16_MODE + description: "M16 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M17_MODE_CTRL + description: Tee mode control register + addressOffset: 68 + size: 32 + resetValue: 3 + fields: + - name: M17_MODE + description: "M17 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M18_MODE_CTRL + description: Tee mode control register + addressOffset: 72 + size: 32 + resetValue: 3 + fields: + - name: M18_MODE + description: "M18 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M19_MODE_CTRL + description: Tee mode control register + addressOffset: 76 + size: 32 + resetValue: 3 + fields: + - name: M19_MODE + description: "M19 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M20_MODE_CTRL + description: Tee mode control register + addressOffset: 80 + size: 32 + resetValue: 3 + fields: + - name: M20_MODE + description: "M20 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M21_MODE_CTRL + description: Tee mode control register + addressOffset: 84 + size: 32 + resetValue: 3 + fields: + - name: M21_MODE + description: "M21 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M22_MODE_CTRL + description: Tee mode control register + addressOffset: 88 + size: 32 + resetValue: 3 + fields: + - name: M22_MODE + description: "M22 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M23_MODE_CTRL + description: Tee mode control register + addressOffset: 92 + size: 32 + resetValue: 3 + fields: + - name: M23_MODE + description: "M23 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M24_MODE_CTRL + description: Tee mode control register + addressOffset: 96 + size: 32 + resetValue: 3 + fields: + - name: M24_MODE + description: "M24 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M25_MODE_CTRL + description: Tee mode control register + addressOffset: 100 + size: 32 + resetValue: 3 + fields: + - name: M25_MODE + description: "M25 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M26_MODE_CTRL + description: Tee mode control register + addressOffset: 104 + size: 32 + resetValue: 3 + fields: + - name: M26_MODE + description: "M26 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M27_MODE_CTRL + description: Tee mode control register + addressOffset: 108 + size: 32 + resetValue: 3 + fields: + - name: M27_MODE + description: "M27 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M28_MODE_CTRL + description: Tee mode control register + addressOffset: 112 + size: 32 + resetValue: 3 + fields: + - name: M28_MODE + description: "M28 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M29_MODE_CTRL + description: Tee mode control register + addressOffset: 116 + size: 32 + resetValue: 3 + fields: + - name: M29_MODE + description: "M29 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M30_MODE_CTRL + description: Tee mode control register + addressOffset: 120 + size: 32 + resetValue: 3 + fields: + - name: M30_MODE + description: "M30 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: M31_MODE_CTRL + description: Tee mode control register + addressOffset: 124 + size: 32 + resetValue: 3 + fields: + - name: M31_MODE + description: "M31 security level mode: 2'd3: ree_mode2. 2'd2: ree_mode1. 2'd1: ree_mode0. 2'd0: tee_mode" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: CLOCK_GATE + description: Clock gating register + addressOffset: 128 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: reg_clk_en + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version register + addressOffset: 4092 + size: 32 + resetValue: 35672706 + fields: + - name: DATE + description: reg_tee_date + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: TIMG0 + description: Timer Group 0 + groupName: TIMG + baseAddress: 1610649600 + addressBlock: + - offset: 0 + size: 104 + usage: registers + interrupt: + - name: TG0_T0_LEVEL + value: 41 + - name: TG0_WDT_LEVEL + value: 42 + registers: + - register: + name: T0CONFIG + description: Timer %s configuration register + addressOffset: 0 + size: 32 + resetValue: 1610620928 + fields: + - name: USE_XTAL + description: "1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: ALARM_EN + description: "When set, the alarm is enabled. This bit is automatically cleared once an\nalarm occurs." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DIVCNT_RST + description: "When set, Timer %s 's clock divider counter will be reset." + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: DIVIDER + description: Timer %s clock (T%s_clk) prescaler value. + bitOffset: 13 + bitWidth: 16 + access: read-write + - name: AUTORELOAD + description: "When set, timer %s auto-reload at alarm is enabled." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: INCREASE + description: "When set, the timer %s time-base counter will increment every clock tick. When\ncleared, the timer %s time-base counter will decrement." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: EN + description: "When set, the timer %s time-base counter is enabled." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: T0LO + description: "Timer %s current value, low 32 bits" + addressOffset: 4 + size: 32 + fields: + - name: LO + description: "After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter\nof timer %s can be read here." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: T0HI + description: "Timer %s current value, high 22 bits" + addressOffset: 8 + size: 32 + fields: + - name: HI + description: "After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter\nof timer %s can be read here." + bitOffset: 0 + bitWidth: 22 + access: read-only + - register: + name: T0UPDATE + description: Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG + addressOffset: 12 + size: 32 + fields: + - name: UPDATE + description: "After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: T0ALARMLO + description: "Timer %s alarm value, low 32 bits" + addressOffset: 16 + size: 32 + fields: + - name: ALARM_LO + description: "Timer %s alarm trigger time-base counter value, low 32 bits." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: T0ALARMHI + description: "Timer %s alarm value, high bits" + addressOffset: 20 + size: 32 + fields: + - name: ALARM_HI + description: "Timer %s alarm trigger time-base counter value, high 22 bits." + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: T0LOADLO + description: "Timer %s reload value, low 32 bits" + addressOffset: 24 + size: 32 + fields: + - name: LOAD_LO + description: "Low 32 bits of the value that a reload will load onto timer %s time-base\nCounter." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: T0LOADHI + description: "Timer %s reload value, high 22 bits" + addressOffset: 28 + size: 32 + fields: + - name: LOAD_HI + description: "High 22 bits of the value that a reload will load onto timer %s time-base\ncounter." + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: T0LOAD + description: Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG + addressOffset: 32 + size: 32 + fields: + - name: LOAD + description: Write any value to trigger a timer %s time-base counter reload. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: WDTCONFIG0 + description: Watchdog timer configuration register + addressOffset: 72 + size: 32 + resetValue: 311296 + fields: + - name: WDT_APPCPU_RESET_EN + description: WDT reset CPU enable. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: WDT_PROCPU_RESET_EN + description: WDT reset CPU enable. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: WDT_FLASHBOOT_MOD_EN + description: "When set, Flash boot protection is enabled." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: WDT_SYS_RESET_LENGTH + description: "System reset signal length selection. 0: 100 ns, 1: 200 ns,\n2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us." + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: WDT_CPU_RESET_LENGTH + description: "CPU reset signal length selection. 0: 100 ns, 1: 200 ns,\n2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us." + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: WDT_USE_XTAL + description: "choose WDT clock:0-apb_clk, 1-xtal_clk." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: WDT_CONF_UPDATE_EN + description: update the WDT configuration registers + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: WDT_STG3 + description: "Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system." + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: WDT_STG2 + description: "Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system." + bitOffset: 25 + bitWidth: 2 + access: read-write + - name: WDT_STG1 + description: "Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system." + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: WDT_STG0 + description: "Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system." + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: WDT_EN + description: "When set, MWDT is enabled." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: WDTCONFIG1 + description: Watchdog timer prescaler register + addressOffset: 76 + size: 32 + resetValue: 65536 + fields: + - name: WDT_DIVCNT_RST + description: "When set, WDT 's clock divider counter will be reset." + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: WDT_CLK_PRESCALE + description: "MWDT clock prescaler value. MWDT clock period = 12.5 ns *\nTIMG_WDT_CLK_PRESCALE." + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: WDTCONFIG2 + description: Watchdog timer stage 0 timeout value + addressOffset: 80 + size: 32 + resetValue: 26000000 + fields: + - name: WDT_STG0_HOLD + description: "Stage 0 timeout value, in MWDT clock cycles." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG3 + description: Watchdog timer stage 1 timeout value + addressOffset: 84 + size: 32 + resetValue: 134217727 + fields: + - name: WDT_STG1_HOLD + description: "Stage 1 timeout value, in MWDT clock cycles." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG4 + description: Watchdog timer stage 2 timeout value + addressOffset: 88 + size: 32 + resetValue: 1048575 + fields: + - name: WDT_STG2_HOLD + description: "Stage 2 timeout value, in MWDT clock cycles." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG5 + description: Watchdog timer stage 3 timeout value + addressOffset: 92 + size: 32 + resetValue: 1048575 + fields: + - name: WDT_STG3_HOLD + description: "Stage 3 timeout value, in MWDT clock cycles." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTFEED + description: Write to feed the watchdog timer + addressOffset: 96 + size: 32 + fields: + - name: WDT_FEED + description: Write any value to feed the MWDT. (WO) + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: WDTWPROTECT + description: Watchdog write protect register + addressOffset: 100 + size: 32 + resetValue: 1356348065 + fields: + - name: WDT_WKEY + description: "If the register contains a different value than its reset value, write\nprotection is enabled." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RTCCALICFG + description: RTC calibration configure register + addressOffset: 104 + size: 32 + resetValue: 69632 + fields: + - name: RTC_CALI_START_CYCLING + description: "0: one-shot frequency calculation,1: periodic frequency calculation," + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RTC_CALI_CLK_SEL + description: "0:rtc slow clock. 1:clk_8m, 2:xtal_32k." + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: RTC_CALI_RDY + description: indicate one-shot frequency calculation is done. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: RTC_CALI_MAX + description: "Configure the time to calculate RTC slow clock's frequency." + bitOffset: 16 + bitWidth: 15 + access: read-write + - name: RTC_CALI_START + description: Set this bit to start one-shot frequency calculation. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RTCCALICFG1 + description: RTC calibration configure1 register + addressOffset: 108 + size: 32 + fields: + - name: RTC_CALI_CYCLING_DATA_VLD + description: indicate periodic frequency calculation is done. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RTC_CALI_VALUE + description: "When one-shot or periodic frequency calculation is done, read this value to calculate RTC slow clock's frequency." + bitOffset: 7 + bitWidth: 25 + access: read-only + - register: + name: INT_ENA_TIMERS + description: Interrupt enable bits + addressOffset: 112 + size: 32 + fields: + - name: T0_INT_ENA + description: The interrupt enable bit for the TIMG_T0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: WDT_INT_ENA + description: The interrupt enable bit for the TIMG_WDT_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW_TIMERS + description: Raw interrupt status + addressOffset: 116 + size: 32 + fields: + - name: T0_INT_RAW + description: The raw interrupt status bit for the TIMG_T0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: WDT_INT_RAW + description: The raw interrupt status bit for the TIMG_WDT_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_ST_TIMERS + description: Masked interrupt status + addressOffset: 120 + size: 32 + fields: + - name: T0_INT_ST + description: The masked interrupt status bit for the TIMG_T0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: WDT_INT_ST + description: The masked interrupt status bit for the TIMG_WDT_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR_TIMERS + description: Interrupt clear bits + addressOffset: 124 + size: 32 + fields: + - name: T0_INT_CLR + description: Set this bit to clear the TIMG_T0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: WDT_INT_CLR + description: Set this bit to clear the TIMG_WDT_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: RTCCALICFG2 + description: Timer group calibration register + addressOffset: 128 + size: 32 + resetValue: 4294967192 + fields: + - name: RTC_CALI_TIMEOUT + description: RTC calibration timeout indicator + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RTC_CALI_TIMEOUT_RST_CNT + description: Cycles that release calibration timeout reset + bitOffset: 3 + bitWidth: 4 + access: read-write + - name: RTC_CALI_TIMEOUT_THRES + description: "Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered." + bitOffset: 7 + bitWidth: 25 + access: read-write + - register: + name: NTIMERS_DATE + description: Timer version control register + addressOffset: 248 + size: 32 + resetValue: 35676274 + fields: + - name: NTIMGS_DATE + description: Timer version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + name: REGCLK + description: Timer group clock gate register + addressOffset: 252 + size: 32 + resetValue: 1879048192 + fields: + - name: ETM_EN + description: "enable timer's etm task and event" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: WDT_CLK_IS_ACTIVE + description: "enable WDT's clock" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TIMER_CLK_IS_ACTIVE + description: "enable Timer 30's clock" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software." + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: TIMG1 + description: Timer Group 1 + baseAddress: 1610653696 + interrupt: + - name: TG1_T0_LEVEL + value: 43 + - name: TG1_WDT_LEVEL + value: 44 + derivedFrom: TIMG0 + - name: TRACE + description: RISC-V Trace Encoder + groupName: TRACE + baseAddress: 1611399168 + addressBlock: + - offset: 0 + size: 48 + usage: registers + interrupt: + - name: TRACE + value: 12 + registers: + - register: + name: MEM_START_ADDR + description: mem start addr + addressOffset: 0 + size: 32 + fields: + - name: MEM_START_ADDR + description: The start address of trace memory + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: MEM_END_ADDR + description: mem end addr + addressOffset: 4 + size: 32 + resetValue: 4294967295 + fields: + - name: MEM_END_ADDR + description: The end address of trace memory + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: MEM_CURRENT_ADDR + description: mem current addr + addressOffset: 8 + size: 32 + fields: + - name: MEM_CURRENT_ADDR + description: "current_mem_addr,indicate that next writing addr" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: MEM_ADDR_UPDATE + description: mem addr update + addressOffset: 12 + size: 32 + fields: + - name: MEM_CURRENT_ADDR_UPDATE + description: "when set this reg, the current_mem_addr will update to start_addr" + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: FIFO_STATUS + description: fifo status register + addressOffset: 16 + size: 32 + resetValue: 1 + fields: + - name: FIFO_EMPTY + description: 1 indicate that fifo is empty + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: WORK_STATUS + description: mem_full interrupt status + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INTR_ENA + description: interrupt enable register + addressOffset: 20 + size: 32 + fields: + - name: FIFO_OVERFLOW_INTR_ENA + description: Set 1 enable fifo_overflow interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_FULL_INTR_ENA + description: Set 1 enable mem_full interrupt + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INTR_RAW + description: interrupt status register + addressOffset: 24 + size: 32 + fields: + - name: FIFO_OVERFLOW_INTR_RAW + description: fifo_overflow interrupt status + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: MEM_FULL_INTR_RAW + description: mem_full interrupt status + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INTR_CLR + description: interrupt clear register + addressOffset: 28 + size: 32 + fields: + - name: FIFO_OVERFLOW_INTR_CLR + description: Set 1 clr fifo overflow interrupt + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: MEM_FULL_INTR_CLR + description: Set 1 clr mem full interrupt + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: TRIGGER + description: trigger register + addressOffset: 32 + size: 32 + resetValue: 12 + fields: + - name: "ON" + description: "[0] set 1 start trace." + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: "OFF" + description: set 1 stop trace. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: MEM_LOOP + description: "if this reg is 1, trace will loop wrtie trace_mem. If is 0, when mem_current_addr at mem_end_addr, it will stop at the mem_end_addr" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RESTART_ENA + description: "enable encoder auto-restart, when lost package, the encoder will end, if enable auto-restart, when fifo empty, encoder will restart and send a sync package." + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: RESYNC_PROLONGED + description: resync configuration register + addressOffset: 36 + size: 32 + resetValue: 128 + fields: + - name: RESYNC_PROLONGED + description: "count number, when count to this value, send a sync package" + bitOffset: 0 + bitWidth: 24 + access: read-write + - name: RESYNC_MODE + description: "resyc mode sel: 0: default, cycle count 1: package num count" + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: CLOCK_GATE + description: Clock gate control register + addressOffset: 40 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: The bit is used to enable clock gate when access all registers in this module. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 1020 + size: 32 + resetValue: 35663920 + fields: + - name: DATE + description: version control register. Note that this default value stored is the latest date when the hardware logic was updated. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: TWAI0 + description: Two-Wire Automotive Interface + groupName: TWAI + baseAddress: 1610661888 + addressBlock: + - offset: 0 + size: 128 + usage: registers + interrupt: + - name: TWAI0 + value: 36 + registers: + - register: + name: MODE + description: TWAI mode register. + addressOffset: 0 + size: 32 + resetValue: 1 + fields: + - name: RESET_MODE + description: "1: reset, detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode. 0: normal, on the '1-to-0' transition of the reset mode bit, the TWAI controller returns to the operating mode." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LISTEN_ONLY_MODE + description: "1: listen only, in this mode the TWAI controller would give no acknowledge to the TWAI-bus, even if a message is received successfully. The error counters are stopped at the current value. 0: normal." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SELF_TEST_MODE + description: "1: self test, in this mode a full node test is possible without any other active node on the bus using the self reception request command. The TWAI controller will perform a successful transmission, even if there is no acknowledge received. 0: normal, an acknowledge is required for successful transmission." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_FILTER_MODE + description: "1:single, the single acceptance filter option is enabled (one filter with the length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled (two filters, each with the length of 16 bit are active)." + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: CMD + description: TWAI command register. + addressOffset: 4 + size: 32 + fields: + - name: TX_REQ + description: "1: present, a message shall be transmitted. 0: absent" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ABORT_TX + description: "1: present, if not already in progress, a pending transmission request is cancelled. 0: absent" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RELEASE_BUF + description: "1: released, the receive buffer, representing the message memory space in the RXFIFO is released. 0: no action" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CLEAR_DATA_OVERRUN + description: "1: clear, the data overrun status bit is cleared. 0: no action." + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SELF_RX_REQUEST + description: "1: present, a message shall be transmitted and received simultaneously. 0: absent." + bitOffset: 4 + bitWidth: 1 + access: write-only + - register: + name: STATUS + description: TWAI status register. + addressOffset: 8 + size: 32 + fields: + - name: RX_BUF_ST + description: "1: full, one or more complete messages are available in the RXFIFO. 0: empty, no message is available" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OVERRUN + description: "1: overrun, a message was lost because there was not enough space for that message in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data overrun command was given" + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TX_BUF_ST + description: "1: released, the CPU may write a message into the transmit buffer. 0: locked, the CPU cannot access the transmit buffer, a message is either waiting for transmission or is in the process of being transmitted" + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TRANSMISSION_COMPLETE + description: "1: complete, last requested transmission has been successfully completed. 0: incomplete, previously requested transmission is not yet completed" + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: RECEIVE + description: "1: receive, the TWAI controller is receiving a message. 0: idle" + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TRANSMIT + description: "1: transmit, the TWAI controller is transmitting a message. 0: idle" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ERR + description: "1: error, at least one of the error counters has reached or exceeded the CPU warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error counters are below the warning limit" + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BUS_OFF_ST + description: "1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the TWAI controller is involved in bus activities" + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: MISS_ST + description: "1: current message is destroyed because of FIFO overflow." + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INTERRUPT + description: "Interrupt signals' register." + addressOffset: 12 + size: 32 + fields: + - name: RECEIVE_INT_ST + description: "1: this bit is set while the receive FIFO is not empty and the RIE bit is set within the interrupt enable register. 0: reset" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TRANSMIT_INT_ST + description: "1: this bit is set whenever the transmit buffer status changes from '0-to-1' (released) and the TIE bit is set within the interrupt enable register. 0: reset" + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ERR_WARNING_INT_ST + description: "1: this bit is set on every change (set and clear) of either the error status or bus status bits and the EIE bit is set within the interrupt enable register. 0: reset" + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: DATA_OVERRUN_INT_ST + description: "1: this bit is set on a '0-to-1' transition of the data overrun status bit and the DOIE bit is set within the interrupt enable register. 0: reset" + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: ERR_PASSIVE_INT_ST + description: "1: this bit is set whenever the TWAI controller has reached the error passive status (at least one error counter exceeds the protocol-defined level of 127) or if the TWAI controller is in the error passive status and enters the error active status again and the EPIE bit is set within the interrupt enable register. 0: reset" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_ST + description: "1: this bit is set when the TWAI controller lost the arbitration and becomes a receiver and the ALIE bit is set within the interrupt enable register. 0: reset" + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BUS_ERR_INT_ST + description: "1: this bit is set when the TWAI controller detects an error on the TWAI-bus and the BEIE bit is set within the interrupt enable register. 0: reset" + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IDLE_INT_ST + description: "1: this bit is set when the TWAI controller detects state of TWAI become IDLE and this interrupt enable bit is set within the interrupt enable register. 0: reset" + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INTERRUPT_ENABLE + description: Interrupt enable register. + addressOffset: 16 + size: 32 + fields: + - name: EXT_RECEIVE_INT_ENA + description: "1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EXT_TRANSMIT_INT_ENA + description: "1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EXT_ERR_WARNING_INT_ENA + description: "1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EXT_DATA_OVERRUN_INT_ENA + description: "1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ERR_PASSIVE_INT_ENA + description: "1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: ARBITRATION_LOST_INT_ENA + description: "1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BUS_ERR_INT_ENA + description: "1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IDLE_INT_ENA + description: "1: enabled, if state of TWAI become IDLE, the TWAI controller requests the respective interrupt. 0: disable" + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: BUS_TIMING_0 + description: Bit timing configuration register 0. + addressOffset: 24 + size: 32 + fields: + - name: BAUD_PRESC + description: The period of the TWAI system clock is programmable and determines the individual bit timing. Software has R/W permission in reset mode and RO permission in operation mode. + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: SYNC_JUMP_WIDTH + description: The synchronization jump width defines the maximum number of clock cycles a bit period may be shortened or lengthened. Software has R/W permission in reset mode and RO in operation mode. + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: BUS_TIMING_1 + description: Bit timing configuration register 1. + addressOffset: 28 + size: 32 + fields: + - name: TIME_SEG1 + description: The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in reset mode and RO in operation mode. + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: TIME_SEG2 + description: The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in reset mode and RO in operation mode. + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: TIME_SAMP + description: "1: triple, the bus is sampled three times. 0: single, the bus is sampled once. Software has R/W permission in reset mode and RO in operation mode." + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: ARB_LOST_CAP + description: TWAI arbiter lost capture register. + addressOffset: 44 + size: 32 + fields: + - name: ARBITRATION_LOST_CAPTURE + description: This register contains information about the bit position of losing arbitration. + bitOffset: 0 + bitWidth: 5 + access: read-only + - register: + name: ERR_CODE_CAP + description: TWAI error info capture register. + addressOffset: 48 + size: 32 + fields: + - name: ERR_CAPTURE_CODE_SEGMENT + description: This register contains information about the location of errors on the bus. + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: ERR_CAPTURE_CODE_DIRECTION + description: "1: RX, error occurred during reception. 0: TX, error occurred during transmission." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ERR_CAPTURE_CODE_TYPE + description: "00: bit error. 01: form error. 10:stuff error. 11:other type of error." + bitOffset: 6 + bitWidth: 2 + access: read-only + - register: + name: ERR_WARNING_LIMIT + description: TWAI error threshold configuration register. + addressOffset: 52 + size: 32 + resetValue: 96 + fields: + - name: ERR_WARNING_LIMIT + description: The threshold that trigger error warning interrupt when this interrupt is enabled. Software has R/W permission in reset mode and RO in operation mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: RX_ERR_CNT + description: Rx error counter register. + addressOffset: 56 + size: 32 + fields: + - name: RX_ERR_CNT + description: The RX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: TX_ERR_CNT + description: Tx error counter register. + addressOffset: 60 + size: 32 + fields: + - name: TX_ERR_CNT + description: The TX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_0 + description: Data register 0. + addressOffset: 64 + size: 32 + fields: + - name: TX_BYTE_0 + description: "In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 0 and when software initiate read operation, it is rx data register 0." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_1 + description: Data register 1. + addressOffset: 68 + size: 32 + fields: + - name: TX_BYTE_1 + description: "In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 1 and when software initiate read operation, it is rx data register 1." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_2 + description: Data register 2. + addressOffset: 72 + size: 32 + fields: + - name: TX_BYTE_2 + description: "In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 2 and when software initiate read operation, it is rx data register 2." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_3 + description: Data register 3. + addressOffset: 76 + size: 32 + fields: + - name: TX_BYTE_3 + description: "In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 3 and when software initiate read operation, it is rx data register 3." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_4 + description: Data register 4. + addressOffset: 80 + size: 32 + fields: + - name: TX_BYTE_4 + description: "In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 4 and when software initiate read operation, it is rx data register 4." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_5 + description: Data register 5. + addressOffset: 84 + size: 32 + fields: + - name: TX_BYTE_5 + description: "In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 5 and when software initiate read operation, it is rx data register 5." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_6 + description: Data register 6. + addressOffset: 88 + size: 32 + fields: + - name: TX_BYTE_6 + description: "In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 6 and when software initiate read operation, it is rx data register 6." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_7 + description: Data register 7. + addressOffset: 92 + size: 32 + fields: + - name: TX_BYTE_7 + description: "In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 7 and when software initiate read operation, it is rx data register 7." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_8 + description: Data register 8. + addressOffset: 96 + size: 32 + fields: + - name: TX_BYTE_8 + description: "In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 8 and when software initiate read operation, it is rx data register 8." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_9 + description: Data register 9. + addressOffset: 100 + size: 32 + fields: + - name: TX_BYTE_9 + description: "In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 9 and when software initiate read operation, it is rx data register 9." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_10 + description: Data register 10. + addressOffset: 104 + size: 32 + fields: + - name: TX_BYTE_10 + description: "In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 10 and when software initiate read operation, it is rx data register 10." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_11 + description: Data register 11. + addressOffset: 108 + size: 32 + fields: + - name: TX_BYTE_11 + description: "In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 11 and when software initiate read operation, it is rx data register 11." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_12 + description: Data register 12. + addressOffset: 112 + size: 32 + fields: + - name: TX_BYTE_12 + description: "In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 12 and when software initiate read operation, it is rx data register 12." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: RX_MESSAGE_CNT + description: Received message counter register. + addressOffset: 116 + size: 32 + fields: + - name: RX_MESSAGE_COUNTER + description: Reflects the number of messages available within the RXFIFO. The value is incremented with each receive event and decremented by the release receive buffer command. + bitOffset: 0 + bitWidth: 7 + access: read-only + - register: + name: CLOCK_DIVIDER + description: Clock divider register. + addressOffset: 124 + size: 32 + fields: + - name: CD + description: These bits are used to define the frequency at the external CLKOUT pin. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CLOCK_OFF + description: "1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has R/W permission in reset mode and RO in operation mode." + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: SW_STANDBY_CFG + description: Software configure standby pin directly. + addressOffset: 128 + size: 32 + resetValue: 2 + fields: + - name: SW_STANDBY_EN + description: Enable standby pin. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SW_STANDBY_CLR + description: Clear standby pin. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: HW_CFG + description: Hardware configure standby pin. + addressOffset: 132 + size: 32 + fields: + - name: HW_STANDBY_EN + description: Enable function that hardware control standby pin. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: HW_STANDBY_CNT + description: Configure standby counter. + addressOffset: 136 + size: 32 + resetValue: 1 + fields: + - name: STANDBY_WAIT_CNT + description: Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN is enabled. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: IDLE_INTR_CNT + description: Configure idle interrupt counter. + addressOffset: 140 + size: 32 + resetValue: 1 + fields: + - name: IDLE_INTR_CNT + description: Configure the number of cycles before triggering idle interrupt. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ECO_CFG + description: ECO configuration register. + addressOffset: 144 + size: 32 + resetValue: 2 + fields: + - name: RDN_ENA + description: Enable eco module. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RDN_RESULT + description: Output of eco module. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: UART0 + description: UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + groupName: UART + baseAddress: 1610612736 + addressBlock: + - offset: 0 + size: 152 + usage: registers + interrupt: + - name: UART0 + value: 33 + registers: + - register: + name: FIFO + description: FIFO data register + addressOffset: 0 + size: 32 + fields: + - name: RXFIFO_RD_BYTE + description: UART 0 accesses FIFO via this register. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 4 + size: 32 + resetValue: 2 + fields: + - name: RXFIFO_FULL_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_EMPTY_INT_RAW + description: This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PARITY_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a parity error in the data. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FRM_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a data frame error . + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DSR_CHG_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CTS_CHG_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BRK_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RXFIFO_TOUT_INT_RAW + description: This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SW_XON_INT_RAW + description: This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SW_XOFF_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GLITCH_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_BRK_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_BRK_IDLE_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RS485_PARITY_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RS485_FRM_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RS485_CLASH_INT_RAW + description: This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: AT_CMD_CHAR_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: WAKEUP_INT_RAW + description: This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 8 + size: 32 + fields: + - name: RXFIFO_FULL_INT_ST + description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_EMPTY_INT_ST + description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: PARITY_ERR_INT_ST + description: This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FRM_ERR_INT_ST + description: This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_ST + description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DSR_CHG_INT_ST + description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CTS_CHG_INT_ST + description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BRK_DET_INT_ST + description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: RXFIFO_TOUT_INT_ST + description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SW_XON_INT_ST + description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SW_XOFF_INT_ST + description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: GLITCH_DET_INT_ST + description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TX_BRK_DONE_INT_ST + description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: TX_BRK_IDLE_DONE_INT_ST + description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_ST + description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: RS485_PARITY_ERR_INT_ST + description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: RS485_FRM_ERR_INT_ST + description: This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: RS485_CLASH_INT_ST + description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: AT_CMD_CHAR_DET_INT_ST + description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: WAKEUP_INT_ST + description: This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + bitOffset: 19 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 12 + size: 32 + fields: + - name: RXFIFO_FULL_INT_ENA + description: This is the enable bit for rxfifo_full_int_st register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_EMPTY_INT_ENA + description: This is the enable bit for txfifo_empty_int_st register. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PARITY_ERR_INT_ENA + description: This is the enable bit for parity_err_int_st register. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FRM_ERR_INT_ENA + description: This is the enable bit for frm_err_int_st register. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_ENA + description: This is the enable bit for rxfifo_ovf_int_st register. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DSR_CHG_INT_ENA + description: This is the enable bit for dsr_chg_int_st register. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CTS_CHG_INT_ENA + description: This is the enable bit for cts_chg_int_st register. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BRK_DET_INT_ENA + description: This is the enable bit for brk_det_int_st register. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RXFIFO_TOUT_INT_ENA + description: This is the enable bit for rxfifo_tout_int_st register. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SW_XON_INT_ENA + description: This is the enable bit for sw_xon_int_st register. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SW_XOFF_INT_ENA + description: This is the enable bit for sw_xoff_int_st register. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GLITCH_DET_INT_ENA + description: This is the enable bit for glitch_det_int_st register. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_BRK_DONE_INT_ENA + description: This is the enable bit for tx_brk_done_int_st register. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_BRK_IDLE_DONE_INT_ENA + description: This is the enable bit for tx_brk_idle_done_int_st register. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_ENA + description: This is the enable bit for tx_done_int_st register. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RS485_PARITY_ERR_INT_ENA + description: This is the enable bit for rs485_parity_err_int_st register. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RS485_FRM_ERR_INT_ENA + description: This is the enable bit for rs485_parity_err_int_st register. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RS485_CLASH_INT_ENA + description: This is the enable bit for rs485_clash_int_st register. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: AT_CMD_CHAR_DET_INT_ENA + description: This is the enable bit for at_cmd_char_det_int_st register. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: WAKEUP_INT_ENA + description: This is the enable bit for uart_wakeup_int_st register. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 16 + size: 32 + fields: + - name: RXFIFO_FULL_INT_CLR + description: Set this bit to clear the rxfifo_full_int_raw interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TXFIFO_EMPTY_INT_CLR + description: Set this bit to clear txfifo_empty_int_raw interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: PARITY_ERR_INT_CLR + description: Set this bit to clear parity_err_int_raw interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: FRM_ERR_INT_CLR + description: Set this bit to clear frm_err_int_raw interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: RXFIFO_OVF_INT_CLR + description: Set this bit to clear rxfifo_ovf_int_raw interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: DSR_CHG_INT_CLR + description: Set this bit to clear the dsr_chg_int_raw interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CTS_CHG_INT_CLR + description: Set this bit to clear the cts_chg_int_raw interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: BRK_DET_INT_CLR + description: Set this bit to clear the brk_det_int_raw interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: RXFIFO_TOUT_INT_CLR + description: Set this bit to clear the rxfifo_tout_int_raw interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SW_XON_INT_CLR + description: Set this bit to clear the sw_xon_int_raw interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SW_XOFF_INT_CLR + description: Set this bit to clear the sw_xoff_int_raw interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: GLITCH_DET_INT_CLR + description: Set this bit to clear the glitch_det_int_raw interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TX_BRK_DONE_INT_CLR + description: Set this bit to clear the tx_brk_done_int_raw interrupt.. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: TX_BRK_IDLE_DONE_INT_CLR + description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: TX_DONE_INT_CLR + description: Set this bit to clear the tx_done_int_raw interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: RS485_PARITY_ERR_INT_CLR + description: Set this bit to clear the rs485_parity_err_int_raw interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: RS485_FRM_ERR_INT_CLR + description: Set this bit to clear the rs485_frm_err_int_raw interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: RS485_CLASH_INT_CLR + description: Set this bit to clear the rs485_clash_int_raw interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: AT_CMD_CHAR_DET_INT_CLR + description: Set this bit to clear the at_cmd_char_det_int_raw interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: WAKEUP_INT_CLR + description: Set this bit to clear the uart_wakeup_int_raw interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - register: + name: CLKDIV + description: Clock divider configuration + addressOffset: 20 + size: 32 + resetValue: 694 + fields: + - name: CLKDIV + description: The integral part of the frequency divider factor. + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: FRAG + description: The decimal part of the frequency divider factor. + bitOffset: 20 + bitWidth: 4 + access: read-write + - register: + name: RX_FILT + description: Rx Filter configuration + addressOffset: 24 + size: 32 + resetValue: 8 + fields: + - name: GLITCH_FILT + description: when input pulse width is lower than this value the pulse is ignored. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GLITCH_FILT_EN + description: Set this bit to enable Rx signal filter. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: STATUS + description: UART status register + addressOffset: 28 + size: 32 + resetValue: 3758145536 + fields: + - name: RXFIFO_CNT + description: Stores the byte number of valid data in Rx-FIFO. + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: DSRN + description: The register represent the level value of the internal uart dsr signal. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: CTSN + description: This register represent the level value of the internal uart cts signal. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: RXD + description: This register represent the level value of the internal uart rxd signal. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TXFIFO_CNT + description: Stores the byte number of data in Tx-FIFO. + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: DTRN + description: This bit represents the level of the internal uart dtr signal. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: RTSN + description: This bit represents the level of the internal uart rts signal. + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: TXD + description: This bit represents the level of the internal uart txd signal. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CONF0 + description: a + addressOffset: 32 + size: 32 + resetValue: 1048604 + fields: + - name: PARITY + description: This register is used to configure the parity check mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PARITY_EN + description: Set this bit to enable uart parity check. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BIT_NUM + description: This register is used to set the length of data. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: STOP_BIT_NUM + description: This register is used to set the length of stop bit. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: TXD_BRK + description: Set this bit to enbale transmitter to send NULL when the process of sending data is done. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: IRDA_DPLX + description: Set this bit to enable IrDA loopback mode. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IRDA_TX_EN + description: This is the start enable bit for IrDA transmitter. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: IRDA_WCTL + description: "1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: IRDA_TX_INV + description: Set this bit to invert the level of IrDA transmitter. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: IRDA_RX_INV + description: Set this bit to invert the level of IrDA receiver. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: LOOPBACK + description: Set this bit to enable uart loopback test mode. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_FLOW_EN + description: Set this bit to enable flow control function for transmitter. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: IRDA_EN + description: Set this bit to enable IrDA protocol. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RXD_INV + description: Set this bit to inverse the level value of uart rxd signal. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TXD_INV + description: Set this bit to inverse the level value of uart txd signal. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DIS_RX_DAT_OVF + description: Disable UART Rx data overflow detect. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: ERR_WR_MASK + description: "1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: AUTOBAUD_EN + description: This is the enable bit for detecting baudrate. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: MEM_CLK_EN + description: UART memory clock gate enable signal. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SW_RTS + description: This register is used to configure the software rts signal which is used in software flow control. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: RXFIFO_RST + description: Set this bit to reset the uart receive-FIFO. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TXFIFO_RST + description: Set this bit to reset the uart transmit-FIFO. + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: CONF1 + description: Configuration register 1 + addressOffset: 36 + size: 32 + resetValue: 24672 + fields: + - name: RXFIFO_FULL_THRHD + description: It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TXFIFO_EMPTY_THRHD + description: It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: CTS_INV + description: Set this bit to inverse the level value of uart cts signal. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DSR_INV + description: Set this bit to inverse the level value of uart dsr signal. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: RTS_INV + description: Set this bit to inverse the level value of uart rts signal. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: DTR_INV + description: Set this bit to inverse the level value of uart dtr signal. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SW_DTR + description: This register is used to configure the software dtr signal which is used in software flow control. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers." + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + name: HWFC_CONF + description: Hardware flow-control configuration + addressOffset: 44 + size: 32 + fields: + - name: RX_FLOW_THRHD + description: This register is used to configure the maximum amount of data that can be received when hardware flow control works. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: RX_FLOW_EN + description: This is the flow enable bit for UART receiver. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: SLEEP_CONF0 + description: UART sleep configure register 0 + addressOffset: 48 + size: 32 + fields: + - name: WK_CHAR1 + description: This register restores the specified wake up char1 to wake up + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: WK_CHAR2 + description: This register restores the specified wake up char2 to wake up + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: WK_CHAR3 + description: This register restores the specified wake up char3 to wake up + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: WK_CHAR4 + description: This register restores the specified wake up char4 to wake up + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: SLEEP_CONF1 + description: UART sleep configure register 1 + addressOffset: 52 + size: 32 + fields: + - name: WK_CHAR0 + description: This register restores the specified char0 to wake up + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: SLEEP_CONF2 + description: UART sleep configure register 2 + addressOffset: 56 + size: 32 + resetValue: 1311984 + fields: + - name: ACTIVE_THRESHOLD + description: The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: RX_WAKE_UP_THRHD + description: In wake up mode 1 this field is used to set the received data number threshold to wake up chip. + bitOffset: 10 + bitWidth: 8 + access: read-write + - name: WK_CHAR_NUM + description: This register is used to select number of wake up char. + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: WK_CHAR_MASK + description: This register is used to mask wake up char. + bitOffset: 21 + bitWidth: 5 + access: read-write + - name: WK_MODE_SEL + description: "This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than" + bitOffset: 26 + bitWidth: 2 + access: read-write + - register: + name: SWFC_CONF0 + description: Software flow-control character configuration + addressOffset: 60 + size: 32 + resetValue: 4881 + fields: + - name: XON_CHAR + description: This register stores the Xon flow control char. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: XOFF_CHAR + description: This register stores the Xoff flow control char. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: XON_XOFF_STILL_SEND + description: "In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SW_FLOW_CON_EN + description: Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: XONOFF_DEL + description: Set this bit to remove flow control char from the received data. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: FORCE_XON + description: Set this bit to enable the transmitter to go on sending data. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: FORCE_XOFF + description: Set this bit to stop the transmitter from sending data. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SEND_XON + description: Set this bit to send Xon char. It is cleared by hardware automatically. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SEND_XOFF + description: Set this bit to send Xoff char. It is cleared by hardware automatically. + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: SWFC_CONF1 + description: Software flow-control character configuration + addressOffset: 64 + size: 32 + resetValue: 57344 + fields: + - name: XON_THRESHOLD + description: When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: XOFF_THRESHOLD + description: When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char. + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: TXBRK_CONF + description: Tx Break character configuration + addressOffset: 68 + size: 32 + resetValue: 10 + fields: + - name: TX_BRK_NUM + description: This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: IDLE_CONF + description: Frame-end idle configuration + addressOffset: 72 + size: 32 + resetValue: 262400 + fields: + - name: RX_IDLE_THRHD + description: It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: TX_IDLE_NUM + description: This register is used to configure the duration time between transfers. + bitOffset: 10 + bitWidth: 10 + access: read-write + - register: + name: RS485_CONF + description: RS485 mode configuration + addressOffset: 76 + size: 32 + fields: + - name: RS485_EN + description: Set this bit to choose the rs485 mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DL0_EN + description: Set this bit to delay the stop bit by 1 bit. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DL1_EN + description: Set this bit to delay the stop bit by 1 bit. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RS485TX_RX_EN + description: Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RS485RXBY_TX_EN + description: "1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RS485_RX_DLY_NUM + description: "This register is used to delay the receiver's internal data signal." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RS485_TX_DLY_NUM + description: "This register is used to delay the transmitter's internal data signal." + bitOffset: 6 + bitWidth: 4 + access: read-write + - register: + name: AT_CMD_PRECNT + description: Pre-sequence timing configuration + addressOffset: 80 + size: 32 + resetValue: 2305 + fields: + - name: PRE_IDLE_NUM + description: This register is used to configure the idle duration time before the first at_cmd is received by receiver. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_POSTCNT + description: Post-sequence timing configuration + addressOffset: 84 + size: 32 + resetValue: 2305 + fields: + - name: POST_IDLE_NUM + description: This register is used to configure the duration time between the last at_cmd and the next data. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_GAPTOUT + description: Timeout configuration + addressOffset: 88 + size: 32 + resetValue: 11 + fields: + - name: RX_GAP_TOUT + description: This register is used to configure the duration time between the at_cmd chars. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_CHAR + description: AT escape sequence detection configuration + addressOffset: 92 + size: 32 + resetValue: 811 + fields: + - name: AT_CMD_CHAR + description: This register is used to configure the content of at_cmd char. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CHAR_NUM + description: This register is used to configure the num of continuous at_cmd chars received by receiver. + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: MEM_CONF + description: UART memory power configuration + addressOffset: 96 + size: 32 + fields: + - name: MEM_FORCE_PD + description: Set this bit to force power down UART memory. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PU + description: Set this bit to force power up UART memory. + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: TOUT_CONF + description: UART threshold and allocation configuration + addressOffset: 100 + size: 32 + resetValue: 40 + fields: + - name: RX_TOUT_EN + description: "This is the enble bit for uart receiver's timeout function." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_TOUT_FLOW_DIS + description: Set this bit to stop accumulating idle_cnt when hardware flow control works. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_TOUT_THRHD + description: This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + bitOffset: 2 + bitWidth: 10 + access: read-write + - register: + name: MEM_TX_STATUS + description: Tx-SRAM write and read offset address. + addressOffset: 104 + size: 32 + fields: + - name: TX_SRAM_WADDR + description: This register stores the offset write address in Tx-SRAM. + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: TX_SRAM_RADDR + description: This register stores the offset read address in Tx-SRAM. + bitOffset: 9 + bitWidth: 8 + access: read-only + - register: + name: MEM_RX_STATUS + description: Rx-SRAM write and read offset address. + addressOffset: 108 + size: 32 + resetValue: 65664 + fields: + - name: RX_SRAM_RADDR + description: This register stores the offset read address in RX-SRAM. + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: RX_SRAM_WADDR + description: This register stores the offset write address in Rx-SRAM. + bitOffset: 9 + bitWidth: 8 + access: read-only + - register: + name: FSM_STATUS + description: UART transmit and receive status. + addressOffset: 112 + size: 32 + fields: + - name: ST_URX_OUT + description: This is the status register of receiver. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: ST_UTX_OUT + description: This is the status register of transmitter. + bitOffset: 4 + bitWidth: 4 + access: read-only + - register: + name: POSPULSE + description: Autobaud high pulse register + addressOffset: 116 + size: 32 + resetValue: 4095 + fields: + - name: POSEDGE_MIN_CNT + description: This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process. + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: NEGPULSE + description: Autobaud low pulse register + addressOffset: 120 + size: 32 + resetValue: 4095 + fields: + - name: NEGEDGE_MIN_CNT + description: This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process. + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: LOWPULSE + description: Autobaud minimum low pulse duration register + addressOffset: 124 + size: 32 + resetValue: 4095 + fields: + - name: MIN_CNT + description: This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process. + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: HIGHPULSE + description: Autobaud minimum high pulse duration register + addressOffset: 128 + size: 32 + resetValue: 4095 + fields: + - name: MIN_CNT + description: This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process. + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: RXD_CNT + description: Autobaud edge change count register + addressOffset: 132 + size: 32 + fields: + - name: RXD_EDGE_CNT + description: This register stores the count of rxd edge change. It is used in baud rate-detect process. + bitOffset: 0 + bitWidth: 10 + access: read-only + - register: + name: CLK_CONF + description: UART core clock configuration + addressOffset: 136 + size: 32 + resetValue: 50331648 + fields: + - name: TX_SCLK_EN + description: Set this bit to enable UART Tx clock. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SCLK_EN + description: Set this bit to enable UART Rx clock. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TX_RST_CORE + description: Write 1 then write 0 to this bit to reset UART Tx. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RST_CORE + description: Write 1 then write 0 to this bit to reset UART Rx. + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: UART Version register + addressOffset: 140 + size: 32 + resetValue: 35680848 + fields: + - name: DATE + description: This is the version register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: AFIFO_STATUS + description: UART AFIFO Status + addressOffset: 144 + size: 32 + resetValue: 10 + fields: + - name: TX_AFIFO_FULL + description: Full signal of APB TX AFIFO. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_AFIFO_EMPTY + description: Empty signal of APB TX AFIFO. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_AFIFO_FULL + description: Full signal of APB RX AFIFO. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: RX_AFIFO_EMPTY + description: Empty signal of APB RX AFIFO. + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: REG_UPDATE + description: UART Registers Configuration Update register + addressOffset: 152 + size: 32 + fields: + - name: REG_UPDATE + description: Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: ID + description: UART ID register + addressOffset: 156 + size: 32 + resetValue: 1280 + fields: + - name: ID + description: This register is used to configure the uart_id. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: UART1 + description: UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + baseAddress: 1610616832 + interrupt: + - name: UART1 + value: 34 + derivedFrom: UART0 + - name: UHCI0 + description: Universal Host Controller Interface 0 + groupName: UHCI + baseAddress: 1610637312 + addressBlock: + - offset: 0 + size: 132 + usage: registers + interrupt: + - name: UHCI0 + value: 32 + registers: + - register: + name: CONF0 + description: a + addressOffset: 0 + size: 32 + resetValue: 1760 + fields: + - name: TX_RST + description: Write 1 then write 0 to this bit to reset decode state machine. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_RST + description: Write 1 then write 0 to this bit to reset encode state machine. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UART0_CE + description: Set this bit to link up HCI and UART0. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: UART1_CE + description: Set this bit to link up HCI and UART1. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SEPER_EN + description: Set this bit to separate the data frame using a special char. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: HEAD_EN + description: Set this bit to encode the data packet with a formatting header. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CRC_REC_EN + description: Set this bit to enable UHCI to receive the 16 bit CRC. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: UART_IDLE_EOF_EN + description: If this bit is set to 1 UHCI will end the payload receiving process when UART has been in idle state. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: LEN_EOF_EN + description: If this bit is set to 1 UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: ENCODE_CRC_EN + description: Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: UART_RX_BRK_EOF_EN + description: If this bit is set to 1 UHCI will end payload receive process when NULL frame is received by UART. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: a + addressOffset: 4 + size: 32 + fields: + - name: RX_START_INT_RAW + description: a + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_START_INT_RAW + description: a + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_HUNG_INT_RAW + description: a + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_HUNG_INT_RAW + description: a + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SEND_S_REG_Q_INT_RAW + description: a + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SEND_A_REG_Q_INT_RAW + description: a + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUT_EOF_INT_RAW + description: This is the interrupt raw bit. Triggered when there are some errors in EOF in the + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: APP_CTRL0_INT_RAW + description: Soft control int raw bit. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: APP_CTRL1_INT_RAW + description: Soft control int raw bit. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: a + addressOffset: 8 + size: 32 + fields: + - name: RX_START_INT_ST + description: a + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_START_INT_ST + description: a + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_ST + description: a + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_ST + description: a + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SEND_S_REG_Q_INT_ST + description: a + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SEND_A_REG_Q_INT_ST + description: a + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OUTLINK_EOF_ERR_INT_ST + description: a + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: APP_CTRL0_INT_ST + description: a + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: APP_CTRL1_INT_ST + description: a + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: a + addressOffset: 12 + size: 32 + fields: + - name: RX_START_INT_ENA + description: a + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_START_INT_ENA + description: a + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_HUNG_INT_ENA + description: a + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_HUNG_INT_ENA + description: a + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SEND_S_REG_Q_INT_ENA + description: a + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SEND_A_REG_Q_INT_ENA + description: a + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUTLINK_EOF_ERR_INT_ENA + description: a + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: APP_CTRL0_INT_ENA + description: a + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: APP_CTRL1_INT_ENA + description: a + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: a + addressOffset: 16 + size: 32 + fields: + - name: RX_START_INT_CLR + description: a + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TX_START_INT_CLR + description: a + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_HUNG_INT_CLR + description: a + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TX_HUNG_INT_CLR + description: a + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SEND_S_REG_Q_INT_CLR + description: a + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SEND_A_REG_Q_INT_CLR + description: a + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: OUTLINK_EOF_ERR_INT_CLR + description: a + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: APP_CTRL0_INT_CLR + description: a + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: APP_CTRL1_INT_CLR + description: a + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: CONF1 + description: a + addressOffset: 20 + size: 32 + resetValue: 51 + fields: + - name: CHECK_SUM_EN + description: a + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CHECK_SEQ_EN + description: a + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CRC_DISABLE + description: a + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SAVE_HEAD + description: a + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_CHECK_SUM_RE + description: a + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TX_ACK_NUM_RE + description: a + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: WAIT_SW_START + description: a + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SW_START + description: a + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: STATE0 + description: a + addressOffset: 24 + size: 32 + fields: + - name: RX_ERR_CAUSE + description: a + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: DECODE_STATE + description: a + bitOffset: 3 + bitWidth: 3 + access: read-only + - register: + name: STATE1 + description: a + addressOffset: 28 + size: 32 + fields: + - name: ENCODE_STATE + description: a + bitOffset: 0 + bitWidth: 3 + access: read-only + - register: + name: ESCAPE_CONF + description: a + addressOffset: 32 + size: 32 + resetValue: 51 + fields: + - name: TX_C0_ESC_EN + description: a + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_DB_ESC_EN + description: a + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TX_11_ESC_EN + description: a + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_13_ESC_EN + description: a + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_C0_ESC_EN + description: a + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_DB_ESC_EN + description: a + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RX_11_ESC_EN + description: a + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_13_ESC_EN + description: a + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: HUNG_CONF + description: a + addressOffset: 36 + size: 32 + resetValue: 8456208 + fields: + - name: TXFIFO_TIMEOUT + description: a + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TXFIFO_TIMEOUT_SHIFT + description: a + bitOffset: 8 + bitWidth: 3 + access: read-write + - name: TXFIFO_TIMEOUT_ENA + description: a + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RXFIFO_TIMEOUT + description: a + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: RXFIFO_TIMEOUT_SHIFT + description: a + bitOffset: 20 + bitWidth: 3 + access: read-write + - name: RXFIFO_TIMEOUT_ENA + description: a + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: ACK_NUM + description: a + addressOffset: 40 + size: 32 + fields: + - name: ACK_NUM + description: a + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: LOAD + description: a + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: RX_HEAD + description: a + addressOffset: 44 + size: 32 + fields: + - name: RX_HEAD + description: a + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: QUICK_SENT + description: a + addressOffset: 48 + size: 32 + fields: + - name: SINGLE_SEND_NUM + description: a + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SINGLE_SEND_EN + description: a + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: ALWAYS_SEND_NUM + description: a + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: ALWAYS_SEND_EN + description: a + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: REG_Q0_WORD0 + description: a + addressOffset: 52 + size: 32 + fields: + - name: SEND_Q0_WORD0 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q0_WORD1 + description: a + addressOffset: 56 + size: 32 + fields: + - name: SEND_Q0_WORD1 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q1_WORD0 + description: a + addressOffset: 60 + size: 32 + fields: + - name: SEND_Q1_WORD0 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q1_WORD1 + description: a + addressOffset: 64 + size: 32 + fields: + - name: SEND_Q1_WORD1 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q2_WORD0 + description: a + addressOffset: 68 + size: 32 + fields: + - name: SEND_Q2_WORD0 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q2_WORD1 + description: a + addressOffset: 72 + size: 32 + fields: + - name: SEND_Q2_WORD1 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q3_WORD0 + description: a + addressOffset: 76 + size: 32 + fields: + - name: SEND_Q3_WORD0 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q3_WORD1 + description: a + addressOffset: 80 + size: 32 + fields: + - name: SEND_Q3_WORD1 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q4_WORD0 + description: a + addressOffset: 84 + size: 32 + fields: + - name: SEND_Q4_WORD0 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q4_WORD1 + description: a + addressOffset: 88 + size: 32 + fields: + - name: SEND_Q4_WORD1 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q5_WORD0 + description: a + addressOffset: 92 + size: 32 + fields: + - name: SEND_Q5_WORD0 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q5_WORD1 + description: a + addressOffset: 96 + size: 32 + fields: + - name: SEND_Q5_WORD1 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q6_WORD0 + description: a + addressOffset: 100 + size: 32 + fields: + - name: SEND_Q6_WORD0 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q6_WORD1 + description: a + addressOffset: 104 + size: 32 + fields: + - name: SEND_Q6_WORD1 + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ESC_CONF0 + description: a + addressOffset: 108 + size: 32 + resetValue: 14474176 + fields: + - name: SEPER_CHAR + description: a + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SEPER_ESC_CHAR0 + description: a + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SEPER_ESC_CHAR1 + description: a + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: ESC_CONF1 + description: a + addressOffset: 112 + size: 32 + resetValue: 14539739 + fields: + - name: ESC_SEQ0 + description: a + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: ESC_SEQ0_CHAR0 + description: a + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: ESC_SEQ0_CHAR1 + description: a + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: ESC_CONF2 + description: a + addressOffset: 116 + size: 32 + resetValue: 14605073 + fields: + - name: ESC_SEQ1 + description: a + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: ESC_SEQ1_CHAR0 + description: a + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: ESC_SEQ1_CHAR1 + description: a + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: ESC_CONF3 + description: a + addressOffset: 120 + size: 32 + resetValue: 14670611 + fields: + - name: ESC_SEQ2 + description: a + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: ESC_SEQ2_CHAR0 + description: a + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: ESC_SEQ2_CHAR1 + description: a + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: PKT_THRES + description: a + addressOffset: 124 + size: 32 + resetValue: 128 + fields: + - name: PKT_THRS + description: a + bitOffset: 0 + bitWidth: 13 + access: read-write + - register: + name: DATE + description: a + addressOffset: 128 + size: 32 + resetValue: 35655936 + fields: + - name: DATE + description: a + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: USB_DEVICE + description: Full-speed USB Serial/JTAG Controller + groupName: USB_DEVICE + baseAddress: 1610674176 + addressBlock: + - offset: 0 + size: 112 + usage: registers + interrupt: + - name: USB_DEVICE + value: 37 + registers: + - register: + name: EP1 + description: FIFO access for the CDC-ACM data IN and OUT endpoints. + addressOffset: 0 + size: 32 + fields: + - name: RDWR_BYTE + description: "Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: EP1_CONF + description: Configuration and control registers for the CDC-ACM FIFOs. + addressOffset: 4 + size: 32 + resetValue: 2 + fields: + - name: WR_DONE + description: Set this bit to indicate writing byte data to UART Tx FIFO is done. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SERIAL_IN_EP_DATA_FREE + description: "1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SERIAL_OUT_EP_DATA_AVAIL + description: "1'b1: Indicate there is data in UART Rx FIFO." + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: INT_RAW + description: Interrupt raw status register. + addressOffset: 8 + size: 32 + resetValue: 8 + fields: + - name: JTAG_IN_FLUSH_INT_RAW + description: The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SOF_INT_RAW + description: The raw interrupt bit turns to high level when SOF frame is received. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SERIAL_OUT_RECV_PKT_INT_RAW + description: The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SERIAL_IN_EMPTY_INT_RAW + description: The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PID_ERR_INT_RAW + description: The raw interrupt bit turns to high level when pid error is detected. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CRC5_ERR_INT_RAW + description: The raw interrupt bit turns to high level when CRC5 error is detected. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CRC16_ERR_INT_RAW + description: The raw interrupt bit turns to high level when CRC16 error is detected. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: STUFF_ERR_INT_RAW + description: The raw interrupt bit turns to high level when stuff error is detected. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IN_TOKEN_REC_IN_EP1_INT_RAW + description: The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: USB_BUS_RESET_INT_RAW + description: The raw interrupt bit turns to high level when usb bus reset is detected. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OUT_EP1_ZERO_PAYLOAD_INT_RAW + description: The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OUT_EP2_ZERO_PAYLOAD_INT_RAW + description: The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RTS_CHG_INT_RAW + description: The raw interrupt bit turns to high level when level of RTS from usb serial channel is changed. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DTR_CHG_INT_RAW + description: The raw interrupt bit turns to high level when level of DTR from usb serial channel is changed. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: GET_LINE_CODE_INT_RAW + description: The raw interrupt bit turns to high level when level of GET LINE CODING request is received. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SET_LINE_CODE_INT_RAW + description: The raw interrupt bit turns to high level when level of SET LINE CODING request is received. + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Interrupt status register. + addressOffset: 12 + size: 32 + fields: + - name: JTAG_IN_FLUSH_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SOF_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SERIAL_OUT_RECV_PKT_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SERIAL_IN_EMPTY_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: PID_ERR_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: CRC5_ERR_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CRC16_ERR_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: STUFF_ERR_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IN_TOKEN_REC_IN_EP1_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: USB_BUS_RESET_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: OUT_EP1_ZERO_PAYLOAD_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: OUT_EP2_ZERO_PAYLOAD_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: RTS_CHG_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: DTR_CHG_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: GET_LINE_CODE_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SET_LINE_CODE_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable status register. + addressOffset: 16 + size: 32 + fields: + - name: JTAG_IN_FLUSH_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SOF_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SERIAL_OUT_RECV_PKT_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SERIAL_IN_EMPTY_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PID_ERR_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CRC5_ERR_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CRC16_ERR_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: STUFF_ERR_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IN_TOKEN_REC_IN_EP1_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: USB_BUS_RESET_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OUT_EP1_ZERO_PAYLOAD_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OUT_EP2_ZERO_PAYLOAD_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RTS_CHG_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DTR_CHG_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: GET_LINE_CODE_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SET_LINE_CODE_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear status register. + addressOffset: 20 + size: 32 + fields: + - name: JTAG_IN_FLUSH_INT_CLR + description: Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SOF_INT_CLR + description: Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SERIAL_OUT_RECV_PKT_INT_CLR + description: Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SERIAL_IN_EMPTY_INT_CLR + description: Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: PID_ERR_INT_CLR + description: Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: CRC5_ERR_INT_CLR + description: Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CRC16_ERR_INT_CLR + description: Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: STUFF_ERR_INT_CLR + description: Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: IN_TOKEN_REC_IN_EP1_INT_CLR + description: Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: USB_BUS_RESET_INT_CLR + description: Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: OUT_EP1_ZERO_PAYLOAD_INT_CLR + description: Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: OUT_EP2_ZERO_PAYLOAD_INT_CLR + description: Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: RTS_CHG_INT_CLR + description: Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: DTR_CHG_INT_CLR + description: Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: GET_LINE_CODE_INT_CLR + description: Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SET_LINE_CODE_INT_CLR + description: Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - register: + name: CONF0 + description: PHY hardware configuration. + addressOffset: 24 + size: 32 + resetValue: 16896 + fields: + - name: PHY_SEL + description: Select internal/external PHY + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EXCHG_PINS_OVERRIDE + description: Enable software control USB D+ D- exchange + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EXCHG_PINS + description: USB D+ D- exchange + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: VREFH + description: "Control single-end input high threshold,1.76V to 2V, step 80mV" + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: VREFL + description: "Control single-end input low threshold,0.8V to 1.04V, step 80mV" + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: VREF_OVERRIDE + description: Enable software control input threshold + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: PAD_PULL_OVERRIDE + description: Enable software control USB D+ D- pullup pulldown + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DP_PULLUP + description: Control USB D+ pull up. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DP_PULLDOWN + description: Control USB D+ pull down. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DM_PULLUP + description: Control USB D- pull up. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DM_PULLDOWN + description: Control USB D- pull down. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PULLUP_VALUE + description: Control pull up value. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: USB_PAD_ENABLE + description: Enable USB pad function. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: USB_JTAG_BRIDGE_EN + description: "Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: TEST + description: Registers used for debugging the PHY. + addressOffset: 28 + size: 32 + resetValue: 48 + fields: + - name: TEST_ENABLE + description: Enable test of the USB pad + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TEST_USB_OE + description: USB pad oen in test + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TEST_TX_DP + description: USB D+ tx value in test + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TEST_TX_DM + description: USB D- tx value in test + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TEST_RX_RCV + description: USB RCV value in test + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TEST_RX_DP + description: USB D+ rx value in test + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: TEST_RX_DM + description: USB D- rx value in test + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: JFIFO_ST + description: JTAG FIFO status and control registers. + addressOffset: 32 + size: 32 + resetValue: 68 + fields: + - name: IN_FIFO_CNT + description: JTAT in fifo counter. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_FIFO_EMPTY + description: "1: JTAG in fifo is empty." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: IN_FIFO_FULL + description: "1: JTAG in fifo is full." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: OUT_FIFO_CNT + description: JTAT out fifo counter. + bitOffset: 4 + bitWidth: 2 + access: read-only + - name: OUT_FIFO_EMPTY + description: "1: JTAG out fifo is empty." + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUT_FIFO_FULL + description: "1: JTAG out fifo is full." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IN_FIFO_RESET + description: Write 1 to reset JTAG in fifo. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: OUT_FIFO_RESET + description: Write 1 to reset JTAG out fifo. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: FRAM_NUM + description: Last received SOF frame index register. + addressOffset: 36 + size: 32 + fields: + - name: SOF_FRAME_INDEX + description: Frame index of received SOF frame. + bitOffset: 0 + bitWidth: 11 + access: read-only + - register: + name: IN_EP0_ST + description: Control IN endpoint status information. + addressOffset: 40 + size: 32 + resetValue: 1 + fields: + - name: IN_EP0_STATE + description: State of IN Endpoint 0. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_EP0_WR_ADDR + description: Write data address of IN endpoint 0. + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: IN_EP0_RD_ADDR + description: Read data address of IN endpoint 0. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: IN_EP1_ST + description: CDC-ACM IN endpoint status information. + addressOffset: 44 + size: 32 + resetValue: 1 + fields: + - name: IN_EP1_STATE + description: State of IN Endpoint 1. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_EP1_WR_ADDR + description: Write data address of IN endpoint 1. + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: IN_EP1_RD_ADDR + description: Read data address of IN endpoint 1. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: IN_EP2_ST + description: CDC-ACM interrupt IN endpoint status information. + addressOffset: 48 + size: 32 + resetValue: 1 + fields: + - name: IN_EP2_STATE + description: State of IN Endpoint 2. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_EP2_WR_ADDR + description: Write data address of IN endpoint 2. + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: IN_EP2_RD_ADDR + description: Read data address of IN endpoint 2. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: IN_EP3_ST + description: JTAG IN endpoint status information. + addressOffset: 52 + size: 32 + resetValue: 1 + fields: + - name: IN_EP3_STATE + description: State of IN Endpoint 3. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_EP3_WR_ADDR + description: Write data address of IN endpoint 3. + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: IN_EP3_RD_ADDR + description: Read data address of IN endpoint 3. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: OUT_EP0_ST + description: Control OUT endpoint status information. + addressOffset: 56 + size: 32 + fields: + - name: OUT_EP0_STATE + description: State of OUT Endpoint 0. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: OUT_EP0_WR_ADDR + description: "Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0." + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: OUT_EP0_RD_ADDR + description: Read data address of OUT endpoint 0. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: OUT_EP1_ST + description: CDC-ACM OUT endpoint status information. + addressOffset: 60 + size: 32 + fields: + - name: OUT_EP1_STATE + description: State of OUT Endpoint 1. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: OUT_EP1_WR_ADDR + description: "Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1." + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: OUT_EP1_RD_ADDR + description: Read data address of OUT endpoint 1. + bitOffset: 9 + bitWidth: 7 + access: read-only + - name: OUT_EP1_REC_DATA_CNT + description: Data count in OUT endpoint 1 when one packet is received. + bitOffset: 16 + bitWidth: 7 + access: read-only + - register: + name: OUT_EP2_ST + description: JTAG OUT endpoint status information. + addressOffset: 64 + size: 32 + fields: + - name: OUT_EP2_STATE + description: State of OUT Endpoint 2. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: OUT_EP2_WR_ADDR + description: "Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2." + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: OUT_EP2_RD_ADDR + description: Read data address of OUT endpoint 2. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: MISC_CONF + description: Clock enable control + addressOffset: 68 + size: 32 + fields: + - name: CLK_EN + description: "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: MEM_CONF + description: Memory power control + addressOffset: 72 + size: 32 + resetValue: 2 + fields: + - name: USB_MEM_PD + description: "1: power down usb memory." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: USB_MEM_CLK_EN + description: "1: Force clock on for usb memory." + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CHIP_RST + description: CDC-ACM chip reset control. + addressOffset: 76 + size: 32 + fields: + - name: RTS + description: "1: Chip reset is detected from usb serial channel. Software write 1 to clear it." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DTR + description: "1: Chip reset is detected from usb jtag channel. Software write 1 to clear it." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: USB_UART_CHIP_RST_DIS + description: Set this bit to disable chip reset from usb serial channel to reset chip. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: SET_LINE_CODE_W0 + description: W0 of SET_LINE_CODING command. + addressOffset: 80 + size: 32 + fields: + - name: DW_DTE_RATE + description: The value of dwDTERate set by host through SET_LINE_CODING command. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SET_LINE_CODE_W1 + description: W1 of SET_LINE_CODING command. + addressOffset: 84 + size: 32 + fields: + - name: BCHAR_FORMAT + description: The value of bCharFormat set by host through SET_LINE_CODING command. + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: BPARITY_TYPE + description: The value of bParityTpye set by host through SET_LINE_CODING command. + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: BDATA_BITS + description: The value of bDataBits set by host through SET_LINE_CODING command. + bitOffset: 16 + bitWidth: 8 + access: read-only + - register: + name: GET_LINE_CODE_W0 + description: W0 of GET_LINE_CODING command. + addressOffset: 88 + size: 32 + fields: + - name: GET_DW_DTE_RATE + description: The value of dwDTERate set by software which is requested by GET_LINE_CODING command. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: GET_LINE_CODE_W1 + description: W1 of GET_LINE_CODING command. + addressOffset: 92 + size: 32 + fields: + - name: GET_BDATA_BITS + description: The value of bCharFormat set by software which is requested by GET_LINE_CODING command. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GET_BPARITY_TYPE + description: The value of bParityTpye set by software which is requested by GET_LINE_CODING command. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: GET_BCHAR_FORMAT + description: The value of bDataBits set by software which is requested by GET_LINE_CODING command. + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: CONFIG_UPDATE + description: "Configuration registers' value update" + addressOffset: 96 + size: 32 + fields: + - name: CONFIG_UPDATE + description: Write 1 to this register would update the value of configure registers from APB clock domain to 48MHz clock domain. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SER_AFIFO_CONFIG + description: Serial AFIFO configure register + addressOffset: 100 + size: 32 + resetValue: 16 + fields: + - name: SERIAL_IN_AFIFO_RESET_WR + description: Write 1 to reset CDC_ACM IN async FIFO write clock domain. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SERIAL_IN_AFIFO_RESET_RD + description: Write 1 to reset CDC_ACM IN async FIFO read clock domain. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SERIAL_OUT_AFIFO_RESET_WR + description: Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SERIAL_OUT_AFIFO_RESET_RD + description: Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SERIAL_OUT_AFIFO_REMPTY + description: CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SERIAL_IN_AFIFO_WFULL + description: CDC_ACM OUT IN async FIFO empty signal in write clock domain. + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: BUS_RESET_ST + description: USB Bus reset status register + addressOffset: 104 + size: 32 + resetValue: 1 + fields: + - name: USB_BUS_RESET_ST + description: "USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus reset is released." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: Date register + addressOffset: 128 + size: 32 + resetValue: 34640416 + fields: + - name: DATE + description: register version. + bitOffset: 0 + bitWidth: 32 + access: read-write diff --git a/esp32p4/svd/esp32p4.svd.yaml b/esp32p4/svd/esp32p4.svd.yaml new file mode 100644 index 0000000000..27f2327b2a --- /dev/null +++ b/esp32p4/svd/esp32p4.svd.yaml @@ -0,0 +1,92833 @@ +--- +vendor: "ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD." +vendorID: ESPRESSIF +name: ESP32-P4 +series: ESP32 P-Series +version: "3" +description: 32-bit RISC-V MCU +licenseText: "Copyright 2024 Espressif Systems (Shanghai) PTE LTD\n\n Licensed under the Apache License, Version 2.0 (the \"License\");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an \"AS IS\" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License." +cpu: + name: RV32IMAFC + revision: r0p0 + endian: little + mpuPresent: false + fpuPresent: true + nvicPrioBits: 0 + vendorSystickConfig: false +addressUnitBits: 32 +width: 32 +resetValue: 0 +resetMask: 4294967295 +peripherals: + - name: ADC + description: ADC (Analog to Digital Converter) + groupName: ADC + baseAddress: 1343086592 + addressBlock: + - offset: 0 + size: 124 + usage: registers + registers: + - register: + name: CTRL + description: Register + addressOffset: 0 + size: 32 + resetValue: 1077920032 + fields: + - name: START_FORCE + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: START + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: WORK_MODE + description: "0: single mode, 1: double mode, 2: alternate mode" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: SAR_SEL + description: "0: SAR1, 1: SAR2, only work for single SAR mode" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SAR_CLK_GATED + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SAR_CLK_DIV + description: SAR clock divider + bitOffset: 6 + bitWidth: 8 + access: read-write + - name: SAR1_PATT_LEN + description: 0 ~ 15 means length 1 ~ 16 + bitOffset: 14 + bitWidth: 4 + access: read-write + - name: SAR2_PATT_LEN + description: 0 ~ 15 means length 1 ~ 16 + bitOffset: 18 + bitWidth: 4 + access: read-write + - name: SAR1_PATT_P_CLEAR + description: clear the pointer of pattern table for DIG ADC1 CTRL + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SAR2_PATT_P_CLEAR + description: clear the pointer of pattern table for DIG ADC2 CTRL + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: DATA_SAR_SEL + description: "1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: DATA_TO_I2S + description: "1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: XPD_SAR1_FORCE + description: force option to xpd sar1 blocks + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: XPD_SAR2_FORCE + description: force option to xpd sar2 blocks + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: WAIT_ARB_CYCLE + description: wait arbit signal stable after sar_done + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CTRL2 + description: Register + addressOffset: 4 + size: 32 + resetValue: 41470 + fields: + - name: MEAS_NUM_LIMIT + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MAX_MEAS_NUM + description: max conversion number + bitOffset: 1 + bitWidth: 8 + access: read-write + - name: SAR1_INV + description: "1: data to DIG ADC1 CTRL is inverted, otherwise not" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SAR2_INV + description: "1: data to DIG ADC2 CTRL is inverted, otherwise not" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TIMER_SEL + description: "1: select saradc timer 0: i2s_ws trigger" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TIMER_TARGET + description: to set saradc timer target + bitOffset: 12 + bitWidth: 12 + access: read-write + - name: TIMER_EN + description: to enable saradc timer trigger + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: FILTER_CTRL1 + description: Register + addressOffset: 8 + size: 32 + fields: + - name: FILTER_FACTOR1 + description: need_des + bitOffset: 26 + bitWidth: 3 + access: read-write + - name: FILTER_FACTOR0 + description: need_des + bitOffset: 29 + bitWidth: 3 + access: read-write + - register: + name: FSM_WAIT + description: Register + addressOffset: 12 + size: 32 + resetValue: 16713736 + fields: + - name: XPD_WAIT + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: RSTB_WAIT + description: need_des + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: STANDBY_WAIT + description: need_des + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: SAR1_STATUS + description: Register + addressOffset: 16 + size: 32 + fields: + - name: SAR1_STATUS + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SAR2_STATUS + description: Register + addressOffset: 20 + size: 32 + fields: + - name: SAR2_STATUS + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SAR1_PATT_TAB1 + description: Register + addressOffset: 24 + size: 32 + fields: + - name: SAR1_PATT_TAB1 + description: item 0 ~ 3 for pattern table 1 (each item one byte) + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: SAR1_PATT_TAB2 + description: Register + addressOffset: 28 + size: 32 + fields: + - name: SAR1_PATT_TAB2 + description: Item 4 ~ 7 for pattern table 1 (each item one byte) + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: SAR1_PATT_TAB3 + description: Register + addressOffset: 32 + size: 32 + fields: + - name: SAR1_PATT_TAB3 + description: Item 8 ~ 11 for pattern table 1 (each item one byte) + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: SAR1_PATT_TAB4 + description: Register + addressOffset: 36 + size: 32 + fields: + - name: SAR1_PATT_TAB4 + description: Item 12 ~ 15 for pattern table 1 (each item one byte) + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: SAR2_PATT_TAB1 + description: Register + addressOffset: 40 + size: 32 + fields: + - name: SAR2_PATT_TAB1 + description: item 0 ~ 3 for pattern table 2 (each item one byte) + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: SAR2_PATT_TAB2 + description: Register + addressOffset: 44 + size: 32 + fields: + - name: SAR2_PATT_TAB2 + description: Item 4 ~ 7 for pattern table 2 (each item one byte) + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: SAR2_PATT_TAB3 + description: Register + addressOffset: 48 + size: 32 + fields: + - name: SAR2_PATT_TAB3 + description: Item 8 ~ 11 for pattern table 2 (each item one byte) + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: SAR2_PATT_TAB4 + description: Register + addressOffset: 52 + size: 32 + fields: + - name: SAR2_PATT_TAB4 + description: Item 12 ~ 15 for pattern table 2 (each item one byte) + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: ARB_CTRL + description: Register + addressOffset: 56 + size: 32 + resetValue: 2304 + fields: + - name: ARB_APB_FORCE + description: adc2 arbiter force to enableapb controller + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ARB_RTC_FORCE + description: adc2 arbiter force to enable rtc controller + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ARB_WIFI_FORCE + description: adc2 arbiter force to enable wifi controller + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ARB_GRANT_FORCE + description: adc2 arbiter force grant + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: ARB_APB_PRIORITY + description: Set adc2 arbiterapb priority + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: ARB_RTC_PRIORITY + description: Set adc2 arbiter rtc priority + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: ARB_WIFI_PRIORITY + description: Set adc2 arbiter wifi priority + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: ARB_FIX_PRIORITY + description: adc2 arbiter uses fixed priority + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: FILTER_CTRL0 + description: Register + addressOffset: 60 + size: 32 + resetValue: 7028736 + fields: + - name: FILTER_CHANNEL1 + description: need_des + bitOffset: 14 + bitWidth: 5 + access: read-write + - name: FILTER_CHANNEL0 + description: apb_adc1_filter_factor + bitOffset: 19 + bitWidth: 5 + access: read-write + - name: FILTER_RESET + description: enable apb_adc1_filter + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAR1_DATA_STATUS + description: Register + addressOffset: 64 + size: 32 + fields: + - name: APB_SARADC1_DATA + description: need_des + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: THRES0_CTRL + description: Register + addressOffset: 68 + size: 32 + resetValue: 262125 + fields: + - name: THRES0_CHANNEL + description: need_des + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: THRES0_HIGH + description: "saradc1's thres0 monitor thres" + bitOffset: 5 + bitWidth: 13 + access: read-write + - name: THRES0_LOW + description: "saradc1's thres0 monitor thres" + bitOffset: 18 + bitWidth: 13 + access: read-write + - register: + name: THRES1_CTRL + description: Register + addressOffset: 72 + size: 32 + resetValue: 262125 + fields: + - name: THRES1_CHANNEL + description: need_des + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: THRES1_HIGH + description: "saradc1's thres0 monitor thres" + bitOffset: 5 + bitWidth: 13 + access: read-write + - name: THRES1_LOW + description: "saradc1's thres0 monitor thres" + bitOffset: 18 + bitWidth: 13 + access: read-write + - register: + name: THRES_CTRL + description: Register + addressOffset: 76 + size: 32 + fields: + - name: THRES_ALL_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: THRES3_EN + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: THRES2_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: THRES1_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: THRES0_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_ENA + description: Register + addressOffset: 80 + size: 32 + fields: + - name: THRES1_LOW_INT_ENA + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: THRES0_LOW_INT_ENA + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: THRES1_HIGH_INT_ENA + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: THRES0_HIGH_INT_ENA + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SAR2_DONE_INT_ENA + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SAR1_DONE_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: Register + addressOffset: 84 + size: 32 + fields: + - name: THRES1_LOW_INT_RAW + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: THRES0_LOW_INT_RAW + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: THRES1_HIGH_INT_RAW + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: THRES0_HIGH_INT_RAW + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SAR2_DONE_INT_RAW + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SAR1_DONE_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Register + addressOffset: 88 + size: 32 + fields: + - name: THRES1_LOW_INT_ST + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: THRES0_LOW_INT_ST + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: THRES1_HIGH_INT_ST + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: THRES0_HIGH_INT_ST + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: APB_SARADC2_DONE_INT_ST + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: APB_SARADC1_DONE_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: Register + addressOffset: 92 + size: 32 + fields: + - name: THRES1_LOW_INT_CLR + description: need_des + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: THRES0_LOW_INT_CLR + description: need_des + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: THRES1_HIGH_INT_CLR + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: THRES0_HIGH_INT_CLR + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: APB_SARADC2_DONE_INT_CLR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: APB_SARADC1_DONE_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: DMA_CONF + description: Register + addressOffset: 96 + size: 32 + resetValue: 255 + fields: + - name: APB_ADC_EOF_NUM + description: the dma_in_suc_eof gen when sample cnt = spi_eof_num + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: APB_ADC_RESET_FSM + description: reset_apb_adc_state + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: APB_ADC_TRANS + description: enable apb_adc use spi_dma + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAR2_DATA_STATUS + description: Register + addressOffset: 100 + size: 32 + fields: + - name: APB_SARADC2_DATA + description: need_des + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: CALI + description: Register + addressOffset: 104 + size: 32 + resetValue: 32768 + fields: + - name: CFG + description: need_des + bitOffset: 0 + bitWidth: 17 + access: read-write + - register: + name: RND_ECO_LOW + description: Register + addressOffset: 108 + size: 32 + fields: + - name: RND_ECO_LOW + description: rnd eco low + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RND_ECO_HIGH + description: Register + addressOffset: 112 + size: 32 + resetValue: 4294967295 + fields: + - name: RND_ECO_HIGH + description: rnd eco high + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RND_ECO_CS + description: Register + addressOffset: 116 + size: 32 + fields: + - name: RND_ECO_EN + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RND_ECO_RESULT + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: CTRL_DATE + description: Register + addressOffset: 1020 + size: 32 + resetValue: 35725920 + fields: + - name: CTRL_DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: AES + description: AES (Advanced Encryption Standard) Accelerator + groupName: AES + baseAddress: 1342767104 + addressBlock: + - offset: 0 + size: 188 + usage: registers + interrupt: + - name: AES + value: 69 + registers: + - register: + name: KEY_0 + description: Key material key_0 configure register + addressOffset: 0 + size: 32 + fields: + - name: KEY_0 + description: This bits stores key_0 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_1 + description: Key material key_1 configure register + addressOffset: 4 + size: 32 + fields: + - name: KEY_1 + description: This bits stores key_1 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_2 + description: Key material key_2 configure register + addressOffset: 8 + size: 32 + fields: + - name: KEY_2 + description: This bits stores key_2 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_3 + description: Key material key_3 configure register + addressOffset: 12 + size: 32 + fields: + - name: KEY_3 + description: This bits stores key_3 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_4 + description: Key material key_4 configure register + addressOffset: 16 + size: 32 + fields: + - name: KEY_4 + description: This bits stores key_4 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_5 + description: Key material key_5 configure register + addressOffset: 20 + size: 32 + fields: + - name: KEY_5 + description: This bits stores key_5 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_6 + description: Key material key_6 configure register + addressOffset: 24 + size: 32 + fields: + - name: KEY_6 + description: This bits stores key_6 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: KEY_7 + description: Key material key_7 configure register + addressOffset: 28 + size: 32 + fields: + - name: KEY_7 + description: This bits stores key_7 that is a part of key material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_IN_0 + description: source text material text_in_0 configure register + addressOffset: 32 + size: 32 + fields: + - name: TEXT_IN_0 + description: This bits stores text_in_0 that is a part of source text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_IN_1 + description: source text material text_in_1 configure register + addressOffset: 36 + size: 32 + fields: + - name: TEXT_IN_1 + description: This bits stores text_in_1 that is a part of source text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_IN_2 + description: source text material text_in_2 configure register + addressOffset: 40 + size: 32 + fields: + - name: TEXT_IN_2 + description: This bits stores text_in_2 that is a part of source text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_IN_3 + description: source text material text_in_3 configure register + addressOffset: 44 + size: 32 + fields: + - name: TEXT_IN_3 + description: This bits stores text_in_3 that is a part of source text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_OUT_0 + description: result text material text_out_0 configure register + addressOffset: 48 + size: 32 + fields: + - name: TEXT_OUT_0 + description: This bits stores text_out_0 that is a part of result text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_OUT_1 + description: result text material text_out_1 configure register + addressOffset: 52 + size: 32 + fields: + - name: TEXT_OUT_1 + description: This bits stores text_out_1 that is a part of result text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_OUT_2 + description: result text material text_out_2 configure register + addressOffset: 56 + size: 32 + fields: + - name: TEXT_OUT_2 + description: This bits stores text_out_2 that is a part of result text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TEXT_OUT_3 + description: result text material text_out_3 configure register + addressOffset: 60 + size: 32 + fields: + - name: TEXT_OUT_3 + description: This bits stores text_out_3 that is a part of result text material. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: MODE + description: AES Mode register + addressOffset: 64 + size: 32 + fields: + - name: MODE + description: "This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256." + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: ENDIAN + description: AES Endian configure register + addressOffset: 68 + size: 32 + fields: + - name: ENDIAN + description: "endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out endian or out_stream endian" + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: TRIGGER + description: AES trigger register + addressOffset: 72 + size: 32 + fields: + - name: TRIGGER + description: Set this bit to start AES calculation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: STATE + description: AES state register + addressOffset: 76 + size: 32 + fields: + - name: STATE + description: "Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done." + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + dim: 4 + dimIncrement: 4 + name: "IV_MEM[%s]" + description: The memory that stores initialization vector + addressOffset: 80 + size: 32 + - register: + dim: 4 + dimIncrement: 4 + name: "H_MEM[%s]" + description: The memory that stores GCM hash subkey + addressOffset: 96 + size: 32 + - register: + dim: 4 + dimIncrement: 4 + name: "J0_MEM[%s]" + description: The memory that stores J0 + addressOffset: 112 + size: 32 + - register: + dim: 4 + dimIncrement: 4 + name: "T0_MEM[%s]" + description: The memory that stores T0 + addressOffset: 128 + size: 32 + - register: + name: DMA_ENABLE + description: DMA-AES working mode register + addressOffset: 144 + size: 32 + fields: + - name: DMA_ENABLE + description: "1'b0: typical AES working mode, 1'b1: DMA-AES working mode." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: BLOCK_MODE + description: AES cipher block mode register + addressOffset: 148 + size: 32 + fields: + - name: BLOCK_MODE + description: "Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved." + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: BLOCK_NUM + description: AES block number register + addressOffset: 152 + size: 32 + fields: + - name: BLOCK_NUM + description: Those bits stores the number of Plaintext/ciphertext block. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: INC_SEL + description: Standard incrementing function configure register + addressOffset: 156 + size: 32 + fields: + - name: INC_SEL + description: "This bit decides the standard incrementing function. 0: INC32. 1: INC128." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: AAD_BLOCK_NUM + description: Additional Authential Data block number register + addressOffset: 160 + size: 32 + fields: + - name: AAD_BLOCK_NUM + description: Those bits stores the number of AAD block. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REMAINDER_BIT_NUM + description: AES remainder bit number register + addressOffset: 164 + size: 32 + fields: + - name: REMAINDER_BIT_NUM + description: Those bits stores the number of remainder bit. + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: CONTINUE + description: AES continue register + addressOffset: 168 + size: 32 + fields: + - name: CONTINUE + description: Set this bit to continue GCM operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: INT_CLEAR + description: AES Interrupt clear register + addressOffset: 172 + size: 32 + fields: + - name: INT_CLEAR + description: Set this bit to clear the AES interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + description: AES Interrupt enable register + addressOffset: 176 + size: 32 + fields: + - name: INT_ENA + description: Set this bit to enable interrupt that occurs when DMA-AES calculation is done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: AES version control register + addressOffset: 180 + size: 32 + resetValue: 538513936 + fields: + - name: DATE + description: This bits stores the version information of AES. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: DMA_EXIT + description: AES-DMA exit config + addressOffset: 184 + size: 32 + fields: + - name: DMA_EXIT + description: "Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer." + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: AHB_DMA + description: AHB_DMA Peripheral + groupName: AHB_DMA + baseAddress: 1342722048 + addressBlock: + - offset: 0 + size: 708 + usage: registers + interrupt: + - name: AHB_PDMA_IN_CH0 + value: 56 + - name: AHB_PDMA_IN_CH1 + value: 57 + - name: AHB_PDMA_IN_CH2 + value: 58 + - name: AHB_PDMA_OUT_CH0 + value: 59 + - name: AHB_PDMA_OUT_CH1 + value: 60 + - name: AHB_PDMA_OUT_CH2 + value: 61 + - name: AXI_PDMA_IN_CH0 + value: 62 + - name: AXI_PDMA_IN_CH1 + value: 63 + - name: AXI_PDMA_IN_CH2 + value: 64 + - name: AXI_PDMA_OUT_CH0 + value: 65 + - name: AXI_PDMA_OUT_CH1 + value: 66 + - name: AXI_PDMA_OUT_CH2 + value: 67 + registers: + - cluster: + dim: 3 + dimIncrement: 16 + dimIndex: "0,1,2" + name: IN_INT_CH%s + description: "Cluster IN_INT_CH%s, containing IN_INT_RAW_CH?, IN_INT_ST_CH?, IN_INT_ENA_CH?, IN_INT_CLR_CH?" + addressOffset: 0 + children: + - register: + name: RAW + description: Raw status interrupt of channel 0 + addressOffset: 0 + size: 32 + fields: + - name: IN_DONE + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF + description: The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR + description: The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY + description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF + description: This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF + description: This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: ST + description: Masked interrupt of channel 0 + addressOffset: 4 + size: 32 + fields: + - name: IN_DONE + description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: IN_SUC_EOF + description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: IN_ERR_EOF + description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: IN_DSCR_ERR + description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: IN_DSCR_EMPTY + description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: INFIFO_OVF + description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: INFIFO_UDF + description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: ENA + description: Interrupt enable bits of channel 0 + addressOffset: 8 + size: 32 + fields: + - name: IN_DONE + description: The interrupt enable bit for the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF + description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF + description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR + description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY + description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF + description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF + description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: CLR + description: Interrupt clear bits of channel 0 + addressOffset: 12 + size: 32 + fields: + - name: IN_DONE + description: Set this bit to clear the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: IN_SUC_EOF + description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: IN_ERR_EOF + description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: IN_DSCR_ERR + description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: IN_DSCR_EMPTY + description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: INFIFO_OVF + description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: INFIFO_UDF + description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - cluster: + dim: 3 + dimIncrement: 16 + dimIndex: "0,1,2" + name: OUT_INT_CH%s + description: "Cluster OUT_INT_CH%s, containing OUT_INT_RAW_CH?, OUT_INT_ST_CH?, OUT_INT_ENA_CH?, OUT_INT_CLR_CH?" + addressOffset: 48 + children: + - register: + name: RAW + description: Raw status interrupt of channel 0 + addressOffset: 0 + size: 32 + fields: + - name: OUT_DONE + description: The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_EOF + description: The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR + description: The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error and the second and third word error of outlink descriptor for Tx channel 0. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF + description: The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF + description: This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF + description: This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: ST + description: Masked interrupt of channel 0 + addressOffset: 4 + size: 32 + fields: + - name: OUT_DONE + description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUT_EOF + description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: OUT_DSCR_ERR + description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: OUT_TOTAL_EOF + description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: OUTFIFO_OVF + description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: OUTFIFO_UDF + description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: ENA + description: Interrupt enable bits of channel 0 + addressOffset: 8 + size: 32 + fields: + - name: OUT_DONE + description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_EOF + description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR + description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF + description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF + description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF + description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: CLR + description: Interrupt clear bits of channel 0 + addressOffset: 12 + size: 32 + fields: + - name: OUT_DONE + description: Set this bit to clear the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: OUT_EOF + description: Set this bit to clear the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: OUT_DSCR_ERR + description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: OUT_TOTAL_EOF + description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: OUTFIFO_OVF + description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: OUTFIFO_UDF + description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: AHB_TEST + description: reserved + addressOffset: 96 + size: 32 + fields: + - name: AHB_TESTMODE + description: reserved + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: AHB_TESTADDR + description: reserved + bitOffset: 4 + bitWidth: 2 + access: read-write + - register: + name: MISC_CONF + description: MISC register + addressOffset: 100 + size: 32 + fields: + - name: AHBM_RST_INTER + description: Set this bit then clear this bit to reset the internal ahb FSM. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ARB_PRI_DIS + description: Set this bit to disable priority arbitration function. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers." + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 104 + size: 32 + resetValue: 36712768 + fields: + - name: DATE + description: register version. + bitOffset: 0 + bitWidth: 32 + access: read-write + - cluster: + dim: 3 + dimIncrement: 192 + dimIndex: "0,1,2" + name: CH%s + description: "Cluster CH%s, containing IN_CONF0_CH?, IN_CONF1_CH?, INFIFO_STATUS_CH?, IN_POP_CH?, IN_LINK_CH?, IN_STATE_CH?, IN_SUC_EOF_DES_ADDR_CH?, IN_ERR_EOF_DES_ADDR_CH?, IN_DSCR_CH?, IN_DSCR_BF0_CH?, IN_DSCR_BF1_CH?, IN_PRI_CH?, IN_PERI_SEL_CH?, OUT_CONF0_CH?, OUT_CONF1_CH?, OUTFIFO_STATUS_CH?, OUT_PUSH_CH?, OUT_LINK_CH?, OUT_STATE_CH?, OUT_EOF_DES_ADDR_CH?, OUT_EOF_BFR_DES_ADDR_CH?, OUT_DSCR_CH?, OUT_DSCR_BF0_CH?, OUT_DSCR_BF1_CH?, OUT_PRI_CH?, OUT_PERI_SEL_CH?" + addressOffset: 112 + children: + - register: + name: IN_CONF0 + description: Configure 0 register of Rx channel 0 + addressOffset: 0 + size: 32 + fields: + - name: IN_RST + description: This bit is used to reset AHB_DMA channel 0 Rx FSM and Rx FIFO pointer. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_LOOP_TEST + description: reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: INDSCR_BURST_EN + description: Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DATA_BURST_EN + description: Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MEM_TRANS_EN + description: Set this bit 1 to enable automatic transmitting data from memory to memory via AHB_DMA. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IN_ETM_EN + description: "Set this bit to 1 to enable etm control mode, dma Rx channel 0 is triggered by etm task." + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: IN_CONF1 + description: Configure 1 register of Rx channel 0 + addressOffset: 4 + size: 32 + fields: + - name: IN_CHECK_OWNER + description: Set this bit to enable checking the owner attribute of the link descriptor. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: INFIFO_STATUS + description: Receive FIFO status of Rx channel 0 + addressOffset: 8 + size: 32 + resetValue: 125829123 + fields: + - name: INFIFO_FULL + description: L1 Rx FIFO full signal for Rx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: INFIFO_EMPTY + description: L1 Rx FIFO empty signal for Rx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: INFIFO_CNT + description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + bitOffset: 2 + bitWidth: 6 + access: read-only + - name: IN_REMAIN_UNDER_1B + description: reserved + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: IN_REMAIN_UNDER_2B + description: reserved + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: IN_REMAIN_UNDER_3B + description: reserved + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: IN_REMAIN_UNDER_4B + description: reserved + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: IN_BUF_HUNGRY + description: reserved + bitOffset: 27 + bitWidth: 1 + access: read-only + - register: + name: IN_POP + description: Pop control register of Rx channel 0 + addressOffset: 12 + size: 32 + resetValue: 2048 + fields: + - name: INFIFO_RDATA + description: This register stores the data popping from AHB_DMA FIFO. + bitOffset: 0 + bitWidth: 12 + access: read-only + - name: INFIFO_POP + description: Set this bit to pop data from AHB_DMA FIFO. + bitOffset: 12 + bitWidth: 1 + access: write-only + - register: + name: IN_LINK + description: Link descriptor configure and control register of Rx channel 0 + addressOffset: 16 + size: 32 + resetValue: 17 + fields: + - name: INLINK_AUTO_RET + description: "Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: INLINK_STOP + description: Set this bit to stop dealing with the inlink descriptors. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: INLINK_START + description: Set this bit to start dealing with the inlink descriptors. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: INLINK_RESTART + description: Set this bit to mount a new inlink descriptor. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: INLINK_PARK + description: "1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working." + bitOffset: 4 + bitWidth: 1 + access: read-only + - register: + name: IN_STATE + description: Receive status of Rx channel 0 + addressOffset: 20 + size: 32 + fields: + - name: INLINK_DSCR_ADDR + description: "This register stores the current inlink descriptor's address." + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: IN_DSCR_STATE + description: reserved + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: IN_STATE + description: reserved + bitOffset: 20 + bitWidth: 3 + access: read-only + - register: + name: IN_SUC_EOF_DES_ADDR + description: Inlink descriptor address when EOF occurs of Rx channel 0 + addressOffset: 24 + size: 32 + fields: + - name: IN_SUC_EOF_DES_ADDR + description: This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_ERR_EOF_DES_ADDR + description: Inlink descriptor address when errors occur of Rx channel 0 + addressOffset: 28 + size: 32 + fields: + - name: IN_ERR_EOF_DES_ADDR + description: This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR + description: Current inlink descriptor address of Rx channel 0 + addressOffset: 32 + size: 32 + fields: + - name: INLINK_DSCR + description: The address of the current inlink descriptor x. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_BF0 + description: The last inlink descriptor address of Rx channel 0 + addressOffset: 36 + size: 32 + fields: + - name: INLINK_DSCR_BF0 + description: The address of the last inlink descriptor x-1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_BF1 + description: The second-to-last inlink descriptor address of Rx channel 0 + addressOffset: 40 + size: 32 + fields: + - name: INLINK_DSCR_BF1 + description: The address of the second-to-last inlink descriptor x-2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_PRI + description: Priority register of Rx channel 0 + addressOffset: 44 + size: 32 + fields: + - name: RX_PRI + description: The priority of Rx channel 0. The larger of the value the higher of the priority. + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: IN_PERI_SEL + description: Peripheral selection of Rx channel 0 + addressOffset: 48 + size: 32 + resetValue: 63 + fields: + - name: PERI_IN_SEL + description: "This register is used to select peripheral for Rx channel 0. I3C. 1: Dummy. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10: RMT,11~15: Dummy" + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: OUT_CONF0 + description: Configure 0 register of Tx channel 0 + addressOffset: 96 + size: 32 + resetValue: 8 + fields: + - name: OUT_RST + description: This bit is used to reset AHB_DMA channel 1 Tx FSM and Tx FIFO pointer. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_LOOP_TEST + description: reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_AUTO_WRBACK + description: Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_EOF_MODE + description: "EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in AHB_DMA" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTDSCR_BURST_EN + description: Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUT_DATA_BURST_EN + description: Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUT_ETM_EN + description: "Set this bit to 1 to enable etm control mode, dma Tx channel 1 is triggered by etm task." + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: OUT_CONF1 + description: Configure 1 register of Tx channel 0 + addressOffset: 100 + size: 32 + fields: + - name: OUT_CHECK_OWNER + description: Set this bit to enable checking the owner attribute of the link descriptor. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: OUTFIFO_STATUS + description: Transmit FIFO status of Tx channel 0 + addressOffset: 104 + size: 32 + resetValue: 125829122 + fields: + - name: OUTFIFO_FULL + description: L1 Tx FIFO full signal for Tx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY + description: L1 Tx FIFO empty signal for Tx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: OUTFIFO_CNT + description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + bitOffset: 2 + bitWidth: 6 + access: read-only + - name: OUT_REMAIN_UNDER_1B + description: reserved + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: OUT_REMAIN_UNDER_2B + description: reserved + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: OUT_REMAIN_UNDER_3B + description: reserved + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: OUT_REMAIN_UNDER_4B + description: reserved + bitOffset: 26 + bitWidth: 1 + access: read-only + - register: + name: OUT_PUSH + description: Push control register of Rx channel 0 + addressOffset: 108 + size: 32 + fields: + - name: OUTFIFO_WDATA + description: This register stores the data that need to be pushed into AHB_DMA FIFO. + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: OUTFIFO_PUSH + description: Set this bit to push data into AHB_DMA FIFO. + bitOffset: 9 + bitWidth: 1 + access: write-only + - register: + name: OUT_LINK + description: Link descriptor configure and control register of Tx channel 0 + addressOffset: 112 + size: 32 + resetValue: 8 + fields: + - name: OUTLINK_STOP + description: Set this bit to stop dealing with the outlink descriptors. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: OUTLINK_START + description: Set this bit to start dealing with the outlink descriptors. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: OUTLINK_RESTART + description: Set this bit to restart a new outlink from the last address. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: OUTLINK_PARK + description: "1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working." + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: OUT_STATE + description: Transmit status of Tx channel 0 + addressOffset: 116 + size: 32 + fields: + - name: OUTLINK_DSCR_ADDR + description: "This register stores the current outlink descriptor's address." + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: OUT_DSCR_STATE + description: reserved + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: OUT_STATE + description: reserved + bitOffset: 20 + bitWidth: 3 + access: read-only + - register: + name: OUT_EOF_DES_ADDR + description: Outlink descriptor address when EOF occurs of Tx channel 0 + addressOffset: 120 + size: 32 + fields: + - name: OUT_EOF_DES_ADDR + description: This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_EOF_BFR_DES_ADDR + description: The last outlink descriptor address when EOF occurs of Tx channel 0 + addressOffset: 124 + size: 32 + fields: + - name: OUT_EOF_BFR_DES_ADDR + description: This register stores the address of the outlink descriptor before the last outlink descriptor. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR + description: Current inlink descriptor address of Tx channel 0 + addressOffset: 128 + size: 32 + fields: + - name: OUTLINK_DSCR + description: The address of the current outlink descriptor y. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_BF0 + description: The last inlink descriptor address of Tx channel 0 + addressOffset: 132 + size: 32 + fields: + - name: OUTLINK_DSCR_BF0 + description: The address of the last outlink descriptor y-1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_BF1 + description: The second-to-last inlink descriptor address of Tx channel 0 + addressOffset: 136 + size: 32 + fields: + - name: OUTLINK_DSCR_BF1 + description: The address of the second-to-last inlink descriptor x-2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_PRI + description: Priority register of Tx channel 0. + addressOffset: 140 + size: 32 + fields: + - name: TX_PRI + description: The priority of Tx channel 0. The larger of the value the higher of the priority. + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: OUT_PERI_SEL + description: Peripheral selection of Tx channel 0 + addressOffset: 144 + size: 32 + resetValue: 63 + fields: + - name: PERI_OUT_SEL + description: "This register is used to select peripheral for Tx channel 0. I3C. 1: Dummy. 2: UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10: RMT,11~15: Dummy" + bitOffset: 0 + bitWidth: 6 + access: read-write + - cluster: + dim: 3 + dimIncrement: 40 + dimIndex: "0,1,2" + name: OUT_CRC_CH%s + description: "Cluster OUT_CRC_CH%s, containing OUT_CRC_INIT_DATA_CH?, TX_CRC_WIDTH_CH?, OUT_CRC_CLEAR_CH?, OUT_CRC_FINAL_RESULT_CH?, TX_CRC_EN_WR_DATA_CH?, TX_CRC_EN_ADDR_CH?, TX_CRC_DATA_EN_WR_DATA_CH?, TX_CRC_DATA_EN_ADDR_CH?, TX_CH_ARB_WEIGH_CH?, TX_ARB_WEIGH_OPT_DIR_CH?" + addressOffset: 700 + children: + - register: + name: OUT_CRC_INIT_DATA + description: This register is used to config ch0 crc initial data(max 32 bit) + addressOffset: 0 + size: 32 + resetValue: 4294967295 + fields: + - name: OUT_CRC_INIT_DATA + description: This register is used to config ch0 of tx crc initial value + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TX_CRC_WIDTH + description: "This register is used to confiig tx ch0 crc result width,2'b00 mean crc_width <=8bit,2'b01 8 reg_vdisp+reg_vsync+reg_vbank" + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: VDISP + description: this field configures the length of valid line (by line) for dpi output + bitOffset: 16 + bitWidth: 12 + access: read-write + - register: + name: DPI_V_CFG1 + description: dsi bridge dpi v config register 1 + addressOffset: 52 + size: 32 + resetValue: 131105 + fields: + - name: VBANK + description: this field configures the length between vsync and valid line (by line) for dpi output + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: VSYNC + description: this field configures the length of vsync (by line) for dpi output + bitOffset: 16 + bitWidth: 12 + access: read-write + - register: + name: DPI_H_CFG0 + description: dsi bridge dpi h config register 0 + addressOffset: 56 + size: 32 + resetValue: 41943840 + fields: + - name: HTOTAL + description: "this field configures the total length of one line (by pixel num) for dpi output, must meet: reg_htotal > reg_hdisp+reg_hsync+reg_hbank" + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: HDISP + description: this field configures the length of valid pixel data (by pixel num) for dpi output + bitOffset: 16 + bitWidth: 12 + access: read-write + - register: + name: DPI_H_CFG1 + description: dsi bridge dpi h config register 1 + addressOffset: 60 + size: 32 + resetValue: 6291504 + fields: + - name: HBANK + description: this field configures the length between hsync and pixel data valid (by pixel num) for dpi output + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: HSYNC + description: this field configures the length of hsync (by pixel num) for dpi output + bitOffset: 16 + bitWidth: 12 + access: read-write + - register: + name: DPI_MISC_CONFIG + description: dsi_bridge dpi misc config register + addressOffset: 64 + size: 32 + resetValue: 6608 + fields: + - name: DPI_EN + description: "this bit configures enable of dpi output, 0: disable, 1: enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FIFO_UNDERRUN_DISCARD_VCNT + description: "this field configures the underrun interrupt musk, when underrun occurs and line cnt is less then this field" + bitOffset: 4 + bitWidth: 12 + access: read-write + - register: + name: DPI_CONFIG_UPDATE + description: dsi_bridge dpi config update register + addressOffset: 68 + size: 32 + fields: + - name: DPI_CONFIG_UPDATE + description: write 1 to this bit to update dpi config register MIPI_DSI_BRG_DPI_* + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + description: dsi_bridge interrupt enable register + addressOffset: 80 + size: 32 + fields: + - name: UNDERRUN_INT_ENA + description: write 1 to enables dpi_underrun_int_st field of MIPI_DSI_BRG_INT_ST_REG controlled by dpi_underrun interrupt signal + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: dsi_bridge interrupt clear register + addressOffset: 84 + size: 32 + fields: + - name: UNDERRUN_INT_CLR + description: write 1 to this bit to clear dpi_underrun_int_raw field of MIPI_DSI_BRG_INT_RAW_REG + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: INT_RAW + description: dsi_bridge raw interrupt register + addressOffset: 88 + size: 32 + fields: + - name: UNDERRUN_INT_RAW + description: the raw interrupt status of dpi_underrun + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: dsi_bridge masked interrupt register + addressOffset: 92 + size: 32 + fields: + - name: UNDERRUN_INT_ST + description: the masked interrupt status of dpi_underrun + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: HOST_BIST_CTL + description: dsi_bridge host bist control register + addressOffset: 96 + size: 32 + fields: + - name: BISTOK + description: bistok + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: BISTON + description: biston + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: HOST_TRIGGER_REV + description: dsi_bridge host trigger reverse control register + addressOffset: 100 + size: 32 + fields: + - name: TX_TRIGGER_REV_EN + description: "tx_trigger reverse. 0: disable, 1: enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_TRIGGER_REV_EN + description: "rx_trigger reverse. 0: disable, 1: enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: BLK_RAW_NUM_CFG + description: dsi_bridge block raw number control register + addressOffset: 104 + size: 32 + resetValue: 230400 + fields: + - name: BLK_RAW_NUM_TOTAL + description: this field configures number of total block pix bits/64 + bitOffset: 0 + bitWidth: 22 + access: read-write + - name: BLK_RAW_NUM_TOTAL_SET + description: write 1 to reload reg_blk_raw_num_total to internal cnt + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: DMA_FRAME_INTERVAL + description: dsi_bridge dam frame interval control register + addressOffset: 108 + size: 32 + resetValue: 536880137 + fields: + - name: DMA_FRAME_SLOT + description: this field configures the max frame_slot_cnt + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: DMA_FRAME_INTERVAL + description: "this field configures the max frame_interval_cnt, frame_interval_cnt increased by 1 when frame_slot_cnt if full" + bitOffset: 10 + bitWidth: 18 + access: read-write + - name: DMA_MULTIBLK_EN + description: "this bit configures enable multi-blk transfer, 0: disable, 1: enable" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: EN + description: "this bit configures enable interval between frame transfer, 0: disable, 1: enable" + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: MEM_AUX_CTRL + description: dsi_bridge mem aux control register + addressOffset: 112 + size: 32 + resetValue: 4896 + fields: + - name: DSI_MEM_AUX_CTRL + description: this field configures dsi_bridge fifo memory aux ctrl + bitOffset: 0 + bitWidth: 14 + access: read-write + - register: + name: RDN_ECO_CS + description: dsi_bridge rdn eco cs register + addressOffset: 116 + size: 32 + fields: + - name: RDN_ECO_EN + description: rdn_eco_en + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RDN_ECO_RESULT + description: rdn_eco_result + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: RDN_ECO_LOW + description: dsi_bridge rdn eco all low register + addressOffset: 120 + size: 32 + fields: + - name: RDN_ECO_LOW + description: rdn_eco_low + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RDN_ECO_HIGH + description: dsi_bridge rdn eco all high register + addressOffset: 124 + size: 32 + resetValue: 4294967295 + fields: + - name: RDN_ECO_HIGH + description: rdn_eco_high + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HOST_CTRL + description: dsi_bridge host control register + addressOffset: 128 + size: 32 + resetValue: 1 + fields: + - name: DSI_CFG_REF_CLK_EN + description: "this bit configures the clk enable refclk and cfg_clk of dsi_host. 0: disable, 1: enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: MEM_CLK_CTRL + description: dsi_bridge mem force on control register + addressOffset: 132 + size: 32 + fields: + - name: DSI_BRIDGE_MEM_CLK_FORCE_ON + description: "this bit configures the clock force on of dsi_bridge fifo memory. 0: disable, 1: force on" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DSI_MEM_CLK_FORCE_ON + description: "this bit configures the clock force on of dpi fifo memory. 0: disable, 1: force on" + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: DMA_FLOW_CTRL + description: dsi_bridge dma flow controller register + addressOffset: 136 + size: 32 + resetValue: 17 + fields: + - name: DSI_DMA_FLOW_CONTROLLER + description: "this bit configures the flow controller, 0: dmac as flow controller, 1:dsi_bridge as flow controller" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DMA_FLOW_MULTIBLK_NUM + description: this field configures the num of blocks when multi-blk is enable and dmac as flow controller + bitOffset: 4 + bitWidth: 4 + access: read-write + - register: + name: RAW_BUF_ALMOST_EMPTY_THRD + description: dsi_bridge buffer empty threshold register + addressOffset: 140 + size: 32 + resetValue: 512 + fields: + - name: DSI_RAW_BUF_ALMOST_EMPTY_THRD + description: "this field configures the fifo almost empty threshold, is valid only when dmac as flow controller" + bitOffset: 0 + bitWidth: 11 + access: read-write + - register: + name: YUV_CFG + description: dsi_bridge yuv format config register + addressOffset: 144 + size: 32 + fields: + - name: PROTOCAL + description: "this bit configures yuv protoocl, 0: bt.601, 1: bt.709" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: YUV_PIX_ENDIAN + description: "this bit configures yuv pixel endian, 0: y0u0y1v1y2u2y3v3, 1: y3u3y2v2y1u1y0v0" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: YUV422_FORMAT + description: "this field configures yuv422 store format, 0: yuyv, 1: yvyu, 2: uyvy, 3: vyuy" + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: PHY_LP_LOOPBACK_CTRL + description: dsi phy lp_loopback test ctrl + addressOffset: 148 + size: 32 + fields: + - name: PHY_LP_TXDATAESC_1 + description: txdataesc_1 ctrl when enable dsi phy lp_loopback_test + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: PHY_LP_TXREQUESTESC_1 + description: txrequestesc_1 ctrl when enable dsi phy lp_loopback_test + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: PHY_LP_TXVALIDESC_1 + description: txvalidesc_1 ctrl when enable dsi phy lp_loopback_test + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PHY_LP_TXLPDTESC_1 + description: txlpdtesc_1 ctrl when enable dsi phy lp_loopback_test + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: PHY_LP_BASEDIR_1 + description: basedir_1 ctrl when enable dsi phy lp_loopback_test + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: PHY_LP_TXDATAESC_0 + description: txdataesc_0 ctrl when enable dsi phy lp_loopback_test + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: PHY_LP_TXREQUESTESC_0 + description: txrequestesc_0 ctrl when enable dsi phy lp_loopback_test + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PHY_LP_TXVALIDESC_0 + description: txvalidesc_0 ctrl when enable dsi phy lp_loopback_test + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PHY_LP_TXLPDTESC_0 + description: txlpdtesc_0 ctrl when enable dsi phy lp_loopback_test + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: PHY_LP_BASEDIR_0 + description: basedir_0 ctrl when enable dsi phy lp_loopback_test + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: PHY_LP_LOOPBACK_CHECK + description: dsi phy lp_loopback test start check + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: PHY_LP_LOOPBACK_CHECK_DONE + description: dsi phy lp_loopback test check done + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: PHY_LP_LOOPBACK_EN + description: dsi phy lp_loopback ctrl en + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: PHY_LP_LOOPBACK_OK + description: result of dsi phy lp_loopback test + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: PHY_HS_LOOPBACK_CTRL + description: dsi phy hp_loopback test ctrl + addressOffset: 152 + size: 32 + resetValue: 512 + fields: + - name: PHY_HS_TXDATAHS_1 + description: txdatahs_1 ctrl when enable dsi phy hs_loopback_test + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: PHY_HS_TXREQUESTDATAHS_1 + description: txrequestdatahs_1 ctrl when enable dsi phy hs_loopback_test + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: PHY_HS_BASEDIR_1 + description: basedir_1 ctrl when enable dsi phy hs_loopback_test + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PHY_HS_TXDATAHS_0 + description: txdatahs_0 ctrl when enable dsi phy hs_loopback_test + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: PHY_HS_TXREQUESTDATAHS_0 + description: txrequestdatahs_0 ctrl when enable dsi phy hs_loopback_test + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PHY_HS_BASEDIR_0 + description: basedir_0 ctrl when enable dsi phy hs_loopback_test + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PHY_HS_TXREQUESTHSCLK + description: txrequesthsclk when enable dsi phy hs_loopback_test + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: PHY_HS_LOOPBACK_CHECK + description: dsi phy hs_loopback test start check + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: PHY_HS_LOOPBACK_CHECK_DONE + description: dsi phy hs_loopback test check done + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: PHY_HS_LOOPBACK_EN + description: dsi phy hs_loopback ctrl en + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: PHY_HS_LOOPBACK_OK + description: result of dsi phy hs_loopback test + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: PHY_LOOPBACK_CNT + description: loopback test cnt + addressOffset: 156 + size: 32 + resetValue: 4194368 + fields: + - name: PHY_HS_CHECK_CNT_TH + description: hs_loopback test check cnt + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: PHY_LP_CHECK_CNT_TH + description: lp_loopback test check cnt + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: MIPI_DSI_HOST + description: MIPI Display Interface Host + groupName: DSI_HOST + baseAddress: 1342832640 + addressBlock: + - offset: 0 + size: 296 + usage: registers + interrupt: + - name: DSI + value: 88 + registers: + - register: + name: VERSION + description: NA + addressOffset: 0 + size: 32 + resetValue: 825504042 + fields: + - name: VERSION + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PWR_UP + description: NA + addressOffset: 4 + size: 32 + fields: + - name: SHUTDOWNZ + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CLKMGR_CFG + description: NA + addressOffset: 8 + size: 32 + fields: + - name: TX_ESC_CLK_DIVISION + description: NA + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TO_CLK_DIVISION + description: NA + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: DPI_VCID + description: NA + addressOffset: 12 + size: 32 + fields: + - name: DPI_VCID + description: NA + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: DPI_COLOR_CODING + description: NA + addressOffset: 16 + size: 32 + fields: + - name: DPI_COLOR_CODING + description: NA + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: LOOSELY18_EN + description: NA + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: DPI_CFG_POL + description: NA + addressOffset: 20 + size: 32 + fields: + - name: DATAEN_ACTIVE_LOW + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: VSYNC_ACTIVE_LOW + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: HSYNC_ACTIVE_LOW + description: NA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SHUTD_ACTIVE_LOW + description: NA + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: COLORM_ACTIVE_LOW + description: NA + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: DPI_LP_CMD_TIM + description: NA + addressOffset: 24 + size: 32 + fields: + - name: INVACT_LPCMD_TIME + description: NA + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: OUTVACT_LPCMD_TIME + description: NA + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: DBI_VCID + description: NA + addressOffset: 28 + size: 32 + fields: + - name: DBI_VCID + description: NA + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: DBI_CFG + description: NA + addressOffset: 32 + size: 32 + fields: + - name: IN_DBI_CONF + description: NA + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: OUT_DBI_CONF + description: NA + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: LUT_SIZE_CONF + description: NA + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: DBI_PARTITIONING_EN + description: NA + addressOffset: 36 + size: 32 + fields: + - name: PARTITIONING_EN + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DBI_CMDSIZE + description: NA + addressOffset: 40 + size: 32 + fields: + - name: WR_CMD_SIZE + description: NA + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: ALLOWED_CMD_SIZE + description: NA + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: PCKHDL_CFG + description: NA + addressOffset: 44 + size: 32 + fields: + - name: EOTP_TX_EN + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EOTP_RX_EN + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BTA_EN + description: NA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ECC_RX_EN + description: NA + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CRC_RX_EN + description: NA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: EOTP_TX_LP_EN + description: NA + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: GEN_VCID + description: NA + addressOffset: 48 + size: 32 + fields: + - name: RX + description: NA + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: TEAR_AUTO + description: NA + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: TX_AUTO + description: NA + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: MODE_CFG + description: NA + addressOffset: 52 + size: 32 + resetValue: 1 + fields: + - name: CMD_VIDEO_MODE + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: VID_MODE_CFG + description: NA + addressOffset: 56 + size: 32 + fields: + - name: VID_MODE_TYPE + description: NA + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: LP_VSA_EN + description: NA + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: LP_VBP_EN + description: NA + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: LP_VFP_EN + description: NA + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: LP_VACT_EN + description: NA + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: LP_HBP_EN + description: NA + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: LP_HFP_EN + description: NA + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FRAME_BTA_ACK_EN + description: NA + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: LP_CMD_EN + description: NA + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: VPG_EN + description: NA + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: VPG_MODE + description: NA + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: VPG_ORIENTATION + description: NA + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: VID_PKT_SIZE + description: NA + addressOffset: 60 + size: 32 + fields: + - name: VID_PKT_SIZE + description: NA + bitOffset: 0 + bitWidth: 14 + access: read-write + - register: + name: VID_NUM_CHUNKS + description: NA + addressOffset: 64 + size: 32 + fields: + - name: VID_NUM_CHUNKS + description: NA + bitOffset: 0 + bitWidth: 13 + access: read-write + - register: + name: VID_NULL_SIZE + description: NA + addressOffset: 68 + size: 32 + fields: + - name: VID_NULL_SIZE + description: NA + bitOffset: 0 + bitWidth: 13 + access: read-write + - register: + name: VID_HSA_TIME + description: NA + addressOffset: 72 + size: 32 + fields: + - name: VID_HSA_TIME + description: NA + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: VID_HBP_TIME + description: NA + addressOffset: 76 + size: 32 + fields: + - name: VID_HBP_TIME + description: NA + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: VID_HLINE_TIME + description: NA + addressOffset: 80 + size: 32 + fields: + - name: VID_HLINE_TIME + description: NA + bitOffset: 0 + bitWidth: 15 + access: read-write + - register: + name: VID_VSA_LINES + description: NA + addressOffset: 84 + size: 32 + fields: + - name: VSA_LINES + description: NA + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: VID_VBP_LINES + description: NA + addressOffset: 88 + size: 32 + fields: + - name: VBP_LINES + description: NA + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: VID_VFP_LINES + description: NA + addressOffset: 92 + size: 32 + fields: + - name: VFP_LINES + description: NA + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: VID_VACTIVE_LINES + description: NA + addressOffset: 96 + size: 32 + fields: + - name: V_ACTIVE_LINES + description: NA + bitOffset: 0 + bitWidth: 14 + access: read-write + - register: + name: EDPI_CMD_SIZE + description: NA + addressOffset: 100 + size: 32 + fields: + - name: EDPI_ALLOWED_CMD_SIZE + description: NA + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: CMD_MODE_CFG + description: NA + addressOffset: 104 + size: 32 + fields: + - name: TEAR_FX_EN + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ACK_RQST_EN + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: GEN_SW_0P_TX + description: NA + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: GEN_SW_1P_TX + description: NA + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: GEN_SW_2P_TX + description: NA + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GEN_SR_0P_TX + description: NA + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: GEN_SR_1P_TX + description: NA + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: GEN_SR_2P_TX + description: NA + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: GEN_LW_TX + description: NA + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DCS_SW_0P_TX + description: NA + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DCS_SW_1P_TX + description: NA + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: DCS_SR_0P_TX + description: NA + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: DCS_LW_TX + description: NA + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: MAX_RD_PKT_SIZE + description: NA + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: GEN_HDR + description: NA + addressOffset: 108 + size: 32 + fields: + - name: GEN_DT + description: NA + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: GEN_VC + description: NA + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: GEN_WC_LSBYTE + description: NA + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: GEN_WC_MSBYTE + description: NA + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: GEN_PLD_DATA + description: NA + addressOffset: 112 + size: 32 + fields: + - name: GEN_PLD_B1 + description: NA + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GEN_PLD_B2 + description: NA + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: GEN_PLD_B3 + description: NA + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: GEN_PLD_B4 + description: NA + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: CMD_PKT_STATUS + description: NA + addressOffset: 116 + size: 32 + resetValue: 327701 + fields: + - name: GEN_CMD_EMPTY + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: GEN_CMD_FULL + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: GEN_PLD_W_EMPTY + description: NA + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: GEN_PLD_W_FULL + description: NA + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: GEN_PLD_R_EMPTY + description: NA + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: GEN_PLD_R_FULL + description: NA + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: GEN_RD_CMD_BUSY + description: NA + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: GEN_BUFF_CMD_EMPTY + description: NA + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: GEN_BUFF_CMD_FULL + description: NA + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: GEN_BUFF_PLD_EMPTY + description: NA + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: GEN_BUFF_PLD_FULL + description: NA + bitOffset: 19 + bitWidth: 1 + access: read-only + - register: + name: TO_CNT_CFG + description: NA + addressOffset: 120 + size: 32 + fields: + - name: LPRX_TO_CNT + description: NA + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: HSTX_TO_CNT + description: NA + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: HS_RD_TO_CNT + description: NA + addressOffset: 124 + size: 32 + fields: + - name: HS_RD_TO_CNT + description: NA + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: LP_RD_TO_CNT + description: NA + addressOffset: 128 + size: 32 + fields: + - name: LP_RD_TO_CNT + description: NA + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: HS_WR_TO_CNT + description: NA + addressOffset: 132 + size: 32 + fields: + - name: HS_WR_TO_CNT + description: NA + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: LP_WR_TO_CNT + description: NA + addressOffset: 136 + size: 32 + fields: + - name: LP_WR_TO_CNT + description: NA + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: BTA_TO_CNT + description: NA + addressOffset: 140 + size: 32 + fields: + - name: BTA_TO_CNT + description: NA + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: SDF_3D + description: NA + addressOffset: 144 + size: 32 + fields: + - name: MODE_3D + description: NA + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: FORMAT_3D + description: NA + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: SECOND_VSYNC + description: NA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RIGHT_FIRST + description: NA + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SEND_3D_CFG + description: NA + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: LPCLK_CTRL + description: NA + addressOffset: 148 + size: 32 + fields: + - name: PHY_TXREQUESTCLKHS + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: AUTO_CLKLANE_CTRL + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: PHY_TMR_LPCLK_CFG + description: NA + addressOffset: 152 + size: 32 + fields: + - name: PHY_CLKLP2HS_TIME + description: NA + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: PHY_CLKHS2LP_TIME + description: NA + bitOffset: 16 + bitWidth: 10 + access: read-write + - register: + name: PHY_TMR_CFG + description: NA + addressOffset: 156 + size: 32 + fields: + - name: PHY_LP2HS_TIME + description: NA + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: PHY_HS2LP_TIME + description: NA + bitOffset: 16 + bitWidth: 10 + access: read-write + - register: + name: PHY_RSTZ + description: NA + addressOffset: 160 + size: 32 + fields: + - name: PHY_SHUTDOWNZ + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PHY_RSTZ + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PHY_ENABLECLK + description: NA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PHY_FORCEPLL + description: NA + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: PHY_IF_CFG + description: NA + addressOffset: 164 + size: 32 + resetValue: 1 + fields: + - name: N_LANES + description: NA + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: PHY_STOP_WAIT_TIME + description: NA + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: PHY_ULPS_CTRL + description: NA + addressOffset: 168 + size: 32 + fields: + - name: PHY_TXREQULPSCLK + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PHY_TXEXITULPSCLK + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PHY_TXREQULPSLAN + description: NA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PHY_TXEXITULPSLAN + description: NA + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: PHY_TX_TRIGGERS + description: NA + addressOffset: 172 + size: 32 + fields: + - name: PHY_TX_TRIGGERS + description: NA + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: PHY_STATUS + description: NA + addressOffset: 176 + size: 32 + resetValue: 320 + fields: + - name: PHY_LOCK + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PHY_DIRECTION + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: PHY_STOPSTATECLKLANE + description: NA + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: PHY_ULPSACTIVENOTCLK + description: NA + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: PHY_STOPSTATE0LANE + description: NA + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: PHY_ULPSACTIVENOT0LANE + description: NA + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: PHY_RXULPSESC0LANE + description: NA + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: PHY_STOPSTATE1LANE + description: NA + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: PHY_ULPSACTIVENOT1LANE + description: NA + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: PHY_TST_CTRL0 + description: NA + addressOffset: 180 + size: 32 + resetValue: 1 + fields: + - name: PHY_TESTCLR + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PHY_TESTCLK + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: PHY_TST_CTRL1 + description: NA + addressOffset: 184 + size: 32 + fields: + - name: PHY_TESTDIN + description: NA + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: PHT_TESTDOUT + description: NA + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: PHY_TESTEN + description: NA + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: INT_ST0 + description: NA + addressOffset: 188 + size: 32 + fields: + - name: ACK_WITH_ERR_0 + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ACK_WITH_ERR_1 + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ACK_WITH_ERR_2 + description: NA + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: ACK_WITH_ERR_3 + description: NA + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: ACK_WITH_ERR_4 + description: NA + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ACK_WITH_ERR_5 + description: NA + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ACK_WITH_ERR_6 + description: NA + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: ACK_WITH_ERR_7 + description: NA + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: ACK_WITH_ERR_8 + description: NA + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: ACK_WITH_ERR_9 + description: NA + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: ACK_WITH_ERR_10 + description: NA + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: ACK_WITH_ERR_11 + description: NA + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: ACK_WITH_ERR_12 + description: NA + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: ACK_WITH_ERR_13 + description: NA + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: ACK_WITH_ERR_14 + description: NA + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: ACK_WITH_ERR_15 + description: NA + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: DPHY_ERRORS_0 + description: NA + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: DPHY_ERRORS_1 + description: NA + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: DPHY_ERRORS_2 + description: NA + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: DPHY_ERRORS_3 + description: NA + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: DPHY_ERRORS_4 + description: NA + bitOffset: 20 + bitWidth: 1 + access: read-only + - register: + name: INT_ST1 + description: NA + addressOffset: 192 + size: 32 + fields: + - name: TO_HS_TX + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TO_LP_RX + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ECC_SINGLE_ERR + description: NA + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: ECC_MILTI_ERR + description: NA + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: CRC_ERR + description: NA + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: PKT_SIZE_ERR + description: NA + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: EOPT_ERR + description: NA + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: DPI_PLD_WR_ERR + description: NA + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: GEN_CMD_WR_ERR + description: NA + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: GEN_PLD_WR_ERR + description: NA + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: GEN_PLD_SEND_ERR + description: NA + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: GEN_PLD_RD_ERR + description: NA + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: GEN_PLD_RECEV_ERR + description: NA + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: DPI_BUFF_PLD_UNDER + description: NA + bitOffset: 19 + bitWidth: 1 + access: read-only + - register: + name: INT_MSK0 + description: NA + addressOffset: 196 + size: 32 + fields: + - name: MASK_ACK_WITH_ERR_0 + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MASK_ACK_WITH_ERR_1 + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MASK_ACK_WITH_ERR_2 + description: NA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MASK_ACK_WITH_ERR_3 + description: NA + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MASK_ACK_WITH_ERR_4 + description: NA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MASK_ACK_WITH_ERR_5 + description: NA + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: MASK_ACK_WITH_ERR_6 + description: NA + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: MASK_ACK_WITH_ERR_7 + description: NA + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: MASK_ACK_WITH_ERR_8 + description: NA + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: MASK_ACK_WITH_ERR_9 + description: NA + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: MASK_ACK_WITH_ERR_10 + description: NA + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: MASK_ACK_WITH_ERR_11 + description: NA + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: MASK_ACK_WITH_ERR_12 + description: NA + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: MASK_ACK_WITH_ERR_13 + description: NA + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: MASK_ACK_WITH_ERR_14 + description: NA + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: MASK_ACK_WITH_ERR_15 + description: NA + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: MASK_DPHY_ERRORS_0 + description: NA + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: MASK_DPHY_ERRORS_1 + description: NA + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MASK_DPHY_ERRORS_2 + description: NA + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: MASK_DPHY_ERRORS_3 + description: NA + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: MASK_DPHY_ERRORS_4 + description: NA + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: INT_MSK1 + description: NA + addressOffset: 200 + size: 32 + fields: + - name: MASK_TO_HS_TX + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MASK_TO_LP_RX + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MASK_ECC_SINGLE_ERR + description: NA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MASK_ECC_MILTI_ERR + description: NA + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MASK_CRC_ERR + description: NA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MASK_PKT_SIZE_ERR + description: NA + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: MASK_EOPT_ERR + description: NA + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: MASK_DPI_PLD_WR_ERR + description: NA + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: MASK_GEN_CMD_WR_ERR + description: NA + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: MASK_GEN_PLD_WR_ERR + description: NA + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: MASK_GEN_PLD_SEND_ERR + description: NA + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: MASK_GEN_PLD_RD_ERR + description: NA + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: MASK_GEN_PLD_RECEV_ERR + description: NA + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: MASK_DPI_BUFF_PLD_UNDER + description: NA + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: PHY_CAL + description: NA + addressOffset: 204 + size: 32 + fields: + - name: TXSKEWCALHS + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: INT_FORCE0 + description: NA + addressOffset: 216 + size: 32 + fields: + - name: FORCE_ACK_WITH_ERR_0 + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FORCE_ACK_WITH_ERR_1 + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FORCE_ACK_WITH_ERR_2 + description: NA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FORCE_ACK_WITH_ERR_3 + description: NA + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FORCE_ACK_WITH_ERR_4 + description: NA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FORCE_ACK_WITH_ERR_5 + description: NA + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FORCE_ACK_WITH_ERR_6 + description: NA + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FORCE_ACK_WITH_ERR_7 + description: NA + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FORCE_ACK_WITH_ERR_8 + description: NA + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FORCE_ACK_WITH_ERR_9 + description: NA + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FORCE_ACK_WITH_ERR_10 + description: NA + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FORCE_ACK_WITH_ERR_11 + description: NA + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FORCE_ACK_WITH_ERR_12 + description: NA + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FORCE_ACK_WITH_ERR_13 + description: NA + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FORCE_ACK_WITH_ERR_14 + description: NA + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: FORCE_ACK_WITH_ERR_15 + description: NA + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: FORCE_DPHY_ERRORS_0 + description: NA + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FORCE_DPHY_ERRORS_1 + description: NA + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: FORCE_DPHY_ERRORS_2 + description: NA + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: FORCE_DPHY_ERRORS_3 + description: NA + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: FORCE_DPHY_ERRORS_4 + description: NA + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: INT_FORCE1 + description: NA + addressOffset: 220 + size: 32 + fields: + - name: FORCE_TO_HS_TX + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FORCE_TO_LP_RX + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FORCE_ECC_SINGLE_ERR + description: NA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FORCE_ECC_MILTI_ERR + description: NA + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FORCE_CRC_ERR + description: NA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FORCE_PKT_SIZE_ERR + description: NA + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FORCE_EOPT_ERR + description: NA + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FORCE_DPI_PLD_WR_ERR + description: NA + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FORCE_GEN_CMD_WR_ERR + description: NA + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FORCE_GEN_PLD_WR_ERR + description: NA + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FORCE_GEN_PLD_SEND_ERR + description: NA + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FORCE_GEN_PLD_RD_ERR + description: NA + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FORCE_GEN_PLD_RECEV_ERR + description: NA + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FORCE_DPI_BUFF_PLD_UNDER + description: NA + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: DSC_PARAMETER + description: NA + addressOffset: 240 + size: 32 + fields: + - name: COMPRESSION_MODE + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: COMPRESS_ALGO + description: NA + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: PPS_SEL + description: NA + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: PHY_TMR_RD_CFG + description: NA + addressOffset: 244 + size: 32 + fields: + - name: MAX_RD_TIME + description: NA + bitOffset: 0 + bitWidth: 15 + access: read-write + - register: + name: VID_SHADOW_CTRL + description: NA + addressOffset: 256 + size: 32 + fields: + - name: VID_SHADOW_EN + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: VID_SHADOW_REQ + description: NA + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: VID_SHADOW_PIN_REQ + description: NA + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: DPI_VCID_ACT + description: NA + addressOffset: 268 + size: 32 + fields: + - name: DPI_VCID_ACT + description: NA + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: DPI_COLOR_CODING_ACT + description: NA + addressOffset: 272 + size: 32 + fields: + - name: DPI_COLOR_CODING_ACT + description: NA + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: LOOSELY18_EN_ACT + description: NA + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: DPI_LP_CMD_TIM_ACT + description: NA + addressOffset: 280 + size: 32 + fields: + - name: INVACT_LPCMD_TIME_ACT + description: NA + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: OUTVACT_LPCMD_TIME_ACT + description: NA + bitOffset: 16 + bitWidth: 8 + access: read-only + - register: + name: EDPI_TE_HW_CFG + description: NA + addressOffset: 284 + size: 32 + fields: + - name: HW_TEAR_EFFECT_ON + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: HW_TEAR_EFFECT_GEN + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: HW_SET_SCAN_LINE + description: NA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SCAN_LINE_PARAMETER + description: NA + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: VID_MODE_CFG_ACT + description: NA + addressOffset: 312 + size: 32 + fields: + - name: VID_MODE_TYPE_ACT + description: NA + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: LP_VSA_EN_ACT + description: NA + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: LP_VBP_EN_ACT + description: NA + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: LP_VFP_EN_ACT + description: NA + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: LP_VACT_EN_ACT + description: NA + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: LP_HBP_EN_ACT + description: NA + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: LP_HFP_EN_ACT + description: NA + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: FRAME_BTA_ACK_EN_ACT + description: NA + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: LP_CMD_EN_ACT + description: NA + bitOffset: 9 + bitWidth: 1 + access: read-only + - register: + name: VID_PKT_SIZE_ACT + description: NA + addressOffset: 316 + size: 32 + fields: + - name: VID_PKT_SIZE_ACT + description: NA + bitOffset: 0 + bitWidth: 14 + access: read-only + - register: + name: VID_NUM_CHUNKS_ACT + description: NA + addressOffset: 320 + size: 32 + fields: + - name: VID_NUM_CHUNKS_ACT + description: NA + bitOffset: 0 + bitWidth: 13 + access: read-only + - register: + name: VID_NULL_SIZE_ACT + description: NA + addressOffset: 324 + size: 32 + fields: + - name: VID_NULL_SIZE_ACT + description: NA + bitOffset: 0 + bitWidth: 13 + access: read-only + - register: + name: VID_HSA_TIME_ACT + description: NA + addressOffset: 328 + size: 32 + fields: + - name: VID_HSA_TIME_ACT + description: NA + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: VID_HBP_TIME_ACT + description: NA + addressOffset: 332 + size: 32 + fields: + - name: VID_HBP_TIME_ACT + description: NA + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: VID_HLINE_TIME_ACT + description: NA + addressOffset: 336 + size: 32 + fields: + - name: VID_HLINE_TIME_ACT + description: NA + bitOffset: 0 + bitWidth: 15 + access: read-only + - register: + name: VID_VSA_LINES_ACT + description: NA + addressOffset: 340 + size: 32 + fields: + - name: VSA_LINES_ACT + description: NA + bitOffset: 0 + bitWidth: 10 + access: read-only + - register: + name: VID_VBP_LINES_ACT + description: NA + addressOffset: 344 + size: 32 + fields: + - name: VBP_LINES_ACT + description: NA + bitOffset: 0 + bitWidth: 10 + access: read-only + - register: + name: VID_VFP_LINES_ACT + description: NA + addressOffset: 348 + size: 32 + fields: + - name: VFP_LINES_ACT + description: NA + bitOffset: 0 + bitWidth: 10 + access: read-only + - register: + name: VID_VACTIVE_LINES_ACT + description: NA + addressOffset: 352 + size: 32 + fields: + - name: V_ACTIVE_LINES_ACT + description: NA + bitOffset: 0 + bitWidth: 14 + access: read-only + - register: + name: VID_PKT_STATUS + description: NA + addressOffset: 360 + size: 32 + resetValue: 65541 + fields: + - name: DPI_CMD_W_EMPTY + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DPI_CMD_W_FULL + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: DPI_PLD_W_EMPTY + description: NA + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: DPI_PLD_W_FULL + description: NA + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DPI_BUFF_PLD_EMPTY + description: NA + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: DPI_BUFF_PLD_FULL + description: NA + bitOffset: 17 + bitWidth: 1 + access: read-only + - register: + name: SDF_3D_ACT + description: NA + addressOffset: 400 + size: 32 + fields: + - name: MODE_3D_ACT + description: NA + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: FORMAT_3D_ACT + description: NA + bitOffset: 2 + bitWidth: 2 + access: read-only + - name: SECOND_VSYNC_ACT + description: NA + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: RIGHT_FIRST_ACT + description: NA + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SEND_3D_CFG_ACT + description: NA + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: ECC + description: ECC (ECC Hardware Accelerator) + groupName: ECC + baseAddress: 1342779392 + addressBlock: + - offset: 0 + size: 120 + usage: registers + interrupt: + - name: ECC + value: 71 + registers: + - register: + name: MULT_INT_RAW + description: "ECC interrupt raw register, valid in level." + addressOffset: 12 + size: 32 + fields: + - name: CALC_DONE_INT_RAW + description: The raw interrupt status bit for the ecc_calc_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: MULT_INT_ST + description: ECC interrupt status register. + addressOffset: 16 + size: 32 + fields: + - name: CALC_DONE_INT_ST + description: The masked interrupt status bit for the ecc_calc_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: MULT_INT_ENA + description: ECC interrupt enable register. + addressOffset: 20 + size: 32 + fields: + - name: CALC_DONE_INT_ENA + description: The interrupt enable bit for the ecc_calc_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: MULT_INT_CLR + description: ECC interrupt clear register. + addressOffset: 24 + size: 32 + fields: + - name: CALC_DONE_INT_CLR + description: Set this bit to clear the ecc_calc_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: MULT_CONF + description: ECC configure register + addressOffset: 28 + size: 32 + fields: + - name: START + description: Write 1 to start caculation of ECC Accelerator. This bit will be self-cleared after the caculatrion is done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RESET + description: Write 1 to reset ECC Accelerator. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: KEY_LENGTH + description: "The key length mode bit of ECC Accelerator. 0: P-192. 1: P-256." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MOD_BASE + description: "The mod base of mod operation, only valid in work_mode 8-11. 0: n(order of curve). 1: p(mod base of curve)" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: WORK_MODE + description: "The work mode bits of ECC Accelerator. 0: Point Mult Mode. 1: Reserved. 2: Point verification mode. 3: Point Verif+mult mode. 4: Jacobian Point Mult Mode. 5: Point Add Mode. 6: Jacobian Point Verification Mode. 7: Point Verif + Jacobian Mult Mode. 8: mod addition. 9. mod substraction. 10: mod multiplication. 11: mod division." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: SECURITY_MODE + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: VERIFICATION_RESULT + description: "The verification result bit of ECC Accelerator, only valid when calculation is done." + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: CLK_EN + description: Write 1 to force on register clock gate. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: MEM_CLOCK_GATE_FORCE_ON + description: ECC memory clock gate force on register + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: MULT_DATE + description: Version control register + addressOffset: 252 + size: 32 + resetValue: 36720704 + fields: + - name: DATE + description: ECC mult version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + name: "K_MEM[%s]" + description: The memory that stores k. + addressOffset: 256 + size: 32 + - register: + dim: 8 + dimIncrement: 4 + name: "PX_MEM[%s]" + description: The memory that stores Px. + addressOffset: 288 + size: 32 + - register: + dim: 8 + dimIncrement: 4 + name: "PY_MEM[%s]" + description: The memory that stores Py. + addressOffset: 320 + size: 32 + - name: ECDSA + description: ECDSA (Elliptic Curve Digital Signature Algorithm) Accelerator + groupName: ECDSA + baseAddress: 1342791680 + addressBlock: + - offset: 0 + size: 248 + usage: registers + registers: + - register: + name: CONF + description: ECDSA configure register + addressOffset: 4 + size: 32 + fields: + - name: WORK_MODE + description: "The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature Generate Mode. 2: Export Public Key Mode. 3: invalid." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: ECC_CURVE + description: "The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SOFTWARE_SET_K + description: "The source of k select bit. 0: k is automatically generated by hardware. 1: k is written by software." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SOFTWARE_SET_Z + description: "The source of z select bit. 0: z is generated from SHA result. 1: z is written by software." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DETERMINISTIC_K + description: "The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by deterministic derivation algorithm." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DETERMINISTIC_LOOP + description: The (loop number - 1) value in the deterministic derivation algorithm to derive k. + bitOffset: 6 + bitWidth: 16 + access: read-write + - register: + name: CLK + description: ECDSA clock gate register + addressOffset: 8 + size: 32 + fields: + - name: GATE_FORCE_ON + description: Write 1 to force on register clock gate. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: "ECDSA interrupt raw register, valid in level." + addressOffset: 12 + size: 32 + fields: + - name: CALC_DONE_INT_RAW + description: The raw interrupt status bit for the ecdsa_calc_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SHA_RELEASE_INT_RAW + description: The raw interrupt status bit for the ecdsa_sha_release_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: ECDSA interrupt status register. + addressOffset: 16 + size: 32 + fields: + - name: CALC_DONE_INT_ST + description: The masked interrupt status bit for the ecdsa_calc_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SHA_RELEASE_INT_ST + description: The masked interrupt status bit for the ecdsa_sha_release_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: ECDSA interrupt enable register. + addressOffset: 20 + size: 32 + fields: + - name: CALC_DONE_INT_ENA + description: The interrupt enable bit for the ecdsa_calc_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SHA_RELEASE_INT_ENA + description: The interrupt enable bit for the ecdsa_sha_release_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: ECDSA interrupt clear register. + addressOffset: 24 + size: 32 + fields: + - name: CALC_DONE_INT_CLR + description: Set this bit to clear the ecdsa_calc_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SHA_RELEASE_INT_CLR + description: Set this bit to clear the ecdsa_sha_release_int interrupt + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: START + description: ECDSA start register + addressOffset: 28 + size: 32 + fields: + - name: START + description: Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared after configuration. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: LOAD_DONE + description: Write 1 to input load done signal of ECDSA Accelerator. This bit will be self-cleared after configuration. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: GET_DONE + description: Write 1 to input get done signal of ECDSA Accelerator. This bit will be self-cleared after configuration. + bitOffset: 2 + bitWidth: 1 + access: write-only + - register: + name: STATE + description: ECDSA status register + addressOffset: 32 + size: 32 + fields: + - name: BUSY + description: "The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY state." + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: RESULT + description: ECDSA result register + addressOffset: 36 + size: 32 + fields: + - name: OPERATION_RESULT + description: "The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is done." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: K_VALUE_WARNING + description: "The k value warning bit of ECDSA Accelerator, valid when k value is bigger than the curve order, then actually taken k = k mod n." + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: Version control register + addressOffset: 252 + size: 32 + resetValue: 36716656 + fields: + - name: DATE + description: ECDSA version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + name: SHA_MODE + description: ECDSA control SHA register + addressOffset: 512 + size: 32 + fields: + - name: SHA_MODE + description: "The work mode bits of SHA Calculator in ECDSA Accelerator. 1: SHA-224. 2: SHA-256. Others: invalid." + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: SHA_START + description: ECDSA control SHA register + addressOffset: 528 + size: 32 + fields: + - name: SHA_START + description: Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This bit will be self-cleared after configuration. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SHA_CONTINUE + description: ECDSA control SHA register + addressOffset: 532 + size: 32 + fields: + - name: SHA_CONTINUE + description: Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This bit will be self-cleared after configuration. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SHA_BUSY + description: ECDSA status register + addressOffset: 536 + size: 32 + fields: + - name: SHA_BUSY + description: "The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in calculation. 0: SHA is idle." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + dim: 8 + dimIncrement: 4 + name: "MESSAGE_MEM[%s]" + description: The memory that stores message. + addressOffset: 640 + size: 32 + - register: + dim: 8 + dimIncrement: 4 + name: "R_MEM[%s]" + description: The memory that stores r. + addressOffset: 2560 + size: 32 + - register: + dim: 8 + dimIncrement: 4 + name: "S_MEM[%s]" + description: The memory that stores s. + addressOffset: 2592 + size: 32 + - register: + dim: 8 + dimIncrement: 4 + name: "Z_MEM[%s]" + description: The memory that stores software written z. + addressOffset: 2624 + size: 32 + - register: + dim: 8 + dimIncrement: 4 + name: "QAX_MEM[%s]" + description: The memory that stores x coordinates of QA or software written k. + addressOffset: 2656 + size: 32 + - register: + dim: 8 + dimIncrement: 4 + name: "QAY_MEM[%s]" + description: The memory that stores y coordinates of QA. + addressOffset: 2688 + size: 32 + - name: EFUSE + description: eFuse Controller + groupName: EFUSE + baseAddress: 1343410176 + addressBlock: + - offset: 0 + size: 984 + usage: registers + registers: + - register: + name: PGM_DATA0 + description: Register 0 that stores data to be programmed. + addressOffset: 0 + size: 32 + fields: + - name: PGM_DATA_0 + description: Configures the 0th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA1 + description: Register 1 that stores data to be programmed. + addressOffset: 4 + size: 32 + fields: + - name: PGM_DATA_1 + description: Configures the 1st 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA2 + description: Register 2 that stores data to be programmed. + addressOffset: 8 + size: 32 + fields: + - name: PGM_DATA_2 + description: Configures the 2nd 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA3 + description: Register 3 that stores data to be programmed. + addressOffset: 12 + size: 32 + fields: + - name: PGM_DATA_3 + description: Configures the 3rd 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA4 + description: Register 4 that stores data to be programmed. + addressOffset: 16 + size: 32 + fields: + - name: PGM_DATA_4 + description: Configures the 4th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA5 + description: Register 5 that stores data to be programmed. + addressOffset: 20 + size: 32 + fields: + - name: PGM_DATA_5 + description: Configures the 5th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA6 + description: Register 6 that stores data to be programmed. + addressOffset: 24 + size: 32 + fields: + - name: PGM_DATA_6 + description: Configures the 6th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA7 + description: Register 7 that stores data to be programmed. + addressOffset: 28 + size: 32 + fields: + - name: PGM_DATA_7 + description: Configures the 7th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_CHECK_VALUE0 + description: Register 0 that stores the RS code to be programmed. + addressOffset: 32 + size: 32 + fields: + - name: PGM_RS_DATA_0 + description: Configures the 0th 32-bit RS code to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_CHECK_VALUE1 + description: Register 1 that stores the RS code to be programmed. + addressOffset: 36 + size: 32 + fields: + - name: PGM_RS_DATA_1 + description: Configures the 1st 32-bit RS code to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_CHECK_VALUE2 + description: Register 2 that stores the RS code to be programmed. + addressOffset: 40 + size: 32 + fields: + - name: PGM_RS_DATA_2 + description: Configures the 2nd 32-bit RS code to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RD_WR_DIS + description: BLOCK0 data register 0. + addressOffset: 44 + size: 32 + fields: + - name: WR_DIS + description: "Represents whether programming of individual eFuse memory bit is disabled or enabled. 1: Disabled. 0 Enabled." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_REPEAT_DATA0 + description: BLOCK0 data register 1. + addressOffset: 48 + size: 32 + fields: + - name: RD_DIS + description: "Represents whether reading of individual eFuse block(block4~block10) is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 0 + bitWidth: 7 + access: read-only + - name: USB_DEVICE_EXCHG_PINS + description: Enable usb device exchange pins of D+ and D-. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: USB_OTG11_EXCHG_PINS + description: Enable usb otg11 exchange pins of D+ and D-. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DIS_USB_JTAG + description: "Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: POWERGLITCH_EN + description: "Represents whether power glitch function is enabled. 1: enabled. 0: disabled." + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: DIS_USB_SERIAL_JTAG + description: "Represents whether USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: DIS_FORCE_DOWNLOAD + description: "Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SPI_DOWNLOAD_MSPI_DIS + description: Set this bit to disable accessing MSPI flash/MSPI ram by SYS AXI matrix during boot_mode_download. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: DIS_TWAI + description: "Represents whether TWAI function is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: JTAG_SEL_ENABLE + description: "Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled. 0: disabled." + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SOFT_DIS_JTAG + description: "Represents whether JTAG is disabled in soft way. Odd number: disabled. Even number: enabled." + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: DIS_PAD_JTAG + description: "Represents whether JTAG is disabled in the hard way(permanently). 1: disabled. 0: enabled." + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_MANUAL_ENCRYPT + description: "Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled." + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: USB_DEVICE_DREFH + description: "USB intphy of usb device signle-end input high threshold, 1.76V to 2V. Step by 80mV" + bitOffset: 21 + bitWidth: 2 + access: read-only + - name: USB_OTG11_DREFH + description: "USB intphy of usb otg11 signle-end input high threshold, 1.76V to 2V. Step by 80mV" + bitOffset: 23 + bitWidth: 2 + access: read-only + - name: USB_PHY_SEL + description: TBD + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: KM_HUK_GEN_STATE_LOW + description: "Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid." + bitOffset: 26 + bitWidth: 6 + access: read-only + - register: + name: RD_REPEAT_DATA1 + description: BLOCK0 data register 2. + addressOffset: 52 + size: 32 + fields: + - name: KM_HUK_GEN_STATE_HIGH + description: "Set this bit to control validation of HUK generate mode. Odd of 1 is invalid, even of 1 is valid." + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: KM_RND_SWITCH_CYCLE + description: "Set bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles." + bitOffset: 3 + bitWidth: 2 + access: read-only + - name: KM_DEPLOY_ONLY_ONCE + description: "Set each bit to control whether corresponding key can only be deployed once. 1 is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds." + bitOffset: 5 + bitWidth: 4 + access: read-only + - name: FORCE_USE_KEY_MANAGER_KEY + description: "Set each bit to control whether corresponding key must come from key manager.. 1 is true, 0 is false. Bit0: ecdsa. Bit1: xts. Bit2: hmac. Bit3: ds." + bitOffset: 9 + bitWidth: 4 + access: read-only + - name: FORCE_DISABLE_SW_INIT_KEY + description: "Set this bit to disable software written init key, and force use efuse_init_key." + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: XTS_KEY_LENGTH_256 + description: "Set this bit to configure flash encryption use xts-128 key, else use xts-256 key." + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: WDT_DELAY_SEL + description: "Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected." + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: SPI_BOOT_CRYPT_CNT + description: "Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 1: enabled. Even number of 1: disabled." + bitOffset: 18 + bitWidth: 3 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE0 + description: "Represents whether revoking first secure boot key is enabled or disabled. 1: enabled. 0: disabled." + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE1 + description: "Represents whether revoking second secure boot key is enabled or disabled. 1: enabled. 0: disabled." + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE2 + description: "Represents whether revoking third secure boot key is enabled or disabled. 1: enabled. 0: disabled." + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: KEY_PURPOSE_0 + description: Represents the purpose of Key0. + bitOffset: 24 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_1 + description: Represents the purpose of Key1. + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_REPEAT_DATA2 + description: BLOCK0 data register 3. + addressOffset: 56 + size: 32 + resetValue: 524288 + fields: + - name: KEY_PURPOSE_2 + description: Represents the purpose of Key2. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_3 + description: Represents the purpose of Key3. + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_4 + description: Represents the purpose of Key4. + bitOffset: 8 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_5 + description: Represents the purpose of Key5. + bitOffset: 12 + bitWidth: 4 + access: read-only + - name: SEC_DPA_LEVEL + description: Represents the spa secure level by configuring the clock random divide mode. + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: ECDSA_ENABLE_SOFT_K + description: "Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used." + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: CRYPT_DPA_ENABLE + description: "Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled." + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_EN + description: "Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled." + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_AGGRESSIVE_REVOKE + description: "Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled." + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: FLASH_TYPE + description: "The type of interfaced flash. 0: four data lines, 1: eight data lines." + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: FLASH_PAGE_SIZE + description: Set flash page size. + bitOffset: 24 + bitWidth: 2 + access: read-only + - name: FLASH_ECC_EN + description: Set this bit to enable ecc for flash boot. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: DIS_USB_OTG_DOWNLOAD_MODE + description: Set this bit to disable download via USB-OTG. + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: FLASH_TPUW + description: "Represents the flash waiting time after power-up, in unit of ms. When the value less than 15, the waiting time is the programmed value. Otherwise, the waiting time is 2 times the programmed value." + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_REPEAT_DATA3 + description: BLOCK0 data register 4. + addressOffset: 60 + size: 32 + fields: + - name: DIS_DOWNLOAD_MODE + description: "Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DIS_DIRECT_BOOT + description: "Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: DIS_USB_SERIAL_JTAG_ROM_PRINT + description: "Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: LOCK_KM_KEY + description: TBD + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + description: "Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: disabled. 0: enabled." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ENABLE_SECURITY_DOWNLOAD + description: "Represents whether security download is enabled or disabled. 1: enabled. 0: disabled." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: UART_PRINT_CONTROL + description: "Represents the type of UART printing. 00: force enable printing. 01: enable printing when GPIO8 is reset at low level. 10: enable printing when GPIO8 is reset at high level. 11: force disable printing." + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: FORCE_SEND_RESUME + description: "Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced. 0:not forced." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SECURE_VERSION + description: Represents the version used by ESP-IDF anti-rollback feature. + bitOffset: 9 + bitWidth: 16 + access: read-only + - name: SECURE_BOOT_DISABLE_FAST_WAKE + description: "Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled. 1: disabled. 0: enabled." + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: HYS_EN_PAD + description: "Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled. 0:disabled." + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: DCDC_VSET + description: Set the dcdc voltage default. + bitOffset: 27 + bitWidth: 5 + access: read-only + - register: + name: RD_REPEAT_DATA4 + description: BLOCK0 data register 5. + addressOffset: 64 + size: 32 + fields: + - name: _0PXA_TIEH_SEL_0 + description: TBD + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: _0PXA_TIEH_SEL_1 + description: TBD. + bitOffset: 2 + bitWidth: 2 + access: read-only + - name: _0PXA_TIEH_SEL_2 + description: TBD. + bitOffset: 4 + bitWidth: 2 + access: read-only + - name: _0PXA_TIEH_SEL_3 + description: TBD. + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: KM_DISABLE_DEPLOY_MODE + description: TBD. + bitOffset: 8 + bitWidth: 4 + access: read-only + - name: USB_DEVICE_DREFL + description: "Represents the usb device single-end input low threhold, 0.8 V to 1.04 V with step of 80 mV." + bitOffset: 12 + bitWidth: 2 + access: read-only + - name: USB_OTG11_DREFL + description: "Represents the usb otg11 single-end input low threhold, 0.8 V to 1.04 V with step of 80 mV." + bitOffset: 14 + bitWidth: 2 + access: read-only + - name: HP_PWR_SRC_SEL + description: "HP system power source select. 0:LDO. 1: DCDC." + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: DCDC_VSET_EN + description: Select dcdc vset use efuse_dcdc_vset. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: DIS_WDT + description: Set this bit to disable watch dog. + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: DIS_SWD + description: Set this bit to disable super-watchdog. + bitOffset: 21 + bitWidth: 1 + access: read-only + - register: + name: RD_MAC_SYS_0 + description: BLOCK1 data register $n. + addressOffset: 68 + size: 32 + fields: + - name: MAC_0 + description: Stores the low 32 bits of MAC address. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_MAC_SYS_1 + description: BLOCK1 data register $n. + addressOffset: 72 + size: 32 + fields: + - name: MAC_1 + description: Stores the high 16 bits of MAC address. + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: MAC_EXT + description: Stores the extended bits of MAC address. + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: RD_MAC_SYS_2 + description: BLOCK1 data register $n. + addressOffset: 76 + size: 32 + fields: + - name: MAC_RESERVED_1 + description: Reserved. + bitOffset: 0 + bitWidth: 14 + access: read-only + - name: MAC_RESERVED_0 + description: Reserved. + bitOffset: 14 + bitWidth: 18 + access: read-only + - register: + name: RD_MAC_SYS_3 + description: BLOCK1 data register $n. + addressOffset: 80 + size: 32 + fields: + - name: MAC_RESERVED_2 + description: Reserved. + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: SYS_DATA_PART0_0 + description: Stores the first 14 bits of the zeroth part of system data. + bitOffset: 18 + bitWidth: 14 + access: read-only + - register: + name: RD_MAC_SYS_4 + description: BLOCK1 data register $n. + addressOffset: 84 + size: 32 + fields: + - name: SYS_DATA_PART0_1 + description: Stores the first 32 bits of the zeroth part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_MAC_SYS_5 + description: BLOCK1 data register $n. + addressOffset: 88 + size: 32 + fields: + - name: SYS_DATA_PART0_2 + description: Stores the second 32 bits of the zeroth part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA0 + description: Register $n of BLOCK2 (system). + addressOffset: 92 + size: 32 + fields: + - name: SYS_DATA_PART1_0 + description: Stores the zeroth 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA1 + description: Register $n of BLOCK2 (system). + addressOffset: 96 + size: 32 + fields: + - name: SYS_DATA_PART1_1 + description: Stores the first 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA2 + description: Register $n of BLOCK2 (system). + addressOffset: 100 + size: 32 + fields: + - name: SYS_DATA_PART1_2 + description: Stores the second 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA3 + description: Register $n of BLOCK2 (system). + addressOffset: 104 + size: 32 + fields: + - name: SYS_DATA_PART1_3 + description: Stores the third 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA4 + description: Register $n of BLOCK2 (system). + addressOffset: 108 + size: 32 + fields: + - name: SYS_DATA_PART1_4 + description: Stores the fourth 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA5 + description: Register $n of BLOCK2 (system). + addressOffset: 112 + size: 32 + fields: + - name: SYS_DATA_PART1_5 + description: Stores the fifth 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA6 + description: Register $n of BLOCK2 (system). + addressOffset: 116 + size: 32 + fields: + - name: SYS_DATA_PART1_6 + description: Stores the sixth 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA7 + description: Register $n of BLOCK2 (system). + addressOffset: 120 + size: 32 + fields: + - name: SYS_DATA_PART1_7 + description: Stores the seventh 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA0 + description: Register $n of BLOCK3 (user). + addressOffset: 124 + size: 32 + fields: + - name: USR_DATA0 + description: Stores the zeroth 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA1 + description: Register $n of BLOCK3 (user). + addressOffset: 128 + size: 32 + fields: + - name: USR_DATA1 + description: Stores the first 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA2 + description: Register $n of BLOCK3 (user). + addressOffset: 132 + size: 32 + fields: + - name: USR_DATA2 + description: Stores the second 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA3 + description: Register $n of BLOCK3 (user). + addressOffset: 136 + size: 32 + fields: + - name: USR_DATA3 + description: Stores the third 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA4 + description: Register $n of BLOCK3 (user). + addressOffset: 140 + size: 32 + fields: + - name: USR_DATA4 + description: Stores the fourth 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA5 + description: Register $n of BLOCK3 (user). + addressOffset: 144 + size: 32 + fields: + - name: USR_DATA5 + description: Stores the fifth 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA6 + description: Register $n of BLOCK3 (user). + addressOffset: 148 + size: 32 + fields: + - name: USR_DATA6 + description: Stores the sixth 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA7 + description: Register $n of BLOCK3 (user). + addressOffset: 152 + size: 32 + fields: + - name: USR_DATA7 + description: Stores the seventh 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA0 + description: Register $n of BLOCK4 (KEY0). + addressOffset: 156 + size: 32 + fields: + - name: KEY0_DATA0 + description: Stores the zeroth 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA1 + description: Register $n of BLOCK4 (KEY0). + addressOffset: 160 + size: 32 + fields: + - name: KEY0_DATA1 + description: Stores the first 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA2 + description: Register $n of BLOCK4 (KEY0). + addressOffset: 164 + size: 32 + fields: + - name: KEY0_DATA2 + description: Stores the second 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA3 + description: Register $n of BLOCK4 (KEY0). + addressOffset: 168 + size: 32 + fields: + - name: KEY0_DATA3 + description: Stores the third 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA4 + description: Register $n of BLOCK4 (KEY0). + addressOffset: 172 + size: 32 + fields: + - name: KEY0_DATA4 + description: Stores the fourth 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA5 + description: Register $n of BLOCK4 (KEY0). + addressOffset: 176 + size: 32 + fields: + - name: KEY0_DATA5 + description: Stores the fifth 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA6 + description: Register $n of BLOCK4 (KEY0). + addressOffset: 180 + size: 32 + fields: + - name: KEY0_DATA6 + description: Stores the sixth 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA7 + description: Register $n of BLOCK4 (KEY0). + addressOffset: 184 + size: 32 + fields: + - name: KEY0_DATA7 + description: Stores the seventh 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA0 + description: Register $n of BLOCK5 (KEY1). + addressOffset: 188 + size: 32 + fields: + - name: KEY1_DATA0 + description: Stores the zeroth 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA1 + description: Register $n of BLOCK5 (KEY1). + addressOffset: 192 + size: 32 + fields: + - name: KEY1_DATA1 + description: Stores the first 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA2 + description: Register $n of BLOCK5 (KEY1). + addressOffset: 196 + size: 32 + fields: + - name: KEY1_DATA2 + description: Stores the second 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA3 + description: Register $n of BLOCK5 (KEY1). + addressOffset: 200 + size: 32 + fields: + - name: KEY1_DATA3 + description: Stores the third 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA4 + description: Register $n of BLOCK5 (KEY1). + addressOffset: 204 + size: 32 + fields: + - name: KEY1_DATA4 + description: Stores the fourth 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA5 + description: Register $n of BLOCK5 (KEY1). + addressOffset: 208 + size: 32 + fields: + - name: KEY1_DATA5 + description: Stores the fifth 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA6 + description: Register $n of BLOCK5 (KEY1). + addressOffset: 212 + size: 32 + fields: + - name: KEY1_DATA6 + description: Stores the sixth 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA7 + description: Register $n of BLOCK5 (KEY1). + addressOffset: 216 + size: 32 + fields: + - name: KEY1_DATA7 + description: Stores the seventh 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA0 + description: Register $n of BLOCK6 (KEY2). + addressOffset: 220 + size: 32 + fields: + - name: KEY2_DATA0 + description: Stores the zeroth 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA1 + description: Register $n of BLOCK6 (KEY2). + addressOffset: 224 + size: 32 + fields: + - name: KEY2_DATA1 + description: Stores the first 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA2 + description: Register $n of BLOCK6 (KEY2). + addressOffset: 228 + size: 32 + fields: + - name: KEY2_DATA2 + description: Stores the second 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA3 + description: Register $n of BLOCK6 (KEY2). + addressOffset: 232 + size: 32 + fields: + - name: KEY2_DATA3 + description: Stores the third 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA4 + description: Register $n of BLOCK6 (KEY2). + addressOffset: 236 + size: 32 + fields: + - name: KEY2_DATA4 + description: Stores the fourth 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA5 + description: Register $n of BLOCK6 (KEY2). + addressOffset: 240 + size: 32 + fields: + - name: KEY2_DATA5 + description: Stores the fifth 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA6 + description: Register $n of BLOCK6 (KEY2). + addressOffset: 244 + size: 32 + fields: + - name: KEY2_DATA6 + description: Stores the sixth 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA7 + description: Register $n of BLOCK6 (KEY2). + addressOffset: 248 + size: 32 + fields: + - name: KEY2_DATA7 + description: Stores the seventh 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA0 + description: Register $n of BLOCK7 (KEY3). + addressOffset: 252 + size: 32 + fields: + - name: KEY3_DATA0 + description: Stores the zeroth 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA1 + description: Register $n of BLOCK7 (KEY3). + addressOffset: 256 + size: 32 + fields: + - name: KEY3_DATA1 + description: Stores the first 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA2 + description: Register $n of BLOCK7 (KEY3). + addressOffset: 260 + size: 32 + fields: + - name: KEY3_DATA2 + description: Stores the second 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA3 + description: Register $n of BLOCK7 (KEY3). + addressOffset: 264 + size: 32 + fields: + - name: KEY3_DATA3 + description: Stores the third 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA4 + description: Register $n of BLOCK7 (KEY3). + addressOffset: 268 + size: 32 + fields: + - name: KEY3_DATA4 + description: Stores the fourth 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA5 + description: Register $n of BLOCK7 (KEY3). + addressOffset: 272 + size: 32 + fields: + - name: KEY3_DATA5 + description: Stores the fifth 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA6 + description: Register $n of BLOCK7 (KEY3). + addressOffset: 276 + size: 32 + fields: + - name: KEY3_DATA6 + description: Stores the sixth 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA7 + description: Register $n of BLOCK7 (KEY3). + addressOffset: 280 + size: 32 + fields: + - name: KEY3_DATA7 + description: Stores the seventh 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA0 + description: Register $n of BLOCK8 (KEY4). + addressOffset: 284 + size: 32 + fields: + - name: KEY4_DATA0 + description: Stores the zeroth 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA1 + description: Register $n of BLOCK8 (KEY4). + addressOffset: 288 + size: 32 + fields: + - name: KEY4_DATA1 + description: Stores the first 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA2 + description: Register $n of BLOCK8 (KEY4). + addressOffset: 292 + size: 32 + fields: + - name: KEY4_DATA2 + description: Stores the second 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA3 + description: Register $n of BLOCK8 (KEY4). + addressOffset: 296 + size: 32 + fields: + - name: KEY4_DATA3 + description: Stores the third 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA4 + description: Register $n of BLOCK8 (KEY4). + addressOffset: 300 + size: 32 + fields: + - name: KEY4_DATA4 + description: Stores the fourth 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA5 + description: Register $n of BLOCK8 (KEY4). + addressOffset: 304 + size: 32 + fields: + - name: KEY4_DATA5 + description: Stores the fifth 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA6 + description: Register $n of BLOCK8 (KEY4). + addressOffset: 308 + size: 32 + fields: + - name: KEY4_DATA6 + description: Stores the sixth 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA7 + description: Register $n of BLOCK8 (KEY4). + addressOffset: 312 + size: 32 + fields: + - name: KEY4_DATA7 + description: Stores the seventh 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA0 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 316 + size: 32 + fields: + - name: KEY5_DATA0 + description: Stores the zeroth 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA1 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 320 + size: 32 + fields: + - name: KEY5_DATA1 + description: Stores the first 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA2 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 324 + size: 32 + fields: + - name: KEY5_DATA2 + description: Stores the second 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA3 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 328 + size: 32 + fields: + - name: KEY5_DATA3 + description: Stores the third 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA4 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 332 + size: 32 + fields: + - name: KEY5_DATA4 + description: Stores the fourth 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA5 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 336 + size: 32 + fields: + - name: KEY5_DATA5 + description: Stores the fifth 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA6 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 340 + size: 32 + fields: + - name: KEY5_DATA6 + description: Stores the sixth 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA7 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 344 + size: 32 + fields: + - name: KEY5_DATA7 + description: Stores the seventh 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA0 + description: Register $n of BLOCK10 (system). + addressOffset: 348 + size: 32 + fields: + - name: SYS_DATA_PART2_0 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA1 + description: Register $n of BLOCK9 (KEY5). + addressOffset: 352 + size: 32 + fields: + - name: SYS_DATA_PART2_1 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA2 + description: Register $n of BLOCK10 (system). + addressOffset: 356 + size: 32 + fields: + - name: SYS_DATA_PART2_2 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA3 + description: Register $n of BLOCK10 (system). + addressOffset: 360 + size: 32 + fields: + - name: SYS_DATA_PART2_3 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA4 + description: Register $n of BLOCK10 (system). + addressOffset: 364 + size: 32 + fields: + - name: SYS_DATA_PART2_4 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA5 + description: Register $n of BLOCK10 (system). + addressOffset: 368 + size: 32 + fields: + - name: SYS_DATA_PART2_5 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA6 + description: Register $n of BLOCK10 (system). + addressOffset: 372 + size: 32 + fields: + - name: SYS_DATA_PART2_6 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA7 + description: Register $n of BLOCK10 (system). + addressOffset: 376 + size: 32 + fields: + - name: SYS_DATA_PART2_7 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_REPEAT_ERR0 + description: Programming error record register 0 of BLOCK0. + addressOffset: 380 + size: 32 + fields: + - name: RD_DIS_ERR + description: Indicates a programming error of RD_DIS. + bitOffset: 0 + bitWidth: 7 + access: read-only + - name: DIS_USB_DEVICE_EXCHG_PINS_ERR + description: Indicates a programming error of DIS_USB_DEVICE_EXCHG_PINS. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DIS_USB_OTG11_EXCHG_PINS_ERR + description: Indicates a programming error of DIS_USB_OTG11_EXCHG_PINS. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DIS_USB_JTAG_ERR + description: Indicates a programming error of DIS_USB_JTAG. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: POWERGLITCH_EN_ERR + description: Indicates a programming error of POWERGLITCH_EN. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: DIS_USB_SERIAL_JTAG_ERR + description: Indicates a programming error of DIS_USB_SERIAL_JTAG. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: DIS_FORCE_DOWNLOAD_ERR + description: Indicates a programming error of DIS_FORCE_DOWNLOAD. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SPI_DOWNLOAD_MSPI_DIS_ERR + description: Indicates a programming error of SPI_DOWNLOAD_MSPI_DIS. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: DIS_TWAI_ERR + description: Indicates a programming error of DIS_TWAI. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: JTAG_SEL_ENABLE_ERR + description: Indicates a programming error of JTAG_SEL_ENABLE. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SOFT_DIS_JTAG_ERR + description: Indicates a programming error of SOFT_DIS_JTAG. + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: DIS_PAD_JTAG_ERR + description: Indicates a programming error of DIS_PAD_JTAG. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR + description: Indicates a programming error of DIS_DOWNLOAD_MANUAL_ENCRYPT. + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: USB_DEVICE_DREFH_ERR + description: Indicates a programming error of USB_DEVICE_DREFH. + bitOffset: 21 + bitWidth: 2 + access: read-only + - name: USB_OTG11_DREFH_ERR + description: Indicates a programming error of USB_OTG11_DREFH. + bitOffset: 23 + bitWidth: 2 + access: read-only + - name: USB_PHY_SEL_ERR + description: Indicates a programming error of USB_PHY_SEL. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: HUK_GEN_STATE_LOW_ERR + description: Indicates a programming error of HUK_GEN_STATE_LOW. + bitOffset: 26 + bitWidth: 6 + access: read-only + - register: + name: RD_REPEAT_ERR1 + description: Programming error record register 1 of BLOCK0. + addressOffset: 384 + size: 32 + fields: + - name: KM_HUK_GEN_STATE_HIGH_ERR + description: Indicates a programming error of HUK_GEN_STATE_HIGH. + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: KM_RND_SWITCH_CYCLE_ERR + description: Indicates a programming error of KM_RND_SWITCH_CYCLE. + bitOffset: 3 + bitWidth: 2 + access: read-only + - name: KM_DEPLOY_ONLY_ONCE_ERR + description: Indicates a programming error of KM_DEPLOY_ONLY_ONCE. + bitOffset: 5 + bitWidth: 4 + access: read-only + - name: FORCE_USE_KEY_MANAGER_KEY_ERR + description: Indicates a programming error of FORCE_USE_KEY_MANAGER_KEY. + bitOffset: 9 + bitWidth: 4 + access: read-only + - name: FORCE_DISABLE_SW_INIT_KEY_ERR + description: Indicates a programming error of FORCE_DISABLE_SW_INIT_KEY. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: XTS_KEY_LENGTH_256_ERR + description: Indicates a programming error of XTS_KEY_LENGTH_256. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: WDT_DELAY_SEL_ERR + description: Indicates a programming error of WDT_DELAY_SEL. + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: SPI_BOOT_CRYPT_CNT_ERR + description: Indicates a programming error of SPI_BOOT_CRYPT_CNT. + bitOffset: 18 + bitWidth: 3 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE0_ERR + description: Indicates a programming error of SECURE_BOOT_KEY_REVOKE0. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE1_ERR + description: Indicates a programming error of SECURE_BOOT_KEY_REVOKE1. + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE2_ERR + description: Indicates a programming error of SECURE_BOOT_KEY_REVOKE2. + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: KEY_PURPOSE_0_ERR + description: Indicates a programming error of KEY_PURPOSE_0. + bitOffset: 24 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_1_ERR + description: Indicates a programming error of KEY_PURPOSE_1. + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_REPEAT_ERR2 + description: Programming error record register 2 of BLOCK0. + addressOffset: 388 + size: 32 + fields: + - name: KEY_PURPOSE_2_ERR + description: Indicates a programming error of KEY_PURPOSE_2. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_3_ERR + description: Indicates a programming error of KEY_PURPOSE_3. + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_4_ERR + description: Indicates a programming error of KEY_PURPOSE_4. + bitOffset: 8 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_5_ERR + description: Indicates a programming error of KEY_PURPOSE_5. + bitOffset: 12 + bitWidth: 4 + access: read-only + - name: SEC_DPA_LEVEL_ERR + description: Indicates a programming error of SEC_DPA_LEVEL. + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: ECDSA_ENABLE_SOFT_K_ERR + description: Indicates a programming error of ECDSA_FORCE_USE_HARDWARE_K. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: CRYPT_DPA_ENABLE_ERR + description: Indicates a programming error of CRYPT_DPA_ENABLE. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_EN_ERR + description: Indicates a programming error of SECURE_BOOT_EN. + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_AGGRESSIVE_REVOKE_ERR + description: Indicates a programming error of SECURE_BOOT_AGGRESSIVE_REVOKE. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: FLASH_TYPE_ERR + description: Indicates a programming error of FLASH_TYPE. + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: FLASH_PAGE_SIZE_ERR + description: Indicates a programming error of FLASH_PAGE_SIZE. + bitOffset: 24 + bitWidth: 2 + access: read-only + - name: FLASH_ECC_EN_ERR + description: Indicates a programming error of FLASH_ECC_EN. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: DIS_USB_OTG_DOWNLOAD_MODE_ERR + description: Indicates a programming error of DIS_USB_OTG_DOWNLOAD_MODE. + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: FLASH_TPUW_ERR + description: Indicates a programming error of FLASH_TPUW. + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_REPEAT_ERR3 + description: Programming error record register 3 of BLOCK0. + addressOffset: 392 + size: 32 + fields: + - name: DIS_DOWNLOAD_MODE_ERR + description: Indicates a programming error of DIS_DOWNLOAD_MODE. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DIS_DIRECT_BOOT_ERR + description: Indicates a programming error of DIS_DIRECT_BOOT. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR + description: Indicates a programming error of DIS_USB_SERIAL_JTAG_ROM_PRINT_ERR. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: LOCK_KM_KEY_ERR + description: TBD + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR + description: Indicates a programming error of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ENABLE_SECURITY_DOWNLOAD_ERR + description: Indicates a programming error of ENABLE_SECURITY_DOWNLOAD. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: UART_PRINT_CONTROL_ERR + description: Indicates a programming error of UART_PRINT_CONTROL. + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: FORCE_SEND_RESUME_ERR + description: Indicates a programming error of FORCE_SEND_RESUME. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SECURE_VERSION_ERR + description: Indicates a programming error of SECURE VERSION. + bitOffset: 9 + bitWidth: 16 + access: read-only + - name: SECURE_BOOT_DISABLE_FAST_WAKE_ERR + description: Indicates a programming error of SECURE_BOOT_DISABLE_FAST_WAKE. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: HYS_EN_PAD_ERR + description: Indicates a programming error of HYS_EN_PAD. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: DCDC_VSET_ERR + description: Indicates a programming error of DCDC_VSET. + bitOffset: 27 + bitWidth: 5 + access: read-only + - register: + name: RD_REPEAT_ERR4 + description: Programming error record register 4 of BLOCK0. + addressOffset: 396 + size: 32 + fields: + - name: _0PXA_TIEH_SEL_0_ERR + description: Indicates a programming error of 0PXA_TIEH_SEL_0. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: _0PXA_TIEH_SEL_1_ERR + description: Indicates a programming error of 0PXA_TIEH_SEL_1. + bitOffset: 2 + bitWidth: 2 + access: read-only + - name: _0PXA_TIEH_SEL_2_ERR + description: Indicates a programming error of 0PXA_TIEH_SEL_2. + bitOffset: 4 + bitWidth: 2 + access: read-only + - name: _0PXA_TIEH_SEL_3_ERR + description: Indicates a programming error of 0PXA_TIEH_SEL_3. + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: KM_DISABLE_DEPLOY_MODE_ERR + description: TBD. + bitOffset: 8 + bitWidth: 4 + access: read-only + - name: USB_DEVICE_DREFL_ERR + description: Indicates a programming error of USB_DEVICE_DREFL. + bitOffset: 12 + bitWidth: 2 + access: read-only + - name: USB_OTG11_DREFL_ERR + description: Indicates a programming error of USB_OTG11_DREFL. + bitOffset: 14 + bitWidth: 2 + access: read-only + - name: HP_PWR_SRC_SEL_ERR + description: Indicates a programming error of HP_PWR_SRC_SEL. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: DCDC_VSET_EN_ERR + description: Indicates a programming error of DCDC_VSET_EN. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: DIS_WDT_ERR + description: Indicates a programming error of DIS_WDT. + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: DIS_SWD_ERR + description: Indicates a programming error of DIS_SWD. + bitOffset: 21 + bitWidth: 1 + access: read-only + - register: + name: RD_RS_ERR0 + description: Programming error record register 0 of BLOCK1-10. + addressOffset: 448 + size: 32 + fields: + - name: MAC_SYS_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: MAC_SYS_FAIL + description: "0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SYS_PART1_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 4 + bitWidth: 3 + access: read-only + - name: SYS_PART1_FAIL + description: "0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: USR_DATA_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 8 + bitWidth: 3 + access: read-only + - name: USR_DATA_FAIL + description: "0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: KEY0_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 12 + bitWidth: 3 + access: read-only + - name: KEY0_FAIL + description: "0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6." + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: KEY1_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: KEY1_FAIL + description: "0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6." + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: KEY2_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 20 + bitWidth: 3 + access: read-only + - name: KEY2_FAIL + description: "0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6." + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: KEY3_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 24 + bitWidth: 3 + access: read-only + - name: KEY3_FAIL + description: "0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6." + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: KEY4_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 28 + bitWidth: 3 + access: read-only + - name: KEY4_FAIL + description: "0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: RD_RS_ERR1 + description: Programming error record register 1 of BLOCK1-10. + addressOffset: 452 + size: 32 + fields: + - name: KEY5_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: KEY5_FAIL + description: "0: Means no failure and that the data of key5 is reliable 1: Means that programming key5 failed and the number of error bytes is over 6." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SYS_PART2_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 4 + bitWidth: 3 + access: read-only + - name: SYS_PART2_FAIL + description: "0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 7 + bitWidth: 1 + access: read-only + - register: + name: CLK + description: eFuse clcok configuration register. + addressOffset: 456 + size: 32 + fields: + - name: MEM_FORCE_PD + description: Set this bit to force eFuse SRAM into power-saving mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_CLK_FORCE_ON + description: Set this bit and force to activate clock signal of eFuse SRAM. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PU + description: Set this bit to force eFuse SRAM into working mode. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EN + description: Set this bit to force enable eFuse register configuration clock signal. + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: CONF + description: eFuse operation mode configuraiton register + addressOffset: 460 + size: 32 + fields: + - name: OP_CODE + description: "0x5A5A: programming operation command 0x5AA5: read operation command." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CFG_ECDSA_BLK + description: Configures which block to use for ECDSA key output. + bitOffset: 16 + bitWidth: 4 + access: read-write + - register: + name: STATUS + description: eFuse status register. + addressOffset: 464 + size: 32 + fields: + - name: STATE + description: Indicates the state of the eFuse state machine. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: OTP_LOAD_SW + description: The value of OTP_LOAD_SW. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: OTP_VDDQ_C_SYNC2 + description: The value of OTP_VDDQ_C_SYNC2. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OTP_STROBE_SW + description: The value of OTP_STROBE_SW. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OTP_CSB_SW + description: The value of OTP_CSB_SW. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OTP_PGENB_SW + description: The value of OTP_PGENB_SW. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: OTP_VDDQ_IS_SW + description: The value of OTP_VDDQ_IS_SW. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: BLK0_VALID_BIT_CNT + description: Indicates the number of block valid bit. + bitOffset: 10 + bitWidth: 10 + access: read-only + - name: CUR_ECDSA_BLK + description: Indicates which block is used for ECDSA key output. + bitOffset: 20 + bitWidth: 4 + access: read-only + - register: + name: CMD + description: eFuse command register. + addressOffset: 468 + size: 32 + fields: + - name: READ_CMD + description: Set this bit to send read command. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PGM_CMD + description: Set this bit to send programming command. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BLK_NUM + description: "The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively." + bitOffset: 2 + bitWidth: 4 + access: read-write + - register: + name: INT_RAW + description: eFuse raw interrupt register. + addressOffset: 472 + size: 32 + fields: + - name: READ_DONE_INT_RAW + description: The raw bit signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PGM_DONE_INT_RAW + description: The raw bit signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: eFuse interrupt status register. + addressOffset: 476 + size: 32 + fields: + - name: READ_DONE_INT_ST + description: The status signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PGM_DONE_INT_ST + description: The status signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: eFuse interrupt enable register. + addressOffset: 480 + size: 32 + fields: + - name: READ_DONE_INT_ENA + description: The enable signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PGM_DONE_INT_ENA + description: The enable signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: eFuse interrupt clear register. + addressOffset: 484 + size: 32 + fields: + - name: READ_DONE_INT_CLR + description: The clear signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: PGM_DONE_INT_CLR + description: The clear signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: DAC_CONF + description: Controls the eFuse programming voltage. + addressOffset: 488 + size: 32 + resetValue: 130583 + fields: + - name: DAC_CLK_DIV + description: Controls the division factor of the rising clock of the programming voltage. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: DAC_CLK_PAD_SEL + description: "Don't care." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DAC_NUM + description: Controls the rising period of the programming voltage. + bitOffset: 9 + bitWidth: 8 + access: read-write + - name: OE_CLR + description: Reduces the power supply of the programming voltage. + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: RD_TIM_CONF + description: Configures read timing parameters. + addressOffset: 492 + size: 32 + resetValue: 251724289 + fields: + - name: THR_A + description: Configures the read hold time. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TRD + description: Configures the read time. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: TSUR_A + description: Configures the read setup time. + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: READ_INIT_NUM + description: Configures the waiting time of reading eFuse memory. + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: WR_TIM_CONF1 + description: Configurarion register 1 of eFuse programming timing parameters. + addressOffset: 496 + size: 32 + resetValue: 19293953 + fields: + - name: TSUP_A + description: Configures the programming setup time. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: PWR_ON_NUM + description: Configures the power up time for VDDQ. + bitOffset: 8 + bitWidth: 16 + access: read-write + - name: THP_A + description: Configures the programming hold time. + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: WR_TIM_CONF2 + description: Configurarion register 2 of eFuse programming timing parameters. + addressOffset: 500 + size: 32 + resetValue: 10486080 + fields: + - name: PWR_OFF_NUM + description: Configures the power outage time for VDDQ. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: TPGM + description: Configures the active programming time. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: WR_TIM_CONF0_RS_BYPASS + description: Configurarion register0 of eFuse programming time parameters and rs bypass operation. + addressOffset: 504 + size: 32 + resetValue: 8192 + fields: + - name: BYPASS_RS_CORRECTION + description: Set this bit to bypass reed solomon correction step. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: BYPASS_RS_BLK_NUM + description: Configures block number of programming twice operation. + bitOffset: 1 + bitWidth: 11 + access: read-write + - name: UPDATE + description: Set this bit to update multi-bit register signals. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: TPGM_INACTIVE + description: Configures the inactive programming time. + bitOffset: 13 + bitWidth: 8 + access: read-write + - register: + name: DATE + description: eFuse version register. + addressOffset: 508 + size: 32 + resetValue: 36720720 + fields: + - name: DATE + description: Stores eFuse version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + name: APB2OTP_WR_DIS + description: eFuse apb2otp block0 data register1. + addressOffset: 2048 + size: 32 + fields: + - name: APB2OTP_BLOCK0_WR_DIS + description: Otp block0 write disable data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK0_BACKUP1_W1 + description: eFuse apb2otp block0 data register2. + addressOffset: 2052 + size: 32 + fields: + - name: APB2OTP_BLOCK0_BACKUP1_W1 + description: Otp block0 backup1 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK0_BACKUP1_W2 + description: eFuse apb2otp block0 data register3. + addressOffset: 2056 + size: 32 + fields: + - name: APB2OTP_BLOCK0_BACKUP1_W2 + description: Otp block0 backup1 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK0_BACKUP1_W3 + description: eFuse apb2otp block0 data register4. + addressOffset: 2060 + size: 32 + fields: + - name: APB2OTP_BLOCK0_BACKUP1_W3 + description: Otp block0 backup1 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK0_BACKUP1_W4 + description: eFuse apb2otp block0 data register5. + addressOffset: 2064 + size: 32 + fields: + - name: APB2OTP_BLOCK0_BACKUP1_W4 + description: Otp block0 backup1 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK0_BACKUP1_W5 + description: eFuse apb2otp block0 data register6. + addressOffset: 2068 + size: 32 + fields: + - name: APB2OTP_BLOCK0_BACKUP1_W5 + description: Otp block0 backup1 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK0_BACKUP2_W1 + description: eFuse apb2otp block0 data register7. + addressOffset: 2072 + size: 32 + fields: + - name: APB2OTP_BLOCK0_BACKUP2_W1 + description: Otp block0 backup2 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK0_BACKUP2_W2 + description: eFuse apb2otp block0 data register8. + addressOffset: 2076 + size: 32 + fields: + - name: APB2OTP_BLOCK0_BACKUP2_W2 + description: Otp block0 backup2 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK0_BACKUP2_W3 + description: eFuse apb2otp block0 data register9. + addressOffset: 2080 + size: 32 + fields: + - name: APB2OTP_BLOCK0_BACKUP2_W3 + description: Otp block0 backup2 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK0_BACKUP2_W4 + description: eFuse apb2otp block0 data register10. + addressOffset: 2084 + size: 32 + fields: + - name: APB2OTP_BLOCK0_BACKUP2_W4 + description: Otp block0 backup2 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK0_BACKUP2_W5 + description: eFuse apb2otp block0 data register11. + addressOffset: 2088 + size: 32 + fields: + - name: APB2OTP_BLOCK0_BACKUP2_W5 + description: Otp block0 backup2 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK0_BACKUP3_W1 + description: eFuse apb2otp block0 data register12. + addressOffset: 2092 + size: 32 + fields: + - name: APB2OTP_BLOCK0_BACKUP3_W1 + description: Otp block0 backup3 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK0_BACKUP3_W2 + description: eFuse apb2otp block0 data register13. + addressOffset: 2096 + size: 32 + fields: + - name: APB2OTP_BLOCK0_BACKUP3_W2 + description: Otp block0 backup3 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK0_BACKUP3_W3 + description: eFuse apb2otp block0 data register14. + addressOffset: 2100 + size: 32 + fields: + - name: APB2OTP_BLOCK0_BACKUP3_W3 + description: Otp block0 backup3 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK0_BACKUP3_W4 + description: eFuse apb2otp block0 data register15. + addressOffset: 2104 + size: 32 + fields: + - name: APB2OTP_BLOCK0_BACKUP3_W4 + description: Otp block0 backup3 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK0_BACKUP3_W5 + description: eFuse apb2otp block0 data register16. + addressOffset: 2108 + size: 32 + fields: + - name: APB2OTP_BLOCK0_BACKUP3_W5 + description: Otp block0 backup3 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK0_BACKUP4_W1 + description: eFuse apb2otp block0 data register17. + addressOffset: 2112 + size: 32 + fields: + - name: APB2OTP_BLOCK0_BACKUP4_W1 + description: Otp block0 backup4 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK0_BACKUP4_W2 + description: eFuse apb2otp block0 data register18. + addressOffset: 2116 + size: 32 + fields: + - name: APB2OTP_BLOCK0_BACKUP4_W2 + description: Otp block0 backup4 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK0_BACKUP4_W3 + description: eFuse apb2otp block0 data register19. + addressOffset: 2120 + size: 32 + fields: + - name: APB2OTP_BLOCK0_BACKUP4_W3 + description: Otp block0 backup4 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK0_BACKUP4_W4 + description: eFuse apb2otp block0 data register20. + addressOffset: 2124 + size: 32 + fields: + - name: APB2OTP_BLOCK0_BACKUP4_W4 + description: Otp block0 backup4 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK0_BACKUP4_W5 + description: eFuse apb2otp block0 data register21. + addressOffset: 2128 + size: 32 + fields: + - name: APB2OTP_BLOCK0_BACKUP4_W5 + description: Otp block0 backup4 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK1_W1 + description: eFuse apb2otp block1 data register1. + addressOffset: 2132 + size: 32 + fields: + - name: APB2OTP_BLOCK1_W1 + description: Otp block1 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK1_W2 + description: eFuse apb2otp block1 data register2. + addressOffset: 2136 + size: 32 + fields: + - name: APB2OTP_BLOCK1_W2 + description: Otp block1 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK1_W3 + description: eFuse apb2otp block1 data register3. + addressOffset: 2140 + size: 32 + fields: + - name: APB2OTP_BLOCK1_W3 + description: Otp block1 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK1_W4 + description: eFuse apb2otp block1 data register4. + addressOffset: 2144 + size: 32 + fields: + - name: APB2OTP_BLOCK1_W4 + description: Otp block1 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK1_W5 + description: eFuse apb2otp block1 data register5. + addressOffset: 2148 + size: 32 + fields: + - name: APB2OTP_BLOCK1_W5 + description: Otp block1 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK1_W6 + description: eFuse apb2otp block1 data register6. + addressOffset: 2152 + size: 32 + fields: + - name: APB2OTP_BLOCK1_W6 + description: Otp block1 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK1_W7 + description: eFuse apb2otp block1 data register7. + addressOffset: 2156 + size: 32 + fields: + - name: APB2OTP_BLOCK1_W7 + description: Otp block1 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK1_W8 + description: eFuse apb2otp block1 data register8. + addressOffset: 2160 + size: 32 + fields: + - name: APB2OTP_BLOCK1_W8 + description: Otp block1 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK1_W9 + description: eFuse apb2otp block1 data register9. + addressOffset: 2164 + size: 32 + fields: + - name: APB2OTP_BLOCK1_W9 + description: Otp block1 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK2_W1 + description: eFuse apb2otp block2 data register1. + addressOffset: 2168 + size: 32 + fields: + - name: APB2OTP_BLOCK2_W1 + description: Otp block2 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK2_W2 + description: eFuse apb2otp block2 data register2. + addressOffset: 2172 + size: 32 + fields: + - name: APB2OTP_BLOCK2_W2 + description: Otp block2 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK2_W3 + description: eFuse apb2otp block2 data register3. + addressOffset: 2176 + size: 32 + fields: + - name: APB2OTP_BLOCK2_W3 + description: Otp block2 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK2_W4 + description: eFuse apb2otp block2 data register4. + addressOffset: 2180 + size: 32 + fields: + - name: APB2OTP_BLOCK2_W4 + description: Otp block2 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK2_W5 + description: eFuse apb2otp block2 data register5. + addressOffset: 2184 + size: 32 + fields: + - name: APB2OTP_BLOCK2_W5 + description: Otp block2 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK2_W6 + description: eFuse apb2otp block2 data register6. + addressOffset: 2188 + size: 32 + fields: + - name: APB2OTP_BLOCK2_W6 + description: Otp block2 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK2_W7 + description: eFuse apb2otp block2 data register7. + addressOffset: 2192 + size: 32 + fields: + - name: APB2OTP_BLOCK2_W7 + description: Otp block2 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK2_W8 + description: eFuse apb2otp block2 data register8. + addressOffset: 2196 + size: 32 + fields: + - name: APB2OTP_BLOCK2_W8 + description: Otp block2 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK2_W9 + description: eFuse apb2otp block2 data register9. + addressOffset: 2200 + size: 32 + fields: + - name: APB2OTP_BLOCK2_W9 + description: Otp block2 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK2_W10 + description: eFuse apb2otp block2 data register10. + addressOffset: 2204 + size: 32 + fields: + - name: APB2OTP_BLOCK2_W10 + description: Otp block2 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK2_W11 + description: eFuse apb2otp block2 data register11. + addressOffset: 2208 + size: 32 + fields: + - name: APB2OTP_BLOCK2_W11 + description: Otp block2 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK3_W1 + description: eFuse apb2otp block3 data register1. + addressOffset: 2212 + size: 32 + fields: + - name: APB2OTP_BLOCK3_W1 + description: Otp block3 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK3_W2 + description: eFuse apb2otp block3 data register2. + addressOffset: 2216 + size: 32 + fields: + - name: APB2OTP_BLOCK3_W2 + description: Otp block3 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK3_W3 + description: eFuse apb2otp block3 data register3. + addressOffset: 2220 + size: 32 + fields: + - name: APB2OTP_BLOCK3_W3 + description: Otp block3 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK3_W4 + description: eFuse apb2otp block3 data register4. + addressOffset: 2224 + size: 32 + fields: + - name: APB2OTP_BLOCK3_W4 + description: Otp block3 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK3_W5 + description: eFuse apb2otp block3 data register5. + addressOffset: 2228 + size: 32 + fields: + - name: APB2OTP_BLOCK3_W5 + description: Otp block3 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK3_W6 + description: eFuse apb2otp block3 data register6. + addressOffset: 2232 + size: 32 + fields: + - name: APB2OTP_BLOCK3_W6 + description: Otp block3 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK3_W7 + description: eFuse apb2otp block3 data register7. + addressOffset: 2236 + size: 32 + fields: + - name: APB2OTP_BLOCK3_W7 + description: Otp block3 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK3_W8 + description: eFuse apb2otp block3 data register8. + addressOffset: 2240 + size: 32 + fields: + - name: APB2OTP_BLOCK3_W8 + description: Otp block3 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK3_W9 + description: eFuse apb2otp block3 data register9. + addressOffset: 2244 + size: 32 + fields: + - name: APB2OTP_BLOCK3_W9 + description: Otp block3 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK3_W10 + description: eFuse apb2otp block3 data register10. + addressOffset: 2248 + size: 32 + fields: + - name: APB2OTP_BLOCK3_W10 + description: Otp block3 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK3_W11 + description: eFuse apb2otp block3 data register11. + addressOffset: 2252 + size: 32 + fields: + - name: APB2OTP_BLOCK3_W11 + description: Otp block3 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK4_W1 + description: eFuse apb2otp block4 data register1. + addressOffset: 2256 + size: 32 + fields: + - name: APB2OTP_BLOCK4_W1 + description: Otp block4 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK4_W2 + description: eFuse apb2otp block4 data register2. + addressOffset: 2260 + size: 32 + fields: + - name: APB2OTP_BLOCK4_W2 + description: Otp block4 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK4_W3 + description: eFuse apb2otp block4 data register3. + addressOffset: 2264 + size: 32 + fields: + - name: APB2OTP_BLOCK4_W3 + description: Otp block4 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK4_W4 + description: eFuse apb2otp block4 data register4. + addressOffset: 2268 + size: 32 + fields: + - name: APB2OTP_BLOCK4_W4 + description: Otp block4 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK4_W5 + description: eFuse apb2otp block4 data register5. + addressOffset: 2272 + size: 32 + fields: + - name: APB2OTP_BLOCK4_W5 + description: Otp block4 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK4_W6 + description: eFuse apb2otp block4 data register6. + addressOffset: 2276 + size: 32 + fields: + - name: APB2OTP_BLOCK4_W6 + description: Otp block4 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK4_W7 + description: eFuse apb2otp block4 data register7. + addressOffset: 2280 + size: 32 + fields: + - name: APB2OTP_BLOCK4_W7 + description: Otp block4 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK4_W8 + description: eFuse apb2otp block4 data register8. + addressOffset: 2284 + size: 32 + fields: + - name: APB2OTP_BLOCK4_W8 + description: Otp block4 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK4_W9 + description: eFuse apb2otp block4 data register9. + addressOffset: 2288 + size: 32 + fields: + - name: APB2OTP_BLOCK4_W9 + description: Otp block4 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK4_W10 + description: eFuse apb2otp block4 data registe10. + addressOffset: 2292 + size: 32 + fields: + - name: APB2OTP_BLOCK4_W10 + description: Otp block4 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK4_W11 + description: eFuse apb2otp block4 data register11. + addressOffset: 2296 + size: 32 + fields: + - name: APB2OTP_BLOCK4_W11 + description: Otp block4 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK5_W1 + description: eFuse apb2otp block5 data register1. + addressOffset: 2300 + size: 32 + fields: + - name: APB2OTP_BLOCK5_W1 + description: Otp block5 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK5_W2 + description: eFuse apb2otp block5 data register2. + addressOffset: 2304 + size: 32 + fields: + - name: APB2OTP_BLOCK5_W2 + description: Otp block5 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK5_W3 + description: eFuse apb2otp block5 data register3. + addressOffset: 2308 + size: 32 + fields: + - name: APB2OTP_BLOCK5_W3 + description: Otp block5 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK5_W4 + description: eFuse apb2otp block5 data register4. + addressOffset: 2312 + size: 32 + fields: + - name: APB2OTP_BLOCK5_W4 + description: Otp block5 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK5_W5 + description: eFuse apb2otp block5 data register5. + addressOffset: 2316 + size: 32 + fields: + - name: APB2OTP_BLOCK5_W5 + description: Otp block5 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK5_W6 + description: eFuse apb2otp block5 data register6. + addressOffset: 2320 + size: 32 + fields: + - name: APB2OTP_BLOCK5_W6 + description: Otp block5 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK5_W7 + description: eFuse apb2otp block5 data register7. + addressOffset: 2324 + size: 32 + fields: + - name: APB2OTP_BLOCK5_W7 + description: Otp block5 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK5_W8 + description: eFuse apb2otp block5 data register8. + addressOffset: 2328 + size: 32 + fields: + - name: APB2OTP_BLOCK5_W8 + description: Otp block5 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK5_W9 + description: eFuse apb2otp block5 data register9. + addressOffset: 2332 + size: 32 + fields: + - name: APB2OTP_BLOCK5_W9 + description: Otp block5 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK5_W10 + description: eFuse apb2otp block5 data register10. + addressOffset: 2336 + size: 32 + fields: + - name: APB2OTP_BLOCK5_W10 + description: Otp block5 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK5_W11 + description: eFuse apb2otp block5 data register11. + addressOffset: 2340 + size: 32 + fields: + - name: APB2OTP_BLOCK5_W11 + description: Otp block5 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK6_W1 + description: eFuse apb2otp block6 data register1. + addressOffset: 2344 + size: 32 + fields: + - name: APB2OTP_BLOCK6_W1 + description: Otp block6 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK6_W2 + description: eFuse apb2otp block6 data register2. + addressOffset: 2348 + size: 32 + fields: + - name: APB2OTP_BLOCK6_W2 + description: Otp block6 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK6_W3 + description: eFuse apb2otp block6 data register3. + addressOffset: 2352 + size: 32 + fields: + - name: APB2OTP_BLOCK6_W3 + description: Otp block6 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK6_W4 + description: eFuse apb2otp block6 data register4. + addressOffset: 2356 + size: 32 + fields: + - name: APB2OTP_BLOCK6_W4 + description: Otp block6 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK6_W5 + description: eFuse apb2otp block6 data register5. + addressOffset: 2360 + size: 32 + fields: + - name: APB2OTP_BLOCK6_W5 + description: Otp block6 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK6_W6 + description: eFuse apb2otp block6 data register6. + addressOffset: 2364 + size: 32 + fields: + - name: APB2OTP_BLOCK6_W6 + description: Otp block6 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK6_W7 + description: eFuse apb2otp block6 data register7. + addressOffset: 2368 + size: 32 + fields: + - name: APB2OTP_BLOCK6_W7 + description: Otp block6 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK6_W8 + description: eFuse apb2otp block6 data register8. + addressOffset: 2372 + size: 32 + fields: + - name: APB2OTP_BLOCK6_W8 + description: Otp block6 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK6_W9 + description: eFuse apb2otp block6 data register9. + addressOffset: 2376 + size: 32 + fields: + - name: APB2OTP_BLOCK6_W9 + description: Otp block6 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK6_W10 + description: eFuse apb2otp block6 data register10. + addressOffset: 2380 + size: 32 + fields: + - name: APB2OTP_BLOCK6_W10 + description: Otp block6 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK6_W11 + description: eFuse apb2otp block6 data register11. + addressOffset: 2384 + size: 32 + fields: + - name: APB2OTP_BLOCK6_W11 + description: Otp block6 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK7_W1 + description: eFuse apb2otp block7 data register1. + addressOffset: 2388 + size: 32 + fields: + - name: APB2OTP_BLOCK7_W1 + description: Otp block7 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK7_W2 + description: eFuse apb2otp block7 data register2. + addressOffset: 2392 + size: 32 + fields: + - name: APB2OTP_BLOCK7_W2 + description: Otp block7 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK7_W3 + description: eFuse apb2otp block7 data register3. + addressOffset: 2396 + size: 32 + fields: + - name: APB2OTP_BLOCK7_W3 + description: Otp block7 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK7_W4 + description: eFuse apb2otp block7 data register4. + addressOffset: 2400 + size: 32 + fields: + - name: APB2OTP_BLOCK7_W4 + description: Otp block7 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK7_W5 + description: eFuse apb2otp block7 data register5. + addressOffset: 2404 + size: 32 + fields: + - name: APB2OTP_BLOCK7_W5 + description: Otp block7 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK7_W6 + description: eFuse apb2otp block7 data register6. + addressOffset: 2408 + size: 32 + fields: + - name: APB2OTP_BLOCK7_W6 + description: Otp block7 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK7_W7 + description: eFuse apb2otp block7 data register7. + addressOffset: 2412 + size: 32 + fields: + - name: APB2OTP_BLOCK7_W7 + description: Otp block7 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK7_W8 + description: eFuse apb2otp block7 data register8. + addressOffset: 2416 + size: 32 + fields: + - name: APB2OTP_BLOCK7_W8 + description: Otp block7 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK7_W9 + description: eFuse apb2otp block7 data register9. + addressOffset: 2420 + size: 32 + fields: + - name: APB2OTP_BLOCK7_W9 + description: Otp block7 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK7_W10 + description: eFuse apb2otp block7 data register10. + addressOffset: 2424 + size: 32 + fields: + - name: APB2OTP_BLOCK7_W10 + description: Otp block7 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK7_W11 + description: eFuse apb2otp block7 data register11. + addressOffset: 2428 + size: 32 + fields: + - name: APB2OTP_BLOCK7_W11 + description: Otp block7 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK8_W1 + description: eFuse apb2otp block8 data register1. + addressOffset: 2432 + size: 32 + fields: + - name: APB2OTP_BLOCK8_W1 + description: Otp block8 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK8_W2 + description: eFuse apb2otp block8 data register2. + addressOffset: 2436 + size: 32 + fields: + - name: APB2OTP_BLOCK8_W2 + description: Otp block8 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK8_W3 + description: eFuse apb2otp block8 data register3. + addressOffset: 2440 + size: 32 + fields: + - name: APB2OTP_BLOCK8_W3 + description: Otp block8 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK8_W4 + description: eFuse apb2otp block8 data register4. + addressOffset: 2444 + size: 32 + fields: + - name: APB2OTP_BLOCK8_W4 + description: Otp block8 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK8_W5 + description: eFuse apb2otp block8 data register5. + addressOffset: 2448 + size: 32 + fields: + - name: APB2OTP_BLOCK8_W5 + description: Otp block8 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK8_W6 + description: eFuse apb2otp block8 data register6. + addressOffset: 2452 + size: 32 + fields: + - name: APB2OTP_BLOCK8_W6 + description: Otp block8 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK8_W7 + description: eFuse apb2otp block8 data register7. + addressOffset: 2456 + size: 32 + fields: + - name: APB2OTP_BLOCK8_W7 + description: Otp block8 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK8_W8 + description: eFuse apb2otp block8 data register8. + addressOffset: 2460 + size: 32 + fields: + - name: APB2OTP_BLOCK8_W8 + description: Otp block8 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK8_W9 + description: eFuse apb2otp block8 data register9. + addressOffset: 2464 + size: 32 + fields: + - name: APB2OTP_BLOCK8_W9 + description: Otp block8 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK8_W10 + description: eFuse apb2otp block8 data register10. + addressOffset: 2468 + size: 32 + fields: + - name: APB2OTP_BLOCK8_W10 + description: Otp block8 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK8_W11 + description: eFuse apb2otp block8 data register11. + addressOffset: 2472 + size: 32 + fields: + - name: APB2OTP_BLOCK8_W11 + description: Otp block8 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK9_W1 + description: eFuse apb2otp block9 data register1. + addressOffset: 2476 + size: 32 + fields: + - name: APB2OTP_BLOCK9_W1 + description: Otp block9 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK9_W2 + description: eFuse apb2otp block9 data register2. + addressOffset: 2480 + size: 32 + fields: + - name: APB2OTP_BLOCK9_W2 + description: Otp block9 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK9_W3 + description: eFuse apb2otp block9 data register3. + addressOffset: 2484 + size: 32 + fields: + - name: APB2OTP_BLOCK9_W3 + description: Otp block9 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK9_W4 + description: eFuse apb2otp block9 data register4. + addressOffset: 2488 + size: 32 + fields: + - name: APB2OTP_BLOCK9_W4 + description: Otp block9 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK9_W5 + description: eFuse apb2otp block9 data register5. + addressOffset: 2492 + size: 32 + fields: + - name: APB2OTP_BLOCK9_W5 + description: Otp block9 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK9_W6 + description: eFuse apb2otp block9 data register6. + addressOffset: 2496 + size: 32 + fields: + - name: APB2OTP_BLOCK9_W6 + description: Otp block9 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK9_W7 + description: eFuse apb2otp block9 data register7. + addressOffset: 2500 + size: 32 + fields: + - name: APB2OTP_BLOCK9_W7 + description: Otp block9 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK9_W8 + description: eFuse apb2otp block9 data register8. + addressOffset: 2504 + size: 32 + fields: + - name: APB2OTP_BLOCK9_W8 + description: Otp block9 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK9_W9 + description: eFuse apb2otp block9 data register9. + addressOffset: 2508 + size: 32 + fields: + - name: APB2OTP_BLOCK9_W9 + description: Otp block9 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK9_W10 + description: eFuse apb2otp block9 data register10. + addressOffset: 2512 + size: 32 + fields: + - name: APB2OTP_BLOCK9_W10 + description: Otp block9 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK9_W11 + description: eFuse apb2otp block9 data register11. + addressOffset: 2516 + size: 32 + fields: + - name: APB2OTP_BLOCK9_W11 + description: Otp block9 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK10_W1 + description: eFuse apb2otp block10 data register1. + addressOffset: 2520 + size: 32 + fields: + - name: APB2OTP_BLOCK10_W1 + description: Otp block10 word1 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK10_W2 + description: eFuse apb2otp block10 data register2. + addressOffset: 2524 + size: 32 + fields: + - name: APB2OTP_BLOCK10_W2 + description: Otp block10 word2 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK10_W3 + description: eFuse apb2otp block10 data register3. + addressOffset: 2528 + size: 32 + fields: + - name: APB2OTP_BLOCK10_W3 + description: Otp block10 word3 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK10_W4 + description: eFuse apb2otp block10 data register4. + addressOffset: 2532 + size: 32 + fields: + - name: APB2OTP_BLOCK10_W4 + description: Otp block10 word4 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK10_W5 + description: eFuse apb2otp block10 data register5. + addressOffset: 2536 + size: 32 + fields: + - name: APB2OTP_BLOCK10_W5 + description: Otp block10 word5 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK10_W6 + description: eFuse apb2otp block10 data register6. + addressOffset: 2540 + size: 32 + fields: + - name: APB2OTP_BLOCK10_W6 + description: Otp block10 word6 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK10_W7 + description: eFuse apb2otp block10 data register7. + addressOffset: 2544 + size: 32 + fields: + - name: APB2OTP_BLOCK10_W7 + description: Otp block10 word7 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK10_W8 + description: eFuse apb2otp block10 data register8. + addressOffset: 2548 + size: 32 + fields: + - name: APB2OTP_BLOCK10_W8 + description: Otp block10 word8 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK10_W9 + description: eFuse apb2otp block10 data register9. + addressOffset: 2552 + size: 32 + fields: + - name: APB2OTP_BLOCK10_W9 + description: Otp block10 word9 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK10_W10 + description: eFuse apb2otp block10 data register10. + addressOffset: 2556 + size: 32 + fields: + - name: APB2OTP_BLOCK19_W10 + description: Otp block10 word10 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_BLK10_W11 + description: eFuse apb2otp block10 data register11. + addressOffset: 2560 + size: 32 + fields: + - name: APB2OTP_BLOCK10_W11 + description: Otp block10 word11 data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APB2OTP_EN + description: eFuse apb2otp enable configuration register. + addressOffset: 2568 + size: 32 + fields: + - name: APB2OTP_APB2OTP_EN + description: Apb2otp mode enable signal. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: GPIO + description: General Purpose Input/Output + groupName: GPIO + baseAddress: 1343094784 + addressBlock: + - offset: 0 + size: 1528 + usage: registers + interrupt: + - name: GPIO + value: 74 + - name: GPIO_INT1 + value: 75 + - name: GPIO_INT2 + value: 76 + - name: GPIO_INT3 + value: 77 + - name: GPIO_PAD_COMP + value: 78 + registers: + - register: + name: BT_SELECT + description: GPIO bit select register + addressOffset: 0 + size: 32 + fields: + - name: BT_SEL + description: GPIO bit select register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: OUT + description: GPIO output register for GPIO0-31 + addressOffset: 4 + size: 32 + fields: + - name: DATA_ORIG + description: GPIO output register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: OUT_W1TS + description: GPIO output set register for GPIO0-31 + addressOffset: 8 + size: 32 + fields: + - name: OUT_W1TS + description: GPIO output set register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: OUT_W1TC + description: GPIO output clear register for GPIO0-31 + addressOffset: 12 + size: 32 + fields: + - name: OUT_W1TC + description: GPIO output clear register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: OUT1 + description: GPIO output register for GPIO32-56 + addressOffset: 16 + size: 32 + fields: + - name: DATA_ORIG + description: GPIO output register for GPIO32-56 + bitOffset: 0 + bitWidth: 25 + access: read-write + - register: + name: OUT1_W1TS + description: GPIO output set register for GPIO32-56 + addressOffset: 20 + size: 32 + fields: + - name: OUT1_W1TS + description: GPIO output set register for GPIO32-56 + bitOffset: 0 + bitWidth: 25 + access: write-only + - register: + name: OUT1_W1TC + description: GPIO output clear register for GPIO32-56 + addressOffset: 24 + size: 32 + fields: + - name: OUT1_W1TC + description: GPIO output clear register for GPIO32-56 + bitOffset: 0 + bitWidth: 25 + access: write-only + - register: + name: ENABLE + description: GPIO output enable register for GPIO0-31 + addressOffset: 32 + size: 32 + fields: + - name: DATA + description: GPIO output enable register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ENABLE_W1TS + description: GPIO output enable set register for GPIO0-31 + addressOffset: 36 + size: 32 + fields: + - name: ENABLE_W1TS + description: GPIO output enable set register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: ENABLE_W1TC + description: GPIO output enable clear register for GPIO0-31 + addressOffset: 40 + size: 32 + fields: + - name: ENABLE_W1TC + description: GPIO output enable clear register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: ENABLE1 + description: GPIO output enable register for GPIO32-56 + addressOffset: 44 + size: 32 + fields: + - name: DATA + description: GPIO output enable register for GPIO32-56 + bitOffset: 0 + bitWidth: 25 + access: read-write + - register: + name: ENABLE1_W1TS + description: GPIO output enable set register for GPIO32-56 + addressOffset: 48 + size: 32 + fields: + - name: ENABLE1_W1TS + description: GPIO output enable set register for GPIO32-56 + bitOffset: 0 + bitWidth: 25 + access: write-only + - register: + name: ENABLE1_W1TC + description: GPIO output enable clear register for GPIO32-56 + addressOffset: 52 + size: 32 + fields: + - name: ENABLE1_W1TC + description: GPIO output enable clear register for GPIO32-56 + bitOffset: 0 + bitWidth: 25 + access: write-only + - register: + name: STRAP + description: pad strapping register + addressOffset: 56 + size: 32 + fields: + - name: STRAPPING + description: pad strapping register + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: IN + description: GPIO input register for GPIO0-31 + addressOffset: 60 + size: 32 + fields: + - name: DATA_NEXT + description: GPIO input register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN1 + description: GPIO input register for GPIO32-56 + addressOffset: 64 + size: 32 + fields: + - name: DATA_NEXT + description: GPIO input register for GPIO32-56 + bitOffset: 0 + bitWidth: 25 + access: read-only + - register: + name: STATUS + description: GPIO interrupt status register for GPIO0-31 + addressOffset: 68 + size: 32 + fields: + - name: INTERRUPT + description: GPIO interrupt status register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STATUS_W1TS + description: GPIO interrupt status set register for GPIO0-31 + addressOffset: 72 + size: 32 + fields: + - name: STATUS_W1TS + description: GPIO interrupt status set register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: STATUS_W1TC + description: GPIO interrupt status clear register for GPIO0-31 + addressOffset: 76 + size: 32 + fields: + - name: STATUS_W1TC + description: GPIO interrupt status clear register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: STATUS1 + description: GPIO interrupt status register for GPIO32-56 + addressOffset: 80 + size: 32 + fields: + - name: INTERRUPT + description: GPIO interrupt status register for GPIO32-56 + bitOffset: 0 + bitWidth: 25 + access: read-write + - register: + name: STATUS1_W1TS + description: GPIO interrupt status set register for GPIO32-56 + addressOffset: 84 + size: 32 + fields: + - name: STATUS1_W1TS + description: GPIO interrupt status set register for GPIO32-56 + bitOffset: 0 + bitWidth: 25 + access: write-only + - register: + name: STATUS1_W1TC + description: GPIO interrupt status clear register for GPIO32-56 + addressOffset: 88 + size: 32 + fields: + - name: STATUS1_W1TC + description: GPIO interrupt status clear register for GPIO32-56 + bitOffset: 0 + bitWidth: 25 + access: write-only + - register: + name: INTR_0 + description: GPIO interrupt 0 status register for GPIO0-31 + addressOffset: 92 + size: 32 + fields: + - name: INT_0 + description: GPIO interrupt 0 status register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INTR1_0 + description: GPIO interrupt 0 status register for GPIO32-56 + addressOffset: 96 + size: 32 + fields: + - name: INT1_0 + description: GPIO interrupt 0 status register for GPIO32-56 + bitOffset: 0 + bitWidth: 25 + access: read-only + - register: + name: INTR_1 + description: GPIO interrupt 1 status register for GPIO0-31 + addressOffset: 100 + size: 32 + fields: + - name: INT_1 + description: GPIO interrupt 1 status register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INTR1_1 + description: GPIO interrupt 1 status register for GPIO32-56 + addressOffset: 104 + size: 32 + fields: + - name: INT1_1 + description: GPIO interrupt 1 status register for GPIO32-56 + bitOffset: 0 + bitWidth: 25 + access: read-only + - register: + name: STATUS_NEXT + description: GPIO interrupt source register for GPIO0-31 + addressOffset: 108 + size: 32 + fields: + - name: STATUS_INTERRUPT_NEXT + description: GPIO interrupt source register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: STATUS_NEXT1 + description: GPIO interrupt source register for GPIO32-56 + addressOffset: 112 + size: 32 + fields: + - name: STATUS_INTERRUPT_NEXT1 + description: GPIO interrupt source register for GPIO32-56 + bitOffset: 0 + bitWidth: 25 + access: read-only + - register: + dim: 57 + dimIncrement: 4 + name: PIN%s + description: GPIO pin configuration register + addressOffset: 116 + size: 32 + fields: + - name: SYNC2_BYPASS + description: "set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: PAD_DRIVER + description: "set this bit to select pad driver. 1:open-drain. 0:normal." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SYNC1_BYPASS + description: "set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge." + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: INT_TYPE + description: "set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CONFIG + description: reserved + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: INT_ENA + description: set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. + bitOffset: 13 + bitWidth: 5 + access: read-write + - register: + dim: 57 + dimIncrement: 4 + name: FUNC%s_OUT_SEL_CFG + description: GPIO output function select register + addressOffset: 1368 + size: 32 + resetValue: 256 + fields: + - name: OUT_SEL + description: "The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n]." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: INV_SEL + description: "set this bit to invert output signal.1:invert.0:not invert." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OEN_SEL + description: "set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OEN_INV_SEL + description: "set this bit to invert output enable signal.1:invert.0:not invert." + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: INTR_2 + description: GPIO interrupt 2 status register for GPIO0-31 + addressOffset: 1596 + size: 32 + fields: + - name: INT_2 + description: GPIO interrupt 2 status register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INTR1_2 + description: GPIO interrupt 2 status register for GPIO32-56 + addressOffset: 1600 + size: 32 + fields: + - name: INT1_2 + description: GPIO interrupt 2 status register for GPIO32-56 + bitOffset: 0 + bitWidth: 25 + access: read-only + - register: + name: INTR_3 + description: GPIO interrupt 3 status register for GPIO0-31 + addressOffset: 1604 + size: 32 + fields: + - name: INT_3 + description: GPIO interrupt 3 status register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INTR1_3 + description: GPIO interrupt 3 status register for GPIO32-56 + addressOffset: 1608 + size: 32 + fields: + - name: INT1_3 + description: GPIO interrupt 3 status register for GPIO32-56 + bitOffset: 0 + bitWidth: 25 + access: read-only + - register: + name: CLOCK_GATE + description: GPIO clock gate register + addressOffset: 1612 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: set this bit to enable GPIO clock gate + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: analog comparator interrupt raw + addressOffset: 1792 + size: 32 + fields: + - name: COMP0_NEG_INT_RAW + description: analog comparator pos edge interrupt raw + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: COMP0_POS_INT_RAW + description: analog comparator neg edge interrupt raw + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: COMP0_ALL_INT_RAW + description: analog comparator neg or pos edge interrupt raw + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: COMP1_NEG_INT_RAW + description: analog comparator pos edge interrupt raw + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: COMP1_POS_INT_RAW + description: analog comparator neg edge interrupt raw + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: COMP1_ALL_INT_RAW + description: analog comparator neg or pos edge interrupt raw + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BISTOK_INT_RAW + description: pad bistok interrupt raw + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BISTFAIL_INT_RAW + description: pad bistfail interrupt raw + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: analog comparator interrupt status + addressOffset: 1796 + size: 32 + fields: + - name: COMP0_NEG_INT_ST + description: analog comparator pos edge interrupt status + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: COMP0_POS_INT_ST + description: analog comparator neg edge interrupt status + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: COMP0_ALL_INT_ST + description: analog comparator neg or pos edge interrupt status + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: COMP1_NEG_INT_ST + description: analog comparator pos edge interrupt status + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: COMP1_POS_INT_ST + description: analog comparator neg edge interrupt status + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: COMP1_ALL_INT_ST + description: analog comparator neg or pos edge interrupt status + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: BISTOK_INT_ST + description: pad bistok interrupt status + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BISTFAIL_INT_ST + description: pad bistfail interrupt status + bitOffset: 7 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: analog comparator interrupt enable + addressOffset: 1800 + size: 32 + resetValue: 255 + fields: + - name: COMP0_NEG_INT_ENA + description: analog comparator pos edge interrupt enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: COMP0_POS_INT_ENA + description: analog comparator neg edge interrupt enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: COMP0_ALL_INT_ENA + description: analog comparator neg or pos edge interrupt enable + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: COMP1_NEG_INT_ENA + description: analog comparator pos edge interrupt enable + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: COMP1_POS_INT_ENA + description: analog comparator neg edge interrupt enable + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: COMP1_ALL_INT_ENA + description: analog comparator neg or pos edge interrupt enable + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BISTOK_INT_ENA + description: pad bistok interrupt enable + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BISTFAIL_INT_ENA + description: pad bistfail interrupt enable + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: analog comparator interrupt clear + addressOffset: 1804 + size: 32 + fields: + - name: COMP0_NEG_INT_CLR + description: analog comparator pos edge interrupt clear + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: COMP0_POS_INT_CLR + description: analog comparator neg edge interrupt clear + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: COMP0_ALL_INT_CLR + description: analog comparator neg or pos edge interrupt clear + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: COMP1_NEG_INT_CLR + description: analog comparator pos edge interrupt clear + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: COMP1_POS_INT_CLR + description: analog comparator neg edge interrupt clear + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: COMP1_ALL_INT_CLR + description: analog comparator neg or pos edge interrupt clear + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: BISTOK_INT_CLR + description: pad bistok interrupt enable + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: BISTFAIL_INT_CLR + description: pad bistfail interrupt enable + bitOffset: 7 + bitWidth: 1 + access: write-only + - register: + name: ZERO_DET0_FILTER_CNT + description: GPIO analog comparator zero detect filter count + addressOffset: 1808 + size: 32 + resetValue: 4294967295 + fields: + - name: ZERO_DET0_FILTER_CNT + description: GPIO analog comparator zero detect filter count + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ZERO_DET1_FILTER_CNT + description: GPIO analog comparator zero detect filter count + addressOffset: 1812 + size: 32 + resetValue: 4294967295 + fields: + - name: ZERO_DET1_FILTER_CNT + description: GPIO analog comparator zero detect filter count + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SEND_SEQ + description: High speed sdio pad bist send sequence + addressOffset: 1816 + size: 32 + resetValue: 305419896 + fields: + - name: SEND_SEQ + description: High speed sdio pad bist send sequence + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RECIVE_SEQ + description: High speed sdio pad bist recive sequence + addressOffset: 1820 + size: 32 + fields: + - name: RECIVE_SEQ + description: High speed sdio pad bist recive sequence + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BISTIN_SEL + description: High speed sdio pad bist in pad sel + addressOffset: 1824 + size: 32 + resetValue: 15 + fields: + - name: BISTIN_SEL + description: "High speed sdio pad bist in pad sel 0:pad39, 1: pad40..." + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: BIST_CTRL + description: High speed sdio pad bist control + addressOffset: 1828 + size: 32 + resetValue: 1 + fields: + - name: BIST_PAD_OE + description: High speed sdio pad bist out pad oe + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: BIST_START + description: High speed sdio pad bist start + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: DATE + description: GPIO version register + addressOffset: 2044 + size: 32 + resetValue: 2294787 + fields: + - name: DATE + description: version register + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + dim: 254 + dimIncrement: 4 + dimIndex: "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254" + name: FUNC%s_IN_SEL_CFG + description: GPIO input function configuration register + addressOffset: 348 + size: 32 + access: read-write + fields: + - name: IN_SEL + description: "set this value: s=0-56: connect GPIO[s] to this port. s=0x3F: set this port always high level. s=0x3E: set this port always low level." + bitOffset: 0 + bitWidth: 6 + - name: IN_INV_SEL + description: "set this bit to invert input signal. 1:invert. 0:not invert." + bitOffset: 6 + bitWidth: 1 + - name: SEL + description: "set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO." + bitOffset: 7 + bitWidth: 1 + - name: GPIO_SD + description: Sigma-Delta Modulation + groupName: GPIOSD + baseAddress: 1343098624 + addressBlock: + - offset: 0 + size: 164 + usage: registers + registers: + - register: + dim: 8 + dimIncrement: 4 + name: SIGMADELTA%s + description: Duty Cycle Configure Register of SDM%s + addressOffset: 0 + size: 32 + resetValue: 65280 + fields: + - name: SD_IN + description: This field is used to configure the duty cycle of sigma delta modulation output. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SD_PRESCALE + description: This field is used to set a divider value to divide APB clock. + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: CLOCK_GATE + description: Clock Gating Configure Register + addressOffset: 32 + size: 32 + fields: + - name: CLK_EN + description: Clock enable bit of configuration registers for sigma delta modulation. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SIGMADELTA_MISC + description: MISC Register + addressOffset: 36 + size: 32 + fields: + - name: FUNCTION_CLK_EN + description: Clock enable bit of sigma delta modulation. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI_SWAP + description: Reserved. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + name: GLITCH_FILTER_CH%s + description: Glitch Filter Configure Register of Channel%s + addressOffset: 48 + size: 32 + fields: + - name: FILTER_CH0_EN + description: Glitch Filter channel enable bit. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FILTER_CH0_INPUT_IO_NUM + description: Glitch Filter input io number. + bitOffset: 1 + bitWidth: 6 + access: read-write + - name: FILTER_CH0_WINDOW_THRES + description: Glitch Filter window threshold. + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: FILTER_CH0_WINDOW_WIDTH + description: Glitch Filter window width. + bitOffset: 13 + bitWidth: 6 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + name: ETM_EVENT_CH%s_CFG + description: Etm Config register of Channel%s + addressOffset: 96 + size: 32 + fields: + - name: ETM_CH0_EVENT_SEL + description: Etm event channel select gpio. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: ETM_CH0_EVENT_EN + description: Etm event send enable bit. + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: ETM_TASK_P0_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 160 + size: 32 + fields: + - name: ETM_TASK_GPIO0_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO0_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO1_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO1_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO2_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO2_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO3_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO3_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P1_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 164 + size: 32 + fields: + - name: ETM_TASK_GPIO4_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO4_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO5_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO5_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO6_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO6_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO7_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO7_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P2_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 168 + size: 32 + fields: + - name: ETM_TASK_GPIO8_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO8_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO9_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO9_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO10_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO10_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO11_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO11_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P3_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 172 + size: 32 + fields: + - name: ETM_TASK_GPIO12_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO12_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO13_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO13_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO14_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO14_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO15_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO15_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P4_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 176 + size: 32 + fields: + - name: ETM_TASK_GPIO16_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO16_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO17_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO17_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO18_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO18_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO19_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO19_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P5_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 180 + size: 32 + fields: + - name: ETM_TASK_GPIO20_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO20_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO21_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO21_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO22_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO22_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO23_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO23_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P6_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 184 + size: 32 + fields: + - name: ETM_TASK_GPIO24_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO24_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO25_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO25_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO26_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO26_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO27_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO27_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P7_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 188 + size: 32 + fields: + - name: ETM_TASK_GPIO28_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO28_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO29_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO29_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO30_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO30_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO31_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO31_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P8_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 192 + size: 32 + fields: + - name: ETM_TASK_GPIO32_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO32_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO33_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO33_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO34_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO34_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO35_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO35_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P9_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 196 + size: 32 + fields: + - name: ETM_TASK_GPIO36_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO36_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO37_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO37_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO38_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO38_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO39_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO39_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P10_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 200 + size: 32 + fields: + - name: ETM_TASK_GPIO40_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO40_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO41_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO41_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO42_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO42_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO43_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO43_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P11_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 204 + size: 32 + fields: + - name: ETM_TASK_GPIO44_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO44_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO45_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO45_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO46_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO46_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO47_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO47_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P12_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 208 + size: 32 + fields: + - name: ETM_TASK_GPIO48_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO48_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO49_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO49_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO50_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO50_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO51_EN + description: Enable bit of GPIO response etm task. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO51_SEL + description: GPIO choose a etm task channel. + bitOffset: 25 + bitWidth: 3 + access: read-write + - register: + name: ETM_TASK_P13_CFG + description: Etm Configure Register to decide which GPIO been chosen + addressOffset: 212 + size: 32 + fields: + - name: ETM_TASK_GPIO52_EN + description: Enable bit of GPIO response etm task. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO52_SEL + description: GPIO choose a etm task channel. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO53_EN + description: Enable bit of GPIO response etm task. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO53_SEL + description: GPIO choose a etm task channel. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: ETM_TASK_GPIO54_EN + description: Enable bit of GPIO response etm task. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ETM_TASK_GPIO54_SEL + description: GPIO choose a etm task channel. + bitOffset: 17 + bitWidth: 3 + access: read-write + - register: + name: VERSION + description: Version Control Register + addressOffset: 252 + size: 32 + resetValue: 35663952 + fields: + - name: GPIO_SD_DATE + description: Version control register. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: H264 + description: H264 Encoder (Core) + groupName: H264 + baseAddress: 1342717952 + addressBlock: + - offset: 0 + size: 244 + usage: registers + interrupt: + - name: H264_REG + value: 126 + registers: + - register: + name: SYS_CTRL + description: H264 system level control register. + addressOffset: 0 + size: 32 + fields: + - name: FRAME_START + description: "Configures whether or not to start encoding one frame.\\\\0: Invalid. No effect\\\\1: Start encoding one frame" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: DMA_MOVE_START + description: "Configures whether or not to start moving reference data from external mem.\\\\0: Invalid. No effect\\\\1: H264 start moving two MB lines of reference frame from external mem to internal mem" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: FRAME_MODE + description: "Configures H264 running mode. When field H264_DUAL_STREAM_MODE is set to 1, this field must be set to 1 too.\\\\0: GOP mode. Before every GOP first frame start, need reconfig reference frame DMA\\\\1: Frame mode. Before every frame start, need reconfig reference frame DMA" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SYS_RST_PULSE + description: "Configures whether or not to reset H264 ip.\\\\0: Invalid. No effect\\\\1: Reset H264 ip" + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: GOP_CONF + description: GOP related configuration register. + addressOffset: 4 + size: 32 + fields: + - name: DUAL_STREAM_MODE + description: "Configures whether or not to enable dual stream mode. When this field is set to 1, H264_FRAME_MODE field must be set to 1 too.\\\\0: Normal mode\\\\1: Dual stream mode" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: GOP_NUM + description: "Configures the frame number of one GOP.\\\\0: The frame number of one GOP is infinite\\\\Others: Actual frame number of one GOP" + bitOffset: 1 + bitWidth: 8 + access: read-write + - register: + name: A_SYS_MB_RES + description: Video A horizontal and vertical MB resolution register. + addressOffset: 8 + size: 32 + fields: + - name: A_SYS_TOTAL_MB_Y + description: Configures video A vertical MB resolution. + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: A_SYS_TOTAL_MB_X + description: Configures video A horizontal MB resolution. + bitOffset: 7 + bitWidth: 7 + access: read-write + - register: + name: A_SYS_CONF + description: Video A system level configuration register. + addressOffset: 12 + size: 32 + resetValue: 515 + fields: + - name: A_DB_TMP_READY_TRIGGER_MB_NUM + description: "Configures when to trigger video A H264_DB_TMP_READY_INT. When the (MB number of written db temp+1) is greater than this filed in first MB line, trigger H264_DB_TMP_READY_INT. Min is 3." + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: A_REC_READY_TRIGGER_MB_LINES + description: "Configures when to trigger video A H264_REC_READY_INT. When the MB line number of generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. Min is 4." + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: A_INTRA_COST_CMP_OFFSET + description: Configures video A intra cost offset when I MB compared with P MB. + bitOffset: 14 + bitWidth: 16 + access: read-write + - register: + name: A_DECI_SCORE + description: Video A luma and chroma MB decimate score Register. + addressOffset: 16 + size: 32 + fields: + - name: A_C_DECI_SCORE + description: "Configures video A chroma MB decimate score. When chroma score is smaller than it, chroma decimate will be enable." + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: A_L_DECI_SCORE + description: "Configures video A luma MB decimate score. When luma score is smaller than it, luma decimate will be enable." + bitOffset: 10 + bitWidth: 10 + access: read-write + - register: + name: A_DECI_SCORE_OFFSET + description: Video A luma and chroma MB decimate score offset Register. + addressOffset: 20 + size: 32 + fields: + - name: A_I16X16_DECI_SCORE_OFFSET + description: Configures video A i16x16 MB decimate score offset. This offset will be added to i16x16 MB score. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: A_I_CHROMA_DECI_SCORE_OFFSET + description: Configures video A I chroma MB decimate score offset. This offset will be added to I chroma MB score. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: A_P16X16_DECI_SCORE_OFFSET + description: Configures video A p16x16 MB decimate score offset. This offset will be added to p16x16 MB score. + bitOffset: 12 + bitWidth: 6 + access: read-write + - name: A_P_CHROMA_DECI_SCORE_OFFSET + description: Configures video A p chroma MB decimate score offset. This offset will be added to p chroma MB score. + bitOffset: 18 + bitWidth: 6 + access: read-write + - register: + name: A_RC_CONF0 + description: Video A rate control configuration register0. + addressOffset: 24 + size: 32 + fields: + - name: A_QP + description: Configures video A frame level initial luma QP value. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: A_RATE_CTRL_U + description: Configures video A parameter U value. U = int((float) u << 8). + bitOffset: 6 + bitWidth: 16 + access: read-write + - name: A_MB_RATE_CTRL_EN + description: "Configures video A whether or not to open macro block rate ctrl.\\\\1:Open the macro block rate ctrl\\\\1:Close the macro block rate ctrl." + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: A_RC_CONF1 + description: Video A rate control configuration register1. + addressOffset: 28 + size: 32 + fields: + - name: A_CHROMA_DC_QP_DELTA + description: Configures video A chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta. + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: A_CHROMA_QP_DELTA + description: Configures video A chroma QP offset based on luma QP. Chroma QP(before map) = Luma QP + reg_chroma_qp_delta. + bitOffset: 3 + bitWidth: 4 + access: read-write + - name: A_QP_MIN + description: Configures video A allowed luma QP min value. + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: A_QP_MAX + description: Configures video A allowed luma QP max value. + bitOffset: 13 + bitWidth: 6 + access: read-write + - name: A_MAD_FRAME_PRED + description: Configures vdieo A frame level predicted MB MAD value. + bitOffset: 19 + bitWidth: 12 + access: read-write + - register: + name: A_DB_BYPASS + description: Video A Deblocking bypass register + addressOffset: 32 + size: 32 + fields: + - name: A_BYPASS_DB_FILTER + description: "Configures whether or not to bypass video A deblcoking filter. \\\\0: Open the deblock filter\\\\1: Close the deblock filter" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: A_ROI_REGION0 + description: Video A H264 ROI region0 range configure register. + addressOffset: 36 + size: 32 + fields: + - name: X + description: Configures the horizontal start macroblocks of region 0 in Video A. + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: Y + description: Configures the vertical start macroblocks of region 0 in Video A. + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: X_LEN + description: Configures the number of macroblocks in horizontal direction of the region 0 in Video A. + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: Y_LEN + description: Configures the number of macroblocks in vertical direction of the region 0 in Video A. + bitOffset: 21 + bitWidth: 7 + access: read-write + - name: EN + description: "Configures whether or not to open Video A ROI of region 0 .\\\\0:Close ROI\\\\1:Open ROI." + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: A_ROI_REGION1 + description: Video A H264 ROI region1 range configure register. + addressOffset: 40 + size: 32 + fields: + - name: X + description: Configures the horizontal start macroblocks of region 1 in Video A. + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: Y + description: Configures the vertical start macroblocks of region 1 in Video A. + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: X_LEN + description: Configures the number of macroblocks in horizontal direction of the region 1 in Video A. + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: Y_LEN + description: Configures the number of macroblocks in vertical direction of the region 1 in Video A. + bitOffset: 21 + bitWidth: 7 + access: read-write + - name: EN + description: "Configures whether or not to open Video A ROI of region 1 .\\\\0:Close ROI\\\\1:Open ROI." + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: A_ROI_REGION2 + description: Video A H264 ROI region2 range configure register. + addressOffset: 44 + size: 32 + fields: + - name: X + description: Configures the horizontal start macroblocks of region 2 in Video A. + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: Y + description: Configures the vertical start macroblocks of region 2 in Video A. + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: X_LEN + description: Configures the number of macroblocks in horizontal direction of the region 2 in Video A. + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: Y_LEN + description: Configures the number of macroblocks in vertical direction of the region 2 in Video A. + bitOffset: 21 + bitWidth: 7 + access: read-write + - name: EN + description: "Configures whether or not to open Video A ROI of region 2 .\\\\0:Close ROI\\\\1:Open ROI." + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: A_ROI_REGION3 + description: Video A H264 ROI region3 range configure register. + addressOffset: 48 + size: 32 + fields: + - name: X + description: Configures the horizontal start macroblocks of region 3 in Video A. + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: Y + description: Configures the vertical start macroblocks of region 3 in Video A. + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: X_LEN + description: Configures the number of macroblocks in horizontal direction of the region 3 in video A. + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: Y_LEN + description: Configures the number of macroblocks in vertical direction of the region 3 in video A. + bitOffset: 21 + bitWidth: 7 + access: read-write + - name: EN + description: "Configures whether or not to open Video A ROI of region 3 .\\\\0:Close ROI\\\\1:Open ROI." + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: A_ROI_REGION4 + description: Video A H264 ROI region4 range configure register. + addressOffset: 52 + size: 32 + fields: + - name: X + description: Configures the horizontal start macroblocks of region 4 in Video A. + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: Y + description: Configures the vertical start macroblocks of region 4 in Video A. + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: X_LEN + description: Configures the number of macroblocks in horizontal direction of the region 4 in video A. + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: Y_LEN + description: Configures the number of macroblocks in vertical direction of the region 4 in video A. + bitOffset: 21 + bitWidth: 7 + access: read-write + - name: EN + description: "Configures whether or not to open Video A ROI of region 4 .\\\\0:Close ROI\\\\1:Open ROI." + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: A_ROI_REGION5 + description: Video A H264 ROI region5 range configure register. + addressOffset: 56 + size: 32 + fields: + - name: X + description: Configures the horizontial start macroblocks of region 5 video A. + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: Y + description: Configures the vertical start macroblocks of region 5 video A. + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: X_LEN + description: Configures the number of macroblocks in horizontal direction of the region 5 video A. + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: Y_LEN + description: Configures the number of macroblocks in vertical direction of the region 5 in video A. + bitOffset: 21 + bitWidth: 7 + access: read-write + - name: EN + description: "Configures whether or not to open Video A ROI of region 5 .\\\\0:Close ROI\\\\1:Open ROI." + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: A_ROI_REGION6 + description: Video A H264 ROI region6 range configure register. + addressOffset: 60 + size: 32 + fields: + - name: X + description: Configures the horizontial start macroblocks of region 6 video A. + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: Y + description: Configures the vertical start macroblocks of region 6 in video A. + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: X_LEN + description: Configures the number of macroblocks in horizontal direction of the region 6 in video A. + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: Y_LEN + description: Configures the number of macroblocks in vertical direction of the region 6 in video A. + bitOffset: 21 + bitWidth: 7 + access: read-write + - name: EN + description: "Configures whether or not to open Video A ROI of region 6 .\\\\0:Close ROI\\\\1:Open ROI." + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: A_ROI_REGION7 + description: Video A H264 ROI region7 range configure register. + addressOffset: 64 + size: 32 + fields: + - name: X + description: Configures the horizontal start macroblocks of region 7 in video A. + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: Y + description: Configures the vertical start macroblocks of region 7 in video A. + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: X_LEN + description: Configures the number of macroblocks in horizontal direction of the region 7 in video A. + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: Y_LEN + description: Configures the number of macroblocks in vertical direction of the region 7 in video A. + bitOffset: 21 + bitWidth: 7 + access: read-write + - name: EN + description: "Configures whether or not to open Video A ROI of region 7 .\\\\0:Close ROI\\\\1:Open ROI." + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: A_ROI_REGION0_3_QP + description: "Video A H264 ROI region0, region1,region2,region3 QP register." + addressOffset: 68 + size: 32 + fields: + - name: A_ROI_REGION0_QP + description: "Configure H264 ROI region0 qp in video A,fixed qp or delta qp." + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: A_ROI_REGION1_QP + description: "Configure H264 ROI region1 qp in video A,fixed qp or delta qp." + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: A_ROI_REGION2_QP + description: "Configure H264 ROI region2 qp in video A,fixed qp or delta qp." + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: A_ROI_REGION3_QP + description: "Configure H264 ROI region3 qp in video A,fixed qp or delta qp." + bitOffset: 21 + bitWidth: 7 + access: read-write + - register: + name: A_ROI_REGION4_7_QP + description: "Video A H264 ROI region4, region5,region6,region7 QP register." + addressOffset: 72 + size: 32 + fields: + - name: A_ROI_REGION4_QP + description: "Configure H264 ROI region4 qp in video A,fixed qp or delta qp." + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: A_ROI_REGION5_QP + description: "Configure H264 ROI region5 qp in video A,fixed qp or delta qp." + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: A_ROI_REGION6_QP + description: "Configure H264 ROI region6 qp in video A,fixed qp or delta qp." + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: A_ROI_REGION7_QP + description: "Configure H264 ROI region7 qp in video A,fixed qp or delta qp." + bitOffset: 21 + bitWidth: 7 + access: read-write + - register: + name: A_NO_ROI_REGION_QP_OFFSET + description: Video A H264 no roi region QP register. + addressOffset: 76 + size: 32 + fields: + - name: A_NO_ROI_REGION_QP + description: "Configure H264 no region qp in video A, delta qp." + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: A_ROI_CONFIG + description: Video A H264 ROI configure register. + addressOffset: 80 + size: 32 + fields: + - name: A_ROI_EN + description: "Configure whether or not to enable ROI in video A.\\\\0:not enable ROI\\\\1:enable ROI." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: A_ROI_MODE + description: "Configure the mode of ROI in video A.\\\\0:fixed qp\\\\1:delta qp." + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: B_SYS_MB_RES + description: Video B horizontal and vertical MB resolution register. + addressOffset: 84 + size: 32 + fields: + - name: B_SYS_TOTAL_MB_Y + description: Configures video B vertical MB resolution. + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: B_SYS_TOTAL_MB_X + description: Configures video B horizontal MB resolution. + bitOffset: 7 + bitWidth: 7 + access: read-write + - register: + name: B_SYS_CONF + description: Video B system level configuration register. + addressOffset: 88 + size: 32 + resetValue: 515 + fields: + - name: B_DB_TMP_READY_TRIGGER_MB_NUM + description: "Configures when to trigger video B H264_DB_TMP_READY_INT. When the (MB number of written db temp+1) is greater than this filed in first MB line, trigger H264_DB_TMP_READY_INT. Min is 3." + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: B_REC_READY_TRIGGER_MB_LINES + description: "Configures when to trigger video B H264_REC_READY_INT. When the MB line number of generated reconstruct pixel is greater than this filed, trigger H264_REC_READY_INT. Min is 4." + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: B_INTRA_COST_CMP_OFFSET + description: Configures video B intra cost offset when I MB compared with P MB. + bitOffset: 14 + bitWidth: 16 + access: read-write + - register: + name: B_DECI_SCORE + description: Video B luma and chroma MB decimate score Register. + addressOffset: 92 + size: 32 + fields: + - name: B_C_DECI_SCORE + description: "Configures video B chroma MB decimate score. When chroma score is smaller than it, chroma decimate will be enable." + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: B_L_DECI_SCORE + description: "Configures video B luma MB decimate score. When luma score is smaller than it, luma decimate will be enable." + bitOffset: 10 + bitWidth: 10 + access: read-write + - register: + name: B_DECI_SCORE_OFFSET + description: Video B luma and chroma MB decimate score offset Register. + addressOffset: 96 + size: 32 + fields: + - name: B_I16X16_DECI_SCORE_OFFSET + description: Configures video B i16x16 MB decimate score offset. This offset will be added to i16x16 MB score. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: B_I_CHROMA_DECI_SCORE_OFFSET + description: Configures video B I chroma MB decimate score offset. This offset will be added to I chroma MB score. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: B_P16X16_DECI_SCORE_OFFSET + description: Configures video B p16x16 MB decimate score offset. This offset will be added to p16x16 MB score. + bitOffset: 12 + bitWidth: 6 + access: read-write + - name: B_P_CHROMA_DECI_SCORE_OFFSET + description: Configures video B p chroma MB decimate score offset. This offset will be added to p chroma MB score. + bitOffset: 18 + bitWidth: 6 + access: read-write + - register: + name: B_RC_CONF0 + description: Video B rate control configuration register0. + addressOffset: 100 + size: 32 + fields: + - name: B_QP + description: Configures video B frame level initial luma QP value. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: B_RATE_CTRL_U + description: Configures video B parameter U value. U = int((float) u << 8). + bitOffset: 6 + bitWidth: 16 + access: read-write + - name: B_MB_RATE_CTRL_EN + description: "Configures video A whether or not to open macro block rate ctrl.\\\\1:Open the macro block rate ctrl\\\\1:Close the macro block rate ctrl." + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: B_RC_CONF1 + description: Video B rate control configuration register1. + addressOffset: 104 + size: 32 + fields: + - name: B_CHROMA_DC_QP_DELTA + description: Configures video B chroma DC QP offset based on Chroma QP. Chroma DC QP = Chroma QP(after map) + reg_chroma_dc_qp_delta. + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: B_CHROMA_QP_DELTA + description: Configures video B chroma QP offset based on luma QP. Chroma QP(before map) = Luma QP + reg_chroma_qp_delta. + bitOffset: 3 + bitWidth: 4 + access: read-write + - name: B_QP_MIN + description: Configures video B allowed luma QP min value. + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: B_QP_MAX + description: Configures video B allowed luma QP max value. + bitOffset: 13 + bitWidth: 6 + access: read-write + - name: B_MAD_FRAME_PRED + description: Configures vdieo B frame level predicted MB MAD value. + bitOffset: 19 + bitWidth: 12 + access: read-write + - register: + name: B_DB_BYPASS + description: Video B Deblocking bypass register + addressOffset: 108 + size: 32 + fields: + - name: B_BYPASS_DB_FILTER + description: "Configures whether or not to bypass video B deblcoking filter. \\\\0: Open the deblock filter\\\\1: Close the deblock filter" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: B_ROI_REGION0 + description: Video B H264 ROI region0 range configure register. + addressOffset: 112 + size: 32 + fields: + - name: X + description: Configures the horizontal start macroblocks of region 0 in Video B. + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: Y + description: Configures the vertical start macroblocks of region 0 in Video B. + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: X_LEN + description: Configures the number of macroblocks in horizontal direction of the region 0 in Video B. + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: Y_LEN + description: Configures the number of macroblocks in vertical direction of the region 0 in Video B. + bitOffset: 21 + bitWidth: 7 + access: read-write + - name: EN + description: "Configures whether or not to open Video B ROI of region 0 .\\\\0:Close ROI\\\\1:Open ROI." + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: B_ROI_REGION1 + description: Video B H264 ROI region1 range configure register. + addressOffset: 116 + size: 32 + fields: + - name: X + description: Configures the horizontal start macroblocks of region 1 in Video B. + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: Y + description: Configures the vertical start macroblocks of region 1 in Video B. + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: X_LEN + description: Configures the number of macroblocks in horizontal direction of the region 1 in Video B. + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: Y_LEN + description: Configures the number of macroblocks in vertical direction of the region 1 in Video B. + bitOffset: 21 + bitWidth: 7 + access: read-write + - name: EN + description: "Configures whether or not to open Video B ROI of region 1 .\\\\0:Close ROI\\\\1:Open ROI." + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: B_ROI_REGION2 + description: Video B H264 ROI region2 range configure register. + addressOffset: 120 + size: 32 + fields: + - name: X + description: Configures the horizontal start macroblocks of region 2 in Video B. + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: Y + description: Configures the vertical start macroblocks of region 2 in Video B. + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: X_LEN + description: Configures the number of macroblocks in horizontal direction of the region 2 in Video B. + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: Y_LEN + description: Configures the number of macroblocks in vertical direction of the region 2 in Video B. + bitOffset: 21 + bitWidth: 7 + access: read-write + - name: EN + description: "Configures whether or not to open Video B ROI of region 2 .\\\\0:Close ROI\\\\1:Open ROI." + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: B_ROI_REGION3 + description: Video B H264 ROI region3 range configure register. + addressOffset: 124 + size: 32 + fields: + - name: X + description: Configures the horizontal start macroblocks of region 3 in Video B. + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: Y + description: Configures the vertical start macroblocks of region 3 in Video B. + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: X_LEN + description: Configures the number of macroblocks in horizontal direction of the region 3 in video B. + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: Y_LEN + description: Configures the number of macroblocks in vertical direction of the region 3 in video B. + bitOffset: 21 + bitWidth: 7 + access: read-write + - name: EN + description: "Configures whether or not to open Video B ROI of region 3 .\\\\0:Close ROI\\\\1:Open ROI." + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: B_ROI_REGION4 + description: Video B H264 ROI region4 range configure register. + addressOffset: 128 + size: 32 + fields: + - name: X + description: Configures the horizontal start macroblocks of region 4 in Video B. + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: Y + description: Configures the vertical start macroblocks of region 4 in Video B. + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: X_LEN + description: Configures the number of macroblocks in horizontal direction of the region 4 in video B. + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: Y_LEN + description: Configures the number of macroblocks in vertical direction of the region 4 in video B. + bitOffset: 21 + bitWidth: 7 + access: read-write + - name: EN + description: "Configures whether or not to open Video B ROI of region 4 .\\\\0:Close ROI\\\\1:Open ROI." + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: B_ROI_REGION5 + description: Video B H264 ROI region5 range configure register. + addressOffset: 132 + size: 32 + fields: + - name: X + description: Configures the horizontial start macroblocks of region 5 video B. + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: Y + description: Configures the vertical start macroblocks of region 5 video B. + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: X_LEN + description: Configures the number of macroblocks in horizontal direction of the region 5 video B. + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: Y_LEN + description: Configures the number of macroblocks in vertical direction of the region 5 in video B. + bitOffset: 21 + bitWidth: 7 + access: read-write + - name: EN + description: "Configures whether or not to open Video B ROI of region 5 .\\\\0:Close ROI\\\\1:Open ROI." + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: B_ROI_REGION6 + description: Video B H264 ROI region6 range configure register. + addressOffset: 136 + size: 32 + fields: + - name: X + description: Configures the horizontial start macroblocks of region 6 video B. + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: Y + description: Configures the vertical start macroblocks of region 6 in video B. + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: X_LEN + description: Configures the number of macroblocks in horizontal direction of the region 6 in video B. + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: Y_LEN + description: Configures the number of macroblocks in vertical direction of the region 6 in video B. + bitOffset: 21 + bitWidth: 7 + access: read-write + - name: EN + description: "Configures whether or not to open Video B ROI of region 6 .\\\\0:Close ROI\\\\1:Open ROI." + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: B_ROI_REGION7 + description: Video B H264 ROI region7 range configure register. + addressOffset: 140 + size: 32 + fields: + - name: X + description: Configures the horizontal start macroblocks of region 7 in video B. + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: Y + description: Configures the vertical start macroblocks of region 7 in video B. + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: X_LEN + description: Configures the number of macroblocks in horizontal direction of the region 7 in video B. + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: Y_LEN + description: Configures the number of macroblocks in vertical direction of the region 7 in video B. + bitOffset: 21 + bitWidth: 7 + access: read-write + - name: EN + description: "Configures whether or not to open Video B ROI of region 7 .\\\\0:Close ROI\\\\1:Open ROI." + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: B_ROI_REGION0_3_QP + description: "Video B H264 ROI region0, region1,region2,region3 QP register." + addressOffset: 144 + size: 32 + fields: + - name: B_ROI_REGION0_QP + description: "Configure H264 ROI region0 qp in video B,fixed qp or delta qp." + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: B_ROI_REGION1_QP + description: "Configure H264 ROI region1 qp in video B,fixed qp or delta qp." + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: B_ROI_REGION2_QP + description: "Configure H264 ROI region2 qp in video B,fixed qp or delta qp." + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: B_ROI_REGION3_QP + description: "Configure H264 ROI region3 qp in video B,fixed qp or delta qp." + bitOffset: 21 + bitWidth: 7 + access: read-write + - register: + name: B_ROI_REGION4_7_QP + description: "Video B H264 ROI region4, region5,region6,region7 QP register." + addressOffset: 148 + size: 32 + fields: + - name: B_ROI_REGION4_QP + description: "Configure H264 ROI region4 qp in video B,fixed qp or delta qp." + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: B_ROI_REGION5_QP + description: "Configure H264 ROI region5 qp in video B,fixed qp or delta qp." + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: B_ROI_REGION6_QP + description: "Configure H264 ROI region6 qp in video B,fixed qp or delta qp." + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: B_ROI_REGION7_QP + description: "Configure H264 ROI region7 qp in video B,fixed qp or delta qp." + bitOffset: 21 + bitWidth: 7 + access: read-write + - register: + name: B_NO_ROI_REGION_QP_OFFSET + description: Video B H264 no roi region QP register. + addressOffset: 152 + size: 32 + fields: + - name: B_NO_ROI_REGION_QP + description: "Configure H264 no region qp in video B, delta qp." + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: B_ROI_CONFIG + description: Video B H264 ROI configure register. + addressOffset: 156 + size: 32 + fields: + - name: B_ROI_EN + description: "Configure whether or not to enable ROI in video B.\\\\0:not enable ROI\\\\1:enable ROI." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: B_ROI_MODE + description: "Configure the mode of ROI in video B.\\\\0:fixed qp\\\\1:delta qp." + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: RC_STATUS0 + description: Rate control status register0. + addressOffset: 160 + size: 32 + fields: + - name: FRAME_MAD_SUM + description: Represents all MB actual MAD sum value of one frame. + bitOffset: 0 + bitWidth: 21 + access: read-only + - register: + name: RC_STATUS1 + description: Rate control status register1. + addressOffset: 164 + size: 32 + fields: + - name: FRAME_ENC_BITS + description: Represents all MB actual encoding bits sum value of one frame. + bitOffset: 0 + bitWidth: 27 + access: read-only + - register: + name: RC_STATUS2 + description: Rate control status register2. + addressOffset: 168 + size: 32 + fields: + - name: FRAME_QP_SUM + description: Represents all MB actual luma QP sum value of one frame. + bitOffset: 0 + bitWidth: 19 + access: read-only + - register: + name: SLICE_HEADER_REMAIN + description: Frame Slice Header remain bit register. + addressOffset: 172 + size: 32 + fields: + - name: SLICE_REMAIN_BITLENGTH + description: Configures Slice Header remain bit number + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SLICE_REMAIN_BIT + description: Configures Slice Header remain bit + bitOffset: 3 + bitWidth: 8 + access: read-write + - register: + name: SLICE_HEADER_BYTE_LENGTH + description: Frame Slice Header byte length register. + addressOffset: 176 + size: 32 + fields: + - name: SLICE_BYTE_LENGTH + description: Configures Slice Header byte number + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: BS_THRESHOLD + description: Bitstream buffer overflow threshold register + addressOffset: 180 + size: 32 + resetValue: 48 + fields: + - name: BS_BUFFER_THRESHOLD + description: Configures bitstream buffer overflow threshold. This value should be bigger than the encode bytes of one 4x4 submb. + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: SLICE_HEADER_BYTE0 + description: Frame Slice Header byte low 32 bit register. + addressOffset: 184 + size: 32 + fields: + - name: SLICE_BYTE_LSB + description: Configures Slice Header low 32 bit + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SLICE_HEADER_BYTE1 + description: Frame Slice Header byte high 32 bit register. + addressOffset: 188 + size: 32 + fields: + - name: SLICE_BYTE_MSB + description: Configures Slice Header high 32 bit + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: INT_RAW + description: Interrupt raw status register + addressOffset: 192 + size: 32 + fields: + - name: DB_TMP_READY_INT_RAW + description: "Raw status bit: The raw interrupt status of H264_DB_TMP_READY_INT. Triggered when H264 written enough db tmp pixel." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REC_READY_INT_RAW + description: "Raw status bit: The raw interrupt status of H264_REC_READY_INT. Triggered when H264 encoding enough reconstruct pixel." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FRAME_DONE_INT_RAW + description: "Raw status bit: The raw interrupt status of H264_FRAME_DONE_INT. Triggered when H264 encoding one frame done." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DMA_MOVE_2MB_LINE_DONE_INT_RAW + description: "Raw status bit: The raw interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. Triggered when H264 move two MB lines of reference frame from external mem to internal mem done." + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Interrupt masked status register + addressOffset: 196 + size: 32 + fields: + - name: DB_TMP_READY_INT_ST + description: The masked interrupt status of H264_DB_TMP_READY_INT. Valid only when the H264_DB_TMP_READY_INT_ENA is set to 1. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: REC_READY_INT_ST + description: The masked interrupt status of H264_REC_READY_INT. Valid only when the H264_REC_READY_INT_ENA is set to 1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: FRAME_DONE_INT_ST + description: The masked interrupt status of H264_FRAME_DONE_INT. Valid only when the H264_FRAME_DONE_INT_ENA is set to 1. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: DMA_MOVE_2MB_LINE_DONE_INT_ST + description: "Masked status bit: The masked interrupt status of H264_DMA_MOVE_2MB_LINE_DONE_INT. Valid only when the H264_DMA_MOVE_2MB_LINE_DONE_INT_ENA is set to 1." + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable register + addressOffset: 200 + size: 32 + fields: + - name: DB_TMP_READY_INT_ENA + description: Write 1 to enable H264_DB_TMP_READY_INT. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REC_READY_INT_ENA + description: Write 1 to enable H264_REC_READY_INT. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FRAME_DONE_INT_ENA + description: Write 1 to enable H264_FRAME_DONE_INT. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DMA_MOVE_2MB_LINE_DONE_INT_ENA + description: "Enable bit: Write 1 to enable H264_DMA_MOVE_2MB_LINE_DONE_INT." + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear register + addressOffset: 204 + size: 32 + fields: + - name: DB_TMP_READY_INT_CLR + description: Write 1 to clear H264_DB_TMP_READY_INT. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: REC_READY_INT_CLR + description: Write 1 to clear H264_REC_READY_INT. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: FRAME_DONE_INT_CLR + description: Write 1 to clear H264_FRAME_DONE_INT. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: DMA_MOVE_2MB_LINE_DONE_INT_CLR + description: "Clear bit: Write 1 to clear H264_DMA_MOVE_2MB_LINE_DONE_INT." + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: CONF + description: General configuration register. + addressOffset: 208 + size: 32 + fields: + - name: CLK_EN + description: "Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REC_RAM_CLK_EN2 + description: "Configures whether or not to open the clock gate for rec ram2.\\\\0: Open the clock gate only when application writes or reads rec ram2\\\\1: Force open the clock gate for rec ram2" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REC_RAM_CLK_EN1 + description: "Configures whether or not to open the clock gate for rec ram1.\\\\0: Open the clock gate only when application writes or reads rec ram1\\\\1: Force open the clock gate for rec ram1" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: QUANT_RAM_CLK_EN2 + description: "Configures whether or not to open the clock gate for quant ram2.\\\\0: Open the clock gate only when application writes or reads quant ram2\\\\1: Force open the clock gate for quant ram2" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: QUANT_RAM_CLK_EN1 + description: "Configures whether or not to open the clock gate for quant ram1.\\\\0: Open the clock gate only when application writes or reads quant ram1\\\\1: Force open the clock gate for quant ram1" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: PRE_RAM_CLK_EN + description: "Configures whether or not to open the clock gate for pre ram.\\\\0: Open the clock gate only when application writes or reads pre ram\\\\1: Force open the clock gate for pre ram" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: MVD_RAM_CLK_EN + description: "Configures whether or not to open the clock gate for mvd ram.\\\\0: Open the clock gate only when application writes or reads mvd ram\\\\1: Force open the clock gate for mvd ram" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: MC_RAM_CLK_EN + description: "Configures whether or not to open the clock gate for mc ram.\\\\0: Open the clock gate only when application writes or reads mc ram\\\\1: Force open the clock gate for mc ram" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: REF_RAM_CLK_EN + description: "Configures whether or not to open the clock gate for ref ram.\\\\0: Open the clock gate only when application writes or reads ref ram\\\\1: Force open the clock gate for ref ram" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: I4X4_REF_RAM_CLK_EN + description: "Configures whether or not to open the clock gate for i4x4_mode ram.\\\\0: Open the clock gate only when application writes or reads i4x4_mode ram\\\\1: Force open the clock gate for i4x4_mode ram" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: IME_RAM_CLK_EN + description: "Configures whether or not to open the clock gate for ime ram.\\\\0: Open the clock gate only when application writes or reads ime ram\\\\1: Force open the clock gate for ime ram" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FME_RAM_CLK_EN + description: "Configures whether or not to open the clock gate for fme ram.\\\\0: Open the clock gate only when application writes or readsfme ram\\\\1: Force open the clock gate for fme ram" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FETCH_RAM_CLK_EN + description: "Configures whether or not to open the clock gate for fetch ram.\\\\0: Open the clock gate only when application writes or reads fetch ram\\\\1: Force open the clock gate for fetch ram" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DB_RAM_CLK_EN + description: "Configures whether or not to open the clock gate for db ram.\\\\0: Open the clock gate only when application writes or reads db ram\\\\1: Force open the clock gate for db ram" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: CUR_MB_RAM_CLK_EN + description: "Configures whether or not to open the clock gate for cur_mb ram.\\\\0: Open the clock gate only when application writes or reads cur_mb ram\\\\1: Force open the clock gate for cur_mb ram" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CAVLC_RAM_CLK_EN + description: "Configures whether or not to open the clock gate for cavlc ram.\\\\0: Open the clock gate only when application writes or reads cavlc ram\\\\1: Force open the clock gate for cavlc ram" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: IME_CLK_EN + description: "Configures whether or not to open the clock gate for ime.\\\\0: Open the clock gate only when ime work\\\\1: Force open the clock gate for ime" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FME_CLK_EN + description: "Configures whether or not to open the clock gate for fme.\\\\0: Open the clock gate only when fme work\\\\1: Force open the clock gate for fme" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MC_CLK_EN + description: "Configures whether or not to open the clock gate for mc.\\\\0: Open the clock gate only when mc work\\\\1: Force open the clock gate for mc" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: INTERPOLATOR_CLK_EN + description: "Configures whether or not to open the clock gate for interpolator.\\\\0: Open the clock gate only when interpolator work\\\\1: Force open the clock gate for interpolator" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: DB_CLK_EN + description: "Configures whether or not to open the clock gate for deblocking filter.\\\\0: Open the clock gate only when deblocking filter work\\\\1: Force open the clock gate for deblocking filter" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CLAVLC_CLK_EN + description: "Configures whether or not to open the clock gate for cavlc.\\\\0: Open the clock gate only when cavlc work\\\\1: Force open the clock gate for cavlc" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: INTRA_CLK_EN + description: "Configures whether or not to open the clock gate for intra.\\\\0: Open the clock gate only when intra work\\\\1: Force open the clock gate for intra" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: DECI_CLK_EN + description: "Configures whether or not to open the clock gate for decimate.\\\\0: Open the clock gate only when decimate work\\\\1: Force open the clock gate for decimate" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: BS_CLK_EN + description: "Configures whether or not to open the clock gate for bs buffer.\\\\0: Open the clock gate only when bs buffer work\\\\1: Force open the clock gate for bs buffer" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: MV_MERGE_CLK_EN + description: "Configures whether or not to open the clock gate for mv merge.\\\\0: Open the clock gate only when mv merge work\\\\1: Force open the clock gate for mv merge" + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: MV_MERGE_CONFIG + description: Mv merge configuration register. + addressOffset: 212 + size: 32 + fields: + - name: MV_MERGE_TYPE + description: "Configure mv merge type.\\\\0: merge p16x16 mv\\\\1: merge min mv\\\\2: merge max mv\\\\3: not valid." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: INT_MV_OUT_EN + description: "Configure mv merge output integer part not zero mv or all part not zero mv.\\\\0: output all part not zero mv\\\\1: output integer part not zero mv." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: A_MV_MERGE_EN + description: "Configure whether or not to enable video A mv merge.\\\\0: disable\\\\1: enable." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: B_MV_MERGE_EN + description: "Configure whether or not to enable video B mv merge.\\\\0: disable\\\\1: enable." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MB_VALID_NUM + description: Represents the valid mb number of mv merge output. + bitOffset: 5 + bitWidth: 13 + access: read-only + - register: + name: DEBUG_DMA_SEL + description: Debug H264 DMA select register + addressOffset: 216 + size: 32 + fields: + - name: DBG_DMA_SEL + description: Every bit represents a dma in h264 + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: SYS_STATUS + description: System status register. + addressOffset: 220 + size: 32 + fields: + - name: FRAME_NUM + description: Represents current frame number. + bitOffset: 0 + bitWidth: 9 + access: read-only + - name: DUAL_STREAM_SEL + description: "Represents which register group is used for cur frame.\\\\0: Register group A is used\\\\1: Register group B is used." + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: INTRA_FLAG + description: "Represents the type of current encoding frame.\\\\0: P frame\\\\1: I frame." + bitOffset: 10 + bitWidth: 1 + access: read-only + - register: + name: FRAME_CODE_LENGTH + description: Frame code byte length register. + addressOffset: 224 + size: 32 + fields: + - name: FRAME_CODE_LENGTH + description: Represents current frame code byte length. + bitOffset: 0 + bitWidth: 24 + access: read-only + - register: + name: DEBUG_INFO0 + description: Debug information register0. + addressOffset: 228 + size: 32 + fields: + - name: TOP_CTRL_INTER_DEBUG_STATE + description: Represents top_ctrl_inter module FSM info. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: TOP_CTRL_INTRA_DEBUG_STATE + description: Represents top_ctrl_intra module FSM info. + bitOffset: 4 + bitWidth: 3 + access: read-only + - name: P_I_CMP_DEBUG_STATE + description: Represents p_i_cmp module FSM info. + bitOffset: 7 + bitWidth: 3 + access: read-only + - name: MVD_DEBUG_STATE + description: Represents mvd module FSM info. + bitOffset: 10 + bitWidth: 3 + access: read-only + - name: MC_CHROMA_IP_DEBUG_STATE + description: Represents mc_chroma_ip module FSM info. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: INTRA_16X16_CHROMA_CTRL_DEBUG_STATE + description: Represents intra_16x16_chroma_ctrl module FSM info. + bitOffset: 14 + bitWidth: 4 + access: read-only + - name: INTRA_4X4_CTRL_DEBUG_STATE + description: Represents intra_4x4_ctrl module FSM info. + bitOffset: 18 + bitWidth: 4 + access: read-only + - name: INTRA_TOP_CTRL_DEBUG_STATE + description: Represents intra_top_ctrl module FSM info. + bitOffset: 22 + bitWidth: 3 + access: read-only + - name: IME_CTRL_DEBUG_STATE + description: Represents ime_ctrl module FSM info. + bitOffset: 25 + bitWidth: 3 + access: read-only + - register: + name: DEBUG_INFO1 + description: Debug information register1. + addressOffset: 232 + size: 32 + fields: + - name: FME_CTRL_DEBUG_STATE + description: Represents fme_ctrl module FSM info. + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: DECI_CALC_DEBUG_STATE + description: "Represents deci_calc module's FSM info. DEV use only." + bitOffset: 3 + bitWidth: 2 + access: read-only + - name: DB_DEBUG_STATE + description: Represents db module FSM info. + bitOffset: 5 + bitWidth: 3 + access: read-only + - name: CAVLC_ENC_DEBUG_STATE + description: Represents cavlc module enc FSM info. + bitOffset: 8 + bitWidth: 4 + access: read-only + - name: CAVLC_SCAN_DEBUG_STATE + description: Represents cavlc module scan FSM info. + bitOffset: 12 + bitWidth: 4 + access: read-only + - name: CAVLC_CTRL_DEBUG_STATE + description: Represents cavlc module ctrl FSM info. + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: BS_BUFFER_DEBUG_STATE + description: Represents bs buffer overflow info. + bitOffset: 18 + bitWidth: 1 + access: read-only + - register: + name: DEBUG_INFO2 + description: Debug information register2. + addressOffset: 236 + size: 32 + fields: + - name: P_RC_DONE_DEBUG_FLAG + description: "Represents p rate ctrl done status.\\\\0: not done\\\\1: done." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: P_P_I_CMP_DONE_DEBUG_FLAG + description: "Represents p p_i_cmp done status.\\\\0: not done\\\\1: done." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: P_MV_MERGE_DONE_DEBUG_FLAG + description: "Represents p mv merge done status.\\\\0: not done\\\\1: done." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: P_MOVE_ORI_DONE_DEBUG_FLAG + description: "Represents p move origin done status.\\\\0: not done\\\\1: done." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: P_MC_DONE_DEBUG_FLAG + description: "Represents p mc done status.\\\\0: not done\\\\1: done." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: P_IME_DONE_DEBUG_FLAG + description: "Represents p ime done status.\\\\0: not done\\\\1: done." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: P_GET_ORI_DONE_DEBUG_FLAG + description: "Represents p get origin done status.\\\\0: not done\\\\1: done." + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: P_FME_DONE_DEBUG_FLAG + description: "Represents p fme done status.\\\\0: not done\\\\1: done." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: P_FETCH_DONE_DEBUG_FLAG + description: "Represents p fetch done status.\\\\0: not done\\\\1: done." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: P_DB_DONE_DEBUG_FLAG + description: "Represents p deblocking done status.\\\\0: not done\\\\1: done." + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: P_BS_BUF_DONE_DEBUG_FLAG + description: "Represents p bitstream buffer done status.\\\\0: not done\\\\1: done." + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: REF_MOVE_2MB_LINE_DONE_DEBUG_FLAG + description: "Represents dma move 2 ref mb line done status.\\\\0: not done\\\\1: done." + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: I_P_I_CMP_DONE_DEBUG_FLAG + description: "Represents I p_i_cmp done status.\\\\0: not done\\\\1: done." + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: I_MOVE_ORI_DONE_DEBUG_FLAG + description: "Represents I move origin done status.\\\\0: not done\\\\1: done." + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: I_GET_ORI_DONE_DEBUG_FLAG + description: "Represents I get origin done status.\\\\0: not done\\\\1: done." + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: I_EC_DONE_DEBUG_FLAG + description: "Represents I encoder done status.\\\\0: not done\\\\1: done." + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: I_DB_DONE_DEBUG_FLAG + description: "Represents I deblocking done status.\\\\0: not done\\\\1: done." + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: I_BS_BUF_DONE_DEBUG_FLAG + description: "Represents I bitstream buffer done status.\\\\0: not done\\\\1: done." + bitOffset: 17 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: Version control register + addressOffset: 240 + size: 32 + resetValue: 36717120 + fields: + - name: LEDC_DATE + description: Configures the version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: H264_DMA + description: H264 Encoder (DMA) + groupName: H264_DMA + baseAddress: 1342861312 + addressBlock: + - offset: 0 + size: 988 + usage: registers + interrupt: + - name: H264_DMA2D_OUT_CH0 + value: 115 + - name: H264_DMA2D_OUT_CH1 + value: 116 + - name: H264_DMA2D_OUT_CH2 + value: 117 + - name: H264_DMA2D_OUT_CH3 + value: 118 + - name: H264_DMA2D_OUT_CH4 + value: 119 + - name: H264_DMA2D_IN_CH0 + value: 120 + - name: H264_DMA2D_IN_CH1 + value: 121 + - name: H264_DMA2D_IN_CH2 + value: 122 + - name: H264_DMA2D_IN_CH3 + value: 123 + - name: H264_DMA2D_IN_CH4 + value: 124 + - name: H264_DMA2D_IN_CH5 + value: 125 + registers: + - register: + name: OUT_CONF0_CH0 + description: TX CH0 config0 register + addressOffset: 0 + size: 32 + resetValue: 2 + fields: + - name: OUT_AUTO_WRBACK_CH0 + description: Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_EOF_MODE_CH0 + description: "EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUTDSCR_BURST_EN_CH0 + description: Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_ECC_AES_EN_CH0 + description: "When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUT_CHECK_OWNER_CH0 + description: Set this bit to enable checking the owner attribute of the link descriptor. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUT_MEM_BURST_LENGTH_CH0 + description: "Block size of Tx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: OUT_PAGE_BOUND_EN_CH0 + description: "Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: OUT_REORDER_EN_CH0 + description: "Enable TX channel 0 macro block reorder when set to 1, only channel0 have this selection" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: OUT_RST_CH0 + description: Write 1 then write 0 to this bit to reset TX channel + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: OUT_CMD_DISABLE_CH0 + description: Write 1 before reset and write 0 after reset + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: OUT_ARB_WEIGHT_OPT_DIS_CH0 + description: Set this bit to 1 to disable arbiter optimum weight function. + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: OUT_INT_RAW_CH0 + description: TX CH0 interrupt raw register + addressOffset: 4 + size: 32 + fields: + - name: OUT_DONE_CH0_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_EOF_CH0_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR_CH0_INT_RAW + description: "The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF_CH0_INT_RAW + description: The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF_L1_CH0_INT_RAW + description: The raw interrupt bit turns to high level when fifo is overflow. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF_L1_CH0_INT_RAW + description: The raw interrupt bit turns to high level when fifo is underflow. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF_L2_CH0_INT_RAW + description: The raw interrupt bit turns to high level when fifo is overflow. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF_L2_CH0_INT_RAW + description: The raw interrupt bit turns to high level when fifo is underflow. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_TASK_OVF_CH0_INT_RAW + description: The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: OUT_INT_ENA_CH0 + description: TX CH0 interrupt ena register + addressOffset: 8 + size: 32 + fields: + - name: OUT_DONE_CH0_INT_ENA + description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_EOF_CH0_INT_ENA + description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR_CH0_INT_ENA + description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF_CH0_INT_ENA + description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF_L1_CH0_INT_ENA + description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF_L1_CH0_INT_ENA + description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF_L2_CH0_INT_ENA + description: The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF_L2_CH0_INT_ENA + description: The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_TASK_OVF_CH0_INT_ENA + description: The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: OUT_INT_ST_CH0 + description: TX CH0 interrupt st register + addressOffset: 12 + size: 32 + fields: + - name: OUT_DONE_CH0_INT_ST + description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUT_EOF_CH0_INT_ST + description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: OUT_DSCR_ERR_CH0_INT_ST + description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: OUT_TOTAL_EOF_CH0_INT_ST + description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: OUTFIFO_OVF_L1_CH0_INT_ST + description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: OUTFIFO_UDF_L1_CH0_INT_ST + description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OUTFIFO_OVF_L2_CH0_INT_ST + description: The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUTFIFO_UDF_L2_CH0_INT_ST + description: The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OUT_DSCR_TASK_OVF_CH0_INT_ST + description: The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: OUT_INT_CLR_CH0 + description: TX CH0 interrupt clr register + addressOffset: 16 + size: 32 + fields: + - name: OUT_DONE_CH0_INT_CLR + description: Set this bit to clear the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: OUT_EOF_CH0_INT_CLR + description: Set this bit to clear the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: OUT_DSCR_ERR_CH0_INT_CLR + description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: OUT_TOTAL_EOF_CH0_INT_CLR + description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: OUTFIFO_OVF_L1_CH0_INT_CLR + description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: OUTFIFO_UDF_L1_CH0_INT_CLR + description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: OUTFIFO_OVF_L2_CH0_INT_CLR + description: Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: OUTFIFO_UDF_L2_CH0_INT_CLR + description: Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: OUT_DSCR_TASK_OVF_CH0_INT_CLR + description: Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: OUTFIFO_STATUS_CH0 + description: TX CH0 outfifo status register + addressOffset: 20 + size: 32 + resetValue: 131202 + fields: + - name: OUTFIFO_FULL_L2_CH0 + description: Tx FIFO full signal for Tx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY_L2_CH0 + description: Tx FIFO empty signal for Tx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: OUTFIFO_CNT_L2_CH0 + description: The register stores the byte number of the data in Tx FIFO for Tx channel 0. + bitOffset: 2 + bitWidth: 4 + access: read-only + - name: OUTFIFO_FULL_L1_CH0 + description: Tx FIFO full signal for Tx channel 0. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY_L1_CH0 + description: Tx FIFO empty signal for Tx channel 0. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OUTFIFO_CNT_L1_CH0 + description: The register stores the byte number of the data in Tx FIFO for Tx channel 0. + bitOffset: 8 + bitWidth: 5 + access: read-only + - name: OUTFIFO_FULL_L3_CH0 + description: Tx FIFO full signal for Tx channel 0. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY_L3_CH0 + description: Tx FIFO empty signal for Tx channel 0. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: OUTFIFO_CNT_L3_CH0 + description: The register stores the 8byte number of the data in Tx FIFO for Tx channel 0. + bitOffset: 18 + bitWidth: 2 + access: read-only + - register: + name: OUT_PUSH_CH0 + description: TX CH0 outfifo push register + addressOffset: 24 + size: 32 + fields: + - name: OUTFIFO_WDATA_CH0 + description: This register stores the data that need to be pushed into DMA Tx FIFO. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: OUTFIFO_PUSH_CH0 + description: Set this bit to push data into DMA Tx FIFO. + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: OUT_LINK_CONF_CH0 + description: TX CH0 out_link dscr ctrl register + addressOffset: 28 + size: 32 + resetValue: 8388608 + fields: + - name: OUTLINK_STOP_CH0 + description: Set this bit to stop dealing with the outlink descriptors. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: OUTLINK_START_CH0 + description: Set this bit to start dealing with the outlink descriptors. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: OUTLINK_RESTART_CH0 + description: Set this bit to restart a new outlink from the last address. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: OUTLINK_PARK_CH0 + description: "1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working." + bitOffset: 23 + bitWidth: 1 + access: read-only + - register: + name: OUT_LINK_ADDR_CH0 + description: TX CH0 out_link dscr addr register + addressOffset: 32 + size: 32 + fields: + - name: OUTLINK_ADDR_CH0 + description: "This register stores the first outlink descriptor's address." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: OUT_STATE_CH0 + description: TX CH0 state register + addressOffset: 36 + size: 32 + resetValue: 16777216 + fields: + - name: OUTLINK_DSCR_ADDR_CH0 + description: "This register stores the current outlink descriptor's address." + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: OUT_DSCR_STATE_CH0 + description: This register stores the current descriptor state machine state. + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: OUT_STATE_CH0 + description: This register stores the current control module state machine state. + bitOffset: 20 + bitWidth: 4 + access: read-only + - name: OUT_RESET_AVAIL_CH0 + description: This register indicate that if the channel reset is safety. + bitOffset: 24 + bitWidth: 1 + access: read-only + - register: + name: OUT_EOF_DES_ADDR_CH0 + description: TX CH0 eof des addr register + addressOffset: 40 + size: 32 + fields: + - name: OUT_EOF_DES_ADDR_CH0 + description: This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_CH0 + description: TX CH0 next dscr addr register + addressOffset: 44 + size: 32 + fields: + - name: OUTLINK_DSCR_CH0 + description: The address of the next outlink descriptor address y. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_BF0_CH0 + description: TX CH0 last dscr addr register + addressOffset: 48 + size: 32 + fields: + - name: OUTLINK_DSCR_BF0_CH0 + description: "The address of the last outlink descriptor's next address y-1." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_BF1_CH0 + description: TX CH0 second-to-last dscr addr register + addressOffset: 52 + size: 32 + fields: + - name: OUTLINK_DSCR_BF1_CH0 + description: "The address of the second-to-last outlink descriptor's next address y-2." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_ARB_CH0 + description: TX CH0 arb register + addressOffset: 60 + size: 32 + resetValue: 17 + fields: + - name: OUT_ARB_TOKEN_NUM_CH0 + description: Set the max number of token count of arbiter + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: EXTER_OUT_ARB_PRIORITY_CH0 + description: Set the priority of channel + bitOffset: 4 + bitWidth: 2 + access: read-write + - register: + name: OUT_RO_STATUS_CH0 + description: TX CH0 reorder status register + addressOffset: 64 + size: 32 + resetValue: 2048 + fields: + - name: OUTFIFO_RO_CNT_CH0 + description: The register stores the 8byte number of the data in reorder Tx FIFO for channel 0. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: OUT_RO_WR_STATE_CH0 + description: The register stores the state of read ram of reorder + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: OUT_RO_RD_STATE_CH0 + description: The register stores the state of write ram of reorder + bitOffset: 8 + bitWidth: 2 + access: read-only + - name: OUT_PIXEL_BYTE_CH0 + description: "the number of bytes contained in a pixel at TX channel 0: 1byte 1: 1.5bytes 2 : 2bytes 3: 2.5bytes 4: 3bytes 5: 4bytes" + bitOffset: 10 + bitWidth: 4 + access: read-only + - name: OUT_BURST_BLOCK_NUM_CH0 + description: the number of macro blocks contained in a burst of data at TX channel + bitOffset: 14 + bitWidth: 4 + access: read-only + - register: + name: OUT_RO_PD_CONF_CH0 + description: TX CH0 reorder power config register + addressOffset: 68 + size: 32 + resetValue: 32 + fields: + - name: OUT_RO_RAM_FORCE_PD_CH0 + description: dma reorder ram power down + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUT_RO_RAM_FORCE_PU_CH0 + description: dma reorder ram power up + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUT_RO_RAM_CLK_FO_CH0 + description: "1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA." + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: OUT_MODE_ENABLE_CH0 + description: tx CH0 mode enable register + addressOffset: 80 + size: 32 + fields: + - name: OUT_TEST_MODE_ENABLE_CH0 + description: "tx CH0 test mode enable.0 : H264_DMA work in normal mode.1 : H264_DMA work in test mode" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: OUT_MODE_YUV_CH0 + description: tx CH0 test mode yuv value register + addressOffset: 84 + size: 32 + fields: + - name: OUT_TEST_Y_VALUE_CH0 + description: tx CH0 test mode y value + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: OUT_TEST_U_VALUE_CH0 + description: tx CH0 test mode u value + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: OUT_TEST_V_VALUE_CH0 + description: tx CH0 test mode v value + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: OUT_ETM_CONF_CH0 + description: TX CH0 ETM config register + addressOffset: 104 + size: 32 + resetValue: 4 + fields: + - name: OUT_ETM_EN_CH0 + description: Set this bit to 1 to enable ETM task function + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_ETM_LOOP_EN_CH0 + description: "when this bit is 1, dscr can be processed after receiving a task" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_TASK_MAK_CH0 + description: ETM dscr_ready maximum cache numbers + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: OUT_BUF_LEN_CH0 + description: tx CH0 buf len register + addressOffset: 112 + size: 32 + fields: + - name: OUT_CMDFIFO_BUF_LEN_HB_CH0 + description: only for debug + bitOffset: 0 + bitWidth: 13 + access: read-only + - register: + name: OUT_FIFO_BCNT_CH0 + description: tx CH0 fifo byte cnt register + addressOffset: 116 + size: 32 + fields: + - name: OUT_CMDFIFO_OUTFIFO_BCNT_CH0 + description: only for debug + bitOffset: 0 + bitWidth: 10 + access: read-only + - register: + name: OUT_PUSH_BYTECNT_CH0 + description: tx CH0 push byte cnt register + addressOffset: 120 + size: 32 + resetValue: 255 + fields: + - name: OUT_CMDFIFO_PUSH_BYTECNT_CH0 + description: only for debug + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: OUT_XADDR_CH0 + description: tx CH0 xaddr register + addressOffset: 124 + size: 32 + fields: + - name: OUT_CMDFIFO_XADDR_CH0 + description: only for debug + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_CONF0_CH1 + description: TX CH1 config0 register + addressOffset: 256 + size: 32 + resetValue: 2 + fields: + - name: OUT_AUTO_WRBACK_CH1 + description: Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_EOF_MODE_CH1 + description: "EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUTDSCR_BURST_EN_CH1 + description: Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_ECC_AES_EN_CH1 + description: "When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUT_CHECK_OWNER_CH1 + description: Set this bit to enable checking the owner attribute of the link descriptor. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUT_MEM_BURST_LENGTH_CH1 + description: "Block size of Tx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 64 bytes" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: OUT_PAGE_BOUND_EN_CH1 + description: "Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: OUT_RST_CH1 + description: Write 1 then write 0 to this bit to reset TX channel + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: OUT_CMD_DISABLE_CH1 + description: Write 1 before reset and write 0 after reset + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: OUT_ARB_WEIGHT_OPT_DIS_CH1 + description: Set this bit to 1 to disable arbiter optimum weight function. + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: OUT_INT_RAW_CH1 + description: TX CH1 interrupt raw register + addressOffset: 260 + size: 32 + fields: + - name: OUT_DONE_CH1_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_EOF_CH1_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR_CH1_INT_RAW + description: "The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF_CH1_INT_RAW + description: The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF_L1_CH1_INT_RAW + description: The raw interrupt bit turns to high level when fifo is overflow. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF_L1_CH1_INT_RAW + description: The raw interrupt bit turns to high level when fifo is underflow. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF_L2_CH1_INT_RAW + description: The raw interrupt bit turns to high level when fifo is overflow. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF_L2_CH1_INT_RAW + description: The raw interrupt bit turns to high level when fifo is underflow. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_TASK_OVF_CH1_INT_RAW + description: The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: OUT_INT_ENA_CH1 + description: TX CH1 interrupt ena register + addressOffset: 264 + size: 32 + fields: + - name: OUT_DONE_CH1_INT_ENA + description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_EOF_CH1_INT_ENA + description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR_CH1_INT_ENA + description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF_CH1_INT_ENA + description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF_L1_CH1_INT_ENA + description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF_L1_CH1_INT_ENA + description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF_L2_CH1_INT_ENA + description: The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF_L2_CH1_INT_ENA + description: The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_TASK_OVF_CH1_INT_ENA + description: The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: OUT_INT_ST_CH1 + description: TX CH1 interrupt st register + addressOffset: 268 + size: 32 + fields: + - name: OUT_DONE_CH1_INT_ST + description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUT_EOF_CH1_INT_ST + description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: OUT_DSCR_ERR_CH1_INT_ST + description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: OUT_TOTAL_EOF_CH1_INT_ST + description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: OUTFIFO_OVF_L1_CH1_INT_ST + description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: OUTFIFO_UDF_L1_CH1_INT_ST + description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OUTFIFO_OVF_L2_CH1_INT_ST + description: The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUTFIFO_UDF_L2_CH1_INT_ST + description: The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OUT_DSCR_TASK_OVF_CH1_INT_ST + description: The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: OUT_INT_CLR_CH1 + description: TX CH1 interrupt clr register + addressOffset: 272 + size: 32 + fields: + - name: OUT_DONE_CH1_INT_CLR + description: Set this bit to clear the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: OUT_EOF_CH1_INT_CLR + description: Set this bit to clear the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: OUT_DSCR_ERR_CH1_INT_CLR + description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: OUT_TOTAL_EOF_CH1_INT_CLR + description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: OUTFIFO_OVF_L1_CH1_INT_CLR + description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: OUTFIFO_UDF_L1_CH1_INT_CLR + description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: OUTFIFO_OVF_L2_CH1_INT_CLR + description: Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: OUTFIFO_UDF_L2_CH1_INT_CLR + description: Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: OUT_DSCR_TASK_OVF_CH1_INT_CLR + description: Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: OUTFIFO_STATUS_CH1 + description: TX CH1 outfifo status register + addressOffset: 276 + size: 32 + resetValue: 131202 + fields: + - name: OUTFIFO_FULL_L2_CH1 + description: Tx FIFO full signal for Tx channel 1. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY_L2_CH1 + description: Tx FIFO empty signal for Tx channel 1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: OUTFIFO_CNT_L2_CH1 + description: The register stores the byte number of the data in Tx FIFO for Tx channel 1. + bitOffset: 2 + bitWidth: 4 + access: read-only + - name: OUTFIFO_FULL_L1_CH1 + description: Tx FIFO full signal for Tx channel 1. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY_L1_CH1 + description: Tx FIFO empty signal for Tx channel 1. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OUTFIFO_CNT_L1_CH1 + description: The register stores the byte number of the data in Tx FIFO for Tx channel 1. + bitOffset: 8 + bitWidth: 5 + access: read-only + - name: OUTFIFO_FULL_L3_CH1 + description: Tx FIFO full signal for Tx channel 1. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY_L3_CH1 + description: Tx FIFO empty signal for Tx channel 1. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: OUTFIFO_CNT_L3_CH1 + description: The register stores the byte number of the data in Tx FIFO for Tx channel 1. + bitOffset: 18 + bitWidth: 2 + access: read-only + - register: + name: OUT_PUSH_CH1 + description: TX CH1 outfifo push register + addressOffset: 280 + size: 32 + fields: + - name: OUTFIFO_WDATA_CH1 + description: This register stores the data that need to be pushed into DMA Tx FIFO. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: OUTFIFO_PUSH_CH1 + description: Set this bit to push data into DMA Tx FIFO. + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: OUT_LINK_CONF_CH1 + description: TX CH1 out_link dscr ctrl register + addressOffset: 284 + size: 32 + resetValue: 8388608 + fields: + - name: OUTLINK_STOP_CH1 + description: Set this bit to stop dealing with the outlink descriptors. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: OUTLINK_START_CH1 + description: Set this bit to start dealing with the outlink descriptors. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: OUTLINK_RESTART_CH1 + description: Set this bit to restart a new outlink from the last address. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: OUTLINK_PARK_CH1 + description: "1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working." + bitOffset: 23 + bitWidth: 1 + access: read-only + - register: + name: OUT_LINK_ADDR_CH1 + description: TX CH1 out_link dscr addr register + addressOffset: 288 + size: 32 + fields: + - name: OUTLINK_ADDR_CH1 + description: "This register stores the first outlink descriptor's address." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: OUT_STATE_CH1 + description: TX CH1 state register + addressOffset: 292 + size: 32 + resetValue: 16777216 + fields: + - name: OUTLINK_DSCR_ADDR_CH1 + description: "This register stores the current outlink descriptor's address." + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: OUT_DSCR_STATE_CH1 + description: This register stores the current descriptor state machine state. + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: OUT_STATE_CH1 + description: This register stores the current control module state machine state. + bitOffset: 20 + bitWidth: 4 + access: read-only + - name: OUT_RESET_AVAIL_CH1 + description: This register indicate that if the channel reset is safety. + bitOffset: 24 + bitWidth: 1 + access: read-only + - register: + name: OUT_EOF_DES_ADDR_CH1 + description: TX CH1 eof des addr register + addressOffset: 296 + size: 32 + fields: + - name: OUT_EOF_DES_ADDR_CH1 + description: This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_CH1 + description: TX CH1 next dscr addr register + addressOffset: 300 + size: 32 + fields: + - name: OUTLINK_DSCR_CH1 + description: The address of the next outlink descriptor address y. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_BF0_CH1 + description: TX CH1 last dscr addr register + addressOffset: 304 + size: 32 + fields: + - name: OUTLINK_DSCR_BF0_CH1 + description: "The address of the last outlink descriptor's next address y-1." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_BF1_CH1 + description: TX CH1 second-to-last dscr addr register + addressOffset: 308 + size: 32 + fields: + - name: OUTLINK_DSCR_BF1_CH1 + description: "The address of the second-to-last outlink descriptor's next address y-2." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_ARB_CH1 + description: TX CH1 arb register + addressOffset: 316 + size: 32 + resetValue: 65 + fields: + - name: OUT_ARB_TOKEN_NUM_CH1 + description: Set the max number of token count of arbiter + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: INTER_OUT_ARB_PRIORITY_CH1 + description: Set the priority of channel + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: OUT_ETM_CONF_CH1 + description: TX CH1 ETM config register + addressOffset: 360 + size: 32 + resetValue: 4 + fields: + - name: OUT_ETM_EN_CH1 + description: Set this bit to 1 to enable ETM task function + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_ETM_LOOP_EN_CH1 + description: "when this bit is 1, dscr can be processed after receiving a task" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_TASK_MAK_CH1 + description: ETM dscr_ready maximum cache numbers + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: OUT_BUF_LEN_CH1 + description: tx CH1 buf len register + addressOffset: 368 + size: 32 + fields: + - name: OUT_CMDFIFO_BUF_LEN_HB_CH1 + description: only for debug + bitOffset: 0 + bitWidth: 13 + access: read-only + - register: + name: OUT_FIFO_BCNT_CH1 + description: tx CH1 fifo byte cnt register + addressOffset: 372 + size: 32 + fields: + - name: OUT_CMDFIFO_OUTFIFO_BCNT_CH1 + description: only for debug + bitOffset: 0 + bitWidth: 10 + access: read-only + - register: + name: OUT_PUSH_BYTECNT_CH1 + description: tx CH1 push byte cnt register + addressOffset: 376 + size: 32 + resetValue: 255 + fields: + - name: OUT_CMDFIFO_PUSH_BYTECNT_CH1 + description: only for debug + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: OUT_XADDR_CH1 + description: tx CH1 xaddr register + addressOffset: 380 + size: 32 + fields: + - name: OUT_CMDFIFO_XADDR_CH1 + description: only for debug + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_CONF0_CH2 + description: TX CH2 config0 register + addressOffset: 512 + size: 32 + resetValue: 2 + fields: + - name: OUT_AUTO_WRBACK_CH2 + description: Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_EOF_MODE_CH2 + description: "EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUTDSCR_BURST_EN_CH2 + description: Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_ECC_AES_EN_CH2 + description: "When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUT_CHECK_OWNER_CH2 + description: Set this bit to enable checking the owner attribute of the link descriptor. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUT_MEM_BURST_LENGTH_CH2 + description: "Block size of Tx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: OUT_PAGE_BOUND_EN_CH2 + description: "Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: OUT_RST_CH2 + description: Write 1 then write 0 to this bit to reset TX channel + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: OUT_CMD_DISABLE_CH2 + description: Write 1 before reset and write 0 after reset + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: OUT_ARB_WEIGHT_OPT_DIS_CH2 + description: Set this bit to 1 to disable arbiter optimum weight function. + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: OUT_INT_RAW_CH2 + description: TX CH2 interrupt raw register + addressOffset: 516 + size: 32 + fields: + - name: OUT_DONE_CH2_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_EOF_CH2_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR_CH2_INT_RAW + description: "The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF_CH2_INT_RAW + description: The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF_L1_CH2_INT_RAW + description: The raw interrupt bit turns to high level when fifo is overflow. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF_L1_CH2_INT_RAW + description: The raw interrupt bit turns to high level when fifo is underflow. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF_L2_CH2_INT_RAW + description: The raw interrupt bit turns to high level when fifo is overflow. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF_L2_CH2_INT_RAW + description: The raw interrupt bit turns to high level when fifo is underflow. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_TASK_OVF_CH2_INT_RAW + description: The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: OUT_INT_ENA_CH2 + description: TX CH2 interrupt ena register + addressOffset: 520 + size: 32 + fields: + - name: OUT_DONE_CH2_INT_ENA + description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_EOF_CH2_INT_ENA + description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR_CH2_INT_ENA + description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF_CH2_INT_ENA + description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF_L1_CH2_INT_ENA + description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF_L1_CH2_INT_ENA + description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF_L2_CH2_INT_ENA + description: The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF_L2_CH2_INT_ENA + description: The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_TASK_OVF_CH2_INT_ENA + description: The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: OUT_INT_ST_CH2 + description: TX CH2 interrupt st register + addressOffset: 524 + size: 32 + fields: + - name: OUT_DONE_CH2_INT_ST + description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUT_EOF_CH2_INT_ST + description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: OUT_DSCR_ERR_CH2_INT_ST + description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: OUT_TOTAL_EOF_CH2_INT_ST + description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: OUTFIFO_OVF_L1_CH2_INT_ST + description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: OUTFIFO_UDF_L1_CH2_INT_ST + description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OUTFIFO_OVF_L2_CH2_INT_ST + description: The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUTFIFO_UDF_L2_CH2_INT_ST + description: The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OUT_DSCR_TASK_OVF_CH2_INT_ST + description: The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: OUT_INT_CLR_CH2 + description: TX CH2 interrupt clr register + addressOffset: 528 + size: 32 + fields: + - name: OUT_DONE_CH2_INT_CLR + description: Set this bit to clear the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: OUT_EOF_CH2_INT_CLR + description: Set this bit to clear the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: OUT_DSCR_ERR_CH2_INT_CLR + description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: OUT_TOTAL_EOF_CH2_INT_CLR + description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: OUTFIFO_OVF_L1_CH2_INT_CLR + description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: OUTFIFO_UDF_L1_CH2_INT_CLR + description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: OUTFIFO_OVF_L2_CH2_INT_CLR + description: Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: OUTFIFO_UDF_L2_CH2_INT_CLR + description: Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: OUT_DSCR_TASK_OVF_CH2_INT_CLR + description: Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: OUTFIFO_STATUS_CH2 + description: TX CH2 outfifo status register + addressOffset: 532 + size: 32 + resetValue: 131202 + fields: + - name: OUTFIFO_FULL_L2_CH2 + description: Tx FIFO full signal for Tx channel 2. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY_L2_CH2 + description: Tx FIFO empty signal for Tx channel 2. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: OUTFIFO_CNT_L2_CH2 + description: The register stores the byte number of the data in Tx FIFO for Tx channel 2. + bitOffset: 2 + bitWidth: 4 + access: read-only + - name: OUTFIFO_FULL_L1_CH2 + description: Tx FIFO full signal for Tx channel 2. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY_L1_CH2 + description: Tx FIFO empty signal for Tx channel 2. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OUTFIFO_CNT_L1_CH2 + description: The register stores the byte number of the data in Tx FIFO for Tx channel 2. + bitOffset: 8 + bitWidth: 5 + access: read-only + - name: OUTFIFO_FULL_L3_CH2 + description: Tx FIFO full signal for Tx channel 2. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY_L3_CH2 + description: Tx FIFO empty signal for Tx channel 2. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: OUTFIFO_CNT_L3_CH2 + description: The register stores the byte number of the data in Tx FIFO for Tx channel 2. + bitOffset: 18 + bitWidth: 2 + access: read-only + - register: + name: OUT_PUSH_CH2 + description: TX CH2 outfifo push register + addressOffset: 536 + size: 32 + fields: + - name: OUTFIFO_WDATA_CH2 + description: This register stores the data that need to be pushed into DMA Tx FIFO. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: OUTFIFO_PUSH_CH2 + description: Set this bit to push data into DMA Tx FIFO. + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: OUT_LINK_CONF_CH2 + description: TX CH2 out_link dscr ctrl register + addressOffset: 540 + size: 32 + resetValue: 8388608 + fields: + - name: OUTLINK_STOP_CH2 + description: Set this bit to stop dealing with the outlink descriptors. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: OUTLINK_START_CH2 + description: Set this bit to start dealing with the outlink descriptors. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: OUTLINK_RESTART_CH2 + description: Set this bit to restart a new outlink from the last address. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: OUTLINK_PARK_CH2 + description: "1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working." + bitOffset: 23 + bitWidth: 1 + access: read-only + - register: + name: OUT_LINK_ADDR_CH2 + description: TX CH2 out_link dscr addr register + addressOffset: 544 + size: 32 + fields: + - name: OUTLINK_ADDR_CH2 + description: "This register stores the first outlink descriptor's address." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: OUT_STATE_CH2 + description: TX CH2 state register + addressOffset: 548 + size: 32 + resetValue: 16777216 + fields: + - name: OUTLINK_DSCR_ADDR_CH2 + description: "This register stores the current outlink descriptor's address." + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: OUT_DSCR_STATE_CH2 + description: This register stores the current descriptor state machine state. + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: OUT_STATE_CH2 + description: This register stores the current control module state machine state. + bitOffset: 20 + bitWidth: 4 + access: read-only + - name: OUT_RESET_AVAIL_CH2 + description: This register indicate that if the channel reset is safety. + bitOffset: 24 + bitWidth: 1 + access: read-only + - register: + name: OUT_EOF_DES_ADDR_CH2 + description: TX CH2 eof des addr register + addressOffset: 552 + size: 32 + fields: + - name: OUT_EOF_DES_ADDR_CH2 + description: This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_CH2 + description: TX CH2 next dscr addr register + addressOffset: 556 + size: 32 + fields: + - name: OUTLINK_DSCR_CH2 + description: The address of the next outlink descriptor address y. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_BF0_CH2 + description: TX CH2 last dscr addr register + addressOffset: 560 + size: 32 + fields: + - name: OUTLINK_DSCR_BF0_CH2 + description: "The address of the last outlink descriptor's next address y-1." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_BF1_CH2 + description: TX CH2 second-to-last dscr addr register + addressOffset: 564 + size: 32 + fields: + - name: OUTLINK_DSCR_BF1_CH2 + description: "The address of the second-to-last outlink descriptor's next address y-2." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_ARB_CH2 + description: TX CH2 arb register + addressOffset: 572 + size: 32 + resetValue: 65 + fields: + - name: OUT_ARB_TOKEN_NUM_CH2 + description: Set the max number of token count of arbiter + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: INTER_OUT_ARB_PRIORITY_CH2 + description: Set the priority of channel + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: OUT_ETM_CONF_CH2 + description: TX CH2 ETM config register + addressOffset: 616 + size: 32 + resetValue: 4 + fields: + - name: OUT_ETM_EN_CH2 + description: Set this bit to 1 to enable ETM task function + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_ETM_LOOP_EN_CH2 + description: "when this bit is 1, dscr can be processed after receiving a task" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_TASK_MAK_CH2 + description: ETM dscr_ready maximum cache numbers + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: OUT_BUF_LEN_CH2 + description: tx CH2 buf len register + addressOffset: 624 + size: 32 + fields: + - name: OUT_CMDFIFO_BUF_LEN_HB_CH2 + description: only for debug + bitOffset: 0 + bitWidth: 13 + access: read-only + - register: + name: OUT_FIFO_BCNT_CH2 + description: tx CH2 fifo byte cnt register + addressOffset: 628 + size: 32 + fields: + - name: OUT_CMDFIFO_OUTFIFO_BCNT_CH2 + description: only for debug + bitOffset: 0 + bitWidth: 10 + access: read-only + - register: + name: OUT_PUSH_BYTECNT_CH2 + description: tx CH2 push byte cnt register + addressOffset: 632 + size: 32 + resetValue: 255 + fields: + - name: OUT_CMDFIFO_PUSH_BYTECNT_CH2 + description: only for debug + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: OUT_XADDR_CH2 + description: tx CH2 xaddr register + addressOffset: 636 + size: 32 + fields: + - name: OUT_CMDFIFO_XADDR_CH2 + description: only for debug + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_CONF0_CH3 + description: TX CH3 config0 register + addressOffset: 768 + size: 32 + resetValue: 2 + fields: + - name: OUT_AUTO_WRBACK_CH3 + description: Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_EOF_MODE_CH3 + description: "EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUTDSCR_BURST_EN_CH3 + description: Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_ECC_AES_EN_CH3 + description: "When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUT_CHECK_OWNER_CH3 + description: Set this bit to enable checking the owner attribute of the link descriptor. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUT_MEM_BURST_LENGTH_CH3 + description: "Block size of Tx channel 3. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: OUT_PAGE_BOUND_EN_CH3 + description: "Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: OUT_ARB_WEIGHT_OPT_DIS_CH3 + description: Set this bit to 1 to disable arbiter optimum weight function. + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: OUT_INT_RAW_CH3 + description: TX CH3 interrupt raw register + addressOffset: 772 + size: 32 + fields: + - name: OUT_DONE_CH3_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_EOF_CH3_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR_CH3_INT_RAW + description: "The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF_CH3_INT_RAW + description: The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF_L1_CH3_INT_RAW + description: The raw interrupt bit turns to high level when fifo is overflow. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF_L1_CH3_INT_RAW + description: The raw interrupt bit turns to high level when fifo is underflow. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF_L2_CH3_INT_RAW + description: The raw interrupt bit turns to high level when fifo is overflow. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF_L2_CH3_INT_RAW + description: The raw interrupt bit turns to high level when fifo is underflow. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_TASK_OVF_CH3_INT_RAW + description: The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: OUT_INT_ENA_CH3 + description: TX CH3 interrupt ena register + addressOffset: 776 + size: 32 + fields: + - name: OUT_DONE_CH3_INT_ENA + description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_EOF_CH3_INT_ENA + description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR_CH3_INT_ENA + description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF_CH3_INT_ENA + description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF_L1_CH3_INT_ENA + description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF_L1_CH3_INT_ENA + description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF_L2_CH3_INT_ENA + description: The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF_L2_CH3_INT_ENA + description: The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_TASK_OVF_CH3_INT_ENA + description: The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: OUT_INT_ST_CH3 + description: TX CH3 interrupt st register + addressOffset: 780 + size: 32 + fields: + - name: OUT_DONE_CH3_INT_ST + description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUT_EOF_CH3_INT_ST + description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: OUT_DSCR_ERR_CH3_INT_ST + description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: OUT_TOTAL_EOF_CH3_INT_ST + description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: OUTFIFO_OVF_L1_CH3_INT_ST + description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: OUTFIFO_UDF_L1_CH3_INT_ST + description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OUTFIFO_OVF_L2_CH3_INT_ST + description: The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUTFIFO_UDF_L2_CH3_INT_ST + description: The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OUT_DSCR_TASK_OVF_CH3_INT_ST + description: The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: OUT_INT_CLR_CH3 + description: TX CH3 interrupt clr register + addressOffset: 784 + size: 32 + fields: + - name: OUT_DONE_CH3_INT_CLR + description: Set this bit to clear the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: OUT_EOF_CH3_INT_CLR + description: Set this bit to clear the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: OUT_DSCR_ERR_CH3_INT_CLR + description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: OUT_TOTAL_EOF_CH3_INT_CLR + description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: OUTFIFO_OVF_L1_CH3_INT_CLR + description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: OUTFIFO_UDF_L1_CH3_INT_CLR + description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: OUTFIFO_OVF_L2_CH3_INT_CLR + description: Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: OUTFIFO_UDF_L2_CH3_INT_CLR + description: Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: OUT_DSCR_TASK_OVF_CH3_INT_CLR + description: Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: OUTFIFO_STATUS_CH3 + description: TX CH3 outfifo status register + addressOffset: 788 + size: 32 + resetValue: 131202 + fields: + - name: OUTFIFO_FULL_L2_CH3 + description: Tx FIFO full signal for Tx channel 2. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY_L2_CH3 + description: Tx FIFO empty signal for Tx channel 2. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: OUTFIFO_CNT_L2_CH3 + description: The register stores the byte number of the data in Tx FIFO for Tx channel 2. + bitOffset: 2 + bitWidth: 4 + access: read-only + - name: OUTFIFO_FULL_L1_CH3 + description: Tx FIFO full signal for Tx channel 2. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY_L1_CH3 + description: Tx FIFO empty signal for Tx channel 2. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OUTFIFO_CNT_L1_CH3 + description: The register stores the byte number of the data in Tx FIFO for Tx channel 2. + bitOffset: 8 + bitWidth: 5 + access: read-only + - name: OUTFIFO_FULL_L3_CH3 + description: Tx FIFO full signal for Tx channel 2. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY_L3_CH3 + description: Tx FIFO empty signal for Tx channel 2. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: OUTFIFO_CNT_L3_CH3 + description: The register stores the byte number of the data in Tx FIFO for Tx channel 2. + bitOffset: 18 + bitWidth: 2 + access: read-only + - register: + name: OUT_PUSH_CH3 + description: TX CH3 outfifo push register + addressOffset: 792 + size: 32 + fields: + - name: OUTFIFO_WDATA_CH3 + description: This register stores the data that need to be pushed into DMA Tx FIFO. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: OUTFIFO_PUSH_CH3 + description: Set this bit to push data into DMA Tx FIFO. + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: OUT_LINK_CONF_CH3 + description: TX CH3 out_link dscr ctrl register + addressOffset: 796 + size: 32 + resetValue: 8388608 + fields: + - name: OUTLINK_STOP_CH3 + description: Set this bit to stop dealing with the outlink descriptors. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: OUTLINK_START_CH3 + description: Set this bit to start dealing with the outlink descriptors. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: OUTLINK_RESTART_CH3 + description: Set this bit to restart a new outlink from the last address. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: OUTLINK_PARK_CH3 + description: "1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working." + bitOffset: 23 + bitWidth: 1 + access: read-only + - register: + name: OUT_LINK_ADDR_CH3 + description: TX CH3 out_link dscr addr register + addressOffset: 800 + size: 32 + fields: + - name: OUTLINK_ADDR_CH3 + description: "This register stores the first outlink descriptor's address." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: OUT_STATE_CH3 + description: TX CH3 state register + addressOffset: 804 + size: 32 + fields: + - name: OUTLINK_DSCR_ADDR_CH3 + description: "This register stores the current outlink descriptor's address." + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: OUT_DSCR_STATE_CH3 + description: This register stores the current descriptor state machine state. + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: OUT_STATE_CH3 + description: This register stores the current control module state machine state. + bitOffset: 20 + bitWidth: 4 + access: read-only + - register: + name: OUT_EOF_DES_ADDR_CH3 + description: TX CH3 eof des addr register + addressOffset: 808 + size: 32 + fields: + - name: OUT_EOF_DES_ADDR_CH3 + description: This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_CH3 + description: TX CH3 next dscr addr register + addressOffset: 812 + size: 32 + fields: + - name: OUTLINK_DSCR_CH3 + description: The address of the next outlink descriptor address y. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_BF0_CH3 + description: TX CH3 last dscr addr register + addressOffset: 816 + size: 32 + fields: + - name: OUTLINK_DSCR_BF0_CH3 + description: "The address of the last outlink descriptor's next address y-1." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_BF1_CH3 + description: TX CH3 second-to-last dscr addr register + addressOffset: 820 + size: 32 + fields: + - name: OUTLINK_DSCR_BF1_CH3 + description: "The address of the second-to-last outlink descriptor's next address y-2." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_ARB_CH3 + description: TX CH3 arb register + addressOffset: 828 + size: 32 + resetValue: 17 + fields: + - name: OUT_ARB_TOKEN_NUM_CH3 + description: Set the max number of token count of arbiter + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: EXTER_OUT_ARB_PRIORITY_CH3 + description: Set the priority of channel + bitOffset: 4 + bitWidth: 2 + access: read-write + - register: + name: OUT_ETM_CONF_CH3 + description: TX CH3 ETM config register + addressOffset: 872 + size: 32 + resetValue: 4 + fields: + - name: OUT_ETM_EN_CH3 + description: Set this bit to 1 to enable ETM task function + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_ETM_LOOP_EN_CH3 + description: "when this bit is 1, dscr can be processed after receiving a task" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_TASK_MAK_CH3 + description: ETM dscr_ready maximum cache numbers + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: OUT_BUF_LEN_CH3 + description: tx CH3 buf len register + addressOffset: 880 + size: 32 + fields: + - name: OUT_CMDFIFO_BUF_LEN_HB_CH3 + description: only for debug + bitOffset: 0 + bitWidth: 13 + access: read-only + - register: + name: OUT_FIFO_BCNT_CH3 + description: tx CH3 fifo byte cnt register + addressOffset: 884 + size: 32 + fields: + - name: OUT_CMDFIFO_OUTFIFO_BCNT_CH3 + description: only for debug + bitOffset: 0 + bitWidth: 10 + access: read-only + - register: + name: OUT_PUSH_BYTECNT_CH3 + description: tx CH3 push byte cnt register + addressOffset: 888 + size: 32 + resetValue: 63 + fields: + - name: OUT_CMDFIFO_PUSH_BYTECNT_CH3 + description: only for debug + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: OUT_XADDR_CH3 + description: tx CH3 xaddr register + addressOffset: 892 + size: 32 + fields: + - name: OUT_CMDFIFO_XADDR_CH3 + description: only for debug + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_BLOCK_BUF_LEN_CH3 + description: tx CH3 block buf len register + addressOffset: 896 + size: 32 + fields: + - name: OUT_BLOCK_BUF_LEN_CH3 + description: only for debug + bitOffset: 0 + bitWidth: 28 + access: read-only + - register: + name: OUT_CONF0_CH4 + description: TX CH4 config0 register + addressOffset: 1024 + size: 32 + resetValue: 2 + fields: + - name: OUT_AUTO_WRBACK_CH4 + description: Set this bit to enable automatic outlink-writeback when all the data pointed by outlink descriptor has been received. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_EOF_MODE_CH4 + description: "EOF flag generation mode when receiving data. 1: EOF flag for Tx channel 0 is generated when data need to read has been popped from FIFO in DMA" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUTDSCR_BURST_EN_CH4 + description: Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_ECC_AES_EN_CH4 + description: "When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUT_CHECK_OWNER_CH4 + description: Set this bit to enable checking the owner attribute of the link descriptor. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUT_MEM_BURST_LENGTH_CH4 + description: "Block size of Tx channel 4. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: OUT_PAGE_BOUND_EN_CH4 + description: "Set this bit to 1 to make sure AXI read data don't cross the address boundary which define by mem_burst_length" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: OUT_ARB_WEIGHT_OPT_DIS_CH4 + description: Set this bit to 1 to disable arbiter optimum weight function. + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: OUT_INT_RAW_CH4 + description: TX CH4 interrupt raw register + addressOffset: 1028 + size: 32 + fields: + - name: OUT_DONE_CH4_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_EOF_CH4_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR_CH4_INT_RAW + description: "The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF_CH4_INT_RAW + description: The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF_L1_CH4_INT_RAW + description: The raw interrupt bit turns to high level when fifo is overflow. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF_L1_CH4_INT_RAW + description: The raw interrupt bit turns to high level when fifo is underflow. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF_L2_CH4_INT_RAW + description: The raw interrupt bit turns to high level when fifo is overflow. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF_L2_CH4_INT_RAW + description: The raw interrupt bit turns to high level when fifo is underflow. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_TASK_OVF_CH4_INT_RAW + description: The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: OUT_INT_ENA_CH4 + description: TX CH4 interrupt ena register + addressOffset: 1032 + size: 32 + fields: + - name: OUT_DONE_CH4_INT_ENA + description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_EOF_CH4_INT_ENA + description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR_CH4_INT_ENA + description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF_CH4_INT_ENA + description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF_L1_CH4_INT_ENA + description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF_L1_CH4_INT_ENA + description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF_L2_CH4_INT_ENA + description: The interrupt enable bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF_L2_CH4_INT_ENA + description: The interrupt enable bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_TASK_OVF_CH4_INT_ENA + description: The interrupt enable bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: OUT_INT_ST_CH4 + description: TX CH4 interrupt st register + addressOffset: 1036 + size: 32 + fields: + - name: OUT_DONE_CH4_INT_ST + description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUT_EOF_CH4_INT_ST + description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: OUT_DSCR_ERR_CH4_INT_ST + description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: OUT_TOTAL_EOF_CH4_INT_ST + description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: OUTFIFO_OVF_L1_CH4_INT_ST + description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: OUTFIFO_UDF_L1_CH4_INT_ST + description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OUTFIFO_OVF_L2_CH4_INT_ST + description: The raw interrupt status bit for the OUTFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUTFIFO_UDF_L2_CH4_INT_ST + description: The raw interrupt status bit for the OUTFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OUT_DSCR_TASK_OVF_CH4_INT_ST + description: The raw interrupt status bit for the OUT_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: OUT_INT_CLR_CH4 + description: TX CH4 interrupt clr register + addressOffset: 1040 + size: 32 + fields: + - name: OUT_DONE_CH4_INT_CLR + description: Set this bit to clear the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: OUT_EOF_CH4_INT_CLR + description: Set this bit to clear the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: OUT_DSCR_ERR_CH4_INT_CLR + description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: OUT_TOTAL_EOF_CH4_INT_CLR + description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: OUTFIFO_OVF_L1_CH4_INT_CLR + description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: OUTFIFO_UDF_L1_CH4_INT_CLR + description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: OUTFIFO_OVF_L2_CH4_INT_CLR + description: Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: OUTFIFO_UDF_L2_CH4_INT_CLR + description: Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: OUT_DSCR_TASK_OVF_CH4_INT_CLR + description: Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: OUTFIFO_STATUS_CH4 + description: TX CH4 outfifo status register + addressOffset: 1044 + size: 32 + resetValue: 131202 + fields: + - name: OUTFIFO_FULL_L2_CH4 + description: Tx FIFO full signal for Tx channel 2. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY_L2_CH4 + description: Tx FIFO empty signal for Tx channel 2. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: OUTFIFO_CNT_L2_CH4 + description: The register stores the byte number of the data in Tx FIFO for Tx channel 2. + bitOffset: 2 + bitWidth: 4 + access: read-only + - name: OUTFIFO_FULL_L1_CH4 + description: Tx FIFO full signal for Tx channel 2. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY_L1_CH4 + description: Tx FIFO empty signal for Tx channel 2. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OUTFIFO_CNT_L1_CH4 + description: The register stores the byte number of the data in Tx FIFO for Tx channel 2. + bitOffset: 8 + bitWidth: 5 + access: read-only + - name: OUTFIFO_FULL_L3_CH4 + description: Tx FIFO full signal for Tx channel 2. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY_L3_CH4 + description: Tx FIFO empty signal for Tx channel 2. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: OUTFIFO_CNT_L3_CH4 + description: The register stores the byte number of the data in Tx FIFO for Tx channel 2. + bitOffset: 18 + bitWidth: 2 + access: read-only + - register: + name: OUT_PUSH_CH4 + description: TX CH4 outfifo push register + addressOffset: 1048 + size: 32 + fields: + - name: OUTFIFO_WDATA_CH4 + description: This register stores the data that need to be pushed into DMA Tx FIFO. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: OUTFIFO_PUSH_CH4 + description: Set this bit to push data into DMA Tx FIFO. + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: OUT_LINK_CONF_CH4 + description: TX CH4 out_link dscr ctrl register + addressOffset: 1052 + size: 32 + resetValue: 8388608 + fields: + - name: OUTLINK_STOP_CH4 + description: Set this bit to stop dealing with the outlink descriptors. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: OUTLINK_START_CH4 + description: Set this bit to start dealing with the outlink descriptors. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: OUTLINK_RESTART_CH4 + description: Set this bit to restart a new outlink from the last address. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: OUTLINK_PARK_CH4 + description: "1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working." + bitOffset: 23 + bitWidth: 1 + access: read-only + - register: + name: OUT_LINK_ADDR_CH4 + description: TX CH4 out_link dscr addr register + addressOffset: 1056 + size: 32 + fields: + - name: OUTLINK_ADDR_CH4 + description: "This register stores the first outlink descriptor's address." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: OUT_STATE_CH4 + description: TX CH4 state register + addressOffset: 1060 + size: 32 + fields: + - name: OUTLINK_DSCR_ADDR_CH4 + description: "This register stores the current outlink descriptor's address." + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: OUT_DSCR_STATE_CH4 + description: This register stores the current descriptor state machine state. + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: OUT_STATE_CH4 + description: This register stores the current control module state machine state. + bitOffset: 20 + bitWidth: 4 + access: read-only + - register: + name: OUT_EOF_DES_ADDR_CH4 + description: TX CH4 eof des addr register + addressOffset: 1064 + size: 32 + fields: + - name: OUT_EOF_DES_ADDR_CH4 + description: This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_CH4 + description: TX CH4 next dscr addr register + addressOffset: 1068 + size: 32 + fields: + - name: OUTLINK_DSCR_CH4 + description: The address of the next outlink descriptor address y. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_BF0_CH4 + description: TX CH4 last dscr addr register + addressOffset: 1072 + size: 32 + fields: + - name: OUTLINK_DSCR_BF0_CH4 + description: "The address of the last outlink descriptor's next address y-1." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_BF1_CH4 + description: TX CH4 second-to-last dscr addr register + addressOffset: 1076 + size: 32 + fields: + - name: OUTLINK_DSCR_BF1_CH4 + description: "The address of the second-to-last outlink descriptor's next address y-2." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_ARB_CH4 + description: TX CH4 arb register + addressOffset: 1084 + size: 32 + resetValue: 17 + fields: + - name: OUT_ARB_TOKEN_NUM_CH4 + description: Set the max number of token count of arbiter + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: EXTER_OUT_ARB_PRIORITY_CH4 + description: Set the priority of channel + bitOffset: 4 + bitWidth: 2 + access: read-write + - register: + name: OUT_ETM_CONF_CH4 + description: TX CH4 ETM config register + addressOffset: 1128 + size: 32 + resetValue: 4 + fields: + - name: OUT_ETM_EN_CH4 + description: Set this bit to 1 to enable ETM task function + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_ETM_LOOP_EN_CH4 + description: "when this bit is 1, dscr can be processed after receiving a task" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_TASK_MAK_CH4 + description: ETM dscr_ready maximum cache numbers + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: OUT_BUF_LEN_CH4 + description: tx CH4 buf len register + addressOffset: 1136 + size: 32 + fields: + - name: OUT_CMDFIFO_BUF_LEN_HB_CH4 + description: only for debug + bitOffset: 0 + bitWidth: 13 + access: read-only + - register: + name: OUT_FIFO_BCNT_CH4 + description: tx CH4 fifo byte cnt register + addressOffset: 1140 + size: 32 + fields: + - name: OUT_CMDFIFO_OUTFIFO_BCNT_CH4 + description: only for debug + bitOffset: 0 + bitWidth: 10 + access: read-only + - register: + name: OUT_PUSH_BYTECNT_CH4 + description: tx CH4 push byte cnt register + addressOffset: 1144 + size: 32 + resetValue: 63 + fields: + - name: OUT_CMDFIFO_PUSH_BYTECNT_CH4 + description: only for debug + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: OUT_XADDR_CH4 + description: tx CH4 xaddr register + addressOffset: 1148 + size: 32 + fields: + - name: OUT_CMDFIFO_XADDR_CH4 + description: only for debug + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_BLOCK_BUF_LEN_CH4 + description: tx CH4 block buf len register + addressOffset: 1152 + size: 32 + fields: + - name: OUT_BLOCK_BUF_LEN_CH4 + description: only for debug + bitOffset: 0 + bitWidth: 28 + access: read-only + - register: + name: IN_CONF0_CH0 + description: RX CH0 config0 register + addressOffset: 1280 + size: 32 + fields: + - name: INDSCR_BURST_EN_CH0 + description: Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_ECC_AES_EN_CH0 + description: "When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: IN_CHECK_OWNER_CH0 + description: Set this bit to enable checking the owner attribute of the link descriptor. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IN_MEM_BURST_LENGTH_CH0 + description: "Block size of Rx channel 0. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: IN_PAGE_BOUND_EN_CH0 + description: "Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: IN_RST_CH0 + description: Write 1 then write 0 to this bit to reset Rx channel + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: IN_CMD_DISABLE_CH0 + description: Write 1 before reset and write 0 after reset + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: IN_ARB_WEIGHT_OPT_DIS_CH0 + description: Set this bit to 1 to disable arbiter optimum weight function. + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: IN_INT_RAW_CH0 + description: RX CH0 interrupt raw register + addressOffset: 1284 + size: 32 + fields: + - name: IN_DONE_CH0_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF_CH0_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF_CH0_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR_CH0_INT_RAW + description: "The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L1_CH0_INT_RAW + description: The raw interrupt bit turns to high level when fifo of Rx channel is overflow. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L1_CH0_INT_RAW + description: The raw interrupt bit turns to high level when fifo of Rx channel is underflow. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L2_CH0_INT_RAW + description: The raw interrupt bit turns to high level when fifo of Rx channel is overflow. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L2_CH0_INT_RAW + description: The raw interrupt bit turns to high level when fifo of Rx channel is underflow. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY_CH0_INT_RAW + description: The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: IN_DSCR_TASK_OVF_CH0_INT_RAW + description: The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: IN_INT_ENA_CH0 + description: RX CH0 interrupt ena register + addressOffset: 1288 + size: 32 + fields: + - name: IN_DONE_CH0_INT_ENA + description: The interrupt enable bit for the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF_CH0_INT_ENA + description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF_CH0_INT_ENA + description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR_CH0_INT_ENA + description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L1_CH0_INT_ENA + description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L1_CH0_INT_ENA + description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L2_CH0_INT_ENA + description: The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L2_CH0_INT_ENA + description: The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY_CH0_INT_ENA + description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: IN_DSCR_TASK_OVF_CH0_INT_ENA + description: The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: IN_INT_ST_CH0 + description: RX CH0 interrupt st register + addressOffset: 1292 + size: 32 + fields: + - name: IN_DONE_CH0_INT_ST + description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: IN_SUC_EOF_CH0_INT_ST + description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: IN_ERR_EOF_CH0_INT_ST + description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: IN_DSCR_ERR_CH0_INT_ST + description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: INFIFO_OVF_L1_CH0_INT_ST + description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: INFIFO_UDF_L1_CH0_INT_ST + description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: INFIFO_OVF_L2_CH0_INT_ST + description: The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: INFIFO_UDF_L2_CH0_INT_ST + description: The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IN_DSCR_EMPTY_CH0_INT_ST + description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: IN_DSCR_TASK_OVF_CH0_INT_ST + description: The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - register: + name: IN_INT_CLR_CH0 + description: RX CH0 interrupt clr register + addressOffset: 1296 + size: 32 + fields: + - name: IN_DONE_CH0_INT_CLR + description: Set this bit to clear the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: IN_SUC_EOF_CH0_INT_CLR + description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: IN_ERR_EOF_CH0_INT_CLR + description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: IN_DSCR_ERR_CH0_INT_CLR + description: Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: INFIFO_OVF_L1_CH0_INT_CLR + description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: INFIFO_UDF_L1_CH0_INT_CLR + description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: INFIFO_OVF_L2_CH0_INT_CLR + description: Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: INFIFO_UDF_L2_CH0_INT_CLR + description: Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: IN_DSCR_EMPTY_CH0_INT_CLR + description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: IN_DSCR_TASK_OVF_CH0_INT_CLR + description: Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - register: + name: INFIFO_STATUS_CH0 + description: RX CH0 INFIFO status register + addressOffset: 1300 + size: 32 + resetValue: 131202 + fields: + - name: INFIFO_FULL_L2_CH0 + description: Rx FIFO full signal for Rx channel. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: INFIFO_EMPTY_L2_CH0 + description: Rx FIFO empty signal for Rx channel. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: INFIFO_CNT_L2_CH0 + description: The register stores the byte number of the data in Rx FIFO for Rx channel. + bitOffset: 2 + bitWidth: 4 + access: read-only + - name: INFIFO_FULL_L1_CH0 + description: Tx FIFO full signal for Tx channel 0. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: INFIFO_EMPTY_L1_CH0 + description: Tx FIFO empty signal for Tx channel 0. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: INFIFO_CNT_L1_CH0 + description: The register stores the byte number of the data in Tx FIFO for Tx channel 0. + bitOffset: 8 + bitWidth: 5 + access: read-only + - name: INFIFO_FULL_L3_CH0 + description: Tx FIFO full signal for Tx channel 0. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: INFIFO_EMPTY_L3_CH0 + description: Tx FIFO empty signal for Tx channel 0. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: INFIFO_CNT_L3_CH0 + description: The register stores the 8byte number of the data in Tx FIFO for Tx channel 0. + bitOffset: 18 + bitWidth: 2 + access: read-only + - register: + name: IN_POP_CH0 + description: RX CH0 INFIFO pop register + addressOffset: 1304 + size: 32 + resetValue: 1024 + fields: + - name: INFIFO_RDATA_CH0 + description: This register stores the data popping from DMA Rx FIFO. + bitOffset: 0 + bitWidth: 11 + access: read-only + - name: INFIFO_POP_CH0 + description: Set this bit to pop data from DMA Rx FIFO. + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: IN_LINK_CONF_CH0 + description: RX CH0 in_link dscr ctrl register + addressOffset: 1308 + size: 32 + resetValue: 17825792 + fields: + - name: INLINK_AUTO_RET_CH0 + description: "Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: INLINK_STOP_CH0 + description: Set this bit to stop dealing with the inlink descriptors. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: INLINK_START_CH0 + description: Set this bit to start dealing with the inlink descriptors. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: INLINK_RESTART_CH0 + description: Set this bit to mount a new inlink descriptor. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: INLINK_PARK_CH0 + description: "1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working." + bitOffset: 24 + bitWidth: 1 + access: read-only + - register: + name: IN_LINK_ADDR_CH0 + description: RX CH0 in_link dscr addr register + addressOffset: 1312 + size: 32 + fields: + - name: INLINK_ADDR_CH0 + description: "This register stores the first inlink descriptor's address." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: IN_STATE_CH0 + description: RX CH0 state register + addressOffset: 1316 + size: 32 + resetValue: 8388608 + fields: + - name: INLINK_DSCR_ADDR_CH0 + description: "This register stores the current inlink descriptor's address." + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: IN_DSCR_STATE_CH0 + description: This register stores the current descriptor state machine state. + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: IN_STATE_CH0 + description: This register stores the current control module state machine state. + bitOffset: 20 + bitWidth: 3 + access: read-only + - name: IN_RESET_AVAIL_CH0 + description: This register indicate that if the channel reset is safety. + bitOffset: 23 + bitWidth: 1 + access: read-only + - register: + name: IN_SUC_EOF_DES_ADDR_CH0 + description: RX CH0 eof des addr register + addressOffset: 1320 + size: 32 + fields: + - name: IN_SUC_EOF_DES_ADDR_CH0 + description: This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_ERR_EOF_DES_ADDR_CH0 + description: RX CH0 err eof des addr register + addressOffset: 1324 + size: 32 + fields: + - name: IN_ERR_EOF_DES_ADDR_CH0 + description: This register stores the address of the inlink descriptor when there are some errors in current receiving data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_CH0 + description: RX CH0 next dscr addr register + addressOffset: 1328 + size: 32 + fields: + - name: INLINK_DSCR_CH0 + description: The address of the next inlink descriptor address x. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_BF0_CH0 + description: RX CH0 last dscr addr register + addressOffset: 1332 + size: 32 + fields: + - name: INLINK_DSCR_BF0_CH0 + description: "The address of the last inlink descriptor's next address x-1." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_BF1_CH0 + description: RX CH0 second-to-last dscr addr register + addressOffset: 1336 + size: 32 + fields: + - name: INLINK_DSCR_BF1_CH0 + description: "The address of the second-to-last inlink descriptor's next address x-2." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_ARB_CH0 + description: RX CH0 arb register + addressOffset: 1344 + size: 32 + resetValue: 81 + fields: + - name: IN_ARB_TOKEN_NUM_CH0 + description: Set the max number of token count of arbiter + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: EXTER_IN_ARB_PRIORITY_CH0 + description: Set the priority of channel + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: INTER_IN_ARB_PRIORITY_CH0 + description: Set the priority of channel + bitOffset: 6 + bitWidth: 3 + access: read-write + - register: + name: IN_RO_PD_CONF_CH0 + description: RX CH0 reorder power config register + addressOffset: 1352 + size: 32 + fields: + - name: IN_RO_RAM_CLK_FO_CH0 + description: "1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA." + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: IN_ETM_CONF_CH0 + description: RX CH0 ETM config register + addressOffset: 1388 + size: 32 + resetValue: 4 + fields: + - name: IN_ETM_EN_CH0 + description: Set this bit to 1 to enable ETM task function + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_ETM_LOOP_EN_CH0 + description: "when this bit is 1, dscr can be processed after receiving a task" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_DSCR_TASK_MAK_CH0 + description: ETM dscr_ready maximum cache numbers + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: IN_FIFO_CNT_CH0 + description: rx CH0 fifo cnt register + addressOffset: 1408 + size: 32 + fields: + - name: IN_CMDFIFO_INFIFO_CNT_CH0 + description: only for debug + bitOffset: 0 + bitWidth: 10 + access: read-only + - register: + name: IN_POP_DATA_CNT_CH0 + description: rx CH0 pop data cnt register + addressOffset: 1412 + size: 32 + resetValue: 7 + fields: + - name: IN_CMDFIFO_POP_DATA_CNT_CH0 + description: only for debug + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: IN_XADDR_CH0 + description: rx CH0 xaddr register + addressOffset: 1416 + size: 32 + fields: + - name: IN_CMDFIFO_XADDR_CH0 + description: only for debug + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_BUF_HB_RCV_CH0 + description: rx CH0 buf len hb rcv register + addressOffset: 1420 + size: 32 + fields: + - name: IN_CMDFIFO_BUF_HB_RCV_CH0 + description: only for debug + bitOffset: 0 + bitWidth: 29 + access: read-only + - register: + name: IN_CONF0_CH1 + description: RX CH1 config0 register + addressOffset: 1536 + size: 32 + fields: + - name: INDSCR_BURST_EN_CH1 + description: Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_ECC_AES_EN_CH1 + description: "When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: IN_CHECK_OWNER_CH1 + description: Set this bit to enable checking the owner attribute of the link descriptor. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IN_MEM_BURST_LENGTH_CH1 + description: "Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: IN_PAGE_BOUND_EN_CH1 + description: "Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: IN_RST_CH1 + description: Write 1 then write 0 to this bit to reset Rx channel + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: IN_CMD_DISABLE_CH1 + description: Write 1 before reset and write 0 after reset + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: IN_ARB_WEIGHT_OPT_DIS_CH1 + description: Set this bit to 1 to disable arbiter optimum weight function. + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: IN_INT_RAW_CH1 + description: RX CH1 interrupt raw register + addressOffset: 1540 + size: 32 + fields: + - name: IN_DONE_CH1_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF_CH1_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF_CH1_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR_CH1_INT_RAW + description: "The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L1_CH1_INT_RAW + description: This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L1_CH1_INT_RAW + description: This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L2_CH1_INT_RAW + description: This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L2_CH1_INT_RAW + description: This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY_CH1_INT_RAW + description: The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: IN_DSCR_TASK_OVF_CH1_INT_RAW + description: The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: IN_INT_ENA_CH1 + description: RX CH1 interrupt ena register + addressOffset: 1544 + size: 32 + fields: + - name: IN_DONE_CH1_INT_ENA + description: The interrupt enable bit for the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF_CH1_INT_ENA + description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF_CH1_INT_ENA + description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR_CH1_INT_ENA + description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L1_CH1_INT_ENA + description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L1_CH1_INT_ENA + description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L2_CH1_INT_ENA + description: The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L2_CH1_INT_ENA + description: The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY_CH1_INT_ENA + description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: IN_DSCR_TASK_OVF_CH1_INT_ENA + description: The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: IN_INT_ST_CH1 + description: RX CH1 interrupt st register + addressOffset: 1548 + size: 32 + fields: + - name: IN_DONE_CH1_INT_ST + description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: IN_SUC_EOF_CH1_INT_ST + description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: IN_ERR_EOF_CH1_INT_ST + description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: IN_DSCR_ERR_CH1_INT_ST + description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: INFIFO_OVF_L1_CH1_INT_ST + description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: INFIFO_UDF_L1_CH1_INT_ST + description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: INFIFO_OVF_L2_CH1_INT_ST + description: The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: INFIFO_UDF_L2_CH1_INT_ST + description: The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IN_DSCR_EMPTY_CH1_INT_ST + description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: IN_DSCR_TASK_OVF_CH1_INT_ST + description: The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - register: + name: IN_INT_CLR_CH1 + description: RX CH1 interrupt clr register + addressOffset: 1552 + size: 32 + fields: + - name: IN_DONE_CH1_INT_CLR + description: Set this bit to clear the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: IN_SUC_EOF_CH1_INT_CLR + description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: IN_ERR_EOF_CH1_INT_CLR + description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: IN_DSCR_ERR_CH1_INT_CLR + description: Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: INFIFO_OVF_L1_CH1_INT_CLR + description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: INFIFO_UDF_L1_CH1_INT_CLR + description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: INFIFO_OVF_L2_CH1_INT_CLR + description: Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: INFIFO_UDF_L2_CH1_INT_CLR + description: Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: IN_DSCR_EMPTY_CH1_INT_CLR + description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: IN_DSCR_TASK_OVF_CH1_INT_CLR + description: Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - register: + name: INFIFO_STATUS_CH1 + description: RX CH1 INFIFO status register + addressOffset: 1556 + size: 32 + resetValue: 131202 + fields: + - name: INFIFO_FULL_L2_CH1 + description: Rx FIFO full signal for Rx channel. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: INFIFO_EMPTY_L2_CH1 + description: Rx FIFO empty signal for Rx channel. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: INFIFO_CNT_L2_CH1 + description: The register stores the byte number of the data in Rx FIFO for Rx channel. + bitOffset: 2 + bitWidth: 4 + access: read-only + - name: INFIFO_FULL_L1_CH1 + description: Tx FIFO full signal for Tx channel 1. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: INFIFO_EMPTY_L1_CH1 + description: Tx FIFO empty signal for Tx channel 1. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: INFIFO_CNT_L1_CH1 + description: The register stores the byte number of the data in Tx FIFO for Tx channel 1. + bitOffset: 8 + bitWidth: 5 + access: read-only + - name: INFIFO_FULL_L3_CH1 + description: Tx FIFO full signal for Tx channel 1. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: INFIFO_EMPTY_L3_CH1 + description: Tx FIFO empty signal for Tx channel 1. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: INFIFO_CNT_L3_CH1 + description: The register stores the byte number of the data in Tx FIFO for Tx channel 1. + bitOffset: 18 + bitWidth: 2 + access: read-only + - register: + name: IN_POP_CH1 + description: RX CH1 INFIFO pop register + addressOffset: 1560 + size: 32 + resetValue: 1024 + fields: + - name: INFIFO_RDATA_CH1 + description: This register stores the data popping from DMA Rx FIFO. + bitOffset: 0 + bitWidth: 11 + access: read-only + - name: INFIFO_POP_CH1 + description: Set this bit to pop data from DMA Rx FIFO. + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: IN_LINK_CONF_CH1 + description: RX CH1 in_link dscr ctrl register + addressOffset: 1564 + size: 32 + resetValue: 17825792 + fields: + - name: INLINK_AUTO_RET_CH1 + description: "Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: INLINK_STOP_CH1 + description: Set this bit to stop dealing with the inlink descriptors. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: INLINK_START_CH1 + description: Set this bit to start dealing with the inlink descriptors. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: INLINK_RESTART_CH1 + description: Set this bit to mount a new inlink descriptor. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: INLINK_PARK_CH1 + description: "1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working." + bitOffset: 24 + bitWidth: 1 + access: read-only + - register: + name: IN_LINK_ADDR_CH1 + description: RX CH1 in_link dscr addr register + addressOffset: 1568 + size: 32 + fields: + - name: INLINK_ADDR_CH1 + description: "This register stores the first inlink descriptor's address." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: IN_STATE_CH1 + description: RX CH1 state register + addressOffset: 1572 + size: 32 + resetValue: 8388608 + fields: + - name: INLINK_DSCR_ADDR_CH1 + description: "This register stores the current inlink descriptor's address." + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: IN_DSCR_STATE_CH1 + description: This register stores the current descriptor state machine state. + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: IN_STATE_CH1 + description: This register stores the current control module state machine state. + bitOffset: 20 + bitWidth: 3 + access: read-only + - name: IN_RESET_AVAIL_CH1 + description: This register indicate that if the channel reset is safety. + bitOffset: 23 + bitWidth: 1 + access: read-only + - register: + name: IN_SUC_EOF_DES_ADDR_CH1 + description: RX CH1 eof des addr register + addressOffset: 1576 + size: 32 + fields: + - name: IN_SUC_EOF_DES_ADDR_CH1 + description: This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_ERR_EOF_DES_ADDR_CH1 + description: RX CH1 err eof des addr register + addressOffset: 1580 + size: 32 + fields: + - name: IN_ERR_EOF_DES_ADDR_CH1 + description: This register stores the address of the inlink descriptor when there are some errors in current receiving data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_CH1 + description: RX CH1 next dscr addr register + addressOffset: 1584 + size: 32 + fields: + - name: INLINK_DSCR_CH1 + description: The address of the next inlink descriptor address x. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_BF0_CH1 + description: RX CH1 last dscr addr register + addressOffset: 1588 + size: 32 + fields: + - name: INLINK_DSCR_BF0_CH1 + description: "The address of the last inlink descriptor's next address x-1." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_BF1_CH1 + description: RX CH1 second-to-last dscr addr register + addressOffset: 1592 + size: 32 + fields: + - name: INLINK_DSCR_BF1_CH1 + description: "The address of the second-to-last inlink descriptor's next address x-2." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_ARB_CH1 + description: RX CH1 arb register + addressOffset: 1600 + size: 32 + resetValue: 81 + fields: + - name: IN_ARB_TOKEN_NUM_CH1 + description: Set the max number of token count of arbiter + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: EXTER_IN_ARB_PRIORITY_CH1 + description: Set the priority of channel + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: INTER_IN_ARB_PRIORITY_CH1 + description: Set the priority of channel + bitOffset: 6 + bitWidth: 3 + access: read-write + - register: + name: IN_ETM_CONF_CH1 + description: RX CH1 ETM config register + addressOffset: 1608 + size: 32 + resetValue: 4 + fields: + - name: IN_ETM_EN_CH1 + description: Set this bit to 1 to enable ETM task function + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_ETM_LOOP_EN_CH1 + description: "when this bit is 1, dscr can be processed after receiving a task" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_DSCR_TASK_MAK_CH1 + description: ETM dscr_ready maximum cache numbers + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: IN_FIFO_CNT_CH1 + description: rx CH1 fifo cnt register + addressOffset: 1664 + size: 32 + fields: + - name: IN_CMDFIFO_INFIFO_CNT_CH1 + description: only for debug + bitOffset: 0 + bitWidth: 10 + access: read-only + - register: + name: IN_POP_DATA_CNT_CH1 + description: rx CH1 pop data cnt register + addressOffset: 1668 + size: 32 + resetValue: 7 + fields: + - name: IN_CMDFIFO_POP_DATA_CNT_CH1 + description: only for debug + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: IN_XADDR_CH1 + description: rx CH1 xaddr register + addressOffset: 1672 + size: 32 + fields: + - name: IN_CMDFIFO_XADDR_CH1 + description: only for debug + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_BUF_HB_RCV_CH1 + description: rx CH1 buf len hb rcv register + addressOffset: 1676 + size: 32 + fields: + - name: IN_CMDFIFO_BUF_HB_RCV_CH1 + description: only for debug + bitOffset: 0 + bitWidth: 29 + access: read-only + - register: + name: IN_CONF0_CH2 + description: RX CH2 config0 register + addressOffset: 1792 + size: 32 + fields: + - name: INDSCR_BURST_EN_CH2 + description: Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_ECC_AES_EN_CH2 + description: "When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: IN_CHECK_OWNER_CH2 + description: Set this bit to enable checking the owner attribute of the link descriptor. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IN_MEM_BURST_LENGTH_CH2 + description: "Block size of Rx channel 2. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: IN_PAGE_BOUND_EN_CH2 + description: "Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: IN_RST_CH2 + description: Write 1 then write 0 to this bit to reset Rx channel + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: IN_CMD_DISABLE_CH2 + description: Write 1 before reset and write 0 after reset + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: IN_ARB_WEIGHT_OPT_DIS_CH2 + description: Set this bit to 1 to disable arbiter optimum weight function. + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: IN_INT_RAW_CH2 + description: RX CH2 interrupt raw register + addressOffset: 1796 + size: 32 + fields: + - name: IN_DONE_CH2_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF_CH2_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF_CH2_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR_CH2_INT_RAW + description: "The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L1_CH2_INT_RAW + description: This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L1_CH2_INT_RAW + description: This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L2_CH2_INT_RAW + description: This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L2_CH2_INT_RAW + description: This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY_CH2_INT_RAW + description: The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: IN_DSCR_TASK_OVF_CH2_INT_RAW + description: The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: IN_INT_ENA_CH2 + description: RX CH2 interrupt ena register + addressOffset: 1800 + size: 32 + fields: + - name: IN_DONE_CH2_INT_ENA + description: The interrupt enable bit for the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF_CH2_INT_ENA + description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF_CH2_INT_ENA + description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR_CH2_INT_ENA + description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L1_CH2_INT_ENA + description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L1_CH2_INT_ENA + description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L2_CH2_INT_ENA + description: The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L2_CH2_INT_ENA + description: The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY_CH2_INT_ENA + description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: IN_DSCR_TASK_OVF_CH2_INT_ENA + description: The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: IN_INT_ST_CH2 + description: RX CH2 interrupt st register + addressOffset: 1804 + size: 32 + fields: + - name: IN_DONE_CH2_INT_ST + description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: IN_SUC_EOF_CH2_INT_ST + description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: IN_ERR_EOF_CH2_INT_ST + description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: IN_DSCR_ERR_CH2_INT_ST + description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: INFIFO_OVF_L1_CH2_INT_ST + description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: INFIFO_UDF_L1_CH2_INT_ST + description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: INFIFO_OVF_L2_CH2_INT_ST + description: The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: INFIFO_UDF_L2_CH2_INT_ST + description: The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IN_DSCR_EMPTY_CH2_INT_ST + description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: IN_DSCR_TASK_OVF_CH2_INT_ST + description: The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - register: + name: IN_INT_CLR_CH2 + description: RX CH2 interrupt clr register + addressOffset: 1808 + size: 32 + fields: + - name: IN_DONE_CH2_INT_CLR + description: Set this bit to clear the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: IN_SUC_EOF_CH2_INT_CLR + description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: IN_ERR_EOF_CH2_INT_CLR + description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: IN_DSCR_ERR_CH2_INT_CLR + description: Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: INFIFO_OVF_L1_CH2_INT_CLR + description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: INFIFO_UDF_L1_CH2_INT_CLR + description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: INFIFO_OVF_L2_CH2_INT_CLR + description: Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: INFIFO_UDF_L2_CH2_INT_CLR + description: Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: IN_DSCR_EMPTY_CH2_INT_CLR + description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: IN_DSCR_TASK_OVF_CH2_INT_CLR + description: Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - register: + name: INFIFO_STATUS_CH2 + description: RX CH2 INFIFO status register + addressOffset: 1812 + size: 32 + resetValue: 131202 + fields: + - name: INFIFO_FULL_L2_CH2 + description: Rx FIFO full signal for Rx channel. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: INFIFO_EMPTY_L2_CH2 + description: Rx FIFO empty signal for Rx channel. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: INFIFO_CNT_L2_CH2 + description: The register stores the byte number of the data in Rx FIFO for Rx channel. + bitOffset: 2 + bitWidth: 4 + access: read-only + - name: INFIFO_FULL_L1_CH2 + description: Tx FIFO full signal for Tx channel 1. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: INFIFO_EMPTY_L1_CH2 + description: Tx FIFO empty signal for Tx channel 1. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: INFIFO_CNT_L1_CH2 + description: The register stores the byte number of the data in Tx FIFO for Tx channel 1. + bitOffset: 8 + bitWidth: 5 + access: read-only + - name: INFIFO_FULL_L3_CH2 + description: Tx FIFO full signal for Tx channel 1. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: INFIFO_EMPTY_L3_CH2 + description: Tx FIFO empty signal for Tx channel 1. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: INFIFO_CNT_L3_CH2 + description: The register stores the byte number of the data in Tx FIFO for Tx channel 1. + bitOffset: 18 + bitWidth: 2 + access: read-only + - register: + name: IN_POP_CH2 + description: RX CH2 INFIFO pop register + addressOffset: 1816 + size: 32 + resetValue: 1024 + fields: + - name: INFIFO_RDATA_CH2 + description: This register stores the data popping from DMA Rx FIFO. + bitOffset: 0 + bitWidth: 11 + access: read-only + - name: INFIFO_POP_CH2 + description: Set this bit to pop data from DMA Rx FIFO. + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: IN_LINK_CONF_CH2 + description: RX CH2 in_link dscr ctrl register + addressOffset: 1820 + size: 32 + resetValue: 17825792 + fields: + - name: INLINK_AUTO_RET_CH2 + description: "Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: INLINK_STOP_CH2 + description: Set this bit to stop dealing with the inlink descriptors. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: INLINK_START_CH2 + description: Set this bit to start dealing with the inlink descriptors. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: INLINK_RESTART_CH2 + description: Set this bit to mount a new inlink descriptor. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: INLINK_PARK_CH2 + description: "1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working." + bitOffset: 24 + bitWidth: 1 + access: read-only + - register: + name: IN_LINK_ADDR_CH2 + description: RX CH2 in_link dscr addr register + addressOffset: 1824 + size: 32 + fields: + - name: INLINK_ADDR_CH2 + description: "This register stores the first inlink descriptor's address." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: IN_STATE_CH2 + description: RX CH2 state register + addressOffset: 1828 + size: 32 + resetValue: 8388608 + fields: + - name: INLINK_DSCR_ADDR_CH2 + description: "This register stores the current inlink descriptor's address." + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: IN_DSCR_STATE_CH2 + description: This register stores the current descriptor state machine state. + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: IN_STATE_CH2 + description: This register stores the current control module state machine state. + bitOffset: 20 + bitWidth: 3 + access: read-only + - name: IN_RESET_AVAIL_CH2 + description: This register indicate that if the channel reset is safety. + bitOffset: 23 + bitWidth: 1 + access: read-only + - register: + name: IN_SUC_EOF_DES_ADDR_CH2 + description: RX CH2 eof des addr register + addressOffset: 1832 + size: 32 + fields: + - name: IN_SUC_EOF_DES_ADDR_CH2 + description: This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_ERR_EOF_DES_ADDR_CH2 + description: RX CH2 err eof des addr register + addressOffset: 1836 + size: 32 + fields: + - name: IN_ERR_EOF_DES_ADDR_CH2 + description: This register stores the address of the inlink descriptor when there are some errors in current receiving data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_CH2 + description: RX CH2 next dscr addr register + addressOffset: 1840 + size: 32 + fields: + - name: INLINK_DSCR_CH2 + description: The address of the next inlink descriptor address x. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_BF0_CH2 + description: RX CH2 last dscr addr register + addressOffset: 1844 + size: 32 + fields: + - name: INLINK_DSCR_BF0_CH2 + description: "The address of the last inlink descriptor's next address x-1." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_BF1_CH2 + description: RX CH2 second-to-last dscr addr register + addressOffset: 1848 + size: 32 + fields: + - name: INLINK_DSCR_BF1_CH2 + description: "The address of the second-to-last inlink descriptor's next address x-2." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_ARB_CH2 + description: RX CH2 arb register + addressOffset: 1856 + size: 32 + resetValue: 65 + fields: + - name: IN_ARB_TOKEN_NUM_CH2 + description: Set the max number of token count of arbiter + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: INTER_IN_ARB_PRIORITY_CH2 + description: Set the priority of channel + bitOffset: 6 + bitWidth: 3 + access: read-write + - register: + name: IN_ETM_CONF_CH2 + description: RX CH2 ETM config register + addressOffset: 1864 + size: 32 + resetValue: 4 + fields: + - name: IN_ETM_EN_CH2 + description: Set this bit to 1 to enable ETM task function + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_ETM_LOOP_EN_CH2 + description: "when this bit is 1, dscr can be processed after receiving a task" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_DSCR_TASK_MAK_CH2 + description: ETM dscr_ready maximum cache numbers + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: IN_FIFO_CNT_CH2 + description: rx CH2 fifo cnt register + addressOffset: 1920 + size: 32 + fields: + - name: IN_CMDFIFO_INFIFO_CNT_CH2 + description: only for debug + bitOffset: 0 + bitWidth: 10 + access: read-only + - register: + name: IN_POP_DATA_CNT_CH2 + description: rx CH2 pop data cnt register + addressOffset: 1924 + size: 32 + resetValue: 7 + fields: + - name: IN_CMDFIFO_POP_DATA_CNT_CH2 + description: only for debug + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: IN_XADDR_CH2 + description: rx CH2 xaddr register + addressOffset: 1928 + size: 32 + fields: + - name: IN_CMDFIFO_XADDR_CH2 + description: only for debug + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_BUF_HB_RCV_CH2 + description: rx CH2 buf len hb rcv register + addressOffset: 1932 + size: 32 + fields: + - name: IN_CMDFIFO_BUF_HB_RCV_CH2 + description: only for debug + bitOffset: 0 + bitWidth: 29 + access: read-only + - register: + name: IN_CONF0_CH3 + description: RX CH3 config0 register + addressOffset: 2048 + size: 32 + fields: + - name: INDSCR_BURST_EN_CH3 + description: Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_ECC_AES_EN_CH3 + description: "When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: IN_CHECK_OWNER_CH3 + description: Set this bit to enable checking the owner attribute of the link descriptor. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IN_MEM_BURST_LENGTH_CH3 + description: "Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: IN_PAGE_BOUND_EN_CH3 + description: "Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: IN_RST_CH3 + description: Write 1 then write 0 to this bit to reset Rx channel + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: IN_CMD_DISABLE_CH3 + description: Write 1 before reset and write 0 after reset + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: IN_ARB_WEIGHT_OPT_DIS_CH3 + description: Set this bit to 1 to disable arbiter optimum weight function. + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: IN_INT_RAW_CH3 + description: RX CH3 interrupt raw register + addressOffset: 2052 + size: 32 + fields: + - name: IN_DONE_CH3_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF_CH3_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF_CH3_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR_CH3_INT_RAW + description: "The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L1_CH3_INT_RAW + description: This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L1_CH3_INT_RAW + description: This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L2_CH3_INT_RAW + description: This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L2_CH3_INT_RAW + description: This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY_CH3_INT_RAW + description: The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: IN_DSCR_TASK_OVF_CH3_INT_RAW + description: The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: IN_INT_ENA_CH3 + description: RX CH3 interrupt ena register + addressOffset: 2056 + size: 32 + fields: + - name: IN_DONE_CH3_INT_ENA + description: The interrupt enable bit for the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF_CH3_INT_ENA + description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF_CH3_INT_ENA + description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR_CH3_INT_ENA + description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L1_CH3_INT_ENA + description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L1_CH3_INT_ENA + description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L2_CH3_INT_ENA + description: The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L2_CH3_INT_ENA + description: The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY_CH3_INT_ENA + description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: IN_DSCR_TASK_OVF_CH3_INT_ENA + description: The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: IN_INT_ST_CH3 + description: RX CH3 interrupt st register + addressOffset: 2060 + size: 32 + fields: + - name: IN_DONE_CH3_INT_ST + description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: IN_SUC_EOF_CH3_INT_ST + description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: IN_ERR_EOF_CH3_INT_ST + description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: IN_DSCR_ERR_CH3_INT_ST + description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: INFIFO_OVF_L1_CH3_INT_ST + description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: INFIFO_UDF_L1_CH3_INT_ST + description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: INFIFO_OVF_L2_CH3_INT_ST + description: The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: INFIFO_UDF_L2_CH3_INT_ST + description: The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IN_DSCR_EMPTY_CH3_INT_ST + description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: IN_DSCR_TASK_OVF_CH3_INT_ST + description: The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - register: + name: IN_INT_CLR_CH3 + description: RX CH3 interrupt clr register + addressOffset: 2064 + size: 32 + fields: + - name: IN_DONE_CH3_INT_CLR + description: Set this bit to clear the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: IN_SUC_EOF_CH3_INT_CLR + description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: IN_ERR_EOF_CH3_INT_CLR + description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: IN_DSCR_ERR_CH3_INT_CLR + description: Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: INFIFO_OVF_L1_CH3_INT_CLR + description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: INFIFO_UDF_L1_CH3_INT_CLR + description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: INFIFO_OVF_L2_CH3_INT_CLR + description: Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: INFIFO_UDF_L2_CH3_INT_CLR + description: Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: IN_DSCR_EMPTY_CH3_INT_CLR + description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: IN_DSCR_TASK_OVF_CH3_INT_CLR + description: Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - register: + name: INFIFO_STATUS_CH3 + description: RX CH3 INFIFO status register + addressOffset: 2068 + size: 32 + resetValue: 131202 + fields: + - name: INFIFO_FULL_L2_CH3 + description: Rx FIFO full signal for Rx channel. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: INFIFO_EMPTY_L2_CH3 + description: Rx FIFO empty signal for Rx channel. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: INFIFO_CNT_L2_CH3 + description: The register stores the byte number of the data in Rx FIFO for Rx channel. + bitOffset: 2 + bitWidth: 4 + access: read-only + - name: INFIFO_FULL_L1_CH3 + description: Tx FIFO full signal for Tx channel 1. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: INFIFO_EMPTY_L1_CH3 + description: Tx FIFO empty signal for Tx channel 1. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: INFIFO_CNT_L1_CH3 + description: The register stores the byte number of the data in Tx FIFO for Tx channel 1. + bitOffset: 8 + bitWidth: 5 + access: read-only + - name: INFIFO_FULL_L3_CH3 + description: Tx FIFO full signal for Tx channel 1. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: INFIFO_EMPTY_L3_CH3 + description: Tx FIFO empty signal for Tx channel 1. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: INFIFO_CNT_L3_CH3 + description: The register stores the byte number of the data in Tx FIFO for Tx channel 1. + bitOffset: 18 + bitWidth: 2 + access: read-only + - register: + name: IN_POP_CH3 + description: RX CH3 INFIFO pop register + addressOffset: 2072 + size: 32 + resetValue: 1024 + fields: + - name: INFIFO_RDATA_CH3 + description: This register stores the data popping from DMA Rx FIFO. + bitOffset: 0 + bitWidth: 11 + access: read-only + - name: INFIFO_POP_CH3 + description: Set this bit to pop data from DMA Rx FIFO. + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: IN_LINK_CONF_CH3 + description: RX CH3 in_link dscr ctrl register + addressOffset: 2076 + size: 32 + resetValue: 17825792 + fields: + - name: INLINK_AUTO_RET_CH3 + description: "Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: INLINK_STOP_CH3 + description: Set this bit to stop dealing with the inlink descriptors. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: INLINK_START_CH3 + description: Set this bit to start dealing with the inlink descriptors. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: INLINK_RESTART_CH3 + description: Set this bit to mount a new inlink descriptor. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: INLINK_PARK_CH3 + description: "1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working." + bitOffset: 24 + bitWidth: 1 + access: read-only + - register: + name: IN_LINK_ADDR_CH3 + description: RX CH3 in_link dscr addr register + addressOffset: 2080 + size: 32 + fields: + - name: INLINK_ADDR_CH3 + description: "This register stores the first inlink descriptor's address." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: IN_STATE_CH3 + description: RX CH3 state register + addressOffset: 2084 + size: 32 + resetValue: 8388608 + fields: + - name: INLINK_DSCR_ADDR_CH3 + description: "This register stores the current inlink descriptor's address." + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: IN_DSCR_STATE_CH3 + description: This register stores the current descriptor state machine state. + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: IN_STATE_CH3 + description: This register stores the current control module state machine state. + bitOffset: 20 + bitWidth: 3 + access: read-only + - name: IN_RESET_AVAIL_CH3 + description: This register indicate that if the channel reset is safety. + bitOffset: 23 + bitWidth: 1 + access: read-only + - register: + name: IN_SUC_EOF_DES_ADDR_CH3 + description: RX CH3 eof des addr register + addressOffset: 2088 + size: 32 + fields: + - name: IN_SUC_EOF_DES_ADDR_CH3 + description: This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_ERR_EOF_DES_ADDR_CH3 + description: RX CH3 err eof des addr register + addressOffset: 2092 + size: 32 + fields: + - name: IN_ERR_EOF_DES_ADDR_CH3 + description: This register stores the address of the inlink descriptor when there are some errors in current receiving data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_CH3 + description: RX CH3 next dscr addr register + addressOffset: 2096 + size: 32 + fields: + - name: INLINK_DSCR_CH3 + description: The address of the next inlink descriptor address x. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_BF0_CH3 + description: RX CH3 last dscr addr register + addressOffset: 2100 + size: 32 + fields: + - name: INLINK_DSCR_BF0_CH3 + description: "The address of the last inlink descriptor's next address x-1." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_BF1_CH3 + description: RX CH3 second-to-last dscr addr register + addressOffset: 2104 + size: 32 + fields: + - name: INLINK_DSCR_BF1_CH3 + description: "The address of the second-to-last inlink descriptor's next address x-2." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_ARB_CH3 + description: RX CH3 arb register + addressOffset: 2112 + size: 32 + resetValue: 65 + fields: + - name: IN_ARB_TOKEN_NUM_CH3 + description: Set the max number of token count of arbiter + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: INTER_IN_ARB_PRIORITY_CH3 + description: Set the priority of channel + bitOffset: 6 + bitWidth: 3 + access: read-write + - register: + name: IN_ETM_CONF_CH3 + description: RX CH3 ETM config register + addressOffset: 2120 + size: 32 + resetValue: 4 + fields: + - name: IN_ETM_EN_CH3 + description: Set this bit to 1 to enable ETM task function + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_ETM_LOOP_EN_CH3 + description: "when this bit is 1, dscr can be processed after receiving a task" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_DSCR_TASK_MAK_CH3 + description: ETM dscr_ready maximum cache numbers + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: IN_FIFO_CNT_CH3 + description: rx CH3 fifo cnt register + addressOffset: 2176 + size: 32 + fields: + - name: IN_CMDFIFO_INFIFO_CNT_CH3 + description: only for debug + bitOffset: 0 + bitWidth: 10 + access: read-only + - register: + name: IN_POP_DATA_CNT_CH3 + description: rx CH3 pop data cnt register + addressOffset: 2180 + size: 32 + resetValue: 7 + fields: + - name: IN_CMDFIFO_POP_DATA_CNT_CH3 + description: only for debug + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: IN_XADDR_CH3 + description: rx CH3 xaddr register + addressOffset: 2184 + size: 32 + fields: + - name: IN_CMDFIFO_XADDR_CH3 + description: only for debug + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_BUF_HB_RCV_CH3 + description: rx CH3 buf len hb rcv register + addressOffset: 2188 + size: 32 + fields: + - name: IN_CMDFIFO_BUF_HB_RCV_CH3 + description: only for debug + bitOffset: 0 + bitWidth: 29 + access: read-only + - register: + name: IN_CONF0_CH4 + description: RX CH4 config0 register + addressOffset: 2304 + size: 32 + fields: + - name: INDSCR_BURST_EN_CH4 + description: Set this bit to 1 to enable INCR burst transfer for Rx transmitting link descriptor when accessing SRAM. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_ECC_AES_EN_CH4 + description: "When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: IN_CHECK_OWNER_CH4 + description: Set this bit to enable checking the owner attribute of the link descriptor. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IN_MEM_BURST_LENGTH_CH4 + description: "Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: IN_PAGE_BOUND_EN_CH4 + description: "Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: IN_RST_CH4 + description: Write 1 then write 0 to this bit to reset Rx channel + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: IN_CMD_DISABLE_CH4 + description: Write 1 before reset and write 0 after reset + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: IN_ARB_WEIGHT_OPT_DIS_CH4 + description: Set this bit to 1 to disable arbiter optimum weight function. + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: IN_INT_RAW_CH4 + description: RX CH4 interrupt raw register + addressOffset: 2308 + size: 32 + fields: + - name: IN_DONE_CH4_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF_CH4_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF_CH4_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and data error is detected + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR_CH4_INT_RAW + description: "The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L1_CH4_INT_RAW + description: This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L1_CH4_INT_RAW + description: This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L2_CH4_INT_RAW + description: This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L2_CH4_INT_RAW + description: This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY_CH4_INT_RAW + description: The raw interrupt bit turns to high level when the last descriptor is done but fifo also remain data. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: IN_DSCR_TASK_OVF_CH4_INT_RAW + description: The raw interrupt bit turns to high level when dscr ready task fifo is overflow. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: IN_INT_ENA_CH4 + description: RX CH4 interrupt ena register + addressOffset: 2312 + size: 32 + fields: + - name: IN_DONE_CH4_INT_ENA + description: The interrupt enable bit for the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF_CH4_INT_ENA + description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF_CH4_INT_ENA + description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR_CH4_INT_ENA + description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L1_CH4_INT_ENA + description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L1_CH4_INT_ENA + description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L2_CH4_INT_ENA + description: The interrupt enable bit for the INFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L2_CH4_INT_ENA + description: The interrupt enable bit for the INFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY_CH4_INT_ENA + description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: IN_DSCR_TASK_OVF_CH4_INT_ENA + description: The interrupt enable bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: IN_INT_ST_CH4 + description: RX CH4 interrupt st register + addressOffset: 2316 + size: 32 + fields: + - name: IN_DONE_CH4_INT_ST + description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: IN_SUC_EOF_CH4_INT_ST + description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: IN_ERR_EOF_CH4_INT_ST + description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: IN_DSCR_ERR_CH4_INT_ST + description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: INFIFO_OVF_L1_CH4_INT_ST + description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: INFIFO_UDF_L1_CH4_INT_ST + description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: INFIFO_OVF_L2_CH4_INT_ST + description: The raw interrupt status bit for the INFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: INFIFO_UDF_L2_CH4_INT_ST + description: The raw interrupt status bit for the INFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IN_DSCR_EMPTY_CH4_INT_ST + description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: IN_DSCR_TASK_OVF_CH4_INT_ST + description: The raw interrupt status bit for the IN_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - register: + name: IN_INT_CLR_CH4 + description: RX CH4 interrupt clr register + addressOffset: 2320 + size: 32 + fields: + - name: IN_DONE_CH4_INT_CLR + description: Set this bit to clear the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: IN_SUC_EOF_CH4_INT_CLR + description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: IN_ERR_EOF_CH4_INT_CLR + description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: IN_DSCR_ERR_CH4_INT_CLR + description: Set this bit to clear the INDSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: INFIFO_OVF_L1_CH4_INT_CLR + description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: INFIFO_UDF_L1_CH4_INT_CLR + description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: INFIFO_OVF_L2_CH4_INT_CLR + description: Set this bit to clear the INFIFO_OVF_L2_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: INFIFO_UDF_L2_CH4_INT_CLR + description: Set this bit to clear the INFIFO_UDF_L2_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: IN_DSCR_EMPTY_CH4_INT_CLR + description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: IN_DSCR_TASK_OVF_CH4_INT_CLR + description: Set this bit to clear the IN_DSCR_TASK_OVF_CH_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - register: + name: INFIFO_STATUS_CH4 + description: RX CH4 INFIFO status register + addressOffset: 2324 + size: 32 + resetValue: 131202 + fields: + - name: INFIFO_FULL_L2_CH4 + description: Rx FIFO full signal for Rx channel. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: INFIFO_EMPTY_L2_CH4 + description: Rx FIFO empty signal for Rx channel. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: INFIFO_CNT_L2_CH4 + description: The register stores the byte number of the data in Rx FIFO for Rx channel. + bitOffset: 2 + bitWidth: 4 + access: read-only + - name: INFIFO_FULL_L1_CH4 + description: Tx FIFO full signal for Tx channel 1. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: INFIFO_EMPTY_L1_CH4 + description: Tx FIFO empty signal for Tx channel 1. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: INFIFO_CNT_L1_CH4 + description: The register stores the byte number of the data in Tx FIFO for Tx channel 1. + bitOffset: 8 + bitWidth: 5 + access: read-only + - name: INFIFO_FULL_L3_CH4 + description: Tx FIFO full signal for Tx channel 1. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: INFIFO_EMPTY_L3_CH4 + description: Tx FIFO empty signal for Tx channel 1. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: INFIFO_CNT_L3_CH4 + description: The register stores the byte number of the data in Tx FIFO for Tx channel 1. + bitOffset: 18 + bitWidth: 2 + access: read-only + - register: + name: IN_POP_CH4 + description: RX CH4 INFIFO pop register + addressOffset: 2328 + size: 32 + resetValue: 1024 + fields: + - name: INFIFO_RDATA_CH4 + description: This register stores the data popping from DMA Rx FIFO. + bitOffset: 0 + bitWidth: 11 + access: read-only + - name: INFIFO_POP_CH4 + description: Set this bit to pop data from DMA Rx FIFO. + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: IN_LINK_CONF_CH4 + description: RX CH4 in_link dscr ctrl register + addressOffset: 2332 + size: 32 + resetValue: 17825792 + fields: + - name: INLINK_AUTO_RET_CH4 + description: "Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: INLINK_STOP_CH4 + description: Set this bit to stop dealing with the inlink descriptors. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: INLINK_START_CH4 + description: Set this bit to start dealing with the inlink descriptors. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: INLINK_RESTART_CH4 + description: Set this bit to mount a new inlink descriptor. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: INLINK_PARK_CH4 + description: "1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working." + bitOffset: 24 + bitWidth: 1 + access: read-only + - register: + name: IN_LINK_ADDR_CH4 + description: RX CH4 in_link dscr addr register + addressOffset: 2336 + size: 32 + fields: + - name: INLINK_ADDR_CH4 + description: "This register stores the first inlink descriptor's address." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: IN_STATE_CH4 + description: RX CH4 state register + addressOffset: 2340 + size: 32 + resetValue: 8388608 + fields: + - name: INLINK_DSCR_ADDR_CH4 + description: "This register stores the current inlink descriptor's address." + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: IN_DSCR_STATE_CH4 + description: This register stores the current descriptor state machine state. + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: IN_STATE_CH4 + description: This register stores the current control module state machine state. + bitOffset: 20 + bitWidth: 3 + access: read-only + - name: IN_RESET_AVAIL_CH4 + description: This register indicate that if the channel reset is safety. + bitOffset: 23 + bitWidth: 1 + access: read-only + - register: + name: IN_SUC_EOF_DES_ADDR_CH4 + description: RX CH4 eof des addr register + addressOffset: 2344 + size: 32 + fields: + - name: IN_SUC_EOF_DES_ADDR_CH4 + description: This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_ERR_EOF_DES_ADDR_CH4 + description: RX CH4 err eof des addr register + addressOffset: 2348 + size: 32 + fields: + - name: IN_ERR_EOF_DES_ADDR_CH4 + description: This register stores the address of the inlink descriptor when there are some errors in current receiving data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_CH4 + description: RX CH4 next dscr addr register + addressOffset: 2352 + size: 32 + fields: + - name: INLINK_DSCR_CH4 + description: The address of the next inlink descriptor address x. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_BF0_CH4 + description: RX CH4 last dscr addr register + addressOffset: 2356 + size: 32 + fields: + - name: INLINK_DSCR_BF0_CH4 + description: "The address of the last inlink descriptor's next address x-1." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_BF1_CH4 + description: RX CH4 second-to-last dscr addr register + addressOffset: 2360 + size: 32 + fields: + - name: INLINK_DSCR_BF1_CH4 + description: "The address of the second-to-last inlink descriptor's next address x-2." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_ARB_CH4 + description: RX CH4 arb register + addressOffset: 2368 + size: 32 + resetValue: 81 + fields: + - name: IN_ARB_TOKEN_NUM_CH4 + description: Set the max number of token count of arbiter + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: EXTER_IN_ARB_PRIORITY_CH4 + description: Set the priority of channel + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: INTER_IN_ARB_PRIORITY_CH4 + description: Set the priority of channel + bitOffset: 6 + bitWidth: 3 + access: read-write + - register: + name: IN_ETM_CONF_CH4 + description: RX CH4 ETM config register + addressOffset: 2376 + size: 32 + resetValue: 4 + fields: + - name: IN_ETM_EN_CH4 + description: Set this bit to 1 to enable ETM task function + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_ETM_LOOP_EN_CH4 + description: "when this bit is 1, dscr can be processed after receiving a task" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_DSCR_TASK_MAK_CH4 + description: ETM dscr_ready maximum cache numbers + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: IN_FIFO_CNT_CH4 + description: rx CH4 fifo cnt register + addressOffset: 2432 + size: 32 + fields: + - name: IN_CMDFIFO_INFIFO_CNT_CH4 + description: only for debug + bitOffset: 0 + bitWidth: 10 + access: read-only + - register: + name: IN_POP_DATA_CNT_CH4 + description: rx CH4 pop data cnt register + addressOffset: 2436 + size: 32 + resetValue: 7 + fields: + - name: IN_CMDFIFO_POP_DATA_CNT_CH4 + description: only for debug + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: IN_XADDR_CH4 + description: rx CH4 xaddr register + addressOffset: 2440 + size: 32 + fields: + - name: IN_CMDFIFO_XADDR_CH4 + description: only for debug + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_BUF_HB_RCV_CH4 + description: rx CH4 buf len hb rcv register + addressOffset: 2444 + size: 32 + fields: + - name: IN_CMDFIFO_BUF_HB_RCV_CH4 + description: only for debug + bitOffset: 0 + bitWidth: 29 + access: read-only + - register: + name: IN_CONF0_CH5 + description: RX CH5 config0 register + addressOffset: 2560 + size: 32 + fields: + - name: IN_ECC_AES_EN_CH5 + description: "When access address space is ecc/aes area, this bit should be set to 1. In this case, the start address of square should be 16-bit aligned. The width of square multiply byte number of one pixel should be 16-bit aligned." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: IN_MEM_BURST_LENGTH_CH5 + description: "Block size of Rx channel 1. 0: single 1: 16 bytes 2: 32 bytes 3: 64 bytes 4: 128 bytes" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: IN_PAGE_BOUND_EN_CH5 + description: "Set this bit to 1 to make sure AXI write data don't cross the address boundary which define by mem_burst_length" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: IN_RST_CH5 + description: Write 1 then write 0 to this bit to reset Rx channel + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: IN_CMD_DISABLE_CH5 + description: Write 1 before reset and write 0 after reset + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: IN_CONF1_CH5 + description: RX CH5 config1 register + addressOffset: 2564 + size: 32 + fields: + - name: BLOCK_START_ADDR_CH5 + description: RX Channel 5 destination start address + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: IN_CONF2_CH5 + description: RX CH5 config2 register + addressOffset: 2568 + size: 32 + resetValue: 1006663680 + fields: + - name: BLOCK_ROW_LENGTH_12LINE_CH5 + description: The number of bytes contained in a row block 12line in RX channel 5 + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: BLOCK_ROW_LENGTH_4LINE_CH5 + description: The number of bytes contained in a row block 4line in RX channel 5 + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: IN_CONF3_CH5 + description: RX CH5 config3 register + addressOffset: 2572 + size: 32 + resetValue: 2097408 + fields: + - name: BLOCK_LENGTH_12LINE_CH5 + description: The number of bytes contained in a block 12line + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: BLOCK_LENGTH_4LINE_CH5 + description: The number of bytes contained in a block 4line + bitOffset: 14 + bitWidth: 14 + access: read-write + - register: + name: IN_INT_RAW_CH5 + description: RX CH5 interrupt raw register + addressOffset: 2576 + size: 32 + fields: + - name: IN_DONE_CH5_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been transmitted to peripherals for Rx channel 1. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF_CH5_INT_RAW + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L1_CH5_INT_RAW + description: This raw interrupt bit turns to high level when fifo of Rx channel is overflow. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L1_CH5_INT_RAW + description: This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FETCH_MB_COL_CNT_OVF_CH5_INT_RAW + description: This raw interrupt bit turns to high level when fifo of Rx channel is underflow. + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: IN_INT_ENA_CH5 + description: RX CH5 interrupt ena register + addressOffset: 2580 + size: 32 + fields: + - name: IN_DONE_CH5_INT_ENA + description: The interrupt enable bit for the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF_CH5_INT_ENA + description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L1_CH5_INT_ENA + description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L1_CH5_INT_ENA + description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FETCH_MB_COL_CNT_OVF_CH5_INT_ENA + description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: IN_INT_ST_CH5 + description: RX CH5 interrupt st register + addressOffset: 2584 + size: 32 + fields: + - name: IN_DONE_CH5_INT_ST + description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: IN_SUC_EOF_CH5_INT_ST + description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: INFIFO_OVF_L1_CH5_INT_ST + description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: INFIFO_UDF_L1_CH5_INT_ST + description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: FETCH_MB_COL_CNT_OVF_CH5_INT_ST + description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - register: + name: IN_INT_CLR_CH5 + description: RX CH5 interrupt clr register + addressOffset: 2588 + size: 32 + fields: + - name: IN_DONE_CH5_INT_CLR + description: Set this bit to clear the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: IN_SUC_EOF_CH5_INT_CLR + description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: INFIFO_OVF_L1_CH5_INT_CLR + description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: INFIFO_UDF_L1_CH5_INT_CLR + description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: FETCH_MB_COL_CNT_OVF_CH5_INT_CLR + description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - register: + name: INFIFO_STATUS_CH5 + description: RX CH5 INFIFO status register + addressOffset: 2592 + size: 32 + resetValue: 2 + fields: + - name: INFIFO_FULL_L1_CH5 + description: Tx FIFO full signal for Tx channel 1. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: INFIFO_EMPTY_L1_CH5 + description: Tx FIFO empty signal for Tx channel 1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: INFIFO_CNT_L1_CH5 + description: The register stores the byte number of the data in Tx FIFO for Tx channel 1. + bitOffset: 2 + bitWidth: 5 + access: read-only + - register: + name: IN_POP_CH5 + description: RX CH5 INFIFO pop register + addressOffset: 2596 + size: 32 + resetValue: 1024 + fields: + - name: INFIFO_RDATA_CH5 + description: This register stores the data popping from DMA Rx FIFO. + bitOffset: 0 + bitWidth: 11 + access: read-only + - name: INFIFO_POP_CH5 + description: Set this bit to pop data from DMA Rx FIFO. + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: IN_STATE_CH5 + description: RX CH5 state register + addressOffset: 2600 + size: 32 + resetValue: 8 + fields: + - name: IN_STATE_CH5 + description: This register stores the current control module state machine state. + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: IN_RESET_AVAIL_CH5 + description: This register indicate that if the channel reset is safety. + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: IN_ARB_CH5 + description: RX CH5 arb register + addressOffset: 2624 + size: 32 + resetValue: 65 + fields: + - name: IN_ARB_TOKEN_NUM_CH5 + description: Set the max number of token count of arbiter + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: INTER_IN_ARB_PRIORITY_CH5 + description: Set the priority of channel + bitOffset: 6 + bitWidth: 3 + access: read-write + - register: + name: IN_FIFO_CNT_CH5 + description: rx CH5 fifo cnt register + addressOffset: 2688 + size: 32 + fields: + - name: IN_CMDFIFO_INFIFO_CNT_CH5 + description: only for debug + bitOffset: 0 + bitWidth: 10 + access: read-only + - register: + name: IN_POP_DATA_CNT_CH5 + description: rx CH5 pop data cnt register + addressOffset: 2692 + size: 32 + resetValue: 255 + fields: + - name: IN_CMDFIFO_POP_DATA_CNT_CH5 + description: only for debug + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: IN_XADDR_CH5 + description: rx CH5 xaddr register + addressOffset: 2696 + size: 32 + fields: + - name: IN_CMDFIFO_XADDR_CH5 + description: only for debug + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_BUF_HB_RCV_CH5 + description: rx CH5 buf len hb rcv register + addressOffset: 2700 + size: 32 + fields: + - name: IN_CMDFIFO_BUF_HB_RCV_CH5 + description: only for debug + bitOffset: 0 + bitWidth: 29 + access: read-only + - register: + name: INTER_AXI_ERR + description: inter memory axi err register + addressOffset: 2816 + size: 32 + fields: + - name: INTER_RID_ERR_CNT + description: AXI read id err cnt + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: INTER_RRESP_ERR_CNT + description: AXI read resp err cnt + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: INTER_WRESP_ERR_CNT + description: AXI write resp err cnt + bitOffset: 8 + bitWidth: 4 + access: read-only + - name: INTER_RD_FIFO_CNT + description: AXI read cmd fifo remain cmd count + bitOffset: 12 + bitWidth: 3 + access: read-only + - name: INTER_RD_BAK_FIFO_CNT + description: AXI read backup cmd fifo remain cmd count + bitOffset: 15 + bitWidth: 4 + access: read-only + - name: INTER_WR_FIFO_CNT + description: AXI write cmd fifo remain cmd count + bitOffset: 19 + bitWidth: 3 + access: read-only + - name: INTER_WR_BAK_FIFO_CNT + description: AXI write backup cmd fifo remain cmd count + bitOffset: 22 + bitWidth: 4 + access: read-only + - register: + name: EXTER_AXI_ERR + description: exter memory axi err register + addressOffset: 2820 + size: 32 + fields: + - name: EXTER_RID_ERR_CNT + description: AXI read id err cnt + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: EXTER_RRESP_ERR_CNT + description: AXI read resp err cnt + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: EXTER_WRESP_ERR_CNT + description: AXI write resp err cnt + bitOffset: 8 + bitWidth: 4 + access: read-only + - name: EXTER_RD_FIFO_CNT + description: AXI read cmd fifo remain cmd count + bitOffset: 12 + bitWidth: 3 + access: read-only + - name: EXTER_RD_BAK_FIFO_CNT + description: AXI read backup cmd fifo remain cmd count + bitOffset: 15 + bitWidth: 4 + access: read-only + - name: EXTER_WR_FIFO_CNT + description: AXI write cmd fifo remain cmd count + bitOffset: 19 + bitWidth: 3 + access: read-only + - name: EXTER_WR_BAK_FIFO_CNT + description: AXI write backup cmd fifo remain cmd count + bitOffset: 22 + bitWidth: 4 + access: read-only + - register: + name: RST_CONF + description: axi reset config register + addressOffset: 2824 + size: 32 + fields: + - name: INTER_AXIM_RD_RST + description: Write 1 then write 0 to this bit to reset axi master read data FIFO. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: INTER_AXIM_WR_RST + description: Write 1 then write 0 to this bit to reset axi master write data FIFO. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EXTER_AXIM_RD_RST + description: Write 1 then write 0 to this bit to reset axi master read data FIFO. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EXTER_AXIM_WR_RST + description: Write 1 then write 0 to this bit to reset axi master write data FIFO. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers." + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: INTER_MEM_START_ADDR0 + description: Start address of inter memory range0 register + addressOffset: 2828 + size: 32 + resetValue: 806354944 + fields: + - name: ACCESS_INTER_MEM_START_ADDR0 + description: The start address of accessible address space. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: INTER_MEM_END_ADDR0 + description: end address of inter memory range0 register + addressOffset: 2832 + size: 32 + resetValue: 2415919103 + fields: + - name: ACCESS_INTER_MEM_END_ADDR0 + description: The end address of accessible address space. The access address beyond this range would lead to descriptor error. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: INTER_MEM_START_ADDR1 + description: Start address of inter memory range1 register + addressOffset: 2836 + size: 32 + resetValue: 806354944 + fields: + - name: ACCESS_INTER_MEM_START_ADDR1 + description: The start address of accessible address space. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: INTER_MEM_END_ADDR1 + description: end address of inter memory range1 register + addressOffset: 2840 + size: 32 + resetValue: 2415919103 + fields: + - name: ACCESS_INTER_MEM_END_ADDR1 + description: The end address of accessible address space. The access address beyond this range would lead to descriptor error. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: EXTER_MEM_START_ADDR0 + description: Start address of exter memory range0 register + addressOffset: 2848 + size: 32 + resetValue: 806354944 + fields: + - name: ACCESS_EXTER_MEM_START_ADDR0 + description: The start address of accessible address space. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: EXTER_MEM_END_ADDR0 + description: end address of exter memory range0 register + addressOffset: 2852 + size: 32 + resetValue: 2415919103 + fields: + - name: ACCESS_EXTER_MEM_END_ADDR0 + description: The end address of accessible address space. The access address beyond this range would lead to descriptor error. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: EXTER_MEM_START_ADDR1 + description: Start address of exter memory range1 register + addressOffset: 2856 + size: 32 + resetValue: 806354944 + fields: + - name: ACCESS_EXTER_MEM_START_ADDR1 + description: The start address of accessible address space. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: EXTER_MEM_END_ADDR1 + description: end address of exter memory range1 register + addressOffset: 2860 + size: 32 + resetValue: 2415919103 + fields: + - name: ACCESS_EXTER_MEM_END_ADDR1 + description: The end address of accessible address space. The access address beyond this range would lead to descriptor error. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: OUT_ARB_CONFIG + description: reserved + addressOffset: 2864 + size: 32 + fields: + - name: OUT_ARB_TIMEOUT_NUM + description: Set the max number of timeout count of arbiter + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: OUT_WEIGHT_EN + description: reserved + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: IN_ARB_CONFIG + description: reserved + addressOffset: 2868 + size: 32 + fields: + - name: IN_ARB_TIMEOUT_NUM + description: Set the max number of timeout count of arbiter + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: IN_WEIGHT_EN + description: reserved + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: reserved + addressOffset: 2876 + size: 32 + resetValue: 539165699 + fields: + - name: DATE + description: register version. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: COUNTER_RST + description: counter reset register + addressOffset: 2896 + size: 32 + fields: + - name: RX_CH0_EXTER_COUNTER_RST + description: Write 1 then write 0 to this bit to reset rx ch0 counter. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_CH1_EXTER_COUNTER_RST + description: Write 1 then write 0 to this bit to reset rx ch1 counter. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_CH2_INTER_COUNTER_RST + description: Write 1 then write 0 to this bit to reset rx ch2 counter. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_CH5_INTER_COUNTER_RST + description: Write 1 then write 0 to this bit to reset rx ch5 counter. + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: RX_CH0_COUNTER + description: rx ch0 counter register + addressOffset: 2900 + size: 32 + fields: + - name: RX_CH0_CNT + description: rx ch0 counter register + bitOffset: 0 + bitWidth: 23 + access: read-only + - register: + name: RX_CH1_COUNTER + description: rx ch1 counter register + addressOffset: 2904 + size: 32 + fields: + - name: RX_CH1_CNT + description: rx ch1 counter register + bitOffset: 0 + bitWidth: 21 + access: read-only + - register: + name: RX_CH2_COUNTER + description: rx ch2 counter register + addressOffset: 2908 + size: 32 + fields: + - name: RX_CH2_CNT + description: rx ch2 counter register + bitOffset: 0 + bitWidth: 11 + access: read-only + - register: + name: RX_CH5_COUNTER + description: rx ch5 counter register + addressOffset: 2912 + size: 32 + fields: + - name: RX_CH5_CNT + description: rx ch5 counter register + bitOffset: 0 + bitWidth: 17 + access: read-only + - name: HMAC + description: HMAC (Hash-based Message Authentication Code) Accelerator + groupName: HMAC + baseAddress: 1342787584 + addressBlock: + - offset: 0 + size: 164 + usage: registers + registers: + - register: + name: SET_START + description: Process control register 0. + addressOffset: 64 + size: 32 + fields: + - name: SET_START + description: Start hmac operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_PARA_PURPOSE + description: Configure purpose. + addressOffset: 68 + size: 32 + fields: + - name: PURPOSE_SET + description: Set hmac parameter purpose. + bitOffset: 0 + bitWidth: 4 + access: write-only + - register: + name: SET_PARA_KEY + description: Configure key. + addressOffset: 72 + size: 32 + fields: + - name: KEY_SET + description: Set hmac parameter key. + bitOffset: 0 + bitWidth: 3 + access: write-only + - register: + name: SET_PARA_FINISH + description: Finish initial configuration. + addressOffset: 76 + size: 32 + fields: + - name: SET_PARA_END + description: Finish hmac configuration. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_MESSAGE_ONE + description: Process control register 1. + addressOffset: 80 + size: 32 + fields: + - name: SET_TEXT_ONE + description: Call SHA to calculate one message block. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_MESSAGE_ING + description: Process control register 2. + addressOffset: 84 + size: 32 + fields: + - name: SET_TEXT_ING + description: Continue typical hmac. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_MESSAGE_END + description: Process control register 3. + addressOffset: 88 + size: 32 + fields: + - name: SET_TEXT_END + description: Start hardware padding. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_RESULT_FINISH + description: Process control register 4. + addressOffset: 92 + size: 32 + fields: + - name: SET_RESULT_END + description: "After read result from upstream, then let hmac back to idle." + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_INVALIDATE_JTAG + description: Invalidate register 0. + addressOffset: 96 + size: 32 + fields: + - name: SET_INVALIDATE_JTAG + description: Clear result from hmac downstream JTAG. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_INVALIDATE_DS + description: Invalidate register 1. + addressOffset: 100 + size: 32 + fields: + - name: SET_INVALIDATE_DS + description: Clear result from hmac downstream DS. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: QUERY_ERROR + description: Error register. + addressOffset: 104 + size: 32 + fields: + - name: QUERY_CHECK + description: "Hmac configuration state. 0: key are agree with purpose. 1: error" + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: QUERY_BUSY + description: Busy register. + addressOffset: 108 + size: 32 + fields: + - name: BUSY_STATE + description: "Hmac state. 1'b0: idle. 1'b1: busy" + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + dim: 16 + dimIncrement: 4 + name: "WR_MESSAGE_MEM[%s]" + description: Message block memory. + addressOffset: 128 + size: 32 + - register: + dim: 8 + dimIncrement: 4 + name: "RD_RESULT_MEM[%s]" + description: Result from upstream. + addressOffset: 192 + size: 32 + - register: + name: SET_MESSAGE_PAD + description: Process control register 5. + addressOffset: 240 + size: 32 + fields: + - name: SET_TEXT_PAD + description: Start software padding. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: ONE_BLOCK + description: Process control register 6. + addressOffset: 244 + size: 32 + fields: + - name: SET_ONE_BLOCK + description: "Don't have to do padding." + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SOFT_JTAG_CTRL + description: Jtag register 0. + addressOffset: 248 + size: 32 + fields: + - name: SOFT_JTAG_CTRL + description: Turn on JTAG verification. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: WR_JTAG + description: Jtag register 1. + addressOffset: 252 + size: 32 + fields: + - name: WR_JTAG + description: 32-bit of key to be compared. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: DATE + description: Date register. + addressOffset: 508 + size: 32 + resetValue: 538969624 + fields: + - name: DATE + description: Hmac date information/ hmac version information. + bitOffset: 0 + bitWidth: 30 + access: read-write + - name: HP_SYS + description: High-Power System + groupName: HP_SYS + baseAddress: 1343115264 + addressBlock: + - offset: 0 + size: 364 + usage: registers + interrupt: + - name: HP_SYS + value: 110 + registers: + - register: + name: VER_DATE + description: NA + addressOffset: 0 + size: 32 + resetValue: 539165977 + fields: + - name: REG_VER_DATE + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CLK_EN + description: NA + addressOffset: 4 + size: 32 + fields: + - name: REG_CLK_EN + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_0 + description: NA + addressOffset: 16 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_0 + description: set 1 will triger a interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_1 + description: NA + addressOffset: 20 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_1 + description: set 1 will triger a interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_2 + description: NA + addressOffset: 24 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_2 + description: set 1 will triger a interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_3 + description: NA + addressOffset: 28 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_3 + description: set 1 will triger a interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CACHE_CLK_CONFIG + description: NA + addressOffset: 32 + size: 32 + resetValue: 51 + fields: + - name: REG_L2_CACHE_CLK_ON + description: l2 cahce clk enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_L1_D_CACHE_CLK_ON + description: l1 dcahce clk enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_L1_I1_CACHE_CLK_ON + description: l1 icahce1 clk enable + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_L1_I0_CACHE_CLK_ON + description: l1 icahce0 clk enable + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: CACHE_RESET_CONFIG + description: NA + addressOffset: 36 + size: 32 + fields: + - name: REG_L1_D_CACHE_RESET + description: set 1 to reset l1 dcahce + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_L1_I1_CACHE_RESET + description: set 1 to reset l1 icahce1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_L1_I0_CACHE_RESET + description: set 1 to reset l1 icahce0 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: DMA_ADDR_CTRL + description: NA + addressOffset: 44 + size: 32 + fields: + - name: REG_SYS_DMA_ADDR_SEL + description: 0 means dma access extmem use 8xxx_xxxx else use 4xxx_xxxx + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: TCM_RAM_WRR_CONFIG + description: NA + addressOffset: 52 + size: 32 + resetValue: 2188302655 + fields: + - name: REG_TCM_RAM_IBUS0_WT + description: weight value of ibus0 + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: REG_TCM_RAM_IBUS1_WT + description: weight value of ibus1 + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: REG_TCM_RAM_IBUS2_WT + description: weight value of ibus2 + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: REG_TCM_RAM_IBUS3_WT + description: weight value of ibus3 + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: REG_TCM_RAM_DBUS0_WT + description: weight value of dbus0 + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: REG_TCM_RAM_DBUS1_WT + description: weight value of dbus1 + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: REG_TCM_RAM_DBUS2_WT + description: weight value of dbus2 + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: REG_TCM_RAM_DBUS3_WT + description: weight value of dbus3 + bitOffset: 21 + bitWidth: 3 + access: read-write + - name: REG_TCM_RAM_DMA_WT + description: weight value of dma + bitOffset: 24 + bitWidth: 3 + access: read-write + - name: REG_TCM_RAM_WRR_HIGH + description: enable weighted round robin arbitration + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TCM_SW_PARITY_BWE_MASK + description: NA + addressOffset: 56 + size: 32 + fields: + - name: REG_TCM_SW_PARITY_BWE_MASK_CTRL + description: Set 1 to mask tcm bwe parity code bit + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: TCM_RAM_PWR_CTRL0 + description: NA + addressOffset: 60 + size: 32 + fields: + - name: REG_HP_TCM_CLK_FORCE_ON + description: hp_tcm clk gatig force on + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: L2_ROM_PWR_CTRL0 + description: NA + addressOffset: 64 + size: 32 + fields: + - name: REG_L2_ROM_CLK_FORCE_ON + description: l2_rom clk gating force on + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: PROBEA_CTRL + description: NA + addressOffset: 80 + size: 32 + fields: + - name: REG_PROBE_A_MOD_SEL + description: "Tihs field is used to selec probe_group from probe_group0 to probe_group15 for module's probe_out[31:0] in a mode" + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: REG_PROBE_A_TOP_SEL + description: "Tihs field is used to selec module's probe_out[31:0] as probe out in a mode" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: REG_PROBE_L_SEL + description: "Tihs field is used to selec probe_out[31:16]" + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: REG_PROBE_H_SEL + description: "Tihs field is used to selec probe_out[31:16]" + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: REG_PROBE_GLOBAL_EN + description: Set this bit to enable global debug probe in hp system. + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: PROBEB_CTRL + description: NA + addressOffset: 84 + size: 32 + fields: + - name: REG_PROBE_B_MOD_SEL + description: "Tihs field is used to selec probe_group from probe_group0 to probe_group15 for module's probe_out[31:0] in b mode." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: REG_PROBE_B_TOP_SEL + description: "Tihs field is used to select module's probe_out[31:0] as probe_out in b mode" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: REG_PROBE_B_EN + description: "Set this bit to enable b mode for debug probe. 1: b mode, 0: a mode." + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: PROBE_OUT + description: NA + addressOffset: 92 + size: 32 + fields: + - name: REG_PROBE_TOP_OUT + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: L2_MEM_RAM_PWR_CTRL0 + description: NA + addressOffset: 96 + size: 32 + fields: + - name: REG_L2_MEM_CLK_FORCE_ON + description: l2ram clk_gating force on + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_CORESTALLED_ST + description: NA + addressOffset: 100 + size: 32 + fields: + - name: REG_CORE0_CORESTALLED_ST + description: hp core0 corestalled status + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: REG_CORE1_CORESTALLED_ST + description: hp core1 corestalled status + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: CRYPTO_CTRL + description: NA + addressOffset: 112 + size: 32 + fields: + - name: REG_ENABLE_SPI_MANUAL_ENCRYPT + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_ENABLE_DOWNLOAD_DB_ENCRYPT + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_ENABLE_DOWNLOAD_G0CB_DECRYPT + description: NA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT + description: NA + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: GPIO_O_HOLD_CTRL0 + description: NA + addressOffset: 116 + size: 32 + fields: + - name: REG_GPIO_0_HOLD_LOW + description: hold control for gpio47~16 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: GPIO_O_HOLD_CTRL1 + description: NA + addressOffset: 120 + size: 32 + fields: + - name: REG_GPIO_0_HOLD_HIGH + description: hold control for gpio56~48 + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: RDN_ECO_CS + description: NA + addressOffset: 124 + size: 32 + fields: + - name: REG_HP_SYS_RDN_ECO_EN + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_HP_SYS_RDN_ECO_RESULT + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: CACHE_APB_POSTW_EN + description: NA + addressOffset: 128 + size: 32 + fields: + - name: REG_CACHE_APB_POSTW_EN + description: "cache apb register interface post write enable, 1 will speed up write, but will take some time to update value to register" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: L2_MEM_SUBSIZE + description: NA + addressOffset: 132 + size: 32 + fields: + - name: REG_L2_MEM_SUB_BLKSIZE + description: l2mem sub block size 00=>32 01=>64 10=>128 11=>256 + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: L2_MEM_INT_RAW + description: NA + addressOffset: 156 + size: 32 + fields: + - name: REG_L2_MEM_ECC_ERR_INT_RAW + description: intr triggered when two bit error detected and corrected from ecc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_L2_MEM_EXCEED_ADDR_INT_RAW + description: intr triggered when access addr exceeds 0xff9ffff at bypass mode or exceeds 0xff80000 at l2cache 128kb mode or exceeds 0xff60000 at l2cache 256kb mode + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_L2_MEM_ERR_RESP_INT_RAW + description: intr triggered when err response occurs + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: L2_MEM_INT_ST + description: NA + addressOffset: 160 + size: 32 + fields: + - name: REG_L2_MEM_ECC_ERR_INT_ST + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: REG_L2_MEM_EXCEED_ADDR_INT_ST + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: REG_L2_MEM_ERR_RESP_INT_ST + description: NA + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: L2_MEM_INT_ENA + description: NA + addressOffset: 164 + size: 32 + fields: + - name: REG_L2_MEM_ECC_ERR_INT_ENA + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_L2_MEM_EXCEED_ADDR_INT_ENA + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_L2_MEM_ERR_RESP_INT_ENA + description: NA + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: L2_MEM_INT_CLR + description: NA + addressOffset: 168 + size: 32 + fields: + - name: REG_L2_MEM_ECC_ERR_INT_CLR + description: NA + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: REG_L2_MEM_EXCEED_ADDR_INT_CLR + description: NA + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: REG_L2_MEM_ERR_RESP_INT_CLR + description: NA + bitOffset: 2 + bitWidth: 1 + access: write-only + - register: + name: L2_MEM_L2_RAM_ECC + description: NA + addressOffset: 172 + size: 32 + fields: + - name: REG_L2_RAM_UNIT0_ECC_EN + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_L2_RAM_UNIT1_ECC_EN + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_L2_RAM_UNIT2_ECC_EN + description: NA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_L2_RAM_UNIT3_ECC_EN + description: NA + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: REG_L2_RAM_UNIT4_ECC_EN + description: NA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_L2_RAM_UNIT5_ECC_EN + description: NA + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: L2_MEM_INT_RECORD0 + description: NA + addressOffset: 176 + size: 32 + fields: + - name: REG_L2_MEM_EXCEED_ADDR_INT_ADDR + description: NA + bitOffset: 0 + bitWidth: 21 + access: read-only + - name: REG_L2_MEM_EXCEED_ADDR_INT_WE + description: NA + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: REG_L2_MEM_EXCEED_ADDR_INT_MASTER + description: NA + bitOffset: 22 + bitWidth: 3 + access: read-only + - register: + name: L2_MEM_INT_RECORD1 + description: NA + addressOffset: 180 + size: 32 + fields: + - name: REG_L2_MEM_ECC_ERR_INT_ADDR + description: NA + bitOffset: 0 + bitWidth: 15 + access: read-only + - name: REG_L2_MEM_ECC_ONE_BIT_ERR + description: NA + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: REG_L2_MEM_ECC_TWO_BIT_ERR + description: NA + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: REG_L2_MEM_ECC_ERR_BIT + description: NA + bitOffset: 17 + bitWidth: 9 + access: read-only + - name: REG_L2_CACHE_ERR_BANK + description: NA + bitOffset: 26 + bitWidth: 1 + access: read-only + - register: + name: L2_MEM_L2_CACHE_ECC + description: NA + addressOffset: 196 + size: 32 + fields: + - name: REG_L2_CACHE_ECC_EN + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: L1CACHE_BUS0_ID + description: NA + addressOffset: 200 + size: 32 + fields: + - name: REG_L1_CACHE_BUS0_ID + description: NA + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: L1CACHE_BUS1_ID + description: NA + addressOffset: 204 + size: 32 + fields: + - name: REG_L1_CACHE_BUS1_ID + description: NA + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: L2_MEM_RDN_ECO_CS + description: NA + addressOffset: 216 + size: 32 + fields: + - name: REG_L2_MEM_RDN_ECO_EN + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_L2_MEM_RDN_ECO_RESULT + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: L2_MEM_RDN_ECO_LOW + description: NA + addressOffset: 220 + size: 32 + fields: + - name: REG_L2_MEM_RDN_ECO_LOW + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: L2_MEM_RDN_ECO_HIGH + description: NA + addressOffset: 224 + size: 32 + resetValue: 4294967295 + fields: + - name: REG_L2_MEM_RDN_ECO_HIGH + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TCM_RDN_ECO_CS + description: NA + addressOffset: 228 + size: 32 + fields: + - name: REG_HP_TCM_RDN_ECO_EN + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_HP_TCM_RDN_ECO_RESULT + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: TCM_RDN_ECO_LOW + description: NA + addressOffset: 232 + size: 32 + fields: + - name: REG_HP_TCM_RDN_ECO_LOW + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TCM_RDN_ECO_HIGH + description: NA + addressOffset: 236 + size: 32 + resetValue: 4294967295 + fields: + - name: REG_HP_TCM_RDN_ECO_HIGH + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: GPIO_DED_HOLD_CTRL + description: NA + addressOffset: 240 + size: 32 + fields: + - name: REG_GPIO_DED_HOLD + description: hold control for gpio63~56 + bitOffset: 0 + bitWidth: 26 + access: read-write + - register: + name: L2_MEM_SW_ECC_BWE_MASK + description: NA + addressOffset: 244 + size: 32 + fields: + - name: REG_L2_MEM_SW_ECC_BWE_MASK_CTRL + description: Set 1 to mask bwe hamming code bit + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: USB20OTG_MEM_CTRL + description: NA + addressOffset: 248 + size: 32 + fields: + - name: REG_USB20_MEM_CLK_FORCE_ON + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: TCM_INT_RAW + description: need_des + addressOffset: 252 + size: 32 + fields: + - name: TCM_PARITY_ERR_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TCM_INT_ST + description: need_des + addressOffset: 256 + size: 32 + fields: + - name: TCM_PARITY_ERR_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: TCM_INT_ENA + description: need_des + addressOffset: 260 + size: 32 + fields: + - name: TCM_PARITY_ERR_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TCM_INT_CLR + description: need_des + addressOffset: 264 + size: 32 + fields: + - name: TCM_PARITY_ERR_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: TCM_PARITY_INT_RECORD + description: need_des + addressOffset: 268 + size: 32 + fields: + - name: TCM_PARITY_ERR_INT_ADDR + description: hp tcm_parity_err_addr + bitOffset: 0 + bitWidth: 13 + access: read-only + - register: + name: L1_CACHE_PWR_CTRL + description: NA + addressOffset: 272 + size: 32 + fields: + - name: REG_L1_CACHE_MEM_FO + description: need_des + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: L2_CACHE_PWR_CTRL + description: NA + addressOffset: 276 + size: 32 + fields: + - name: REG_L2_CACHE_MEM_FO + description: need_des + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: CPU_WAITI_CONF + description: CPU_WAITI configuration register + addressOffset: 280 + size: 32 + resetValue: 1 + fields: + - name: CPU_WAIT_MODE_FORCE_ON + description: Set 1 to force cpu_waiti_clk enable. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CPU_WAITI_DELAY_NUM + description: "This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close" + bitOffset: 1 + bitWidth: 4 + access: read-write + - register: + name: CORE_DEBUG_RUNSTALL_CONF + description: Core Debug runstall configure register + addressOffset: 284 + size: 32 + fields: + - name: CORE_DEBUG_RUNSTALL_ENABLE + description: Set this field to 1 to enable debug runstall feature between HP-core and LP-core. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_AHB_TIMEOUT + description: need_des + addressOffset: 288 + size: 32 + resetValue: 131071 + fields: + - name: EN + description: set this field to 1 to enable hp core0&1 ahb timeout handle + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: THRES + description: This field used to set hp core0&1 ahb bus timeout threshold + bitOffset: 1 + bitWidth: 16 + access: read-write + - register: + name: CORE_IBUS_TIMEOUT + description: need_des + addressOffset: 292 + size: 32 + resetValue: 131071 + fields: + - name: EN + description: set this field to 1 to enable hp core0&1 ibus timeout handle + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: THRES + description: This field used to set hp core0&1 ibus timeout threshold + bitOffset: 1 + bitWidth: 16 + access: read-write + - register: + name: CORE_DBUS_TIMEOUT + description: need_des + addressOffset: 296 + size: 32 + resetValue: 131071 + fields: + - name: EN + description: set this field to 1 to enable hp core0&1 dbus timeout handle + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: THRES + description: This field used to set hp core0&1 dbus timeout threshold + bitOffset: 1 + bitWidth: 16 + access: read-write + - register: + name: ICM_CPU_H2X_CFG + description: need_des + addressOffset: 312 + size: 32 + resetValue: 3 + fields: + - name: CPU_ICM_H2X_POST_WR_EN + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CPU_ICM_H2X_CUT_THROUGH_EN + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CPU_ICM_H2X_BRIDGE_BUSY + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: PERI1_APB_POSTW_EN + description: NA + addressOffset: 316 + size: 32 + fields: + - name: PERI1_APB_POSTW_EN + description: "hp_peri1 apb register interface post write enable, 1 will speed up write, but will take some time to update value to register" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: BITSCRAMBLER_PERI_SEL + description: Bitscrambler Peri Sel + addressOffset: 320 + size: 32 + resetValue: 255 + fields: + - name: BITSCRAMBLER_PERI_RX_SEL + description: "Set this field to sel peri with DMA RX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none" + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: BITSCRAMBLER_PERI_TX_SEL + description: "Set this field to sel peri with DMA TX interface to connec with bitscrambler: 4'h0 : lcd_cam, 4'h1: gpspi2, 4'h2: gpspi3, 4'h3: parl_io, 4'h4: aes, 4'h5: sha, 4'h6: adc, 4'h7: i2s0, 4'h8: i2s1, 4'h9: i2s2, 4'ha: i3c_mst, 4'hb: uhci0, 4'hc: RMT, else : none" + bitOffset: 4 + bitWidth: 4 + access: read-write + - register: + name: APB_SYNC_POSTW_EN + description: N/A + addressOffset: 324 + size: 32 + fields: + - name: GMAC_APB_POSTW_EN + description: N/A + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DSI_HOST_APB_POSTW_EN + description: N/A + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CSI_HOST_APB_SYNC_POSTW_EN + description: N/A + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CSI_HOST_APB_ASYNC_POSTW_EN + description: N/A + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: GDMA_CTRL + description: N/A + addressOffset: 328 + size: 32 + fields: + - name: DEBUG_CH_NUM + description: N/A + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: GMAC_CTRL0 + description: N/A + addressOffset: 332 + size: 32 + fields: + - name: PTP_PPS + description: N/A + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SBD_FLOWCTRL + description: N/A + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PHY_INTF_SEL + description: N/A + bitOffset: 2 + bitWidth: 3 + access: read-write + - name: GMAC_MEM_CLK_FORCE_ON + description: N/A + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: GMAC_RST_CLK_TX_N + description: N/A + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: GMAC_RST_CLK_RX_N + description: N/A + bitOffset: 7 + bitWidth: 1 + access: read-only + - register: + name: GMAC_CTRL1 + description: N/A + addressOffset: 336 + size: 32 + fields: + - name: PTP_TIMESTAMP_L + description: N/A + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: GMAC_CTRL2 + description: N/A + addressOffset: 340 + size: 32 + fields: + - name: PTP_TIMESTAMP_H + description: N/A + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: VPU_CTRL + description: N/A + addressOffset: 344 + size: 32 + fields: + - name: PPA_LSLP_MEM_PD + description: N/A + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: JPEG_SDSLP_MEM_PD + description: N/A + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: JPEG_LSLP_MEM_PD + description: N/A + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: JPEG_DSLP_MEM_PD + description: N/A + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DMA2D_LSLP_MEM_PD + description: N/A + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: USBOTG20_CTRL + description: N/A + addressOffset: 348 + size: 32 + resetValue: 8529472 + fields: + - name: OTG_PHY_TEST_DONE + description: N/A + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: USB_MEM_AUX_CTRL + description: N/A + bitOffset: 1 + bitWidth: 14 + access: read-write + - name: PHY_SUSPENDM + description: N/A + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: PHY_SUSPEND_FORCE_EN + description: N/A + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PHY_RSTN + description: N/A + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: PHY_RESET_FORCE_EN + description: N/A + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: PHY_PLL_FORCE_EN + description: N/A + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PHY_PLL_EN + description: N/A + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: OTG_SUSPENDM + description: N/A + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: OTG_PHY_TXBITSTUFF_EN + description: N/A + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: OTG_PHY_REFCLK_MODE + description: N/A + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: OTG_PHY_BISTEN + description: N/A + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: TCM_ERR_RESP_CTRL + description: need_des + addressOffset: 352 + size: 32 + fields: + - name: TCM_ERR_RESP_EN + description: Set 1 to turn on tcm error response + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: L2_MEM_REFRESH + description: NA + addressOffset: 356 + size: 32 + resetValue: 64 + fields: + - name: REG_L2_MEM_UNIT0_REFERSH_EN + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_L2_MEM_UNIT1_REFERSH_EN + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_L2_MEM_UNIT2_REFERSH_EN + description: NA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_L2_MEM_UNIT3_REFERSH_EN + description: NA + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: REG_L2_MEM_UNIT4_REFERSH_EN + description: NA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_L2_MEM_UNIT5_REFERSH_EN + description: NA + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REG_L2_MEM_REFERSH_CNT_RESET + description: Set 1 to reset l2mem_refresh_cnt + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REG_L2_MEM_UNIT0_REFRESH_DONE + description: NA + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: REG_L2_MEM_UNIT1_REFRESH_DONE + description: NA + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: REG_L2_MEM_UNIT2_REFRESH_DONE + description: NA + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: REG_L2_MEM_UNIT3_REFRESH_DONE + description: NA + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: REG_L2_MEM_UNIT4_REFRESH_DONE + description: NA + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: REG_L2_MEM_UNIT5_REFRESH_DONE + description: NA + bitOffset: 12 + bitWidth: 1 + access: read-only + - register: + name: TCM_INIT + description: NA + addressOffset: 360 + size: 32 + resetValue: 2 + fields: + - name: REG_TCM_INIT_EN + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_TCM_INIT_CNT_RESET + description: Set 1 to reset tcm init cnt + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_TCM_INIT_DONE + description: NA + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: TCM_PARITY_CHECK_CTRL + description: need_des + addressOffset: 364 + size: 32 + fields: + - name: TCM_PARITY_CHECK_EN + description: Set 1 to turn on tcm parity check + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DESIGN_FOR_VERIFICATION0 + description: need_des + addressOffset: 368 + size: 32 + fields: + - name: DFV0 + description: register for DV + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DESIGN_FOR_VERIFICATION1 + description: need_des + addressOffset: 372 + size: 32 + fields: + - name: DFV1 + description: register for DV + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PSRAM_FLASH_ADDR_INTERCHANGE + description: need_des + addressOffset: 384 + size: 32 + fields: + - name: CPU + description: Set 1 to enable addr interchange between psram and flash in axi matrix when hp cpu access through cache + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DMA + description: "Set 1 to enable addr interchange between psram and flash in axi matrix when dma device access, lp core access and hp core access through ahb" + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: AHB2AXI_BRESP_ERR_INT_RAW + description: NA + addressOffset: 392 + size: 32 + fields: + - name: CPU_ICM_H2X_BRESP_ERR_INT_RAW + description: "the raw interrupt status of bresp error, triggered when if bresp err occurs in post write mode in ahb2axi." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: AHB2AXI_BRESP_ERR_INT_ST + description: need_des + addressOffset: 396 + size: 32 + fields: + - name: CPU_ICM_H2X_BRESP_ERR_INT_ST + description: the masked interrupt status of cpu_icm_h2x_bresp_err + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: AHB2AXI_BRESP_ERR_INT_ENA + description: need_des + addressOffset: 400 + size: 32 + fields: + - name: CPU_ICM_H2X_BRESP_ERR_INT_ENA + description: Write 1 to enable cpu_icm_h2x_bresp_err int + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: AHB2AXI_BRESP_ERR_INT_CLR + description: need_des + addressOffset: 404 + size: 32 + fields: + - name: CPU_ICM_H2X_BRESP_ERR_INT_CLR + description: Write 1 to clear cpu_icm_h2x_bresp_err int + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: L2_MEM_ERR_RESP_CTRL + description: need_des + addressOffset: 408 + size: 32 + fields: + - name: L2_MEM_ERR_RESP_EN + description: Set 1 to turn on l2mem error response + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: L2_MEM_AHB_BUFFER_CTRL + description: need_des + addressOffset: 412 + size: 32 + fields: + - name: L2_MEM_AHB_WRBUFFER_EN + description: Set 1 to turn on l2mem ahb wr buffer + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: L2_MEM_AHB_RDBUFFER_EN + description: Set 1 to turn on l2mem ahb rd buffer + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CORE_DMACTIVE_LPCORE + description: need_des + addressOffset: 416 + size: 32 + fields: + - name: CORE_DMACTIVE_LPCORE + description: hp core dmactive_lpcore value + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: CORE_ERR_RESP_DIS + description: need_des + addressOffset: 420 + size: 32 + fields: + - name: CORE_ERR_RESP_DIS + description: Set bit0 to disable ibus err resp. Set bit1 to disable dbus err resp. Set bit 2 to disable ahb err resp. + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: CORE_TIMEOUT_INT_RAW + description: Hp core bus timeout interrupt raw register + addressOffset: 424 + size: 32 + fields: + - name: CORE0_AHB_TIMEOUT_INT_RAW + description: the raw interrupt status of hp core0 ahb timeout + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE1_AHB_TIMEOUT_INT_RAW + description: the raw interrupt status of hp core1 ahb timeout + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CORE0_IBUS_TIMEOUT_INT_RAW + description: the raw interrupt status of hp core0 ibus timeout + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CORE1_IBUS_TIMEOUT_INT_RAW + description: the raw interrupt status of hp core1 ibus timeout + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CORE0_DBUS_TIMEOUT_INT_RAW + description: the raw interrupt status of hp core0 dbus timeout + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CORE1_DBUS_TIMEOUT_INT_RAW + description: the raw interrupt status of hp core1 dbus timeout + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: CORE_TIMEOUT_INT_ST + description: masked interrupt register + addressOffset: 428 + size: 32 + fields: + - name: CORE0_AHB_TIMEOUT_INT_ST + description: the masked interrupt status of hp core0 ahb timeout + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE1_AHB_TIMEOUT_INT_ST + description: the masked interrupt status of hp core1 ahb timeout + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CORE0_IBUS_TIMEOUT_INT_ST + description: the masked interrupt status of hp core0 ibus timeout + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CORE1_IBUS_TIMEOUT_INT_ST + description: the masked interrupt status of hp core1 ibus timeout + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: CORE0_DBUS_TIMEOUT_INT_ST + description: the masked interrupt status of hp core0 dbus timeout + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: CORE1_DBUS_TIMEOUT_INT_ST + description: the masked interrupt status of hp core1 dbus timeout + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: CORE_TIMEOUT_INT_ENA + description: masked interrupt register + addressOffset: 432 + size: 32 + fields: + - name: CORE0_AHB_TIMEOUT_INT_ENA + description: Write 1 to enable hp_core0_ahb_timeout int + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE1_AHB_TIMEOUT_INT_ENA + description: Write 1 to enable hp_core1_ahb_timeout int + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CORE0_IBUS_TIMEOUT_INT_ENA + description: Write 1 to enable hp_core0_ibus_timeout int + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CORE1_IBUS_TIMEOUT_INT_ENA + description: Write 1 to enable hp_core1_ibus_timeout int + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CORE0_DBUS_TIMEOUT_INT_ENA + description: Write 1 to enable hp_core0_dbus_timeout int + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CORE1_DBUS_TIMEOUT_INT_ENA + description: Write 1 to enable hp_core1_dbus_timeout int + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: CORE_TIMEOUT_INT_CLR + description: interrupt clear register + addressOffset: 436 + size: 32 + fields: + - name: CORE0_AHB_TIMEOUT_INT_CLR + description: Write 1 to clear hp_core0_ahb_timeout int + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CORE1_AHB_TIMEOUT_INT_CLR + description: Write 1 to clear hp_core1_ahb_timeout int + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CORE0_IBUS_TIMEOUT_INT_CLR + description: Write 1 to clear hp_core0_ibus_timeout int + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CORE1_IBUS_TIMEOUT_INT_CLR + description: Write 1 to clear hp_core1_ibus_timeout int + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: CORE0_DBUS_TIMEOUT_INT_CLR + description: Write 1 to clear hp_core0_dbus_timeout int + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: CORE1_DBUS_TIMEOUT_INT_CLR + description: Write 1 to clear hp_core1_dbus_timeout int + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: GPIO_O_HYS_CTRL0 + description: NA + addressOffset: 448 + size: 32 + fields: + - name: REG_GPIO_0_HYS_LOW + description: hys control for gpio47~16 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: GPIO_O_HYS_CTRL1 + description: NA + addressOffset: 452 + size: 32 + fields: + - name: REG_GPIO_0_HYS_HIGH + description: hys control for gpio56~48 + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: RSA_PD_CTRL + description: rsa pd ctrl register + addressOffset: 464 + size: 32 + resetValue: 2 + fields: + - name: RSA_MEM_FORCE_PD + description: Set this bit to power down rsa internal memory. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RSA_MEM_FORCE_PU + description: Set this bit to force power up rsa internal memory + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RSA_MEM_PD + description: Set this bit to force power down rsa internal memory. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: ECC_PD_CTRL + description: ecc pd ctrl register + addressOffset: 468 + size: 32 + resetValue: 2 + fields: + - name: ECC_MEM_FORCE_PD + description: Set this bit to power down ecc internal memory. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ECC_MEM_FORCE_PU + description: Set this bit to force power up ecc internal memory + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ECC_MEM_PD + description: Set this bit to force power down ecc internal memory. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: RNG_CFG + description: rng cfg register + addressOffset: 472 + size: 32 + fields: + - name: RNG_SAMPLE_ENABLE + description: enable rng sample chain + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RNG_CHAIN_CLK_DIV_NUM + description: chain clk div num to pad for debug + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: RNG_SAMPLE_CNT + description: debug rng sample cnt + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: UART_PD_CTRL + description: ecc pd ctrl register + addressOffset: 476 + size: 32 + resetValue: 2 + fields: + - name: UART_MEM_FORCE_PD + description: Set this bit to power down hp uart internal memory. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: UART_MEM_FORCE_PU + description: Set this bit to force power up hp uart internal memory + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: PERI_MEM_CLK_FORCE_ON + description: hp peri mem clk force on regpster + addressOffset: 480 + size: 32 + fields: + - name: RMT_MEM_CLK_FORCE_ON + description: Set this bit to force on mem clk in rmt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: BITSCRAMBLER_TX_MEM_CLK_FORCE_ON + description: Set this bit to force on tx mem clk in bitscrambler + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BITSCRAMBLER_RX_MEM_CLK_FORCE_ON + description: Set this bit to force on rx mem clk in bitscrambler + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: GDMA_MEM_CLK_FORCE_ON + description: Set this bit to force on mem clk in gdma + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: HP_SYS_CLKRST + description: HP_SYS_CLKRST Peripheral + groupName: HP_SYS_CLKRST + baseAddress: 1343119360 + addressBlock: + - offset: 0 + size: 240 + usage: registers + registers: + - register: + name: CLK_EN0 + description: Reserved + addressOffset: 0 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: ROOT_CLK_CTRL0 + description: Reserved + addressOffset: 4 + size: 32 + fields: + - name: CPUICM_DELAY_NUM + description: Reserved + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: SOC_CLK_DIV_UPDATE + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CPU_CLK_DIV_NUM + description: Reserved + bitOffset: 5 + bitWidth: 8 + access: read-write + - name: CPU_CLK_DIV_NUMERATOR + description: Reserved + bitOffset: 13 + bitWidth: 8 + access: read-write + - name: CPU_CLK_DIV_DENOMINATOR + description: Reserved + bitOffset: 21 + bitWidth: 8 + access: read-write + - register: + name: ROOT_CLK_CTRL1 + description: Reserved + addressOffset: 8 + size: 32 + resetValue: 1 + fields: + - name: MEM_CLK_DIV_NUM + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: MEM_CLK_DIV_NUMERATOR + description: Reserved + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: MEM_CLK_DIV_DENOMINATOR + description: Reserved + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SYS_CLK_DIV_NUM + description: Reserved + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: ROOT_CLK_CTRL2 + description: Reserved + addressOffset: 12 + size: 32 + resetValue: 65536 + fields: + - name: SYS_CLK_DIV_NUMERATOR + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SYS_CLK_DIV_DENOMINATOR + description: Reserved + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: APB_CLK_DIV_NUM + description: Reserved + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: APB_CLK_DIV_NUMERATOR + description: Reserved + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: ROOT_CLK_CTRL3 + description: Reserved + addressOffset: 16 + size: 32 + fields: + - name: APB_CLK_DIV_DENOMINATOR + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: SOC_CLK_CTRL0 + description: Reserved + addressOffset: 20 + size: 32 + resetValue: 3873413039 + fields: + - name: CORE0_CLIC_CLK_EN + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE1_CLIC_CLK_EN + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MISC_CPU_CLK_EN + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CORE0_CPU_CLK_EN + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CORE1_CPU_CLK_EN + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TCM_CPU_CLK_EN + description: Reserved + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BUSMON_CPU_CLK_EN + description: Reserved + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: L1CACHE_CPU_CLK_EN + description: Reserved + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: L1CACHE_D_CPU_CLK_EN + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: L1CACHE_I0_CPU_CLK_EN + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: L1CACHE_I1_CPU_CLK_EN + description: Reserved + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TRACE_CPU_CLK_EN + description: Reserved + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: ICM_CPU_CLK_EN + description: Reserved + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: GDMA_CPU_CLK_EN + description: Reserved + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: VPU_CPU_CLK_EN + description: Reserved + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: L1CACHE_MEM_CLK_EN + description: Reserved + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: L1CACHE_D_MEM_CLK_EN + description: Reserved + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: L1CACHE_I0_MEM_CLK_EN + description: Reserved + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: L1CACHE_I1_MEM_CLK_EN + description: Reserved + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: L2CACHE_MEM_CLK_EN + description: Reserved + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: L2MEM_MEM_CLK_EN + description: Reserved + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: L2MEMMON_MEM_CLK_EN + description: Reserved + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: ICM_MEM_CLK_EN + description: Reserved + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: MISC_SYS_CLK_EN + description: Reserved + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TRACE_SYS_CLK_EN + description: Reserved + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: L2CACHE_SYS_CLK_EN + description: Reserved + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: L2MEM_SYS_CLK_EN + description: Reserved + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: L2MEMMON_SYS_CLK_EN + description: Reserved + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: TCMMON_SYS_CLK_EN + description: Reserved + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: ICM_SYS_CLK_EN + description: Reserved + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: FLASH_SYS_CLK_EN + description: Reserved + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: PSRAM_SYS_CLK_EN + description: Reserved + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SOC_CLK_CTRL1 + description: Reserved + addressOffset: 24 + size: 32 + resetValue: 2088730655 + fields: + - name: GPSPI2_SYS_CLK_EN + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: GPSPI3_SYS_CLK_EN + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGDMA_SYS_CLK_EN + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: AHB_PDMA_SYS_CLK_EN + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: AXI_PDMA_SYS_CLK_EN + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: GDMA_SYS_CLK_EN + description: Reserved + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DMA2D_SYS_CLK_EN + description: Reserved + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: VPU_SYS_CLK_EN + description: Reserved + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: JPEG_SYS_CLK_EN + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: PPA_SYS_CLK_EN + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CSI_BRG_SYS_CLK_EN + description: Reserved + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CSI_HOST_SYS_CLK_EN + description: Reserved + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DSI_SYS_CLK_EN + description: Reserved + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: EMAC_SYS_CLK_EN + description: Reserved + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SDMMC_SYS_CLK_EN + description: Reserved + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: USB_OTG11_SYS_CLK_EN + description: Reserved + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: USB_OTG20_SYS_CLK_EN + description: Reserved + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: UHCI_SYS_CLK_EN + description: Reserved + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: UART0_SYS_CLK_EN + description: Reserved + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: UART1_SYS_CLK_EN + description: Reserved + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: UART2_SYS_CLK_EN + description: Reserved + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: UART3_SYS_CLK_EN + description: Reserved + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: UART4_SYS_CLK_EN + description: Reserved + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: PARLIO_SYS_CLK_EN + description: Reserved + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: ETM_SYS_CLK_EN + description: Reserved + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PVT_SYS_CLK_EN + description: Reserved + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: CRYPTO_SYS_CLK_EN + description: Reserved + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: KEY_MANAGER_SYS_CLK_EN + description: Reserved + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: BITSRAMBLER_SYS_CLK_EN + description: Reserved + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: BITSRAMBLER_RX_SYS_CLK_EN + description: Reserved + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: BITSRAMBLER_TX_SYS_CLK_EN + description: Reserved + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: H264_SYS_CLK_EN + description: Reserved + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SOC_CLK_CTRL2 + description: Reserved + addressOffset: 28 + size: 32 + resetValue: 553127902 + fields: + - name: RMT_SYS_CLK_EN + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: HP_CLKRST_APB_CLK_EN + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SYSREG_APB_CLK_EN + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ICM_APB_CLK_EN + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: INTRMTX_APB_CLK_EN + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ADC_APB_CLK_EN + description: Reserved + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: UHCI_APB_CLK_EN + description: Reserved + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: UART0_APB_CLK_EN + description: Reserved + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: UART1_APB_CLK_EN + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: UART2_APB_CLK_EN + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: UART3_APB_CLK_EN + description: Reserved + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: UART4_APB_CLK_EN + description: Reserved + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: I2C0_APB_CLK_EN + description: Reserved + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: I2C1_APB_CLK_EN + description: Reserved + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: I2S0_APB_CLK_EN + description: Reserved + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: I2S1_APB_CLK_EN + description: Reserved + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: I2S2_APB_CLK_EN + description: Reserved + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: I3C_MST_APB_CLK_EN + description: Reserved + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: I3C_SLV_APB_CLK_EN + description: Reserved + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: GPSPI2_APB_CLK_EN + description: Reserved + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: GPSPI3_APB_CLK_EN + description: Reserved + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIMERGRP0_APB_CLK_EN + description: Reserved + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: TIMERGRP1_APB_CLK_EN + description: Reserved + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SYSTIMER_APB_CLK_EN + description: Reserved + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TWAI0_APB_CLK_EN + description: Reserved + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TWAI1_APB_CLK_EN + description: Reserved + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TWAI2_APB_CLK_EN + description: Reserved + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: MCPWM0_APB_CLK_EN + description: Reserved + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: MCPWM1_APB_CLK_EN + description: Reserved + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: USB_DEVICE_APB_CLK_EN + description: Reserved + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: PCNT_APB_CLK_EN + description: Reserved + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: PARLIO_APB_CLK_EN + description: Reserved + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SOC_CLK_CTRL3 + description: Reserved + addressOffset: 32 + size: 32 + resetValue: 8 + fields: + - name: LEDC_APB_CLK_EN + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LCDCAM_APB_CLK_EN + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ETM_APB_CLK_EN + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IOMUX_APB_CLK_EN + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: REF_CLK_CTRL0 + description: Reserved + addressOffset: 36 + size: 32 + resetValue: 33624841 + fields: + - name: REF_50M_CLK_DIV_NUM + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: REF_25M_CLK_DIV_NUM + description: Reserved + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: REF_240M_CLK_DIV_NUM + description: Reserved + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: REF_160M_CLK_DIV_NUM + description: Reserved + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: REF_CLK_CTRL1 + description: Reserved + addressOffset: 40 + size: 32 + resetValue: 1477903619 + fields: + - name: REF_120M_CLK_DIV_NUM + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: REF_80M_CLK_DIV_NUM + description: Reserved + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: REF_20M_CLK_DIV_NUM + description: Reserved + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: TM_400M_CLK_EN + description: Reserved + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TM_200M_CLK_EN + description: Reserved + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TM_100M_CLK_EN + description: Reserved + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: REF_50M_CLK_EN + description: Reserved + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: REF_25M_CLK_EN + description: Reserved + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: TM_480M_CLK_EN + description: Reserved + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: REF_240M_CLK_EN + description: Reserved + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TM_240M_CLK_EN + description: Reserved + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: REF_CLK_CTRL2 + description: Reserved + addressOffset: 44 + size: 32 + resetValue: 277 + fields: + - name: REF_160M_CLK_EN + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TM_160M_CLK_EN + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REF_120M_CLK_EN + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TM_120M_CLK_EN + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: REF_80M_CLK_EN + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TM_80M_CLK_EN + description: Reserved + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TM_60M_CLK_EN + description: Reserved + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TM_48M_CLK_EN + description: Reserved + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: REF_20M_CLK_EN + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TM_20M_CLK_EN + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: PERI_CLK_CTRL00 + description: Reserved + addressOffset: 48 + size: 32 + resetValue: 49212 + fields: + - name: FLASH_CLK_SRC_SEL + description: Reserved + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: FLASH_PLL_CLK_EN + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FLASH_CORE_CLK_EN + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FLASH_CORE_CLK_DIV_NUM + description: Reserved + bitOffset: 4 + bitWidth: 8 + access: read-write + - name: PSRAM_CLK_SRC_SEL + description: Reserved + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: PSRAM_PLL_CLK_EN + description: Reserved + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PSRAM_CORE_CLK_EN + description: Reserved + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: PSRAM_CORE_CLK_DIV_NUM + description: Reserved + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: PAD_EMAC_REF_CLK_EN + description: Reserved + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: EMAC_RMII_CLK_SRC_SEL + description: Reserved + bitOffset: 25 + bitWidth: 2 + access: read-write + - name: EMAC_RMII_CLK_EN + description: Reserved + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: EMAC_RX_CLK_SRC_SEL + description: Reserved + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: EMAC_RX_CLK_EN + description: Reserved + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: PERI_CLK_CTRL01 + description: Reserved + addressOffset: 52 + size: 32 + resetValue: 1025 + fields: + - name: EMAC_RX_CLK_DIV_NUM + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: EMAC_TX_CLK_SRC_SEL + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: EMAC_TX_CLK_EN + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: EMAC_TX_CLK_DIV_NUM + description: Reserved + bitOffset: 10 + bitWidth: 8 + access: read-write + - name: EMAC_PTP_REF_CLK_SRC_SEL + description: Reserved + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: EMAC_PTP_REF_CLK_EN + description: Reserved + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: EMAC_UNUSED0_CLK_EN + description: Reserved + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: EMAC_UNUSED1_CLK_EN + description: Reserved + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SDIO_HS_MODE + description: Reserved + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SDIO_LS_CLK_SRC_SEL + description: Reserved + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SDIO_LS_CLK_EN + description: Reserved + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: PERI_CLK_CTRL02 + description: Reserved + addressOffset: 56 + size: 32 + fields: + - name: SDIO_LS_CLK_DIV_NUM + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SDIO_LS_CLK_EDGE_CFG_UPDATE + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SDIO_LS_CLK_EDGE_L + description: Reserved + bitOffset: 9 + bitWidth: 4 + access: read-write + - name: SDIO_LS_CLK_EDGE_H + description: Reserved + bitOffset: 13 + bitWidth: 4 + access: read-write + - name: SDIO_LS_CLK_EDGE_N + description: Reserved + bitOffset: 17 + bitWidth: 4 + access: read-write + - name: SDIO_LS_SLF_CLK_EDGE_SEL + description: Reserved + bitOffset: 21 + bitWidth: 2 + access: read-write + - name: SDIO_LS_DRV_CLK_EDGE_SEL + description: Reserved + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: SDIO_LS_SAM_CLK_EDGE_SEL + description: Reserved + bitOffset: 25 + bitWidth: 2 + access: read-write + - name: SDIO_LS_SLF_CLK_EN + description: Reserved + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SDIO_LS_DRV_CLK_EN + description: Reserved + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SDIO_LS_SAM_CLK_EN + description: Reserved + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: MIPI_DSI_DPHY_CLK_SRC_SEL + description: Reserved + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: PERI_CLK_CTRL03 + description: Reserved + addressOffset: 60 + size: 32 + fields: + - name: MIPI_DSI_DPHY_CFG_CLK_EN + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MIPI_DSI_DPHY_PLL_REFCLK_EN + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MIPI_CSI_DPHY_CLK_SRC_SEL + description: Reserved + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: MIPI_CSI_DPHY_CFG_CLK_EN + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MIPI_DSI_DPICLK_SRC_SEL + description: Reserved + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: MIPI_DSI_DPICLK_EN + description: Reserved + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: MIPI_DSI_DPICLK_DIV_NUM + description: Reserved + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: PERI_CLK_CTRL10 + description: Reserved + addressOffset: 64 + size: 32 + fields: + - name: I2C0_CLK_SRC_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: I2C0_CLK_EN + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: I2C0_CLK_DIV_NUM + description: Reserved + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: I2C0_CLK_DIV_NUMERATOR + description: Reserved + bitOffset: 10 + bitWidth: 8 + access: read-write + - name: I2C0_CLK_DIV_DENOMINATOR + description: Reserved + bitOffset: 18 + bitWidth: 8 + access: read-write + - name: I2C1_CLK_SRC_SEL + description: Reserved + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: I2C1_CLK_EN + description: Reserved + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: PERI_CLK_CTRL11 + description: Reserved + addressOffset: 68 + size: 32 + fields: + - name: I2C1_CLK_DIV_NUM + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: I2C1_CLK_DIV_NUMERATOR + description: Reserved + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: I2C1_CLK_DIV_DENOMINATOR + description: Reserved + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: I2S0_RX_CLK_EN + description: Reserved + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: I2S0_RX_CLK_SRC_SEL + description: Reserved + bitOffset: 25 + bitWidth: 2 + access: read-write + - register: + name: PERI_CLK_CTRL12 + description: Reserved + addressOffset: 72 + size: 32 + fields: + - name: I2S0_RX_DIV_N + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: I2S0_RX_DIV_X + description: Reserved + bitOffset: 8 + bitWidth: 9 + access: read-write + - name: I2S0_RX_DIV_Y + description: Reserved + bitOffset: 17 + bitWidth: 9 + access: read-write + - register: + name: PERI_CLK_CTRL13 + description: Reserved + addressOffset: 76 + size: 32 + fields: + - name: I2S0_RX_DIV_Z + description: Reserved + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: I2S0_RX_DIV_YN1 + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: I2S0_TX_CLK_EN + description: Reserved + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: I2S0_TX_CLK_SRC_SEL + description: Reserved + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: I2S0_TX_DIV_N + description: Reserved + bitOffset: 13 + bitWidth: 8 + access: read-write + - name: I2S0_TX_DIV_X + description: Reserved + bitOffset: 21 + bitWidth: 9 + access: read-write + - register: + name: PERI_CLK_CTRL14 + description: Reserved + addressOffset: 80 + size: 32 + fields: + - name: I2S0_TX_DIV_Y + description: Reserved + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: I2S0_TX_DIV_Z + description: Reserved + bitOffset: 9 + bitWidth: 9 + access: read-write + - name: I2S0_TX_DIV_YN1 + description: Reserved + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: I2S0_MST_CLK_SEL + description: Reserved + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: I2S1_RX_CLK_EN + description: Reserved + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: I2S1_RX_CLK_SRC_SEL + description: Reserved + bitOffset: 21 + bitWidth: 2 + access: read-write + - name: I2S1_RX_DIV_N + description: Reserved + bitOffset: 23 + bitWidth: 8 + access: read-write + - register: + name: PERI_CLK_CTRL15 + description: Reserved + addressOffset: 84 + size: 32 + fields: + - name: I2S1_RX_DIV_X + description: Reserved + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: I2S1_RX_DIV_Y + description: Reserved + bitOffset: 9 + bitWidth: 9 + access: read-write + - name: I2S1_RX_DIV_Z + description: Reserved + bitOffset: 18 + bitWidth: 9 + access: read-write + - name: I2S1_RX_DIV_YN1 + description: Reserved + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: I2S1_TX_CLK_EN + description: Reserved + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: I2S1_TX_CLK_SRC_SEL + description: Reserved + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: PERI_CLK_CTRL16 + description: Reserved + addressOffset: 88 + size: 32 + fields: + - name: I2S1_TX_DIV_N + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: I2S1_TX_DIV_X + description: Reserved + bitOffset: 8 + bitWidth: 9 + access: read-write + - name: I2S1_TX_DIV_Y + description: Reserved + bitOffset: 17 + bitWidth: 9 + access: read-write + - register: + name: PERI_CLK_CTRL17 + description: Reserved + addressOffset: 92 + size: 32 + fields: + - name: I2S1_TX_DIV_Z + description: Reserved + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: I2S1_TX_DIV_YN1 + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: I2S1_MST_CLK_SEL + description: Reserved + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: I2S2_RX_CLK_EN + description: Reserved + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: I2S2_RX_CLK_SRC_SEL + description: Reserved + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: I2S2_RX_DIV_N + description: Reserved + bitOffset: 14 + bitWidth: 8 + access: read-write + - name: I2S2_RX_DIV_X + description: Reserved + bitOffset: 22 + bitWidth: 9 + access: read-write + - register: + name: PERI_CLK_CTRL18 + description: Reserved + addressOffset: 96 + size: 32 + fields: + - name: I2S2_RX_DIV_Y + description: Reserved + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: I2S2_RX_DIV_Z + description: Reserved + bitOffset: 9 + bitWidth: 9 + access: read-write + - name: I2S2_RX_DIV_YN1 + description: Reserved + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: I2S2_TX_CLK_EN + description: Reserved + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: I2S2_TX_CLK_SRC_SEL + description: Reserved + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: I2S2_TX_DIV_N + description: Reserved + bitOffset: 22 + bitWidth: 8 + access: read-write + - register: + name: PERI_CLK_CTRL19 + description: Reserved + addressOffset: 100 + size: 32 + fields: + - name: I2S2_TX_DIV_X + description: Reserved + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: I2S2_TX_DIV_Y + description: Reserved + bitOffset: 9 + bitWidth: 9 + access: read-write + - name: I2S2_TX_DIV_Z + description: Reserved + bitOffset: 18 + bitWidth: 9 + access: read-write + - name: I2S2_TX_DIV_YN1 + description: Reserved + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: I2S2_MST_CLK_SEL + description: Reserved + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LCD_CLK_SRC_SEL + description: Reserved + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: LCD_CLK_EN + description: Reserved + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: PERI_CLK_CTRL110 + description: Reserved + addressOffset: 104 + size: 32 + resetValue: 67108864 + fields: + - name: LCD_CLK_DIV_NUM + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: LCD_CLK_DIV_NUMERATOR + description: Reserved + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: LCD_CLK_DIV_DENOMINATOR + description: Reserved + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: UART0_CLK_SRC_SEL + description: Reserved + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: UART0_CLK_EN + description: Reserved + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: PERI_CLK_CTRL111 + description: Reserved + addressOffset: 108 + size: 32 + resetValue: 67108864 + fields: + - name: UART0_SCLK_DIV_NUM + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: UART0_SCLK_DIV_NUMERATOR + description: Reserved + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: UART0_SCLK_DIV_DENOMINATOR + description: Reserved + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: UART1_CLK_SRC_SEL + description: Reserved + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: UART1_CLK_EN + description: Reserved + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: PERI_CLK_CTRL112 + description: Reserved + addressOffset: 112 + size: 32 + resetValue: 67108864 + fields: + - name: UART1_SCLK_DIV_NUM + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: UART1_SCLK_DIV_NUMERATOR + description: Reserved + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: UART1_SCLK_DIV_DENOMINATOR + description: Reserved + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: UART2_CLK_SRC_SEL + description: Reserved + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: UART2_CLK_EN + description: Reserved + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: PERI_CLK_CTRL113 + description: Reserved + addressOffset: 116 + size: 32 + resetValue: 67108864 + fields: + - name: UART2_SCLK_DIV_NUM + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: UART2_SCLK_DIV_NUMERATOR + description: Reserved + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: UART2_SCLK_DIV_DENOMINATOR + description: Reserved + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: UART3_CLK_SRC_SEL + description: Reserved + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: UART3_CLK_EN + description: Reserved + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: PERI_CLK_CTRL114 + description: Reserved + addressOffset: 120 + size: 32 + resetValue: 67108864 + fields: + - name: UART3_SCLK_DIV_NUM + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: UART3_SCLK_DIV_NUMERATOR + description: Reserved + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: UART3_SCLK_DIV_DENOMINATOR + description: Reserved + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: UART4_CLK_SRC_SEL + description: Reserved + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: UART4_CLK_EN + description: Reserved + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: PERI_CLK_CTRL115 + description: Reserved + addressOffset: 124 + size: 32 + fields: + - name: UART4_SCLK_DIV_NUM + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: UART4_SCLK_DIV_NUMERATOR + description: Reserved + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: UART4_SCLK_DIV_DENOMINATOR + description: Reserved + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: TWAI0_CLK_SRC_SEL + description: Reserved + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TWAI0_CLK_EN + description: Reserved + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TWAI1_CLK_SRC_SEL + description: Reserved + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TWAI1_CLK_EN + description: Reserved + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: TWAI2_CLK_SRC_SEL + description: Reserved + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: TWAI2_CLK_EN + description: Reserved + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: PERI_CLK_CTRL116 + description: Reserved + addressOffset: 128 + size: 32 + resetValue: 17825800 + fields: + - name: GPSPI2_CLK_SRC_SEL + description: Reserved + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: GPSPI2_HS_CLK_EN + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: GPSPI2_HS_CLK_DIV_NUM + description: Reserved + bitOffset: 4 + bitWidth: 8 + access: read-write + - name: GPSPI2_MST_CLK_DIV_NUM + description: Reserved + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: GPSPI2_MST_CLK_EN + description: Reserved + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: GPSPI3_CLK_SRC_SEL + description: Reserved + bitOffset: 21 + bitWidth: 3 + access: read-write + - name: GPSPI3_HS_CLK_EN + description: Reserved + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: PERI_CLK_CTRL117 + description: Reserved + addressOffset: 132 + size: 32 + resetValue: 65536 + fields: + - name: GPSPI3_HS_CLK_DIV_NUM + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GPSPI3_MST_CLK_DIV_NUM + description: Reserved + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: GPSPI3_MST_CLK_EN + description: Reserved + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PARLIO_RX_CLK_SRC_SEL + description: Reserved + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: PARLIO_RX_CLK_EN + description: Reserved + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PARLIO_RX_CLK_DIV_NUM + description: Reserved + bitOffset: 20 + bitWidth: 8 + access: read-write + - register: + name: PERI_CLK_CTRL118 + description: Reserved + addressOffset: 136 + size: 32 + fields: + - name: PARLIO_RX_CLK_DIV_NUMERATOR + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: PARLIO_RX_CLK_DIV_DENOMINATOR + description: Reserved + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: PARLIO_TX_CLK_SRC_SEL + description: Reserved + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: PARLIO_TX_CLK_EN + description: Reserved + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: PARLIO_TX_CLK_DIV_NUM + description: Reserved + bitOffset: 19 + bitWidth: 8 + access: read-write + - register: + name: PERI_CLK_CTRL119 + description: Reserved + addressOffset: 140 + size: 32 + fields: + - name: PARLIO_TX_CLK_DIV_NUMERATOR + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: PARLIO_TX_CLK_DIV_DENOMINATOR + description: Reserved + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: I3C_MST_CLK_SRC_SEL + description: Reserved + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: I3C_MST_CLK_EN + description: Reserved + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: I3C_MST_CLK_DIV_NUM + description: Reserved + bitOffset: 19 + bitWidth: 8 + access: read-write + - name: CAM_CLK_SRC_SEL + description: Reserved + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: CAM_CLK_EN + description: Reserved + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: PERI_CLK_CTRL120 + description: Reserved + addressOffset: 144 + size: 32 + fields: + - name: CAM_CLK_DIV_NUM + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CAM_CLK_DIV_NUMERATOR + description: Reserved + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: CAM_CLK_DIV_DENOMINATOR + description: Reserved + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: PERI_CLK_CTRL20 + description: Reserved + addressOffset: 148 + size: 32 + resetValue: 3372220416 + fields: + - name: MCPWM0_CLK_SRC_SEL + description: Reserved + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: MCPWM0_CLK_EN + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCPWM0_CLK_DIV_NUM + description: Reserved + bitOffset: 3 + bitWidth: 8 + access: read-write + - name: MCPWM1_CLK_SRC_SEL + description: Reserved + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: MCPWM1_CLK_EN + description: Reserved + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: MCPWM1_CLK_DIV_NUM + description: Reserved + bitOffset: 14 + bitWidth: 8 + access: read-write + - name: TIMERGRP0_T0_SRC_SEL + description: Reserved + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: TIMERGRP0_T0_CLK_EN + description: Reserved + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TIMERGRP0_T1_SRC_SEL + description: Reserved + bitOffset: 25 + bitWidth: 2 + access: read-write + - name: TIMERGRP0_T1_CLK_EN + description: Reserved + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: TIMERGRP0_WDT_SRC_SEL + description: Reserved + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: TIMERGRP0_WDT_CLK_EN + description: Reserved + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TIMERGRP0_TGRT_CLK_EN + description: Reserved + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: PERI_CLK_CTRL21 + description: Reserved + addressOffset: 152 + size: 32 + resetValue: 1379926016 + fields: + - name: TIMERGRP0_TGRT_CLK_SRC_SEL + description: Reserved + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: TIMERGRP0_TGRT_CLK_DIV_NUM + description: Reserved + bitOffset: 4 + bitWidth: 16 + access: read-write + - name: TIMERGRP1_T0_SRC_SEL + description: Reserved + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TIMERGRP1_T0_CLK_EN + description: Reserved + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TIMERGRP1_T1_SRC_SEL + description: Reserved + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: TIMERGRP1_T1_CLK_EN + description: Reserved + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TIMERGRP1_WDT_SRC_SEL + description: Reserved + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: TIMERGRP1_WDT_CLK_EN + description: Reserved + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SYSTIMER_CLK_SRC_SEL + description: Reserved + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SYSTIMER_CLK_EN + description: Reserved + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: PERI_CLK_CTRL22 + description: Reserved + addressOffset: 156 + size: 32 + fields: + - name: LEDC_CLK_SRC_SEL + description: Reserved + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: LEDC_CLK_EN + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RMT_CLK_SRC_SEL + description: Reserved + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: RMT_CLK_EN + description: Reserved + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RMT_CLK_DIV_NUM + description: Reserved + bitOffset: 6 + bitWidth: 8 + access: read-write + - name: RMT_CLK_DIV_NUMERATOR + description: Reserved + bitOffset: 14 + bitWidth: 8 + access: read-write + - name: RMT_CLK_DIV_DENOMINATOR + description: Reserved + bitOffset: 22 + bitWidth: 8 + access: read-write + - name: ADC_CLK_SRC_SEL + description: Reserved + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: PERI_CLK_CTRL23 + description: Reserved + addressOffset: 160 + size: 32 + resetValue: 8 + fields: + - name: ADC_CLK_EN + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ADC_CLK_DIV_NUM + description: Reserved + bitOffset: 1 + bitWidth: 8 + access: read-write + - name: ADC_CLK_DIV_NUMERATOR + description: Reserved + bitOffset: 9 + bitWidth: 8 + access: read-write + - name: ADC_CLK_DIV_DENOMINATOR + description: Reserved + bitOffset: 17 + bitWidth: 8 + access: read-write + - register: + name: PERI_CLK_CTRL24 + description: Reserved + addressOffset: 164 + size: 32 + resetValue: 1028 + fields: + - name: ADC_SAR1_CLK_DIV_NUM + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: ADC_SAR2_CLK_DIV_NUM + description: Reserved + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: PVT_CLK_DIV_NUM + description: Reserved + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: PVT_CLK_EN + description: Reserved + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: PERI_CLK_CTRL25 + description: Reserved + addressOffset: 168 + size: 32 + resetValue: 8372224 + fields: + - name: PVT_PERI_GROUP_CLK_DIV_NUM + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: PVT_PERI_GROUP1_CLK_EN + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: PVT_PERI_GROUP2_CLK_EN + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PVT_PERI_GROUP3_CLK_EN + description: Reserved + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: PVT_PERI_GROUP4_CLK_EN + description: Reserved + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CRYPTO_CLK_SRC_SEL + description: Reserved + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CRYPTO_AES_CLK_EN + description: Reserved + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CRYPTO_DS_CLK_EN + description: Reserved + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CRYPTO_ECC_CLK_EN + description: Reserved + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CRYPTO_HMAC_CLK_EN + description: Reserved + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: CRYPTO_RSA_CLK_EN + description: Reserved + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: CRYPTO_SEC_CLK_EN + description: Reserved + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: CRYPTO_SHA_CLK_EN + description: Reserved + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CRYPTO_ECDSA_CLK_EN + description: Reserved + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CRYPTO_KM_CLK_EN + description: Reserved + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: ISP_CLK_SRC_SEL + description: Reserved + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: ISP_CLK_EN + description: Reserved + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: PERI_CLK_CTRL26 + description: Reserved + addressOffset: 172 + size: 32 + resetValue: 512 + fields: + - name: ISP_CLK_DIV_NUM + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: IOMUX_CLK_SRC_SEL + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: IOMUX_CLK_EN + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: IOMUX_CLK_DIV_NUM + description: Reserved + bitOffset: 10 + bitWidth: 8 + access: read-write + - name: H264_CLK_SRC_SEL + description: Reserved + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: H264_CLK_EN + description: Reserved + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: H264_CLK_DIV_NUM + description: Reserved + bitOffset: 20 + bitWidth: 8 + access: read-write + - name: PADBIST_RX_CLK_SRC_SEL + description: Reserved + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: PADBIST_RX_CLK_EN + description: Reserved + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: PERI_CLK_CTRL27 + description: Reserved + addressOffset: 176 + size: 32 + fields: + - name: PADBIST_RX_CLK_DIV_NUM + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: PADBIST_TX_CLK_SRC_SEL + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: PADBIST_TX_CLK_EN + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PADBIST_TX_CLK_DIV_NUM + description: Reserved + bitOffset: 10 + bitWidth: 8 + access: read-write + - register: + name: CLK_FORCE_ON_CTRL0 + description: Reserved + addressOffset: 180 + size: 32 + resetValue: 262143 + fields: + - name: CPUICM_GATED_CLK_FORCE_ON + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TCM_CPU_CLK_FORCE_ON + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BUSMON_CPU_CLK_FORCE_ON + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: L1CACHE_CPU_CLK_FORCE_ON + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: L1CACHE_D_CPU_CLK_FORCE_ON + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: L1CACHE_I0_CPU_CLK_FORCE_ON + description: Reserved + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: L1CACHE_I1_CPU_CLK_FORCE_ON + description: Reserved + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TRACE_CPU_CLK_FORCE_ON + description: Reserved + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TRACE_SYS_CLK_FORCE_ON + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: L1CACHE_MEM_CLK_FORCE_ON + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: L1CACHE_D_MEM_CLK_FORCE_ON + description: Reserved + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: L1CACHE_I0_MEM_CLK_FORCE_ON + description: Reserved + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: L1CACHE_I1_MEM_CLK_FORCE_ON + description: Reserved + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: L2CACHE_MEM_CLK_FORCE_ON + description: Reserved + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: L2MEM_MEM_CLK_FORCE_ON + description: Reserved + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SAR1_CLK_FORCE_ON + description: Reserved + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SAR2_CLK_FORCE_ON + description: Reserved + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: GMAC_TX_CLK_FORCE_ON + description: Reserved + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: DPA_CTRL0 + description: Reserved + addressOffset: 184 + size: 32 + fields: + - name: SEC_DPA_LEVEL + description: Reserved + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SEC_DPA_CFG_SEL + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: ANA_PLL_CTRL0 + description: Reserved + addressOffset: 188 + size: 32 + fields: + - name: PLLA_CAL_END + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PLLA_CAL_STOP + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CPU_PLL_CAL_END + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CPU_PLL_CAL_STOP + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SDIO_PLL_CAL_END + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SDIO_PLL_CAL_STOP + description: Reserved + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SYS_PLL_CAL_END + description: Reserved + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SYS_PLL_CAL_STOP + description: Reserved + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: MSPI_CAL_END + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: MSPI_CAL_STOP + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: HP_RST_EN0 + description: Reserved + addressOffset: 192 + size: 32 + resetValue: 256 + fields: + - name: RST_EN_CORECTRL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RST_EN_PVT_TOP + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RST_EN_PVT_PERI_GROUP1 + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RST_EN_PVT_PERI_GROUP2 + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RST_EN_PVT_PERI_GROUP3 + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RST_EN_PVT_PERI_GROUP4 + description: Reserved + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RST_EN_REGDMA + description: Reserved + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RST_EN_CORE0_GLOBAL + description: Reserved + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RST_EN_CORE1_GLOBAL + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RST_EN_CORETRACE0 + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RST_EN_CORETRACE1 + description: Reserved + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: RST_EN_HP_TCM + description: Reserved + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RST_EN_HP_CACHE + description: Reserved + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RST_EN_L1_I0_CACHE + description: Reserved + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: RST_EN_L1_I1_CACHE + description: Reserved + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RST_EN_L1_D_CACHE + description: Reserved + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RST_EN_L2_CACHE + description: Reserved + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RST_EN_L2_MEM + description: Reserved + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: RST_EN_L2MEMMON + description: Reserved + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RST_EN_TCMMON + description: Reserved + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RST_EN_PVT_APB + description: Reserved + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: RST_EN_GDMA + description: Reserved + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: RST_EN_MSPI_AXI + description: Reserved + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RST_EN_DUAL_MSPI_AXI + description: Reserved + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: RST_EN_MSPI_APB + description: Reserved + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: RST_EN_DUAL_MSPI_APB + description: Reserved + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: RST_EN_DSI_BRG + description: Reserved + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RST_EN_CSI_HOST + description: Reserved + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RST_EN_CSI_BRG + description: Reserved + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: RST_EN_ISP + description: Reserved + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: RST_EN_JPEG + description: Reserved + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: RST_EN_DMA2D + description: Reserved + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_RST_EN1 + description: Reserved + addressOffset: 196 + size: 32 + fields: + - name: RST_EN_PPA + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RST_EN_AHB_PDMA + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RST_EN_AXI_PDMA + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RST_EN_IOMUX + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RST_EN_PADBIST + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RST_EN_STIMER + description: Reserved + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RST_EN_TIMERGRP0 + description: Reserved + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RST_EN_TIMERGRP1 + description: Reserved + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RST_EN_UART0_CORE + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RST_EN_UART1_CORE + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RST_EN_UART2_CORE + description: Reserved + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: RST_EN_UART3_CORE + description: Reserved + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RST_EN_UART4_CORE + description: Reserved + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RST_EN_UART0_APB + description: Reserved + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: RST_EN_UART1_APB + description: Reserved + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RST_EN_UART2_APB + description: Reserved + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RST_EN_UART3_APB + description: Reserved + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RST_EN_UART4_APB + description: Reserved + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: RST_EN_UHCI + description: Reserved + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RST_EN_I3CMST + description: Reserved + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RST_EN_I3CSLV + description: Reserved + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: RST_EN_I2C1 + description: Reserved + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: RST_EN_I2C0 + description: Reserved + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RST_EN_RMT + description: Reserved + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: RST_EN_PWM0 + description: Reserved + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: RST_EN_PWM1 + description: Reserved + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: RST_EN_CAN0 + description: Reserved + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RST_EN_CAN1 + description: Reserved + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RST_EN_CAN2 + description: Reserved + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: RST_EN_LEDC + description: Reserved + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: RST_EN_PCNT + description: Reserved + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: RST_EN_ETM + description: Reserved + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_RST_EN2 + description: Reserved + addressOffset: 200 + size: 32 + fields: + - name: RST_EN_INTRMTX + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RST_EN_PARLIO + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RST_EN_PARLIO_RX + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RST_EN_PARLIO_TX + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RST_EN_I2S0_APB + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RST_EN_I2S1_APB + description: Reserved + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RST_EN_I2S2_APB + description: Reserved + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RST_EN_SPI2 + description: Reserved + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RST_EN_SPI3 + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RST_EN_LCDCAM + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RST_EN_ADC + description: Reserved + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: RST_EN_BITSRAMBLER + description: Reserved + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RST_EN_BITSRAMBLER_RX + description: Reserved + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RST_EN_BITSRAMBLER_TX + description: Reserved + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: RST_EN_CRYPTO + description: Reserved + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RST_EN_SEC + description: Reserved + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RST_EN_AES + description: Reserved + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RST_EN_DS + description: Reserved + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: RST_EN_SHA + description: Reserved + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RST_EN_HMAC + description: Reserved + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RST_EN_ECDSA + description: Reserved + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: RST_EN_RSA + description: Reserved + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: RST_EN_ECC + description: Reserved + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RST_EN_KM + description: Reserved + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: RST_EN_H264 + description: Reserved + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: HP_FORCE_NORST0 + description: Reserved + addressOffset: 204 + size: 32 + fields: + - name: FORCE_NORST_CORE0 + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_CORE1 + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_CORETRACE0 + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_CORETRACE1 + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_L2MEMMON + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_TCMMON + description: Reserved + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_GDMA + description: Reserved + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_MSPI_AXI + description: Reserved + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_DUAL_MSPI_AXI + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_MSPI_APB + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_DUAL_MSPI_APB + description: Reserved + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_DSI_BRG + description: Reserved + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_CSI_HOST + description: Reserved + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_CSI_BRG + description: Reserved + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_ISP + description: Reserved + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_JPEG + description: Reserved + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_DMA2D + description: Reserved + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_PPA + description: Reserved + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_AHB_PDMA + description: Reserved + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_AXI_PDMA + description: Reserved + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_IOMUX + description: Reserved + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_PADBIST + description: Reserved + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_STIMER + description: Reserved + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_TIMERGRP0 + description: Reserved + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_TIMERGRP1 + description: Reserved + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_UART0 + description: Reserved + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_UART1 + description: Reserved + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_UART2 + description: Reserved + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_UART3 + description: Reserved + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_UART4 + description: Reserved + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_UHCI + description: Reserved + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_I3CMST + description: Reserved + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_FORCE_NORST1 + description: Reserved + addressOffset: 208 + size: 32 + fields: + - name: FORCE_NORST_I3CSLV + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_I2C1 + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_I2C0 + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_RMT + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_PWM0 + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_PWM1 + description: Reserved + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_CAN0 + description: Reserved + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_CAN1 + description: Reserved + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_CAN2 + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_LEDC + description: Reserved + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_PCNT + description: Reserved + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_ETM + description: Reserved + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_INTRMTX + description: Reserved + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_PARLIO + description: Reserved + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_PARLIO_RX + description: Reserved + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_PARLIO_TX + description: Reserved + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_I2S0 + description: Reserved + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_I2S1 + description: Reserved + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_I2S2 + description: Reserved + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_SPI2 + description: Reserved + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_SPI3 + description: Reserved + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_LCDCAM + description: Reserved + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_ADC + description: Reserved + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_BITSRAMBLER + description: Reserved + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_BITSRAMBLER_RX + description: Reserved + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_BITSRAMBLER_TX + description: Reserved + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: FORCE_NORST_H264 + description: Reserved + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: HPWDT_CORE0_RST_CTRL0 + description: Reserved + addressOffset: 212 + size: 32 + resetValue: 4113 + fields: + - name: HPCORE0_STALL_EN + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: HPCORE0_STALL_WAIT_NUM + description: Reserved + bitOffset: 1 + bitWidth: 8 + access: read-write + - name: WDT_HPCORE0_RST_LEN + description: Reserved + bitOffset: 9 + bitWidth: 8 + access: read-write + - register: + name: HPWDT_CORE1_RST_CTRL0 + description: Reserved + addressOffset: 216 + size: 32 + resetValue: 4113 + fields: + - name: HPCORE1_STALL_EN + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: HPCORE1_STALL_WAIT_NUM + description: Reserved + bitOffset: 1 + bitWidth: 8 + access: read-write + - name: WDT_HPCORE1_RST_LEN + description: Reserved + bitOffset: 9 + bitWidth: 8 + access: read-write + - register: + name: CPU_SRC_FREQ0 + description: CPU Source Frequency + addressOffset: 220 + size: 32 + fields: + - name: CPU_SRC_FREQ + description: "cpu source clock frequency, step by 0.25MHz" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CPU_CLK_STATUS0 + description: CPU Clock Status + addressOffset: 224 + size: 32 + fields: + - name: ASIC_OR_FPGA + description: "0: ASIC mode, 1: FPGA mode" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CPU_DIV_EFFECT + description: "0: Divider bypass, 1: Divider takes effect" + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CPU_SRC_IS_CPLL + description: "0: CPU source isn't cpll_400m, 1: CPU Source is cll_400m" + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CPU_DIV_NUM_CUR + description: cpu current div number + bitOffset: 3 + bitWidth: 8 + access: read-only + - name: CPU_DIV_NUMERATOR_CUR + description: cpu current div numerator + bitOffset: 11 + bitWidth: 8 + access: read-only + - name: CPU_DIV_DENOMINATOR_CUR + description: cpu current div denominator + bitOffset: 19 + bitWidth: 8 + access: read-only + - register: + name: DBG_CLK_CTRL0 + description: Reserved + addressOffset: 228 + size: 32 + resetValue: 67108863 + fields: + - name: DBG_CH0_SEL + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: DBG_CH1_SEL + description: Reserved + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: DBG_CH2_SEL + description: Reserved + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: DBG_CH0_DIV_NUM + description: Reserved + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: DBG_CLK_CTRL1 + description: Reserved + addressOffset: 232 + size: 32 + resetValue: 771 + fields: + - name: DBG_CH1_DIV_NUM + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: DBG_CH2_DIV_NUM + description: Reserved + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: DBG_CH0_EN + description: Reserved + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DBG_CH1_EN + description: Reserved + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: DBG_CH2_EN + description: Reserved + bitOffset: 18 + bitWidth: 1 + access: read-write + - register: + name: HPCORE_WDT_RESET_SOURCE0 + description: Reserved + addressOffset: 236 + size: 32 + resetValue: 2 + fields: + - name: HPCORE0_WDT_RESET_SOURCE_SEL + description: "1'b0: use wdt0 to reset hpcore0, 1'b1: use wdt1 to reset hpcore0" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: HPCORE1_WDT_RESET_SOURCE_SEL + description: "1'b0: use wdt0 to reset hpcore1, 1'b1: use wdt1 to reset hpcore1" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: LP_HUK + description: LP_HUK Peripheral + groupName: HUK + baseAddress: 1343307776 + addressBlock: + - offset: 0 + size: 424 + usage: registers + interrupt: + - name: LP_HUK + value: 20 + registers: + - register: + name: CLK + description: HUK Generator clock gate control register + addressOffset: 4 + size: 32 + resetValue: 1 + fields: + - name: EN + description: Write 1 to force on register clock gate. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_CG_FORCE_ON + description: Write 1 to force on memory clock gate. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: "HUK Generator interrupt raw register, valid in level." + addressOffset: 8 + size: 32 + fields: + - name: PREP_DONE_INT_RAW + description: The raw interrupt status bit for the huk_prep_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PROC_DONE_INT_RAW + description: The raw interrupt status bit for the huk_proc_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: POST_DONE_INT_RAW + description: The raw interrupt status bit for the huk_post_done_int interrupt + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: HUK Generator interrupt status register. + addressOffset: 12 + size: 32 + fields: + - name: PREP_DONE_INT_ST + description: The masked interrupt status bit for the huk_prep_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PROC_DONE_INT_ST + description: The masked interrupt status bit for the huk_proc_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: POST_DONE_INT_ST + description: The masked interrupt status bit for the huk_post_done_int interrupt + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: HUK Generator interrupt enable register. + addressOffset: 16 + size: 32 + fields: + - name: PREP_DONE_INT_ENA + description: The interrupt enable bit for the huk_prep_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PROC_DONE_INT_ENA + description: The interrupt enable bit for the huk_proc_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: POST_DONE_INT_ENA + description: The interrupt enable bit for the huk_post_done_int interrupt + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: HUK Generator interrupt clear register. + addressOffset: 20 + size: 32 + fields: + - name: PREP_DONE_INT_CLR + description: Set this bit to clear the huk_prep_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: PROC_DONE_INT_CLR + description: Set this bit to clear the huk_proc_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: POST_DONE_INT_CLR + description: Set this bit to clear the huk_post_done_int interrupt + bitOffset: 2 + bitWidth: 1 + access: write-only + - register: + name: CONF + description: HUK Generator configuration register + addressOffset: 32 + size: 32 + fields: + - name: MODE + description: "Set this field to choose the huk process. 1: process huk generate mode. 0: process huk recovery mode." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: START + description: HUK Generator control register + addressOffset: 36 + size: 32 + fields: + - name: START + description: Write 1 to continue HUK Generator operation at LOAD/GAIN state. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CONTINUE + description: Write 1 to start HUK Generator at IDLE state. + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: STATE + description: HUK Generator state register + addressOffset: 40 + size: 32 + fields: + - name: STATE + description: "The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY." + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: STATUS + description: HUK Generator HUK status register + addressOffset: 52 + size: 32 + fields: + - name: STATUS + description: "The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid. 2: HUK is generated but invalid. 3: reserved." + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: RISK_LEVEL + description: "The risk level of HUK. 0-6: the higher the risk level is, the more error bits there are in the PUF SRAM. 7: Error Level, HUK is invalid." + bitOffset: 2 + bitWidth: 3 + access: read-only + - register: + name: DATE + description: Version control register + addressOffset: 252 + size: 32 + resetValue: 36720704 + fields: + - name: DATE + description: HUK Generator version control register. + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + dim: 96 + dimIncrement: 4 + name: "INFO_MEM[%s]" + description: The memory that stores HUK info. + addressOffset: 256 + size: 32 + - name: I2C0 + description: I2C (Inter-Integrated Circuit) Controller 0 + groupName: I2C + baseAddress: 1342980096 + addressBlock: + - offset: 0 + size: 144 + usage: registers + interrupt: + - name: I2C0 + value: 44 + registers: + - register: + name: SCL_LOW_PERIOD + description: Configures the low level width of the SCL Clock. + addressOffset: 0 + size: 32 + fields: + - name: SCL_LOW_PERIOD + description: "Configures the low level width of the SCL Clock. \nMeasurement unit: i2c_sclk." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: CTR + description: Transmission setting + addressOffset: 4 + size: 32 + resetValue: 520 + fields: + - name: SDA_FORCE_OUT + description: "Configures the SDA output mode\n1: Direct output,\n\n0: Open drain output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_FORCE_OUT + description: "Configures the SCL output mode\n1: Direct output,\n\n0: Open drain output." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SAMPLE_SCL_LEVEL + description: "Configures the sample mode for SDA.\n1: Sample SDA data on the SCL low level.\n\n0: Sample SDA data on the SCL high level." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_FULL_ACK_LEVEL + description: Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MS_MODE + description: "Configures the module as an I2C Master or Slave. \n0: Slave\n\n1: Master" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TRANS_START + description: "Configures to start sending the data in txfifo for slave. \n0: No effect\n\n1: Start" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TX_LSB_FIRST + description: "Configures to control the sending order for data needing to be sent. \n1: send data from the least significant bit,\n\n0: send data from the most significant bit." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_LSB_FIRST + description: "Configures to control the storage order for received data.\n1: receive data from the least significant bit\n\n0: receive data from the most significant bit." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "Configures whether to gate clock signal for registers.\n\n0: Force clock on for registers \n\n1: Support clock only when registers are read or written to by software." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ARBITRATION_EN + description: "Configures to enable I2C bus arbitration detection.\n0: No effect\n\n1: Enable" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FSM_RST + description: "Configures to reset the SCL_FSM.\n0: No effect\n\n1: Reset" + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: CONF_UPGATE + description: "Configures this bit for synchronization\n0: No effect\n\n1: Synchronize" + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: SLV_TX_AUTO_START_EN + description: "Configures to enable slave to send data automatically\n0: Disable\n\n1: Enable" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: ADDR_10BIT_RW_CHECK_EN + description: "Configures to check if the r/w bit of 10bit addressing consists with I2C protocol.\n0: Not check\n\n1: Check" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: ADDR_BROADCASTING_EN + description: "Configures to support the 7bit general call function. \n0: Not support\n\n1: Support" + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: SR + description: Describe I2C work status. + addressOffset: 8 + size: 32 + resetValue: 49152 + fields: + - name: RESP_REC + description: "Represents the received ACK value in master mode or slave mode.\n0: ACK,\n\n1: NACK." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SLAVE_RW + description: "Represents the transfer direction in slave mode,.\n1: Master reads from slave,\n\n0: Master writes to slave." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ARB_LOST + description: "Represents whether the I2C controller loses control of SCL line.\n0: No arbitration lost\n\n1: Arbitration lost" + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BUS_BUSY + description: "Represents the I2C bus state.\n1: The I2C bus is busy transferring data, \n\n0: The I2C bus is in idle state." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SLAVE_ADDRESSED + description: "Represents whether the address sent by the master is equal to the address of the slave.\nValid only when the module is configured as an I2C Slave.\n0: Not equal\n\n1: Equal" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: RXFIFO_CNT + description: Represents the number of data bytes to be sent. + bitOffset: 8 + bitWidth: 6 + access: read-only + - name: STRETCH_CAUSE + description: "Represents the cause of SCL clocking stretching in slave mode.\n0: Stretching SCL low when the master starts to read data.\n\n1: Stretching SCL low when I2C TX FIFO is empty in slave mode.\n\n2: Stretching SCL low when I2C RX FIFO is full in slave mode." + bitOffset: 14 + bitWidth: 2 + access: read-only + - name: TXFIFO_CNT + description: Represents the number of data bytes received in RAM. + bitOffset: 18 + bitWidth: 6 + access: read-only + - name: SCL_MAIN_STATE_LAST + description: "Represents the states of the I2C module state machine. \n0: Idle,\n\n1: Address shift,\n\n2: ACK address,\n\n3: Rx data,\n\n4: Tx data,\n\n5: Send ACK,\n\n6: Wait ACK" + bitOffset: 24 + bitWidth: 3 + access: read-only + - name: SCL_STATE_LAST + description: "Represents the states of the state machine used to produce SCL.\n0: Idle,\n\n1: Start,\n\n2: Negative edge,\n\n3: Low,\n\n4: Positive edge,\n\n5: High,\n\n6: Stop" + bitOffset: 28 + bitWidth: 3 + access: read-only + - register: + name: TO + description: Setting time out control for receiving data. + addressOffset: 12 + size: 32 + resetValue: 16 + fields: + - name: TIME_OUT_VALUE + description: "Configures the timeout threshold period for SCL stucking at high or low level. The actual period is 2^(reg_time_out_value).\nMeasurement unit: i2c_sclk." + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: TIME_OUT_EN + description: "Configures to enable time out control.\n0: No effect\n\n1: Enable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: SLAVE_ADDR + description: Local slave address setting + addressOffset: 16 + size: 32 + fields: + - name: SLAVE_ADDR + description: Configure the slave address of I2C Slave. + bitOffset: 0 + bitWidth: 15 + access: read-write + - name: ADDR_10BIT_EN + description: "Configures to enable the slave 10-bit addressing mode in master mode. \n0: No effect\n\n1: Enable" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: FIFO_ST + description: FIFO status register. + addressOffset: 20 + size: 32 + fields: + - name: RXFIFO_RADDR + description: Represents the offset address of the APB reading from RXFIFO + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: RXFIFO_WADDR + description: Represents the offset address of i2c module receiving data and writing to RXFIFO. + bitOffset: 5 + bitWidth: 5 + access: read-only + - name: TXFIFO_RADDR + description: Represents the offset address of i2c module reading from TXFIFO. + bitOffset: 10 + bitWidth: 5 + access: read-only + - name: TXFIFO_WADDR + description: Represents the offset address of APB bus writing to TXFIFO. + bitOffset: 15 + bitWidth: 5 + access: read-only + - name: SLAVE_RW_POINT + description: Represents the offset address in the I2C Slave RAM addressed by I2C Master when in I2C slave mode. + bitOffset: 22 + bitWidth: 8 + access: read-only + - register: + name: FIFO_CONF + description: FIFO configuration register. + addressOffset: 24 + size: 32 + resetValue: 16523 + fields: + - name: RXFIFO_WM_THRHD + description: "Configures the water mark threshold of RXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid." + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: TXFIFO_WM_THRHD + description: "Configures the water mark threshold of TXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid." + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: NONFIFO_EN + description: Configures to enable APB nonfifo access. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FIFO_ADDR_CFG_EN + description: "Configures to enable double addressing mode. When this mode is enabled, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM. \n0: Disable\n\n1: Enable" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RX_FIFO_RST + description: "Configures to reset RXFIFO.\n0: No effect\n\n1: Reset" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_FIFO_RST + description: "Configures to reset TXFIFO.\n0: No effect\n\n1: Reset" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FIFO_PRT_EN + description: "Configures to enable FIFO pointer in non-fifo access mode. This bit controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.\n0: No effect\n\n1: Enable" + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DATA + description: Rx FIFO read data. + addressOffset: 28 + size: 32 + fields: + - name: FIFO_RDATA + description: Represents the value of RXFIFO read data. + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 32 + size: 32 + resetValue: 2 + fields: + - name: RXFIFO_WM_INT_RAW + description: The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_WM_INT_RAW + description: The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_RAW + description: The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: END_DETECT_INT_RAW + description: The raw interrupt status of the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS_DONE_INT_RAW + description: The raw interrupt status of the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_RAW + description: The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: MST_TXFIFO_UDF_INT_RAW + description: The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_RAW + description: The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_RAW + description: The raw interrupt status of the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TRANS_START_INT_RAW + description: The raw interrupt status of the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: NACK_INT_RAW + description: The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: TXFIFO_OVF_INT_RAW + description: The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: RXFIFO_UDF_INT_RAW + description: The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SCL_ST_TO_INT_RAW + description: The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SCL_MAIN_ST_TO_INT_RAW + description: The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DET_START_INT_RAW + description: The raw interrupt status of I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLAVE_STRETCH_INT_RAW + description: The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: GENERAL_CALL_INT_RAW + description: The raw interrupt status of I2C_GENARAL_CALL_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: SLAVE_ADDR_UNMATCH_INT_RAW + description: The raw interrupt status of I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 36 + size: 32 + fields: + - name: RXFIFO_WM_INT_CLR + description: Write 1 to clear I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TXFIFO_WM_INT_CLR + description: Write 1 to clear I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RXFIFO_OVF_INT_CLR + description: Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: END_DETECT_INT_CLR + description: Write 1 to clear the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: BYTE_TRANS_DONE_INT_CLR + description: Write 1 to clear the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: ARBITRATION_LOST_INT_CLR + description: Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: MST_TXFIFO_UDF_INT_CLR + description: Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TRANS_COMPLETE_INT_CLR + description: Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: TIME_OUT_INT_CLR + description: Write 1 to clear the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: TRANS_START_INT_CLR + description: Write 1 to clear the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: NACK_INT_CLR + description: Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: TXFIFO_OVF_INT_CLR + description: Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: RXFIFO_UDF_INT_CLR + description: Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: SCL_ST_TO_INT_CLR + description: Write 1 to clear I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SCL_MAIN_ST_TO_INT_CLR + description: Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: DET_START_INT_CLR + description: Write 1 to clear I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: SLAVE_STRETCH_INT_CLR + description: Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: GENERAL_CALL_INT_CLR + description: Write 1 to clear I2C_GENARAL_CALL_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: SLAVE_ADDR_UNMATCH_INT_CLR + description: Write 1 to clear I2C_SLAVE_ADDR_UNMATCH_INT_RAW interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 40 + size: 32 + fields: + - name: RXFIFO_WM_INT_ENA + description: Write 1 to enable I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_WM_INT_ENA + description: Write 1 to enable I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_ENA + description: Write 1 to enable I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: END_DETECT_INT_ENA + description: Write 1 to enable the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: BYTE_TRANS_DONE_INT_ENA + description: Write 1 to enable the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ARBITRATION_LOST_INT_ENA + description: Write 1 to enable the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: MST_TXFIFO_UDF_INT_ENA + description: Write 1 to enable I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TRANS_COMPLETE_INT_ENA + description: Write 1 to enable the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TIME_OUT_INT_ENA + description: Write 1 to enable the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TRANS_START_INT_ENA + description: Write 1 to enable the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: NACK_INT_ENA + description: Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TXFIFO_OVF_INT_ENA + description: Write 1 to enable I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RXFIFO_UDF_INT_ENA + description: Write 1 to enable I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SCL_ST_TO_INT_ENA + description: Write 1 to enable I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SCL_MAIN_ST_TO_INT_ENA + description: Write 1 to enable I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DET_START_INT_ENA + description: Write 1 to enable I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLAVE_STRETCH_INT_ENA + description: Write 1 to enable I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: GENERAL_CALL_INT_ENA + description: Write 1 to enable I2C_GENARAL_CALL_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SLAVE_ADDR_UNMATCH_INT_ENA + description: Write 1 to enable I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-write + - register: + name: INT_STATUS + description: Status of captured I2C communication events + addressOffset: 44 + size: 32 + fields: + - name: RXFIFO_WM_INT_ST + description: The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_WM_INT_ST + description: The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_ST + description: The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: END_DETECT_INT_ST + description: The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS_DONE_INT_ST + description: The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_ST + description: The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: MST_TXFIFO_UDF_INT_ST + description: The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_ST + description: The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_ST + description: The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TRANS_START_INT_ST + description: The masked interrupt status status of the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: NACK_INT_ST + description: The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: TXFIFO_OVF_INT_ST + description: The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: RXFIFO_UDF_INT_ST + description: The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SCL_ST_TO_INT_ST + description: The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SCL_MAIN_ST_TO_INT_ST + description: The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DET_START_INT_ST + description: The masked interrupt status status of I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLAVE_STRETCH_INT_ST + description: The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: GENERAL_CALL_INT_ST + description: The masked interrupt status status of I2C_GENARAL_CALL_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: SLAVE_ADDR_UNMATCH_INT_ST + description: The masked interrupt status status of I2C_SLAVE_ADDR_UNMATCH_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-only + - register: + name: SDA_HOLD + description: Configures the hold time after a negative SCL edge. + addressOffset: 48 + size: 32 + fields: + - name: TIME + description: "Configures the time to hold the data after the falling edge of SCL.\nMeasurement unit: i2c_sclk" + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SDA_SAMPLE + description: Configures the sample time after a positive SCL edge. + addressOffset: 52 + size: 32 + fields: + - name: TIME + description: "Configures the sample time after a positive SCL edge.\nMeasurement unit: i2c_sclk" + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_HIGH_PERIOD + description: Configures the high level width of SCL + addressOffset: 56 + size: 32 + fields: + - name: SCL_HIGH_PERIOD + description: "Configures for how long SCL remains high in master mode.\nMeasurement unit: i2c_sclk" + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: SCL_WAIT_HIGH_PERIOD + description: "Configures the SCL_FSM's waiting period for SCL high level in master mode.\nMeasurement unit: i2c_sclk" + bitOffset: 9 + bitWidth: 7 + access: read-write + - register: + name: SCL_START_HOLD + description: Configures the delay between the SDA and SCL negative edge for a start condition + addressOffset: 64 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "Configures the time between the falling edge of SDA and the falling edge of SCL for a START condition.\nMeasurement unit: i2c_sclk." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_RSTART_SETUP + description: Configures the delay between the positive edge of SCL and the negative edge of SDA + addressOffset: 68 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "Configures the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition.\nMeasurement unit: i2c_sclk" + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_STOP_HOLD + description: Configures the delay after the SCL clock edge for a stop condition + addressOffset: 72 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "Configures the delay after the STOP condition.\nMeasurement unit: i2c_sclk" + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_STOP_SETUP + description: "Configures the delay between the SDA and SCL rising edge for a stop condition.\nMeasurement unit: i2c_sclk" + addressOffset: 76 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "Configures the time between the rising edge of SCL and the rising edge of SDA.\nMeasurement unit: i2c_sclk" + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: FILTER_CFG + description: SCL and SDA filter configuration register + addressOffset: 80 + size: 32 + resetValue: 768 + fields: + - name: SCL_FILTER_THRES + description: "Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL input has smaller width than this register value, the I2C controller will ignore that pulse. \nMeasurement unit: i2c_sclk" + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: SDA_FILTER_THRES + description: "Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA input has smaller width than this register value, the I2C controller will ignore that pulse. \nMeasurement unit: i2c_sclk" + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: SCL_FILTER_EN + description: Configures to enable the filter function for SCL. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SDA_FILTER_EN + description: Configures to enable the filter function for SDA. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: CLK_CONF + description: I2C CLK configuration register + addressOffset: 84 + size: 32 + resetValue: 2097152 + fields: + - name: SCLK_DIV_NUM + description: the integral part of the fractional divisor for i2c module + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SCLK_DIV_A + description: the numerator of the fractional part of the fractional divisor for i2c module + bitOffset: 8 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_B + description: the denominator of the fractional part of the fractional divisor for i2c module + bitOffset: 14 + bitWidth: 6 + access: read-write + - name: SCLK_SEL + description: "The clock selection for i2c module:0-XTAL,1-CLK_8MHz." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SCLK_ACTIVE + description: The clock switch for i2c module + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + name: COMD0 + description: I2C command register 0 + addressOffset: 88 + size: 32 + fields: + - name: COMMAND0 + description: "Configures command 0. It consists of three parts: \nop_code is the command,\n0: RSTART, \n1: WRITE,\n2: READ,\n3: STOP,\n4: END.\n\nByte_num represents the number of bytes that need to be sent or received.\nack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND0_DONE + description: "Represents whether command 0 is done in I2C Master mode.\n0: Not done\n\n1: Done" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD1 + description: I2C command register 1 + addressOffset: 92 + size: 32 + fields: + - name: COMMAND1 + description: "Configures command 1. See details in I2C_CMD0_REG[13:0]." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND1_DONE + description: "Represents whether command 1 is done in I2C Master mode.\n0: Not done\n\n1: Done" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD2 + description: I2C command register 2 + addressOffset: 96 + size: 32 + fields: + - name: COMMAND2 + description: "Configures command 2. See details in I2C_CMD0_REG[13:0]." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND2_DONE + description: "Represents whether command 2 is done in I2C Master mode.\n0: Not done\n\n1: Done" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD3 + description: I2C command register 3 + addressOffset: 100 + size: 32 + fields: + - name: COMMAND3 + description: "Configures command 3. See details in I2C_CMD0_REG[13:0]." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND3_DONE + description: "Represents whether command 3 is done in I2C Master mode.\n0: Not done\n\n1: Done" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD4 + description: I2C command register 4 + addressOffset: 104 + size: 32 + fields: + - name: COMMAND4 + description: "Configures command 4. See details in I2C_CMD0_REG[13:0]." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND4_DONE + description: "Represents whether command 4 is done in I2C Master mode.\n0: Not done\n\n1: Done" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD5 + description: I2C command register 5 + addressOffset: 108 + size: 32 + fields: + - name: COMMAND5 + description: "Configures command 5. See details in I2C_CMD0_REG[13:0]." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND5_DONE + description: "Represents whether command 5 is done in I2C Master mode.\n0: Not done\n\n1: Done" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD6 + description: I2C command register 6 + addressOffset: 112 + size: 32 + fields: + - name: COMMAND6 + description: "Configures command 6. See details in I2C_CMD0_REG[13:0]." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND6_DONE + description: "Represents whether command 6 is done in I2C Master mode.\n0: Not done\n\n1: Done" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD7 + description: I2C command register 7 + addressOffset: 116 + size: 32 + fields: + - name: COMMAND7 + description: "Configures command 7. See details in I2C_CMD0_REG[13:0]." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND7_DONE + description: "Represents whether command 7 is done in I2C Master mode.\n0: Not done\n\n1: Done" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SCL_ST_TIME_OUT + description: SCL status time out register + addressOffset: 120 + size: 32 + resetValue: 16 + fields: + - name: SCL_ST_TO_I2C + description: "Configures the threshold value of SCL_FSM state unchanged period. It should be no more than 23.\nMeasurement unit: i2c_sclk" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SCL_MAIN_ST_TIME_OUT + description: SCL main status time out register + addressOffset: 124 + size: 32 + resetValue: 16 + fields: + - name: SCL_MAIN_ST_TO_I2C + description: "Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be no more than 23.\nMeasurement unit: i2c_sclk" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SCL_SP_CONF + description: Power configuration register + addressOffset: 128 + size: 32 + fields: + - name: SCL_RST_SLV_EN + description: "Configures to send out SCL pulses when I2C master is IDLE. The number of pulses equals to reg_scl_rst_slv_num[4:0]." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_RST_SLV_NUM + description: "Configure the pulses of SCL generated in I2C master mode. \nValid when reg_scl_rst_slv_en is 1.\nMeasurement unit: i2c_sclk" + bitOffset: 1 + bitWidth: 5 + access: read-write + - name: SCL_PD_EN + description: "Configures to power down the I2C output SCL line. \n0: Not power down.\n\n1: Power down.\nValid only when reg_scl_force_out is 1." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SDA_PD_EN + description: "Configures to power down the I2C output SDA line. \n0: Not power down.\n\n1: Power down.\nValid only when reg_sda_force_out is 1." + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: SCL_STRETCH_CONF + description: Set SCL stretch of I2C slave + addressOffset: 132 + size: 32 + fields: + - name: STRETCH_PROTECT_NUM + description: "Configures the time period to release the SCL line from stretching to avoid timing violation. Usually it should be larger than the SDA setup time.\nMeasurement unit: i2c_sclk" + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: SLAVE_SCL_STRETCH_EN + description: "Configures to enable slave SCL stretch function.\n0: Disable\n\n1: Enable\nThe SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLAVE_SCL_STRETCH_CLR + description: "Configures to clear the I2C slave SCL stretch function.\n0: No effect\n\n1: Clear" + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: SLAVE_BYTE_ACK_CTL_EN + description: "Configures to enable the function for slave to control ACK level.\n0: Disable\n\n1: Enable" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SLAVE_BYTE_ACK_LVL + description: "Set the ACK level when slave controlling ACK level function enables.\n0: Low level\n\n1: High level" + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version register + addressOffset: 248 + size: 32 + resetValue: 35656050 + fields: + - name: DATE + description: Version control register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TXFIFO_START_ADDR + description: I2C TXFIFO base address register + addressOffset: 256 + size: 32 + fields: + - name: TXFIFO_START_ADDR + description: Represents the I2C txfifo first address. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RXFIFO_START_ADDR + description: I2C RXFIFO base address register + addressOffset: 384 + size: 32 + fields: + - name: RXFIFO_START_ADDR + description: Represents the I2C rxfifo first address. + bitOffset: 0 + bitWidth: 32 + access: read-only + - name: I2C1 + description: I2C (Inter-Integrated Circuit) Controller 1 + baseAddress: 1342984192 + interrupt: + - name: I2C1 + value: 45 + derivedFrom: I2C0 + - name: I2S0 + description: I2S (Inter-IC Sound) Controller 0 + groupName: I2S + baseAddress: 1342988288 + addressBlock: + - offset: 0 + size: 96 + usage: registers + interrupt: + - name: I2S0 + value: 27 + registers: + - register: + name: INT_RAW + description: "I2S interrupt raw register, valid in level." + addressOffset: 12 + size: 32 + fields: + - name: RX_DONE_INT_RAW + description: The raw interrupt status bit for the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_RAW + description: The raw interrupt status bit for the i2s_tx_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_RAW + description: The raw interrupt status bit for the i2s_rx_hung_int interrupt + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_RAW + description: The raw interrupt status bit for the i2s_tx_hung_int interrupt + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: I2S interrupt status register. + addressOffset: 16 + size: 32 + fields: + - name: RX_DONE_INT_ST + description: The masked interrupt status bit for the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_ST + description: The masked interrupt status bit for the i2s_tx_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_ST + description: The masked interrupt status bit for the i2s_rx_hung_int interrupt + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_ST + description: The masked interrupt status bit for the i2s_tx_hung_int interrupt + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: I2S interrupt enable register. + addressOffset: 20 + size: 32 + fields: + - name: RX_DONE_INT_ENA + description: The interrupt enable bit for the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_ENA + description: The interrupt enable bit for the i2s_tx_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_HUNG_INT_ENA + description: The interrupt enable bit for the i2s_rx_hung_int interrupt + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_HUNG_INT_ENA + description: The interrupt enable bit for the i2s_tx_hung_int interrupt + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: I2S interrupt clear register. + addressOffset: 24 + size: 32 + fields: + - name: RX_DONE_INT_CLR + description: Set this bit to clear the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TX_DONE_INT_CLR + description: Set this bit to clear the i2s_tx_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_HUNG_INT_CLR + description: Set this bit to clear the i2s_rx_hung_int interrupt + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TX_HUNG_INT_CLR + description: Set this bit to clear the i2s_tx_hung_int interrupt + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: RX_CONF + description: I2S RX configure register + addressOffset: 32 + size: 32 + resetValue: 12629504 + fields: + - name: RX_RESET + description: Set this bit to reset receiver + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: RX_FIFO_RESET + description: Set this bit to reset Rx AFIFO + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_START + description: Set this bit to start receiving data + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_SLAVE_MOD + description: Set this bit to enable slave receiver mode + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_STOP_MODE + description: "0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: RX_MONO + description: Set this bit to enable receiver in mono mode + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_BIG_ENDIAN + description: "I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RX_UPDATE + description: Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RX_MONO_FST_VLD + description: "1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RX_PCM_CONF + description: "I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: RX_PCM_BYPASS + description: Set this bit to bypass Compress/Decompress module for received data. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RX_MSB_SHIFT + description: Set this bit to enable receiver in Phillips standard mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: RX_LEFT_ALIGN + description: "1: I2S RX left alignment mode. 0: I2S RX right alignment mode." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RX_24_FILL_EN + description: "1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RX_WS_IDLE_POL + description: "0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: RX_BIT_ORDER + description: "I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RX_TDM_EN + description: "1: Enable I2S TDM Rx mode . 0: Disable." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RX_PDM_EN + description: "1: Enable I2S PDM Rx mode . 0: Disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: RX_BCK_DIV_NUM + description: Bit clock configuration bits in receiver mode. + bitOffset: 21 + bitWidth: 6 + access: read-write + - register: + name: TX_CONF + description: I2S TX configure register + addressOffset: 36 + size: 32 + resetValue: 12644880 + fields: + - name: TX_RESET + description: Set this bit to reset transmitter + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TX_FIFO_RESET + description: Set this bit to reset Tx AFIFO + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TX_START + description: Set this bit to start transmitting data + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_SLAVE_MOD + description: Set this bit to enable slave transmitter mode + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_STOP_EN + description: Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TX_CHAN_EQUAL + description: "1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TX_MONO + description: Set this bit to enable transmitter in mono mode + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_BIG_ENDIAN + description: "I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TX_UPDATE + description: Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TX_MONO_FST_VLD + description: "1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TX_PCM_CONF + description: "I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: TX_PCM_BYPASS + description: Set this bit to bypass Compress/Decompress module for transmitted data. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_MSB_SHIFT + description: Set this bit to enable transmitter in Phillips standard mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_BCK_NO_DLY + description: "1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TX_LEFT_ALIGN + description: "1: I2S TX left alignment mode. 0: I2S TX right alignment mode." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TX_24_FILL_EN + description: "1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: TX_WS_IDLE_POL + description: "0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: TX_BIT_ORDER + description: "I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TX_TDM_EN + description: "1: Enable I2S TDM Tx mode . 0: Disable." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: TX_PDM_EN + description: "1: Enable I2S PDM Tx mode . 0: Disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TX_BCK_DIV_NUM + description: Bit clock configuration bits in transmitter mode. + bitOffset: 21 + bitWidth: 6 + access: read-write + - name: TX_CHAN_MOD + description: I2S transmitter channel mode configuration bits. + bitOffset: 27 + bitWidth: 3 + access: read-write + - name: SIG_LOOPBACK + description: Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: RX_CONF1 + description: I2S RX configure register 1 + addressOffset: 40 + size: 32 + resetValue: 2021376000 + fields: + - name: RX_TDM_WS_WIDTH + description: "The width of rx_ws_out at idle level in TDM mode is (I2S_RX_TDM_WS_WIDTH[8:0] +1) * T_bck" + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: RX_BITS_MOD + description: "Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode." + bitOffset: 14 + bitWidth: 5 + access: read-write + - name: RX_HALF_SAMPLE_BITS + description: I2S Rx half sample bits -1. + bitOffset: 19 + bitWidth: 8 + access: read-write + - name: RX_TDM_CHAN_BITS + description: The Rx bit number for each channel minus 1in TDM mode. + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: TX_CONF1 + description: I2S TX configure register 1 + addressOffset: 44 + size: 32 + resetValue: 2021376000 + fields: + - name: TX_TDM_WS_WIDTH + description: "The width of tx_ws_out at idle level in TDM mode is (I2S_TX_TDM_WS_WIDTH[8:0] +1) * T_bck" + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: TX_BITS_MOD + description: "Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode." + bitOffset: 14 + bitWidth: 5 + access: read-write + - name: TX_HALF_SAMPLE_BITS + description: I2S Tx half sample bits -1. + bitOffset: 19 + bitWidth: 8 + access: read-write + - name: TX_TDM_CHAN_BITS + description: The Tx bit number for each channel minus 1in TDM mode. + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: TX_PCM2PDM_CONF + description: I2S TX PCM2PDM configuration register + addressOffset: 64 + size: 32 + resetValue: 4890628 + fields: + - name: TX_PDM_HP_BYPASS + description: I2S TX PDM bypass hp filter or not. The option has been removed. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_PDM_SINC_OSR2 + description: I2S TX PDM OSR2 value + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: TX_PDM_PRESCALE + description: I2S TX PDM prescale for sigmadelta + bitOffset: 5 + bitWidth: 8 + access: read-write + - name: TX_PDM_HP_IN_SHIFT + description: "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4" + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: TX_PDM_LP_IN_SHIFT + description: "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4" + bitOffset: 15 + bitWidth: 2 + access: read-write + - name: TX_PDM_SINC_IN_SHIFT + description: "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4" + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: TX_PDM_SIGMADELTA_IN_SHIFT + description: "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4" + bitOffset: 19 + bitWidth: 2 + access: read-write + - name: TX_PDM_SIGMADELTA_DITHER2 + description: I2S TX PDM sigmadelta dither2 value + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: TX_PDM_SIGMADELTA_DITHER + description: I2S TX PDM sigmadelta dither value + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TX_PDM_DAC_2OUT_EN + description: I2S TX PDM dac mode enable + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TX_PDM_DAC_MODE_EN + description: I2S TX PDM dac 2channel enable + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PCM2PDM_CONV_EN + description: I2S TX PDM Converter enable + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: TX_PCM2PDM_CONF1 + description: I2S TX PCM2PDM configuration register + addressOffset: 68 + size: 32 + resetValue: 66552768 + fields: + - name: TX_PDM_FP + description: I2S TX PDM Fp + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: TX_PDM_FS + description: I2S TX PDM Fs + bitOffset: 10 + bitWidth: 10 + access: read-write + - name: TX_IIR_HP_MULT12_5 + description: "The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])" + bitOffset: 20 + bitWidth: 3 + access: read-write + - name: TX_IIR_HP_MULT12_0 + description: "The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])" + bitOffset: 23 + bitWidth: 3 + access: read-write + - register: + name: RX_PDM2PCM_CONF + description: I2S RX configure register + addressOffset: 72 + size: 32 + resetValue: 4162846720 + fields: + - name: RX_PDM2PCM_EN + description: "1: Enable PDM2PCM RX mode. 0: DIsable." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RX_PDM_SINC_DSR_16_EN + description: "Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: RX_PDM2PCM_AMPLIFY_NUM + description: Configure PDM RX amplify number. + bitOffset: 21 + bitWidth: 4 + access: read-write + - name: RX_PDM_HP_BYPASS + description: I2S PDM RX bypass hp filter or not. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: RX_IIR_HP_MULT12_5 + description: "The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + LP_I2S_RX_IIR_HP_MULT12_5[2:0])" + bitOffset: 26 + bitWidth: 3 + access: read-write + - name: RX_IIR_HP_MULT12_0 + description: "The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + LP_I2S_RX_IIR_HP_MULT12_0[2:0])" + bitOffset: 29 + bitWidth: 3 + access: read-write + - register: + name: RX_TDM_CTRL + description: I2S TX TDM mode control register + addressOffset: 80 + size: 32 + resetValue: 65535 + fields: + - name: RX_TDM_PDM_CHAN0_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN1_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN2_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN3_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN4_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN5_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN6_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN7_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN8_EN + description: "1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN9_EN + description: "1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN10_EN + description: "1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN11_EN + description: "1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN12_EN + description: "1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN13_EN + description: "1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN14_EN + description: "1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN15_EN + description: "1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RX_TDM_TOT_CHAN_NUM + description: The total channel number of I2S TX TDM mode. + bitOffset: 16 + bitWidth: 4 + access: read-write + - register: + name: TX_TDM_CTRL + description: I2S TX TDM mode control register + addressOffset: 84 + size: 32 + resetValue: 65535 + fields: + - name: TX_TDM_CHAN0_EN + description: "1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN1_EN + description: "1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN2_EN + description: "1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN3_EN + description: "1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN4_EN + description: "1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN5_EN + description: "1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN6_EN + description: "1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN7_EN + description: "1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN8_EN + description: "1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN9_EN + description: "1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN10_EN + description: "1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN11_EN + description: "1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN12_EN + description: "1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN13_EN + description: "1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN14_EN + description: "1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN15_EN + description: "1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TX_TDM_TOT_CHAN_NUM + description: The total channel number of I2S TX TDM mode. + bitOffset: 16 + bitWidth: 4 + access: read-write + - name: TX_TDM_SKIP_MSK_EN + description: "When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels." + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: RX_TIMING + description: I2S RX timing control register + addressOffset: 88 + size: 32 + fields: + - name: RX_SD_IN_DM + description: "The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: RX_SD1_IN_DM + description: "The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: RX_SD2_IN_DM + description: "The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: RX_SD3_IN_DM + description: "The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: RX_WS_OUT_DM + description: "The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: RX_BCK_OUT_DM + description: "The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: RX_WS_IN_DM + description: "The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: RX_BCK_IN_DM + description: "The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 28 + bitWidth: 2 + access: read-write + - register: + name: TX_TIMING + description: I2S TX timing control register + addressOffset: 92 + size: 32 + fields: + - name: TX_SD_OUT_DM + description: "The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: TX_SD1_OUT_DM + description: "The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: TX_WS_OUT_DM + description: "The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: TX_BCK_OUT_DM + description: "The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TX_WS_IN_DM + description: "The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: TX_BCK_IN_DM + description: "The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 28 + bitWidth: 2 + access: read-write + - register: + name: LC_HUNG_CONF + description: I2S HUNG configure register. + addressOffset: 96 + size: 32 + resetValue: 2064 + fields: + - name: LC_FIFO_TIMEOUT + description: the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: LC_FIFO_TIMEOUT_SHIFT + description: The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + bitOffset: 8 + bitWidth: 3 + access: read-write + - name: LC_FIFO_TIMEOUT_ENA + description: The enable bit for FIFO timeout + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: RXEOF_NUM + description: I2S RX data number control register. + addressOffset: 100 + size: 32 + resetValue: 64 + fields: + - name: RX_EOF_NUM + description: "The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel." + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: CONF_SIGLE_DATA + description: I2S signal data register + addressOffset: 104 + size: 32 + fields: + - name: SINGLE_DATA + description: The configured constant channel data to be sent out. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STATE + description: I2S TX status register + addressOffset: 108 + size: 32 + resetValue: 1 + fields: + - name: TX_IDLE + description: "1: i2s_tx is idle state. 0: i2s_tx is working." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: ETM_CONF + description: I2S ETM configure register + addressOffset: 112 + size: 32 + resetValue: 65600 + fields: + - name: ETM_TX_SEND_WORD_NUM + description: "I2S ETM send x words event. When sending word number of reg_etm_tx_send_word_num[9:0], i2s will trigger an etm event." + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: ETM_RX_RECEIVE_WORD_NUM + description: "I2S ETM receive x words event. When receiving word number of reg_etm_rx_receive_word_num[9:0], i2s will trigger an etm event." + bitOffset: 10 + bitWidth: 10 + access: read-write + - register: + name: FIFO_CNT + description: I2S sync counter register + addressOffset: 116 + size: 32 + fields: + - name: TX_FIFO_CNT + description: tx fifo counter value. + bitOffset: 0 + bitWidth: 31 + access: read-only + - name: TX_FIFO_CNT_RST + description: Set this bit to reset tx fifo counter. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: BCK_CNT + description: I2S sync counter register + addressOffset: 120 + size: 32 + fields: + - name: TX_BCK_CNT + description: tx bck counter value. + bitOffset: 0 + bitWidth: 31 + access: read-only + - name: TX_BCK_CNT_RST + description: Set this bit to reset tx bck counter. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: CLK_GATE + description: Clock gate register + addressOffset: 124 + size: 32 + fields: + - name: CLK_EN + description: set this bit to enable clock gate + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 128 + size: 32 + resetValue: 36713024 + fields: + - name: DATE + description: I2S version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: I2S1 + description: I2S (Inter-IC Sound) Controller 1 + baseAddress: 1342992384 + interrupt: + - name: I2S1 + value: 28 + derivedFrom: I2S0 + - name: I2S2 + description: I2S (Inter-IC Sound) Controller 2 + baseAddress: 1342996480 + interrupt: + - name: I2S2 + value: 29 + derivedFrom: I2S0 + - name: I3C_MST + description: I3C Controller (Master) + groupName: I3C_MST + baseAddress: 1343070208 + addressBlock: + - offset: 0 + size: 144 + usage: registers + interrupt: + - name: I3C + value: 101 + registers: + - register: + name: DEVICE_CTRL + description: DEVICE_CTRL register controls the transfer properties and disposition of controllers capabilities. + addressOffset: 0 + size: 32 + resetValue: 4128 + fields: + - name: REG_BA_INCLUDE + description: "This bit is used to include I3C broadcast address(0x7E) for private transfer.(If I3C broadcast address is not include for the private transfer, In-Band Interrupts driven from Slaves may not win address arbitration. Hence IBIs will get delayed)" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_TRANS_START + description: Transfer Start + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_CLK_EN + description: NA + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: REG_IBI_RSTART_TRANS_EN + description: NA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_AUTO_DIS_IBI_EN + description: NA + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REG_DMA_RX_EN + description: NA + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: REG_DMA_TX_EN + description: NA + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: REG_MULTI_SLV_SINGLE_CCC_EN + description: "0: rx high bit first, 1: rx low bit first" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REG_RX_BIT_ORDER + description: "0: rx low byte fist, 1: rx high byte first" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REG_RX_BYTE_ORDER + description: NA + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: REG_SCL_PULLUP_FORCE_EN + description: This bit is used to force scl_pullup_en + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: REG_SCL_OE_FORCE_EN + description: This bit is used to force scl_oe + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: REG_SDA_PP_RD_PULLUP_EN + description: NA + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: REG_SDA_RD_TBIT_HLVL_PULLUP_EN + description: NA + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: REG_SDA_PP_WR_PULLUP_EN + description: NA + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: REG_DATA_BYTE_CNT_UNLATCH + description: "1: read current real-time updated value 0: read latch data byte cnt value" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: REG_MEM_CLK_FORCE_ON + description: "1: dev characteristic and address table memory clk date force on . 0 : clock gating by rd/wr." + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: BUFFER_THLD_CTRL + description: In-Band Interrupt Status Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI status entries in the IBI buffer that trigger the IBI_STATUS_THLD_STAT interrupt. + addressOffset: 28 + size: 32 + resetValue: 266305 + fields: + - name: REG_CMD_BUF_EMPTY_THLD + description: Command Buffer Empty Threshold Value is used to control the number of empty locations(or greater) in the Command Buffer that trigger CMD_BUFFER_READY_STAT interrupt. + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: REG_RESP_BUF_THLD + description: Response Buffer Threshold Value is used to control the number of entries in the Response Buffer that trigger the RESP_READY_STAT_INTR. + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: REG_IBI_DATA_BUF_THLD + description: In-Band Interrupt Data Threshold Value . Every In Band Interrupt received by I3C controller generates an IBI status. This field controls the number of IBI data entries in the IBI buffer that trigger the IBI_DATA_THLD_STAT interrupt. + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: REG_IBI_STATUS_BUF_THLD + description: NA + bitOffset: 18 + bitWidth: 3 + access: read-write + - register: + name: DATA_BUFFER_THLD_CTRL + description: NA + addressOffset: 32 + size: 32 + resetValue: 9 + fields: + - name: REG_TX_DATA_BUF_THLD + description: "Transmit Buffer Threshold Value. This field controls the number of empty locations in the Transmit FIFO that trigger the TX_THLD_STAT interrupt. Supports values: 000:2 001:4 010:8 011:16 100:31, else:31" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: REG_RX_DATA_BUF_THLD + description: "Receive Buffer Threshold Value. This field controls the number of empty locations in the Receive FIFO that trigger the RX_THLD_STAT interrupt. Supports: 000:2 001:4 010:8 011:16 100:31, else:31" + bitOffset: 3 + bitWidth: 3 + access: read-write + - register: + name: IBI_NOTIFY_CTRL + description: NA + addressOffset: 36 + size: 32 + fields: + - name: REG_NOTIFY_SIR_REJECTED + description: "Notify Rejected Slave Interrupt Request Control. This bit is used to suppress reporting to the application about Slave Interrupt Request. 0:Suppress passing the IBI Status to the IBI FIFO(hence not notifying the application) when a SIR request is NACKed and auto-disabled base on the IBI_SIR_REQ_REJECT register. 1: Writes IBI Status to the IBI FIFO(hence notifying the application) when SIR request is NACKed and auto-disabled based on the IBI_SIR_REQ_REJECT registerl." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: IBI_SIR_REQ_PAYLOAD + description: NA + addressOffset: 40 + size: 32 + fields: + - name: REG_SIR_REQ_PAYLOAD + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: IBI_SIR_REQ_REJECT + description: NA + addressOffset: 44 + size: 32 + fields: + - name: REG_SIR_REQ_REJECT + description: "The application of controller can decide whether to send ACK or NACK for Slave request received from any I3C device. A device specific response control bit is provided to select the response option, Master will ACK/NACK the Master Request based on programming of control bit, corresponding to the interrupting device. 0:ACK the SIR Request 1:NACK and send direct auto disable CCC" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: INT_CLR + description: NA + addressOffset: 48 + size: 32 + fields: + - name: TX_DATA_BUF_THLD_INT_CLR + description: NA + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: RX_DATA_BUF_THLD_INT_CLR + description: NA + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: IBI_STATUS_THLD_INT_CLR + description: NA + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CMD_BUF_EMPTY_THLD_INT_CLR + description: NA + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: RESP_READY_INT_CLR + description: NA + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: NXT_CMD_REQ_ERR_INT_CLR + description: NA + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TRANSFER_ERR_INT_CLR + description: NA + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TRANSFER_COMPLETE_INT_CLR + description: NA + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: COMMAND_DONE_INT_CLR + description: NA + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: DETECT_START_INT_CLR + description: NA + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: RESP_BUF_OVF_INT_CLR + description: NA + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: IBI_DATA_BUF_OVF_INT_CLR + description: NA + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: IBI_STATUS_BUF_OVF_INT_CLR + description: NA + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: IBI_HANDLE_DONE_INT_CLR + description: NA + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: IBI_DETECT_INT_CLR + description: NA + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: CMD_CCC_MISMATCH_INT_CLR + description: NA + bitOffset: 15 + bitWidth: 1 + access: write-only + - register: + name: INT_RAW + description: NA + addressOffset: 52 + size: 32 + resetValue: 8 + fields: + - name: TX_DATA_BUF_THLD_INT_RAW + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_DATA_BUF_THLD_INT_RAW + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IBI_STATUS_THLD_INT_RAW + description: NA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CMD_BUF_EMPTY_THLD_INT_RAW + description: NA + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RESP_READY_INT_RAW + description: NA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: NXT_CMD_REQ_ERR_INT_RAW + description: NA + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TRANSFER_ERR_INT_RAW + description: NA + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TRANSFER_COMPLETE_INT_RAW + description: NA + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: COMMAND_DONE_INT_RAW + description: NA + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DETECT_START_INT_RAW + description: NA + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RESP_BUF_OVF_INT_RAW + description: NA + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: IBI_DATA_BUF_OVF_INT_RAW + description: NA + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: IBI_STATUS_BUF_OVF_INT_RAW + description: NA + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: IBI_HANDLE_DONE_INT_RAW + description: NA + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: IBI_DETECT_INT_RAW + description: NA + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CMD_CCC_MISMATCH_INT_RAW + description: NA + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: NA + addressOffset: 56 + size: 32 + fields: + - name: TX_DATA_BUF_THLD_INT_ST + description: This interrupt is generated when number of empty locations in transmit buffer is greater than or equal to threshold value specified by TX_EMPTY_BUS_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in transmit buffer is less than threshold value. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RX_DATA_BUF_THLD_INT_ST + description: This interrupt is generated when number of entries in receive buffer is greater than or equal to threshold value specified by RX_BUF_THLD field in DATA_BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in receive buffer is less than threshold value. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: IBI_STATUS_THLD_INT_ST + description: Only used in master mode. This interrupt is generated when number of entries in IBI buffer is greater than or equal to threshold value specified by IBI_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in IBI buffer is less than threshold value. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CMD_BUF_EMPTY_THLD_INT_ST + description: This interrupt is generated when number of empty locations in command buffer is greater than or equal to threshold value specified by CMD_EMPTY_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of empty locations in command buffer is less than threshold value. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: RESP_READY_INT_ST + description: This interrupt is generated when number of entries in response buffer is greater than or equal to threshold value specified by RESP_BUF_THLD field in BUFFER_THLD_CTRL register. This interrupt will be cleared automatically when number of entries in response buffer is less than threshold value. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: NXT_CMD_REQ_ERR_INT_ST + description: "This interrupt is generated if toc is 0(master will restart next command), but command buf is empty." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: TRANSFER_ERR_INT_ST + description: "This interrupt is generated if any error occurs during transfer. The error type will be specified in the response packet associated with the command (in ERR_STATUS field of RESPONSE_BUFFER_PORT register). This bit can be cleared by writing 1'h1." + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TRANSFER_COMPLETE_INT_ST + description: NA + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: COMMAND_DONE_INT_ST + description: NA + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DETECT_START_INT_ST + description: NA + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: RESP_BUF_OVF_INT_ST + description: NA + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: IBI_DATA_BUF_OVF_INT_ST + description: NA + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: IBI_STATUS_BUF_OVF_INT_ST + description: NA + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: IBI_HANDLE_DONE_INT_ST + description: NA + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: IBI_DETECT_INT_ST + description: NA + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: CMD_CCC_MISMATCH_INT_ST + description: NA + bitOffset: 15 + bitWidth: 1 + access: read-only + - register: + name: INT_ST_ENA + description: The Interrupt status will be updated in INTR_STATUS register if corresponding Status Enable bit set. + addressOffset: 60 + size: 32 + fields: + - name: TX_DATA_BUF_THLD_INT_ENA + description: Transmit Buffer threshold status enable. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_DATA_BUF_THLD_INT_ENA + description: Receive Buffer threshold status enable. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IBI_STATUS_THLD_INT_ENA + description: Only used in master mode. IBI Buffer threshold status enable. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CMD_BUF_EMPTY_THLD_INT_ENA + description: Command buffer ready status enable. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RESP_READY_INT_ENA + description: Response buffer ready status enable. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: NXT_CMD_REQ_ERR_INT_ENA + description: next command request error status enable + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TRANSFER_ERR_INT_ENA + description: Transfer error status enable + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TRANSFER_COMPLETE_INT_ENA + description: NA + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: COMMAND_DONE_INT_ENA + description: NA + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DETECT_START_INT_ENA + description: NA + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RESP_BUF_OVF_INT_ENA + description: NA + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: IBI_DATA_BUF_OVF_INT_ENA + description: NA + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: IBI_STATUS_BUF_OVF_INT_ENA + description: NA + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: IBI_HANDLE_DONE_INT_ENA + description: NA + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: IBI_DETECT_INT_ENA + description: NA + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CMD_CCC_MISMATCH_INT_ENA + description: NA + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: RESET_CTRL + description: NA + addressOffset: 68 + size: 32 + fields: + - name: REG_CORE_SOFT_RST + description: NA + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: REG_CMD_BUF_RST + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_RESP_BUF_RST + description: NA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_TX_DATA_BUF_BUF_RST + description: NA + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: REG_RX_DATA_BUF_RST + description: NA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_IBI_DATA_BUF_RST + description: NA + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REG_IBI_STATUS_BUF_RST + description: NA + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: BUFFER_STATUS_LEVEL + description: BUFFER_STATUS_LEVEL reflects the status level of Buffers in the controller. + addressOffset: 72 + size: 32 + resetValue: 16 + fields: + - name: CMD_BUF_EMPTY_CNT + description: Command Buffer Empty Locations contains the number of empty locations in the command buffer. + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: RESP_BUF_CNT + description: Response Buffer Level Value contains the number of valid data entries in the response buffer. + bitOffset: 8 + bitWidth: 4 + access: read-only + - name: IBI_DATA_BUF_CNT + description: IBI Buffer Level Value contains the number of valid entries in the IBI Buffer. This is field is used in master mode. + bitOffset: 16 + bitWidth: 4 + access: read-only + - name: IBI_STATUS_BUF_CNT + description: IBI Buffer Status Count contains the number of IBI status entries in the IBI Buffer. This field is used in master mode. + bitOffset: 24 + bitWidth: 4 + access: read-only + - register: + name: DATA_BUFFER_STATUS_LEVEL + description: DATA_BUFFER_STATUS_LEVEL reflects the status level of the Buffers in the controller. + addressOffset: 76 + size: 32 + resetValue: 32 + fields: + - name: TX_DATA_BUF_EMPTY_CNT + description: Transmit Buffer Empty Level Value contains the number of empty locations in the transmit Buffer. + bitOffset: 0 + bitWidth: 6 + access: read-only + - name: RX_DATA_BUF_CNT + description: Receive Buffer Level value contains the number of valid data entries in the receive buffer. + bitOffset: 16 + bitWidth: 6 + access: read-only + - register: + name: PRESENT_STATE0 + description: NA + addressOffset: 80 + size: 32 + resetValue: 3 + fields: + - name: SDA_LVL + description: This bit is used to check the SCL line level to recover from error and for debugging. This bit reflects the value of synchronized scl_in_a. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SCL_LVL + description: This bit is used to check the SDA line level to recover from error and for debugging. This bit reflects the value of synchronized sda_in_a. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: BUS_BUSY + description: NA + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: BUS_FREE + description: NA + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: CMD_TID + description: NA + bitOffset: 9 + bitWidth: 4 + access: read-only + - name: SCL_GEN_FSM_STATE + description: NA + bitOffset: 13 + bitWidth: 3 + access: read-only + - name: IBI_EV_HANDLE_FSM_STATE + description: NA + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: I2C_MODE_FSM_STATE + description: NA + bitOffset: 19 + bitWidth: 3 + access: read-only + - name: SDR_MODE_FSM_STATE + description: NA + bitOffset: 22 + bitWidth: 4 + access: read-only + - name: DAA_MODE_FSM_STATE + description: "Reflects whether the Master Controller is in IDLE or not. This bit will be set when all the buffer(Command, Response, IBI, Transmit, Receive) are empty along with the Master State machine is in idle state. 0X0: not in idle 0x1: in idle" + bitOffset: 26 + bitWidth: 3 + access: read-only + - name: MAIN_FSM_STATE + description: NA + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: PRESENT_STATE1 + description: NA + addressOffset: 84 + size: 32 + fields: + - name: DATA_BYTE_CNT + description: "Present transfer data byte cnt: tx data byte cnt if write rx data byte cnt if read ibi data byte cnt if IBI handle." + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: DEVICE_TABLE + description: Pointer for Device Address Table + addressOffset: 88 + size: 32 + fields: + - name: REG_DCT_DAA_INIT_INDEX + description: Reserved + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: REG_DAT_DAA_INIT_INDEX + description: NA + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: PRESENT_DCT_INDEX + description: NA + bitOffset: 8 + bitWidth: 4 + access: read-only + - name: PRESENT_DAT_INDEX + description: NA + bitOffset: 12 + bitWidth: 4 + access: read-only + - register: + name: TIME_OUT_VALUE + description: NA + addressOffset: 92 + size: 32 + resetValue: 4260880 + fields: + - name: REG_RESP_BUF_TO_VALUE + description: NA + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: REG_RESP_BUF_TO_EN + description: NA + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: REG_IBI_DATA_BUF_TO_VALUE + description: NA + bitOffset: 6 + bitWidth: 5 + access: read-write + - name: REG_IBI_DATA_BUF_TO_EN + description: NA + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: REG_IBI_STATUS_BUF_TO_VALUE + description: NA + bitOffset: 12 + bitWidth: 5 + access: read-write + - name: REG_IBI_STATUS_BUF_TO_EN + description: NA + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: REG_RX_DATA_BUF_TO_VALUE + description: NA + bitOffset: 18 + bitWidth: 5 + access: read-write + - name: REG_RX_DATA_BUF_TO_EN + description: NA + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: SCL_I3C_MST_OD_TIME + description: NA + addressOffset: 96 + size: 32 + resetValue: 327705 + fields: + - name: REG_I3C_MST_OD_LOW_PERIOD + description: SCL Open-Drain low count for I3C transfers targeted to I3C devices. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: REG_I3C_MST_OD_HIGH_PERIOD + description: SCL Open-Drain High count for I3C transfers targeted to I3C devices. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SCL_I3C_MST_PP_TIME + description: NA + addressOffset: 100 + size: 32 + resetValue: 327685 + fields: + - name: REG_I3C_MST_PP_LOW_PERIOD + description: NA + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: REG_I3C_MST_PP_HIGH_PERIOD + description: NA + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: SCL_I2C_FM_TIME + description: NA + addressOffset: 104 + size: 32 + resetValue: 4915363 + fields: + - name: REG_I2C_FM_LOW_PERIOD + description: NA + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: REG_I2C_FM_HIGH_PERIOD + description: The SCL open-drain low count timing for I2C Fast Mode transfers. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SCL_I2C_FMP_TIME + description: NA + addressOffset: 108 + size: 32 + resetValue: 2162751 + fields: + - name: REG_I2C_FMP_LOW_PERIOD + description: NA + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: REG_I2C_FMP_HIGH_PERIOD + description: NA + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: SCL_EXT_LOW_TIME + description: NA + addressOffset: 112 + size: 32 + fields: + - name: REG_I3C_MST_EXT_LOW_PERIOD1 + description: NA + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: REG_I3C_MST_EXT_LOW_PERIOD2 + description: NA + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: REG_I3C_MST_EXT_LOW_PERIOD3 + description: NA + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: REG_I3C_MST_EXT_LOW_PERIOD4 + description: NA + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: SDA_SAMPLE_TIME + description: NA + addressOffset: 116 + size: 32 + fields: + - name: REG_SDA_OD_SAMPLE_TIME + description: It is used to adjust sda sample point when scl high under open drain speed + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: REG_SDA_PP_SAMPLE_TIME + description: It is used to adjust sda sample point when scl high under push pull speed + bitOffset: 9 + bitWidth: 5 + access: read-write + - register: + name: SDA_HOLD_TIME + description: NA + addressOffset: 120 + size: 32 + resetValue: 1 + fields: + - name: REG_SDA_OD_TX_HOLD_TIME + description: It is used to adjust sda drive point after scl neg under open drain speed + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: REG_SDA_PP_TX_HOLD_TIME + description: It is used to adjust sda dirve point after scl neg under push pull speed + bitOffset: 9 + bitWidth: 5 + access: read-write + - register: + name: SCL_START_HOLD + description: NA + addressOffset: 124 + size: 32 + resetValue: 8 + fields: + - name: REG_SCL_START_HOLD_TIME + description: I2C_SCL_START_HOLD_TIME + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: REG_START_DET_HOLD_TIME + description: NA + bitOffset: 9 + bitWidth: 2 + access: read-write + - register: + name: SCL_RSTART_SETUP + description: NA + addressOffset: 128 + size: 32 + resetValue: 8 + fields: + - name: REG_SCL_RSTART_SETUP_TIME + description: I2C_SCL_RSTART_SETUP_TIME + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_STOP_HOLD + description: NA + addressOffset: 132 + size: 32 + resetValue: 8 + fields: + - name: REG_SCL_STOP_HOLD_TIME + description: I2C_SCL_STOP_HOLD_TIME + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_STOP_SETUP + description: NA + addressOffset: 136 + size: 32 + resetValue: 8 + fields: + - name: REG_SCL_STOP_SETUP_TIME + description: I2C_SCL_STOP_SETUP_TIME + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: BUS_FREE_TIME + description: NA + addressOffset: 144 + size: 32 + resetValue: 5 + fields: + - name: REG_BUS_FREE_TIME + description: "I3C Bus Free Count Value. This field is used only in Master mode. In pure Bus System, this field represents tCAS. In Mixed Bus System, this field is expected to be programmed to tLOW of I2C Timing." + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: SCL_TERMN_T_EXT_LOW_TIME + description: NA + addressOffset: 148 + size: 32 + resetValue: 2 + fields: + - name: REG_I3C_MST_TERMN_T_EXT_LOW_TIME + description: NA + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: VER_ID + description: NA + addressOffset: 160 + size: 32 + resetValue: 539165956 + fields: + - name: REG_I3C_MST_VER_ID + description: This field indicates the controller current release number that is read by an application. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: VER_TYPE + description: NA + addressOffset: 164 + size: 32 + fields: + - name: REG_I3C_MST_VER_TYPE + description: This field indicates the controller current release type that is read by an application. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FPGA_DEBUG_PROBE + description: NA + addressOffset: 172 + size: 32 + resetValue: 1 + fields: + - name: REG_I3C_MST_FPGA_DEBUG_PROBE + description: For Debug Probe Test on FPGA + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RND_ECO_CS + description: NA + addressOffset: 176 + size: 32 + fields: + - name: REG_RND_ECO_EN + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RND_ECO_RESULT + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: RND_ECO_LOW + description: NA + addressOffset: 180 + size: 32 + fields: + - name: REG_RND_ECO_LOW + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RND_ECO_HIGH + description: NA + addressOffset: 184 + size: 32 + resetValue: 65535 + fields: + - name: REG_RND_ECO_HIGH + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: I3C_MST_MEM + description: I3C_MST_MEM Peripheral + groupName: I3C_MST_MEM + baseAddress: 1343070208 + addressBlock: + - offset: 0 + size: 264 + usage: registers + registers: + - register: + name: COMMAND_BUF_PORT + description: NA + addressOffset: 8 + size: 32 + fields: + - name: REG_COMMAND + description: Contains a Command Descriptor structure that depends on the requested transfer type. Command Descriptor structure is used to schedule the transfers to devices on I3C bus. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RESPONSE_BUF_PORT + description: NA + addressOffset: 12 + size: 32 + fields: + - name: RESPONSE + description: The Response Buffer can be read through this register. The response status for each Command is written into the Response Buffer by the controller if ROC (Response On Completion) bit is set or if transfer error has occurred. The response buffer can be read through this register. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RX_DATA_PORT + description: NA + addressOffset: 16 + size: 32 + fields: + - name: RX_DATA_PORT + description: "Receive Data Port. Receive data is mapped to the Rx-data buffer and receive data is always packed in 4-byte aligned data words. If the length of data transfer is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional data bytes have to be ignored) at the end of the transferred data. The valid data must be identified using the DATA_LENGTH filed in the Response Descriptor." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: TX_DATA_PORT + description: NA + addressOffset: 20 + size: 32 + fields: + - name: REG_TX_DATA_PORT + description: "Transmit Data Port. Transmit data is mapped to the Tx-data buffer and transmit data is always packed in 4-byte aligned data words. If the length of data transfer is not aligned to 4-bytes boundary, then there will be extra(unused) bytes(the additional data bytes have to be ignored) at the end of the transferred data. The valid data must be identified using the DATA_LENGTH filed in the Response Descriptor." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: IBI_STATUS_BUF + description: "In-Band Interrupt Buffer Status/Data Register. When receiving an IBI, IBI_PORT is used to both: Read the IBI Status Read the IBI Data(which is raw/opaque data)" + addressOffset: 24 + size: 32 + fields: + - name: DATA_LENGTH + description: "This field represents the length of data received along with IBI, in bytes." + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: IBI_ID + description: "IBI Identifier. The byte received after START which includes the address the R/W bit: Device address and R/W bit in case of Slave Interrupt or Master Request." + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: IBI_STS + description: "IBI received data/status. IBI Data register is mapped to the IBI Buffer. The IBI Data is always packed in4-byte aligned and put to the IBI Buffer. This register When read from, reads the data from the IBI buffer. IBI Status register when read from, returns the data from the IBI Buffer and indicates how the controller responded to incoming IBI(SIR, MR and HJ)." + bitOffset: 28 + bitWidth: 1 + access: read-only + - register: + name: IBI_DATA_BUF + description: NA + addressOffset: 64 + size: 32 + fields: + - name: IBI_DATA + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_ADDR_TABLE1_LOC + description: NA + addressOffset: 192 + size: 32 + fields: + - name: REG_DAT_DEV1_STATIC_ADDR + description: NA + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: REG_DAT_DEV1_DYNAMIC_ADDR + description: "Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address." + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: REG_DAT_DEV1_NACK_RETRY_CNT + description: "This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state." + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: REG_DAT_DEV1_I2C + description: Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DEV_ADDR_TABLE2_LOC + description: NA + addressOffset: 196 + size: 32 + fields: + - name: REG_DAT_DEV2_STATIC_ADDR + description: NA + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: REG_DAT_DEV2_DYNAMIC_ADDR + description: "Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address." + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: REG_DAT_DEV2_NACK_RETRY_CNT + description: "This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state." + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: REG_DAT_DEV2_I2C + description: Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DEV_ADDR_TABLE3_LOC + description: NA + addressOffset: 200 + size: 32 + fields: + - name: REG_DAT_DEV3_STATIC_ADDR + description: NA + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: REG_DAT_DEV3_DYNAMIC_ADDR + description: "Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address." + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: REG_DAT_DEV3_NACK_RETRY_CNT + description: "This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state." + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: REG_DAT_DEV3_I2C + description: Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DEV_ADDR_TABLE4_LOC + description: NA + addressOffset: 204 + size: 32 + fields: + - name: REG_DAT_DEV4_STATIC_ADDR + description: NA + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: REG_DAT_DEV4_DYNAMIC_ADDR + description: "Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address." + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: REG_DAT_DEV4_NACK_RETRY_CNT + description: "This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state." + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: REG_DAT_DEV4_I2C + description: Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DEV_ADDR_TABLE5_LOC + description: NA + addressOffset: 208 + size: 32 + fields: + - name: REG_DAT_DEV5_STATIC_ADDR + description: NA + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: REG_DAT_DEV5_DYNAMIC_ADDR + description: "Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address." + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: REG_DAT_DEV5_NACK_RETRY_CNT + description: "This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state." + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: REG_DAT_DEV5_I2C + description: Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DEV_ADDR_TABLE6_LOC + description: NA + addressOffset: 212 + size: 32 + fields: + - name: REG_DAT_DEV6_STATIC_ADDR + description: NA + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: REG_DAT_DEV6_DYNAMIC_ADDR + description: "Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address." + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: REG_DAT_DEV6_NACK_RETRY_CNT + description: "This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state." + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: REG_DAT_DEV6_I2C + description: Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DEV_ADDR_TABLE7_LOC + description: NA + addressOffset: 216 + size: 32 + fields: + - name: REG_DAT_DEV7_STATIC_ADDR + description: NA + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: REG_DAT_DEV7_DYNAMIC_ADDR + description: "Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address." + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: REG_DAT_DEV7_NACK_RETRY_CNT + description: "This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state." + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: REG_DAT_DEV7_I2C + description: Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DEV_ADDR_TABLE8_LOC + description: NA + addressOffset: 220 + size: 32 + fields: + - name: REG_DAT_DEV8_STATIC_ADDR + description: NA + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: REG_DAT_DEV8_DYNAMIC_ADDR + description: "Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address." + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: REG_DAT_DEV8_NACK_RETRY_CNT + description: "This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state." + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: REG_DAT_DEV8_I2C + description: Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DEV_ADDR_TABLE9_LOC + description: NA + addressOffset: 224 + size: 32 + fields: + - name: REG_DAT_DEV9_STATIC_ADDR + description: NA + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: REG_DAT_DEV9_DYNAMIC_ADDR + description: "Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address." + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: REG_DAT_DEV9_NACK_RETRY_CNT + description: "This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state." + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: REG_DAT_DEV9_I2C + description: Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DEV_ADDR_TABLE10_LOC + description: NA + addressOffset: 228 + size: 32 + fields: + - name: REG_DAT_DEV10_STATIC_ADDR + description: NA + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: REG_DAT_DEV10_DYNAMIC_ADDR + description: "Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address." + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: REG_DAT_DEV10_NACK_RETRY_CNT + description: "This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state." + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: REG_DAT_DEV10_I2C + description: Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DEV_ADDR_TABLE11_LOC + description: NA + addressOffset: 232 + size: 32 + fields: + - name: REG_DAT_DEV11_STATIC_ADDR + description: NA + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: REG_DAT_DEV11_DYNAMIC_ADDR + description: "Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address." + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: REG_DAT_DEV11_NACK_RETRY_CNT + description: "This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state." + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: REG_DAT_DEV11_I2C + description: Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DEV_ADDR_TABLE12_LOC + description: NA + addressOffset: 236 + size: 32 + fields: + - name: REG_DAT_DEV12_STATIC_ADDR + description: NA + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: REG_DAT_DEV12_DYNAMIC_ADDR + description: "Device Dynamic Address with parity, The MSB,bit[23], should be programmed with parity of dynamic address." + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: REG_DAT_DEV12_NACK_RETRY_CNT + description: "This field is used to set the Device NACK Retry count for the particular device. If the Device NACK's for the device address, the controller automatically retries the same device until this count expires. If the Slave does not ACK for the mentioned number of retries, then controller generates an error response and move to the Halt state." + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: REG_DAT_DEV12_I2C + description: Legacy I2C device or not. This bit should be set to 1 if the device is a legacy I2C device. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DEV_CHAR_TABLE1_LOC1 + description: NA + addressOffset: 256 + size: 32 + fields: + - name: DCT_DEV1_LOC1 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE1_LOC2 + description: NA + addressOffset: 260 + size: 32 + fields: + - name: DCT_DEV1_LOC2 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE1_LOC3 + description: NA + addressOffset: 264 + size: 32 + fields: + - name: DCT_DEV1_LOC3 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE1_LOC4 + description: NA + addressOffset: 268 + size: 32 + fields: + - name: DCT_DEV1_LOC4 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE2_LOC1 + description: NA + addressOffset: 272 + size: 32 + fields: + - name: DCT_DEV2_LOC1 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE2_LOC2 + description: NA + addressOffset: 276 + size: 32 + fields: + - name: DCT_DEV2_LOC2 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE2_LOC3 + description: NA + addressOffset: 280 + size: 32 + fields: + - name: DCT_DEV2_LOC3 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE2_LOC4 + description: NA + addressOffset: 284 + size: 32 + fields: + - name: DCT_DEV2_LOC4 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE3_LOC1 + description: NA + addressOffset: 288 + size: 32 + fields: + - name: DCT_DEV3_LOC1 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE3_LOC2 + description: NA + addressOffset: 292 + size: 32 + fields: + - name: DCT_DEV3_LOC2 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE3_LOC3 + description: NA + addressOffset: 296 + size: 32 + fields: + - name: DCT_DEV3_LOC3 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE3_LOC4 + description: NA + addressOffset: 300 + size: 32 + fields: + - name: DCT_DEV3_LOC4 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE4_LOC1 + description: NA + addressOffset: 304 + size: 32 + fields: + - name: DCT_DEV4_LOC1 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE4_LOC2 + description: NA + addressOffset: 308 + size: 32 + fields: + - name: DCT_DEV4_LOC2 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE4_LOC3 + description: NA + addressOffset: 312 + size: 32 + fields: + - name: DCT_DEV4_LOC3 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE4_LOC4 + description: NA + addressOffset: 316 + size: 32 + fields: + - name: DCT_DEV4_LOC4 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE5_LOC1 + description: NA + addressOffset: 320 + size: 32 + fields: + - name: DCT_DEV5_LOC1 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE5_LOC2 + description: NA + addressOffset: 324 + size: 32 + fields: + - name: DCT_DEV5_LOC2 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE5_LOC3 + description: NA + addressOffset: 328 + size: 32 + fields: + - name: DCT_DEV5_LOC3 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE5_LOC4 + description: NA + addressOffset: 332 + size: 32 + fields: + - name: DCT_DEV5_LOC4 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE6_LOC1 + description: NA + addressOffset: 336 + size: 32 + fields: + - name: DCT_DEV6_LOC1 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE6_LOC2 + description: NA + addressOffset: 340 + size: 32 + fields: + - name: DCT_DEV6_LOC2 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE6_LOC3 + description: NA + addressOffset: 344 + size: 32 + fields: + - name: DCT_DEV6_LOC3 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE6_LOC4 + description: NA + addressOffset: 348 + size: 32 + fields: + - name: DCT_DEV6_LOC4 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE7_LOC1 + description: NA + addressOffset: 352 + size: 32 + fields: + - name: DCT_DEV7_LOC1 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE7_LOC2 + description: NA + addressOffset: 356 + size: 32 + fields: + - name: DCT_DEV7_LOC2 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE7_LOC3 + description: NA + addressOffset: 360 + size: 32 + fields: + - name: DCT_DEV7_LOC3 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE7_LOC4 + description: NA + addressOffset: 364 + size: 32 + fields: + - name: DCT_DEV7_LOC4 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE8_LOC1 + description: NA + addressOffset: 368 + size: 32 + fields: + - name: DCT_DEV8_LOC1 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE8_LOC2 + description: NA + addressOffset: 372 + size: 32 + fields: + - name: DCT_DEV8_LOC2 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE8_LOC3 + description: NA + addressOffset: 376 + size: 32 + fields: + - name: DCT_DEV8_LOC3 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE8_LOC4 + description: NA + addressOffset: 380 + size: 32 + fields: + - name: DCT_DEV8_LOC4 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE9_LOC1 + description: NA + addressOffset: 384 + size: 32 + fields: + - name: DCT_DEV9_LOC1 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE9_LOC2 + description: NA + addressOffset: 388 + size: 32 + fields: + - name: DCT_DEV9_LOC2 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE9_LOC3 + description: NA + addressOffset: 392 + size: 32 + fields: + - name: DCT_DEV9_LOC3 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE9_LOC4 + description: NA + addressOffset: 396 + size: 32 + fields: + - name: DCT_DEV9_LOC4 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE10_LOC1 + description: NA + addressOffset: 400 + size: 32 + fields: + - name: DCT_DEV10_LOC1 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE10_LOC2 + description: NA + addressOffset: 404 + size: 32 + fields: + - name: DCT_DEV10_LOC2 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE10_LOC3 + description: NA + addressOffset: 408 + size: 32 + fields: + - name: DCT_DEV10_LOC3 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE10_LOC4 + description: NA + addressOffset: 412 + size: 32 + fields: + - name: DCT_DEV10_LOC4 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE11_LOC1 + description: NA + addressOffset: 416 + size: 32 + fields: + - name: DCT_DEV11_LOC1 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE11_LOC2 + description: NA + addressOffset: 420 + size: 32 + fields: + - name: DCT_DEV11_LOC2 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE11_LOC3 + description: NA + addressOffset: 424 + size: 32 + fields: + - name: DCT_DEV11_LOC3 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE11_LOC4 + description: NA + addressOffset: 428 + size: 32 + fields: + - name: DCT_DEV11_LOC4 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE12_LOC1 + description: NA + addressOffset: 432 + size: 32 + fields: + - name: DCT_DEV12_LOC1 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE12_LOC2 + description: NA + addressOffset: 436 + size: 32 + fields: + - name: DCT_DEV12_LOC2 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE12_LOC3 + description: NA + addressOffset: 440 + size: 32 + fields: + - name: DCT_DEV12_LOC3 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEV_CHAR_TABLE12_LOC4 + description: NA + addressOffset: 444 + size: 32 + fields: + - name: DCT_DEV12_LOC4 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - name: I3C_SLV + description: I3C Controller (Slave) + groupName: I3C_SLV + baseAddress: 1343074304 + addressBlock: + - offset: 0 + size: 64 + usage: registers + interrupt: + - name: I3C_SLV + value: 102 + registers: + - register: + name: CONFIG + description: NA + addressOffset: 4 + size: 32 + resetValue: 3080193 + fields: + - name: SLVENA + description: "1: allow the slave to operate on i2c or i3c bus. 0: the slave will ignore the bus. This should be not set until registers such as PARTNO, IDEXT and the like are set 1st -if used- since they impact data to the master" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: NACK + description: "1:the slave will NACK all requests to it except CCC broadcast. This should be used with caution as the Master may determine the slave is missing if overused." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MATCHSS + description: "1: the START and STOP sticky STATUS bits will only be set if MATCHED is set..This allows START and STOP to be used to detect end of a message to /from this slave." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: S0IGNORE + description: "If 1, the Slave will not detect S0 or S1 errors and so not lock up waiting on an Exit Pattern. This should only be used when the bus will not use HDR." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DDROK + description: NA + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IDRAND + description: NA + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: OFFLINE + description: NA + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: BAMATCH + description: "Bus Available condition match value for current ???Slow clock???. This provides the count of the slow clock to count out 1us (or more) to allow an IBI to drive SDA Low when the Master is not doing so. The max width , and so max value, is controlled by the block. Only if enabled for events such IBI or MR or HJ, and if enabled to provide this as a register. With is limited to CLK_SLOW_BITS" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SADDR + description: "If allowed by the block:sets i2c 7 bits static address,else should be 0. If enabled to use one and to be provided by SW. Block may provide in HW as well." + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: STATUS + description: NA + addressOffset: 8 + size: 32 + fields: + - name: STNOTSTOP + description: "Is 1 if bus is busy(activity) and 0 when in a STOP condition. Other bits may also set when busy. Note that this can also be true from an S0 or S1 error, which waits for an Exit Pattern." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: STMSG + description: "Is 1 if this bus Slave is listening to the bus traffic or repsonding, If STNOSTOP=1, then this will be 0 when a non-matching address seen until next respeated START it STOP." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: STCCCH + description: Is 1 if a CCC message is being handled automatically. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: STREQRD + description: "1 if the req in process is an sdr read from this slave or an IBI is being pushed out," + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: STREQWR + description: NA + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: STDAA + description: NA + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: STHDR + description: NA + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: START + description: NA + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: MATCHED + description: NA + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: STOP + description: NA + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: RXPEND + description: "Receiving a message from master,which is not being handled by block(not a CCC internally processed). For all but External FIFO, this uses DATACTRL RXTRIG, which defaults to not-empty. If DMA is enabled for RX, DMA will be signaled as well. Will self-clear if data is read(FIFO and non-FIFO)" + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TXNOTFULL + description: "Is 1 when the To-bus buffer/FIFO can accept more data to go out. Defau:1. For all but External FIFO, this uses DATACTRL TXTRIG,which defaults to not-full. If DMA is enabled for TX, it will also be signaled to provide more." + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: DACHG + description: "The Slv Dynamic Address has been assigned, reassigned, or reset(lost) and is now in that state of being valid or none. Actual DA can be seen in the DYNADDR register. Note that this will also be used when MAP Auto feature is configured. This will be changing one or more MAP items. See DYNADDR and/or MAPCTRLn. DYNAADDR for the main DA(0) will indicate if last change was due to Auto MAP." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: CCC + description: "A common -command-code(CCC), not handled by block, has been received. This acts differently between: *Broadcasted ones, which will then also correspond with RXPEND and the 1st byte will be the CCC(command) . *Direct ones, which may never be directed to this device. If it is, then the TXSEND or RXPEND will be triggered with this end the RXPEND will contain the command." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: ERRWARN + description: NA + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: HDRMATCH + description: NA + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: CTRL + description: NA + addressOffset: 12 + size: 32 + fields: + - name: SLV_EVENT + description: "If set to non-0, will request an event. Once requested, STATUS.EVENT and EVDET will show the status as it progresses. Once completed, the field will automatically return to 0. Once non-0, only 0 can be written(to cancel) until done. 0: Normal mode. If set to 0 after was a non-0 value, will cancel if not already in flight. 1: start an IBI. This will try to push through an IBI on the bus. If data associate with the IBI, it will be drawn from the IBIDATA field. Note that if Time control is enabled, this will include anytime control related bytes further, the IBIDATA byte will have bit7 set to 1." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: EXTDATA + description: reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MAPIDX + description: "Index of Dynamic Address that IBI is for. This is 0 for the main or base Dynamic Address, or can be any valid index." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: IBIDATA + description: "Data byte to go with an IBI, if enabled for it. If enabled (was in BCR), then it is required." + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: PENDINT + description: "Should be set to the pending interrupt that GETSTATUS CCC will return. This should be maintained by the application if used and configured, as the Master will read this. If not configured, the GETSTATUS field will return 1 if an IBI is pending, and 0 otherwise." + bitOffset: 16 + bitWidth: 4 + access: read-write + - name: ACTSTATE + description: NA + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: VENDINFO + description: NA + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: INTSET + description: INSET allows setting enables for interrupts(connecting the corresponding STATUS source to causing an IRQ to the processor) + addressOffset: 16 + size: 32 + fields: + - name: STOP_ENA + description: "Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: RXPEND_ENA + description: "Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TXSEND_ENA + description: NA + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: INTCLR + description: NA + addressOffset: 20 + size: 32 + fields: + - name: STOP_CLR + description: "Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped." + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: RXPEND_CLR + description: "Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end." + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TXSEND_CLR + description: NA + bitOffset: 12 + bitWidth: 1 + access: write-only + - register: + name: INTMASKED + description: NA + addressOffset: 24 + size: 32 + fields: + - name: STOP_MASK + description: "Interrupt on STOP state on the bus. See Start as the preferred interrupt when needed. This interrupt may not trigger for quick STOP/START combination, as it relates to the state of being stopped." + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: RXPEND_MASK + description: "Interrupt when receiving a message from Master, which is not being handled by the block (excludes CCCs being handled automatically). If FIFO, then RX fullness trigger. If DMA, then message end." + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TXSEND_MASK + description: NA + bitOffset: 12 + bitWidth: 1 + access: read-only + - register: + name: DATACTRL + description: NA + addressOffset: 44 + size: 32 + resetValue: 176 + fields: + - name: FLUSHTB + description: Flushes the from-bus buffer/FIFO. Not normally used + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: FLUSHFB + description: Flushes the to-bus buffer/FIFO. Used when Master terminates a to-bus (read) message prematurely + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: UNLOCK + description: "If this bit is not written 1, the register bits from 7 to 4 are not changed on write." + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TXTRIG + description: "Trigger level for tx emptiness when FIFOed, Affects interrupt and DMA(if enabled). The defaults is 3" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: RXTRIG + description: "Trigger level for rx fulless when FIFOed, Affects interrupt and DMA(if enabled). The defaults is 3" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: TXCOUNT + description: NA + bitOffset: 16 + bitWidth: 5 + access: read-only + - name: RXCOUNT + description: NA + bitOffset: 24 + bitWidth: 5 + access: read-only + - name: TXFULL + description: NA + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: RXEMPTY + description: NA + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: WDATAB + description: NA + addressOffset: 48 + size: 32 + fields: + - name: WDATAB + description: NA + bitOffset: 0 + bitWidth: 8 + access: write-only + - name: WDATA_END + description: NA + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: WDATABE + description: NA + addressOffset: 52 + size: 32 + fields: + - name: WDATABE + description: NA + bitOffset: 0 + bitWidth: 8 + access: write-only + - register: + name: RDARAB + description: Read Byte Data (from-bus) register + addressOffset: 64 + size: 32 + fields: + - name: DATA0 + description: "This register allows reading a byte from the bus unless external FIFO is used. A byte should not be read unless there is data waiting, as indicated by the RXPEND bit being set in the STATUS register" + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: RDATAH + description: Read Half-word Data (from-bus) register + addressOffset: 72 + size: 32 + fields: + - name: DATA_LSB + description: NA + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: DATA_MSB + description: "This register allows reading a Half-word (byte pair) from the bus unless external FIFO is used. A Half-word should not be read unless there is at least 2 bytes of data waiting, as indicated by the RX FIFO level trigger or RXCOUNT available space in the DATACTRL register" + bitOffset: 8 + bitWidth: 8 + access: read-only + - register: + name: CAPABILITIES2 + description: NA + addressOffset: 92 + size: 32 + resetValue: 256 + fields: + - name: CAPABLITIES2 + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CAPABILITIES + description: NA + addressOffset: 96 + size: 32 + resetValue: 2081684508 + fields: + - name: CAPABLITIES + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IDPARTNO + description: NA + addressOffset: 108 + size: 32 + fields: + - name: PARTNO + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: IDEXT + description: NA + addressOffset: 112 + size: 32 + fields: + - name: IDEXT + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: VENDORID + description: NA + addressOffset: 116 + size: 32 + resetValue: 21840 + fields: + - name: VID + description: NA + bitOffset: 0 + bitWidth: 15 + access: read-write + - name: AXI_ICM + description: AXI_ICM Peripheral + groupName: ICM_AXI + baseAddress: 1342849024 + addressBlock: + - offset: 0 + size: 16 + usage: registers + registers: + - register: + name: VERID_FILEDS + description: NA + addressOffset: 0 + size: 32 + resetValue: 875574314 + fields: + - name: ICM_REG_VERID + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HW_CFG + description: NA + addressOffset: 4 + size: 32 + resetValue: 7393617 + fields: + - name: ICM_REG_AXI_HWCFG_QOS_SUPPORT + description: NA + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ICM_REG_AXI_HWCFG_APB3_SUPPORT + description: NA + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ICM_REG_AXI_HWCFG_AXI4_SUPPORT + description: NA + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: ICM_REG_AXI_HWCFG_LOCK_EN + description: NA + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: ICM_REG_AXI_HWCFG_TRUST_ZONE_EN + description: NA + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ICM_REG_AXI_HWCFG_DECODER_TYPE + description: NA + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ICM_REG_AXI_HWCFG_REMAP_EN + description: NA + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: ICM_REG_AXI_HWCFG_BI_DIR_CMD_EN + description: NA + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: ICM_REG_AXI_HWCFG_LOW_POWER_INF_EN + description: NA + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: ICM_REG_AXI_HWCFG_AXI_NUM_MASTERS + description: NA + bitOffset: 12 + bitWidth: 5 + access: read-only + - name: ICM_REG_AXI_HWCFG_AXI_NUM_SLAVES + description: NA + bitOffset: 20 + bitWidth: 5 + access: read-only + - register: + name: CMD + description: NA + addressOffset: 8 + size: 32 + fields: + - name: ICM_REG_AXI_CMD + description: NA + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: ICM_REG_RD_WR_CHAN + description: NA + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: ICM_REG_AXI_MASTER_PORT + description: NA + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: ICM_REG_AXI_ERR_BIT + description: NA + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: ICM_REG_AXI_SOFT_RESET_BIT + description: NA + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ICM_REG_AXI_RD_WR_CMD + description: NA + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: ICM_REG_AXI_CMD_EN + description: NA + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DATA + description: NA + addressOffset: 12 + size: 32 + fields: + - name: ICM_REG_DATA + description: NA + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: IO_MUX + description: Input/Output Multiplexer + groupName: IO_MUX + baseAddress: 1343098880 + addressBlock: + - offset: 0 + size: 232 + usage: registers + registers: + - register: + name: DATE + description: iomux version + addressOffset: 260 + size: 32 + resetValue: 2101794 + fields: + - name: DATE + description: csv date + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + dim: 54 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53" + name: GPIO%s + description: IO_MUX Control Register + addressOffset: 4 + size: 32 + access: read-write + fields: + - name: MCU_OE + description: "Configures whether or not to enable the output of GPIOn in sleep mode. 0: Disable 1: Enable" + bitOffset: 0 + bitWidth: 1 + - name: SLP_SEL + description: "Configures whether or not to enter sleep mode for GPIOn. 0: Not enter 1: Enter" + bitOffset: 1 + bitWidth: 1 + - name: MCU_WPD + description: "Configure whether or not to enable pull-down resistor of GPIOn during sleep mode. 0: Disable 1: Enable" + bitOffset: 2 + bitWidth: 1 + - name: MCU_WPU + description: "Configures whether or not to enable pull-up resistor of GPIOn during sleep mode. 0: Disable 1: Enable" + bitOffset: 3 + bitWidth: 1 + - name: MCU_IE + description: "Configures whether or not to enable the input of GPIOn during sleep mode. 0: Disable 1: Enable" + bitOffset: 4 + bitWidth: 1 + - name: MCU_DRV + description: "Configures the drive strength of GPIOn during sleep mode. 0: ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA" + bitOffset: 5 + bitWidth: 2 + - name: FUN_WPD + description: "Configures whether or not to enable pull-down resistor of GPIOn. 0: Disable 1: Enable" + bitOffset: 7 + bitWidth: 1 + - name: FUN_WPU + description: "Configures whether or not enable pull-up resistor of GPIOn. 0: Disable 1: Enable" + bitOffset: 8 + bitWidth: 1 + - name: FUN_IE + description: "Configures whether or not to enable input of GPIOn. 0: Disable 1: Enable" + bitOffset: 9 + bitWidth: 1 + - name: FUN_DRV + description: "Configures the drive strength of GPIOn. 0: ~5 mA 1: ~10 mA 2: ~20 mA 3: ~40 mA" + bitOffset: 10 + bitWidth: 2 + - name: MCU_SEL + description: "Configures to select IO MUX function for this pin. 0: Select Function 0 1: Select Function 1 ......" + bitOffset: 12 + bitWidth: 3 + - name: FILTER_EN + description: "Configures whether or not to enable filter for pin input signals. 0: Disable 1: Enable" + bitOffset: 15 + bitWidth: 1 + - name: ISP + description: ISP Peripheral + groupName: ISP + baseAddress: 1342836736 + addressBlock: + - offset: 0 + size: 580 + usage: registers + interrupt: + - name: ISP + value: 100 + registers: + - register: + name: VER_DATE + description: version control register + addressOffset: 0 + size: 32 + resetValue: 539035144 + fields: + - name: VER_DATA + description: csv version + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CLK_EN + description: isp clk control register + addressOffset: 4 + size: 32 + fields: + - name: CLK_EN + description: "this bit configures the clk force on of isp reg. 0: disable, 1: enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CLK_BLC_FORCE_ON + description: "this bit configures the clk force on of blc. 0: disable, 1: enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CLK_DPC_FORCE_ON + description: "this bit configures the clk force on of dpc. 0: disable, 1: enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CLK_BF_FORCE_ON + description: "this bit configures the clk force on of bf. 0: disable, 1: enable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CLK_LSC_FORCE_ON + description: "this bit configures the clk force on of lsc. 0: disable, 1: enable" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CLK_DEMOSAIC_FORCE_ON + description: "this bit configures the clk force on of demosaic. 0: disable, 1: enable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CLK_MEDIAN_FORCE_ON + description: "this bit configures the clk force on of median. 0: disable, 1: enable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CLK_CCM_FORCE_ON + description: "this bit configures the clk force on of ccm. 0: disable, 1: enable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_GAMMA_FORCE_ON + description: "this bit configures the clk force on of gamma. 0: disable, 1: enable" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CLK_RGB2YUV_FORCE_ON + description: "this bit configures the clk force on of rgb2yuv. 0: disable, 1: enable" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CLK_SHARP_FORCE_ON + description: "this bit configures the clk force on of sharp. 0: disable, 1: enable" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CLK_COLOR_FORCE_ON + description: "this bit configures the clk force on of color. 0: disable, 1: enable" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CLK_YUV2RGB_FORCE_ON + description: "this bit configures the clk force on of yuv2rgb. 0: disable, 1: enable" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CLK_AE_FORCE_ON + description: "this bit configures the clk force on of ae. 0: disable, 1: enable" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: CLK_AF_FORCE_ON + description: "this bit configures the clk force on of af. 0: disable, 1: enable" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CLK_AWB_FORCE_ON + description: "this bit configures the clk force on of awb. 0: disable, 1: enable" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CLK_HIST_FORCE_ON + description: "this bit configures the clk force on of hist. 0: disable, 1: enable" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CLK_MIPI_IDI_FORCE_ON + description: "this bit configures the clk force on of mipi idi input. 0: disable, 1: enable" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: ISP_MEM_CLK_FORCE_ON + description: "this bit configures the clk force on of all isp memory. 0: disable, 1: enable" + bitOffset: 18 + bitWidth: 1 + access: read-write + - register: + name: CNTL + description: isp module enable control register + addressOffset: 8 + size: 32 + resetValue: 1073751106 + fields: + - name: MIPI_DATA_EN + description: "this bit configures mipi input data enable. 0: disable, 1: enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ISP_EN + description: "this bit configures isp global enable. 0: disable, 1: enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BLC_EN + description: "this bit configures blc enable. 0: disable, 1: enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DPC_EN + description: "this bit configures dpc enable. 0: disable, 1: enable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: BF_EN + description: "this bit configures bf enable. 0: disable, 1: enable" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: LSC_EN + description: "this bit configures lsc enable. 0: disable, 1: enable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DEMOSAIC_EN + description: "this bit configures demosaic enable. 0: disable, 1: enable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: MEDIAN_EN + description: "this bit configures median enable. 0: disable, 1: enable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CCM_EN + description: "this bit configures ccm enable. 0: disable, 1: enable" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: GAMMA_EN + description: "this bit configures gamma enable. 0: disable, 1: enable" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RGB2YUV_EN + description: "this bit configures rgb2yuv enable. 0: disable, 1: enable" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SHARP_EN + description: "this bit configures sharp enable. 0: disable, 1: enable" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: COLOR_EN + description: "this bit configures color enable. 0: disable, 1: enable" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: YUV2RGB_EN + description: "this bit configures yuv2rgb enable. 0: disable, 1: enable" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: AE_EN + description: "this bit configures ae enable. 0: disable, 1: enable" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: AF_EN + description: "this bit configures af enable. 0: disable, 1: enable" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: AWB_EN + description: "this bit configures awb enable. 0: disable, 1: enable" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: HIST_EN + description: "this bit configures hist enable. 0: disable, 1: enable" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: BYTE_ENDIAN_ORDER + description: "select input idi data byte_endian_order when isp is bypass, 0: csi_data[31:0], 1: {[7:0], [15:8], [23:16], [31:24]}" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ISP_DATA_TYPE + description: "this field configures input data type, 0:RAW8 1:RAW10 2:RAW12" + bitOffset: 25 + bitWidth: 2 + access: read-write + - name: ISP_IN_SRC + description: "this field configures input data source, 0:CSI HOST 1:CAM 2:DMA" + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: ISP_OUT_TYPE + description: "this field configures pixel output type, 0: RAW8 1: YUV422 2: RGB888 3: YUV420 4: RGB565" + bitOffset: 29 + bitWidth: 3 + access: read-write + - register: + name: HSYNC_CNT + description: header hsync interval control register + addressOffset: 12 + size: 32 + resetValue: 7 + fields: + - name: HSYNC_CNT + description: this field configures the number of clock before hsync and after vsync and line_end when decodes pix data from idi to isp + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: FRAME_CFG + description: frame control parameter register + addressOffset: 16 + size: 32 + resetValue: 1612579296 + fields: + - name: VADR_NUM + description: "this field configures input image size in y-direction, image row number - 1" + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: HADR_NUM + description: "this field configures input image size in x-direction, image line number - 1" + bitOffset: 12 + bitWidth: 12 + access: read-write + - name: BAYER_MODE + description: "this field configures the bayer mode of input pixel. 00 : BG/GR 01 : GB/RG 10 : GR/BG 11 : RG/GB" + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: HSYNC_START_EXIST + description: "this bit configures the line end packet exist or not. 0: not exist, 1: exist" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HSYNC_END_EXIST + description: "this bit configures the line start packet exist or not. 0: not exist, 1: exist" + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: CCM_COEF0 + description: ccm coef register 0 + addressOffset: 20 + size: 32 + resetValue: 38799168 + fields: + - name: CCM_RR + description: this field configures the color correction matrix coefficient + bitOffset: 0 + bitWidth: 13 + access: read-write + - name: CCM_RG + description: this field configures the color correction matrix coefficient + bitOffset: 13 + bitWidth: 13 + access: read-write + - register: + name: CCM_COEF1 + description: ccm coef register 1 + addressOffset: 24 + size: 32 + resetValue: 36180160 + fields: + - name: CCM_RB + description: this field configures the color correction matrix coefficient + bitOffset: 0 + bitWidth: 13 + access: read-write + - name: CCM_GR + description: this field configures the color correction matrix coefficient + bitOffset: 13 + bitWidth: 13 + access: read-write + - register: + name: CCM_COEF3 + description: ccm coef register 3 + addressOffset: 28 + size: 32 + resetValue: 35653248 + fields: + - name: CCM_GG + description: this field configures the color correction matrix coefficient + bitOffset: 0 + bitWidth: 13 + access: read-write + - name: CCM_GB + description: this field configures the color correction matrix coefficient + bitOffset: 13 + bitWidth: 13 + access: read-write + - register: + name: CCM_COEF4 + description: ccm coef register 4 + addressOffset: 32 + size: 32 + resetValue: 39325760 + fields: + - name: CCM_BR + description: this field configures the color correction matrix coefficient + bitOffset: 0 + bitWidth: 13 + access: read-write + - name: CCM_BG + description: this field configures the color correction matrix coefficient + bitOffset: 13 + bitWidth: 13 + access: read-write + - register: + name: CCM_COEF5 + description: ccm coef register 5 + addressOffset: 36 + size: 32 + resetValue: 1856 + fields: + - name: CCM_BB + description: this field configures the color correction matrix coefficient + bitOffset: 0 + bitWidth: 13 + access: read-write + - register: + name: BF_MATRIX_CTRL + description: bf pix2matrix ctrl + addressOffset: 40 + size: 32 + fields: + - name: BF_TAIL_PIXEN_PULSE_TL + description: "matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse function" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: BF_TAIL_PIXEN_PULSE_TH + description: "matrix tail pixen high level threshold, must < hnum-1, only reg_bf_tail_pixen_pulse_th!=0 and reg_bf_tail_pixen_pulse_tl!=0 and reg_bf_tail_pixen_pulse_th < reg_bf_tail_pixen_pulse_tl will enable tail pulse function" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: BF_PADDING_DATA + description: this field configures bf matrix padding data + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: BF_PADDING_MODE + description: "this bit configures the padding mode of bf matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding" + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: BF_SIGMA + description: bf denoising level control register + addressOffset: 44 + size: 32 + resetValue: 2 + fields: + - name: SIGMA + description: "this field configures the bayer denoising level, valid data from 2 to 20" + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: BF_GAU0 + description: bf gau template register 0 + addressOffset: 48 + size: 32 + resetValue: 4294967295 + fields: + - name: GAU_TEMPLATE21 + description: this field configures index 21 of gausian template + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: GAU_TEMPLATE20 + description: this field configures index 20 of gausian template + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: GAU_TEMPLATE12 + description: this field configures index 12 of gausian template + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: GAU_TEMPLATE11 + description: this field configures index 11 of gausian template + bitOffset: 12 + bitWidth: 4 + access: read-write + - name: GAU_TEMPLATE10 + description: this field configures index 10 of gausian template + bitOffset: 16 + bitWidth: 4 + access: read-write + - name: GAU_TEMPLATE02 + description: this field configures index 02 of gausian template + bitOffset: 20 + bitWidth: 4 + access: read-write + - name: GAU_TEMPLATE01 + description: this field configures index 01 of gausian template + bitOffset: 24 + bitWidth: 4 + access: read-write + - name: GAU_TEMPLATE00 + description: this field configures index 00 of gausian template + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: BF_GAU1 + description: bf gau template register 1 + addressOffset: 52 + size: 32 + resetValue: 15 + fields: + - name: GAU_TEMPLATE22 + description: this field configures index 22 of gausian template + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: DPC_CTRL + description: DPC mode control register + addressOffset: 56 + size: 32 + resetValue: 4 + fields: + - name: DPC_CHECK_EN + description: "this bit configures the check mode enable. 0: disable, 1: enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: STA_EN + description: "this bit configures the sta dpc enable. 0: disable, 1: enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DYN_EN + description: "this bit configures the dyn dpc enable. 0: disable, 1: enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DPC_BLACK_EN + description: "this bit configures input image type select when in check mode, 0: white img, 1: black img" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DPC_METHOD_SEL + description: "this bit configures dyn dpc method select. 0: simple method, 1: hard method" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DPC_CHECK_OD_EN + description: "this bit configures output pixel data when in check mode or not. 0: no data output, 1: data output" + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: DPC_CONF + description: DPC parameter config register + addressOffset: 60 + size: 32 + resetValue: 68169776 + fields: + - name: DPC_THRESHOLD_L + description: "this bit configures the threshold to detect black img in check mode, or the low threshold(use 8 bit 0~255) in dyn method 0, or the low threshold factor (use 5 bit 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: DPC_THRESHOLD_H + description: "this bit configures the threshold to detect white img in check mode, or the high threshold(use 8 bit 0~255) in dyn method 0, or the high threshold factor (use 5 bit 10000-> 16/16, 00001->1/16, 0/16~16/16) in dyn method 1" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: DPC_FACTOR_DARK + description: this field configures the dynamic correction method 1 dark factor + bitOffset: 16 + bitWidth: 6 + access: read-write + - name: DPC_FACTOR_BRIG + description: this field configures the dynamic correction method 1 bright factor + bitOffset: 22 + bitWidth: 6 + access: read-write + - register: + name: DPC_MATRIX_CTRL + description: dpc pix2matrix ctrl + addressOffset: 64 + size: 32 + fields: + - name: DPC_TAIL_PIXEN_PULSE_TL + description: "matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse function" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: DPC_TAIL_PIXEN_PULSE_TH + description: "matrix tail pixen high level threshold, must < hnum-1, only reg_dpc_tail_pixen_pulse_th!=0 and reg_dpc_tail_pixen_pulse_tl!=0 and reg_dpc_tail_pixen_pulse_th < reg_dpc_tail_pixen_pulse_tl will enable tail pulse function" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: DPC_PADDING_DATA + description: this field configures dpc matrix padding data + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: DPC_PADDING_MODE + description: "this bit configures the padding mode of dpc matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding" + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: DPC_DEADPIX_CNT + description: DPC dead-pix number register + addressOffset: 68 + size: 32 + fields: + - name: DPC_DEADPIX_CNT + description: this field represents the dead pixel count + bitOffset: 0 + bitWidth: 10 + access: read-only + - register: + name: LUT_CMD + description: LUT command register + addressOffset: 72 + size: 32 + fields: + - name: LUT_ADDR + description: "this field configures the lut access addr, when select lsc lut, [11:10]:00 sel gb_b lut, 01 sel r_gr lut" + bitOffset: 0 + bitWidth: 12 + access: write-only + - name: LUT_NUM + description: "this field configures the lut selection. 0000:LSC LUT 0001:DPC LUT" + bitOffset: 12 + bitWidth: 4 + access: write-only + - name: LUT_CMD + description: "this bit configures the access event of lut. 0:rd 1: wr" + bitOffset: 16 + bitWidth: 1 + access: write-only + - register: + name: LUT_WDATA + description: LUT write data register + addressOffset: 76 + size: 32 + fields: + - name: LUT_WDATA + description: this field configures the write data of lut. please initial ISP_LUT_WDATA before write ISP_LUT_CMD register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LUT_RDATA + description: LUT read data register + addressOffset: 80 + size: 32 + fields: + - name: LUT_RDATA + description: this field represents the read data of lut. read ISP_LUT_RDATA after write ISP_LUT_CMD register + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: LSC_TABLESIZE + description: LSC point in x-direction + addressOffset: 84 + size: 32 + resetValue: 31 + fields: + - name: LSC_XTABLESIZE + description: this field configures lsc table size in x-direction + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DEMOSAIC_MATRIX_CTRL + description: demosaic pix2matrix ctrl + addressOffset: 88 + size: 32 + fields: + - name: DEMOSAIC_TAIL_PIXEN_PULSE_TL + description: "matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: DEMOSAIC_TAIL_PIXEN_PULSE_TH + description: "matrix tail pixen high level threshold, must < hnum-1, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: DEMOSAIC_PADDING_DATA + description: this field configures demosaic matrix padding data + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: DEMOSAIC_PADDING_MODE + description: "this bit configures the padding mode of demosaic matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding" + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: DEMOSAIC_GRAD_RATIO + description: demosaic gradient select ratio + addressOffset: 92 + size: 32 + resetValue: 16 + fields: + - name: DEMOSAIC_GRAD_RATIO + description: this field configures demosaic gradient select ratio + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: MEDIAN_MATRIX_CTRL + description: median pix2matrix ctrl + addressOffset: 96 + size: 32 + fields: + - name: MEDIAN_PADDING_DATA + description: this field configures median matrix padding data + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: MEDIAN_PADDING_MODE + description: "this bit configures the padding mode of median matrix. 0: use pixel in image to do padding 1: use reg_padding_data to do padding" + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: raw interrupt register + addressOffset: 100 + size: 32 + fields: + - name: ISP_DATA_TYPE_ERR_INT_RAW + description: "the raw interrupt status of input data type error. isp only support RGB bayer data type, other type will report type_err_int" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ISP_ASYNC_FIFO_OVF_INT_RAW + description: the raw interrupt status of isp input fifo overflow + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ISP_BUF_FULL_INT_RAW + description: the raw interrupt status of isp input buffer full + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: ISP_HVNUM_SETTING_ERR_INT_RAW + description: the raw interrupt status of hnum and vnum setting format error + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: ISP_DATA_TYPE_SETTING_ERR_INT_RAW + description: the raw interrupt status of setting invalid reg_data_type + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ISP_MIPI_HNUM_UNMATCH_INT_RAW + description: the raw interrupt status of hnum setting unmatch with mipi input + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: DPC_CHECK_DONE_INT_RAW + description: the raw interrupt status of dpc check done + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: GAMMA_XCOORD_ERR_INT_RAW + description: "the raw interrupt status of gamma setting error. it report the sum of the lengths represented by reg_gamma_x00~x0F isn't equal to 256" + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: AE_MONITOR_INT_RAW + description: the raw interrupt status of ae monitor + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: AE_FRAME_DONE_INT_RAW + description: the raw interrupt status of ae. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: AF_FDONE_INT_RAW + description: "the raw interrupt status of af statistic. when auto_update enable, each frame done will send one int pulse when manual_update, each time when write 1 to reg_manual_update will send a int pulse when next frame done" + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: AF_ENV_INT_RAW + description: the raw interrupt status of af monitor. send a int pulse when env_det function enabled and environment changes detected + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: AWB_FDONE_INT_RAW + description: the raw interrupt status of awb. send a int pulse when statistic of one awb frame done + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: HIST_FDONE_INT_RAW + description: the raw interrupt status of histogram. send a int pulse when statistic of one frame histogram done + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: FRAME_INT_RAW + description: the raw interrupt status of isp frame end + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: BLC_FRAME_INT_RAW + description: the raw interrupt status of blc frame done + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: LSC_FRAME_INT_RAW + description: the raw interrupt status of lsc frame done + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: DPC_FRAME_INT_RAW + description: the raw interrupt status of dpc frame done + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: BF_FRAME_INT_RAW + description: the raw interrupt status of bf frame done + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: DEMOSAIC_FRAME_INT_RAW + description: the raw interrupt status of demosaic frame done + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: MEDIAN_FRAME_INT_RAW + description: the raw interrupt status of median frame done + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: CCM_FRAME_INT_RAW + description: the raw interrupt status of ccm frame done + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: GAMMA_FRAME_INT_RAW + description: the raw interrupt status of gamma frame done + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: RGB2YUV_FRAME_INT_RAW + description: the raw interrupt status of rgb2yuv frame done + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: SHARP_FRAME_INT_RAW + description: the raw interrupt status of sharp frame done + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: COLOR_FRAME_INT_RAW + description: the raw interrupt status of color frame done + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: YUV2RGB_FRAME_INT_RAW + description: the raw interrupt status of yuv2rgb frame done + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: TAIL_IDI_FRAME_INT_RAW + description: the raw interrupt status of isp_tail idi frame_end + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: HEADER_IDI_FRAME_INT_RAW + description: the raw interrupt status of real input frame end of isp_input + bitOffset: 28 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: masked interrupt register + addressOffset: 104 + size: 32 + fields: + - name: ISP_DATA_TYPE_ERR_INT_ST + description: the masked interrupt status of input data type error + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ISP_ASYNC_FIFO_OVF_INT_ST + description: the masked interrupt status of isp input fifo overflow + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ISP_BUF_FULL_INT_ST + description: the masked interrupt status of isp input buffer full + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: ISP_HVNUM_SETTING_ERR_INT_ST + description: the masked interrupt status of hnum and vnum setting format error + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: ISP_DATA_TYPE_SETTING_ERR_INT_ST + description: the masked interrupt status of setting invalid reg_data_type + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ISP_MIPI_HNUM_UNMATCH_INT_ST + description: the masked interrupt status of hnum setting unmatch with mipi input + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: DPC_CHECK_DONE_INT_ST + description: the masked interrupt status of dpc check done + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: GAMMA_XCOORD_ERR_INT_ST + description: the masked interrupt status of gamma setting error + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: AE_MONITOR_INT_ST + description: the masked interrupt status of ae monitor + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: AE_FRAME_DONE_INT_ST + description: the masked interrupt status of ae + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: AF_FDONE_INT_ST + description: the masked interrupt status of af statistic + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: AF_ENV_INT_ST + description: the masked interrupt status of af monitor + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: AWB_FDONE_INT_ST + description: the masked interrupt status of awb + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: HIST_FDONE_INT_ST + description: the masked interrupt status of histogram + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: FRAME_INT_ST + description: the masked interrupt status of isp frame end + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: BLC_FRAME_INT_ST + description: the masked interrupt status of blc frame done + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: LSC_FRAME_INT_ST + description: the masked interrupt status of lsc frame done + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: DPC_FRAME_INT_ST + description: the masked interrupt status of dpc frame done + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: BF_FRAME_INT_ST + description: the masked interrupt status of bf frame done + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: DEMOSAIC_FRAME_INT_ST + description: the masked interrupt status of demosaic frame done + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: MEDIAN_FRAME_INT_ST + description: the masked interrupt status of median frame done + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: CCM_FRAME_INT_ST + description: the masked interrupt status of ccm frame done + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: GAMMA_FRAME_INT_ST + description: the masked interrupt status of gamma frame done + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: RGB2YUV_FRAME_INT_ST + description: the masked interrupt status of rgb2yuv frame done + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: SHARP_FRAME_INT_ST + description: the masked interrupt status of sharp frame done + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: COLOR_FRAME_INT_ST + description: the masked interrupt status of color frame done + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: YUV2RGB_FRAME_INT_ST + description: the masked interrupt status of yuv2rgb frame done + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: TAIL_IDI_FRAME_INT_ST + description: the masked interrupt status of isp_tail idi frame_end + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: HEADER_IDI_FRAME_INT_ST + description: the masked interrupt status of real input frame end of isp_input + bitOffset: 28 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: interrupt enable register + addressOffset: 108 + size: 32 + resetValue: 195 + fields: + - name: ISP_DATA_TYPE_ERR_INT_ENA + description: write 1 to enable input data type error + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ISP_ASYNC_FIFO_OVF_INT_ENA + description: write 1 to enable isp input fifo overflow + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ISP_BUF_FULL_INT_ENA + description: write 1 to enable isp input buffer full + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ISP_HVNUM_SETTING_ERR_INT_ENA + description: write 1 to enable hnum and vnum setting format error + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ISP_DATA_TYPE_SETTING_ERR_INT_ENA + description: write 1 to enable setting invalid reg_data_type + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ISP_MIPI_HNUM_UNMATCH_INT_ENA + description: write 1 to enable hnum setting unmatch with mipi input + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DPC_CHECK_DONE_INT_ENA + description: write 1 to enable dpc check done + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: GAMMA_XCOORD_ERR_INT_ENA + description: write 1 to enable gamma setting error + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: AE_MONITOR_INT_ENA + description: write 1 to enable ae monitor + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: AE_FRAME_DONE_INT_ENA + description: write 1 to enable ae + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: AF_FDONE_INT_ENA + description: write 1 to enable af statistic + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: AF_ENV_INT_ENA + description: write 1 to enable af monitor + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: AWB_FDONE_INT_ENA + description: write 1 to enable awb + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: HIST_FDONE_INT_ENA + description: write 1 to enable histogram + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FRAME_INT_ENA + description: write 1 to enable isp frame end + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: BLC_FRAME_INT_ENA + description: write 1 to enable blc frame done + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: LSC_FRAME_INT_ENA + description: write 1 to enable lsc frame done + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DPC_FRAME_INT_ENA + description: write 1 to enable dpc frame done + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: BF_FRAME_INT_ENA + description: write 1 to enable bf frame done + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: DEMOSAIC_FRAME_INT_ENA + description: write 1 to enable demosaic frame done + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: MEDIAN_FRAME_INT_ENA + description: write 1 to enable median frame done + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CCM_FRAME_INT_ENA + description: write 1 to enable ccm frame done + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: GAMMA_FRAME_INT_ENA + description: write 1 to enable gamma frame done + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RGB2YUV_FRAME_INT_ENA + description: write 1 to enable rgb2yuv frame done + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SHARP_FRAME_INT_ENA + description: write 1 to enable sharp frame done + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: COLOR_FRAME_INT_ENA + description: write 1 to enable color frame done + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: YUV2RGB_FRAME_INT_ENA + description: write 1 to enable yuv2rgb frame done + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TAIL_IDI_FRAME_INT_ENA + description: write 1 to enable isp_tail idi frame_end + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HEADER_IDI_FRAME_INT_ENA + description: write 1 to enable real input frame end of isp_input + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: interrupt clear register + addressOffset: 112 + size: 32 + fields: + - name: ISP_DATA_TYPE_ERR_INT_CLR + description: write 1 to clear input data type error + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ISP_ASYNC_FIFO_OVF_INT_CLR + description: write 1 to clear isp input fifo overflow + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: ISP_BUF_FULL_INT_CLR + description: write 1 to clear isp input buffer full + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: ISP_HVNUM_SETTING_ERR_INT_CLR + description: write 1 to clear hnum and vnum setting format error + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: ISP_DATA_TYPE_SETTING_ERR_INT_CLR + description: write 1 to clear setting invalid reg_data_type + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: ISP_MIPI_HNUM_UNMATCH_INT_CLR + description: write 1 to clear hnum setting unmatch with mipi input + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: DPC_CHECK_DONE_INT_CLR + description: write 1 to clear dpc check done + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: GAMMA_XCOORD_ERR_INT_CLR + description: write 1 to clear gamma setting error + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: AE_MONITOR_INT_CLR + description: write 1 to clear ae monitor + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: AE_FRAME_DONE_INT_CLR + description: write 1 to clear ae + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: AF_FDONE_INT_CLR + description: write 1 to clear af statistic + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: AF_ENV_INT_CLR + description: write 1 to clear af monitor + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: AWB_FDONE_INT_CLR + description: write 1 to clear awb + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: HIST_FDONE_INT_CLR + description: write 1 to clear histogram + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: FRAME_INT_CLR + description: write 1 to clear isp frame end + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: BLC_FRAME_INT_CLR + description: write 1 to clear blc frame done + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: LSC_FRAME_INT_CLR + description: write 1 to clear lsc frame done + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: DPC_FRAME_INT_CLR + description: write 1 to clear dpc frame done + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: BF_FRAME_INT_CLR + description: write 1 to clear bf frame done + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: DEMOSAIC_FRAME_INT_CLR + description: write 1 to clear demosaic frame done + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: MEDIAN_FRAME_INT_CLR + description: write 1 to clear median frame done + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: CCM_FRAME_INT_CLR + description: write 1 to clear ccm frame done + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: GAMMA_FRAME_INT_CLR + description: write 1 to clear gamma frame done + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: RGB2YUV_FRAME_INT_CLR + description: write 1 to clear rgb2yuv frame done + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: SHARP_FRAME_INT_CLR + description: write 1 to clear sharp frame done + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: COLOR_FRAME_INT_CLR + description: write 1 to clear color frame done + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: YUV2RGB_FRAME_INT_CLR + description: write 1 to clear yuv2rgb frame done + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: TAIL_IDI_FRAME_INT_CLR + description: write 1 to clear isp_tail idi frame_end + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: HEADER_IDI_FRAME_INT_CLR + description: write 1 to clear real input frame end of isp_input + bitOffset: 28 + bitWidth: 1 + access: write-only + - register: + name: GAMMA_CTRL + description: gamma control register + addressOffset: 116 + size: 32 + resetValue: 14 + fields: + - name: GAMMA_UPDATE + description: Indicates that gamma register configuration is complete + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: GAMMA_B_LAST_CORRECT + description: "this bit configures enable of last b segment correcction. 0: disable, 1: enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: GAMMA_G_LAST_CORRECT + description: "this bit configures enable of last g segment correcction. 0: disable, 1: enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: GAMMA_R_LAST_CORRECT + description: "this bit configures enable of last r segment correcction. 0: disable, 1: enable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: GAMMA_RY1 + description: point of Y-axis of r channel gamma curve register 1 + addressOffset: 120 + size: 32 + resetValue: 270544960 + fields: + - name: GAMMA_R_Y03 + description: this field configures the point 3 of Y-axis of r channel gamma curve + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GAMMA_R_Y02 + description: this field configures the point 2 of Y-axis of r channel gamma curve + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: GAMMA_R_Y01 + description: this field configures the point 1 of Y-axis of r channel gamma curve + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: GAMMA_R_Y00 + description: this field configures the point 0 of Y-axis of r channel gamma curve + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: GAMMA_RY2 + description: point of Y-axis of r channel gamma curve register 2 + addressOffset: 124 + size: 32 + resetValue: 1348497536 + fields: + - name: GAMMA_R_Y07 + description: this field configures the point 7 of Y-axis of r channel gamma curve + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GAMMA_R_Y06 + description: this field configures the point 6 of Y-axis of r channel gamma curve + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: GAMMA_R_Y05 + description: this field configures the point 5 of Y-axis of r channel gamma curve + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: GAMMA_R_Y04 + description: this field configures the point 4 of Y-axis of r channel gamma curve + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: GAMMA_RY3 + description: point of Y-axis of r channel gamma curve register 3 + addressOffset: 128 + size: 32 + resetValue: 2426450112 + fields: + - name: GAMMA_R_Y0B + description: this field configures the point 11 of Y-axis of r channel gamma curve + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GAMMA_R_Y0A + description: this field configures the point 10 of Y-axis of r channel gamma curve + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: GAMMA_R_Y09 + description: this field configures the point 9 of Y-axis of r channel gamma curve + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: GAMMA_R_Y08 + description: this field configures the point 8 of Y-axis of r channel gamma curve + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: GAMMA_RY4 + description: point of Y-axis of r channel gamma curve register 4 + addressOffset: 132 + size: 32 + resetValue: 3504402687 + fields: + - name: GAMMA_R_Y0F + description: this field configures the point 15 of Y-axis of r channel gamma curve + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GAMMA_R_Y0E + description: this field configures the point 14 of Y-axis of r channel gamma curve + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: GAMMA_R_Y0D + description: this field configures the point 13 of Y-axis of r channel gamma curve + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: GAMMA_R_Y0C + description: this field configures the point 12 of Y-axis of r channel gamma curve + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: GAMMA_GY1 + description: point of Y-axis of g channel gamma curve register 1 + addressOffset: 136 + size: 32 + resetValue: 270544960 + fields: + - name: GAMMA_G_Y03 + description: this field configures the point 3 of Y-axis of g channel gamma curve + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GAMMA_G_Y02 + description: this field configures the point 2 of Y-axis of g channel gamma curve + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: GAMMA_G_Y01 + description: this field configures the point 1 of Y-axis of g channel gamma curve + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: GAMMA_G_Y00 + description: this field configures the point 0 of Y-axis of g channel gamma curve + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: GAMMA_GY2 + description: point of Y-axis of g channel gamma curve register 2 + addressOffset: 140 + size: 32 + resetValue: 1348497536 + fields: + - name: GAMMA_G_Y07 + description: this field configures the point 7 of Y-axis of g channel gamma curve + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GAMMA_G_Y06 + description: this field configures the point 6 of Y-axis of g channel gamma curve + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: GAMMA_G_Y05 + description: this field configures the point 5 of Y-axis of g channel gamma curve + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: GAMMA_G_Y04 + description: this field configures the point 4 of Y-axis of g channel gamma curve + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: GAMMA_GY3 + description: point of Y-axis of g channel gamma curve register 3 + addressOffset: 144 + size: 32 + resetValue: 2426450112 + fields: + - name: GAMMA_G_Y0B + description: this field configures the point 11 of Y-axis of g channel gamma curve + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GAMMA_G_Y0A + description: this field configures the point 10 of Y-axis of g channel gamma curve + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: GAMMA_G_Y09 + description: this field configures the point 9 of Y-axis of g channel gamma curve + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: GAMMA_G_Y08 + description: this field configures the point 8 of Y-axis of g channel gamma curve + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: GAMMA_GY4 + description: point of Y-axis of g channel gamma curve register 4 + addressOffset: 148 + size: 32 + resetValue: 3504402687 + fields: + - name: GAMMA_G_Y0F + description: this field configures the point 15 of Y-axis of g channel gamma curve + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GAMMA_G_Y0E + description: this field configures the point 14 of Y-axis of g channel gamma curve + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: GAMMA_G_Y0D + description: this field configures the point 13 of Y-axis of g channel gamma curve + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: GAMMA_G_Y0C + description: this field configures the point 12 of Y-axis of g channel gamma curve + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: GAMMA_BY1 + description: point of Y-axis of b channel gamma curve register 1 + addressOffset: 152 + size: 32 + resetValue: 270544960 + fields: + - name: GAMMA_B_Y03 + description: this field configures the point 3 of Y-axis of b channel gamma curve + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GAMMA_B_Y02 + description: this field configures the point 2 of Y-axis of b channel gamma curve + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: GAMMA_B_Y01 + description: this field configures the point 1 of Y-axis of b channel gamma curve + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: GAMMA_B_Y00 + description: this field configures the point 0 of Y-axis of b channel gamma curve + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: GAMMA_BY2 + description: point of Y-axis of b channel gamma curve register 2 + addressOffset: 156 + size: 32 + resetValue: 1348497536 + fields: + - name: GAMMA_B_Y07 + description: this field configures the point 7 of Y-axis of b channel gamma curve + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GAMMA_B_Y06 + description: this field configures the point 6 of Y-axis of b channel gamma curve + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: GAMMA_B_Y05 + description: this field configures the point 5 of Y-axis of b channel gamma curve + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: GAMMA_B_Y04 + description: this field configures the point 4 of Y-axis of b channel gamma curve + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: GAMMA_BY3 + description: point of Y-axis of b channel gamma curve register 3 + addressOffset: 160 + size: 32 + resetValue: 2426450112 + fields: + - name: GAMMA_B_Y0B + description: this field configures the point 11 of Y-axis of b channel gamma curve + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GAMMA_B_Y0A + description: this field configures the point 10 of Y-axis of b channel gamma curve + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: GAMMA_B_Y09 + description: this field configures the point 9 of Y-axis of b channel gamma curve + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: GAMMA_B_Y08 + description: this field configures the point 8 of Y-axis of b channel gamma curve + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: GAMMA_BY4 + description: point of Y-axis of b channel gamma curve register 4 + addressOffset: 164 + size: 32 + resetValue: 3504402687 + fields: + - name: GAMMA_B_Y0F + description: this field configures the point 15 of Y-axis of b channel gamma curve + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GAMMA_B_Y0E + description: this field configures the point 14 of Y-axis of b channel gamma curve + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: GAMMA_B_Y0D + description: this field configures the point 13 of Y-axis of b channel gamma curve + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: GAMMA_B_Y0C + description: this field configures the point 12 of Y-axis of b channel gamma curve + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: GAMMA_RX1 + description: point of X-axis of r channel gamma curve register 1 + addressOffset: 168 + size: 32 + resetValue: 9586980 + fields: + - name: GAMMA_R_X07 + description: "this field configures the point 7 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: GAMMA_R_X06 + description: "this field configures the point 6 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: GAMMA_R_X05 + description: "this field configures the point 5 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: GAMMA_R_X04 + description: "this field configures the point 4 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: GAMMA_R_X03 + description: "this field configures the point 3 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: GAMMA_R_X02 + description: "this field configures the point 2 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: GAMMA_R_X01 + description: "this field configures the point 1 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: GAMMA_R_X00 + description: "this field configures the point 0 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 21 + bitWidth: 3 + access: read-write + - register: + name: GAMMA_RX2 + description: point of X-axis of r channel gamma curve register 2 + addressOffset: 172 + size: 32 + resetValue: 9586980 + fields: + - name: GAMMA_R_X0F + description: "this field configures the point 15 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: GAMMA_R_X0E + description: "this field configures the point 14 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: GAMMA_R_X0D + description: "this field configures the point 13 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: GAMMA_R_X0C + description: "this field configures the point 12 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: GAMMA_R_X0B + description: "this field configures the point 11 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: GAMMA_R_X0A + description: "this field configures the point 10 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: GAMMA_R_X09 + description: "this field configures the point 9 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: GAMMA_R_X08 + description: "this field configures the point 8 of X-axis of r channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 21 + bitWidth: 3 + access: read-write + - register: + name: GAMMA_GX1 + description: point of X-axis of g channel gamma curve register 1 + addressOffset: 176 + size: 32 + resetValue: 9586980 + fields: + - name: GAMMA_G_X07 + description: "this field configures the point 7 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: GAMMA_G_X06 + description: "this field configures the point 6 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: GAMMA_G_X05 + description: "this field configures the point 5 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: GAMMA_G_X04 + description: "this field configures the point 4 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: GAMMA_G_X03 + description: "this field configures the point 3 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: GAMMA_G_X02 + description: "this field configures the point 2 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: GAMMA_G_X01 + description: "this field configures the point 1 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: GAMMA_G_X00 + description: "this field configures the point 0 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 21 + bitWidth: 3 + access: read-write + - register: + name: GAMMA_GX2 + description: point of X-axis of g channel gamma curve register 2 + addressOffset: 180 + size: 32 + resetValue: 9586980 + fields: + - name: GAMMA_G_X0F + description: "this field configures the point 15 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: GAMMA_G_X0E + description: "this field configures the point 14 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: GAMMA_G_X0D + description: "this field configures the point 13 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: GAMMA_G_X0C + description: "this field configures the point 12 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: GAMMA_G_X0B + description: "this field configures the point 11 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: GAMMA_G_X0A + description: "this field configures the point 10 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: GAMMA_G_X09 + description: "this field configures the point 9 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: GAMMA_G_X08 + description: "this field configures the point 8 of X-axis of g channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 21 + bitWidth: 3 + access: read-write + - register: + name: GAMMA_BX1 + description: point of X-axis of b channel gamma curve register 1 + addressOffset: 184 + size: 32 + resetValue: 9586980 + fields: + - name: GAMMA_B_X07 + description: "this field configures the point 7 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: GAMMA_B_X06 + description: "this field configures the point 6 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: GAMMA_B_X05 + description: "this field configures the point 5 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: GAMMA_B_X04 + description: "this field configures the point 4 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: GAMMA_B_X03 + description: "this field configures the point 3 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: GAMMA_B_X02 + description: "this field configures the point 2 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: GAMMA_B_X01 + description: "this field configures the point 1 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: GAMMA_B_X00 + description: "this field configures the point 0 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 21 + bitWidth: 3 + access: read-write + - register: + name: GAMMA_BX2 + description: point of X-axis of b channel gamma curve register 2 + addressOffset: 188 + size: 32 + resetValue: 9586980 + fields: + - name: GAMMA_B_X0F + description: "this field configures the point 15 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: GAMMA_B_X0E + description: "this field configures the point 14 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: GAMMA_B_X0D + description: "this field configures the point 13 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: GAMMA_B_X0C + description: "this field configures the point 12 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: GAMMA_B_X0B + description: "this field configures the point 11 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: GAMMA_B_X0A + description: "this field configures the point 10 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: GAMMA_B_X09 + description: "this field configures the point 9 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: GAMMA_B_X08 + description: "this field configures the point 8 of X-axis of b channel gamma curve, it represents the power of the distance from the previous point" + bitOffset: 21 + bitWidth: 3 + access: read-write + - register: + name: AE_CTRL + description: ae control register + addressOffset: 192 + size: 32 + fields: + - name: AE_UPDATE + description: write 1 to this bit triggers one statistic event + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: AE_SELECT + description: "this field configures ae input data source, 0: data from median, 1: data from gama" + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: AE_MONITOR + description: ae monitor control register + addressOffset: 196 + size: 32 + fields: + - name: TL + description: this field configures the lower lum threshold of ae monitor + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TH + description: this field configures the higher lum threshold of ae monitor + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: PERIOD + description: this field cnfigures ae monitor frame period + bitOffset: 16 + bitWidth: 6 + access: read-write + - register: + name: AE_BX + description: ae window register in x-direction + addressOffset: 200 + size: 32 + resetValue: 384 + fields: + - name: AE_X_BSIZE + description: this field configures every block x size + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: AE_X_START + description: this field configures first block start x address + bitOffset: 11 + bitWidth: 11 + access: read-write + - register: + name: AE_BY + description: ae window register in y-direction + addressOffset: 204 + size: 32 + resetValue: 216 + fields: + - name: AE_Y_BSIZE + description: this field configures every block y size + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: AE_Y_START + description: this field configures first block start y address + bitOffset: 11 + bitWidth: 11 + access: read-write + - register: + name: AE_WINPIXNUM + description: ae sub-window pix num register + addressOffset: 208 + size: 32 + resetValue: 82944 + fields: + - name: AE_SUBWIN_PIXNUM + description: this field configures the pixel number of each sub win + bitOffset: 0 + bitWidth: 17 + access: read-write + - register: + name: AE_WIN_RECIPROCAL + description: reciprocal of ae sub-window pixel number + addressOffset: 212 + size: 32 + fields: + - name: AE_SUBWIN_RECIP + description: "this field configures the reciprocal of each subwin_pixnum, 20bit fraction" + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: AE_BLOCK_MEAN_0 + description: ae statistic result register 0 + addressOffset: 216 + size: 32 + fields: + - name: AE_B03_MEAN + description: this field configures block03 Y mean data + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: AE_B02_MEAN + description: this field configures block02 Y mean data + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: AE_B01_MEAN + description: this field configures block01 Y mean data + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: AE_B00_MEAN + description: this field configures block00 Y mean data + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: AE_BLOCK_MEAN_1 + description: ae statistic result register 1 + addressOffset: 220 + size: 32 + fields: + - name: AE_B12_MEAN + description: this field configures block12 Y mean data + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: AE_B11_MEAN + description: this field configures block11 Y mean data + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: AE_B10_MEAN + description: this field configures block10 Y mean data + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: AE_B04_MEAN + description: this field configures block04 Y mean data + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: AE_BLOCK_MEAN_2 + description: ae statistic result register 2 + addressOffset: 224 + size: 32 + fields: + - name: AE_B21_MEAN + description: this field configures block21 Y mean data + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: AE_B20_MEAN + description: this field configures block20 Y mean data + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: AE_B14_MEAN + description: this field configures block14 Y mean data + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: AE_B13_MEAN + description: this field configures block13 Y mean data + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: AE_BLOCK_MEAN_3 + description: ae statistic result register 3 + addressOffset: 228 + size: 32 + fields: + - name: AE_B30_MEAN + description: this field configures block30 Y mean data + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: AE_B24_MEAN + description: this field configures block24 Y mean data + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: AE_B23_MEAN + description: this field configures block23 Y mean data + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: AE_B22_MEAN + description: this field configures block22 Y mean data + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: AE_BLOCK_MEAN_4 + description: ae statistic result register 4 + addressOffset: 232 + size: 32 + fields: + - name: AE_B34_MEAN + description: this field configures block34 Y mean data + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: AE_B33_MEAN + description: this field configures block33 Y mean data + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: AE_B32_MEAN + description: this field configures block32 Y mean data + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: AE_B31_MEAN + description: this field configures block31 Y mean data + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: AE_BLOCK_MEAN_5 + description: ae statistic result register 5 + addressOffset: 236 + size: 32 + fields: + - name: AE_B43_MEAN + description: this field configures block43 Y mean data + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: AE_B42_MEAN + description: this field configures block42 Y mean data + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: AE_B41_MEAN + description: this field configures block41 Y mean data + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: AE_B40_MEAN + description: this field configures block40 Y mean data + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: AE_BLOCK_MEAN_6 + description: ae statistic result register 6 + addressOffset: 240 + size: 32 + fields: + - name: AE_B44_MEAN + description: this field configures block44 Y mean data + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: SHARP_CTRL0 + description: sharp control register 0 + addressOffset: 244 + size: 32 + fields: + - name: SHARP_THRESHOLD_LOW + description: this field configures sharpen threshold for detail + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SHARP_THRESHOLD_HIGH + description: this field configures sharpen threshold for edge + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SHARP_AMOUNT_LOW + description: this field configures sharpen amount for detail + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SHARP_AMOUNT_HIGH + description: this field configures sharpen amount for edge + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: SHARP_FILTER0 + description: sharp usm config register 0 + addressOffset: 248 + size: 32 + resetValue: 1089 + fields: + - name: SHARP_FILTER_COE00 + description: this field configures unsharp masking(usm) filter coefficient + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: SHARP_FILTER_COE01 + description: this field configures usm filter coefficient + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: SHARP_FILTER_COE02 + description: this field configures usm filter coefficient + bitOffset: 10 + bitWidth: 5 + access: read-write + - register: + name: SHARP_FILTER1 + description: sharp usm config register 1 + addressOffset: 252 + size: 32 + resetValue: 2178 + fields: + - name: SHARP_FILTER_COE10 + description: this field configures usm filter coefficient + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: SHARP_FILTER_COE11 + description: this field configures usm filter coefficient + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: SHARP_FILTER_COE12 + description: this field configures usm filter coefficient + bitOffset: 10 + bitWidth: 5 + access: read-write + - register: + name: SHARP_FILTER2 + description: sharp usm config register 2 + addressOffset: 256 + size: 32 + resetValue: 1089 + fields: + - name: SHARP_FILTER_COE20 + description: this field configures usm filter coefficient + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: SHARP_FILTER_COE21 + description: this field configures usm filter coefficient + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: SHARP_FILTER_COE22 + description: this field configures usm filter coefficient + bitOffset: 10 + bitWidth: 5 + access: read-write + - register: + name: SHARP_MATRIX_CTRL + description: sharp pix2matrix ctrl + addressOffset: 260 + size: 32 + fields: + - name: SHARP_TAIL_PIXEN_PULSE_TL + description: "matrix tail pixen low level threshold, should not to large to prevent expanding to next frame, only reg_demosaic_tail_pixen_pulse_th!=0 and reg_demosaic_tail_pixen_pulse_tl!=0 and reg_demosaic_tail_pixen_pulse_th < reg_demosaic_tail_pixen_pulse_tl will enable tail pulse function" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SHARP_TAIL_PIXEN_PULSE_TH + description: "matrix tail pixen high level threshold, must < hnum-1, only reg_sharp_tail_pixen_pulse_th!=0 and reg_sharp_tail_pixen_pulse_tl!=0 and reg_sharp_tail_pixen_pulse_th < reg_sharp_tail_pixen_pulse_tl will enable tail pulse function" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SHARP_PADDING_DATA + description: this field configures sharp padding data + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SHARP_PADDING_MODE + description: this field configures sharp padding mode + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: SHARP_CTRL1 + description: sharp control register 1 + addressOffset: 264 + size: 32 + fields: + - name: SHARP_GRADIENT_MAX + description: "this field configures sharp max gradient, refresh at the end of each frame end" + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: DMA_CNTL + description: isp dma source trans control register + addressOffset: 268 + size: 32 + resetValue: 1081512 + fields: + - name: DMA_EN + description: write 1 to triger dma to get 1 frame + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: DMA_UPDATE + description: write 1 to update reg_dma_burst_len & reg_dma_data_type + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DMA_DATA_TYPE + description: this field configures the idi data type for image data + bitOffset: 2 + bitWidth: 6 + access: read-write + - name: DMA_BURST_LEN + description: "this field configures dma burst len when data source is dma. set according to dma_msize, it is the number of 64bits in a dma transfer" + bitOffset: 8 + bitWidth: 12 + access: read-write + - name: DMA_INTERVAL + description: "this field configures dma req interval, 12'b1: 1 cycle, 12'b11 2 cycle ..." + bitOffset: 20 + bitWidth: 12 + access: read-write + - register: + name: DMA_RAW_DATA + description: isp dma source total raw number set register + addressOffset: 272 + size: 32 + fields: + - name: DMA_RAW_NUM_TOTAL + description: this field configures the the number of 64bits in a frame + bitOffset: 0 + bitWidth: 22 + access: read-write + - name: DMA_RAW_NUM_TOTAL_SET + description: write 1 to update reg_dma_raw_num_total + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: CAM_CNTL + description: isp cam source control register + addressOffset: 276 + size: 32 + resetValue: 4 + fields: + - name: CAM_EN + description: "write 1 to start recive camera data, write 0 to disable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CAM_UPDATE + description: write 1 to update ISP_CAM_CONF + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CAM_RESET + description: "this bit configures cam clk domain reset, 1: reset cam input logic, 0: release reset" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CAM_CLK_INV + description: "this bit configures the invertion of cam clk from pad. 0: not invert cam clk, 1: invert cam clk" + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: CAM_CONF + description: isp cam source config register + addressOffset: 280 + size: 32 + resetValue: 168 + fields: + - name: CAM_DATA_ORDER + description: "this field configures data order of cam port, 0: cam_data_in, 1:{cam_data_in[7:0], cam_data_in[15:8]}" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CAM_2BYTE_MODE + description: "this field configures enable of cam 2 byte mode(input 2 bytes each clock). 0: disable, 1: enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CAM_DATA_TYPE + description: "this field configures idi data type for image data, 0x2a: RAW8, 0x2b: RAW10, 0x2c: RAW12" + bitOffset: 2 + bitWidth: 6 + access: read-write + - name: CAM_DE_INV + description: "this bit configures cam data enable invert. 0: not invert, 1: invert" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CAM_HSYNC_INV + description: "this bit configures cam hsync invert. 0: not invert, 1: invert" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CAM_VSYNC_INV + description: "this bit configures cam vsync invert. 0: not invert, 1: invert" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CAM_VSYNC_FILTER_THRES + description: this bit configures the number of clock of vsync filter length + bitOffset: 11 + bitWidth: 3 + access: read-write + - name: CAM_VSYNC_FILTER_EN + description: this bit configures vsync filter en + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: AF_CTRL0 + description: af control register 0 + addressOffset: 284 + size: 32 + fields: + - name: AF_AUTO_UPDATE + description: "this bit configures auto_update enable. when set to 1, will update sum and lum each frame" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: AF_MANUAL_UPDATE + description: write 1 to this bit will update the sum and lum once + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: AF_ENV_THRESHOLD + description: "this field configures env threshold. when both sum and lum changes larger than this value, consider environment changes and need to trigger a new autofocus. 4Bit fractional" + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: AF_ENV_PERIOD + description: "this field configures environment changes detection period (frame). When set to 0, disable this function" + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: AF_CTRL1 + description: af control register 1 + addressOffset: 288 + size: 32 + fields: + - name: AF_THPIXNUM + description: this field configures pixnum used when calculating the autofocus threshold. Set to 0 to disable threshold calculation + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: AF_GEN_TH_CTRL + description: af gen threshold control register + addressOffset: 292 + size: 32 + resetValue: 71303296 + fields: + - name: AF_GEN_THRESHOLD_MIN + description: this field configures min threshold when use auto_threshold + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: AF_GEN_THRESHOLD_MAX + description: this field configures max threshold when use auto_threshold + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: AF_ENV_USER_TH_SUM + description: af monitor user sum threshold register + addressOffset: 296 + size: 32 + fields: + - name: AF_ENV_USER_THRESHOLD_SUM + description: this field configures user setup env detect sum threshold + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: AF_ENV_USER_TH_LUM + description: af monitor user lum threshold register + addressOffset: 300 + size: 32 + fields: + - name: AF_ENV_USER_THRESHOLD_LUM + description: this field configures user setup env detect lum threshold + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: AF_THRESHOLD + description: af threshold register + addressOffset: 304 + size: 32 + resetValue: 256 + fields: + - name: AF_THRESHOLD + description: "this field configures user threshold. When set to non-zero, autofocus will use this threshold" + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: AF_GEN_THRESHOLD + description: this field represents the last calculated threshold + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: AF_HSCALE_A + description: h-scale of af window a register + addressOffset: 308 + size: 32 + resetValue: 65664 + fields: + - name: AF_RPOINT_A + description: "this field configures left coordinate of focus window a, must >= 2" + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: AF_LPOINT_A + description: "this field configures top coordinate of focus window a, must >= 2" + bitOffset: 16 + bitWidth: 12 + access: read-write + - register: + name: AF_VSCALE_A + description: v-scale of af window a register + addressOffset: 312 + size: 32 + resetValue: 65664 + fields: + - name: AF_BPOINT_A + description: "this field configures right coordinate of focus window a, must <= hnum-2" + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: AF_TPOINT_A + description: "this field configures bottom coordinate of focus window a, must <= hnum-2" + bitOffset: 16 + bitWidth: 12 + access: read-write + - register: + name: AF_HSCALE_B + description: h-scale of af window b register + addressOffset: 316 + size: 32 + resetValue: 65664 + fields: + - name: AF_RPOINT_B + description: "this field configures left coordinate of focus window b, must >= 2" + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: AF_LPOINT_B + description: "this field configures top coordinate of focus window b, must >= 2" + bitOffset: 16 + bitWidth: 12 + access: read-write + - register: + name: AF_VSCALE_B + description: v-scale of af window b register + addressOffset: 320 + size: 32 + resetValue: 65664 + fields: + - name: AF_BPOINT_B + description: "this field configures right coordinate of focus window b, must <= hnum-2" + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: AF_TPOINT_B + description: "this field configures bottom coordinate of focus window b, must <= hnum-2" + bitOffset: 16 + bitWidth: 12 + access: read-write + - register: + name: AF_HSCALE_C + description: v-scale of af window c register + addressOffset: 324 + size: 32 + resetValue: 65664 + fields: + - name: AF_RPOINT_C + description: "this field configures left coordinate of focus window c, must >= 2" + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: AF_LPOINT_C + description: "this field configures top coordinate of focus window c, must >= 2" + bitOffset: 16 + bitWidth: 12 + access: read-write + - register: + name: AF_VSCALE_C + description: v-scale of af window c register + addressOffset: 328 + size: 32 + resetValue: 65664 + fields: + - name: AF_BPOINT_C + description: "this field configures right coordinate of focus window c, must <= hnum-2" + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: AF_TPOINT_C + description: "this field configures bottom coordinate of focus window c, must <= hnum-2" + bitOffset: 16 + bitWidth: 12 + access: read-write + - register: + name: AF_SUM_A + description: result of sum of af window a + addressOffset: 332 + size: 32 + fields: + - name: AF_SUMA + description: this field represents the result of accumulation of pix grad of focus window a + bitOffset: 0 + bitWidth: 30 + access: read-only + - register: + name: AF_SUM_B + description: result of sum of af window b + addressOffset: 336 + size: 32 + fields: + - name: AF_SUMB + description: this field represents the result of accumulation of pix grad of focus window b + bitOffset: 0 + bitWidth: 30 + access: read-only + - register: + name: AF_SUM_C + description: result of sum of af window c + addressOffset: 340 + size: 32 + fields: + - name: AF_SUMC + description: this field represents the result of accumulation of pix grad of focus window c + bitOffset: 0 + bitWidth: 30 + access: read-only + - register: + name: AF_LUM_A + description: result of lum of af window a + addressOffset: 344 + size: 32 + fields: + - name: AF_LUMA + description: this field represents the result of accumulation of pix light of focus window a + bitOffset: 0 + bitWidth: 28 + access: read-only + - register: + name: AF_LUM_B + description: result of lum of af window b + addressOffset: 348 + size: 32 + fields: + - name: AF_LUMB + description: this field represents the result of accumulation of pix light of focus window b + bitOffset: 0 + bitWidth: 28 + access: read-only + - register: + name: AF_LUM_C + description: result of lum of af window c + addressOffset: 352 + size: 32 + fields: + - name: AF_LUMC + description: this field represents the result of accumulation of pix light of focus window c + bitOffset: 0 + bitWidth: 28 + access: read-only + - register: + name: AWB_MODE + description: awb mode control register + addressOffset: 356 + size: 32 + resetValue: 3 + fields: + - name: AWB_MODE + description: "this field configures awb algo sel. 00: none sellected. 01: sel algo0. 10: sel algo1. 11: sel both algo0 and algo1" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: AWB_SAMPLE + description: "this bit configures awb sample location, 0:before ccm, 1:after ccm" + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: AWB_HSCALE + description: h-scale of awb window + addressOffset: 360 + size: 32 + resetValue: 1919 + fields: + - name: AWB_RPOINT + description: this field configures awb window right coordinate + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: AWB_LPOINT + description: this field configures awb window left coordinate + bitOffset: 16 + bitWidth: 12 + access: read-write + - register: + name: AWB_VSCALE + description: v-scale of awb window + addressOffset: 364 + size: 32 + resetValue: 1079 + fields: + - name: AWB_BPOINT + description: this field configures awb window bottom coordinate + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: AWB_TPOINT + description: this field configures awb window top coordinate + bitOffset: 16 + bitWidth: 12 + access: read-write + - register: + name: AWB_TH_LUM + description: awb lum threshold register + addressOffset: 368 + size: 32 + resetValue: 50135040 + fields: + - name: AWB_MIN_LUM + description: this field configures lower threshold of r+g+b + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: AWB_MAX_LUM + description: this field configures upper threshold of r+g+b + bitOffset: 16 + bitWidth: 10 + access: read-write + - register: + name: AWB_TH_RG + description: awb r/g threshold register + addressOffset: 372 + size: 32 + resetValue: 67043328 + fields: + - name: AWB_MIN_RG + description: "this field configures lower threshold of r/g, 2bit integer and 8bit fraction" + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: AWB_MAX_RG + description: "this field configures upper threshold of r/g, 2bit integer and 8bit fraction" + bitOffset: 16 + bitWidth: 10 + access: read-write + - register: + name: AWB_TH_BG + description: awb b/g threshold register + addressOffset: 376 + size: 32 + resetValue: 67043328 + fields: + - name: AWB_MIN_BG + description: "this field configures lower threshold of b/g, 2bit integer and 8bit fraction" + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: AWB_MAX_BG + description: "this field configures upper threshold of b/g, 2bit integer and 8bit fraction" + bitOffset: 16 + bitWidth: 10 + access: read-write + - register: + name: AWB0_WHITE_CNT + description: result of awb white point number + addressOffset: 380 + size: 32 + fields: + - name: AWB0_WHITE_CNT + description: this field configures number of white point detected of algo0 + bitOffset: 0 + bitWidth: 24 + access: read-only + - register: + name: AWB0_ACC_R + description: result of accumulate of r channel of all white points + addressOffset: 384 + size: 32 + fields: + - name: AWB0_ACC_R + description: this field represents accumulate of channel r of all white point of algo0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: AWB0_ACC_G + description: result of accumulate of g channel of all white points + addressOffset: 388 + size: 32 + fields: + - name: AWB0_ACC_G + description: this field represents accumulate of channel g of all white point of algo0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: AWB0_ACC_B + description: result of accumulate of b channel of all white points + addressOffset: 392 + size: 32 + fields: + - name: AWB0_ACC_B + description: this field represents accumulate of channel b of all white point of algo0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: COLOR_CTRL + description: color control register + addressOffset: 396 + size: 32 + resetValue: 8388736 + fields: + - name: COLOR_SATURATION + description: this field configures the color saturation value + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: COLOR_HUE + description: this field configures the color hue angle + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: COLOR_CONTRAST + description: this field configures the color contrast value + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: COLOR_BRIGHTNESS + description: "this field configures the color brightness value, signed 2's complement" + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: BLC_VALUE + description: blc black level register + addressOffset: 400 + size: 32 + fields: + - name: BLC_R3_VALUE + description: this field configures the black level of bottom right channel of bayer img + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: BLC_R2_VALUE + description: this field configures the black level of bottom left channel of bayer img + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: BLC_R1_VALUE + description: this field configures the black level of top right channel of bayer img + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: BLC_R0_VALUE + description: this field configures the black level of top left channel of bayer img + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: BLC_CTRL0 + description: blc stretch control register + addressOffset: 404 + size: 32 + fields: + - name: BLC_R3_STRETCH + description: "this bit configures the stretch feature of bottom right channel. 0: stretch disable, 1: stretch enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: BLC_R2_STRETCH + description: "this bit configures the stretch feature of bottom left channel. 0: stretch disable, 1: stretch enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BLC_R1_STRETCH + description: "this bit configures the stretch feature of top right channel. 0: stretch disable, 1: stretch enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: BLC_R0_STRETCH + description: "this bit configures the stretch feature of top left channel. 0: stretch disable, 1: stretch enable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: BLC_CTRL1 + description: blc window control register + addressOffset: 408 + size: 32 + fields: + - name: BLC_WINDOW_TOP + description: this field configures blc average calculation window top + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: BLC_WINDOW_LEFT + description: this field configures blc average calculation window left + bitOffset: 11 + bitWidth: 11 + access: read-write + - name: BLC_WINDOW_VNUM + description: this field configures blc average calculation window vnum + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: BLC_WINDOW_HNUM + description: this field configures blc average calculation window hnum + bitOffset: 26 + bitWidth: 4 + access: read-write + - name: BLC_FILTER_EN + description: "this bit configures enable blc average input filter. 0: disable, 1: enable" + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: BLC_CTRL2 + description: blc black threshold control register + addressOffset: 412 + size: 32 + fields: + - name: BLC_R3_TH + description: this field configures black threshold when get blc average of bottom right channel + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: BLC_R2_TH + description: this field configures black threshold when get blc average of bottom left channel + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: BLC_R1_TH + description: this field configures black threshold when get blc average of top right channel + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: BLC_R0_TH + description: this field configures black threshold when get blc average of top left channel + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: BLC_MEAN + description: results of the average of black window + addressOffset: 416 + size: 32 + fields: + - name: BLC_R3_MEAN + description: this field represents the average black value of bottom right channel + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: BLC_R2_MEAN + description: this field represents the average black value of bottom left channel + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: BLC_R1_MEAN + description: this field represents the average black value of top right channel + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: BLC_R0_MEAN + description: this field represents the average black value of top left channel + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: HIST_MODE + description: histogram mode control register + addressOffset: 420 + size: 32 + resetValue: 4 + fields: + - name: HIST_MODE + description: "this field configures statistic mode. 0: RAW_B, 1: RAW_GB, 2: RAW_GR 3: RAW_R, 4: RGB, 5:YUV_Y, 6:YUV_U, 7:YUV_V" + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: HIST_COEFF + description: histogram rgb to gray coefficients register + addressOffset: 424 + size: 32 + resetValue: 5592405 + fields: + - name: B + description: "this field configures coefficient of B when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: G + description: "this field configures coefficient of G when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: R + description: "this field configures coefficient of R when set hist_mode to RGB, sum of coeff_r and coeff_g and coeff_b should be 256" + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: HIST_OFFS + description: histogram window offsets register + addressOffset: 428 + size: 32 + fields: + - name: HIST_Y_OFFS + description: this field configures y coordinate of first window + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: HIST_X_OFFS + description: this field configures x coordinate of first window + bitOffset: 16 + bitWidth: 12 + access: read-write + - register: + name: HIST_SIZE + description: histogram sub-window size register + addressOffset: 432 + size: 32 + resetValue: 1179680 + fields: + - name: HIST_Y_SIZE + description: this field configures y direction size of subwindow + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: HIST_X_SIZE + description: this field configures x direction size of subwindow + bitOffset: 16 + bitWidth: 9 + access: read-write + - register: + name: HIST_SEG0 + description: histogram bin control register 0 + addressOffset: 436 + size: 32 + resetValue: 270544960 + fields: + - name: HIST_SEG_3_4 + description: this field configures threshold of histogram bin 3 and bin 4 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HIST_SEG_2_3 + description: this field configures threshold of histogram bin 2 and bin 3 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HIST_SEG_1_2 + description: this field configures threshold of histogram bin 1 and bin 2 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HIST_SEG_0_1 + description: this field configures threshold of histogram bin 0 and bin 1 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HIST_SEG1 + description: histogram bin control register 1 + addressOffset: 440 + size: 32 + resetValue: 1348497536 + fields: + - name: HIST_SEG_7_8 + description: this field configures threshold of histogram bin 7 and bin 8 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HIST_SEG_6_7 + description: this field configures threshold of histogram bin 6 and bin 7 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HIST_SEG_5_6 + description: this field configures threshold of histogram bin 5 and bin 6 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HIST_SEG_4_5 + description: this field configures threshold of histogram bin 4 and bin 5 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HIST_SEG2 + description: histogram bin control register 2 + addressOffset: 444 + size: 32 + resetValue: 2426450112 + fields: + - name: HIST_SEG_11_12 + description: this field configures threshold of histogram bin 11 and bin 12 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HIST_SEG_10_11 + description: this field configures threshold of histogram bin 10 and bin 11 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HIST_SEG_9_10 + description: this field configures threshold of histogram bin 9 and bin 10 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HIST_SEG_8_9 + description: this field configures threshold of histogram bin 8 and bin 9 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HIST_SEG3 + description: histogram bin control register 3 + addressOffset: 448 + size: 32 + resetValue: 13689072 + fields: + - name: HIST_SEG_14_15 + description: this field configures threshold of histogram bin 14 and bin 15 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HIST_SEG_13_14 + description: this field configures threshold of histogram bin 13 and bin 14 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HIST_SEG_12_13 + description: this field configures threshold of histogram bin 12 and bin 13 + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: HIST_WEIGHT0 + description: histogram sub-window weight register 0 + addressOffset: 452 + size: 32 + resetValue: 16843009 + fields: + - name: HIST_WEIGHT_03 + description: this field configures weight of subwindow 03 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HIST_WEIGHT_02 + description: this field configures weight of subwindow 02 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HIST_WEIGHT_01 + description: this field configures weight of subwindow 01 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HIST_WEIGHT_00 + description: this field configures weight of subwindow 00 and sum of all weight should be 256 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HIST_WEIGHT1 + description: histogram sub-window weight register 1 + addressOffset: 456 + size: 32 + resetValue: 16843009 + fields: + - name: HIST_WEIGHT_12 + description: this field configures weight of subwindow 12 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HIST_WEIGHT_11 + description: this field configures weight of subwindow 11 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HIST_WEIGHT_10 + description: this field configures weight of subwindow 10 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HIST_WEIGHT_04 + description: this field configures weight of subwindow 04 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HIST_WEIGHT2 + description: histogram sub-window weight register 2 + addressOffset: 460 + size: 32 + resetValue: 16843009 + fields: + - name: HIST_WEIGHT_21 + description: this field configures weight of subwindow 21 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HIST_WEIGHT_20 + description: this field configures weight of subwindow 20 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HIST_WEIGHT_14 + description: this field configures weight of subwindow 04 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HIST_WEIGHT_13 + description: this field configures weight of subwindow 13 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HIST_WEIGHT3 + description: histogram sub-window weight register 3 + addressOffset: 464 + size: 32 + resetValue: 3892379905 + fields: + - name: HIST_WEIGHT_30 + description: this field configures weight of subwindow 30 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HIST_WEIGHT_24 + description: this field configures weight of subwindow 24 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HIST_WEIGHT_23 + description: this field configures weight of subwindow 23 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HIST_WEIGHT_22 + description: this field configures weight of subwindow 22 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HIST_WEIGHT4 + description: histogram sub-window weight register 4 + addressOffset: 468 + size: 32 + resetValue: 16843009 + fields: + - name: HIST_WEIGHT_34 + description: this field configures weight of subwindow 34 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HIST_WEIGHT_33 + description: this field configures weight of subwindow 33 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HIST_WEIGHT_32 + description: this field configures weight of subwindow 32 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HIST_WEIGHT_31 + description: this field configures weight of subwindow 31 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HIST_WEIGHT5 + description: histogram sub-window weight register 5 + addressOffset: 472 + size: 32 + resetValue: 16843009 + fields: + - name: HIST_WEIGHT_43 + description: this field configures weight of subwindow 43 + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HIST_WEIGHT_42 + description: this field configures weight of subwindow 42 + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HIST_WEIGHT_41 + description: this field configures weight of subwindow 41 + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HIST_WEIGHT_40 + description: this field configures weight of subwindow 40 + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: HIST_WEIGHT6 + description: histogram sub-window weight register 6 + addressOffset: 476 + size: 32 + resetValue: 1 + fields: + - name: HIST_WEIGHT_44 + description: this field configures weight of subwindow 44 + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: HIST_BIN0 + description: result of histogram bin 0 + addressOffset: 480 + size: 32 + fields: + - name: HIST_BIN_0 + description: this field represents result of histogram bin 0 + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: HIST_BIN1 + description: result of histogram bin 1 + addressOffset: 484 + size: 32 + fields: + - name: HIST_BIN_1 + description: this field represents result of histogram bin 1 + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: HIST_BIN2 + description: result of histogram bin 2 + addressOffset: 488 + size: 32 + fields: + - name: HIST_BIN_2 + description: this field represents result of histogram bin 2 + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: HIST_BIN3 + description: result of histogram bin 3 + addressOffset: 492 + size: 32 + fields: + - name: HIST_BIN_3 + description: this field represents result of histogram bin 3 + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: HIST_BIN4 + description: result of histogram bin 4 + addressOffset: 496 + size: 32 + fields: + - name: HIST_BIN_4 + description: this field represents result of histogram bin 4 + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: HIST_BIN5 + description: result of histogram bin 5 + addressOffset: 500 + size: 32 + fields: + - name: HIST_BIN_5 + description: this field represents result of histogram bin 5 + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: HIST_BIN6 + description: result of histogram bin 6 + addressOffset: 504 + size: 32 + fields: + - name: HIST_BIN_6 + description: this field represents result of histogram bin 6 + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: HIST_BIN7 + description: result of histogram bin 7 + addressOffset: 508 + size: 32 + fields: + - name: HIST_BIN_7 + description: this field represents result of histogram bin 7 + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: HIST_BIN8 + description: result of histogram bin 8 + addressOffset: 512 + size: 32 + fields: + - name: HIST_BIN_8 + description: this field represents result of histogram bin 8 + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: HIST_BIN9 + description: result of histogram bin 9 + addressOffset: 516 + size: 32 + fields: + - name: HIST_BIN_9 + description: this field represents result of histogram bin 9 + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: HIST_BIN10 + description: result of histogram bin 10 + addressOffset: 520 + size: 32 + fields: + - name: HIST_BIN_10 + description: this field represents result of histogram bin 10 + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: HIST_BIN11 + description: result of histogram bin 11 + addressOffset: 524 + size: 32 + fields: + - name: HIST_BIN_11 + description: this field represents result of histogram bin 11 + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: HIST_BIN12 + description: result of histogram bin 12 + addressOffset: 528 + size: 32 + fields: + - name: HIST_BIN_12 + description: this field represents result of histogram bin 12 + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: HIST_BIN13 + description: result of histogram bin 13 + addressOffset: 532 + size: 32 + fields: + - name: HIST_BIN_13 + description: this field represents result of histogram bin 13 + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: HIST_BIN14 + description: result of histogram bin 14 + addressOffset: 536 + size: 32 + fields: + - name: HIST_BIN_14 + description: this field represents result of histogram bin 14 + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: HIST_BIN15 + description: result of histogram bin 15 + addressOffset: 540 + size: 32 + fields: + - name: HIST_BIN_15 + description: this field represents result of histogram bin 15 + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: MEM_AUX_CTRL_0 + description: mem aux control register 0 + addressOffset: 544 + size: 32 + resetValue: 320869152 + fields: + - name: HEADER_MEM_AUX_CTRL + description: this field configures the mem_aux of isp input buffer memory + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: DPC_LUT_MEM_AUX_CTRL + description: this field represents this field configures the mem_aux of dpc lut memory + bitOffset: 16 + bitWidth: 14 + access: read-write + - register: + name: MEM_AUX_CTRL_1 + description: mem aux control register 1 + addressOffset: 548 + size: 32 + resetValue: 320869152 + fields: + - name: LSC_LUT_R_GR_MEM_AUX_CTRL + description: this field configures the mem_aux of lsc r gr lut memory + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: LSC_LUT_GB_B_MEM_AUX_CTRL + description: this field configures the mem_aux of lsc gb b lut memory + bitOffset: 16 + bitWidth: 14 + access: read-write + - register: + name: MEM_AUX_CTRL_2 + description: mem aux control register 2 + addressOffset: 552 + size: 32 + resetValue: 320869152 + fields: + - name: BF_MATRIX_MEM_AUX_CTRL + description: this field configures the mem_aux of bf line buffer memory + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: DPC_MATRIX_MEM_AUX_CTRL + description: this field configures the mem_aux of dpc line buffer memory + bitOffset: 16 + bitWidth: 14 + access: read-write + - register: + name: MEM_AUX_CTRL_3 + description: mem aux control register 3 + addressOffset: 556 + size: 32 + resetValue: 320869152 + fields: + - name: SHARP_MATRIX_Y_MEM_AUX_CTRL + description: this field configures the mem_aux of sharp y line buffer memory + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: DEMOSAIC_MATRIX_MEM_AUX_CTRL + description: this field configures the mem_aux of demosaic line buffer memory + bitOffset: 16 + bitWidth: 14 + access: read-write + - register: + name: MEM_AUX_CTRL_4 + description: mem aux control register 4 + addressOffset: 560 + size: 32 + resetValue: 4896 + fields: + - name: SHARP_MATRIX_UV_MEM_AUX_CTRL + description: this field configures the mem_aux of sharp uv line buffer memory + bitOffset: 0 + bitWidth: 14 + access: read-write + - register: + name: YUV_FORMAT + description: yuv format control register + addressOffset: 564 + size: 32 + fields: + - name: YUV_MODE + description: "this bit configures the yuv mode. 0: ITU-R BT.601, 1: ITU-R BT.709" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: YUV_RANGE + description: "this bit configures the yuv range. 0: full range, 1: limit range" + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: RDN_ECO_CS + description: rdn eco cs register + addressOffset: 568 + size: 32 + fields: + - name: RDN_ECO_EN + description: rdn_eco_en + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RDN_ECO_RESULT + description: rdn_eco_result + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: RDN_ECO_LOW + description: rdn eco all low register + addressOffset: 572 + size: 32 + fields: + - name: RDN_ECO_LOW + description: rdn_eco_low + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RDN_ECO_HIGH + description: rdn eco all high register + addressOffset: 576 + size: 32 + resetValue: 4294967295 + fields: + - name: RDN_ECO_HIGH + description: rdn_eco_high + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: JPEG + description: JPEG Codec + groupName: JPEG + baseAddress: 1342726144 + addressBlock: + - offset: 0 + size: 176 + usage: registers + interrupt: + - name: JPEG + value: 95 + registers: + - register: + name: CONFIG + description: Control and configuration registers + addressOffset: 0 + size: 32 + resetValue: 4229464 + fields: + - name: FSM_RST + description: fsm reset + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: JPEG_START + description: start to compress a new pic(in dma reg mode) + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: QNR_PRESITION + description: "0:8bit qnr,1:12bit qnr(TBD)" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FF_CHECK_EN + description: "enable whether to add \"00\" after \"ff\"" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SAMPLE_SEL + description: "0:yuv444,1:yuv422, 2:yuv420" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_LINKLIST_MODE + description: "1:use linklist to configure dma" + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: DEBUG_DIRECT_OUT_EN + description: "0:normal mode,1:debug mode for direct output from input" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: GRAY_SEL + description: "0:use non-fifo way to access qnr ram,1:use fifo way to access qnr ram" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: LQNR_TBL_SEL + description: choose luminance quntization table id(TBD) + bitOffset: 9 + bitWidth: 2 + access: read-write + - name: CQNR_TBL_SEL + description: choose chrominance quntization table id (TBD) + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: COLOR_SPACE + description: "configure picture's color space:0-rb888,1-yuv422,2-rgb565, 3-gray" + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: DHT_FIFO_EN + description: "0:use non-fifo way to write dht len_total/codemin/value table,1:use fifo way to write dht len_total/codemin/value table. Reading dht len_total/codemin/value table only has nonfifo way" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: MEM_CLK_FORCE_ON + description: "force memory's clock enabled" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: JFIF_VER + description: "decode pause period to trigger decode_timeout int, the timeout periods =2 power (reg_decode_timeout_thres) -1" + bitOffset: 17 + bitWidth: 6 + access: read-write + - name: DECODE_TIMEOUT_TASK_SEL + description: "0: software use reset to abort decode process ,1: decoder abort decode process by itself" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SOFT_RST + description: "when set to 1, soft reset JPEG module except jpeg_reg module" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: FIFO_RST + description: fifo reset + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PIXEL_REV + description: reverse the source color pixel + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TAILER_EN + description: "set this bit to add EOI of \"0xffd9\" at the end of bitstream" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: PAUSE_EN + description: set this bit to pause jpeg encoding + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PD + description: "0: no operation,1:force jpeg memory to power down" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PU + description: "0: no operation,1:force jpeg memory to power up" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: MODE + description: "0:encoder mode, 1: decoder mode" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DQT_INFO + description: Control and configuration registers + addressOffset: 4 + size: 32 + resetValue: 50462976 + fields: + - name: T0_DQT_INFO + description: "Configure dqt table0's quantization coefficient precision in bit[7:4], configure dqt table0's table id in bit[3:0]" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: T1_DQT_INFO + description: "Configure dqt table1's quantization coefficient precision in bit[7:4], configure dqt table1's table id in bit[3:0]" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: T2_DQT_INFO + description: "Configure dqt table2's quantization coefficient precision in bit[7:4], configure dqt table2's table id in bit[3:0]" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: T3_DQT_INFO + description: "Configure dqt table3's quantization coefficient precision in bit[7:4], configure dqt table3's table id in bit[3:0]" + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: PIC_SIZE + description: Control and configuration registers + addressOffset: 8 + size: 32 + resetValue: 41943520 + fields: + - name: VA + description: "configure picture's height. when encode, the max configurable bits is 14, when decode, the max configurable bits is 16" + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: HA + description: "configure picture's width. when encode, the max configurable bits is 14, when decode, the max configurable bits is 16" + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: T0QNR + description: Control and configuration registers + addressOffset: 16 + size: 32 + fields: + - name: T0_QNR_VAL + description: write this reg to configure 64 quantization coefficient in t0 table + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: T1QNR + description: Control and configuration registers + addressOffset: 20 + size: 32 + fields: + - name: CHROMINANCE_QNR_VAL + description: write this reg to configure 64 quantization coefficient in t1 table + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: T2QNR + description: Control and configuration registers + addressOffset: 24 + size: 32 + fields: + - name: T2_QNR_VAL + description: write this reg to configure 64 quantization coefficient in t2 table + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: T3QNR + description: Control and configuration registers + addressOffset: 28 + size: 32 + fields: + - name: T3_QNR_VAL + description: write this reg to configure 64 quantization coefficient in t3 table + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DECODE_CONF + description: Control and configuration registers + addressOffset: 32 + size: 32 + resetValue: 1594032128 + fields: + - name: RESTART_INTERVAL + description: configure restart interval in DRI marker when decode + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: COMPONENT_NUM + description: configure number of components in frame when decode + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SW_DHT_EN + description: software decode dht table enable + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: SOS_CHECK_BYTE_NUM + description: Configure the byte number to check next sos marker in the multi-scan picture after one scan is decoded down. The real check number is reg_sos_check_byte_num+1 + bitOffset: 25 + bitWidth: 2 + access: read-write + - name: RST_CHECK_BYTE_NUM + description: Configure the byte number to check next rst marker after one rst interval is decoded down. The real check number is reg_rst_check_byte_num+1 + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: MULTI_SCAN_ERR_CHECK + description: reserved for decoder + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: DEZIGZAG_READY_CTL + description: reserved for decoder + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: C0 + description: Control and configuration registers + addressOffset: 36 + size: 32 + resetValue: 4352 + fields: + - name: DQT_TBL_SEL + description: choose c0 quntization table id (TBD) + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: Y_FACTOR + description: vertical sampling factor of c0 + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: X_FACTOR + description: horizontal sampling factor of c0 + bitOffset: 12 + bitWidth: 4 + access: read-write + - name: ID + description: the identifier of c0 + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: C1 + description: Control and configuration registers + addressOffset: 40 + size: 32 + resetValue: 4352 + fields: + - name: DQT_TBL_SEL + description: choose c1 quntization table id (TBD) + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: Y_FACTOR + description: vertical sampling factor of c1 + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: X_FACTOR + description: horizontal sampling factor of c1 + bitOffset: 12 + bitWidth: 4 + access: read-write + - name: ID + description: the identifier of c1 + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: C2 + description: Control and configuration registers + addressOffset: 44 + size: 32 + resetValue: 4352 + fields: + - name: DQT_TBL_SEL + description: choose c2 quntization table id (TBD) + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: Y_FACTOR + description: vertical sampling factor of c2 + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: X_FACTOR + description: horizontal sampling factor of c2 + bitOffset: 12 + bitWidth: 4 + access: read-write + - name: ID + description: the identifier of c2 + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: C3 + description: Control and configuration registers + addressOffset: 48 + size: 32 + resetValue: 4352 + fields: + - name: DQT_TBL_SEL + description: choose c3 quntization table id (TBD) + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: Y_FACTOR + description: vertical sampling factor of c3 + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: X_FACTOR + description: horizontal sampling factor of c3 + bitOffset: 12 + bitWidth: 4 + access: read-write + - name: ID + description: the identifier of c3 + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: DHT_INFO + description: Control and configuration registers + addressOffset: 52 + size: 32 + resetValue: 4112 + fields: + - name: DC0_DHT_ID + description: configure dht dc table 0 id + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: DC1_DHT_ID + description: configure dht dc table 1 id + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: AC0_DHT_ID + description: configure dht ac table 0 id + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: AC1_DHT_ID + description: configure dht ac table 1 id + bitOffset: 12 + bitWidth: 4 + access: read-write + - register: + name: INT_RAW + description: Interrupt raw registers + addressOffset: 56 + size: 32 + fields: + - name: DONE_INT_RAW + description: This raw interrupt bit turns to high level when JPEG finishes encoding a picture.. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RLE_PARALLEL_ERR_INT_RAW + description: The raw interrupt bit to sign that rle parallel error when decoding. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CID_ERR_INT_RAW + description: The raw interrupt bit to sign that scan id check with component fails when decoding. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: C_DHT_DC_ID_ERR_INT_RAW + description: "The raw interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: C_DHT_AC_ID_ERR_INT_RAW + description: "The raw interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: C_DQT_ID_ERR_INT_RAW + description: "The raw interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RST_UXP_ERR_INT_RAW + description: The raw interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RST_CHECK_NONE_ERR_INT_RAW + description: The raw interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RST_CHECK_POS_ERR_INT_RAW + description: The raw interrupt bit to sign that RST header marker position mismatches with restart interval when decoding. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: OUT_EOF_INT_RAW + description: The raw interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SR_COLOR_MODE_ERR_INT_RAW + description: The raw interrupt bit to sign that the selected source color mode is not supported. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DCT_DONE_INT_RAW + description: The raw interrupt bit to sign that one dct calculation is finished. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: BS_LAST_BLOCK_EOF_INT_RAW + description: The raw interrupt bit to sign that the coding process for last block is finished. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SCAN_CHECK_NONE_ERR_INT_RAW + description: The raw interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SCAN_CHECK_POS_ERR_INT_RAW + description: The raw interrupt bit to sign that SOS header marker position wrong when decoding. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: UXP_DET_INT_RAW + description: The raw interrupt bit to sign that unsupported header marker is detected when decoding. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: EN_FRAME_EOF_ERR_INT_RAW + description: The raw interrupt bit to sign that received pixel blocks are smaller than expected when encoding. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: EN_FRAME_EOF_LACK_INT_RAW + description: The raw interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: DE_FRAME_EOF_ERR_INT_RAW + description: The raw interrupt bit to sign that decoded blocks are smaller than expected when decoding. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: DE_FRAME_EOF_LACK_INT_RAW + description: The raw interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SOS_UNMATCH_ERR_INT_RAW + description: "The raw interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: MARKER_ERR_FST_SCAN_INT_RAW + description: The raw interrupt bit to sign that the first scan has header marker error when decoding. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: MARKER_ERR_OTHER_SCAN_INT_RAW + description: The raw interrupt bit to sign that the following scans but not the first scan have header marker error when decoding. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: UNDET_INT_RAW + description: The raw interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: DECODE_TIMEOUT_INT_RAW + description: The raw interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding. + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: INT_ENA + description: Interrupt enable registers + addressOffset: 60 + size: 32 + fields: + - name: DONE_INT_ENA + description: This enable interrupt bit turns to high level when JPEG finishes encoding a picture.. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RLE_PARALLEL_ERR_INT_ENA + description: The enable interrupt bit to sign that rle parallel error when decoding. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CID_ERR_INT_ENA + description: The enable interrupt bit to sign that scan id check with component fails when decoding. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: C_DHT_DC_ID_ERR_INT_ENA + description: "The enable interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: C_DHT_AC_ID_ERR_INT_ENA + description: "The enable interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: C_DQT_ID_ERR_INT_ENA + description: "The enable interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RST_UXP_ERR_INT_ENA + description: The enable interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RST_CHECK_NONE_ERR_INT_ENA + description: The enable interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RST_CHECK_POS_ERR_INT_ENA + description: The enable interrupt bit to sign that RST header marker position mismatches with restart interval when decoding. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: OUT_EOF_INT_ENA + description: The enable interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SR_COLOR_MODE_ERR_INT_ENA + description: The enable interrupt bit to sign that the selected source color mode is not supported. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DCT_DONE_INT_ENA + description: The enable interrupt bit to sign that one dct calculation is finished. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: BS_LAST_BLOCK_EOF_INT_ENA + description: The enable interrupt bit to sign that the coding process for last block is finished. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SCAN_CHECK_NONE_ERR_INT_ENA + description: The enable interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SCAN_CHECK_POS_ERR_INT_ENA + description: The enable interrupt bit to sign that SOS header marker position wrong when decoding. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: UXP_DET_INT_ENA + description: The enable interrupt bit to sign that unsupported header marker is detected when decoding. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: EN_FRAME_EOF_ERR_INT_ENA + description: The enable interrupt bit to sign that received pixel blocks are smaller than expected when encoding. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: EN_FRAME_EOF_LACK_INT_ENA + description: The enable interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: DE_FRAME_EOF_ERR_INT_ENA + description: The enable interrupt bit to sign that decoded blocks are smaller than expected when decoding. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: DE_FRAME_EOF_LACK_INT_ENA + description: The enable interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SOS_UNMATCH_ERR_INT_ENA + description: "The enable interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: MARKER_ERR_FST_SCAN_INT_ENA + description: The enable interrupt bit to sign that the first scan has header marker error when decoding. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: MARKER_ERR_OTHER_SCAN_INT_ENA + description: The enable interrupt bit to sign that the following scans but not the first scan have header marker error when decoding. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: UNDET_INT_ENA + description: The enable interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: DECODE_TIMEOUT_INT_ENA + description: The enable interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding. + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Interrupt status registers + addressOffset: 64 + size: 32 + fields: + - name: DONE_INT_ST + description: This status interrupt bit turns to high level when JPEG finishes encoding a picture.. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RLE_PARALLEL_ERR_INT_ST + description: The status interrupt bit to sign that rle parallel error when decoding. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CID_ERR_INT_ST + description: The status interrupt bit to sign that scan id check with component fails when decoding. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: C_DHT_DC_ID_ERR_INT_ST + description: "The status interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: C_DHT_AC_ID_ERR_INT_ST + description: "The status interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: C_DQT_ID_ERR_INT_ST + description: "The status interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: RST_UXP_ERR_INT_ST + description: The status interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: RST_CHECK_NONE_ERR_INT_ST + description: The status interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: RST_CHECK_POS_ERR_INT_ST + description: The status interrupt bit to sign that RST header marker position mismatches with restart interval when decoding. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: OUT_EOF_INT_ST + description: The status interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SR_COLOR_MODE_ERR_INT_ST + description: The status interrupt bit to sign that the selected source color mode is not supported. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: DCT_DONE_INT_ST + description: The status interrupt bit to sign that one dct calculation is finished. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: BS_LAST_BLOCK_EOF_INT_ST + description: The status interrupt bit to sign that the coding process for last block is finished. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SCAN_CHECK_NONE_ERR_INT_ST + description: The status interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SCAN_CHECK_POS_ERR_INT_ST + description: The status interrupt bit to sign that SOS header marker position wrong when decoding. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: UXP_DET_INT_ST + description: The status interrupt bit to sign that unsupported header marker is detected when decoding. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: EN_FRAME_EOF_ERR_INT_ST + description: The status interrupt bit to sign that received pixel blocks are smaller than expected when encoding. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: EN_FRAME_EOF_LACK_INT_ST + description: The status interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: DE_FRAME_EOF_ERR_INT_ST + description: The status interrupt bit to sign that decoded blocks are smaller than expected when decoding. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: DE_FRAME_EOF_LACK_INT_ST + description: The status interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: SOS_UNMATCH_ERR_INT_ST + description: "The status interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding." + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: MARKER_ERR_FST_SCAN_INT_ST + description: The status interrupt bit to sign that the first scan has header marker error when decoding. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: MARKER_ERR_OTHER_SCAN_INT_ST + description: The status interrupt bit to sign that the following scans but not the first scan have header marker error when decoding. + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: UNDET_INT_ST + description: The status interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding. + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: DECODE_TIMEOUT_INT_ST + description: The status interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding. + bitOffset: 24 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: Interrupt clear registers + addressOffset: 68 + size: 32 + fields: + - name: DONE_INT_CLR + description: This clear interrupt bit turns to high level when JPEG finishes encoding a picture.. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: RLE_PARALLEL_ERR_INT_CLR + description: The clear interrupt bit to sign that rle parallel error when decoding. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CID_ERR_INT_CLR + description: The clear interrupt bit to sign that scan id check with component fails when decoding. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: C_DHT_DC_ID_ERR_INT_CLR + description: "The clear interrupt bit to sign that scan component's dc dht id check with dc dht table's id fails when decoding." + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: C_DHT_AC_ID_ERR_INT_CLR + description: "The clear interrupt bit to sign that scan component's ac dht id check with ac dht table's id fails when decoding." + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: C_DQT_ID_ERR_INT_CLR + description: "The clear interrupt bit to sign that scan component's dqt id check with dqt table's id fails when decoding." + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: RST_UXP_ERR_INT_CLR + description: The clear interrupt bit to sign that RST header marker is detected but restart interval is 0 when decoding. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: RST_CHECK_NONE_ERR_INT_CLR + description: The clear interrupt bit to sign that RST header marker is not detected but restart interval is not 0 when decoding. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: RST_CHECK_POS_ERR_INT_CLR + description: The clear interrupt bit to sign that RST header marker position mismatches with restart interval when decoding. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: OUT_EOF_INT_CLR + description: The clear interrupt bit turns to high level when the last pixel of one square has been transmitted for Tx channel. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SR_COLOR_MODE_ERR_INT_CLR + description: The clear interrupt bit to sign that the selected source color mode is not supported. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: DCT_DONE_INT_CLR + description: The clear interrupt bit to sign that one dct calculation is finished. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: BS_LAST_BLOCK_EOF_INT_CLR + description: The clear interrupt bit to sign that the coding process for last block is finished. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: SCAN_CHECK_NONE_ERR_INT_CLR + description: The clear interrupt bit to sign that SOS header marker is not detected but there are still components left to be decoded. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SCAN_CHECK_POS_ERR_INT_CLR + description: The clear interrupt bit to sign that SOS header marker position wrong when decoding. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: UXP_DET_INT_CLR + description: The clear interrupt bit to sign that unsupported header marker is detected when decoding. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: EN_FRAME_EOF_ERR_INT_CLR + description: The clear interrupt bit to sign that received pixel blocks are smaller than expected when encoding. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: EN_FRAME_EOF_LACK_INT_CLR + description: The clear interrupt bit to sign that the frame eof sign bit from dma input is missing when encoding. But the number of pixel blocks is enough. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: DE_FRAME_EOF_ERR_INT_CLR + description: The clear interrupt bit to sign that decoded blocks are smaller than expected when decoding. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: DE_FRAME_EOF_LACK_INT_CLR + description: The clear interrupt bit to sign that the either frame eof from dma input or eoi marker is missing when encoding. But the number of decoded blocks is enough. + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: SOS_UNMATCH_ERR_INT_CLR + description: "The clear interrupt bit to sign that the component number of a scan is 0 or does not match the sos marker's length when decoding." + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: MARKER_ERR_FST_SCAN_INT_CLR + description: The clear interrupt bit to sign that the first scan has header marker error when decoding. + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: MARKER_ERR_OTHER_SCAN_INT_CLR + description: The clear interrupt bit to sign that the following scans but not the first scan have header marker error when decoding. + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: UNDET_INT_CLR + description: The clear interrupt bit to sign that JPEG format is not detected at the eof data of a packet when decoding. + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: DECODE_TIMEOUT_INT_CLR + description: The clear interrupt bit to sign that decode pause time is longer than the setting decode timeout time when decoding. + bitOffset: 24 + bitWidth: 1 + access: write-only + - register: + name: STATUS0 + description: Trace and Debug registers + addressOffset: 72 + size: 32 + fields: + - name: BITSTREAM_EOF_VLD_CNT + description: the valid bit count for last bitstream + bitOffset: 11 + bitWidth: 6 + access: read-only + - name: DCTOUT_ZZSCAN_ADDR + description: the zig-zag read addr from dctout_ram + bitOffset: 17 + bitWidth: 6 + access: read-only + - name: QNRVAL_ZZSCAN_ADDR + description: the zig-zag read addr from qnrval_ram + bitOffset: 23 + bitWidth: 6 + access: read-only + - name: REG_STATE_YUV + description: the state of jpeg fsm + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: STATUS2 + description: Trace and Debug registers + addressOffset: 76 + size: 32 + resetValue: 134217728 + fields: + - name: SOURCE_PIXEL + description: source pixels fetched from dma + bitOffset: 0 + bitWidth: 24 + access: read-only + - name: LAST_BLOCK + description: indicate the encoding process for the last mcu of the picture + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: LAST_MCU + description: indicate the encoding process for the last block of the picture + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: LAST_DC + description: indicate the encoding process is at the header of the last block of the picture + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: PACKFIFO_READY + description: "the jpeg pack_fifo ready signal, high active" + bitOffset: 27 + bitWidth: 1 + access: read-only + - register: + name: STATUS3 + description: Trace and Debug registers + addressOffset: 80 + size: 32 + fields: + - name: YO + description: component y transferred from rgb input + bitOffset: 0 + bitWidth: 9 + access: read-only + - name: Y_READY + description: "component y valid signal, high active" + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: CBO + description: component cb transferred from rgb input + bitOffset: 10 + bitWidth: 9 + access: read-only + - name: CB_READY + description: "component cb valid signal, high active" + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: CRO + description: component cr transferred from rgb input + bitOffset: 20 + bitWidth: 9 + access: read-only + - name: CR_READY + description: "component cr valid signal, high active" + bitOffset: 29 + bitWidth: 1 + access: read-only + - register: + name: STATUS4 + description: Trace and Debug registers + addressOffset: 84 + size: 32 + fields: + - name: HFM_BITSTREAM + description: the hufman bitstream during encoding process + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DHT_TOTLEN_DC0 + description: Trace and Debug registers + addressOffset: 88 + size: 32 + fields: + - name: DHT_TOTLEN_DC0 + description: write the numbers of 1~n codeword length sum from 1~16 of dc0 table + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DHT_VAl_DC0 + description: Trace and Debug registers + addressOffset: 92 + size: 32 + fields: + - name: DHT_VAL_DC0 + description: write codeword corresponding huffman values of dc0 table + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DHT_TOTLEN_AC0 + description: Trace and Debug registers + addressOffset: 96 + size: 32 + fields: + - name: DHT_TOTLEN_AC0 + description: write the numbers of 1~n codeword length sum from 1~16 of ac0 table + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DHT_VAl_AC0 + description: Trace and Debug registers + addressOffset: 100 + size: 32 + fields: + - name: DHT_VAL_AC0 + description: write codeword corresponding huffman values of ac0 table + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DHT_TOTLEN_DC1 + description: Trace and Debug registers + addressOffset: 104 + size: 32 + fields: + - name: DHT_TOTLEN_DC1 + description: write the numbers of 1~n codeword length sum from 1~16 of dc1 table + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DHT_VAl_DC1 + description: Trace and Debug registers + addressOffset: 108 + size: 32 + fields: + - name: DHT_VAL_DC1 + description: write codeword corresponding huffman values of dc1 table + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DHT_TOTLEN_AC1 + description: Trace and Debug registers + addressOffset: 112 + size: 32 + fields: + - name: DHT_TOTLEN_AC1 + description: write the numbers of 1~n codeword length sum from 1~16 of ac1 table + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DHT_VAl_AC1 + description: Trace and Debug registers + addressOffset: 116 + size: 32 + fields: + - name: DHT_VAL_AC1 + description: write codeword corresponding huffman values of ac1 table + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DHT_CODEMIN_DC0 + description: Trace and Debug registers + addressOffset: 120 + size: 32 + fields: + - name: DHT_CODEMIN_DC0 + description: write the minimum codeword of code length from 1~16 of dc0 table. The codeword is left shifted to the MSB position of a 16bit word + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DHT_CODEMIN_AC0 + description: Trace and Debug registers + addressOffset: 124 + size: 32 + fields: + - name: DHT_CODEMIN_AC0 + description: write the minimum codeword of code length from 1~16 of ac0 table. The codeword is left shifted to the MSB position of a 16bit word + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DHT_CODEMIN_DC1 + description: Trace and Debug registers + addressOffset: 128 + size: 32 + fields: + - name: DHT_CODEMIN_DC1 + description: write the minimum codeword of code length from 1~16 of dc1 table. The codeword is left shifted to the MSB position of a 16bit word + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DHT_CODEMIN_AC1 + description: Trace and Debug registers + addressOffset: 132 + size: 32 + fields: + - name: DHT_CODEMIN_AC1 + description: write the minimum codeword of code length from 1~16 of ac1 table. The codeword is left shifted to the MSB position of a 16bit word + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DECODER_STATUS0 + description: Trace and Debug registers + addressOffset: 136 + size: 32 + fields: + - name: DECODE_BYTE_CNT + description: Reserved + bitOffset: 0 + bitWidth: 26 + access: read-only + - name: HEADER_DEC_ST + description: Reserved + bitOffset: 26 + bitWidth: 4 + access: read-only + - name: DECODE_SAMPLE_SEL + description: Reserved + bitOffset: 30 + bitWidth: 2 + access: read-only + - register: + name: DECODER_STATUS1 + description: Trace and Debug registers + addressOffset: 140 + size: 32 + fields: + - name: ENCODE_DATA + description: Reserved + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: COUNT_Q + description: Reserved + bitOffset: 16 + bitWidth: 7 + access: read-only + - name: MCU_FSM_READY + description: Reserved + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: DECODE_DATA + description: Reserved + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: DECODER_STATUS2 + description: Trace and Debug registers + addressOffset: 144 + size: 32 + fields: + - name: COMP_BLOCK_NUM + description: Reserved + bitOffset: 0 + bitWidth: 26 + access: read-only + - name: SCAN_NUM + description: Reserved + bitOffset: 26 + bitWidth: 3 + access: read-only + - name: RST_CHECK_WAIT + description: Reserved + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: SCAN_CHECK_WAIT + description: Reserved + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: MCU_IN_PROC + description: Reserved + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: DECODER_STATUS3 + description: Trace and Debug registers + addressOffset: 148 + size: 32 + fields: + - name: LOOKUP_DATA + description: Reserved + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DECODER_STATUS4 + description: Trace and Debug registers + addressOffset: 152 + size: 32 + fields: + - name: BLOCK_EOF_CNT + description: Reserved + bitOffset: 0 + bitWidth: 26 + access: read-only + - name: DEZIGZAG_READY + description: Reserved + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: DE_FRAME_EOF_CHECK + description: Reserved + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: DE_DMA2D_IN_PUSH + description: Reserved + bitOffset: 28 + bitWidth: 1 + access: read-only + - register: + name: DECODER_STATUS5 + description: Trace and Debug registers + addressOffset: 156 + size: 32 + fields: + - name: IDCT_HFM_DATA + description: Reserved + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: NS0 + description: Reserved + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: NS1 + description: Reserved + bitOffset: 19 + bitWidth: 3 + access: read-only + - name: NS2 + description: Reserved + bitOffset: 22 + bitWidth: 3 + access: read-only + - name: NS3 + description: Reserved + bitOffset: 25 + bitWidth: 3 + access: read-only + - name: DATA_LAST_O + description: Reserved + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: RDN_RESULT + description: redundant registers for jpeg + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: RDN_ENA + description: redundant control registers for jpeg + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: STATUS5 + description: Trace and Debug registers + addressOffset: 160 + size: 32 + fields: + - name: PIC_BLOCK_NUM + description: Reserved + bitOffset: 0 + bitWidth: 24 + access: read-only + - register: + name: ECO_LOW + description: Trace and Debug registers + addressOffset: 164 + size: 32 + fields: + - name: RDN_ECO_LOW + description: redundant registers for jpeg + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ECO_HIGH + description: Trace and Debug registers + addressOffset: 168 + size: 32 + resetValue: 4294967295 + fields: + - name: RDN_ECO_HIGH + description: redundant registers for jpeg + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SYS + description: Trace and Debug registers + addressOffset: 248 + size: 32 + fields: + - name: CLK_EN + description: Reserved + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: VERSION + description: Trace and Debug registers + addressOffset: 252 + size: 32 + resetValue: 34673040 + fields: + - name: JPEG_VER + description: Reserved + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: LCD_CAM + description: Camera/LCD Controller + groupName: LCDCAM + baseAddress: 1343078400 + addressBlock: + - offset: 0 + size: 76 + usage: registers + registers: + - register: + name: LCD_CLOCK + description: LCD clock config register. + addressOffset: 0 + size: 32 + resetValue: 2115 + fields: + - name: LCD_CLKCNT_N + description: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: LCD_CLK_EQU_SYSCLK + description: "1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1)." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: LCD_CK_IDLE_EDGE + description: "1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: LCD_CK_OUT_EDGE + description: "1: LCD_PCLK line is high in the first half data cycle. 0: LCD_PCLK line is low in the second half data cycle." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: LCD_CLKM_DIV_NUM + description: Integral LCD clock divider value + bitOffset: 9 + bitWidth: 8 + access: read-write + - name: LCD_CLKM_DIV_B + description: Fractional clock divider numerator value + bitOffset: 17 + bitWidth: 6 + access: read-write + - name: LCD_CLKM_DIV_A + description: Fractional clock divider denominator value + bitOffset: 23 + bitWidth: 6 + access: read-write + - name: LCD_CLK_SEL + description: "Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock." + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: CLK_EN + description: Set this bit to enable clk gate + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CAM_CTRL + description: CAM config register. + addressOffset: 4 + size: 32 + resetValue: 2048 + fields: + - name: CAM_STOP_EN + description: "Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CAM_VSYNC_FILTER_THRES + description: Filter threshold value for CAM_VSYNC signal. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: CAM_UPDATE + description: "1: Update Camera registers, will be cleared by hardware. 0 : Not care." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CAM_BYTE_ORDER + description: "1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CAM_BIT_ORDER + description: "1: invert data byte order, only valid in 2 byte mode. 0: Not change." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CAM_LINE_INT_EN + description: "1: Enable to generate CAM_HS_INT. 0: Disable." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CAM_VS_EOF_EN + description: "1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CAM_CLKM_DIV_NUM + description: Integral Camera clock divider value + bitOffset: 9 + bitWidth: 8 + access: read-write + - name: CAM_CLKM_DIV_B + description: Fractional clock divider numerator value + bitOffset: 17 + bitWidth: 6 + access: read-write + - name: CAM_CLKM_DIV_A + description: Fractional clock divider denominator value + bitOffset: 23 + bitWidth: 6 + access: read-write + - name: CAM_CLK_SEL + description: "Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock." + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: CAM_CTRL1 + description: CAM config register. + addressOffset: 8 + size: 32 + fields: + - name: CAM_REC_DATA_BYTELEN + description: Camera receive data byte length minus 1 to set DMA in_suc_eof_int. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CAM_LINE_INT_NUM + description: The line number minus 1 to generate cam_hs_int. + bitOffset: 16 + bitWidth: 6 + access: read-write + - name: CAM_CLK_INV + description: "1: Invert the input signal CAM_PCLK. 0: Not invert." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: CAM_VSYNC_FILTER_EN + description: "1: Enable CAM_VSYNC filter function. 0: bypass." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: CAM_2BYTE_EN + description: "1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: CAM_DE_INV + description: "CAM_DE invert enable signal, valid in high level." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: CAM_HSYNC_INV + description: "CAM_HSYNC invert enable signal, valid in high level." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CAM_VSYNC_INV + description: "CAM_VSYNC invert enable signal, valid in high level." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: CAM_VH_DE_MODE_EN + description: "1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control signals are CAM_DE and CAM_VSYNC." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CAM_START + description: Camera module start signal. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CAM_RESET + description: Camera module reset signal. + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: CAM_AFIFO_RESET + description: Camera AFIFO reset signal. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: CAM_RGB_YUV + description: CAM YUV/RGB converter configuration register. + addressOffset: 12 + size: 32 + resetValue: 12582912 + fields: + - name: CAM_CONV_8BITS_DATA_INV + description: "1:invert every two 8bits input data. 2. disabled." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CAM_CONV_YUV2YUV_MODE + description: "0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1." + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CAM_CONV_YUV_MODE + description: "0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in" + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CAM_CONV_PROTOCOL_MODE + description: "0:BT601. 1:BT709." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CAM_CONV_DATA_OUT_MODE + description: "LIMIT or FULL mode of Data out. 0: limit. 1: full" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: CAM_CONV_DATA_IN_MODE + description: "LIMIT or FULL mode of Data in. 0: limit. 1: full" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CAM_CONV_MODE_8BITS_ON + description: "0: 16bits mode. 1: 8bits mode." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CAM_CONV_TRANS_MODE + description: "0: YUV to RGB. 1: RGB to YUV." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CAM_CONV_ENABLE + description: "0: Bypass converter. 1: Enable converter." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LCD_RGB_YUV + description: LCD YUV/RGB converter configuration register. + addressOffset: 16 + size: 32 + resetValue: 12582912 + fields: + - name: LCD_CONV_8BITS_DATA_INV + description: "1:invert every two 8bits input data. 2. disabled." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: LCD_CONV_TXTORX + description: "0: txtorx mode off. 1: txtorx mode on." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: LCD_CONV_YUV2YUV_MODE + description: "0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode, trans_mode must be set to 1." + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: LCD_CONV_YUV_MODE + description: "0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in" + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: LCD_CONV_PROTOCOL_MODE + description: "0:BT601. 1:BT709." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LCD_CONV_DATA_OUT_MODE + description: "LIMIT or FULL mode of Data out. 0: limit. 1: full" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LCD_CONV_DATA_IN_MODE + description: "LIMIT or FULL mode of Data in. 0: limit. 1: full" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LCD_CONV_MODE_8BITS_ON + description: "0: 16bits mode. 1: 8bits mode." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LCD_CONV_TRANS_MODE + description: "0: YUV to RGB. 1: RGB to YUV." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LCD_CONV_ENABLE + description: "0: Bypass converter. 1: Enable converter." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LCD_USER + description: LCD config register. + addressOffset: 20 + size: 32 + resetValue: 1 + fields: + - name: LCD_DOUT_CYCLELEN + description: The output data cycles minus 1 of LCD module. + bitOffset: 0 + bitWidth: 13 + access: read-write + - name: LCD_ALWAYS_OUT_EN + description: "LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or reg_lcd_reset is set." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: LCD_DOUT_BYTE_SWIZZLE_MODE + description: "0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA" + bitOffset: 14 + bitWidth: 3 + access: read-write + - name: LCD_DOUT_BYTE_SWIZZLE_ENABLE + description: "1: enable byte swizzle 0: disable" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: LCD_DOUT_BIT_ORDER + description: "1: change bit order in every byte. 0: Not change." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: LCD_BYTE_MODE + description: "2: 24bit mode. 1: 16bit mode. 0: 8bit mode" + bitOffset: 19 + bitWidth: 2 + access: read-write + - name: LCD_UPDATE + description: "1: Update LCD registers, will be cleared by hardware. 0 : Not care." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: LCD_BIT_ORDER + description: "1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: LCD_BYTE_ORDER + description: "1: invert data byte order, only valid in 2 byte mode. 0: Not change." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: LCD_DOUT + description: "1: Be able to send data out in LCD sequence when LCD starts. 0: Disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: LCD_DUMMY + description: "1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LCD_CMD + description: "1: Be able to send command in LCD sequence when LCD starts. 0: Disable." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LCD_START + description: "LCD start sending data enable signal, valid in high level." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LCD_RESET + description: The value of command. + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: LCD_DUMMY_CYCLELEN + description: The dummy cycle length minus 1. + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: LCD_CMD_2_CYCLE_EN + description: "The cycle length of command phase. 1: 2 cycles. 0: 1 cycle." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LCD_MISC + description: LCD config register. + addressOffset: 24 + size: 32 + resetValue: 192 + fields: + - name: LCD_WIRE_MODE + description: "The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: LCD_VFK_CYCLELEN + description: The setup cycle length minus 1 in LCD non-RGB mode. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: LCD_VBK_CYCLELEN + description: "The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold time cycle length in LCD non-RGB mode." + bitOffset: 12 + bitWidth: 13 + access: read-write + - name: LCD_NEXT_FRAME_EN + description: "1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LCD_BK_EN + description: "1: Enable blank region when LCD sends data out. 0: No blank region." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LCD_AFIFO_RESET + description: LCD AFIFO reset signal. + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: LCD_CD_DATA_SET + description: "1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = reg_cd_idle_edge." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LCD_CD_DUMMY_SET + description: "1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = reg_cd_idle_edge." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LCD_CD_CMD_SET + description: "1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = reg_cd_idle_edge." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LCD_CD_IDLE_EDGE + description: The default value of LCD_CD. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LCD_CTRL + description: LCD config register. + addressOffset: 28 + size: 32 + fields: + - name: LCD_HB_FRONT + description: It is the horizontal blank front porch of a frame. + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: LCD_VA_HEIGHT + description: It is the vertical active height of a frame. + bitOffset: 11 + bitWidth: 10 + access: read-write + - name: LCD_VT_HEIGHT + description: It is the vertical total height of a frame. + bitOffset: 21 + bitWidth: 10 + access: read-write + - name: LCD_RGB_MODE_EN + description: "1: Enable LCD RGB mode. 0: Disable LCD RGB mode." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LCD_CTRL1 + description: LCD config register. + addressOffset: 32 + size: 32 + fields: + - name: LCD_VB_FRONT + description: It is the vertical blank front porch of a frame. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: LCD_HA_WIDTH + description: It is the horizontal active width of a frame. + bitOffset: 8 + bitWidth: 12 + access: read-write + - name: LCD_HT_WIDTH + description: It is the horizontal total width of a frame. + bitOffset: 20 + bitWidth: 12 + access: read-write + - register: + name: LCD_CTRL2 + description: LCD config register. + addressOffset: 36 + size: 32 + resetValue: 65537 + fields: + - name: LCD_VSYNC_WIDTH + description: It is the position of LCD_VSYNC active pulse in a line. + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: LCD_VSYNC_IDLE_POL + description: It is the idle value of LCD_VSYNC. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: LCD_DE_IDLE_POL + description: It is the idle value of LCD_DE. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: LCD_HS_BLANK_EN + description: "1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: LCD_HSYNC_WIDTH + description: It is the position of LCD_HSYNC active pulse in a line. + bitOffset: 16 + bitWidth: 7 + access: read-write + - name: LCD_HSYNC_IDLE_POL + description: It is the idle value of LCD_HSYNC. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: LCD_HSYNC_POSITION + description: It is the position of LCD_HSYNC active pulse in a line. + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: LCD_FIRST_CMD_VAL + description: LCD config register. + addressOffset: 40 + size: 32 + fields: + - name: LCD_FIRST_CMD_VALUE + description: The LCD write command value of first cmd cycle. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LCD_LATTER_CMD_VAL + description: LCD config register. + addressOffset: 44 + size: 32 + fields: + - name: LCD_LATTER_CMD_VALUE + description: The LCD write command value of latter cmd cycle. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LCD_DLY_MODE_CFG1 + description: LCD config register. + addressOffset: 48 + size: 32 + fields: + - name: DOUT16_MODE + description: "The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DOUT17_MODE + description: "The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DOUT18_MODE + description: "The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DOUT19_MODE + description: "The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DOUT20_MODE + description: "The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: DOUT21_MODE + description: "The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DOUT22_MODE + description: "The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DOUT23_MODE + description: "The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: LCD_CD_MODE + description: "The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: LCD_DE_MODE + description: "The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: LCD_HSYNC_MODE + description: "The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: LCD_VSYNC_MODE + description: "The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: LCD_DLY_MODE_CFG2 + description: LCD config register. + addressOffset: 56 + size: 32 + fields: + - name: DOUT0_MODE + description: "The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DOUT1_MODE + description: "The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DOUT2_MODE + description: "The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DOUT3_MODE + description: "The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DOUT4_MODE + description: "The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: DOUT5_MODE + description: "The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DOUT6_MODE + description: "The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DOUT7_MODE + description: "The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DOUT8_MODE + description: "The output data bit 16 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DOUT9_MODE + description: "The output data bit 18 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DOUT10_MODE + description: "The output data bit 20 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DOUT11_MODE + description: "The output data bit 22 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: DOUT12_MODE + description: "The output data bit 24 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: DOUT13_MODE + description: "The output data bit 26 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: DOUT14_MODE + description: "The output data bit 28 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: DOUT15_MODE + description: "The output data bit 30 is delayed by module clock LCD_CLK. 0: output without delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK." + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: LC_DMA_INT_ENA + description: LCDCAM interrupt enable register. + addressOffset: 100 + size: 32 + fields: + - name: LCD_VSYNC_INT_ENA + description: The enable bit for LCD frame end interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LCD_TRANS_DONE_INT_ENA + description: The enable bit for lcd transfer end interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CAM_VSYNC_INT_ENA + description: The enable bit for Camera frame end interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CAM_HS_INT_ENA + description: The enable bit for Camera line interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: LC_DMA_INT_RAW + description: "LCDCAM interrupt raw register, valid in level." + addressOffset: 104 + size: 32 + fields: + - name: LCD_VSYNC_INT_RAW + description: The raw bit for LCD frame end interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: LCD_TRANS_DONE_INT_RAW + description: The raw bit for lcd transfer end interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CAM_VSYNC_INT_RAW + description: The raw bit for Camera frame end interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CAM_HS_INT_RAW + description: The raw bit for Camera line interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: LC_DMA_INT_ST + description: LCDCAM interrupt status register. + addressOffset: 108 + size: 32 + fields: + - name: LCD_VSYNC_INT_ST + description: The status bit for LCD frame end interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: LCD_TRANS_DONE_INT_ST + description: The status bit for lcd transfer end interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CAM_VSYNC_INT_ST + description: The status bit for Camera frame end interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CAM_HS_INT_ST + description: The status bit for Camera transfer end interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: LC_DMA_INT_CLR + description: LCDCAM interrupt clear register. + addressOffset: 112 + size: 32 + fields: + - name: LCD_VSYNC_INT_CLR + description: The clear bit for LCD frame end interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: LCD_TRANS_DONE_INT_CLR + description: The clear bit for lcd transfer end interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CAM_VSYNC_INT_CLR + description: The clear bit for Camera frame end interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CAM_HS_INT_CLR + description: The clear bit for Camera line interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: LC_REG_DATE + description: Version register + addressOffset: 252 + size: 32 + resetValue: 36712592 + fields: + - name: LC_DATE + description: LCD_CAM version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: LEDC + description: LED Control PWM (Pulse Width Modulation) + groupName: LEDC + baseAddress: 1343041536 + addressBlock: + - offset: 0 + size: 292 + usage: registers + interrupt: + - name: LEDC + value: 52 + registers: + - register: + dim: 8 + dimIncrement: 20 + name: CH%s_CONF0 + description: Configuration register 0 for channel %s + addressOffset: 0 + size: 32 + fields: + - name: TIMER_SEL_CH + description: "Configures which timer is channel %s selected.\\\\0: Select timer0\\\\1: Select timer1\\\\2: Select timer2\\\\3: Select timer3" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SIG_OUT_EN_CH + description: "Configures whether or not to enable signal output on channel %s.\\\\0: Signal output disable\\\\1: Signal output enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IDLE_LV_CH + description: "Configures the output value when channel %s is inactive. Valid only when LEDC_SIG_OUT_EN_CH%s is 0.\\\\0: Output level is low\\\\1: Output level is high" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PARA_UP_CH + description: "Configures whether or not to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware.\\\\0: Invalid. No effect\\\\1: Update" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: OVF_NUM_CH + description: Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times. + bitOffset: 5 + bitWidth: 10 + access: read-write + - name: OVF_CNT_EN_CH + description: "Configures whether or not to enable the ovf_cnt of channel %s.\\\\0: Disable\\\\1: Enable" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: OVF_CNT_RESET_CH + description: "Configures whether or not to reset the ovf_cnt of channel %s.\\\\0: Invalid. No effect\\\\1: Reset the ovf_cnt" + bitOffset: 16 + bitWidth: 1 + access: write-only + - register: + dim: 8 + dimIncrement: 20 + name: CH%s_HPOINT + description: High point register for channel %s + addressOffset: 4 + size: 32 + fields: + - name: HPOINT_CH + description: Configures high point of signal output on channel %s. The output value changes to high when the selected timers has reached the value specified by this register. + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + dim: 8 + dimIncrement: 20 + name: CH%s_DUTY + description: Initial duty cycle register for channel %s + addressOffset: 8 + size: 32 + fields: + - name: DUTY_CH + description: Configures the duty of signal output on channel %s. + bitOffset: 0 + bitWidth: 25 + access: read-write + - register: + dim: 8 + dimIncrement: 20 + name: CH%s_CONF1 + description: Configuration register 1 for channel %s + addressOffset: 12 + size: 32 + fields: + - name: DUTY_START_CH + description: "Configures whether the duty cycle fading configurations take effect.\\\\0: Not take effect\\\\1: Take effect" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + dim: 8 + dimIncrement: 20 + name: CH%s_DUTY_R + description: Current duty cycle register for channel %s + addressOffset: 16 + size: 32 + fields: + - name: DUTY_CH_R + description: Represents the current duty of output signal on channel %s. + bitOffset: 0 + bitWidth: 25 + access: read-only + - register: + dim: 4 + dimIncrement: 8 + name: TIMER%s_CONF + description: Timer %s configuration register + addressOffset: 160 + size: 32 + resetValue: 16777216 + fields: + - name: TIMER_DUTY_RES + description: Configures the range of the counter in timer %s. + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: CLK_DIV_TIMER + description: Configures the divisor for the divider in timer %s.The least significant eight bits represent the fractional part. + bitOffset: 5 + bitWidth: 18 + access: read-write + - name: TIMER_PAUSE + description: "Configures whether or not to pause the counter in timer %s.\\\\0: Normal\\\\1: Pause" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TIMER_RST + description: "Configures whether or not to reset timer %s. The counter will show 0 after reset.\\\\0: Not reset\\\\1: Reset" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TICK_SEL_TIMER + description: Configures which clock is timer %s selected. Unused. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TIMER_PARA_UP + description: "Configures whether or not to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES.\\\\0: Invalid. No effect\\\\1: Update" + bitOffset: 26 + bitWidth: 1 + access: write-only + - register: + dim: 4 + dimIncrement: 8 + name: TIMER%s_VALUE + description: Timer %s current counter value register + addressOffset: 164 + size: 32 + fields: + - name: TIMER_CNT + description: Represents the current counter value of timer %s. + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: INT_RAW + description: Interrupt raw status register + addressOffset: 192 + size: 32 + fields: + - name: TIMER0_OVF_INT_RAW + description: "Raw status bit: The raw interrupt status of LEDC_TIMER0_OVF_INT. Triggered when the timer0 has reached its maximum counter value." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMER1_OVF_INT_RAW + description: "Raw status bit: The raw interrupt status of LEDC_TIMER1_OVF_INT. Triggered when the timer1 has reached its maximum counter value." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER2_OVF_INT_RAW + description: "Raw status bit: The raw interrupt status of LEDC_TIMER2_OVF_INT. Triggered when the timer2 has reached its maximum counter value." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TIMER3_OVF_INT_RAW + description: "Raw status bit: The raw interrupt status of LEDC_TIMER3_OVF_INT. Triggered when the timer3 has reached its maximum counter value." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH0_INT_RAW + description: "Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Triggered when the fading of duty has finished." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH1_INT_RAW + description: "Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Triggered when the fading of duty has finished." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH2_INT_RAW + description: "Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Triggered when the fading of duty has finished." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH3_INT_RAW + description: "Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Triggered when the fading of duty has finished." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH4_INT_RAW + description: "Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Triggered when the fading of duty has finished." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH5_INT_RAW + description: "Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Triggered when the fading of duty has finished." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH6_INT_RAW + description: "Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Triggered when the fading of duty has finished." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH7_INT_RAW + description: "Raw status bit: The raw interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Triggered when the fading of duty has finished." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH0_INT_RAW + description: "Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH0_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH1_INT_RAW + description: "Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH1_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH2_INT_RAW + description: "Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH2_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH3_INT_RAW + description: "Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH3_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH4_INT_RAW + description: "Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH4_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH5_INT_RAW + description: "Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH5_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH6_INT_RAW + description: "Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH6_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH7_INT_RAW + description: "Raw status bit: The raw interrupt status of LEDC_OVF_CNT_CH7_INT. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7." + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Interrupt masked status register + addressOffset: 196 + size: 32 + fields: + - name: TIMER0_OVF_INT_ST + description: "Masked status bit: The masked interrupt status of LEDC_TIMER0_OVF_INT. Valid only when LEDC_TIMER0_OVF_INT_ENA is set to 1." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TIMER1_OVF_INT_ST + description: "Masked status bit: The masked interrupt status of LEDC_TIMER1_OVF_INT. Valid only when LEDC_TIMER1_OVF_INT_ENA is set to 1." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TIMER2_OVF_INT_ST + description: "Masked status bit: The masked interrupt status of LEDC_TIMER2_OVF_INT. Valid only when LEDC_TIMER2_OVF_INT_ENA is set to 1." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TIMER3_OVF_INT_ST + description: "Masked status bit: The masked interrupt status of LEDC_TIMER3_OVF_INT. Valid only when LEDC_TIMER3_OVF_INT_ENA is set to 1." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH0_INT_ST + description: "Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH0_INT. Valid only when LEDC_DUTY_CHNG_END_CH0_INT_ENA is set to 1." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH1_INT_ST + description: "Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH1_INT. Valid only when LEDC_DUTY_CHNG_END_CH1_INT_ENA is set to 1." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH2_INT_ST + description: "Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH2_INT. Valid only when LEDC_DUTY_CHNG_END_CH2_INT_ENA is set to 1." + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH3_INT_ST + description: "Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH3_INT. Valid only when LEDC_DUTY_CHNG_END_CH3_INT_ENA is set to 1." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH4_INT_ST + description: "Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH4_INT. Valid only when LEDC_DUTY_CHNG_END_CH4_INT_ENA is set to 1." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH5_INT_ST + description: "Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH5_INT. Valid only when LEDC_DUTY_CHNG_END_CH5_INT_ENA is set to 1." + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH6_INT_ST + description: "Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH6_INT. Valid only when LEDC_DUTY_CHNG_END_CH6_INT_ENA is set to 1." + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH7_INT_ST + description: "Masked status bit: The masked interrupt status of LEDC_DUTY_CHNG_END_CH7_INT. Valid only when LEDC_DUTY_CHNG_END_CH7_INT_ENA is set to 1." + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH0_INT_ST + description: "Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH0_INT. Valid only when LEDC_OVF_CNT_CH0_INT_ENA is set to 1." + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH1_INT_ST + description: "Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH1_INT. Valid only when LEDC_OVF_CNT_CH1_INT_ENA is set to 1." + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH2_INT_ST + description: "Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH2_INT. Valid only when LEDC_OVF_CNT_CH2_INT_ENA is set to 1." + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH3_INT_ST + description: "Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH3_INT. Valid only when LEDC_OVF_CNT_CH3_INT_ENA is set to 1." + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH4_INT_ST + description: "Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH4_INT. Valid only when LEDC_OVF_CNT_CH4_INT_ENA is set to 1." + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH5_INT_ST + description: "Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH5_INT. Valid only when LEDC_OVF_CNT_CH5_INT_ENA is set to 1." + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH6_INT_ST + description: "Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH6_INT. Valid only when LEDC_OVF_CNT_CH6_INT_ENA is set to 1." + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH7_INT_ST + description: "Masked status bit: The masked interrupt status of LEDC_OVF_CNT_CH7_INT. Valid only when LEDC_OVF_CNT_CH7_INT_ENA is set to 1." + bitOffset: 19 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable register + addressOffset: 200 + size: 32 + fields: + - name: TIMER0_OVF_INT_ENA + description: "Enable bit: Write 1 to enable LEDC_TIMER0_OVF_INT." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMER1_OVF_INT_ENA + description: "Enable bit: Write 1 to enable LEDC_TIMER1_OVF_INT." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER2_OVF_INT_ENA + description: "Enable bit: Write 1 to enable LEDC_TIMER2_OVF_INT." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TIMER3_OVF_INT_ENA + description: "Enable bit: Write 1 to enable LEDC_TIMER3_OVF_INT." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH0_INT_ENA + description: "Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH0_INT." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH1_INT_ENA + description: "Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH1_INT." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH2_INT_ENA + description: "Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH2_INT." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH3_INT_ENA + description: "Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH3_INT." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH4_INT_ENA + description: "Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH4_INT." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH5_INT_ENA + description: "Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH5_INT." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH6_INT_ENA + description: "Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH6_INT." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH7_INT_ENA + description: "Enable bit: Write 1 to enable LEDC_DUTY_CHNG_END_CH7_INT." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH0_INT_ENA + description: "Enable bit: Write 1 to enable LEDC_OVF_CNT_CH0_INT." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH1_INT_ENA + description: "Enable bit: Write 1 to enable LEDC_OVF_CNT_CH1_INT." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH2_INT_ENA + description: "Enable bit: Write 1 to enable LEDC_OVF_CNT_CH2_INT." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH3_INT_ENA + description: "Enable bit: Write 1 to enable LEDC_OVF_CNT_CH3_INT." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH4_INT_ENA + description: "Enable bit: Write 1 to enable LEDC_OVF_CNT_CH4_INT." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH5_INT_ENA + description: "Enable bit: Write 1 to enable LEDC_OVF_CNT_CH5_INT." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH6_INT_ENA + description: "Enable bit: Write 1 to enable LEDC_OVF_CNT_CH6_INT." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH7_INT_ENA + description: "Enable bit: Write 1 to enable LEDC_OVF_CNT_CH7_INT." + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear register + addressOffset: 204 + size: 32 + fields: + - name: TIMER0_OVF_INT_CLR + description: "Clear bit: Write 1 to clear LEDC_TIMER0_OVF_INT." + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TIMER1_OVF_INT_CLR + description: "Clear bit: Write 1 to clear LEDC_TIMER1_OVF_INT." + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TIMER2_OVF_INT_CLR + description: "Clear bit: Write 1 to clear LEDC_TIMER2_OVF_INT." + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TIMER3_OVF_INT_CLR + description: "Clear bit: Write 1 to clear LEDC_TIMER3_OVF_INT." + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH0_INT_CLR + description: "Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH0_INT." + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH1_INT_CLR + description: "Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH1_INT." + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH2_INT_CLR + description: "Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH2_INT." + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH3_INT_CLR + description: "Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH3_INT." + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH4_INT_CLR + description: "Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH4_INT." + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH5_INT_CLR + description: "Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH5_INT." + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH6_INT_CLR + description: "Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH6_INT." + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH7_INT_CLR + description: "Clear bit: Write 1 to clear LEDC_DUTY_CHNG_END_CH7_INT." + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH0_INT_CLR + description: "Clear bit: Write 1 to clear LEDC_OVF_CNT_CH0_INT." + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH1_INT_CLR + description: "Clear bit: Write 1 to clear LEDC_OVF_CNT_CH1_INT." + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH2_INT_CLR + description: "Clear bit: Write 1 to clear LEDC_OVF_CNT_CH2_INT." + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH3_INT_CLR + description: "Clear bit: Write 1 to clear LEDC_OVF_CNT_CH3_INT." + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH4_INT_CLR + description: "Clear bit: Write 1 to clear LEDC_OVF_CNT_CH4_INT." + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH5_INT_CLR + description: "Clear bit: Write 1 to clear LEDC_OVF_CNT_CH5_INT." + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH6_INT_CLR + description: "Clear bit: Write 1 to clear LEDC_OVF_CNT_CH6_INT." + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH7_INT_CLR + description: "Clear bit: Write 1 to clear LEDC_OVF_CNT_CH7_INT." + bitOffset: 19 + bitWidth: 1 + access: write-only + - register: + dim: 8 + dimIncrement: 4 + name: CH%s_GAMMA_CONF + description: Ledc ch%s gamma config register. + addressOffset: 256 + size: 32 + fields: + - name: CH_GAMMA_ENTRY_NUM + description: Configures the number of duty cycle fading rages for LEDC ch%s. + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: CH_GAMMA_PAUSE + description: "Configures whether or not to pause duty cycle fading of LEDC ch%s.\\\\0: Invalid. No effect\\\\1: Pause" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CH_GAMMA_RESUME + description: "Configures whether or nor to resume duty cycle fading of LEDC ch%s.\\\\0: Invalid. No effect\\\\1: Resume" + bitOffset: 6 + bitWidth: 1 + access: write-only + - register: + name: EVT_TASK_EN0 + description: Ledc event task enable bit register0. + addressOffset: 288 + size: 32 + fields: + - name: EVT_DUTY_CHNG_END_CH0_EN + description: "Configures whether or not to enable the ledc_ch0_duty_chng_end event.\\\\0: Disable\\\\1: Enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EVT_DUTY_CHNG_END_CH1_EN + description: "Configures whether or not to enable the ledc_ch1_duty_chng_end event.\\\\0: Disable\\\\1: Enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EVT_DUTY_CHNG_END_CH2_EN + description: "Configures whether or not to enable the ledc_ch2_duty_chng_end event.\\\\0: Disable\\\\1: Enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EVT_DUTY_CHNG_END_CH3_EN + description: "Configures whether or not to enable the ledc_ch3_duty_chng_end event.\\\\0: Disable\\\\1: Enable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: EVT_DUTY_CHNG_END_CH4_EN + description: "Configures whether or not to enable the ledc_ch4_duty_chng_end event.\\\\0: Disable\\\\1: Enable" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: EVT_DUTY_CHNG_END_CH5_EN + description: "Configures whether or not to enable the ledc_ch5_duty_chng_end event.\\\\0: Disable\\\\1: Enable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: EVT_DUTY_CHNG_END_CH6_EN + description: "Configures whether or not to enable the ledc_ch6_duty_chng_end event.\\\\0: Disable\\\\1: Enable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: EVT_DUTY_CHNG_END_CH7_EN + description: "Configures whether or not to enable the ledc_ch7_duty_chng_end event.\\\\0: Disable\\\\1: Enable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: EVT_OVF_CNT_PLS_CH0_EN + description: "Configures whether or not to enable the ledc_ch0_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: EVT_OVF_CNT_PLS_CH1_EN + description: "Configures whether or not to enable the ledc_ch1_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: EVT_OVF_CNT_PLS_CH2_EN + description: "Configures whether or not to enable the ledc_ch2_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: EVT_OVF_CNT_PLS_CH3_EN + description: "Configures whether or not to enable the ledc_ch3_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: EVT_OVF_CNT_PLS_CH4_EN + description: "Configures whether or not to enable the ledc_ch4_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: EVT_OVF_CNT_PLS_CH5_EN + description: "Configures whether or not to enable the ledc_ch5_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: EVT_OVF_CNT_PLS_CH6_EN + description: "Configures whether or not to enable the ledc_ch6_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: EVT_OVF_CNT_PLS_CH7_EN + description: "Configures whether or not to enable the ledc_ch7_ovf_cnt_pls event.\\\\0: Disable\\\\1: Enable" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: EVT_TIME_OVF_TIMER0_EN + description: "Configures whether or not to enable the ledc_timer0_ovf event.\\\\0: Disable\\\\1: Enable" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: EVT_TIME_OVF_TIMER1_EN + description: "Configures whether or not to enable the ledc_timer1_ovf event.\\\\0: Disable\\\\1: Enable" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: EVT_TIME_OVF_TIMER2_EN + description: "Configures whether or not to enable the ledc_timer2_ovf event.\\\\0: Disable\\\\1: Enable" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: EVT_TIME_OVF_TIMER3_EN + description: "Configures whether or not to enable the ledc_timer3_ovf event.\\\\0: Disable\\\\1: Enable" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: EVT_TIME0_CMP_EN + description: "Configures whether or not to enable the ledc_timer0_cmp event.\\\\0: Disable\\\\1: Enable" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: EVT_TIME1_CMP_EN + description: "Configures whether or not to enable the ledc_timer1_cmp event.\\\\0: Disable\\\\1: Enable" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: EVT_TIME2_CMP_EN + description: "Configures whether or not to enable the ledc_timer2_cmp event.\\\\0: Disable\\\\1: Enable" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: EVT_TIME3_CMP_EN + description: "Configures whether or not to enable the ledc_timer3_cmp event.\\\\0: Disable\\\\1: Enable" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TASK_DUTY_SCALE_UPDATE_CH0_EN + description: "Configures whether or not to enable the ledc_ch0_duty_scale_update task.\\\\0: Disable\\\\1: Enable" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TASK_DUTY_SCALE_UPDATE_CH1_EN + description: "Configures whether or not to enable the ledc_ch1_duty_scale_update task.\\\\0: Disable\\\\1: Enable" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TASK_DUTY_SCALE_UPDATE_CH2_EN + description: "Configures whether or not to enable the ledc_ch2_duty_scale_update task.\\\\0: Disable\\\\1: Enable" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TASK_DUTY_SCALE_UPDATE_CH3_EN + description: "Configures whether or not to enable the ledc_ch3_duty_scale_update task.\\\\0: Disable\\\\1: Enable" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: TASK_DUTY_SCALE_UPDATE_CH4_EN + description: "Configures whether or not to enable the ledc_ch4_duty_scale_update task.\\\\0: Disable\\\\1: Enable" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: TASK_DUTY_SCALE_UPDATE_CH5_EN + description: "Configures whether or not to enable the ledc_ch5_duty_scale_update task.\\\\0: Disable\\\\1: Enable" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TASK_DUTY_SCALE_UPDATE_CH6_EN + description: "Configures whether or not to enable the ledc_ch6_duty_scale_update task.\\\\0: Disable\\\\1: Enable" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TASK_DUTY_SCALE_UPDATE_CH7_EN + description: "Configures whether or not to enable the ledc_ch7_duty_scale_update task.\\\\0: Disable\\\\1: Enable" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EVT_TASK_EN1 + description: Ledc event task enable bit register1. + addressOffset: 292 + size: 32 + fields: + - name: TASK_TIMER0_RES_UPDATE_EN + description: "Configures whether or not to enable ledc_timer0_res_update task.\\\\0: Disable\\\\1: Enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TASK_TIMER1_RES_UPDATE_EN + description: "Configures whether or not to enable ledc_timer1_res_update task.\\\\0: Disable\\\\1: Enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TASK_TIMER2_RES_UPDATE_EN + description: "Configures whether or not to enable ledc_timer2_res_update task.\\\\0: Disable\\\\1: Enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TASK_TIMER3_RES_UPDATE_EN + description: "Configures whether or not to enable ledc_timer3_res_update task.\\\\0: Disable\\\\1: Enable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TASK_TIMER0_CAP_EN + description: "Configures whether or not to enable ledc_timer0_cap task.\\\\0: Disable\\\\1: Enable" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TASK_TIMER1_CAP_EN + description: "Configures whether or not to enable ledc_timer1_cap task.\\\\0: Disable\\\\1: Enable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TASK_TIMER2_CAP_EN + description: "Configures whether or not to enable ledc_timer2_cap task.\\\\0: Disable\\\\1: Enable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TASK_TIMER3_CAP_EN + description: "Configures whether or not to enable ledc_timer3_cap task.\\\\0: Disable\\\\1: Enable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TASK_SIG_OUT_DIS_CH0_EN + description: "Configures whether or not to enable ledc_ch0_sig_out_dis task.\\\\0: Disable\\\\1: Enable" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TASK_SIG_OUT_DIS_CH1_EN + description: "Configures whether or not to enable ledc_ch1_sig_out_dis task.\\\\0: Disable\\\\1: Enable" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TASK_SIG_OUT_DIS_CH2_EN + description: "Configures whether or not to enable ledc_ch2_sig_out_dis task.\\\\0: Disable\\\\1: Enable" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TASK_SIG_OUT_DIS_CH3_EN + description: "Configures whether or not to enable ledc_ch3_sig_out_dis task.\\\\0: Disable\\\\1: Enable" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TASK_SIG_OUT_DIS_CH4_EN + description: "Configures whether or not to enable ledc_ch4_sig_out_dis task.\\\\0: Disable\\\\1: Enable" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TASK_SIG_OUT_DIS_CH5_EN + description: "Configures whether or not to enable ledc_ch5_sig_out_dis task.\\\\0: Disable\\\\1: Enable" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TASK_SIG_OUT_DIS_CH6_EN + description: "Configures whether or not to enable ledc_ch6_sig_out_dis task.\\\\0: Disable\\\\1: Enable" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TASK_SIG_OUT_DIS_CH7_EN + description: "Configures whether or not to enable ledc_ch7_sig_out_dis task.\\\\0: Disable\\\\1: Enable" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TASK_OVF_CNT_RST_CH0_EN + description: "Configures whether or not to enable ledc_ch0_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: TASK_OVF_CNT_RST_CH1_EN + description: "Configures whether or not to enable ledc_ch1_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: TASK_OVF_CNT_RST_CH2_EN + description: "Configures whether or not to enable ledc_ch2_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TASK_OVF_CNT_RST_CH3_EN + description: "Configures whether or not to enable ledc_ch3_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: TASK_OVF_CNT_RST_CH4_EN + description: "Configures whether or not to enable ledc_ch4_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TASK_OVF_CNT_RST_CH5_EN + description: "Configures whether or not to enable ledc_ch5_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: TASK_OVF_CNT_RST_CH6_EN + description: "Configures whether or not to enable ledc_ch6_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TASK_OVF_CNT_RST_CH7_EN + description: "Configures whether or not to enable ledc_ch7_ovf_cnt_rst task.\\\\0: Disable\\\\1: Enable" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TASK_TIMER0_RST_EN + description: "Configures whether or not to enable ledc_timer0_rst task.\\\\0: Disable\\\\1: Enable" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TASK_TIMER1_RST_EN + description: "Configures whether or not to enable ledc_timer1_rst task.\\\\0: Disable\\\\1: Enable" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TASK_TIMER2_RST_EN + description: "Configures whether or not to enable ledc_timer2_rst task.\\\\0: Disable\\\\1: Enable" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TASK_TIMER3_RST_EN + description: "Configures whether or not to enable ledc_timer3_rst task.\\\\0: Disable\\\\1: Enable" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: TASK_TIMER0_PAUSE_RESUME_EN + description: "Configures whether or not to enable ledc_timer0_pause_resume task.\\\\0: Disable\\\\1: Enable" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: TASK_TIMER1_PAUSE_RESUME_EN + description: "Configures whether or not to enable ledc_timer1_pause_resume task.\\\\0: Disable\\\\1: Enable" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TASK_TIMER2_PAUSE_RESUME_EN + description: "Configures whether or not to enable ledc_timer2_pause_resume task.\\\\0: Disable\\\\1: Enable" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TASK_TIMER3_PAUSE_RESUME_EN + description: "Configures whether or not to enable ledc_timer3_pause_resume task.\\\\0: Disable\\\\1: Enable" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EVT_TASK_EN2 + description: Ledc event task enable bit register2. + addressOffset: 296 + size: 32 + fields: + - name: TASK_GAMMA_RESTART_CH0_EN + description: "Configures whether or not to enable ledc_ch0_gamma_restart task.\\\\0: Disable\\\\1: Enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESTART_CH1_EN + description: "Configures whether or not to enable ledc_ch1_gamma_restart task.\\\\0: Disable\\\\1: Enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESTART_CH2_EN + description: "Configures whether or not to enable ledc_ch2_gamma_restart task.\\\\0: Disable\\\\1: Enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESTART_CH3_EN + description: "Configures whether or not to enable ledc_ch3_gamma_restart task.\\\\0: Disable\\\\1: Enable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESTART_CH4_EN + description: "Configures whether or not to enable ledc_ch4_gamma_restart task.\\\\0: Disable\\\\1: Enable" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESTART_CH5_EN + description: "Configures whether or not to enable ledc_ch5_gamma_restart task.\\\\0: Disable\\\\1: Enable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESTART_CH6_EN + description: "Configures whether or not to enable ledc_ch6_gamma_restart task.\\\\0: Disable\\\\1: Enable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESTART_CH7_EN + description: "Configures whether or not to enable ledc_ch7_gamma_restart task.\\\\0: Disable\\\\1: Enable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_PAUSE_CH0_EN + description: "Configures whether or not to enable ledc_ch0_gamma_pause task.\\\\0: Disable\\\\1: Enable" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_PAUSE_CH1_EN + description: "Configures whether or not to enable ledc_ch1_gamma_pause task.\\\\0: Disable\\\\1: Enable" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_PAUSE_CH2_EN + description: "Configures whether or not to enable ledc_ch2_gamma_pause task.\\\\0: Disable\\\\1: Enable" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_PAUSE_CH3_EN + description: "Configures whether or not to enable ledc_ch3_gamma_pause task.\\\\0: Disable\\\\1: Enable" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_PAUSE_CH4_EN + description: "Configures whether or not to enable ledc_ch4_gamma_pause task.\\\\0: Disable\\\\1: Enable" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_PAUSE_CH5_EN + description: "Configures whether or not to enable ledc_ch5_gamma_pause task.\\\\0: Disable\\\\1: Enable" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_PAUSE_CH6_EN + description: "Configures whether or not to enable ledc_ch6_gamma_pause task.\\\\0: Disable\\\\1: Enable" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_PAUSE_CH7_EN + description: "Configures whether or not to enable ledc_ch7_gamma_pause task.\\\\0: Disable\\\\1: Enable" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESUME_CH0_EN + description: "Configures whether or not to enable ledc_ch0_gamma_resume task.\\\\0: Disable\\\\1: Enable" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESUME_CH1_EN + description: "Configures whether or not to enable ledc_ch1_gamma_resume task.\\\\0: Disable\\\\1: Enable" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESUME_CH2_EN + description: "Configures whether or not to enable ledc_ch2_gamma_resume task.\\\\0: Disable\\\\1: Enable" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESUME_CH3_EN + description: "Configures whether or not to enable ledc_ch3_gamma_resume task.\\\\0: Disable\\\\1: Enable" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESUME_CH4_EN + description: "Configures whether or not to enable ledc_ch4_gamma_resume task.\\\\0: Disable\\\\1: Enable" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESUME_CH5_EN + description: "Configures whether or not to enable ledc_ch5_gamma_resume task.\\\\0: Disable\\\\1: Enable" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESUME_CH6_EN + description: "Configures whether or not to enable ledc_ch6_gamma_resume task.\\\\0: Disable\\\\1: Enable" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TASK_GAMMA_RESUME_CH7_EN + description: "Configures whether or not to enable ledc_ch7_gamma_resume task.\\\\0: Disable\\\\1: Enable" + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: TIMER%s_CMP + description: Ledc timer%s compare value register. + addressOffset: 320 + size: 32 + fields: + - name: TIMER_CMP + description: Configures the comparison value for LEDC timer%s. + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: TIMER%s_CNT_CAP + description: Ledc timer%s captured count value register. + addressOffset: 336 + size: 32 + fields: + - name: TIMER_CNT_CAP + description: Represents the captured LEDC timer%s count value. + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: CONF + description: LEDC global configuration register + addressOffset: 368 + size: 32 + fields: + - name: APB_CLK_SEL + description: "Configures the clock source for the four timers.\\\\0: APB_CLK\\\\1: RC_FAST_CLK\\\\2: XTAL_CLK\\\\3: Invalid. No clock" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: GAMMA_RAM_CLK_EN_CH0 + description: "Configures whether or not to open LEDC ch0 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch0 gamma ram\\\\1: Force open the clock gate for LEDC ch0 gamma ram" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: GAMMA_RAM_CLK_EN_CH1 + description: "Configures whether or not to open LEDC ch1 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch1 gamma ram\\\\1: Force open the clock gate for LEDC ch1 gamma ram" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: GAMMA_RAM_CLK_EN_CH2 + description: "Configures whether or not to open LEDC ch2 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch2 gamma ram\\\\1: Force open the clock gate for LEDC ch2 gamma ram" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: GAMMA_RAM_CLK_EN_CH3 + description: "Configures whether or not to open LEDC ch3 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch3 gamma ram\\\\1: Force open the clock gate for LEDC ch3 gamma ram" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: GAMMA_RAM_CLK_EN_CH4 + description: "Configures whether or not to open LEDC ch4 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch4 gamma ram\\\\1: Force open the clock gate for LEDC ch4 gamma ram" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: GAMMA_RAM_CLK_EN_CH5 + description: "Configures whether or not to open LEDC ch5 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch5 gamma ram\\\\1: Force open the clock gate for LEDC ch5 gamma ram" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: GAMMA_RAM_CLK_EN_CH6 + description: "Configures whether or not to open LEDC ch6 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch6 gamma ram\\\\1: Force open the clock gate for LEDC ch6 gamma ram" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: GAMMA_RAM_CLK_EN_CH7 + description: "Configures whether or not to open LEDC ch7 gamma ram clock gate.\\\\0: Open the clock gate only when application writes or reads LEDC ch7 gamma ram\\\\1: Force open the clock gate for LEDC ch7 gamma ram" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 372 + size: 32 + resetValue: 36712560 + fields: + - name: LEDC_DATE + description: Configures the version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: LP_INTR + description: Low-power Interrupt Controller + groupName: LPINTR + baseAddress: 1343406080 + addressBlock: + - offset: 0 + size: 24 + usage: registers + registers: + - register: + name: SW_INT_RAW + description: need_des + addressOffset: 0 + size: 32 + fields: + - name: LP_SW_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SW_INT_ST + description: need_des + addressOffset: 4 + size: 32 + fields: + - name: LP_SW_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: SW_INT_ENA + description: need_des + addressOffset: 8 + size: 32 + fields: + - name: LP_SW_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SW_INT_CLR + description: need_des + addressOffset: 12 + size: 32 + fields: + - name: LP_SW_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: STATUS + description: need_des + addressOffset: 16 + size: 32 + fields: + - name: LP_HUK_INTR_ST + description: need_des + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SYSREG_INTR_ST + description: need_des + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: LP_SW_INTR_ST + description: need_des + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: LP_EFUSE_INTR_ST + description: need_des + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: LP_UART_INTR_ST + description: need_des + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: LP_TSENS_INTR_ST + description: need_des + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: LP_TOUCH_INTR_ST + description: need_des + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: LP_SPI_INTR_ST + description: need_des + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: LP_I2S_INTR_ST + description: need_des + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: LP_I2C_INTR_ST + description: need_des + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: LP_GPIO_INTR_ST + description: need_des + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: LP_ADC_INTR_ST + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: ANAPERI_INTR_ST + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: PMU_REG_1_INTR_ST + description: need_des + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: PMU_REG_0_INTR_ST + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: MB_LP_INTR_ST + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: MB_HP_INTR_ST + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: LP_TIMER_REG_1_INTR_ST + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: LP_TIMER_REG_0_INTR_ST + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: LP_WDT_INTR_ST + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: LP_RTC_INTR_ST + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: HP_INTR_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + fields: + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: LP_PERI + description: LP_PERI Peripheral + groupName: LPPERI + baseAddress: 1343356928 + addressBlock: + - offset: 0 + size: 44 + usage: registers + registers: + - register: + name: CLK_EN + description: need_des + addressOffset: 0 + size: 32 + resetValue: 2147418112 + fields: + - name: CK_EN_RNG + description: need_des + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CK_EN_LP_TSENS + description: need_des + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: CK_EN_LP_PMS + description: need_des + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: CK_EN_LP_EFUSE + description: need_des + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: CK_EN_LP_IOMUX + description: need_des + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CK_EN_LP_TOUCH + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CK_EN_LP_SPI + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: CK_EN_LP_ADC + description: need_des + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: CK_EN_LP_I2S_TX + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: CK_EN_LP_I2S_RX + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: CK_EN_LP_I2S + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CK_EN_LP_I2CMST + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: CK_EN_LP_I2C + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CK_EN_LP_UART + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CK_EN_LP_INTR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CK_EN_LP_CORE + description: write 1 to force on lp_core clk + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CORE_CLK_SEL + description: need_des + addressOffset: 4 + size: 32 + fields: + - name: LP_I2S_TX_CLK_SEL + description: need_des + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: LP_I2S_RX_CLK_SEL + description: need_des + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: LP_I2C_CLK_SEL + description: need_des + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: LP_UART_CLK_SEL + description: need_des + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: RESET_EN + description: need_des + addressOffset: 8 + size: 32 + fields: + - name: RST_EN_LP_TSENS + description: need_des + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RST_EN_LP_PMS + description: need_des + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RST_EN_LP_EFUSE + description: need_des + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: RST_EN_LP_IOMUX + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: RST_EN_LP_TOUCH + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RST_EN_LP_SPI + description: need_des + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: RST_EN_LP_ADC + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: RST_EN_LP_I2S + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: RST_EN_LP_I2CMST + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RST_EN_LP_I2C + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RST_EN_LP_UART + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: RST_EN_LP_INTR + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: RST_EN_LP_ROM + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: RST_EN_LP_CORE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: CPU + description: need_des + addressOffset: 12 + size: 32 + resetValue: 2147483648 + fields: + - name: LPCORE_DBGM_UNAVAILABLE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: MEM_CTRL + description: need_des + addressOffset: 40 + size: 32 + resetValue: 2147483648 + fields: + - name: LP_UART_WAKEUP_FLAG_CLR + description: need_des + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: LP_UART_WAKEUP_FLAG + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: LP_UART_WAKEUP_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LP_UART_MEM_FORCE_PD + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_UART_MEM_FORCE_PU + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: ADC_CTRL + description: need_des + addressOffset: 44 + size: 32 + resetValue: 67372032 + fields: + - name: SAR2_CLK_FORCE_ON + description: need_des + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SAR1_CLK_FORCE_ON + description: need_des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: LPADC_FUNC_DIV_NUM + description: need_des + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: LPADC_SAR2_DIV_NUM + description: need_des + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: LPADC_SAR1_DIV_NUM + description: need_des + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: LP_I2S_RXCLK_DIV_NUM + description: need_des + addressOffset: 48 + size: 32 + resetValue: 33554432 + fields: + - name: LP_I2S_RX_CLKM_DIV_NUM + description: need_des + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: LP_I2S_RXCLK_DIV_XYZ + description: need_des + addressOffset: 52 + size: 32 + resetValue: 16384 + fields: + - name: LP_I2S_RX_CLKM_DIV_YN1 + description: need_des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: LP_I2S_RX_CLKM_DIV_Z + description: need_des + bitOffset: 5 + bitWidth: 9 + access: read-write + - name: LP_I2S_RX_CLKM_DIV_Y + description: need_des + bitOffset: 14 + bitWidth: 9 + access: read-write + - name: LP_I2S_RX_CLKM_DIV_X + description: need_des + bitOffset: 23 + bitWidth: 9 + access: read-write + - register: + name: LP_I2S_TXCLK_DIV_NUM + description: need_des + addressOffset: 56 + size: 32 + resetValue: 33554432 + fields: + - name: LP_I2S_TX_CLKM_DIV_NUM + description: need_des + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: LP_I2S_TXCLK_DIV_XYZ + description: need_des + addressOffset: 60 + size: 32 + resetValue: 16384 + fields: + - name: LP_I2S_TX_CLKM_DIV_YN1 + description: need_des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: LP_I2S_TX_CLKM_DIV_Z + description: need_des + bitOffset: 5 + bitWidth: 9 + access: read-write + - name: LP_I2S_TX_CLKM_DIV_Y + description: need_des + bitOffset: 14 + bitWidth: 9 + access: read-write + - name: LP_I2S_TX_CLKM_DIV_X + description: need_des + bitOffset: 23 + bitWidth: 9 + access: read-write + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + fields: + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: LP_SYS + description: LP_SYS Peripheral + groupName: LPSYSREG + baseAddress: 1343291392 + addressBlock: + - offset: 0 + size: 272 + usage: registers + interrupt: + - name: LP_SYS + value: 19 + registers: + - register: + name: LP_SYS_VER_DATE + description: need_des + addressOffset: 0 + size: 32 + resetValue: 539165961 + fields: + - name: VER_DATE + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CLK_SEL_CTRL + description: need_des + addressOffset: 4 + size: 32 + fields: + - name: ENA_SW_SEL_SYS_CLK + description: reserved + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SW_SYS_CLK_SRC_SEL + description: reserved + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: SYS_CTRL + description: need_des + addressOffset: 8 + size: 32 + resetValue: 536856568 + fields: + - name: LP_CORE_DISABLE + description: lp cpu disable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SYS_SW_RST + description: digital system software reset bit + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: FORCE_DOWNLOAD_BOOT + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DIG_FIB + description: need_des + bitOffset: 3 + bitWidth: 8 + access: read-write + - name: IO_MUX_RESET_DISABLE + description: reset disable bit for LP IOMUX + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: ANA_FIB + description: need_des + bitOffset: 14 + bitWidth: 7 + access: read-only + - name: LP_FIB_SEL + description: need_des + bitOffset: 21 + bitWidth: 8 + access: read-write + - name: LP_CORE_ETM_WAKEUP_FLAG_CLR + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: LP_CORE_ETM_WAKEUP_FLAG + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SYSTIMER_STALL_SEL + description: "0: use systimer_stall signal from hp_core0, 1: use systimer_stall signal from hp_core1" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_CLK_CTRL + description: need_des + addressOffset: 12 + size: 32 + resetValue: 16385 + fields: + - name: CLK_EN + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LP_FOSC_HP_CKEN + description: reserved + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: LP_RST_CTRL + description: need_des + addressOffset: 16 + size: 32 + resetValue: 3 + fields: + - name: ANA_RST_BYPASS + description: "analog source reset bypass : wdt,brown out,super wdt,glitch" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SYS_RST_BYPASS + description: "system source reset bypass : software reset,hp wdt,lp wdt,efuse" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EFUSE_FORCE_NORST + description: efuse force no reset control + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: LP_CORE_BOOT_ADDR + description: need_des + addressOffset: 24 + size: 32 + resetValue: 1343225856 + fields: + - name: LP_CPU_BOOT_ADDR + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: EXT_WAKEUP1 + description: need_des + addressOffset: 28 + size: 32 + fields: + - name: SEL + description: Bitmap to select RTC pads for ext wakeup1 + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: STATUS_CLR + description: clear ext wakeup1 status + bitOffset: 16 + bitWidth: 1 + access: write-only + - register: + name: EXT_WAKEUP1_STATUS + description: need_des + addressOffset: 32 + size: 32 + fields: + - name: EXT_WAKEUP1_STATUS + description: ext wakeup1 status + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: LP_TCM_PWR_CTRL + description: need_des + addressOffset: 36 + size: 32 + fields: + - name: LP_TCM_ROM_CLK_FORCE_ON + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: LP_TCM_RAM_CLK_FORCE_ON + description: need_des + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: BOOT_ADDR_HP_LP + description: need_des + addressOffset: 40 + size: 32 + fields: + - name: BOOT_ADDR_HP_LP + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_STORE0 + description: need_des + addressOffset: 44 + size: 32 + fields: + - name: LP_SCRATCH0 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_STORE1 + description: need_des + addressOffset: 48 + size: 32 + fields: + - name: LP_SCRATCH1 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_STORE2 + description: need_des + addressOffset: 52 + size: 32 + fields: + - name: LP_SCRATCH2 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_STORE3 + description: need_des + addressOffset: 56 + size: 32 + fields: + - name: LP_SCRATCH3 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_STORE4 + description: need_des + addressOffset: 60 + size: 32 + fields: + - name: LP_SCRATCH4 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_STORE5 + description: need_des + addressOffset: 64 + size: 32 + fields: + - name: LP_SCRATCH5 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_STORE6 + description: need_des + addressOffset: 68 + size: 32 + fields: + - name: LP_SCRATCH6 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_STORE7 + description: need_des + addressOffset: 72 + size: 32 + fields: + - name: LP_SCRATCH7 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_STORE8 + description: need_des + addressOffset: 76 + size: 32 + fields: + - name: LP_SCRATCH8 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_STORE9 + description: need_des + addressOffset: 80 + size: 32 + fields: + - name: LP_SCRATCH9 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_STORE10 + description: need_des + addressOffset: 84 + size: 32 + fields: + - name: LP_SCRATCH10 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_STORE11 + description: need_des + addressOffset: 88 + size: 32 + fields: + - name: LP_SCRATCH11 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_STORE12 + description: need_des + addressOffset: 92 + size: 32 + fields: + - name: LP_SCRATCH12 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_STORE13 + description: need_des + addressOffset: 96 + size: 32 + fields: + - name: LP_SCRATCH13 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_STORE14 + description: need_des + addressOffset: 100 + size: 32 + fields: + - name: LP_SCRATCH14 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_STORE15 + description: need_des + addressOffset: 104 + size: 32 + fields: + - name: LP_SCRATCH15 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_PROBEA_CTRL + description: need_des + addressOffset: 108 + size: 32 + fields: + - name: PROBE_A_MOD_SEL + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: PROBE_A_TOP_SEL + description: need_des + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: PROBE_L_SEL + description: need_des + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: PROBE_H_SEL + description: need_des + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: PROBE_GLOBAL_EN + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: LP_PROBEB_CTRL + description: need_des + addressOffset: 112 + size: 32 + fields: + - name: PROBE_B_MOD_SEL + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: PROBE_B_TOP_SEL + description: need_des + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: PROBE_B_EN + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: LP_PROBE_OUT + description: need_des + addressOffset: 116 + size: 32 + fields: + - name: PROBE_TOP_OUT + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: F2S_APB_BRG_CNTL + description: need_des + addressOffset: 156 + size: 32 + fields: + - name: F2S_APB_POSTW_EN + description: reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: USB_CTRL + description: need_des + addressOffset: 256 + size: 32 + fields: + - name: SW_HW_USB_PHY_SEL + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SW_USB_PHY_SEL + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: USBOTG20_WAKEUP_CLR + description: clear usb wakeup to PMU. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: USBOTG20_IN_SUSPEND + description: indicate usb otg2.0 is in suspend state. + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: ANA_XPD_PAD_GROUP + description: need_des + addressOffset: 268 + size: 32 + resetValue: 255 + fields: + - name: ANA_REG_XPD_PAD_GROUP + description: Set 1 to power up pad group + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: LP_TCM_RAM_RDN_ECO_CS + description: need_des + addressOffset: 272 + size: 32 + fields: + - name: LP_TCM_RAM_RDN_ECO_EN + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LP_TCM_RAM_RDN_ECO_RESULT + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: LP_TCM_RAM_RDN_ECO_LOW + description: need_des + addressOffset: 276 + size: 32 + fields: + - name: LP_TCM_RAM_RDN_ECO_LOW + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_TCM_RAM_RDN_ECO_HIGH + description: need_des + addressOffset: 280 + size: 32 + resetValue: 4294967295 + fields: + - name: LP_TCM_RAM_RDN_ECO_HIGH + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_TCM_ROM_RDN_ECO_CS + description: need_des + addressOffset: 284 + size: 32 + fields: + - name: LP_TCM_ROM_RDN_ECO_EN + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LP_TCM_ROM_RDN_ECO_RESULT + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: LP_TCM_ROM_RDN_ECO_LOW + description: need_des + addressOffset: 288 + size: 32 + fields: + - name: LP_TCM_ROM_RDN_ECO_LOW + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_TCM_ROM_RDN_ECO_HIGH + description: need_des + addressOffset: 292 + size: 32 + resetValue: 4294967295 + fields: + - name: LP_TCM_ROM_RDN_ECO_HIGH + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_ROOT_CLK_CTRL + description: need_des + addressOffset: 304 + size: 32 + resetValue: 3 + fields: + - name: CPU_CLK_EN + description: clock gate enable for hp cpu root 400M clk + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SYS_CLK_EN + description: clock gate enable for hp sys root 480M clk + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: LP_PMU_RDN_ECO_LOW + description: need_des + addressOffset: 312 + size: 32 + fields: + - name: PMU_RDN_ECO_LOW + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_PMU_RDN_ECO_HIGH + description: need_des + addressOffset: 316 + size: 32 + resetValue: 4294967295 + fields: + - name: PMU_RDN_ECO_HIGH + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PAD_COMP0 + description: need_des + addressOffset: 328 + size: 32 + fields: + - name: DREF_COMP0 + description: pad comp dref + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: MODE_COMP0 + description: pad comp mode + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: XPD_COMP0 + description: pad comp xpd + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: PAD_COMP1 + description: need_des + addressOffset: 332 + size: 32 + fields: + - name: DREF_COMP1 + description: pad comp dref + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: MODE_COMP1 + description: pad comp mode + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: XPD_COMP1 + description: pad comp xpd + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: BACKUP_DMA_CFG0 + description: need_des + addressOffset: 340 + size: 32 + resetValue: 419840330 + fields: + - name: BURST_LIMIT_AON + description: need_des + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: READ_INTERVAL_AON + description: need_des + bitOffset: 5 + bitWidth: 7 + access: read-write + - name: LINK_BACKUP_TOUT_THRES_AON + description: need_des + bitOffset: 12 + bitWidth: 10 + access: read-write + - name: LINK_TOUT_THRES_AON + description: need_des + bitOffset: 22 + bitWidth: 10 + access: read-write + - register: + name: BACKUP_DMA_CFG1 + description: need_des + addressOffset: 344 + size: 32 + fields: + - name: AON_BYPASS + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: BACKUP_DMA_CFG2 + description: need_des + addressOffset: 348 + size: 32 + fields: + - name: LINK_ADDR_AON + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BOOT_ADDR_HP_CORE1 + description: need_des + addressOffset: 356 + size: 32 + fields: + - name: BOOT_ADDR_HP_CORE1 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_ADDRHOLE_ADDR + description: need_des + addressOffset: 360 + size: 32 + fields: + - name: LP_ADDRHOLE_ADDR + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: LP_ADDRHOLE_INFO + description: need_des + addressOffset: 364 + size: 32 + fields: + - name: LP_ADDRHOLE_ID + description: "master id: 5'h0: hp core0, 5'h1:hp core1, 5'h2:lp core, 5'h3:usb otg11, 5'h4: regdma, 5'h5: gmac, 5'h5 sdmmc, 5'h7: usbotg20, 5'h8: trace0, 5'h9: trace1, 5'ha tcm monitor, 5'hb: l2mem monitor. 5'h10~5'h1f: ahb pdma." + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: LP_ADDRHOLE_WR + description: "1:write trans, 0: read trans." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: LP_ADDRHOLE_SECURE + description: "1: illegal address access, 0: access without permission" + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: INT_RAW + description: raw interrupt register + addressOffset: 368 + size: 32 + fields: + - name: LP_ADDRHOLE_INT_RAW + description: "the raw interrupt status of lp addrhole(for lp peri and lp ram tee apm, and lp matrix default slave)" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: IDBUS_ADDRHOLE_INT_RAW + description: the raw interrupt status of idbus addrhole(only for lp cpu ibus and dbus) + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: LP_CORE_AHB_TIMEOUT_INT_RAW + description: the raw interrupt status of lp core ahb bus timeout + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: LP_CORE_IBUS_TIMEOUT_INT_RAW + description: the raw interrupt status of lp core ibus timeout + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: LP_CORE_DBUS_TIMEOUT_INT_RAW + description: the raw interrupt status of lp core dbus timeout + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ETM_TASK_ULP_INT_RAW + description: the raw interrupt status of etm task ulp + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SLOW_CLK_TICK_INT_RAW + description: the raw interrupt status of slow_clk_tick + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: masked interrupt register + addressOffset: 372 + size: 32 + fields: + - name: LP_ADDRHOLE_INT_ST + description: "the masked interrupt status of lp addrhole (for lp peri and lp ram tee apm, and lp matrix default slave)" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: IDBUS_ADDRHOLE_INT_ST + description: the masked interrupt status of idbus addrhole(only for lp cpu ibus and dbus) + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: LP_CORE_AHB_TIMEOUT_INT_ST + description: the masked interrupt status of lp core ahb bus timeout + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: LP_CORE_IBUS_TIMEOUT_INT_ST + description: the masked interrupt status of lp core ibus timeout + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: LP_CORE_DBUS_TIMEOUT_INT_ST + description: the masked interrupt status of lp core dbus timeout + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ETM_TASK_ULP_INT_ST + description: the masked interrupt status of etm task ulp + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SLOW_CLK_TICK_INT_ST + description: the masked interrupt status of slow_clk_tick + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: masked interrupt register + addressOffset: 376 + size: 32 + fields: + - name: LP_ADDRHOLE_INT_ENA + description: Write 1 to enable lp addrhole int + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IDBUS_ADDRHOLE_INT_ENA + description: Write 1 to enable idbus addrhole int + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: LP_CORE_AHB_TIMEOUT_INT_ENA + description: Write 1 to enable lp_core_ahb_timeout int + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: LP_CORE_IBUS_TIMEOUT_INT_ENA + description: Write 1 to enable lp_core_ibus_timeout int + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: LP_CORE_DBUS_TIMEOUT_INT_ENA + description: Write 1 to enable lp_core_dbus_timeout int + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ETM_TASK_ULP_INT_ENA + description: Write 1 to enable etm task ulp int + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SLOW_CLK_TICK_INT_ENA + description: Write 1 to enable slow_clk_tick int + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: interrupt clear register + addressOffset: 380 + size: 32 + fields: + - name: LP_ADDRHOLE_INT_CLR + description: write 1 to clear lp addrhole int + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: IDBUS_ADDRHOLE_INT_CLR + description: write 1 to clear idbus addrhole int + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: LP_CORE_AHB_TIMEOUT_INT_CLR + description: Write 1 to clear lp_core_ahb_timeout int + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: LP_CORE_IBUS_TIMEOUT_INT_CLR + description: Write 1 to clear lp_core_ibus_timeout int + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: LP_CORE_DBUS_TIMEOUT_INT_CLR + description: Write 1 to clear lp_core_dbus_timeout int + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: ETM_TASK_ULP_INT_CLR + description: Write 1 to clear etm tasl ulp int + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: SLOW_CLK_TICK_INT_CLR + description: Write 1 to clear slow_clk_tick int + bitOffset: 6 + bitWidth: 1 + access: write-only + - register: + name: HP_MEM_AUX_CTRL + description: need_des + addressOffset: 384 + size: 32 + resetValue: 8304 + fields: + - name: HP_MEM_AUX_CTRL + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_MEM_AUX_CTRL + description: need_des + addressOffset: 388 + size: 32 + resetValue: 8304 + fields: + - name: LP_MEM_AUX_CTRL + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_ROM_AUX_CTRL + description: need_des + addressOffset: 392 + size: 32 + resetValue: 112 + fields: + - name: HP_ROM_AUX_CTRL + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_ROM_AUX_CTRL + description: need_des + addressOffset: 396 + size: 32 + resetValue: 112 + fields: + - name: LP_ROM_AUX_CTRL + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_CPU_DBG_PC + description: need_des + addressOffset: 400 + size: 32 + fields: + - name: LP_CPU_DBG_PC + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: LP_CPU_EXC_PC + description: need_des + addressOffset: 404 + size: 32 + fields: + - name: LP_CPU_EXC_PC + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IDBUS_ADDRHOLE_ADDR + description: need_des + addressOffset: 408 + size: 32 + fields: + - name: IDBUS_ADDRHOLE_ADDR + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IDBUS_ADDRHOLE_INFO + description: need_des + addressOffset: 412 + size: 32 + fields: + - name: IDBUS_ADDRHOLE_ID + description: need_des + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: IDBUS_ADDRHOLE_WR + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: IDBUS_ADDRHOLE_SECURE + description: need_des + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: HP_POR_RST_BYPASS_CTRL + description: need_des + addressOffset: 416 + size: 32 + resetValue: 4278255360 + fields: + - name: HP_PO_CNNT_RSTN_BYPASS_CTRL + description: "[15] 1'b1: po_cnnt_rstn bypass sys_sw_rstn\n[14] 1'b1: po_cnnt_rstn bypass hp_wdt_sys_rstn\n[13] 1'b1: po_cnnt_rstn bypass hp_cpu_intrusion_rstn\n[12] 1'b1: po_cnnt_rstn bypass hp_sdio_sys_rstn\n[11] 1'b1: po_cnnt_rstn bypass usb_jtag_chip_rst\n[10] 1'b1: po_cnnt_rstn bypass usb_uart_chip_rst\n[9] 1'b1: po_cnnt_rstn bypass lp_wdt_hp_sys_rstn\n[8] 1'b1: po_cnnt_rstn bypass efuse_err_rstn" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: HP_PO_RSTN_BYPASS_CTRL + description: "[31] 1'b1: po_rstn bypass sys_sw_rstn\n[30] 1'b1: po_rstn bypass hp_wdt_sys_rstn\n[29] 1'b1: po_rstn bypass hp_cpu_intrusion_rstn\n[28] 1'b1: po_rstn bypass hp_sdio_sys_rstn\n[27] 1'b1: po_rstn bypass usb_jtag_chip_rst\n[26] 1'b1: po_rstn bypass usb_uart_chip_rst\n[25] 1'b1: po_rstn bypass lp_wdt_hp_sys_rstn\n[24] 1'b1: po_rstn bypass efuse_err_rstn" + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: RNG_DATA + description: rng data register + addressOffset: 420 + size: 32 + fields: + - name: RND_DATA + description: result of rng output + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: LP_CORE_AHB_TIMEOUT + description: need_des + addressOffset: 432 + size: 32 + resetValue: 8388607 + fields: + - name: EN + description: set this field to 1 to enable lp core ahb timeout handle + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: THRES + description: This field used to set lp core ahb bus timeout threshold + bitOffset: 1 + bitWidth: 16 + access: read-write + - name: LP2HP_AHB_TIMEOUT_EN + description: set this field to 1 to enable lp2hp ahb timeout handle + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: LP2HP_AHB_TIMEOUT_THRES + description: This field used to set lp2hp ahb bus timeout threshold + bitOffset: 18 + bitWidth: 5 + access: read-write + - register: + name: LP_CORE_IBUS_TIMEOUT + description: need_des + addressOffset: 436 + size: 32 + resetValue: 131071 + fields: + - name: EN + description: set this field to 1 to enable lp core ibus timeout handle + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: THRES + description: This field used to set lp core ibus timeout threshold + bitOffset: 1 + bitWidth: 16 + access: read-write + - register: + name: LP_CORE_DBUS_TIMEOUT + description: need_des + addressOffset: 440 + size: 32 + resetValue: 131071 + fields: + - name: EN + description: set this field to 1 to enable lp core dbus timeout handle + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: THRES + description: This field used to set lp core dbus timeout threshold + bitOffset: 1 + bitWidth: 16 + access: read-write + - register: + name: LP_CORE_ERR_RESP_DIS + description: need_des + addressOffset: 444 + size: 32 + fields: + - name: LP_CORE_ERR_RESP_DIS + description: Set bit0 to disable ibus err resp;Set bit1 to disable dbus err resp; Set bit 2 to disable ahb err resp. + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: RNG_CFG + description: rng cfg register + addressOffset: 448 + size: 32 + resetValue: 3 + fields: + - name: RNG_TIMER_EN + description: enable rng timer + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RNG_TIMER_PSCALE + description: configure ng timer pscale + bitOffset: 1 + bitWidth: 8 + access: read-write + - name: RNG_SAR_ENABLE + description: enable rng_saradc + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RNG_SAR_DATA + description: debug rng sar sample cnt + bitOffset: 16 + bitWidth: 13 + access: read-only + - name: LP_ANA_PERI + description: LP_ANA_PERI Peripheral + groupName: LP_ANA_PERI + baseAddress: 1343303680 + addressBlock: + - offset: 0 + size: 320 + usage: registers + interrupt: + - name: LP_ANA + value: 8 + registers: + - register: + name: LP_ANA_BOD_MODE0_CNTL + description: need_des + addressOffset: 0 + size: 32 + resetValue: 268173568 + fields: + - name: LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA + description: need_des + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: LP_ANA_BOD_MODE0_PD_RF_ENA + description: need_des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: LP_ANA_BOD_MODE0_INTR_WAIT + description: need_des + bitOffset: 8 + bitWidth: 10 + access: read-write + - name: LP_ANA_BOD_MODE0_RESET_WAIT + description: need_des + bitOffset: 18 + bitWidth: 10 + access: read-write + - name: LP_ANA_BOD_MODE0_CNT_CLR + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_ANA_BOD_MODE0_INTR_ENA + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LP_ANA_BOD_MODE0_RESET_SEL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_ANA_BOD_MODE0_RESET_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_ANA_BOD_MODE1_CNTL + description: need_des + addressOffset: 4 + size: 32 + fields: + - name: LP_ANA_BOD_MODE1_RESET_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_ANA_VDD_SOURCE_CNTL + description: need_des + addressOffset: 8 + size: 32 + resetValue: 67109119 + fields: + - name: LP_ANA_DETMODE_SEL + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: LP_ANA_VGOOD_EVENT_RECORD + description: need_des + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: LP_ANA_VBAT_EVENT_RECORD_CLR + description: need_des + bitOffset: 16 + bitWidth: 8 + access: write-only + - name: LP_ANA_BOD_SOURCE_ENA + description: need_des + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: LP_ANA_VDDBAT_BOD_CNTL + description: need_des + addressOffset: 12 + size: 32 + resetValue: 4290772992 + fields: + - name: LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: LP_ANA_VDDBAT_CHARGER + description: need_des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: LP_ANA_VDDBAT_CNT_CLR + description: need_des + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: LP_ANA_VDDBAT_UPVOLTAGE_TARGET + description: need_des + bitOffset: 12 + bitWidth: 10 + access: read-write + - name: LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET + description: need_des + bitOffset: 22 + bitWidth: 10 + access: read-write + - register: + name: LP_ANA_VDDBAT_CHARGE_CNTL + description: need_des + addressOffset: 16 + size: 32 + resetValue: 4290772992 + fields: + - name: LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: LP_ANA_VDDBAT_CHARGE_CHARGER + description: need_des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: LP_ANA_VDDBAT_CHARGE_CNT_CLR + description: need_des + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET + description: need_des + bitOffset: 12 + bitWidth: 10 + access: read-write + - name: LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET + description: need_des + bitOffset: 22 + bitWidth: 10 + access: read-write + - register: + name: LP_ANA_CK_GLITCH_CNTL + description: need_des + addressOffset: 20 + size: 32 + fields: + - name: LP_ANA_CK_GLITCH_RESET_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_ANA_PG_GLITCH_CNTL + description: need_des + addressOffset: 24 + size: 32 + fields: + - name: LP_ANA_POWER_GLITCH_RESET_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_ANA_FIB_ENABLE + description: need_des + addressOffset: 28 + size: 32 + resetValue: 4294967295 + fields: + - name: LP_ANA_ANA_FIB_ENA + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_ANA_INT_RAW + description: need_des + addressOffset: 32 + size: 32 + fields: + - name: LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_ANA_BOD_MODE0_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_ANA_INT_ST + description: need_des + addressOffset: 36 + size: 32 + fields: + - name: LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: LP_ANA_VDDBAT_UPVOLTAGE_INT_ST + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: LP_ANA_BOD_MODE0_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: LP_ANA_INT_ENA + description: need_des + addressOffset: 40 + size: 32 + fields: + - name: LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_ANA_BOD_MODE0_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_ANA_INT_CLR + description: need_des + addressOffset: 44 + size: 32 + fields: + - name: LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR + description: need_des + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: LP_ANA_BOD_MODE0_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: LP_ANA_LP_INT_RAW + description: need_des + addressOffset: 48 + size: 32 + fields: + - name: LP_ANA_BOD_MODE0_LP_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_ANA_LP_INT_ST + description: need_des + addressOffset: 52 + size: 32 + fields: + - name: LP_ANA_BOD_MODE0_LP_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: LP_ANA_LP_INT_ENA + description: need_des + addressOffset: 56 + size: 32 + fields: + - name: LP_ANA_BOD_MODE0_LP_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_ANA_LP_INT_CLR + description: need_des + addressOffset: 60 + size: 32 + fields: + - name: LP_ANA_BOD_MODE0_LP_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: LP_ANA_TOUCH_APPROACH_WORK_MEAS_NUM + description: need_des + addressOffset: 252 + size: 32 + resetValue: 104960100 + fields: + - name: LP_ANA_TOUCH_APPROACH_MEAS_NUM2 + description: need_des + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: LP_ANA_TOUCH_APPROACH_MEAS_NUM1 + description: need_des + bitOffset: 10 + bitWidth: 10 + access: read-write + - name: LP_ANA_TOUCH_APPROACH_MEAS_NUM0 + description: need_des + bitOffset: 20 + bitWidth: 10 + access: read-write + - register: + name: LP_ANA_TOUCH_SCAN_CTRL1 + description: need_des + addressOffset: 256 + size: 32 + resetValue: 524288 + fields: + - name: LP_ANA_TOUCH_SHIELD_PAD_EN + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LP_ANA_TOUCH_INACTIVE_CONNECTION + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: LP_ANA_TOUCH_SCAN_PAD_MAP + description: need_des + bitOffset: 2 + bitWidth: 15 + access: read-write + - name: LP_ANA_TOUCH_XPD_WAIT + description: need_des + bitOffset: 17 + bitWidth: 15 + access: read-write + - register: + name: LP_ANA_TOUCH_SCAN_CTRL2 + description: need_des + addressOffset: 260 + size: 32 + resetValue: 935329728 + fields: + - name: LP_ANA_TOUCH_TIMEOUT_NUM + description: need_des + bitOffset: 6 + bitWidth: 16 + access: read-write + - name: LP_ANA_TOUCH_TIMEOUT_EN + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: LP_ANA_TOUCH_OUT_RING + description: need_des + bitOffset: 23 + bitWidth: 4 + access: read-write + - name: LP_ANA_FREQ_SCAN_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LP_ANA_FREQ_SCAN_CNT_LIMIT + description: need_des + bitOffset: 28 + bitWidth: 2 + access: read-write + - register: + name: LP_ANA_TOUCH_WORK + description: need_des + addressOffset: 264 + size: 32 + fields: + - name: LP_ANA_DIV_NUM2 + description: need_des + bitOffset: 16 + bitWidth: 3 + access: read-write + - name: LP_ANA_DIV_NUM1 + description: need_des + bitOffset: 19 + bitWidth: 3 + access: read-write + - name: LP_ANA_DIV_NUM0 + description: need_des + bitOffset: 22 + bitWidth: 3 + access: read-write + - name: LP_ANA_TOUCH_OUT_SEL + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LP_ANA_TOUCH_OUT_RESET + description: need_des + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: LP_ANA_TOUCH_OUT_GATE + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: LP_ANA_TOUCH_WORK_MEAS_NUM + description: need_des + addressOffset: 268 + size: 32 + resetValue: 104960100 + fields: + - name: LP_ANA_TOUCH_MEAS_NUM2 + description: need_des + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: LP_ANA_TOUCH_MEAS_NUM1 + description: need_des + bitOffset: 10 + bitWidth: 10 + access: read-write + - name: LP_ANA_TOUCH_MEAS_NUM0 + description: need_des + bitOffset: 20 + bitWidth: 10 + access: read-write + - register: + name: LP_ANA_TOUCH_FILTER1 + description: need_des + addressOffset: 272 + size: 32 + resetValue: 1779040768 + fields: + - name: LP_ANA_TOUCH_NEG_NOISE_DISUPDATE_BASELINE_EN + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LP_ANA_TOUCH_HYSTERESIS + description: need_des + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: LP_ANA_TOUCH_NEG_NOISE_THRES + description: need_des + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: LP_ANA_TOUCH_NOISE_THRES + description: need_des + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: LP_ANA_TOUCH_SMOOTH_LVL + description: need_des + bitOffset: 7 + bitWidth: 2 + access: read-write + - name: LP_ANA_TOUCH_JITTER_STEP + description: need_des + bitOffset: 9 + bitWidth: 4 + access: read-write + - name: LP_ANA_TOUCH_FILTER_MODE + description: need_des + bitOffset: 13 + bitWidth: 3 + access: read-write + - name: LP_ANA_TOUCH_FILTER_EN + description: need_des + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: LP_ANA_TOUCH_NEG_NOISE_LIMIT + description: need_des + bitOffset: 17 + bitWidth: 4 + access: read-write + - name: LP_ANA_TOUCH_APPROACH_LIMIT + description: need_des + bitOffset: 21 + bitWidth: 8 + access: read-write + - name: LP_ANA_TOUCH_DEBOUNCE_LIMIT + description: need_des + bitOffset: 29 + bitWidth: 3 + access: read-write + - register: + name: LP_ANA_TOUCH_FILTER2 + description: need_des + addressOffset: 276 + size: 32 + resetValue: 536838144 + fields: + - name: LP_ANA_TOUCH_OUTEN + description: need_des + bitOffset: 15 + bitWidth: 15 + access: read-write + - name: LP_ANA_TOUCH_BYPASS_NOISE_THRES + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_ANA_TOUCH_BYPASS_NEG_NOISE_THRES + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_ANA_TOUCH_FILTER3 + description: need_des + addressOffset: 280 + size: 32 + fields: + - name: LP_ANA_TOUCH_BASELINE_SW + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: LP_ANA_TOUCH_UPDATE_BASELINE_SW + description: need_des + bitOffset: 16 + bitWidth: 1 + access: write-only + - register: + name: LP_ANA_TOUCH_SLP0 + description: need_des + addressOffset: 284 + size: 32 + resetValue: 1966080 + fields: + - name: LP_ANA_TOUCH_SLP_TH0 + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: LP_ANA_TOUCH_SLP_CHANNEL_CLR + description: need_des + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: LP_ANA_TOUCH_SLP_PAD + description: need_des + bitOffset: 17 + bitWidth: 4 + access: read-write + - register: + name: LP_ANA_TOUCH_SLP1 + description: need_des + addressOffset: 288 + size: 32 + fields: + - name: LP_ANA_TOUCH_SLP_TH2 + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: LP_ANA_TOUCH_SLP_TH1 + description: need_des + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_CLR + description: need_des + addressOffset: 292 + size: 32 + fields: + - name: LP_ANA_TOUCH_CHANNEL_CLR + description: need_des + bitOffset: 0 + bitWidth: 15 + access: write-only + - name: LP_ANA_TOUCH_STATUS_CLR + description: need_des + bitOffset: 15 + bitWidth: 1 + access: write-only + - register: + name: LP_ANA_TOUCH_APPROACH + description: need_des + addressOffset: 296 + size: 32 + resetValue: 4095 + fields: + - name: PAD0 + description: need_des + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: PAD1 + description: need_des + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: PAD2 + description: need_des + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: LP_ANA_TOUCH_SLP_APPROACH_EN + description: need_des + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: LP_ANA_TOUCH_FREQ0_SCAN_PARA + description: need_des + addressOffset: 300 + size: 32 + fields: + - name: LP_ANA_TOUCH_FREQ0_DCAP_LPF + description: need_des + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: LP_ANA_TOUCH_FREQ0_DRES_LPF + description: need_des + bitOffset: 7 + bitWidth: 2 + access: read-write + - name: LP_ANA_TOUCH_FREQ0_DRV_LS + description: need_des + bitOffset: 9 + bitWidth: 4 + access: read-write + - name: LP_ANA_TOUCH_FREQ0_DRV_HS + description: need_des + bitOffset: 13 + bitWidth: 5 + access: read-write + - name: LP_ANA_TOUCH_FREQ0_DBIAS + description: need_des + bitOffset: 18 + bitWidth: 5 + access: read-write + - register: + name: LP_ANA_TOUCH_FREQ1_SCAN_PARA + description: need_des + addressOffset: 304 + size: 32 + fields: + - name: LP_ANA_TOUCH_FREQ1_DCAP_LPF + description: need_des + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: LP_ANA_TOUCH_FREQ1_DRES_LPF + description: need_des + bitOffset: 7 + bitWidth: 2 + access: read-write + - name: LP_ANA_TOUCH_FREQ1_DRV_LS + description: need_des + bitOffset: 9 + bitWidth: 4 + access: read-write + - name: LP_ANA_TOUCH_FREQ1_DRV_HS + description: need_des + bitOffset: 13 + bitWidth: 5 + access: read-write + - name: LP_ANA_TOUCH_FREQ1_DBIAS + description: need_des + bitOffset: 18 + bitWidth: 5 + access: read-write + - register: + name: LP_ANA_TOUCH_FREQ2_SCAN_PARA + description: need_des + addressOffset: 308 + size: 32 + fields: + - name: LP_ANA_TOUCH_FREQ2_DCAP_LPF + description: need_des + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: LP_ANA_TOUCH_FREQ2_DRES_LPF + description: need_des + bitOffset: 7 + bitWidth: 2 + access: read-write + - name: LP_ANA_TOUCH_FREQ2_DRV_LS + description: need_des + bitOffset: 9 + bitWidth: 4 + access: read-write + - name: LP_ANA_TOUCH_FREQ2_DRV_HS + description: need_des + bitOffset: 13 + bitWidth: 5 + access: read-write + - name: LP_ANA_TOUCH_FREQ2_DBIAS + description: need_des + bitOffset: 18 + bitWidth: 5 + access: read-write + - register: + name: LP_ANA_TOUCH_ANA_PARA + description: need_des + addressOffset: 312 + size: 32 + fields: + - name: LP_ANA_TOUCH_TOUCH_BUF_DRV + description: need_des + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: LP_ANA_TOUCH_TOUCH_EN_CAL + description: need_des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: LP_ANA_TOUCH_TOUCH_DCAP_CAL + description: need_des + bitOffset: 4 + bitWidth: 7 + access: read-write + - register: + name: LP_ANA_TOUCH_MUX0 + description: need_des + addressOffset: 316 + size: 32 + resetValue: 536870912 + fields: + - name: LP_ANA_TOUCH_DATA_SEL + description: need_des + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: LP_ANA_TOUCH_FREQ_SEL + description: need_des + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: LP_ANA_TOUCH_BUFSEL + description: need_des + bitOffset: 12 + bitWidth: 15 + access: read-write + - name: LP_ANA_TOUCH_DONE_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LP_ANA_TOUCH_DONE_FORCE + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_ANA_TOUCH_FSM_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LP_ANA_TOUCH_START_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_ANA_TOUCH_START_FORCE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_ANA_TOUCH_MUX1 + description: need_des + addressOffset: 320 + size: 32 + fields: + - name: LP_ANA_TOUCH_START + description: need_des + bitOffset: 0 + bitWidth: 15 + access: read-write + - name: LP_ANA_TOUCH_XPD + description: need_des + bitOffset: 15 + bitWidth: 15 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD0_TH0 + description: need_des + addressOffset: 324 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD0_TH0 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD0_TH1 + description: need_des + addressOffset: 328 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD0_TH1 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD0_TH2 + description: need_des + addressOffset: 332 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD0_TH2 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD1_TH0 + description: need_des + addressOffset: 336 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD1_TH0 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD1_TH1 + description: need_des + addressOffset: 340 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD1_TH1 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD1_TH2 + description: need_des + addressOffset: 344 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD1_TH2 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD2_TH0 + description: need_des + addressOffset: 348 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD2_TH0 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD2_TH1 + description: need_des + addressOffset: 352 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD2_TH1 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD2_TH2 + description: need_des + addressOffset: 356 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD2_TH2 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD3_TH0 + description: need_des + addressOffset: 360 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD3_TH0 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD3_TH1 + description: need_des + addressOffset: 364 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD3_TH1 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD3_TH2 + description: need_des + addressOffset: 368 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD3_TH2 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD4_TH0 + description: need_des + addressOffset: 372 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD4_TH0 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD4_TH1 + description: need_des + addressOffset: 376 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD4_TH1 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD4_TH2 + description: need_des + addressOffset: 380 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD4_TH2 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD5_TH0 + description: need_des + addressOffset: 384 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD5_TH0 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD5_TH1 + description: need_des + addressOffset: 388 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD5_TH1 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD5_TH2 + description: need_des + addressOffset: 392 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD5_TH2 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD6_TH0 + description: need_des + addressOffset: 396 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD6_TH0 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD6_TH1 + description: need_des + addressOffset: 400 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD6_TH1 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD6_TH2 + description: need_des + addressOffset: 404 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD6_TH2 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD7_TH0 + description: need_des + addressOffset: 408 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD7_TH0 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD7_TH1 + description: need_des + addressOffset: 412 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD7_TH1 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD7_TH2 + description: need_des + addressOffset: 416 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD7_TH2 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD8_TH0 + description: need_des + addressOffset: 420 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD8_TH0 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD8_TH1 + description: need_des + addressOffset: 424 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD8_TH1 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD8_TH2 + description: need_des + addressOffset: 428 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD8_TH2 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD9_TH0 + description: need_des + addressOffset: 432 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD9_TH0 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD9_TH1 + description: need_des + addressOffset: 436 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD9_TH1 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD9_TH2 + description: need_des + addressOffset: 440 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD9_TH2 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD10_TH0 + description: need_des + addressOffset: 444 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD10_TH0 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD10_TH1 + description: need_des + addressOffset: 448 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD10_TH1 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD10_TH2 + description: need_des + addressOffset: 452 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD10_TH2 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD11_TH0 + description: need_des + addressOffset: 456 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD11_TH0 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD11_TH1 + description: need_des + addressOffset: 460 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD11_TH1 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD11_TH2 + description: need_des + addressOffset: 464 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD11_TH2 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD12_TH0 + description: need_des + addressOffset: 468 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD12_TH0 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD12_TH1 + description: need_des + addressOffset: 472 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD12_TH1 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD12_TH2 + description: need_des + addressOffset: 476 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD12_TH2 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD13_TH0 + description: need_des + addressOffset: 480 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD13_TH0 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD13_TH1 + description: need_des + addressOffset: 484 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD13_TH1 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD13_TH2 + description: need_des + addressOffset: 488 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD13_TH2 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD14_TH0 + description: need_des + addressOffset: 492 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD14_TH0 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD14_TH1 + description: need_des + addressOffset: 496 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD14_TH1 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_TOUCH_PAD14_TH2 + description: need_des + addressOffset: 500 + size: 32 + fields: + - name: LP_ANA_TOUCH_PAD14_TH2 + description: Reserved + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: LP_ANA_DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 2294816 + fields: + - name: LP_ANA_LP_ANA_DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: LP_ANA_CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: LP_AON_CLKRST + description: LP_AON_CLKRST Peripheral + groupName: LP_AON_CLKRST + baseAddress: 1343295488 + addressBlock: + - offset: 0 + size: 84 + usage: registers + registers: + - register: + name: LP_AONCLKRST_LP_CLK_CONF + description: need_des + addressOffset: 0 + size: 32 + resetValue: 4 + fields: + - name: LP_AONCLKRST_SLOW_CLK_SEL + description: need_des + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: LP_AONCLKRST_FAST_CLK_SEL + description: need_des + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: LP_AONCLKRST_LP_PERI_DIV_NUM + description: need_des + bitOffset: 4 + bitWidth: 6 + access: read-write + - name: LP_AONCLKRST_ANA_SEL_REF_PLL8M + description: need_des + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: LP_AONCLKRST_LP_CLK_PO_EN + description: need_des + addressOffset: 4 + size: 32 + fields: + - name: LP_AONCLKRST_CLK_CORE_EFUSE_OEN + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_CLK_LP_BUS_OEN + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_CLK_AON_SLOW_OEN + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_CLK_AON_FAST_OEN + description: need_des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_CLK_SLOW_OEN + description: need_des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_CLK_FAST_OEN + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_CLK_FOSC_OEN + description: need_des + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_CLK_RC32K_OEN + description: need_des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_CLK_SXTAL_OEN + description: need_des + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_CLK_SOSC_OEN + description: "1'b1: probe sosc clk on\n1'b0: probe sosc clk off" + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: LP_AONCLKRST_LP_CLK_EN + description: need_des + addressOffset: 8 + size: 32 + resetValue: 134217728 + fields: + - name: LP_AONCLKRST_LP_RTC_XTAL_FORCE_ON + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_CK_EN_LP_RAM + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_ETM_EVENT_TICK_EN + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_PLL8M_CLK_FORCE_ON + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_XTAL_CLK_FORCE_ON + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_FOSC_CLK_FORCE_ON + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_AONCLKRST_LP_RST_EN + description: need_des + addressOffset: 12 + size: 32 + fields: + - name: LP_AONCLKRST_RST_EN_LP_HUK + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_RST_EN_LP_ANAPERI + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_RST_EN_LP_WDT + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_RST_EN_LP_TIMER + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_RST_EN_LP_RTC + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_RST_EN_LP_MAILBOX + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_RST_EN_LP_AONEFUSEREG + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_RST_EN_LP_RAM + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_AONCLKRST_RESET_CAUSE + description: need_des + addressOffset: 16 + size: 32 + resetValue: 33554432 + fields: + - name: LP_AONCLKRST_LPCORE_RESET_CAUSE + description: "6'h1: POR reset\n6'h9: PMU LP PERI power down reset\n6'ha: PMU LP CPU reset\n6'hf: brown out reset\n6'h10: LP watchdog chip reset\n6'h12: super watch dog reset\n6'h13: glitch reset\n6'h14: software reset" + bitOffset: 0 + bitWidth: 6 + access: read-only + - name: LP_AONCLKRST_LPCORE_RESET_FLAG + description: need_des + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: LP_AONCLKRST_HPCORE0_RESET_CAUSE + description: "6'h1: POR reset\n6'h3: digital system software reset\n6'h5: PMU HP system power down reset\n6'h7: HP system reset from HP watchdog\n6'h9: HP system reset from LP watchdog\n6'hb: HP core reset from HP watchdog\n6'hc: HP core software reset\n6'hd: HP core reset from LP watchdog\n6'hf: brown out reset\n6'h10: LP watchdog chip reset\n6'h12: super watch dog reset\n6'h13: glitch reset\n6'h14: efuse crc error reset\n6'h16: HP usb jtag chip reset\n6'h17: HP usb uart chip reset\n6'h18: HP jtag reset\n6'h1a: HP core lockup" + bitOffset: 7 + bitWidth: 6 + access: read-only + - name: LP_AONCLKRST_HPCORE0_RESET_FLAG + description: need_des + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: LP_AONCLKRST_HPCORE1_RESET_CAUSE + description: "6'h1: POR reset\n6'h3: digital system software reset\n6'h5: PMU HP system power down reset\n6'h7: HP system reset from HP watchdog\n6'h9: HP system reset from LP watchdog\n6'hb: HP core reset from HP watchdog\n6'hc: HP core software reset\n6'hd: HP core reset from LP watchdog\n6'hf: brown out reset\n6'h10: LP watchdog chip reset\n6'h12: super watch dog reset\n6'h13: glitch reset\n6'h14: efuse crc error reset\n6'h16: HP usb jtag chip reset\n6'h17: HP usb uart chip reset\n6'h18: HP jtag reset\n6'h1a: HP core lockup" + bitOffset: 14 + bitWidth: 6 + access: read-only + - name: LP_AONCLKRST_HPCORE1_RESET_FLAG + description: need_des + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: LP_AONCLKRST_LPCORE_RESET_CAUSE_PMU_LP_CPU_MASK + description: "1'b0: enable lpcore pmu_lp_cpu_reset reset_cause, 1'b1: disable lpcore pmu_lp_cpu_reset reset_cause" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_LPCORE_RESET_CAUSE_CLR + description: need_des + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: LP_AONCLKRST_LPCORE_RESET_FLAG_CLR + description: need_des + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: LP_AONCLKRST_HPCORE0_RESET_CAUSE_CLR + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: LP_AONCLKRST_HPCORE0_RESET_FLAG_CLR + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: LP_AONCLKRST_HPCORE1_RESET_CAUSE_CLR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: LP_AONCLKRST_HPCORE1_RESET_FLAG_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: LP_AONCLKRST_HPCPU_RESET_CTRL0 + description: need_des + addressOffset: 20 + size: 32 + resetValue: 2147647490 + fields: + - name: LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN + description: "write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup reset feature" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH + description: need_des + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN + description: "write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset hpcore0 feature" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HPCORE0_STALL_WAIT + description: need_des + bitOffset: 5 + bitWidth: 7 + access: read-write + - name: LP_AONCLKRST_HPCORE0_STALL_EN + description: need_des + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HPCORE0_SW_RESET + description: need_des + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET + description: need_des + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL + description: "1'b1: boot from HP TCM ROM: 0x4FC00000\n1'b0: boot from LP TCM RAM: 0x50108000" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN + description: "write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup reset feature" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH + description: need_des + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN + description: "write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset hpcore1 feature" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HPCORE1_STALL_WAIT + description: need_des + bitOffset: 21 + bitWidth: 7 + access: read-write + - name: LP_AONCLKRST_HPCORE1_STALL_EN + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HPCORE1_SW_RESET + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL + description: "1'b1: boot from HP TCM ROM: 0x4FC00000\n1'b0: boot from LP TCM RAM: 0x50108000" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_AONCLKRST_HPCPU_RESET_CTRL1 + description: need_des + addressOffset: 24 + size: 32 + fields: + - name: LP_AONCLKRST_HPCORE0_SW_STALL_CODE + description: "HP core0 software stall when set to 8'h86" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: LP_AONCLKRST_HPCORE1_SW_STALL_CODE + description: "HP core1 software stall when set to 8'h86" + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: LP_AONCLKRST_FOSC_CNTL + description: need_des + addressOffset: 28 + size: 32 + resetValue: 1677721600 + fields: + - name: LP_AONCLKRST_FOSC_DFREQ + description: need_des + bitOffset: 22 + bitWidth: 10 + access: read-write + - register: + name: LP_AONCLKRST_RC32K_CNTL + description: need_des + addressOffset: 32 + size: 32 + resetValue: 650 + fields: + - name: LP_AONCLKRST_RC32K_DFREQ + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_AONCLKRST_SOSC_CNTL + description: need_des + addressOffset: 36 + size: 32 + resetValue: 721420288 + fields: + - name: LP_AONCLKRST_SOSC_DFREQ + description: need_des + bitOffset: 22 + bitWidth: 10 + access: read-write + - register: + name: LP_AONCLKRST_CLK_TO_HP + description: need_des + addressOffset: 40 + size: 32 + resetValue: 4026531840 + fields: + - name: LP_AONCLKRST_ICG_HP_XTAL32K + description: reserved + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_ICG_HP_SOSC + description: reserved + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_ICG_HP_OSC32K + description: reserved + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_ICG_HP_FOSC + description: reserved + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_AONCLKRST_LPMEM_FORCE + description: need_des + addressOffset: 44 + size: 32 + fields: + - name: LP_AONCLKRST_LPMEM_CLK_FORCE_ON + description: reserved + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_AONCLKRST_XTAL32K + description: need_des + addressOffset: 48 + size: 32 + resetValue: 1723858944 + fields: + - name: LP_AONCLKRST_DRES_XTAL32K + description: need_des + bitOffset: 22 + bitWidth: 3 + access: read-write + - name: LP_AONCLKRST_DGM_XTAL32K + description: need_des + bitOffset: 25 + bitWidth: 3 + access: read-write + - name: LP_AONCLKRST_DBUF_XTAL32K + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_DAC_XTAL32K + description: need_des + bitOffset: 29 + bitWidth: 3 + access: read-write + - register: + name: LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS + description: need_des + addressOffset: 52 + size: 32 + resetValue: 4294967295 + fields: + - name: LP_AONCLKRST_MUX_HPSYS_RESET_BYPASS + description: reserved + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_AONCLKRST_HPSYS_0_RESET_BYPASS + description: need_des + addressOffset: 56 + size: 32 + resetValue: 4294967295 + fields: + - name: LP_AONCLKRST_HPSYS_0_RESET_BYPASS + description: reserved + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_AONCLKRST_HPSYS_APM_RESET_BYPASS + description: need_des + addressOffset: 60 + size: 32 + resetValue: 4294967295 + fields: + - name: LP_AONCLKRST_HPSYS_APM_RESET_BYPASS + description: reserved + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LP_AONCLKRST_HP_CLK_CTRL + description: HP Clock Control Register. + addressOffset: 64 + size: 32 + resetValue: 536870908 + fields: + - name: LP_AONCLKRST_HP_ROOT_CLK_SRC_SEL + description: "HP SoC Root Clock Source Select. 2'd0: xtal_40m, 2'd1: cpll_400m, 2'd2: fosc_20m." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: LP_AONCLKRST_HP_ROOT_CLK_EN + description: HP SoC Root Clock Enable. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_PAD_PARLIO_TX_CLK_EN + description: PARLIO TX Clock From Pad Enable. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_PAD_PARLIO_RX_CLK_EN + description: PARLIO RX Clock From Pad Enable. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_PAD_UART4_SLP_CLK_EN + description: UART4 SLP Clock From Pad Enable. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_PAD_UART3_SLP_CLK_EN + description: UART3 SLP Clock From Pad Enable. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_PAD_UART2_SLP_CLK_EN + description: UART2 SLP Clock From Pad Enable. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_PAD_UART1_SLP_CLK_EN + description: UART1 SLP Clock From Pad Enable. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_PAD_UART0_SLP_CLK_EN + description: UART0 SLP Clock From Pad Enable. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_PAD_I2S2_MCLK_EN + description: I2S2 MCLK Clock From Pad Enable. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_PAD_I2S1_MCLK_EN + description: I2S1 MCLK Clock From Pad Enable. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_PAD_I2S0_MCLK_EN + description: I2S0 MCLK Clock From Pad Enable. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_PAD_EMAC_TX_CLK_EN + description: EMAC RX Clock From Pad Enable. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_PAD_EMAC_RX_CLK_EN + description: EMAC TX Clock From Pad Enable. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_PAD_EMAC_TXRX_CLK_EN + description: EMAC TXRX Clock From Pad Enable. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_XTAL_32K_CLK_EN + description: XTAL 32K Clock Enable. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_RC_32K_CLK_EN + description: RC 32K Clock Enable. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_SOSC_150K_CLK_EN + description: SOSC 150K Clock Enable. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_PLL_8M_CLK_EN + description: PLL 8M Clock Enable. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_AUDIO_PLL_CLK_EN + description: AUDIO PLL Clock Enable. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_SDIO_PLL2_CLK_EN + description: SDIO PLL2 Clock Enable. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_SDIO_PLL1_CLK_EN + description: SDIO PLL1 Clock Enable. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_SDIO_PLL0_CLK_EN + description: SDIO PLL0 Clock Enable. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_FOSC_20M_CLK_EN + description: FOSC 20M Clock Enable. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_XTAL_40M_CLK_EN + description: XTAL 40M Clock Enalbe. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_CPLL_400M_CLK_EN + description: CPLL 400M Clock Enable. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_SPLL_480M_CLK_EN + description: SPLL 480M Clock Enable. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_HP_MPLL_500M_CLK_EN + description: MPLL 500M Clock Enable. + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: LP_AONCLKRST_HP_USB_CLKRST_CTRL0 + description: HP USB Clock Reset Control Register. + addressOffset: 68 + size: 32 + resetValue: 163889786 + fields: + - name: LP_AONCLKRST_USB_OTG20_SLEEP_MODE + description: unused. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_USB_OTG20_BK_SYS_CLK_EN + description: unused. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_USB_OTG11_SLEEP_MODE + description: unused. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_USB_OTG11_BK_SYS_CLK_EN + description: unused. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_USB_OTG11_48M_CLK_EN + description: usb otg11 fs phy clock enable. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_USB_DEVICE_48M_CLK_EN + description: usb device fs phy clock enable. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_USB_48M_DIV_NUM + description: usb 480m to 25m divide number. + bitOffset: 6 + bitWidth: 8 + access: read-write + - name: LP_AONCLKRST_USB_25M_DIV_NUM + description: usb 500m to 25m divide number. + bitOffset: 14 + bitWidth: 8 + access: read-write + - name: LP_AONCLKRST_USB_12M_DIV_NUM + description: usb 480m to 12m divide number. + bitOffset: 22 + bitWidth: 8 + access: read-write + - register: + name: LP_AONCLKRST_HP_USB_CLKRST_CTRL1 + description: HP USB Clock Reset Control Register. + addressOffset: 72 + size: 32 + resetValue: 3221225472 + fields: + - name: LP_AONCLKRST_RST_EN_USB_OTG20_ADP + description: usb otg20 adp reset en + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_RST_EN_USB_OTG20_PHY + description: usb otg20 phy reset en + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_RST_EN_USB_OTG20 + description: usb otg20 reset en + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_RST_EN_USB_OTG11 + description: usb org11 reset en + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_RST_EN_USB_DEVICE + description: usb device reset en + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_USB_OTG20_PHYREF_CLK_SRC_SEL + description: "usb otg20 hs phy src sel. 2'd0: 12m, 2'd1: 25m, 2'd2: pad_hsphy_refclk." + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: LP_AONCLKRST_USB_OTG20_PHYREF_CLK_EN + description: usb otg20 hs phy refclk enable. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_USB_OTG20_ULPI_CLK_EN + description: usb otg20 ulpi clock enable. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_AONCLKRST_HP_SDMMC_EMAC_RST_CTRL + description: need_des + addressOffset: 76 + size: 32 + fields: + - name: LP_AONCLKRST_RST_EN_SDMMC + description: hp sdmmc reset en + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_FORCE_NORST_SDMMC + description: hp sdmmc force norst + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_RST_EN_EMAC + description: hp emac reset en + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_AONCLKRST_FORCE_NORST_EMAC + description: hp emac force norst + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_AONCLKRST_DATE + description: need_des + addressOffset: 1020 + size: 32 + fields: + - name: LP_AONCLKRST_CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: LP_GPIO + description: Low-power General Purpose Input/Output + groupName: LP_GPIO + baseAddress: 1343397888 + addressBlock: + - offset: 0 + size: 236 + usage: registers + interrupt: + - name: LP_GPIO + value: 10 + registers: + - register: + name: CLK_EN + description: Reserved + addressOffset: 0 + size: 32 + resetValue: 1 + fields: + - name: REG_CLK_EN + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: VER_DATE + description: Reserved + addressOffset: 4 + size: 32 + resetValue: 2294563 + fields: + - name: REG_VER_DATE + description: Reserved + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + name: OUT + description: Reserved + addressOffset: 8 + size: 32 + fields: + - name: REG_GPIO_OUT_DATA + description: Reserved + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: OUT_W1TS + description: Reserved + addressOffset: 12 + size: 32 + fields: + - name: REG_GPIO_OUT_DATA_W1TS + description: Reserved + bitOffset: 0 + bitWidth: 16 + access: write-only + - register: + name: OUT_W1TC + description: Reserved + addressOffset: 16 + size: 32 + fields: + - name: REG_GPIO_OUT_DATA_W1TC + description: Reserved + bitOffset: 0 + bitWidth: 16 + access: write-only + - register: + name: ENABLE + description: Reserved + addressOffset: 20 + size: 32 + fields: + - name: REG_GPIO_ENABLE_DATA + description: Reserved + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: ENABLE_W1TS + description: Reserved + addressOffset: 24 + size: 32 + fields: + - name: REG_GPIO_ENABLE_DATA_W1TS + description: Reserved + bitOffset: 0 + bitWidth: 16 + access: write-only + - register: + name: ENABLE_W1TC + description: Reserved + addressOffset: 28 + size: 32 + fields: + - name: REG_GPIO_ENABLE_DATA_W1TC + description: Reserved + bitOffset: 0 + bitWidth: 16 + access: write-only + - register: + name: STATUS + description: Reserved + addressOffset: 32 + size: 32 + fields: + - name: REG_GPIO_STATUS_DATA + description: Reserved + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: STATUS_W1TS + description: Reserved + addressOffset: 36 + size: 32 + fields: + - name: REG_GPIO_STATUS_DATA_W1TS + description: Reserved + bitOffset: 0 + bitWidth: 16 + access: write-only + - register: + name: STATUS_W1TC + description: Reserved + addressOffset: 40 + size: 32 + fields: + - name: REG_GPIO_STATUS_DATA_W1TC + description: Reserved + bitOffset: 0 + bitWidth: 16 + access: write-only + - register: + name: STATUS_NEXT + description: Reserved + addressOffset: 44 + size: 32 + fields: + - name: REG_GPIO_STATUS_INTERRUPT_NEXT + description: Reserved + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: IN + description: Reserved + addressOffset: 48 + size: 32 + fields: + - name: REG_GPIO_IN_DATA_NEXT + description: Reserved + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: PIN0 + description: Reserved + addressOffset: 52 + size: 32 + fields: + - name: REG_GPIO_PIN0_WAKEUP_ENABLE + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_PIN0_INT_TYPE + description: Reserved + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: REG_GPIO_PIN0_PAD_DRIVER + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_GPIO_PIN0_EDGE_WAKEUP_CLR + description: need des + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: PIN1 + description: Reserved + addressOffset: 56 + size: 32 + fields: + - name: REG_GPIO_PIN1_WAKEUP_ENABLE + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_PIN1_INT_TYPE + description: Reserved + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: REG_GPIO_PIN1_PAD_DRIVER + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_GPI1_PIN0_EDGE_WAKEUP_CLR + description: need des + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: PIN2 + description: Reserved + addressOffset: 60 + size: 32 + fields: + - name: REG_GPIO_PIN2_WAKEUP_ENABLE + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_PIN2_INT_TYPE + description: Reserved + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: REG_GPIO_PIN2_PAD_DRIVER + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_GPI2_PIN0_EDGE_WAKEUP_CLR + description: need des + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: PIN3 + description: Reserved + addressOffset: 64 + size: 32 + fields: + - name: REG_GPIO_PIN3_WAKEUP_ENABLE + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_PIN3_INT_TYPE + description: Reserved + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: REG_GPIO_PIN3_PAD_DRIVER + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_GPI3_PIN0_EDGE_WAKEUP_CLR + description: need des + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: PIN4 + description: Reserved + addressOffset: 68 + size: 32 + fields: + - name: REG_GPIO_PIN4_WAKEUP_ENABLE + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_PIN4_INT_TYPE + description: Reserved + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: REG_GPIO_PIN4_PAD_DRIVER + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_GPI4_PIN0_EDGE_WAKEUP_CLR + description: need des + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: PIN5 + description: Reserved + addressOffset: 72 + size: 32 + fields: + - name: REG_GPIO_PIN5_WAKEUP_ENABLE + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_PIN5_INT_TYPE + description: Reserved + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: REG_GPIO_PIN5_PAD_DRIVER + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_GPI5_PIN0_EDGE_WAKEUP_CLR + description: need des + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: PIN6 + description: Reserved + addressOffset: 76 + size: 32 + fields: + - name: REG_GPIO_PIN6_WAKEUP_ENABLE + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_PIN6_INT_TYPE + description: Reserved + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: REG_GPIO_PIN6_PAD_DRIVER + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_GPI6_PIN0_EDGE_WAKEUP_CLR + description: need des + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: PIN7 + description: Reserved + addressOffset: 80 + size: 32 + fields: + - name: REG_GPIO_PIN7_WAKEUP_ENABLE + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_PIN7_INT_TYPE + description: Reserved + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: REG_GPIO_PIN7_PAD_DRIVER + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_GPI7_PIN0_EDGE_WAKEUP_CLR + description: need des + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: PIN8 + description: Reserved + addressOffset: 84 + size: 32 + fields: + - name: REG_GPIO_PIN8_WAKEUP_ENABLE + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_PIN8_INT_TYPE + description: Reserved + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: REG_GPIO_PIN8_PAD_DRIVER + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_GPI8_PIN0_EDGE_WAKEUP_CLR + description: need des + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: PIN9 + description: Reserved + addressOffset: 88 + size: 32 + fields: + - name: REG_GPIO_PIN9_WAKEUP_ENABLE + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_PIN9_INT_TYPE + description: Reserved + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: REG_GPIO_PIN9_PAD_DRIVER + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_GPI9_PIN0_EDGE_WAKEUP_CLR + description: need des + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: PIN10 + description: Reserved + addressOffset: 92 + size: 32 + fields: + - name: REG_GPIO_PIN10_WAKEUP_ENABLE + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_PIN10_INT_TYPE + description: Reserved + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: REG_GPIO_PIN10_PAD_DRIVER + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_GPI10_PIN0_EDGE_WAKEUP_CLR + description: need des + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: PIN11 + description: Reserved + addressOffset: 96 + size: 32 + fields: + - name: REG_GPIO_PIN11_WAKEUP_ENABLE + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_PIN11_INT_TYPE + description: Reserved + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: REG_GPIO_PIN11_PAD_DRIVER + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_GPI11_PIN0_EDGE_WAKEUP_CLR + description: need des + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: PIN12 + description: Reserved + addressOffset: 100 + size: 32 + fields: + - name: REG_GPIO_PIN12_WAKEUP_ENABLE + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_PIN12_INT_TYPE + description: Reserved + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: REG_GPIO_PIN12_PAD_DRIVER + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_GPI12_PIN0_EDGE_WAKEUP_CLR + description: need des + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: PIN13 + description: Reserved + addressOffset: 104 + size: 32 + fields: + - name: REG_GPIO_PIN13_WAKEUP_ENABLE + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_PIN13_INT_TYPE + description: Reserved + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: REG_GPIO_PIN13_PAD_DRIVER + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_GPI13_PIN0_EDGE_WAKEUP_CLR + description: need des + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: PIN14 + description: Reserved + addressOffset: 108 + size: 32 + fields: + - name: REG_GPIO_PIN14_WAKEUP_ENABLE + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_PIN14_INT_TYPE + description: Reserved + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: REG_GPIO_PIN14_PAD_DRIVER + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_GPI14_PIN0_EDGE_WAKEUP_CLR + description: need des + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: PIN15 + description: Reserved + addressOffset: 112 + size: 32 + fields: + - name: REG_GPIO_PIN15_WAKEUP_ENABLE + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_PIN15_INT_TYPE + description: Reserved + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: REG_GPIO_PIN15_PAD_DRIVER + description: Reserved + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_GPI15_PIN0_EDGE_WAKEUP_CLR + description: need des + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: FUNC0_IN_SEL_CFG + description: Reserved + addressOffset: 116 + size: 32 + resetValue: 192 + fields: + - name: REG_GPIO_FUNC0_IN_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_SIG0_IN_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC0_IN_SEL + description: "reg_gpio_func0_in_sel[5:4]==2'b11->constant 1,reg_gpio_func0_in_sel[5:4]==2'b10->constant 0" + bitOffset: 2 + bitWidth: 6 + access: read-write + - register: + name: FUNC1_IN_SEL_CFG + description: Reserved + addressOffset: 120 + size: 32 + resetValue: 192 + fields: + - name: REG_GPIO_FUNC1_IN_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_SIG1_IN_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC1_IN_SEL + description: Reserved + bitOffset: 2 + bitWidth: 6 + access: read-write + - register: + name: FUNC2_IN_SEL_CFG + description: Reserved + addressOffset: 124 + size: 32 + resetValue: 128 + fields: + - name: REG_GPIO_FUNC2_IN_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_SIG2_IN_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC2_IN_SEL + description: Reserved + bitOffset: 2 + bitWidth: 6 + access: read-write + - register: + name: FUNC3_IN_SEL_CFG + description: Reserved + addressOffset: 128 + size: 32 + resetValue: 192 + fields: + - name: REG_GPIO_FUNC3_IN_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_SIG3_IN_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC3_IN_SEL + description: Reserved + bitOffset: 2 + bitWidth: 6 + access: read-write + - register: + name: FUNC4_IN_SEL_CFG + description: Reserved + addressOffset: 132 + size: 32 + resetValue: 192 + fields: + - name: REG_GPIO_FUNC4_IN_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_SIG4_IN_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC4_IN_SEL + description: Reserved + bitOffset: 2 + bitWidth: 6 + access: read-write + - register: + name: FUNC5_IN_SEL_CFG + description: Reserved + addressOffset: 136 + size: 32 + resetValue: 128 + fields: + - name: REG_GPIO_FUNC5_IN_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_SIG5_IN_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC5_IN_SEL + description: Reserved + bitOffset: 2 + bitWidth: 6 + access: read-write + - register: + name: FUNC6_IN_SEL_CFG + description: Reserved + addressOffset: 140 + size: 32 + resetValue: 128 + fields: + - name: REG_GPIO_FUNC6_IN_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_SIG6_IN_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC6_IN_SEL + description: Reserved + bitOffset: 2 + bitWidth: 6 + access: read-write + - register: + name: FUNC7_IN_SEL_CFG + description: Reserved + addressOffset: 144 + size: 32 + resetValue: 128 + fields: + - name: REG_GPIO_FUNC7_IN_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_SIG7_IN_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC7_IN_SEL + description: Reserved + bitOffset: 2 + bitWidth: 6 + access: read-write + - register: + name: FUNC8_IN_SEL_CFG + description: Reserved + addressOffset: 148 + size: 32 + resetValue: 128 + fields: + - name: REG_GPIO_FUNC8_IN_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_SIG8_IN_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC8_IN_SEL + description: Reserved + bitOffset: 2 + bitWidth: 6 + access: read-write + - register: + name: FUNC9_IN_SEL_CFG + description: Reserved + addressOffset: 152 + size: 32 + resetValue: 128 + fields: + - name: REG_GPIO_FUNC9_IN_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_SIG9_IN_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC9_IN_SEL + description: Reserved + bitOffset: 2 + bitWidth: 6 + access: read-write + - register: + name: FUNC10_IN_SEL_CFG + description: Reserved + addressOffset: 156 + size: 32 + resetValue: 128 + fields: + - name: REG_GPIO_FUNC10_IN_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_SIG10_IN_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC10_IN_SEL + description: Reserved + bitOffset: 2 + bitWidth: 6 + access: read-write + - register: + name: FUNC11_IN_SEL_CFG + description: Reserved + addressOffset: 160 + size: 32 + resetValue: 128 + fields: + - name: REG_GPIO_FUNC11_IN_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_SIG11_IN_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC11_IN_SEL + description: Reserved + bitOffset: 2 + bitWidth: 6 + access: read-write + - register: + name: FUNC12_IN_SEL_CFG + description: Reserved + addressOffset: 164 + size: 32 + resetValue: 128 + fields: + - name: REG_GPIO_FUNC12_IN_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_SIG12_IN_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC12_IN_SEL + description: Reserved + bitOffset: 2 + bitWidth: 6 + access: read-write + - register: + name: FUNC13_IN_SEL_CFG + description: Reserved + addressOffset: 168 + size: 32 + resetValue: 128 + fields: + - name: REG_GPIO_FUNC13_IN_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_SIG13_IN_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC13_IN_SEL + description: Reserved + bitOffset: 2 + bitWidth: 6 + access: read-write + - register: + name: FUNC0_OUT_SEL_CFG + description: Reserved + addressOffset: 244 + size: 32 + resetValue: 256 + fields: + - name: REG_GPIO_FUNC0_OE_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC0_OE_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC0_OUT_INV_SEL + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC0_OUT_SEL + description: "reg_gpio_func0_out_sel[5:1]==16 -> output gpio register value to pad" + bitOffset: 3 + bitWidth: 6 + access: read-write + - register: + name: FUNC1_OUT_SEL_CFG + description: Reserved + addressOffset: 248 + size: 32 + resetValue: 256 + fields: + - name: REG_GPIO_FUNC1_OE_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC1_OE_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC1_OUT_INV_SEL + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC1_OUT_SEL + description: Reserved + bitOffset: 3 + bitWidth: 6 + access: read-write + - register: + name: FUNC2_OUT_SEL_CFG + description: Reserved + addressOffset: 252 + size: 32 + resetValue: 256 + fields: + - name: REG_GPIO_FUNC2_OE_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC2_OE_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC2_OUT_INV_SEL + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC2_OUT_SEL + description: Reserved + bitOffset: 3 + bitWidth: 6 + access: read-write + - register: + name: FUNC3_OUT_SEL_CFG + description: Reserved + addressOffset: 256 + size: 32 + resetValue: 256 + fields: + - name: REG_GPIO_FUNC3_OE_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC3_OE_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC3_OUT_INV_SEL + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC3_OUT_SEL + description: Reserved + bitOffset: 3 + bitWidth: 6 + access: read-write + - register: + name: FUNC4_OUT_SEL_CFG + description: Reserved + addressOffset: 260 + size: 32 + resetValue: 256 + fields: + - name: REG_GPIO_FUNC4_OE_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC4_OE_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC4_OUT_INV_SEL + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC4_OUT_SEL + description: Reserved + bitOffset: 3 + bitWidth: 6 + access: read-write + - register: + name: FUNC5_OUT_SEL_CFG + description: Reserved + addressOffset: 264 + size: 32 + resetValue: 256 + fields: + - name: REG_GPIO_FUNC5_OE_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC5_OE_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC5_OUT_INV_SEL + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC5_OUT_SEL + description: Reserved + bitOffset: 3 + bitWidth: 6 + access: read-write + - register: + name: FUNC6_OUT_SEL_CFG + description: Reserved + addressOffset: 268 + size: 32 + resetValue: 256 + fields: + - name: REG_GPIO_FUNC6_OE_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC6_OE_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC6_OUT_INV_SEL + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC6_OUT_SEL + description: Reserved + bitOffset: 3 + bitWidth: 6 + access: read-write + - register: + name: FUNC7_OUT_SEL_CFG + description: Reserved + addressOffset: 272 + size: 32 + resetValue: 256 + fields: + - name: REG_GPIO_FUNC7_OE_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC7_OE_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC7_OUT_INV_SEL + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC7_OUT_SEL + description: Reserved + bitOffset: 3 + bitWidth: 6 + access: read-write + - register: + name: FUNC8_OUT_SEL_CFG + description: Reserved + addressOffset: 276 + size: 32 + resetValue: 256 + fields: + - name: REG_GPIO_FUNC8_OE_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC8_OE_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC8_OUT_INV_SEL + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC8_OUT_SEL + description: Reserved + bitOffset: 3 + bitWidth: 6 + access: read-write + - register: + name: FUNC9_OUT_SEL_CFG + description: Reserved + addressOffset: 280 + size: 32 + resetValue: 256 + fields: + - name: REG_GPIO_FUNC9_OE_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC9_OE_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC9_OUT_INV_SEL + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC9_OUT_SEL + description: Reserved + bitOffset: 3 + bitWidth: 6 + access: read-write + - register: + name: FUNC10_OUT_SEL_CFG + description: Reserved + addressOffset: 284 + size: 32 + resetValue: 256 + fields: + - name: REG_GPIO_FUNC10_OE_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC10_OE_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC10_OUT_INV_SEL + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC10_OUT_SEL + description: Reserved + bitOffset: 3 + bitWidth: 6 + access: read-write + - register: + name: FUNC11_OUT_SEL_CFG + description: Reserved + addressOffset: 288 + size: 32 + resetValue: 256 + fields: + - name: REG_GPIO_FUNC11_OE_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC11_OE_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC11_OUT_INV_SEL + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC11_OUT_SEL + description: Reserved + bitOffset: 3 + bitWidth: 6 + access: read-write + - register: + name: FUNC12_OUT_SEL_CFG + description: Reserved + addressOffset: 292 + size: 32 + resetValue: 256 + fields: + - name: REG_GPIO_FUNC12_OE_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC12_OE_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC12_OUT_INV_SEL + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC12_OUT_SEL + description: Reserved + bitOffset: 3 + bitWidth: 6 + access: read-write + - register: + name: FUNC13_OUT_SEL_CFG + description: Reserved + addressOffset: 296 + size: 32 + resetValue: 256 + fields: + - name: REG_GPIO_FUNC13_OE_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC13_OE_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC13_OUT_INV_SEL + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC13_OUT_SEL + description: Reserved + bitOffset: 3 + bitWidth: 6 + access: read-write + - register: + name: FUNC14_OUT_SEL_CFG + description: Reserved + addressOffset: 300 + size: 32 + resetValue: 256 + fields: + - name: REG_GPIO_FUNC14_OE_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC14_OE_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC14_OUT_INV_SEL + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC14_OUT_SEL + description: Reserved + bitOffset: 3 + bitWidth: 6 + access: read-write + - register: + name: FUNC15_OUT_SEL_CFG + description: Reserved + addressOffset: 304 + size: 32 + resetValue: 256 + fields: + - name: REG_GPIO_FUNC15_OE_INV_SEL + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC15_OE_SEL + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC15_OUT_INV_SEL + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_GPIO_FUNC15_OUT_SEL + description: Reserved + bitOffset: 3 + bitWidth: 6 + access: read-write + - name: LP_I2C0 + description: Low-power I2C (Inter-Integrated Circuit) Controller 0 + groupName: LP_I2C + baseAddress: 1343365120 + addressBlock: + - offset: 0 + size: 136 + usage: registers + interrupt: + - name: LP_I2C0 + value: 11 + registers: + - register: + name: SCL_LOW_PERIOD + description: "Configures the low level width of the SCL\nClock" + addressOffset: 0 + size: 32 + fields: + - name: SCL_LOW_PERIOD + description: "Configures the low level width of the SCL Clock. \nMeasurement unit: i2c_sclk." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: CTR + description: Transmission setting + addressOffset: 4 + size: 32 + resetValue: 520 + fields: + - name: SDA_FORCE_OUT + description: "Configures the SDA output mode\n1: Direct output,\n\n0: Open drain output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_FORCE_OUT + description: "Configures the SCL output mode\n1: Direct output,\n\n0: Open drain output." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SAMPLE_SCL_LEVEL + description: "Configures the sample mode for SDA.\n1: Sample SDA data on the SCL low level.\n\n0: Sample SDA data on the SCL high level." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_FULL_ACK_LEVEL + description: Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has reached the threshold. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TRANS_START + description: "Configures to start sending the data in txfifo for slave. \n0: No effect\n\n1: Start" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TX_LSB_FIRST + description: "Configures to control the sending order for data needing to be sent. \n1: send data from the least significant bit,\n\n0: send data from the most significant bit." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_LSB_FIRST + description: "Configures to control the storage order for received data.\n1: receive data from the least significant bit\n\n0: receive data from the most significant bit." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "Configures whether to gate clock signal for registers.\n\n0: Force clock on for registers \n\n1: Support clock only when registers are read or written to by software." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ARBITRATION_EN + description: "Configures to enable I2C bus arbitration detection.\n0: No effect\n\n1: Enable" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FSM_RST + description: "Configures to reset the SCL_FSM.\n0: No effect\n\n1: Reset" + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: CONF_UPGATE + description: "Configures this bit for synchronization\n0: No effect\n\n1: Synchronize" + bitOffset: 11 + bitWidth: 1 + access: write-only + - register: + name: SR + description: Describe I2C work status. + addressOffset: 8 + size: 32 + fields: + - name: RESP_REC + description: "Represents the received ACK value in master mode or slave mode.\n0: ACK,\n\n1: NACK." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ARB_LOST + description: "Represents whether the I2C controller loses control of SCL line.\n0: No arbitration lost\n\n1: Arbitration lost" + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BUS_BUSY + description: "Represents the I2C bus state.\n1: The I2C bus is busy transferring data, \n\n0: The I2C bus is in idle state." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: RXFIFO_CNT + description: Represents the number of data bytes to be sent. + bitOffset: 8 + bitWidth: 5 + access: read-only + - name: TXFIFO_CNT + description: Represents the number of data bytes received in RAM. + bitOffset: 18 + bitWidth: 5 + access: read-only + - name: SCL_MAIN_STATE_LAST + description: "Represents the states of the I2C module state machine. \n0: Idle,\n\n1: Address shift,\n\n2: ACK address,\n\n3: Rx data,\n\n4: Tx data,\n\n5: Send ACK,\n\n6: Wait ACK" + bitOffset: 24 + bitWidth: 3 + access: read-only + - name: SCL_STATE_LAST + description: "Represents the states of the state machine used to produce SCL.\n0: Idle,\n\n1: Start,\n\n2: Negative edge,\n\n3: Low,\n\n4: Positive edge,\n\n5: High,\n\n6: Stop" + bitOffset: 28 + bitWidth: 3 + access: read-only + - register: + name: TO + description: Setting time out control for receiving data. + addressOffset: 12 + size: 32 + resetValue: 16 + fields: + - name: TIME_OUT_VALUE + description: "Configures the timeout threshold period for SCL stucking at high or low level. The actual period is 2^(reg_time_out_value).\nMeasurement unit: i2c_sclk." + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: TIME_OUT_EN + description: "Configures to enable time out control.\n0: No effect\n\n1: Enable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: FIFO_ST + description: FIFO status register. + addressOffset: 20 + size: 32 + fields: + - name: RXFIFO_RADDR + description: Represents the offset address of the APB reading from RXFIFO + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: RXFIFO_WADDR + description: Represents the offset address of i2c module receiving data and writing to RXFIFO. + bitOffset: 5 + bitWidth: 4 + access: read-only + - name: TXFIFO_RADDR + description: Represents the offset address of i2c module reading from TXFIFO. + bitOffset: 10 + bitWidth: 4 + access: read-only + - name: TXFIFO_WADDR + description: Represents the offset address of APB bus writing to TXFIFO. + bitOffset: 15 + bitWidth: 4 + access: read-only + - register: + name: FIFO_CONF + description: FIFO configuration register. + addressOffset: 24 + size: 32 + resetValue: 16454 + fields: + - name: RXFIFO_WM_THRHD + description: "Configures the water mark threshold of RXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: TXFIFO_WM_THRHD + description: "Configures the water mark threshold of TXFIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid." + bitOffset: 5 + bitWidth: 4 + access: read-write + - name: NONFIFO_EN + description: Configures to enable APB nonfifo access. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: RX_FIFO_RST + description: "Configures to reset RXFIFO.\n0: No effect\n\n1: Reset" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_FIFO_RST + description: "Configures to reset TXFIFO.\n0: No effect\n\n1: Reset" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FIFO_PRT_EN + description: "Configures to enable FIFO pointer in non-fifo access mode. This bit controls the valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.\n0: No effect\n\n1: Enable" + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DATA + description: Rx FIFO read data. + addressOffset: 28 + size: 32 + fields: + - name: FIFO_RDATA + description: Represents the value of RXFIFO read data. + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 32 + size: 32 + resetValue: 2 + fields: + - name: RXFIFO_WM_INT_RAW + description: The raw interrupt status of I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_WM_INT_RAW + description: The raw interrupt status of I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_RAW + description: The raw interrupt status of I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: END_DETECT_INT_RAW + description: The raw interrupt status of the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS_DONE_INT_RAW + description: The raw interrupt status of the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_RAW + description: The raw interrupt status of the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: MST_TXFIFO_UDF_INT_RAW + description: The raw interrupt status of I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_RAW + description: The raw interrupt status of the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_RAW + description: The raw interrupt status of the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TRANS_START_INT_RAW + description: The raw interrupt status of the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: NACK_INT_RAW + description: The raw interrupt status of I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: TXFIFO_OVF_INT_RAW + description: The raw interrupt status of I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: RXFIFO_UDF_INT_RAW + description: The raw interrupt status of I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SCL_ST_TO_INT_RAW + description: The raw interrupt status of I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SCL_MAIN_ST_TO_INT_RAW + description: The raw interrupt status of I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DET_START_INT_RAW + description: The raw interrupt status of I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 36 + size: 32 + fields: + - name: RXFIFO_WM_INT_CLR + description: Write 1 to clear I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TXFIFO_WM_INT_CLR + description: Write 1 to clear I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RXFIFO_OVF_INT_CLR + description: Write 1 to clear I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: END_DETECT_INT_CLR + description: Write 1 to clear the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: BYTE_TRANS_DONE_INT_CLR + description: Write 1 to clear the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: ARBITRATION_LOST_INT_CLR + description: Write 1 to clear the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: MST_TXFIFO_UDF_INT_CLR + description: Write 1 to clear I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TRANS_COMPLETE_INT_CLR + description: Write 1 to clear the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: TIME_OUT_INT_CLR + description: Write 1 to clear the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: TRANS_START_INT_CLR + description: Write 1 to clear the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: NACK_INT_CLR + description: Write 1 to clear I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: TXFIFO_OVF_INT_CLR + description: Write 1 to clear I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: RXFIFO_UDF_INT_CLR + description: Write 1 to clear I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: SCL_ST_TO_INT_CLR + description: Write 1 to clear I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SCL_MAIN_ST_TO_INT_CLR + description: Write 1 to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: DET_START_INT_CLR + description: Write 1 to clear I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 40 + size: 32 + fields: + - name: RXFIFO_WM_INT_ENA + description: Write 1 to anable I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_WM_INT_ENA + description: Write 1 to anable I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_ENA + description: Write 1 to anable I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: END_DETECT_INT_ENA + description: Write 1 to anable the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: BYTE_TRANS_DONE_INT_ENA + description: Write 1 to anable the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ARBITRATION_LOST_INT_ENA + description: Write 1 to anable the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: MST_TXFIFO_UDF_INT_ENA + description: Write 1 to anable I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TRANS_COMPLETE_INT_ENA + description: Write 1 to anable the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TIME_OUT_INT_ENA + description: Write 1 to anable the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TRANS_START_INT_ENA + description: Write 1 to anable the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: NACK_INT_ENA + description: Write 1 to anable I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TXFIFO_OVF_INT_ENA + description: Write 1 to anable I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RXFIFO_UDF_INT_ENA + description: Write 1 to anable I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SCL_ST_TO_INT_ENA + description: Write 1 to anable I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SCL_MAIN_ST_TO_INT_ENA + description: Write 1 to anable I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DET_START_INT_ENA + description: Write 1 to anable I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: INT_STATUS + description: Status of captured I2C communication events + addressOffset: 44 + size: 32 + fields: + - name: RXFIFO_WM_INT_ST + description: The masked interrupt status status of I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_WM_INT_ST + description: The masked interrupt status status of I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_ST + description: The masked interrupt status status of I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: END_DETECT_INT_ST + description: The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS_DONE_INT_ST + description: The masked interrupt status status of the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_ST + description: The masked interrupt status status of the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: MST_TXFIFO_UDF_INT_ST + description: The masked interrupt status status of I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_ST + description: The masked interrupt status status of the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_ST + description: The masked interrupt status status of the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TRANS_START_INT_ST + description: The masked interrupt status status of the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: NACK_INT_ST + description: The masked interrupt status status of I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: TXFIFO_OVF_INT_ST + description: The masked interrupt status status of I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: RXFIFO_UDF_INT_ST + description: The masked interrupt status status of I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SCL_ST_TO_INT_ST + description: The masked interrupt status status of I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SCL_MAIN_ST_TO_INT_ST + description: The masked interrupt status status of I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DET_START_INT_ST + description: The masked interrupt status status of I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - register: + name: SDA_HOLD + description: Configures the hold time after a negative SCL edge. + addressOffset: 48 + size: 32 + fields: + - name: TIME + description: "Configures the time to hold the data after the falling edge of SCL.\nMeasurement unit: i2c_sclk" + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SDA_SAMPLE + description: Configures the sample time after a positive SCL edge. + addressOffset: 52 + size: 32 + fields: + - name: TIME + description: "Configures the sample time after a positive SCL edge.\nMeasurement unit: i2c_sclk" + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_HIGH_PERIOD + description: Configures the high level width of SCL + addressOffset: 56 + size: 32 + fields: + - name: SCL_HIGH_PERIOD + description: "Configures for how long SCL remains high in master mode.\nMeasurement unit: i2c_sclk" + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: SCL_WAIT_HIGH_PERIOD + description: "Configures the SCL_FSM's waiting period for SCL high level in master mode.\nMeasurement unit: i2c_sclk" + bitOffset: 9 + bitWidth: 7 + access: read-write + - register: + name: SCL_START_HOLD + description: Configures the delay between the SDA and SCL negative edge for a start condition + addressOffset: 64 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "Configures the time between the falling edge of SDA and the falling edge of SCL for a START condition.\nMeasurement unit: i2c_sclk." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_RSTART_SETUP + description: "Configures the delay between the positive\nedge of SCL and the negative edge of SDA" + addressOffset: 68 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "Configures the time between the positive edge of SCL and the negative edge of SDA for a RESTART condition.\nMeasurement unit: i2c_sclk" + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_STOP_HOLD + description: "Configures the delay after the SCL clock\nedge for a stop condition" + addressOffset: 72 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "Configures the delay after the STOP condition.\nMeasurement unit: i2c_sclk" + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_STOP_SETUP + description: "Configures the delay between the SDA and\nSCL positive edge for a stop condition" + addressOffset: 76 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "Configures the time between the rising edge of SCL and the rising edge of SDA.\nMeasurement unit: i2c_sclk" + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: FILTER_CFG + description: SCL and SDA filter configuration register + addressOffset: 80 + size: 32 + resetValue: 768 + fields: + - name: SCL_FILTER_THRES + description: "Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL input has smaller width than this register value, the I2C controller will ignore that pulse. \nMeasurement unit: i2c_sclk" + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: SDA_FILTER_THRES + description: "Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA input has smaller width than this register value, the I2C controller will ignore that pulse. \nMeasurement unit: i2c_sclk" + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: SCL_FILTER_EN + description: Configures to enable the filter function for SCL. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SDA_FILTER_EN + description: Configures to enable the filter function for SDA. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: CLK_CONF + description: I2C CLK configuration register + addressOffset: 84 + size: 32 + resetValue: 2097152 + fields: + - name: SCLK_DIV_NUM + description: the integral part of the fractional divisor for i2c module + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SCLK_DIV_A + description: the numerator of the fractional part of the fractional divisor for i2c module + bitOffset: 8 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_B + description: the denominator of the fractional part of the fractional divisor for i2c module + bitOffset: 14 + bitWidth: 6 + access: read-write + - name: SCLK_SEL + description: "The clock selection for i2c module:0-XTAL,1-CLK_8MHz." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SCLK_ACTIVE + description: The clock switch for i2c module + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + name: COMD0 + description: I2C command register 0 + addressOffset: 88 + size: 32 + fields: + - name: COMMAND0 + description: "Configures command 0. It consists of three parts: \nop_code is the command,\n0: RSTART, \n1: WRITE,\n2: READ,\n3: STOP,\n4: END.\n\nByte_num represents the number of bytes that need to be sent or received.\nack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND0_DONE + description: "Represents whether command 0 is done in I2C Master mode.\n0: Not done\n\n1: Done" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD1 + description: I2C command register 1 + addressOffset: 92 + size: 32 + fields: + - name: COMMAND1 + description: "Configures command 1. See details in I2C_CMD0_REG[13:0]." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND1_DONE + description: "Represents whether command 1 is done in I2C Master mode.\n0: Not done\n\n1: Done" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD2 + description: I2C command register 2 + addressOffset: 96 + size: 32 + fields: + - name: COMMAND2 + description: "Configures command 2. See details in I2C_CMD0_REG[13:0]." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND2_DONE + description: "Represents whether command 2 is done in I2C Master mode.\n0: Not done\n\n1: Done" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD3 + description: I2C command register 3 + addressOffset: 100 + size: 32 + fields: + - name: COMMAND3 + description: "Configures command 3. See details in I2C_CMD0_REG[13:0]." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND3_DONE + description: "Represents whether command 3 is done in I2C Master mode.\n0: Not done\n\n1: Done" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD4 + description: I2C command register 4 + addressOffset: 104 + size: 32 + fields: + - name: COMMAND4 + description: "Configures command 4. See details in I2C_CMD0_REG[13:0]." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND4_DONE + description: "Represents whether command 4 is done in I2C Master mode.\n0: Not done\n\n1: Done" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD5 + description: I2C command register 5 + addressOffset: 108 + size: 32 + fields: + - name: COMMAND5 + description: "Configures command 5. See details in I2C_CMD0_REG[13:0]." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND5_DONE + description: "Represents whether command 5 is done in I2C Master mode.\n0: Not done\n\n1: Done" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD6 + description: I2C command register 6 + addressOffset: 112 + size: 32 + fields: + - name: COMMAND6 + description: "Configures command 6. See details in I2C_CMD0_REG[13:0]." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND6_DONE + description: "Represents whether command 6 is done in I2C Master mode.\n0: Not done\n\n1: Done" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMD7 + description: I2C command register 7 + addressOffset: 116 + size: 32 + fields: + - name: COMMAND7 + description: "Configures command 7. See details in I2C_CMD0_REG[13:0]." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND7_DONE + description: "Represents whether command 7 is done in I2C Master mode.\n0: Not done\n\n1: Done" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SCL_ST_TIME_OUT + description: SCL status time out register + addressOffset: 120 + size: 32 + resetValue: 16 + fields: + - name: SCL_ST_TO_I2C + description: "Configures the threshold value of SCL_FSM state unchanged period. It should be no more than 23.\nMeasurement unit: i2c_sclk" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SCL_MAIN_ST_TIME_OUT + description: SCL main status time out register + addressOffset: 124 + size: 32 + resetValue: 16 + fields: + - name: SCL_MAIN_ST_TO_I2C + description: "Configures the threshold value of SCL_MAIN_FSM state unchanged period.nIt should be no more than 23.\nMeasurement unit: i2c_sclk" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SCL_SP_CONF + description: Power configuration register + addressOffset: 128 + size: 32 + fields: + - name: SCL_RST_SLV_EN + description: "When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_RST_SLV_NUM + description: "Configures to send out SCL pulses when I2C master is IDLE. The number of pulses equals to reg_scl_rst_slv_num[4:0]." + bitOffset: 1 + bitWidth: 5 + access: read-write + - name: SCL_PD_EN + description: "Configure the pulses of SCL generated in I2C master mode. \nValid when reg_scl_rst_slv_en is 1.\nMeasurement unit: i2c_sclk" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SDA_PD_EN + description: "Configures to power down the I2C output SCL line. \n0: Not power down.\n\n1: Power down.\nValid only when reg_scl_force_out is 1." + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version register + addressOffset: 248 + size: 32 + resetValue: 35656003 + fields: + - name: DATE + description: Version control register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TXFIFO_START_ADDR + description: I2C TXFIFO base address register + addressOffset: 256 + size: 32 + fields: + - name: TXFIFO_START_ADDR + description: Represents the I2C txfifo first address. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RXFIFO_START_ADDR + description: I2C RXFIFO base address register + addressOffset: 384 + size: 32 + fields: + - name: RXFIFO_START_ADDR + description: Represents the I2C rxfifo first address. + bitOffset: 0 + bitWidth: 32 + access: read-only + - name: LP_I2S0 + description: Low-power I2S (Inter-IC Sound) Controller 0 + groupName: LP_I2S + baseAddress: 1343377408 + addressBlock: + - offset: 0 + size: 152 + usage: registers + interrupt: + - name: LP_I2S0 + value: 12 + registers: + - register: + name: VAD_CONF + description: I2S VAD Configure register + addressOffset: 0 + size: 32 + fields: + - name: VAD_EN + description: VAD enable register + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: VAD_RESET + description: VAD reset register + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: VAD_FORCE_START + description: VAD force start register. + bitOffset: 2 + bitWidth: 1 + access: write-only + - register: + name: VAD_RESULT + description: I2S VAD Result register + addressOffset: 4 + size: 32 + fields: + - name: VAD_FLAG + description: Reg vad flag observe signal + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ENERGY_ENOUGH + description: Reg energy enough observe signal + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: RX_MEM_CONF + description: I2S VAD Observe register + addressOffset: 8 + size: 32 + resetValue: 32256 + fields: + - name: RX_MEM_FIFO_CNT + description: The number of data in the rx mem + bitOffset: 0 + bitWidth: 9 + access: read-only + - name: RX_MEM_THRESHOLD + description: I2S rx mem will trigger an interrupt when the data in the mem is over(not including equal) reg_rx_mem_threshold + bitOffset: 9 + bitWidth: 8 + access: read-write + - register: + name: INT_RAW + description: "I2S interrupt raw register, valid in level." + addressOffset: 12 + size: 32 + fields: + - name: RX_DONE_INT_RAW + description: The raw interrupt status bit for the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_RAW + description: The raw interrupt status bit for the i2s_rx_hung_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_FIFOMEM_UDF_INT_RAW + description: The raw interrupt status bit for the i2s_rx_fifomem_udf_int interrupt + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: VAD_DONE_INT_RAW + description: The raw interrupt status bit for the vad_done_int interrupt + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: VAD_RESET_DONE_INT_RAW + description: The raw interrupt status bit for the vad_reset_done_int interrupt + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: RX_MEM_THRESHOLD_INT_RAW + description: The raw interrupt status bit for the rx_mem_threshold_int interrupt + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: I2S interrupt status register. + addressOffset: 16 + size: 32 + fields: + - name: RX_DONE_INT_ST + description: The masked interrupt status bit for the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_ST + description: The masked interrupt status bit for the i2s_rx_hung_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_FIFOMEM_UDF_INT_ST + description: The masked interrupt status bit for the i2s_rx_fifomem_udf_int interrupt + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: LP_VAD_DONE_INT_ST + description: The masked interrupt status bit for the vad_done_int interrupt + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: LP_VAD_RESET_DONE_INT_ST + description: The masked interrupt status bit for the vad_reset_done_int interrupt + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: RX_MEM_THRESHOLD_INT_ST + description: The masked interrupt status bit for the rx_mem_threshold_int interrupt + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: I2S interrupt enable register. + addressOffset: 20 + size: 32 + fields: + - name: RX_DONE_INT_ENA + description: The interrupt enable bit for the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_HUNG_INT_ENA + description: The interrupt enable bit for the i2s_rx_hung_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_FIFOMEM_UDF_INT_ENA + description: The interrupt enable bit for the i2s_rx_fifomem_udf_int interrupt + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: LP_VAD_DONE_INT_ENA + description: The interrupt enable bit for the vad_done_int interrupt + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: LP_VAD_RESET_DONE_INT_ENA + description: The interrupt enable bit for the vad_reset_done_int interrupt + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_MEM_THRESHOLD_INT_ENA + description: The interrupt enable bit for the rx_mem_threshold_int interrupt + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: I2S interrupt clear register. + addressOffset: 24 + size: 32 + fields: + - name: RX_DONE_INT_CLR + description: Set this bit to clear the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: RX_HUNG_INT_CLR + description: Set this bit to clear the i2s_rx_hung_int interrupt + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_FIFOMEM_UDF_INT_CLR + description: Set this bit to clear the i2s_rx_fifomem_udf_int interrupt + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: LP_VAD_DONE_INT_CLR + description: Set this bit to clear the vad_done_int interrupt + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: LP_VAD_RESET_DONE_INT_CLR + description: Set this bit to clear the vad_reset_done_int interrupt + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: RX_MEM_THRESHOLD_INT_CLR + description: Set this bit to clear the rx_mem_threshold_int interrupt + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: RX_CONF + description: I2S RX configure register + addressOffset: 32 + size: 32 + resetValue: 38400 + fields: + - name: RX_RESET + description: Set this bit to reset receiver + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: RX_FIFO_RESET + description: Set this bit to reset Rx AFIFO + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_START + description: Set this bit to start receiving data + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_SLAVE_MOD + description: Set this bit to enable slave receiver mode + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_FIFOMEM_RESET + description: Set this bit to reset Rx Syncfifomem + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: RX_MONO + description: Set this bit to enable receiver in mono mode + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RX_BIG_ENDIAN + description: "I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RX_UPDATE + description: Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RX_MONO_FST_VLD + description: "1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RX_PCM_CONF + description: "I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: RX_PCM_BYPASS + description: Set this bit to bypass Compress/Decompress module for received data. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RX_STOP_MODE + description: "0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full." + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: RX_LEFT_ALIGN + description: "1: I2S RX left alignment mode. 0: I2S RX right alignment mode." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RX_24_FILL_EN + description: "1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RX_WS_IDLE_POL + description: "0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: RX_BIT_ORDER + description: "I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RX_TDM_EN + description: "1: Enable I2S TDM Rx mode . 0: Disable." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RX_PDM_EN + description: "1: Enable I2S PDM Rx mode . 0: Disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: RX_CONF1 + description: I2S RX configure register 1 + addressOffset: 40 + size: 32 + resetValue: 792584960 + fields: + - name: RX_TDM_WS_WIDTH + description: "The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck" + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: RX_BCK_DIV_NUM + description: Bit clock configuration bits in receiver mode. + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: RX_BITS_MOD + description: "Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode." + bitOffset: 13 + bitWidth: 5 + access: read-write + - name: RX_HALF_SAMPLE_BITS + description: I2S Rx half sample bits -1. + bitOffset: 18 + bitWidth: 6 + access: read-write + - name: RX_TDM_CHAN_BITS + description: The Rx bit number for each channel minus 1in TDM mode. + bitOffset: 24 + bitWidth: 5 + access: read-write + - name: RX_MSB_SHIFT + description: Set this bit to enable receiver in Phillips standard mode + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: RX_TDM_CTRL + description: I2S TX TDM mode control register + addressOffset: 80 + size: 32 + resetValue: 3 + fields: + - name: RX_TDM_PDM_CHAN0_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN1_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_TDM_TOT_CHAN_NUM + description: The total channel number of I2S TX TDM mode. + bitOffset: 16 + bitWidth: 4 + access: read-write + - register: + name: RX_TIMING + description: I2S RX timing control register + addressOffset: 88 + size: 32 + fields: + - name: RX_SD_IN_DM + description: "The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: RX_WS_OUT_DM + description: "The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: RX_BCK_OUT_DM + description: "The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: RX_WS_IN_DM + description: "The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: RX_BCK_IN_DM + description: "The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 28 + bitWidth: 2 + access: read-write + - register: + name: LC_HUNG_CONF + description: I2S HUNG configure register. + addressOffset: 96 + size: 32 + resetValue: 2064 + fields: + - name: LC_FIFO_TIMEOUT + description: the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: LC_FIFO_TIMEOUT_SHIFT + description: The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + bitOffset: 8 + bitWidth: 3 + access: read-write + - name: LC_FIFO_TIMEOUT_ENA + description: The enable bit for FIFO timeout + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: RXEOF_NUM + description: I2S RX data number control register. + addressOffset: 100 + size: 32 + resetValue: 64 + fields: + - name: RX_EOF_NUM + description: "The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel." + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: CONF_SIGLE_DATA + description: I2S signal data register + addressOffset: 104 + size: 32 + fields: + - name: SINGLE_DATA + description: The configured constant channel data to be sent out. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RX_PDM_CONF + description: I2S RX configure register + addressOffset: 112 + size: 32 + resetValue: 4162846720 + fields: + - name: RX_PDM2PCM_EN + description: "1: Enable PDM2PCM RX mode. 0: DIsable." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RX_PDM_SINC_DSR_16_EN + description: "Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: RX_PDM2PCM_AMPLIFY_NUM + description: Configure PDM RX amplify number. + bitOffset: 21 + bitWidth: 4 + access: read-write + - name: RX_PDM_HP_BYPASS + description: I2S PDM RX bypass hp filter or not. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: RX_IIR_HP_MULT12_5 + description: "The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 + LP_I2S_RX_IIR_HP_MULT12_5[2:0])" + bitOffset: 26 + bitWidth: 3 + access: read-write + - name: RX_IIR_HP_MULT12_0 + description: "The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 + LP_I2S_RX_IIR_HP_MULT12_0[2:0])" + bitOffset: 29 + bitWidth: 3 + access: read-write + - register: + name: ECO_LOW + description: I2S ECO register + addressOffset: 116 + size: 32 + fields: + - name: RDN_ECO_LOW + description: logic low eco registers + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ECO_HIGH + description: I2S ECO register + addressOffset: 120 + size: 32 + resetValue: 4294967295 + fields: + - name: RDN_ECO_HIGH + description: logic high eco registers + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ECO_CONF + description: I2S ECO register + addressOffset: 124 + size: 32 + fields: + - name: RDN_ENA + description: enable rdn counter bit + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RDN_RESULT + description: rdn result + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: VAD_PARAM0 + description: I2S VAD Parameter register + addressOffset: 128 + size: 32 + resetValue: 13112200 + fields: + - name: PARAM_MIN_ENERGY + description: VAD parameter + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: PARAM_INIT_FRAME_NUM + description: VAD parameter + bitOffset: 16 + bitWidth: 9 + access: read-write + - register: + name: VAD_PARAM1 + description: I2S VAD Parameter register + addressOffset: 132 + size: 32 + resetValue: 673062467 + fields: + - name: PARAM_MIN_SPEECH_COUNT + description: VAD parameter + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: PARAM_MAX_SPEECH_COUNT + description: VAD parameter + bitOffset: 4 + bitWidth: 7 + access: read-write + - name: PARAM_HANGOVER_SPEECH + description: VAD parameter + bitOffset: 11 + bitWidth: 5 + access: read-write + - name: PARAM_HANGOVER_SILENT + description: VAD parameter + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: PARAM_MAX_OFFSET + description: VAD parameter + bitOffset: 24 + bitWidth: 7 + access: read-write + - name: PARAM_SKIP_BAND_ENERGY + description: Set 1 to skip band energy check. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: VAD_PARAM2 + description: I2S VAD Parameter register + addressOffset: 136 + size: 32 + resetValue: 2126014054 + fields: + - name: PARAM_NOISE_AMP_DOWN + description: VAD parameter + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: PARAM_NOISE_AMP_UP + description: VAD parameter + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: VAD_PARAM3 + description: I2S VAD Parameter register + addressOffset: 140 + size: 32 + resetValue: 2104590303 + fields: + - name: PARAM_NOISE_SPE_UP0 + description: VAD parameter + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: PARAM_NOISE_SPE_UP1 + description: VAD parameter + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: VAD_PARAM4 + description: I2S VAD Parameter register + addressOffset: 144 + size: 32 + resetValue: 2040161894 + fields: + - name: PARAM_NOISE_SPE_DOWN + description: VAD parameter + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: PARAM_NOISE_MEAN_DOWN + description: VAD parameter + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: VAD_PARAM5 + description: I2S VAD Parameter register + addressOffset: 148 + size: 32 + resetValue: 2083028337 + fields: + - name: PARAM_NOISE_MEAN_UP0 + description: VAD parameter + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: PARAM_NOISE_MEAN_UP1 + description: VAD parameter + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: VAD_PARAM6 + description: I2S VAD Parameter register + addressOffset: 152 + size: 32 + resetValue: 3019930880 + fields: + - name: PARAM_NOISE_STD_FS_THSL + description: "Feature_sum threshold to determine noise_std max value when vad_tag=1, equal to ((noise_std_max)>>11)^2*5" + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: PARAM_NOISE_STD_FS_THSH + description: "Feature_sum threshold to determine noise_std max value when vad_tag=0, equal to ((noise_std_max)>>11)^2*5" + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: VAD_PARAM7 + description: I2S VAD Parameter register + addressOffset: 156 + size: 32 + resetValue: 21528248 + fields: + - name: PARAM_THRES_UPD_BASE + description: VAD parameter + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: PARAM_THRES_UPD_VARY + description: VAD parameter + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: VAD_PARAM8 + description: I2S VAD Parameter register + addressOffset: 160 + size: 32 + resetValue: 536891456 + fields: + - name: PARAM_THRES_UPD_BDL + description: Noise_std boundary low when updating threshold. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: PARAM_THRES_UPD_BDH + description: Noise_std boundary high when updating threshold. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: PARAM_FEATURE_BURST + description: VAD parameter + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: VAD_OB0 + description: I2S VAD Observe register + addressOffset: 176 + size: 32 + fields: + - name: SPEECH_COUNT_OB + description: Reg silent count observe + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: SILENT_COUNT_OB + description: Reg speech count observe + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: MAX_SIGNAL0_OB + description: Reg max signal0 observe + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: VAD_OB1 + description: I2S VAD Observe register + addressOffset: 180 + size: 32 + fields: + - name: MAX_SIGNAL1_OB + description: Reg max signal1 observe + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: MAX_SIGNAL2_OB + description: Reg max signal2 observe + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: VAD_OB2 + description: I2S VAD Observe register + addressOffset: 184 + size: 32 + fields: + - name: NOISE_AMP_OB + description: Reg noise_amp observe signal + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: VAD_OB3 + description: I2S VAD Observe register + addressOffset: 188 + size: 32 + fields: + - name: NOISE_MEAN_OB + description: Reg noise_mean observe signal + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: VAD_OB4 + description: I2S VAD Observe register + addressOffset: 192 + size: 32 + fields: + - name: NOISE_STD_OB + description: Reg noise_std observe signal + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: VAD_OB5 + description: I2S VAD Observe register + addressOffset: 196 + size: 32 + fields: + - name: OFFSET_OB + description: Reg offset observe signal + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: VAD_OB6 + description: I2S VAD Observe register + addressOffset: 200 + size: 32 + fields: + - name: THRESHOLD_OB + description: Reg threshold observe signal + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: VAD_OB7 + description: I2S VAD Observe register + addressOffset: 204 + size: 32 + fields: + - name: ENERGY_LOW_OB + description: Reg energy bit 31~0 observe signal + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: VAD_OB8 + description: I2S VAD Observe register + addressOffset: 208 + size: 32 + fields: + - name: ENERGY_HIGH_OB + description: Reg energy bit 63~32 observe signal + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CLK_GATE + description: Clock gate register + addressOffset: 248 + size: 32 + resetValue: 10 + fields: + - name: CLK_EN + description: set this bit to enable clock gate + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: VAD_CG_FORCE_ON + description: VAD clock gate force on register + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_MEM_CG_FORCE_ON + description: I2S rx mem clock gate force on register + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_REG_CG_FORCE_ON + description: I2S rx reg clock gate force on register + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 252 + size: 32 + resetValue: 36720704 + fields: + - name: DATE + description: I2S version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: LP_IO_MUX + description: Low-power Input/Output Multiplexer + groupName: LP_IOMUX + baseAddress: 1343401984 + addressBlock: + - offset: 0 + size: 84 + usage: registers + registers: + - register: + name: CLK_EN + description: Reserved + addressOffset: 0 + size: 32 + resetValue: 1 + fields: + - name: REG_CLK_EN + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: VER_DATE + description: Reserved + addressOffset: 4 + size: 32 + resetValue: 2294547 + fields: + - name: REG_VER_DATE + description: Reserved + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + name: PAD0 + description: Reserved + addressOffset: 8 + size: 32 + resetValue: 2 + fields: + - name: REG_PAD0_DRV + description: Reserved + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: REG_PAD0_RDE + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_PAD0_RUE + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: REG_PAD0_MUX_SEL + description: "1:use LP GPIO,0: use digital GPIO" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_PAD0_FUN_SEL + description: function sel + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: REG_PAD0_SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: REG_PAD0_SLP_IE + description: input enable in sleep mode + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REG_PAD0_SLP_OE + description: output enable in sleep mode + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REG_PAD0_FUN_IE + description: input enable in work mode + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: REG_PAD0_FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: PAD1 + description: Reserved + addressOffset: 12 + size: 32 + resetValue: 2 + fields: + - name: REG_PAD1_DRV + description: Reserved + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: REG_PAD1_RDE + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_PAD1_RUE + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: REG_PAD1_MUX_SEL + description: "1:use LP GPIO,0: use digital GPIO" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_PAD1_FUN_SEL + description: function sel + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: REG_PAD1_SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: REG_PAD1_SLP_IE + description: input enable in sleep mode + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REG_PAD1_SLP_OE + description: output enable in sleep mode + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REG_PAD1_FUN_IE + description: input enable in work mode + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: REG_PAD1_FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: PAD2 + description: Reserved + addressOffset: 16 + size: 32 + resetValue: 2 + fields: + - name: REG_PAD2_DRV + description: Reserved + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: REG_PAD2_RDE + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_PAD2_RUE + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: REG_PAD2_MUX_SEL + description: "1:use LP GPIO,0: use digital GPIO" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_PAD2_FUN_SEL + description: function sel + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: REG_PAD2_SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: REG_PAD2_SLP_IE + description: input enable in sleep mode + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REG_PAD2_SLP_OE + description: output enable in sleep mode + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REG_PAD2_FUN_IE + description: input enable in work mode + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: REG_PAD2_FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: PAD3 + description: Reserved + addressOffset: 20 + size: 32 + resetValue: 2 + fields: + - name: REG_PAD3_DRV + description: Reserved + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: REG_PAD3_RDE + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_PAD3_RUE + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: REG_PAD3_MUX_SEL + description: "1:use LP GPIO,0: use digital GPIO" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_PAD3_FUN_SEL + description: function sel + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: REG_PAD3_SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: REG_PAD3_SLP_IE + description: input enable in sleep mode + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REG_PAD3_SLP_OE + description: output enable in sleep mode + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REG_PAD3_FUN_IE + description: input enable in work mode + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: REG_PAD3_FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: PAD4 + description: Reserved + addressOffset: 24 + size: 32 + resetValue: 2 + fields: + - name: REG_PAD4_DRV + description: Reserved + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: REG_PAD4_RDE + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_PAD4_RUE + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: REG_PAD4_MUX_SEL + description: "1:use LP GPIO,0: use digital GPIO" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_PAD4_FUN_SEL + description: function sel + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: REG_PAD4_SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: REG_PAD4_SLP_IE + description: input enable in sleep mode + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REG_PAD4_SLP_OE + description: output enable in sleep mode + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REG_PAD4_FUN_IE + description: input enable in work mode + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: REG_PAD4_FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: PAD5 + description: Reserved + addressOffset: 28 + size: 32 + resetValue: 2 + fields: + - name: REG_PAD5_DRV + description: Reserved + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: REG_PAD5_RDE + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_PAD5_RUE + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: REG_PAD5_MUX_SEL + description: "1:use LP GPIO,0: use digital GPIO" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_PAD5_FUN_SEL + description: function sel + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: REG_PAD5_SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: REG_PAD5_SLP_IE + description: input enable in sleep mode + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REG_PAD5_SLP_OE + description: output enable in sleep mode + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REG_PAD5_FUN_IE + description: input enable in work mode + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: REG_PAD5_FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: PAD6 + description: Reserved + addressOffset: 32 + size: 32 + resetValue: 2 + fields: + - name: REG_PAD6_DRV + description: Reserved + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: REG_PAD6_RDE + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_PAD6_RUE + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: REG_PAD6_MUX_SEL + description: "1:use LP GPIO,0: use digital GPIO" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_PAD6_FUN_SEL + description: function sel + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: REG_PAD6_SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: REG_PAD6_SLP_IE + description: input enable in sleep mode + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REG_PAD6_SLP_OE + description: output enable in sleep mode + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REG_PAD6_FUN_IE + description: input enable in work mode + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: REG_PAD6_FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: PAD7 + description: Reserved + addressOffset: 36 + size: 32 + resetValue: 2 + fields: + - name: REG_PAD7_DRV + description: Reserved + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: REG_PAD7_RDE + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_PAD7_RUE + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: REG_PAD7_MUX_SEL + description: "1:use LP GPIO,0: use digital GPIO" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_PAD7_FUN_SEL + description: function sel + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: REG_PAD7_SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: REG_PAD7_SLP_IE + description: input enable in sleep mode + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REG_PAD7_SLP_OE + description: output enable in sleep mode + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REG_PAD7_FUN_IE + description: input enable in work mode + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: REG_PAD7_FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: PAD8 + description: Reserved + addressOffset: 40 + size: 32 + resetValue: 2 + fields: + - name: REG_PAD8_DRV + description: Reserved + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: REG_PAD8_RDE + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_PAD8_RUE + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: REG_PAD8_MUX_SEL + description: "1:use LP GPIO,0: use digital GPIO" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_PAD8_FUN_SEL + description: function sel + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: REG_PAD8_SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: REG_PAD8_SLP_IE + description: input enable in sleep mode + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REG_PAD8_SLP_OE + description: output enable in sleep mode + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REG_PAD8_FUN_IE + description: input enable in work mode + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: REG_PAD8_FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: PAD9 + description: Reserved + addressOffset: 44 + size: 32 + resetValue: 2 + fields: + - name: REG_PAD9_DRV + description: Reserved + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: REG_PAD9_RDE + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_PAD9_RUE + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: REG_PAD9_MUX_SEL + description: "1:use LP GPIO,0: use digital GPIO" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_PAD9_FUN_SEL + description: function sel + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: REG_PAD9_SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: REG_PAD9_SLP_IE + description: input enable in sleep mode + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REG_PAD9_SLP_OE + description: output enable in sleep mode + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REG_PAD9_FUN_IE + description: input enable in work mode + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: REG_PAD9_FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: PAD10 + description: Reserved + addressOffset: 48 + size: 32 + resetValue: 2 + fields: + - name: REG_PAD10_DRV + description: Reserved + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: REG_PAD10_RDE + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_PAD10_RUE + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: REG_PAD10_MUX_SEL + description: "1:use LP GPIO,0: use digital GPIO" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_PAD10_FUN_SEL + description: function sel + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: REG_PAD10_SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: REG_PAD10_SLP_IE + description: input enable in sleep mode + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REG_PAD10_SLP_OE + description: output enable in sleep mode + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REG_PAD10_FUN_IE + description: input enable in work mode + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: REG_PAD10_FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: PAD11 + description: Reserved + addressOffset: 52 + size: 32 + resetValue: 2 + fields: + - name: REG_PAD11_DRV + description: Reserved + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: REG_PAD11_RDE + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_PAD11_RUE + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: REG_PAD11_MUX_SEL + description: "1:use LP GPIO,0: use digital GPIO" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_PAD11_FUN_SEL + description: function sel + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: REG_PAD11_SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: REG_PAD11_SLP_IE + description: input enable in sleep mode + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REG_PAD11_SLP_OE + description: output enable in sleep mode + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REG_PAD11_FUN_IE + description: input enable in work mode + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: REG_PAD11_FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: PAD120 + description: Reserved + addressOffset: 56 + size: 32 + resetValue: 2 + fields: + - name: REG_PAD12_DRV + description: Reserved + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: REG_PAD12_RDE + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_PAD12_RUE + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: REG_PAD12_MUX_SEL + description: "1:use LP GPIO,0: use digital GPIO" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_PAD12_FUN_SEL + description: function sel + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: REG_PAD12_SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: REG_PAD12_SLP_IE + description: input enable in sleep mode + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REG_PAD12_SLP_OE + description: output enable in sleep mode + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REG_PAD12_FUN_IE + description: input enable in work mode + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: REG_PAD12_FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: PAD13 + description: Reserved + addressOffset: 60 + size: 32 + resetValue: 2 + fields: + - name: REG_PAD13_DRV + description: Reserved + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: REG_PAD13_RDE + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_PAD13_RUE + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: REG_PAD13_MUX_SEL + description: "1:use LP GPIO,0: use digital GPIO" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_PAD13_FUN_SEL + description: function sel + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: REG_PAD13_SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: REG_PAD13_SLP_IE + description: input enable in sleep mode + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REG_PAD13_SLP_OE + description: output enable in sleep mode + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REG_PAD13_FUN_IE + description: input enable in work mode + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: REG_PAD13_FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: PAD14 + description: Reserved + addressOffset: 64 + size: 32 + resetValue: 2 + fields: + - name: REG_PAD14_DRV + description: Reserved + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: REG_PAD14_RDE + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_PAD14_RUE + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: REG_PAD14_MUX_SEL + description: "1:use LP GPIO,0: use digital GPIO" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_PAD14_FUN_SEL + description: function sel + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: REG_PAD14_SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: REG_PAD14_SLP_IE + description: input enable in sleep mode + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REG_PAD14_SLP_OE + description: output enable in sleep mode + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REG_PAD14_FUN_IE + description: input enable in work mode + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: REG_PAD14_FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: PAD15 + description: Reserved + addressOffset: 68 + size: 32 + resetValue: 2 + fields: + - name: REG_PAD15_DRV + description: Reserved + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: REG_PAD15_RDE + description: Reserved + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REG_PAD15_RUE + description: Reserved + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: REG_PAD15_MUX_SEL + description: "1:use LP GPIO,0: use digital GPIO" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: REG_PAD15_FUN_SEL + description: function sel + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: REG_PAD15_SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: REG_PAD15_SLP_IE + description: input enable in sleep mode + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REG_PAD15_SLP_OE + description: output enable in sleep mode + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: REG_PAD15_FUN_IE + description: input enable in work mode + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: REG_PAD15_FILTER_EN + description: need des + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: EXT_WAKEUP0_SEL + description: Reserved + addressOffset: 72 + size: 32 + fields: + - name: REG_XTL_EXT_CTR_SEL + description: select LP GPIO 0 ~ 15 to control XTAL + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: REG_EXT_WAKEUP0_SEL + description: Reserved + bitOffset: 5 + bitWidth: 5 + access: read-write + - register: + name: LP_PAD_HOLD + description: Reserved + addressOffset: 76 + size: 32 + fields: + - name: REG_LP_GPIO_HOLD + description: Reserved + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: LP_PAD_HYS + description: Reserved + addressOffset: 80 + size: 32 + fields: + - name: REG_LP_GPIO_HYS + description: Reserved + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: LP_UART + description: Low-power UART (Universal Asynchronous Receiver-Transmitter) Controller + groupName: LP_UART + baseAddress: 1343361024 + addressBlock: + - offset: 0 + size: 132 + usage: registers + interrupt: + - name: LP_UART + value: 16 + registers: + - register: + name: FIFO + description: FIFO data register + addressOffset: 0 + size: 32 + fields: + - name: RXFIFO_RD_BYTE + description: UART 0 accesses FIFO via this register. + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 4 + size: 32 + resetValue: 2 + fields: + - name: RXFIFO_FULL_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_EMPTY_INT_RAW + description: This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PARITY_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a parity error in the data. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FRM_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a data frame error . + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DSR_CHG_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CTS_CHG_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BRK_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RXFIFO_TOUT_INT_RAW + description: This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SW_XON_INT_RAW + description: This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SW_XOFF_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GLITCH_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_BRK_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_BRK_IDLE_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: AT_CMD_CHAR_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: WAKEUP_INT_RAW + description: This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 8 + size: 32 + fields: + - name: RXFIFO_FULL_INT_ST + description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_EMPTY_INT_ST + description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: PARITY_ERR_INT_ST + description: This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FRM_ERR_INT_ST + description: This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_ST + description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DSR_CHG_INT_ST + description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CTS_CHG_INT_ST + description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BRK_DET_INT_ST + description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: RXFIFO_TOUT_INT_ST + description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SW_XON_INT_ST + description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SW_XOFF_INT_ST + description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: GLITCH_DET_INT_ST + description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TX_BRK_DONE_INT_ST + description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: TX_BRK_IDLE_DONE_INT_ST + description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_ST + description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: AT_CMD_CHAR_DET_INT_ST + description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: WAKEUP_INT_ST + description: This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + bitOffset: 19 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 12 + size: 32 + fields: + - name: RXFIFO_FULL_INT_ENA + description: This is the enable bit for rxfifo_full_int_st register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_EMPTY_INT_ENA + description: This is the enable bit for txfifo_empty_int_st register. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PARITY_ERR_INT_ENA + description: This is the enable bit for parity_err_int_st register. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FRM_ERR_INT_ENA + description: This is the enable bit for frm_err_int_st register. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_ENA + description: This is the enable bit for rxfifo_ovf_int_st register. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DSR_CHG_INT_ENA + description: This is the enable bit for dsr_chg_int_st register. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CTS_CHG_INT_ENA + description: This is the enable bit for cts_chg_int_st register. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BRK_DET_INT_ENA + description: This is the enable bit for brk_det_int_st register. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RXFIFO_TOUT_INT_ENA + description: This is the enable bit for rxfifo_tout_int_st register. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SW_XON_INT_ENA + description: This is the enable bit for sw_xon_int_st register. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SW_XOFF_INT_ENA + description: This is the enable bit for sw_xoff_int_st register. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GLITCH_DET_INT_ENA + description: This is the enable bit for glitch_det_int_st register. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_BRK_DONE_INT_ENA + description: This is the enable bit for tx_brk_done_int_st register. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_BRK_IDLE_DONE_INT_ENA + description: This is the enable bit for tx_brk_idle_done_int_st register. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_ENA + description: This is the enable bit for tx_done_int_st register. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: AT_CMD_CHAR_DET_INT_ENA + description: This is the enable bit for at_cmd_char_det_int_st register. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: WAKEUP_INT_ENA + description: This is the enable bit for uart_wakeup_int_st register. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 16 + size: 32 + fields: + - name: RXFIFO_FULL_INT_CLR + description: Set this bit to clear the rxfifo_full_int_raw interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TXFIFO_EMPTY_INT_CLR + description: Set this bit to clear txfifo_empty_int_raw interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: PARITY_ERR_INT_CLR + description: Set this bit to clear parity_err_int_raw interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: FRM_ERR_INT_CLR + description: Set this bit to clear frm_err_int_raw interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: RXFIFO_OVF_INT_CLR + description: Set this bit to clear rxfifo_ovf_int_raw interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: DSR_CHG_INT_CLR + description: Set this bit to clear the dsr_chg_int_raw interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CTS_CHG_INT_CLR + description: Set this bit to clear the cts_chg_int_raw interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: BRK_DET_INT_CLR + description: Set this bit to clear the brk_det_int_raw interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: RXFIFO_TOUT_INT_CLR + description: Set this bit to clear the rxfifo_tout_int_raw interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SW_XON_INT_CLR + description: Set this bit to clear the sw_xon_int_raw interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SW_XOFF_INT_CLR + description: Set this bit to clear the sw_xoff_int_raw interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: GLITCH_DET_INT_CLR + description: Set this bit to clear the glitch_det_int_raw interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TX_BRK_DONE_INT_CLR + description: Set this bit to clear the tx_brk_done_int_raw interrupt.. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: TX_BRK_IDLE_DONE_INT_CLR + description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: TX_DONE_INT_CLR + description: Set this bit to clear the tx_done_int_raw interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: AT_CMD_CHAR_DET_INT_CLR + description: Set this bit to clear the at_cmd_char_det_int_raw interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: WAKEUP_INT_CLR + description: Set this bit to clear the uart_wakeup_int_raw interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - register: + name: CLKDIV_SYNC + description: Clock divider configuration + addressOffset: 20 + size: 32 + resetValue: 694 + fields: + - name: CLKDIV + description: The integral part of the frequency divider factor. + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: CLKDIV_FRAG + description: The decimal part of the frequency divider factor. + bitOffset: 20 + bitWidth: 4 + access: read-write + - register: + name: RX_FILT + description: Rx Filter configuration + addressOffset: 24 + size: 32 + resetValue: 8 + fields: + - name: GLITCH_FILT + description: when input pulse width is lower than this value the pulse is ignored. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GLITCH_FILT_EN + description: Set this bit to enable Rx signal filter. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: STATUS + description: UART status register + addressOffset: 28 + size: 32 + resetValue: 3758145536 + fields: + - name: RXFIFO_CNT + description: Stores the byte number of valid data in Rx-FIFO. + bitOffset: 3 + bitWidth: 5 + access: read-only + - name: DSRN + description: The register represent the level value of the internal uart dsr signal. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: CTSN + description: This register represent the level value of the internal uart cts signal. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: RXD + description: This register represent the level value of the internal uart rxd signal. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TXFIFO_CNT + description: Stores the byte number of data in Tx-FIFO. + bitOffset: 19 + bitWidth: 5 + access: read-only + - name: DTRN + description: This bit represents the level of the internal uart dtr signal. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: RTSN + description: This bit represents the level of the internal uart rts signal. + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: TXD + description: This bit represents the level of the internal uart txd signal. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CONF0_SYNC + description: Configuration register 0 + addressOffset: 32 + size: 32 + resetValue: 28 + fields: + - name: PARITY + description: This register is used to configure the parity check mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PARITY_EN + description: Set this bit to enable uart parity check. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BIT_NUM + description: This register is used to set the length of data. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: STOP_BIT_NUM + description: This register is used to set the length of stop bit. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: TXD_BRK + description: Set this bit to enbale transmitter to send NULL when the process of sending data is done. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: LOOPBACK + description: Set this bit to enable uart loopback test mode. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_FLOW_EN + description: Set this bit to enable flow control function for transmitter. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: RXD_INV + description: Set this bit to inverse the level value of uart rxd signal. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TXD_INV + description: Set this bit to inverse the level value of uart txd signal. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DIS_RX_DAT_OVF + description: Disable UART Rx data overflow detect. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: ERR_WR_MASK + description: "1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: MEM_CLK_EN + description: UART memory clock gate enable signal. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SW_RTS + description: This register is used to configure the software rts signal which is used in software flow control. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: RXFIFO_RST + description: Set this bit to reset the uart receive-FIFO. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TXFIFO_RST + description: Set this bit to reset the uart transmit-FIFO. + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: CONF1 + description: Configuration register 1 + addressOffset: 36 + size: 32 + resetValue: 24672 + fields: + - name: RXFIFO_FULL_THRHD + description: It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + bitOffset: 3 + bitWidth: 5 + access: read-write + - name: TXFIFO_EMPTY_THRHD + description: It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + bitOffset: 11 + bitWidth: 5 + access: read-write + - name: CTS_INV + description: Set this bit to inverse the level value of uart cts signal. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DSR_INV + description: Set this bit to inverse the level value of uart dsr signal. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: RTS_INV + description: Set this bit to inverse the level value of uart rts signal. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: DTR_INV + description: Set this bit to inverse the level value of uart dtr signal. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SW_DTR + description: This register is used to configure the software dtr signal which is used in software flow control. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers." + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + name: HWFC_CONF_SYNC + description: Hardware flow-control configuration + addressOffset: 44 + size: 32 + fields: + - name: RX_FLOW_THRHD + description: This register is used to configure the maximum amount of data that can be received when hardware flow control works. + bitOffset: 3 + bitWidth: 5 + access: read-write + - name: RX_FLOW_EN + description: This is the flow enable bit for UART receiver. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: SLEEP_CONF0 + description: UART sleep configure register 0 + addressOffset: 48 + size: 32 + fields: + - name: WK_CHAR1 + description: This register restores the specified wake up char1 to wake up + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: WK_CHAR2 + description: This register restores the specified wake up char2 to wake up + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: WK_CHAR3 + description: This register restores the specified wake up char3 to wake up + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: WK_CHAR4 + description: This register restores the specified wake up char4 to wake up + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: SLEEP_CONF1 + description: UART sleep configure register 1 + addressOffset: 52 + size: 32 + fields: + - name: WK_CHAR0 + description: This register restores the specified char0 to wake up + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: SLEEP_CONF2 + description: UART sleep configure register 2 + addressOffset: 56 + size: 32 + resetValue: 1319152 + fields: + - name: ACTIVE_THRESHOLD + description: The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: RX_WAKE_UP_THRHD + description: In wake up mode 1 this field is used to set the received data number threshold to wake up chip. + bitOffset: 13 + bitWidth: 5 + access: read-write + - name: WK_CHAR_NUM + description: This register is used to select number of wake up char. + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: WK_CHAR_MASK + description: This register is used to mask wake up char. + bitOffset: 21 + bitWidth: 5 + access: read-write + - name: WK_MODE_SEL + description: "This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than" + bitOffset: 26 + bitWidth: 2 + access: read-write + - register: + name: SWFC_CONF0_SYNC + description: Software flow-control character configuration + addressOffset: 60 + size: 32 + resetValue: 4881 + fields: + - name: XON_CHAR + description: This register stores the Xon flow control char. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: XOFF_CHAR + description: This register stores the Xoff flow control char. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: XON_XOFF_STILL_SEND + description: "In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SW_FLOW_CON_EN + description: Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: XONOFF_DEL + description: Set this bit to remove flow control char from the received data. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: FORCE_XON + description: Set this bit to enable the transmitter to go on sending data. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: FORCE_XOFF + description: Set this bit to stop the transmitter from sending data. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SEND_XON + description: Set this bit to send Xon char. It is cleared by hardware automatically. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SEND_XOFF + description: Set this bit to send Xoff char. It is cleared by hardware automatically. + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: SWFC_CONF1 + description: Software flow-control character configuration + addressOffset: 64 + size: 32 + resetValue: 24576 + fields: + - name: XON_THRESHOLD + description: When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char. + bitOffset: 3 + bitWidth: 5 + access: read-write + - name: XOFF_THRESHOLD + description: When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char. + bitOffset: 11 + bitWidth: 5 + access: read-write + - register: + name: TXBRK_CONF_SYNC + description: Tx Break character configuration + addressOffset: 68 + size: 32 + resetValue: 10 + fields: + - name: TX_BRK_NUM + description: This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: IDLE_CONF_SYNC + description: Frame-end idle configuration + addressOffset: 72 + size: 32 + resetValue: 262400 + fields: + - name: RX_IDLE_THRHD + description: It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: TX_IDLE_NUM + description: This register is used to configure the duration time between transfers. + bitOffset: 10 + bitWidth: 10 + access: read-write + - register: + name: RS485_CONF_SYNC + description: RS485 mode configuration + addressOffset: 76 + size: 32 + fields: + - name: DL0_EN + description: Set this bit to delay the stop bit by 1 bit. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DL1_EN + description: Set this bit to delay the stop bit by 1 bit. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: AT_CMD_PRECNT_SYNC + description: Pre-sequence timing configuration + addressOffset: 80 + size: 32 + resetValue: 2305 + fields: + - name: PRE_IDLE_NUM + description: This register is used to configure the idle duration time before the first at_cmd is received by receiver. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_POSTCNT_SYNC + description: Post-sequence timing configuration + addressOffset: 84 + size: 32 + resetValue: 2305 + fields: + - name: POST_IDLE_NUM + description: This register is used to configure the duration time between the last at_cmd and the next data. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_GAPTOUT_SYNC + description: Timeout configuration + addressOffset: 88 + size: 32 + resetValue: 11 + fields: + - name: RX_GAP_TOUT + description: This register is used to configure the duration time between the at_cmd chars. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_CHAR_SYNC + description: AT escape sequence detection configuration + addressOffset: 92 + size: 32 + resetValue: 811 + fields: + - name: AT_CMD_CHAR + description: This register is used to configure the content of at_cmd char. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CHAR_NUM + description: This register is used to configure the num of continuous at_cmd chars received by receiver. + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: MEM_CONF + description: UART memory power configuration + addressOffset: 96 + size: 32 + fields: + - name: MEM_FORCE_PD + description: Set this bit to force power down UART memory. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PU + description: Set this bit to force power up UART memory. + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: TOUT_CONF_SYNC + description: UART threshold and allocation configuration + addressOffset: 100 + size: 32 + resetValue: 40 + fields: + - name: RX_TOUT_EN + description: "This is the enble bit for uart receiver's timeout function." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_TOUT_FLOW_DIS + description: Set this bit to stop accumulating idle_cnt when hardware flow control works. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_TOUT_THRHD + description: This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + bitOffset: 2 + bitWidth: 10 + access: read-write + - register: + name: MEM_TX_STATUS + description: Tx-SRAM write and read offset address. + addressOffset: 104 + size: 32 + fields: + - name: TX_SRAM_WADDR + description: This register stores the offset write address in Tx-SRAM. + bitOffset: 3 + bitWidth: 5 + access: read-only + - name: TX_SRAM_RADDR + description: This register stores the offset read address in Tx-SRAM. + bitOffset: 12 + bitWidth: 5 + access: read-only + - register: + name: MEM_RX_STATUS + description: Rx-SRAM write and read offset address. + addressOffset: 108 + size: 32 + resetValue: 65664 + fields: + - name: RX_SRAM_RADDR + description: This register stores the offset read address in RX-SRAM. + bitOffset: 3 + bitWidth: 5 + access: read-only + - name: RX_SRAM_WADDR + description: This register stores the offset write address in Rx-SRAM. + bitOffset: 12 + bitWidth: 5 + access: read-only + - register: + name: FSM_STATUS + description: UART transmit and receive status. + addressOffset: 112 + size: 32 + fields: + - name: ST_URX_OUT + description: This is the status register of receiver. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: ST_UTX_OUT + description: This is the status register of transmitter. + bitOffset: 4 + bitWidth: 4 + access: read-only + - register: + name: CLK_CONF + description: UART core clock configuration + addressOffset: 136 + size: 32 + resetValue: 50331648 + fields: + - name: TX_SCLK_EN + description: Set this bit to enable UART Tx clock. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: RX_SCLK_EN + description: Set this bit to enable UART Rx clock. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TX_RST_CORE + description: Write 1 then write 0 to this bit to reset UART Tx. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RX_RST_CORE + description: Write 1 then write 0 to this bit to reset UART Rx. + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: UART Version register + addressOffset: 140 + size: 32 + resetValue: 36720720 + fields: + - name: DATE + description: This is the version register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: AFIFO_STATUS + description: UART AFIFO Status + addressOffset: 144 + size: 32 + resetValue: 10 + fields: + - name: TX_AFIFO_FULL + description: Full signal of APB TX AFIFO. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_AFIFO_EMPTY + description: Empty signal of APB TX AFIFO. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_AFIFO_FULL + description: Full signal of APB RX AFIFO. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: RX_AFIFO_EMPTY + description: Empty signal of APB RX AFIFO. + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: REG_UPDATE + description: UART Registers Configuration Update register + addressOffset: 152 + size: 32 + fields: + - name: REG_UPDATE + description: Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: ID + description: UART ID register + addressOffset: 156 + size: 32 + resetValue: 1280 + fields: + - name: ID + description: This register is used to configure the uart_id. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: MCPWM0 + description: Motor Control Pulse-Width Modulation 0 + groupName: MCPWM + baseAddress: 1342963712 + addressBlock: + - offset: 0 + size: 332 + usage: registers + interrupt: + - name: PWM0 + value: 38 + registers: + - register: + name: CLK_CFG + description: PWM clock prescaler register. + addressOffset: 0 + size: 32 + fields: + - name: CLK_PRESCALE + description: "Configures the prescaler value of clock, so that the period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + dim: 3 + dimIncrement: 16 + name: TIMER%s_CFG0 + description: PWM timer%s period and update method configuration register. + addressOffset: 4 + size: 32 + resetValue: 65280 + fields: + - name: TIMER_PRESCALE + description: "Configures the prescaler value of timer%s, so that the period of PT0_clk = Period of PWM_clk * (PWM_TIMER%s_PRESCALE + 1)" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TIMER_PERIOD + description: Configures the period shadow of PWM timer%s + bitOffset: 8 + bitWidth: 16 + access: read-write + - name: TIMER_PERIOD_UPMETHOD + description: "Configures the update method for active register of PWM timer%s period.\\\\0: Immediate\\\\1: TEZ\\\\2: Sync\\\\3: TEZ or sync\\\\TEZ here and below means timer equal zero event" + bitOffset: 24 + bitWidth: 2 + access: read-write + - register: + dim: 3 + dimIncrement: 16 + name: TIMER%s_CFG1 + description: PWM timer%s working mode and start/stop control register. + addressOffset: 8 + size: 32 + fields: + - name: TIMER_START + description: "Configures whether or not to start/stop PWM timer%s.\\\\0: If PWM timer%s starts, then stops at TEZ\\\\1: If timer%s starts, then stops at TEP\\\\2: PWM timer%s starts and runs on\\\\3: Timer%s starts and stops at the next TEZ\\\\4: Timer0 starts and stops at the next TEP.\\\\TEP here and below means the event that happens when the timer equals to period" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: TIMER_MOD + description: "Configures the working mode of PWM timer%s.\\\\0: Freeze\\\\1: Increase mode\\\\2: Decrease mode\\\\3: Up-down mode" + bitOffset: 3 + bitWidth: 2 + access: read-write + - register: + dim: 3 + dimIncrement: 16 + name: TIMER%s_SYNC + description: PWM timer%s sync function configuration register. + addressOffset: 12 + size: 32 + fields: + - name: TIMER_SYNCI_EN + description: "Configures whether or not to enable timer%s reloading with phase on sync input event is enabled.\\\\0: Disable\\\\1: Enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SW + description: Configures the generation of software sync. Toggling this bit will trigger a software sync. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER_SYNCO_SEL + description: "Configures the selection of PWM timer%s sync_out.\\\\0: Sync_in\\\\1: TEZ\\\\2: TEP\\\\3: Invalid, sync_out selects noting" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: TIMER_PHASE + description: Configures the phase for timer%s reload on sync event. + bitOffset: 4 + bitWidth: 16 + access: read-write + - name: TIMER_PHASE_DIRECTION + description: "Configures the PWM timer%s's direction when timer%s mode is up-down mode.\\\\0: Increase\\\\1: Decrease" + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + dim: 3 + dimIncrement: 16 + name: TIMER%s_STATUS + description: PWM timer%s status register. + addressOffset: 16 + size: 32 + fields: + - name: TIMER_VALUE + description: Represents current PWM timer%s counter value. + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: TIMER_DIRECTION + description: "Represents current PWM timer%s counter direction.\\\\0: Increment\\\\1: Decrement" + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: TIMER_SYNCI_CFG + description: Synchronization input selection register for PWM timers. + addressOffset: 52 + size: 32 + fields: + - name: TIMER0_SYNCISEL + description: "Configures the selection of sync input for PWM timer0.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: TIMER1_SYNCISEL + description: "Configures the selection of sync input for PWM timer1.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected" + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: TIMER2_SYNCISEL + description: "Configures the selection of sync input for PWM timer2.\\\\1: PWM timer0 sync_out\\\\2: PWM timer1 sync_out\\\\3: PWM timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\Other values: No sync input selected" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: EXTERNAL_SYNCI0_INVERT + description: "Configures whether or not to invert SYNC0 from GPIO matrix.\\\\0: Not invert\\\\1: Invert" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: EXTERNAL_SYNCI1_INVERT + description: "Configures whether or not to invert SYNC1 from GPIO matrix.\\\\0: Not invert\\\\1: Invert" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: EXTERNAL_SYNCI2_INVERT + description: "Configures whether or not to invert SYNC2 from GPIO matrix.\\\\0: Not invert\\\\1: Invert" + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: OPERATOR_TIMERSEL + description: "PWM operator's timer select register" + addressOffset: 56 + size: 32 + fields: + - name: OPERATOR0_TIMERSEL + description: "Configures which PWM timer will be the timing reference for PWM operator0.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: OPERATOR1_TIMERSEL + description: "Configures which PWM timer will be the timing reference for PWM operator1.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: OPERATOR2_TIMERSEL + description: "Configures which PWM timer will be the timing reference for PWM operator2.\\\\0: Timer0\\\\1: Timer1\\\\2: Timer2\\\\3: Invalid, will select timer2" + bitOffset: 4 + bitWidth: 2 + access: read-write + - register: + dim: 3 + dimIncrement: 56 + name: GEN%s_STMP_CFG + description: Generator%s time stamp registers A and B transfer status and update method register + addressOffset: 60 + size: 32 + fields: + - name: CMPR_A_UPMETHOD + description: "Configures the update method for PWM generator %s time stamp A's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update" + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: CMPR_B_UPMETHOD + description: "Configures the update method for PWM generator %s time stamp B's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update" + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: CMPR_A_SHDW_FULL + description: "Represents whether or not generator%s time stamp A's shadow reg is transferred.\\\\0: A's active reg has been updated with shadow register latest value.\\\\1: A's shadow reg is filled and waiting to be transferred to A's active reg" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CMPR_B_SHDW_FULL + description: "Represents whether or not generator%s time stamp B's shadow reg is transferred.\\\\0: B's active reg has been updated with shadow register latest value.\\\\1: B's shadow reg is filled and waiting to be transferred to B's active reg" + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + dim: 3 + dimIncrement: 56 + name: GEN%s_TSTMP_A + description: "Generator%s time stamp A's shadow register" + addressOffset: 64 + size: 32 + fields: + - name: CMPR_A + description: "Configures the value of PWM generator %s time stamp A's shadow register." + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + dim: 3 + dimIncrement: 56 + name: GEN%s_TSTMP_B + description: "Generator%s time stamp B's shadow register" + addressOffset: 68 + size: 32 + fields: + - name: CMPR_B + description: "Configures the value of PWM generator %s time stamp B's shadow register." + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + dim: 3 + dimIncrement: 56 + name: GEN%s_CFG0 + description: Generator%s fault event T0 and T1 configuration register + addressOffset: 72 + size: 32 + fields: + - name: GEN_CFG_UPMETHOD + description: "Configures update method for PWM generator %s's active register.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update" + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: GEN_T0_SEL + description: "Configures source selection for PWM generator %s event_t0, take effect immediately.\\\\0: fault_event0\\\\1: fault_event1\\\\2: fault_event2\\\\3: sync_taken\\\\4: Invalid, Select nothing" + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: GEN_T1_SEL + description: "Configures source selection for PWM generator %s event_t1, take effect immediately.\\\\0: fault_event0\\\\1: fault_event1\\\\2: fault_event2\\\\3: sync_taken\\\\4: Invalid, Select nothing" + bitOffset: 7 + bitWidth: 3 + access: read-write + - register: + dim: 3 + dimIncrement: 56 + name: GEN%s_FORCE + description: Generator%s output signal force mode register. + addressOffset: 76 + size: 32 + resetValue: 32 + fields: + - name: GEN_CNTUFORCE_UPMETHOD + description: "Configures update method for continuous software force of PWM generator%s.\\\\0: Immediately\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: TEA\\\\Bit3 is set to 1: TEB\\\\Bit4 is set to 1: Sync\\\\Bit5 is set to 1: Disable update. TEA/B here and below means an event generated when the timer's value equals to that of register A/B." + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: GEN_A_CNTUFORCE_MODE + description: "Configures continuous software force mode for PWM%s A.\\\\0: Disabled\\\\1: Low\\\\2: High\\\\3: Disabled" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: GEN_B_CNTUFORCE_MODE + description: "Configures continuous software force mode for PWM%s B.\\\\0: Disabled\\\\1: Low\\\\2: High\\\\3: Disabled" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: GEN_A_NCIFORCE + description: "Configures the generation of non-continuous immediate software-force event for PWM%s A, a toggle will trigger a force event." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GEN_A_NCIFORCE_MODE + description: "Configures non-continuous immediate software force mode for PWM%s A.\\\\0: Disabled\\\\1: Low\\\\2: High\\\\3: Disabled" + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: GEN_B_NCIFORCE + description: "Configures the generation of non-continuous immediate software-force event for PWM%s B, a toggle will trigger a force event." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: GEN_B_NCIFORCE_MODE + description: "Configures non-continuous immediate software force mode for PWM%s B.\\\\0: Disabled\\\\1: Low\\\\2: High\\\\3: Disabled" + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + dim: 3 + dimIncrement: 56 + name: GEN%s_A + description: PWM%s output signal A actions configuration register + addressOffset: 80 + size: 32 + fields: + - name: UTEZ + description: "Configures action on PWM%s A triggered by event TEZ when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + description: "Configures action on PWM%s A triggered by event TEP when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + description: "Configures action on PWM%s A triggered by event TEA when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + description: "Configures action on PWM%s A triggered by event TEB when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + description: "Configures action on PWM%s A triggered by event_t0 when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + description: "Configures action on PWM%s A triggered by event_t1 when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + description: "Configures action on PWM%s A triggered by event TEZ when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle" + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + description: "Configures action on PWM%s A triggered by event TEP when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle" + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + description: "Configures action on PWM%s A triggered by event TEA when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle" + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + description: "Configures action on PWM%s A triggered by event TEB when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle" + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + description: "Configures action on PWM%s A triggered by event_t0 when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle" + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + description: "Configures action on PWM%s A triggered by event_t1 when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + dim: 3 + dimIncrement: 56 + name: GEN%s_B + description: PWM%s output signal B actions configuration register + addressOffset: 84 + size: 32 + fields: + - name: UTEZ + description: "Configures action on PWM%s B triggered by event TEZ when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + description: "Configures action on PWM%s B triggered by event TEP when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + description: "Configures action on PWM%s B triggered by event TEA when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + description: "Configures action on PWM%s B triggered by event TEB when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + description: "Configures action on PWM%s B triggered by event_t0 when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + description: "Configures action on PWM%s B triggered by event_t1 when timer increasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + description: "Configures action on PWM%s B triggered by event TEZ when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle" + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + description: "Configures action on PWM%s B triggered by event TEP when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle" + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + description: "Configures action on PWM%s B triggered by event TEA when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle" + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + description: "Configures action on PWM%s B triggered by event TEB when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle" + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + description: "Configures action on PWM%s B triggered by event_t0 when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle" + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + description: "Configures action on PWM%s B triggered by event_t1 when timer decreasing.\\\\0: No change\\\\1: Low\\\\2: High\\\\3: Toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + dim: 3 + dimIncrement: 56 + name: DT%s_CFG + description: Dead time configuration register + addressOffset: 88 + size: 32 + resetValue: 98304 + fields: + - name: DB_FED_UPMETHOD + description: "Configures update method for FED (Falling edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update" + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: DB_RED_UPMETHOD + description: "Configures update method for RED (rising edge delay) active register.\\\\0: Immediate\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP\\\\Bit2 is set to 1: Sync\\\\Bit3 is set to 1: Disable the update" + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: DB_DEB_MODE + description: "Configures S8 in table, dual-edge B mode.\\\\0: fed/red take effect on different path separately\\\\1: fed/red take effect on B path, A out is in bypass or dulpB mode" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DB_A_OUTSWAP + description: Configures S6 in table. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DB_B_OUTSWAP + description: Configures S7 in table. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DB_RED_INSEL + description: Configures S4 in table. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DB_FED_INSEL + description: Configures S5 in table. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DB_RED_OUTINVERT + description: Configures S2 in table. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DB_FED_OUTINVERT + description: Configures S3 in table. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DB_A_OUTBYPASS + description: Configures S1 in table. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DB_B_OUTBYPASS + description: Configures S0 in table. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DB_CLK_SEL + description: "Configures dead time generator %s clock selection.\\\\0: PWM_clk\\\\1: PT_clk" + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + dim: 3 + dimIncrement: 56 + name: DT%s_FED_CFG + description: Falling edge delay (FED) shadow register + addressOffset: 92 + size: 32 + fields: + - name: DB_FED + description: Configures shadow register for FED. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + dim: 3 + dimIncrement: 56 + name: DT%s_RED_CFG + description: Rising edge delay (RED) shadow register + addressOffset: 96 + size: 32 + fields: + - name: DB_RED + description: Configures shadow register for RED. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + dim: 3 + dimIncrement: 56 + name: CARRIER%s_CFG + description: Carrier%s configuration register + addressOffset: 100 + size: 32 + fields: + - name: CHOPPER_EN + description: "Configures whether or not to enable carrier%s.\\\\0: Bypassed\\\\1: Enabled" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CHOPPER_PRESCALE + description: "Configures the prescale value of PWM carrier%s clock (PC_clk), so that period of PC_clk = period of PWM_clk * (PWM_CARRIER%s_PRESCALE + 1)" + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CHOPPER_DUTY + description: Configures carrier duty. Duty = PWM_CARRIER%s_DUTY / 8 + bitOffset: 5 + bitWidth: 3 + access: read-write + - name: CHOPPER_OSHTWTH + description: "Configures width of the first pulse. Measurement unit: Periods of the carrier." + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: CHOPPER_OUT_INVERT + description: "Configures whether or not to invert the output of PWM%s A and PWM%s B for this submodule.\\\\0: Normal\\\\1: Invert" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CHOPPER_IN_INVERT + description: "Configures whether or not to invert the input of PWM%s A and PWM%s B for this submodule.\\\\0: Normal\\\\1: Invert" + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + dim: 3 + dimIncrement: 56 + name: FH%s_CFG0 + description: PWM%s A and PWM%s B trip events actions configuration register + addressOffset: 104 + size: 32 + fields: + - name: TZ_SW_CBC + description: "Configures whether or not to enable software force cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TZ_F2_CBC + description: "Configures whether or not event_f2 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TZ_F1_CBC + description: "Configures whether or not event_f1 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TZ_F0_CBC + description: "Configures whether or not event_f0 will trigger cycle-by-cycle mode action.\\\\0: Disable\\\\1: Enable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TZ_SW_OST + description: "Configures whether or not to enable software force one-shot mode action.\\\\0: Disable\\\\1: Enable" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TZ_F2_OST + description: "Configures whether or not event_f2 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TZ_F1_OST + description: "Configures whether or not event_f1 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TZ_F0_OST + description: "Configures whether or not event_f0 will trigger one-shot mode action.\\\\0: Disable\\\\1: Enable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TZ_A_CBC_D + description: "Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: TZ_A_CBC_U + description: "Configures cycle-by-cycle mode action on PWM%s A when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: TZ_A_OST_D + description: "Configures one-shot mode action on PWM%s A when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle" + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: TZ_A_OST_U + description: "Configures one-shot mode action on PWM%s A when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle" + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: TZ_B_CBC_D + description: "Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle" + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: TZ_B_CBC_U + description: "Configures cycle-by-cycle mode action on PWM%s B when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle" + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: TZ_B_OST_D + description: "Configures one-shot mode action on PWM%s B when fault event occurs and timer is decreasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle" + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TZ_B_OST_U + description: "Configures one-shot mode action on PWM%s B when fault event occurs and timer is increasing.\\\\0: Do nothing\\\\1: Force low\\\\2: Force high\\\\3: Toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + dim: 3 + dimIncrement: 56 + name: FH%s_CFG1 + description: Software triggers for fault handler actions configuration register + addressOffset: 108 + size: 32 + fields: + - name: TZ_CLR_OST + description: Configures the generation of software one-shot mode action clear. A toggle (software negate its value) triggers a clear for on going one-shot mode action. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TZ_CBCPULSE + description: "Configures the refresh moment selection of cycle-by-cycle mode action.\\\\0: Select nothing, will not refresh\\\\Bit0 is set to 1: TEZ\\\\Bit1 is set to 1: TEP" + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: TZ_FORCE_CBC + description: Configures the generation of software cycle-by-cycle mode action. A toggle (software negate its value) triggers a cycle-by-cycle mode action. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TZ_FORCE_OST + description: Configures the generation of software one-shot mode action. A toggle (software negate its value) triggers a one-shot mode action. + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + dim: 3 + dimIncrement: 56 + name: FH%s_STATUS + description: Fault events status register + addressOffset: 112 + size: 32 + fields: + - name: TZ_CBC_ON + description: "Represents whether or not an cycle-by-cycle mode action is on going.\\\\0:No action\\\\1: On going" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TZ_OST_ON + description: "Represents whether or not an one-shot mode action is on going.\\\\0:No action\\\\1: On going" + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: FAULT_DETECT + description: Fault detection configuration and status register + addressOffset: 228 + size: 32 + fields: + - name: F0_EN + description: "Configures whether or not to enable event_f0 generation.\\\\0: Disable\\\\1: Enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: F1_EN + description: "Configures whether or not to enable event_f1 generation.\\\\0: Disable\\\\1: Enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: F2_EN + description: "Configures whether or not to enable event_f2 generation.\\\\0: Disable\\\\1: Enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: F0_POLE + description: "Configures event_f0 trigger polarity on FAULT0 source from GPIO matrix.\\\\0: Level low\\\\1: Level high" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: F1_POLE + description: "Configures event_f1 trigger polarity on FAULT1 source from GPIO matrix.\\\\0: Level low\\\\1: Level high" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: F2_POLE + description: "Configures event_f2 trigger polarity on FAULT2 source from GPIO matrix.\\\\0: Level low\\\\1: Level high" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: EVENT_F0 + description: "Represents whether or not an event_f0 is on going.\\\\0: No action\\\\1: On going" + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: EVENT_F1 + description: "Represents whether or not an event_f1 is on going.\\\\0: No action\\\\1: On going" + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: EVENT_F2 + description: "Represents whether or not an event_f2 is on going.\\\\0: No action\\\\1: On going" + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: CAP_TIMER_CFG + description: Capture timer configuration register + addressOffset: 232 + size: 32 + fields: + - name: CAP_TIMER_EN + description: "Configures whether or not to enable capture timer increment.\\\\0: Disable\\\\1: Enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CAP_SYNCI_EN + description: "Configures whether or not to enable capture timer sync.\\\\0: Disable\\\\1: Enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CAP_SYNCI_SEL + description: "Configures the selection of capture module sync input.\\\\0: None\\\\1: Timer0 sync_out\\\\2: Timer1 sync_out\\\\3: Timer2 sync_out\\\\4: SYNC0 from GPIO matrix\\\\5: SYNC1 from GPIO matrix\\\\6: SYNC2 from GPIO matrix\\\\7: None" + bitOffset: 2 + bitWidth: 3 + access: read-write + - name: CAP_SYNC_SW + description: "Configures the generation of a capture timer sync when reg_cap_synci_en is 1.\\\\0: Invalid, No effect\\\\1: Trigger a capture timer sync, capture timer is loaded with value in phase register" + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: CAP_TIMER_PHASE + description: Capture timer sync phase register + addressOffset: 236 + size: 32 + fields: + - name: CAP_PHASE + description: Configures phase value for capture timer sync operation. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 3 + dimIncrement: 4 + name: CAP_CH%s_CFG + description: Capture channel %s configuration register + addressOffset: 240 + size: 32 + fields: + - name: CAP_EN + description: "Configures whether or not to enable capture on channel %s.\\\\0: Disable\\\\1: Enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CAP_MODE + description: "Configures which edge of capture on channel %s after prescaling is used.\\\\0: None\\\\Bit0 is set to 1: Rnable capture on the negative edge\\\\Bit1 is set to 1: Enable capture on the positive edge" + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: CAP_PRESCALE + description: Configures prescale value on possitive edge of CAP%s. Prescale value = PWM_CAP%s_PRESCALE + 1 + bitOffset: 3 + bitWidth: 8 + access: read-write + - name: CAP_IN_INVERT + description: "Configures whether or not to invert CAP%s from GPIO matrix before prescale.\\\\0: Normal\\\\1: Invert" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CAP_SW + description: "Configures the generation of software capture.\\\\0: Invalid, No effect\\\\1: Trigger a software forced capture on channel %s" + bitOffset: 12 + bitWidth: 1 + access: write-only + - register: + dim: 3 + dimIncrement: 4 + name: CAP_CH%s + description: CAP%s capture value register + addressOffset: 252 + size: 32 + fields: + - name: CAP_VALUE + description: Represents value of last capture on CAP%s + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CAP_STATUS + description: Last capture trigger edge information register + addressOffset: 264 + size: 32 + fields: + - name: CAP0_EDGE + description: "Represents edge of last capture trigger on channel0.\\\\0: Posedge\\\\1: Negedge" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CAP1_EDGE + description: "Represents edge of last capture trigger on channel1.\\\\0: Posedge\\\\1: Negedge" + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CAP2_EDGE + description: "Represents edge of last capture trigger on channel2.\\\\0: Posedge\\\\1: Negedge" + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: UPDATE_CFG + description: Generator Update configuration register + addressOffset: 268 + size: 32 + resetValue: 5 + fields: + - name: GLOBAL_UP_EN + description: "Configures whether or not to enable global update for all active registers in MCPWM module.\\\\0: Disable\\\\1: Enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: GLOBAL_FORCE_UP + description: Configures the generation of global forced update for all active registers in MCPWM module. A toggle (software invert its value) will trigger a global forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0/1/2_UP_EN are both set to 1. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OP0_UP_EN + description: "Configures whether or not to enable update of active registers in PWM operator0. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\\\0: Disable\\\\1: Enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OP0_FORCE_UP + description: Configures the generation of forced update for active registers in PWM operator0. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP0_UP_EN are both set to 1. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OP1_UP_EN + description: "Configures whether or not to enable update of active registers in PWM operator1. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\\\0: Disable\\\\1: Enable" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OP1_FORCE_UP + description: Configures the generation of forced update for active registers in PWM operator1. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP1_UP_EN are both set to 1. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OP2_UP_EN + description: "Configures whether or not to enable update of active registers in PWM operator2. Valid only when PWM_GLOBAL_UP_EN is set to 1.\\\\0: Disable\\\\1: Enable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OP2_FORCE_UP + description: Configures the generation of forced update for active registers in PWM operator2. A toggle (software invert its value) will trigger a forced update. Valid only when MCPWM_GLOBAL_UP_EN and MCPWM_OP2_UP_EN are both set to 1. + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: INT_ENA + description: Interrupt enable register + addressOffset: 272 + size: 32 + fields: + - name: TIMER0_STOP_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMER1_STOP_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER2_STOP_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TIMER0_TEZ_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TIMER1_TEZ_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TIMER2_TEZ_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TIMER0_TEP_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TIMER1_TEP_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TIMER2_TEP_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FAULT0_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FAULT1_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FAULT2_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FAULT0_CLR_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FAULT1_CLR_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FAULT2_CLR_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CMPR0_TEA_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CMPR1_TEA_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CMPR2_TEA_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: CMPR0_TEB_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: CMPR1_TEB_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: CMPR2_TEB_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TZ0_CBC_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM0." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: TZ1_CBC_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM1." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TZ2_CBC_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM2." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TZ0_OST_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM0." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TZ1_OST_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM1." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TZ2_OST_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM2." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CAP0_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: CAP1_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CAP2_INT_ENA + description: "Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2." + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: Interrupt raw status register + addressOffset: 276 + size: 32 + fields: + - name: TIMER0_STOP_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered when the timer 0 stops." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMER1_STOP_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered when the timer 1 stops." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER2_STOP_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered when the timer 2 stops." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TIMER0_TEZ_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEZ event." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TIMER1_TEZ_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEZ event." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TIMER2_TEZ_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEZ event." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TIMER0_TEP_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 0 TEP event." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TIMER1_TEP_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 1 TEP event." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TIMER2_TEP_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered by a PWM timer 2 TEP event." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FAULT0_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 starts." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FAULT1_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 starts." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FAULT2_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 starts." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FAULT0_CLR_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered when event_f0 clears." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FAULT1_CLR_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered when event_f1 clears." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FAULT2_CLR_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered when event_f2 clears." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CMPR0_TEA_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEA event" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CMPR1_TEA_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEA event" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CMPR2_TEA_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEA event" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: CMPR0_TEB_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 0 TEB event" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: CMPR1_TEB_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 1 TEB event" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: CMPR2_TEB_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered by a PWM operator 2 TEB event" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TZ0_CBC_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: TZ1_CBC_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TZ2_CBC_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TZ0_OST_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM0." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TZ1_OST_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM1." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TZ2_OST_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered by a one-shot mode action on PWM2." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CAP0_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP0." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: CAP1_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP1." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CAP2_INT_RAW + description: "Raw status bit: The raw interrupt status of the interrupt triggered by capture on CAP2." + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Interrupt masked status register + addressOffset: 280 + size: 32 + fields: + - name: TIMER0_STOP_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered when the timer 0 stops." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TIMER1_STOP_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered when the timer 1 stops." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TIMER2_STOP_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered when the timer 2 stops." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TIMER0_TEZ_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 0 TEZ event." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TIMER1_TEZ_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 1 TEZ event." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TIMER2_TEZ_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 2 TEZ event." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: TIMER0_TEP_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 0 TEP event." + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TIMER1_TEP_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 1 TEP event." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIMER2_TEP_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered by a PWM timer 2 TEP event." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: FAULT0_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered when event_f0 starts." + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: FAULT1_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered when event_f1 starts." + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: FAULT2_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered when event_f2 starts." + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: FAULT0_CLR_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered when event_f0 clears." + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: FAULT1_CLR_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered when event_f1 clears." + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: FAULT2_CLR_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered when event_f2 clears." + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: CMPR0_TEA_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 0 TEA event" + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: CMPR1_TEA_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 1 TEA event" + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: CMPR2_TEA_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 2 TEA event" + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: CMPR0_TEB_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 0 TEB event" + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: CMPR1_TEB_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 1 TEB event" + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: CMPR2_TEB_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered by a PWM operator 2 TEB event" + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: TZ0_CBC_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM0." + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: TZ1_CBC_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM1." + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: TZ2_CBC_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered by a cycle-by-cycle mode action on PWM2." + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: TZ0_OST_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM0." + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: TZ1_OST_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM1." + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: TZ2_OST_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered by a one-shot mode action on PWM2." + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: CAP0_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP0." + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: CAP1_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP1." + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: CAP2_INT_ST + description: "Masked status bit: The masked interrupt status of the interrupt triggered by capture on CAP2." + bitOffset: 29 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: Interrupt clear register + addressOffset: 284 + size: 32 + fields: + - name: TIMER0_STOP_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered when the timer 0 stops." + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TIMER1_STOP_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered when the timer 1 stops." + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TIMER2_STOP_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered when the timer 2 stops." + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TIMER0_TEZ_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEZ event." + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TIMER1_TEZ_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEZ event." + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: TIMER2_TEZ_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEZ event." + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TIMER0_TEP_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 0 TEP event." + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TIMER1_TEP_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 1 TEP event." + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: TIMER2_TEP_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered by a PWM timer 2 TEP event." + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: FAULT0_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered when event_f0 starts." + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: FAULT1_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered when event_f1 starts." + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: FAULT2_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered when event_f2 starts." + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: FAULT0_CLR_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered when event_f0 clears." + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: FAULT1_CLR_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered when event_f1 clears." + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: FAULT2_CLR_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered when event_f2 clears." + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: CMPR0_TEA_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEA event" + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: CMPR1_TEA_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEA event" + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: CMPR2_TEA_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEA event" + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: CMPR0_TEB_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 0 TEB event" + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: CMPR1_TEB_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 1 TEB event" + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: CMPR2_TEB_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered by a PWM operator 2 TEB event" + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: TZ0_CBC_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0." + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: TZ1_CBC_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1." + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: TZ2_CBC_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2." + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: TZ0_OST_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM0." + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: TZ1_OST_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM1." + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: TZ2_OST_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered by a one-shot mode action on PWM2." + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: CAP0_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered by capture on CAP0." + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: CAP1_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered by capture on CAP1." + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: CAP2_INT_CLR + description: "Clear bit: Write 1 to clear the interrupt triggered by capture on CAP2." + bitOffset: 29 + bitWidth: 1 + access: write-only + - register: + name: EVT_EN + description: Event enable register + addressOffset: 288 + size: 32 + fields: + - name: EVT_TIMER0_STOP_EN + description: "Configures whether or not to enable timer0 stop event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EVT_TIMER1_STOP_EN + description: "Configures whether or not to enable timer1 stop event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EVT_TIMER2_STOP_EN + description: "Configures whether or not to enable timer2 stop event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EVT_TIMER0_TEZ_EN + description: "Configures whether or not to enable timer0 equal zero event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: EVT_TIMER1_TEZ_EN + description: "Configures whether or not to enable timer1 equal zero event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: EVT_TIMER2_TEZ_EN + description: "Configures whether or not to enable timer2 equal zero event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: EVT_TIMER0_TEP_EN + description: "Configures whether or not to enable timer0 equal period event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: EVT_TIMER1_TEP_EN + description: "Configures whether or not to enable timer1 equal period event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: EVT_TIMER2_TEP_EN + description: "Configures whether or not to enable timer2 equal period event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: EVT_OP0_TEA_EN + description: "Configures whether or not to enable PWM generator0 timer equal a event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: EVT_OP1_TEA_EN + description: "Configures whether or not to enable PWM generator1 timer equal a event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: EVT_OP2_TEA_EN + description: "Configures whether or not to enable PWM generator2 timer equal a event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: EVT_OP0_TEB_EN + description: "Configures whether or not to enable PWM generator0 timer equal b event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: EVT_OP1_TEB_EN + description: "Configures whether or not to enable PWM generator1 timer equal b event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: EVT_OP2_TEB_EN + description: "Configures whether or not to enable PWM generator2 timer equal b event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: EVT_F0_EN + description: "Configures whether or not to enable fault0 event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: EVT_F1_EN + description: "Configures whether or not to enable fault1 event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: EVT_F2_EN + description: "Configures whether or not to enable fault2 event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: EVT_F0_CLR_EN + description: "Configures whether or not to enable fault0 clear event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: EVT_F1_CLR_EN + description: "Configures whether or not to enable fault1 clear event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: EVT_F2_CLR_EN + description: "Configures whether or not to enable fault2 clear event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: EVT_TZ0_CBC_EN + description: "Configures whether or not to enable cycle-by-cycle trip0 event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: EVT_TZ1_CBC_EN + description: "Configures whether or not to enable cycle-by-cycle trip1 event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: EVT_TZ2_CBC_EN + description: "Configures whether or not to enable cycle-by-cycle trip2 event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: EVT_TZ0_OST_EN + description: "Configures whether or not to enable one-shot trip0 event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: EVT_TZ1_OST_EN + description: "Configures whether or not to enable one-shot trip1 event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: EVT_TZ2_OST_EN + description: "Configures whether or not to enable one-shot trip2 event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: EVT_CAP0_EN + description: "Configures whether or not to enable capture0 event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: EVT_CAP1_EN + description: "Configures whether or not to enable capture1 event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: EVT_CAP2_EN + description: "Configures whether or not to enable capture2 event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: TASK_EN + description: Task enable register + addressOffset: 292 + size: 32 + fields: + - name: TASK_CMPR0_A_UP_EN + description: "Configures whether or not to enable PWM generator0 timer stamp A's shadow register update task receive.\\\\0: Disable\\\\1: Enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TASK_CMPR1_A_UP_EN + description: "Configures whether or not to enable PWM generator1 timer stamp A's shadow register update task receive.\\\\0: Disable\\\\1: Enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TASK_CMPR2_A_UP_EN + description: "Configures whether or not to enable PWM generator2 timer stamp A's shadow register update task receive.\\\\0: Disable\\\\1: Enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TASK_CMPR0_B_UP_EN + description: "Configures whether or not to enable PWM generator0 timer stamp B's shadow register update task receive.\\\\0: Disable\\\\1: Enable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TASK_CMPR1_B_UP_EN + description: "Configures whether or not to enable PWM generator1 timer stamp B's shadow register update task receive.\\\\0: Disable\\\\1: Enable" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TASK_CMPR2_B_UP_EN + description: "Configures whether or not to enable PWM generator2 timer stamp B's shadow register update task receive.\\\\0: Disable\\\\1: Enable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TASK_GEN_STOP_EN + description: "Configures whether or not to enable all PWM generate stop task receive.\\\\0: Disable\\\\1: Enable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TASK_TIMER0_SYNC_EN + description: "Configures whether or not to enable timer0 sync task receive.\\\\0: Disable\\\\1: Enable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TASK_TIMER1_SYNC_EN + description: "Configures whether or not to enable timer1 sync task receive.\\\\0: Disable\\\\1: Enable" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TASK_TIMER2_SYNC_EN + description: "Configures whether or not to enable timer2 sync task receive.\\\\0: Disable\\\\1: Enable" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TASK_TIMER0_PERIOD_UP_EN + description: "Configures whether or not to enable timer0 period update task receive.\\\\0: Disable\\\\1: Enable" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TASK_TIMER1_PERIOD_UP_EN + description: "Configures whether or not to enable timer1 period update task receive.\\\\0: Disable\\\\1: Enable" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TASK_TIMER2_PERIOD_UP_EN + description: "Configures whether or not to enable timer2 period update task receive.\\\\0: Disable\\\\1: Enable" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TASK_TZ0_OST_EN + description: "Configures whether or not to enable one shot trip0 task receive.\\\\0: Disable\\\\1: Enable" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TASK_TZ1_OST_EN + description: "Configures whether or not to enable one shot trip1 task receive.\\\\0: Disable\\\\1: Enable" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TASK_TZ2_OST_EN + description: "Configures whether or not to enable one shot trip2 task receive.\\\\0: Disable\\\\1: Enable" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TASK_CLR0_OST_EN + description: "Configures whether or not to enable one shot trip0 clear task receive.\\\\0: Disable\\\\1: Enable" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: TASK_CLR1_OST_EN + description: "Configures whether or not to enable one shot trip1 clear task receive.\\\\0: Disable\\\\1: Enable" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: TASK_CLR2_OST_EN + description: "Configures whether or not to enable one shot trip2 clear task receive.\\\\0: Disable\\\\1: Enable" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TASK_CAP0_EN + description: "Configures whether or not to enable capture0 task receive.\\\\0: Disable\\\\1: Enable" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: TASK_CAP1_EN + description: "Configures whether or not to enable capture1 task receive.\\\\0: Disable\\\\1: Enable" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TASK_CAP2_EN + description: "Configures whether or not to enable capture2 task receive.\\\\0: Disable\\\\1: Enable" + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + name: EVT_EN2 + description: Event enable register2 + addressOffset: 296 + size: 32 + fields: + - name: EVT_OP0_TEE1_EN + description: "Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E1_REG event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EVT_OP1_TEE1_EN + description: "Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E1_REG event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EVT_OP2_TEE1_EN + description: "Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E1_REG event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EVT_OP0_TEE2_EN + description: "Configures whether or not to enable PWM generator0 timer equal OP0_TSTMP_E2_REG event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: EVT_OP1_TEE2_EN + description: "Configures whether or not to enable PWM generator1 timer equal OP1_TSTMP_E2_REG event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: EVT_OP2_TEE2_EN + description: "Configures whether or not to enable PWM generator2 timer equal OP2_TSTMP_E2_REG event generate.\\\\0: Disable\\\\1: Enable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + dim: 3 + dimIncrement: 8 + name: OP%s_TSTMP_E1 + description: Generator%s timer stamp E1 value register + addressOffset: 300 + size: 32 + fields: + - name: OP_TSTMP_E1 + description: Configures generator%s timer stamp E1 value register + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + dim: 3 + dimIncrement: 8 + name: OP%s_TSTMP_E2 + description: Generator%s timer stamp E2 value register + addressOffset: 304 + size: 32 + fields: + - name: OP_TSTMP_E2 + description: Configures generator%s timer stamp E2 value register + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: CLK + description: Global configuration register + addressOffset: 324 + size: 32 + fields: + - name: EN + description: "Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: VERSION + description: Version register. + addressOffset: 328 + size: 32 + resetValue: 35725968 + fields: + - name: DATE + description: Configures the version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: MCPWM1 + description: Motor Control Pulse-Width Modulation 1 + baseAddress: 1342967808 + interrupt: + - name: PWM1 + value: 39 + derivedFrom: MCPWM0 + - name: PARL_IO + description: Parallel IO Controller + groupName: PARL_IO + baseAddress: 1343025152 + addressBlock: + - offset: 0 + size: 84 + usage: registers + interrupt: + - name: PARLIO_RX + value: 113 + - name: PARLIO_TX + value: 114 + registers: + - register: + name: RX_MODE_CFG + description: Parallel RX Sampling mode configuration register. + addressOffset: 0 + size: 32 + resetValue: 14680064 + fields: + - name: RX_EXT_EN_SEL + description: Configures rx external enable signal selection from IO PAD. + bitOffset: 21 + bitWidth: 4 + access: read-write + - name: RX_SW_EN + description: Set this bit to enable data sampling by software. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: RX_EXT_EN_INV + description: Set this bit to invert the external enable signal. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RX_PULSE_SUBMODE_SEL + description: "Configures the rxd pulse sampling submode. \n4'd0: positive pulse start(data bit included) && positive pulse end(data bit included)\n4'd1: positive pulse start(data bit included) && positive pulse end (data bit excluded)\n4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit included)\n4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded)\n4'd4: positive pulse start(data bit included) && length end\n4'd5: positive pulse start(data bit excluded) && length end" + bitOffset: 27 + bitWidth: 3 + access: read-write + - name: RX_SMP_MODE_SEL + description: "Configures the rxd sampling mode. \n2'b00: external level enable mode\n2'b01: external pulse enable mode \n2'b10: internal software enable mode" + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: RX_DATA_CFG + description: Parallel RX data configuration register. + addressOffset: 4 + size: 32 + resetValue: 1610612736 + fields: + - name: RX_BITLEN + description: Configures expected byte number of received data. + bitOffset: 9 + bitWidth: 19 + access: read-write + - name: RX_DATA_ORDER_INV + description: Set this bit to invert bit order of one byte sent from RX_FIFO to DMA. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: RX_BUS_WID_SEL + description: "Configures the rxd bus width. \n3'd0: bus width is 1.\n3'd1: bus width is 2.\n3'd2: bus width is 4.\n3'd3: bus width is 8." + bitOffset: 29 + bitWidth: 3 + access: read-write + - register: + name: RX_GENRL_CFG + description: Parallel RX general configuration register. + addressOffset: 8 + size: 32 + resetValue: 570417152 + fields: + - name: RX_GATING_EN + description: Set this bit to enable the clock gating of output rx clock. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RX_TIMEOUT_THRES + description: Configures threshold of timeout counter. + bitOffset: 13 + bitWidth: 16 + access: read-write + - name: RX_TIMEOUT_EN + description: Set this bit to enable timeout function to generate error eof. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: RX_EOF_GEN_SEL + description: "Configures the DMA eof generated mechanism. 1'b0: eof generated by data bit length. 1'b1: eof generated by external enable signal." + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: RX_START_CFG + description: Parallel RX Start configuration register. + addressOffset: 12 + size: 32 + fields: + - name: RX_START + description: Set this bit to start rx data sampling. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TX_DATA_CFG + description: Parallel TX data configuration register. + addressOffset: 16 + size: 32 + resetValue: 1610612736 + fields: + - name: TX_BITLEN + description: Configures expected byte number of sent data. + bitOffset: 9 + bitWidth: 19 + access: read-write + - name: TX_DATA_ORDER_INV + description: Set this bit to invert bit order of one byte sent from TX_FIFO to IO data. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: TX_BUS_WID_SEL + description: "Configures the txd bus width. \n3'd0: bus width is 1.\n3'd1: bus width is 2.\n3'd2: bus width is 4.\n3'd3: bus width is 8." + bitOffset: 29 + bitWidth: 3 + access: read-write + - register: + name: TX_START_CFG + description: Parallel TX Start configuration register. + addressOffset: 20 + size: 32 + fields: + - name: TX_START + description: Set this bit to start tx data transmit. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TX_GENRL_CFG + description: Parallel TX general configuration register. + addressOffset: 24 + size: 32 + fields: + - name: TX_EOF_GEN_SEL + description: "Configures the tx eof generated mechanism. 1'b0: eof generated by data bit length. 1'b1: eof generated by DMA eof." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_IDLE_VALUE + description: Configures bus value of transmitter in IDLE state. + bitOffset: 14 + bitWidth: 16 + access: read-write + - name: TX_GATING_EN + description: Set this bit to enable the clock gating of output tx clock. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TX_VALID_OUTPUT_EN + description: Set this bit to enable the output of tx data valid signal. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: FIFO_CFG + description: Parallel IO FIFO configuration register. + addressOffset: 28 + size: 32 + fields: + - name: TX_FIFO_SRST + description: Set this bit to reset async fifo in tx module. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: RX_FIFO_SRST + description: Set this bit to reset async fifo in rx module. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: REG_UPDATE + description: Parallel IO FIFO configuration register. + addressOffset: 32 + size: 32 + fields: + - name: RX_REG_UPDATE + description: Set this bit to update rx register configuration. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: ST + description: Parallel IO module status register0. + addressOffset: 36 + size: 32 + fields: + - name: TX_READY + description: Represents the status that tx is ready to transmit. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Parallel IO interrupt enable singal configuration register. + addressOffset: 40 + size: 32 + fields: + - name: TX_FIFO_REMPTY_INT_ENA + description: Set this bit to enable TX_FIFO_REMPTY_INT. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_FIFO_WOVF_INT_ENA + description: Set this bit to enable RX_FIFO_WOVF_INT. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TX_EOF_INT_ENA + description: Set this bit to enable TX_EOF_INT. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: Parallel IO interrupt raw singal status register. + addressOffset: 44 + size: 32 + fields: + - name: TX_FIFO_REMPTY_INT_RAW + description: The raw interrupt status of TX_FIFO_REMPTY_INT. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_FIFO_WOVF_INT_RAW + description: The raw interrupt status of RX_FIFO_WOVF_INT. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TX_EOF_INT_RAW + description: The raw interrupt status of TX_EOF_INT. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Parallel IO interrupt singal status register. + addressOffset: 48 + size: 32 + fields: + - name: TX_FIFO_REMPTY_INT_ST + description: The masked interrupt status of TX_FIFO_REMPTY_INT. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RX_FIFO_WOVF_INT_ST + description: The masked interrupt status of RX_FIFO_WOVF_INT. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TX_EOF_INT_ST + description: The masked interrupt status of TX_EOF_INT. + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: Parallel IO interrupt clear singal configuration register. + addressOffset: 52 + size: 32 + fields: + - name: TX_FIFO_REMPTY_INT_CLR + description: Set this bit to clear TX_FIFO_REMPTY_INT. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: RX_FIFO_WOVF_INT_CLR + description: Set this bit to clear RX_FIFO_WOVF_INT. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TX_EOF_INT_CLR + description: Set this bit to clear TX_EOF_INT. + bitOffset: 2 + bitWidth: 1 + access: write-only + - register: + name: RX_ST0 + description: Parallel IO RX status register0 + addressOffset: 56 + size: 32 + fields: + - name: RX_CNT + description: Indicates the cycle number of reading Rx FIFO. + bitOffset: 8 + bitWidth: 5 + access: read-only + - name: RX_FIFO_WR_BIT_CNT + description: Indicates the current written bit number into Rx FIFO. + bitOffset: 13 + bitWidth: 19 + access: read-only + - register: + name: RX_ST1 + description: Parallel IO RX status register1 + addressOffset: 60 + size: 32 + fields: + - name: RX_FIFO_RD_BIT_CNT + description: Indicates the current read bit number from Rx FIFO. + bitOffset: 13 + bitWidth: 19 + access: read-only + - register: + name: TX_ST0 + description: Parallel IO TX status register0 + addressOffset: 64 + size: 32 + fields: + - name: TX_CNT + description: Indicates the cycle number of reading Tx FIFO. + bitOffset: 6 + bitWidth: 7 + access: read-only + - name: TX_FIFO_RD_BIT_CNT + description: Indicates the current read bit number from Tx FIFO. + bitOffset: 13 + bitWidth: 19 + access: read-only + - register: + name: RX_CLK_CFG + description: Parallel IO RX clk configuration register + addressOffset: 68 + size: 32 + fields: + - name: RX_CLK_I_INV + description: Set this bit to invert the input Rx core clock. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: RX_CLK_O_INV + description: Set this bit to invert the output Rx core clock. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TX_CLK_CFG + description: Parallel IO TX clk configuration register + addressOffset: 72 + size: 32 + fields: + - name: TX_CLK_I_INV + description: Set this bit to invert the input Tx core clock. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TX_CLK_O_INV + description: Set this bit to invert the output Tx core clock. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CLK + description: Parallel IO clk configuration register + addressOffset: 288 + size: 32 + fields: + - name: EN + description: Force clock on for this register file + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: VERSION + description: Version register. + addressOffset: 1020 + size: 32 + resetValue: 35725920 + fields: + - name: DATE + description: Version of this register file + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: PAU + description: PAU Peripheral + groupName: PAU + baseAddress: 1611214848 + addressBlock: + - offset: 0 + size: 68 + usage: registers + interrupt: + - name: PAU + value: 112 + registers: + - register: + name: REGDMA_CONF + description: Peri backup control register + addressOffset: 0 + size: 32 + fields: + - name: FLOW_ERR + description: backup error type + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: START + description: backup start signal + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TO_MEM + description: backup direction(reg to mem / mem to reg) + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: LINK_SEL + description: Link select + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: START_MAC + description: mac sw backup start signal + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: TO_MEM_MAC + description: mac sw backup direction(reg to mem / mem to reg) + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SEL_MAC + description: mac hw/sw select + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: REGDMA_CLK_CONF + description: Clock control register + addressOffset: 4 + size: 32 + fields: + - name: CLK_EN + description: clock enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: REGDMA_ETM_CTRL + description: ETM start ctrl reg + addressOffset: 8 + size: 32 + fields: + - name: ETM_START_0 + description: etm_start_0 reg + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ETM_START_1 + description: etm_start_1 reg + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: ETM_START_2 + description: etm_start_2 reg + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: ETM_START_3 + description: etm_start_3 reg + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: REGDMA_LINK_0_ADDR + description: link_0_addr + addressOffset: 12 + size: 32 + fields: + - name: LINK_ADDR_0 + description: link_0_addr reg + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGDMA_LINK_1_ADDR + description: Link_1_addr + addressOffset: 16 + size: 32 + fields: + - name: LINK_ADDR_1 + description: Link_1_addr reg + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGDMA_LINK_2_ADDR + description: Link_2_addr + addressOffset: 20 + size: 32 + fields: + - name: LINK_ADDR_2 + description: Link_2_addr reg + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGDMA_LINK_3_ADDR + description: Link_3_addr + addressOffset: 24 + size: 32 + fields: + - name: LINK_ADDR_3 + description: Link_3_addr reg + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGDMA_LINK_MAC_ADDR + description: Link_mac_addr + addressOffset: 28 + size: 32 + fields: + - name: LINK_ADDR_MAC + description: Link_mac_addr reg + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REGDMA_CURRENT_LINK_ADDR + description: current link addr + addressOffset: 32 + size: 32 + fields: + - name: CURRENT_LINK_ADDR + description: current link addr reg + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: REGDMA_BACKUP_ADDR + description: Backup addr + addressOffset: 36 + size: 32 + fields: + - name: BACKUP_ADDR + description: backup addr reg + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: REGDMA_MEM_ADDR + description: mem addr + addressOffset: 40 + size: 32 + fields: + - name: MEM_ADDR + description: mem addr reg + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: REGDMA_BKP_CONF + description: backup config + addressOffset: 44 + size: 32 + resetValue: 2098207008 + fields: + - name: READ_INTERVAL + description: Link read_interval + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: LINK_TOUT_THRES + description: link wait timeout threshold + bitOffset: 7 + bitWidth: 10 + access: read-write + - name: BURST_LIMIT + description: burst limit + bitOffset: 17 + bitWidth: 5 + access: read-write + - name: BACKUP_TOUT_THRES + description: Backup timeout threshold + bitOffset: 22 + bitWidth: 10 + access: read-write + - register: + name: INT_ENA + description: Read only register for error and done + addressOffset: 48 + size: 32 + fields: + - name: DONE_INT_ENA + description: backup done flag + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ERROR_INT_ENA + description: error flag + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: Read only register for error and done + addressOffset: 52 + size: 32 + fields: + - name: DONE_INT_RAW + description: backup done flag + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ERROR_INT_RAW + description: error flag + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Read only register for error and done + addressOffset: 56 + size: 32 + fields: + - name: DONE_INT_CLR + description: backup done flag + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ERROR_INT_CLR + description: error flag + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: INT_ST + description: Read only register for error and done + addressOffset: 60 + size: 32 + fields: + - name: DONE_INT_ST + description: backup done flag + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ERROR_INT_ST + description: error flag + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: Date register. + addressOffset: 1020 + size: 32 + resetValue: 35663984 + fields: + - name: DATE + description: REGDMA date information/ REGDMA version information. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: PCNT + description: Pulse Count Controller + groupName: PCNT + baseAddress: 1343000576 + addressBlock: + - offset: 0 + size: 120 + usage: registers + interrupt: + - name: PCNT + value: 111 + registers: + - register: + dim: 4 + dimIncrement: 12 + name: U%s_CONF0 + description: Configuration register 0 for unit %s + addressOffset: 0 + size: 32 + resetValue: 15376 + fields: + - name: FILTER_THRES_U + description: "This sets the maximum threshold, in APB_CLK cycles, for the filter.\n\nAny pulses with width less than this will be ignored when the filter is enabled." + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: FILTER_EN_U + description: "This is the enable bit for unit %s's input filter." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: THR_ZERO_EN_U + description: "This is the enable bit for unit %s's zero comparator." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: THR_H_LIM_EN_U + description: "This is the enable bit for unit %s's thr_h_lim comparator. Configures it to enable the high limit interrupt." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: THR_L_LIM_EN_U + description: "This is the enable bit for unit %s's thr_l_lim comparator. Configures it to enable the low limit interrupt." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: THR_THRES0_EN_U + description: "This is the enable bit for unit %s's thres0 comparator." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: THR_THRES1_EN_U + description: "This is the enable bit for unit %s's thres1 comparator." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CH0_NEG_MODE_U + description: "This register sets the behavior when the signal input of channel 0 detects a negative edge.\n\n1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter" + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CH0_POS_MODE_U + description: "This register sets the behavior when the signal input of channel 0 detects a positive edge.\n\n1: Increase the counter.2: Decrease the counter.0, 3: No effect on counter" + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: CH0_HCTRL_MODE_U + description: "This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high.\n\n0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification" + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: CH0_LCTRL_MODE_U + description: "This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low.\n\n0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification" + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CH1_NEG_MODE_U + description: "This register sets the behavior when the signal input of channel 1 detects a negative edge.\n\n1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter" + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CH1_POS_MODE_U + description: "This register sets the behavior when the signal input of channel 1 detects a positive edge.\n\n1: Increment the counter.2: Decrement the counter.0, 3: No effect on counter" + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CH1_HCTRL_MODE_U + description: "This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high.\n\n0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification" + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: CH1_LCTRL_MODE_U + description: "This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low.\n\n0: No modification.1: Invert behavior (increase -> decrease, decrease -> increase).2, 3: Inhibit counter modification" + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + dim: 4 + dimIncrement: 12 + name: U%s_CONF1 + description: Configuration register 1 for unit %s + addressOffset: 4 + size: 32 + fields: + - name: CNT_THRES0_U + description: This register is used to configure the thres0 value for unit %s. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CNT_THRES1_U + description: This register is used to configure the thres1 value for unit %s. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + dim: 4 + dimIncrement: 12 + name: U%s_CONF2 + description: Configuration register 2 for unit %s + addressOffset: 8 + size: 32 + fields: + - name: CNT_H_LIM_U + description: "This register is used to configure the thr_h_lim value for unit %s. When pcnt reaches this value, the counter will be cleared to 0." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CNT_L_LIM_U + description: "This register is used to configure the thr_l_lim value for unit %s. When pcnt reaches this value, the counter will be cleared to 0." + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: U%s_CNT + description: Counter value for unit %s + addressOffset: 48 + size: 32 + fields: + - name: PULSE_CNT_U + description: This register stores the current pulse count value for unit %s. + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: INT_RAW + description: Interrupt raw status register + addressOffset: 64 + size: 32 + fields: + - name: CNT_THR_EVENT_U0_INT_RAW + description: The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U1_INT_RAW + description: The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U2_INT_RAW + description: The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U3_INT_RAW + description: The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Interrupt status register + addressOffset: 68 + size: 32 + fields: + - name: CNT_THR_EVENT_U0_INT_ST + description: The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U1_INT_ST + description: The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U2_INT_ST + description: The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U3_INT_ST + description: The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable register + addressOffset: 72 + size: 32 + fields: + - name: CNT_THR_EVENT_U0_INT_ENA + description: The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U1_INT_ENA + description: The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U2_INT_ENA + description: The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U3_INT_ENA + description: The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear register + addressOffset: 76 + size: 32 + fields: + - name: CNT_THR_EVENT_U0_INT_CLR + description: Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CNT_THR_EVENT_U1_INT_CLR + description: Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CNT_THR_EVENT_U2_INT_CLR + description: Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CNT_THR_EVENT_U3_INT_CLR + description: Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + dim: 4 + dimIncrement: 4 + name: U%s_STATUS + description: PNCT UNIT%s status register + addressOffset: 80 + size: 32 + fields: + - name: CNT_THR_ZERO_MODE_U + description: "The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive." + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: CNT_THR_THRES1_LAT_U + description: "The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others" + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CNT_THR_THRES0_LAT_U + description: "The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others" + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: CNT_THR_L_LIM_LAT_U + description: "The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others" + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: CNT_THR_H_LIM_LAT_U + description: "The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CNT_THR_ZERO_LAT_U + description: "The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others" + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: CTRL + description: Control register for all counters + addressOffset: 96 + size: 32 + resetValue: 1 + fields: + - name: PULSE_CNT_RST_U0 + description: "Set this bit to clear unit 0's counter." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U0 + description: "Set this bit to freeze unit 0's counter." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PULSE_CNT_RST_U1 + description: "Set this bit to clear unit 1's counter." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U1 + description: "Set this bit to freeze unit 1's counter." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PULSE_CNT_RST_U2 + description: "Set this bit to clear unit 2's counter." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U2 + description: "Set this bit to freeze unit 2's counter." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: PULSE_CNT_RST_U3 + description: "Set this bit to clear unit 3's counter." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U3 + description: "Set this bit to freeze unit 3's counter." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DALTA_CHANGE_EN_U0 + description: "Configures this bit to enable unit 0's step comparator." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DALTA_CHANGE_EN_U1 + description: "Configures this bit to enable unit 1's step comparator." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DALTA_CHANGE_EN_U2 + description: "Configures this bit to enable unit 2's step comparator." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DALTA_CHANGE_EN_U3 + description: "Configures this bit to enable unit 3's step comparator." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application" + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: U3_CHANGE_CONF + description: "Configuration register for unit $n's step value." + addressOffset: 100 + size: 32 + fields: + - name: CNT_STEP_U3 + description: Configures the step value for unit 3. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CNT_STEP_LIM_U3 + description: Configures the step limit value for unit 3. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: U2_CHANGE_CONF + description: "Configuration register for unit $n's step value." + addressOffset: 104 + size: 32 + fields: + - name: CNT_STEP_U2 + description: Configures the step value for unit 2. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CNT_STEP_LIM_U2 + description: Configures the step limit value for unit 2. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: U1_CHANGE_CONF + description: "Configuration register for unit $n's step value." + addressOffset: 108 + size: 32 + fields: + - name: CNT_STEP_U1 + description: Configures the step value for unit 1. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CNT_STEP_LIM_U1 + description: Configures the step limit value for unit 1. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: U0_CHANGE_CONF + description: "Configuration register for unit $n's step value." + addressOffset: 112 + size: 32 + fields: + - name: CNT_STEP_U0 + description: Configures the step value for unit 0. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CNT_STEP_LIM_U0 + description: Configures the step limit value for unit 0. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: DATE + description: PCNT version control register + addressOffset: 252 + size: 32 + resetValue: 571021568 + fields: + - name: DATE + description: This is the PCNT version control register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: PMU + description: PMU Peripheral + groupName: PMU + baseAddress: 1343311872 + addressBlock: + - offset: 0 + size: 540 + usage: registers + interrupt: + - name: PMU0 + value: 6 + - name: PMU1 + value: 7 + registers: + - register: + name: HP_ACTIVE_DIG_POWER + description: need_des + addressOffset: 0 + size: 32 + fields: + - name: HP_ACTIVE_DCDC_SWITCH_PD_EN + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_HP_MEM_DSLP + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_PD_HP_MEM_PD_EN + description: need_des + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_PD_CNNT_PD_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_PD_TOP_PD_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_ACTIVE_ICG_HP_FUNC + description: need_des + addressOffset: 4 + size: 32 + resetValue: 4294967295 + fields: + - name: HP_ACTIVE_DIG_ICG_FUNC_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_ACTIVE_ICG_HP_APB + description: need_des + addressOffset: 8 + size: 32 + resetValue: 4294967295 + fields: + - name: HP_ACTIVE_DIG_ICG_APB_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_ACTIVE_ICG_MODEM + description: need_des + addressOffset: 12 + size: 32 + fields: + - name: HP_ACTIVE_DIG_ICG_MODEM_CODE + description: need_des + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: HP_ACTIVE_HP_SYS_CNTL + description: need_des + addressOffset: 16 + size: 32 + fields: + - name: HP_ACTIVE_HP_POWER_DET_BYPASS + description: need_des + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_UART_WAKEUP_EN + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_LP_PAD_HOLD_ALL + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_HP_PAD_HOLD_ALL + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_DIG_PAD_SLP_SEL + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_DIG_PAUSE_WDT + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_DIG_CPU_STALL + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: HP_ACTIVE_HP_CK_POWER + description: need_des + addressOffset: 20 + size: 32 + fields: + - name: HP_ACTIVE_I2C_ISO_EN + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_I2C_RETENTION + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_XPD_PLL_I2C + description: need_des + bitOffset: 23 + bitWidth: 4 + access: read-write + - name: HP_ACTIVE_XPD_PLL + description: need_des + bitOffset: 27 + bitWidth: 4 + access: read-write + - register: + name: HP_ACTIVE_BIAS + description: need_des + addressOffset: 24 + size: 32 + resetValue: 5242880 + fields: + - name: HP_ACTIVE_DCM_VSET + description: need_des + bitOffset: 18 + bitWidth: 5 + access: read-write + - name: HP_ACTIVE_DCM_MODE + description: need_des + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: HP_ACTIVE_XPD_BIAS + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_DBG_ATTEN + description: need_des + bitOffset: 26 + bitWidth: 4 + access: read-write + - name: HP_ACTIVE_PD_CUR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SLEEP + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_ACTIVE_BACKUP + description: need_des + addressOffset: 28 + size: 32 + fields: + - name: HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE + description: need_des + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE + description: need_des + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: HP_ACTIVE_RETENTION_MODE + description: need_des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: HP_SLEEP2ACTIVE_RETENTION_EN + description: need_des + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: HP_MODEM2ACTIVE_RETENTION_EN + description: need_des + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: HP_SLEEP2ACTIVE_BACKUP_CLK_SEL + description: need_des + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: HP_MODEM2ACTIVE_BACKUP_CLK_SEL + description: need_des + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: HP_SLEEP2ACTIVE_BACKUP_MODE + description: need_des + bitOffset: 20 + bitWidth: 3 + access: read-write + - name: HP_MODEM2ACTIVE_BACKUP_MODE + description: need_des + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: HP_SLEEP2ACTIVE_BACKUP_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_MODEM2ACTIVE_BACKUP_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: HP_ACTIVE_BACKUP_CLK + description: need_des + addressOffset: 32 + size: 32 + fields: + - name: HP_ACTIVE_BACKUP_ICG_FUNC_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_ACTIVE_SYSCLK + description: need_des + addressOffset: 36 + size: 32 + fields: + - name: HP_ACTIVE_DIG_SYS_CLK_NO_DIV + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_ICG_SYS_CLOCK_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_SYS_CLK_SLP_SEL + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_ICG_SLP_SEL + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_DIG_SYS_CLK_SEL + description: need_des + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: HP_ACTIVE_HP_REGULATOR0 + description: need_des + addressOffset: 40 + size: 32 + resetValue: 3328668032 + fields: + - name: LP_DBIAS_VOL + description: need_des + bitOffset: 4 + bitWidth: 5 + access: read-only + - name: HP_DBIAS_VOL + description: need_des + bitOffset: 9 + bitWidth: 5 + access: read-only + - name: DIG_REGULATOR0_DBIAS_SEL + description: need_des + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DIG_DBIAS_INIT + description: need_des + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD + description: need_des + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD + description: need_des + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_HP_REGULATOR_XPD + description: need_des + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS + description: need_des + bitOffset: 19 + bitWidth: 4 + access: read-write + - name: HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS + description: need_des + bitOffset: 23 + bitWidth: 4 + access: read-write + - name: HP_ACTIVE_HP_REGULATOR_DBIAS + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: HP_ACTIVE_HP_REGULATOR1 + description: need_des + addressOffset: 44 + size: 32 + fields: + - name: HP_ACTIVE_HP_REGULATOR_DRV_B + description: need_des + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: HP_ACTIVE_XTAL + description: need_des + addressOffset: 48 + size: 32 + resetValue: 2147483648 + fields: + - name: HP_ACTIVE_XPD_XTAL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_MODEM_DIG_POWER + description: need_des + addressOffset: 52 + size: 32 + fields: + - name: HP_MODEM_DCDC_SWITCH_PD_EN + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: HP_MODEM_HP_MEM_DSLP + description: need_des + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: HP_MODEM_PD_HP_MEM_PD_EN + description: need_des + bitOffset: 23 + bitWidth: 4 + access: write-only + - name: HP_MODEM_PD_HP_WIFI_PD_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: HP_MODEM_PD_HP_CPU_PD_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: HP_MODEM_PD_CNNT_PD_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: HP_MODEM_PD_TOP_PD_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: HP_MODEM_ICG_HP_FUNC + description: need_des + addressOffset: 56 + size: 32 + resetValue: 4294967295 + fields: + - name: HP_MODEM_DIG_ICG_FUNC_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: HP_MODEM_ICG_HP_APB + description: need_des + addressOffset: 60 + size: 32 + resetValue: 4294967295 + fields: + - name: HP_MODEM_DIG_ICG_APB_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: HP_MODEM_ICG_MODEM + description: need_des + addressOffset: 64 + size: 32 + fields: + - name: HP_MODEM_DIG_ICG_MODEM_CODE + description: need_des + bitOffset: 30 + bitWidth: 2 + access: write-only + - register: + name: HP_MODEM_HP_SYS_CNTL + description: need_des + addressOffset: 68 + size: 32 + fields: + - name: HP_MODEM_HP_POWER_DET_BYPASS + description: need_des + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: HP_MODEM_UART_WAKEUP_EN + description: need_des + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: HP_MODEM_LP_PAD_HOLD_ALL + description: need_des + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: HP_MODEM_HP_PAD_HOLD_ALL + description: need_des + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: HP_MODEM_DIG_PAD_SLP_SEL + description: need_des + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: HP_MODEM_DIG_PAUSE_WDT + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: HP_MODEM_DIG_CPU_STALL + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - register: + name: HP_MODEM_HP_CK_POWER + description: need_des + addressOffset: 72 + size: 32 + fields: + - name: HP_MODEM_I2C_ISO_EN + description: need_des + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: HP_MODEM_I2C_RETENTION + description: need_des + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: HP_MODEM_XPD_PLL_I2C + description: need_des + bitOffset: 23 + bitWidth: 4 + access: write-only + - name: HP_MODEM_XPD_PLL + description: need_des + bitOffset: 27 + bitWidth: 4 + access: write-only + - register: + name: HP_MODEM_BIAS + description: need_des + addressOffset: 76 + size: 32 + resetValue: 5242880 + fields: + - name: HP_MODEM_DCM_VSET + description: need_des + bitOffset: 18 + bitWidth: 5 + access: write-only + - name: HP_MODEM_DCM_MODE + description: need_des + bitOffset: 23 + bitWidth: 2 + access: write-only + - name: HP_MODEM_XPD_BIAS + description: need_des + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: HP_MODEM_DBG_ATTEN + description: need_des + bitOffset: 26 + bitWidth: 4 + access: write-only + - name: HP_MODEM_PD_CUR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: SLEEP + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: HP_MODEM_BACKUP + description: need_des + addressOffset: 80 + size: 32 + fields: + - name: HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE + description: need_des + bitOffset: 4 + bitWidth: 2 + access: write-only + - name: HP_MODEM_RETENTION_MODE + description: need_des + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: HP_SLEEP2MODEM_RETENTION_EN + description: need_des + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: HP_SLEEP2MODEM_BACKUP_CLK_SEL + description: need_des + bitOffset: 14 + bitWidth: 2 + access: write-only + - name: HP_SLEEP2MODEM_BACKUP_MODE + description: need_des + bitOffset: 20 + bitWidth: 3 + access: write-only + - name: HP_SLEEP2MODEM_BACKUP_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - register: + name: HP_MODEM_BACKUP_CLK + description: need_des + addressOffset: 84 + size: 32 + fields: + - name: HP_MODEM_BACKUP_ICG_FUNC_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: HP_MODEM_SYSCLK + description: need_des + addressOffset: 88 + size: 32 + fields: + - name: HP_MODEM_DIG_SYS_CLK_NO_DIV + description: need_des + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: HP_MODEM_ICG_SYS_CLOCK_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: HP_MODEM_SYS_CLK_SLP_SEL + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: HP_MODEM_ICG_SLP_SEL + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: HP_MODEM_DIG_SYS_CLK_SEL + description: need_des + bitOffset: 30 + bitWidth: 2 + access: write-only + - register: + name: HP_MODEM_HP_REGULATOR0 + description: need_des + addressOffset: 92 + size: 32 + resetValue: 3328638976 + fields: + - name: HP_MODEM_HP_REGULATOR_SLP_MEM_XPD + description: need_des + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD + description: need_des + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: HP_MODEM_HP_REGULATOR_XPD + description: need_des + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS + description: need_des + bitOffset: 19 + bitWidth: 4 + access: write-only + - name: HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS + description: need_des + bitOffset: 23 + bitWidth: 4 + access: write-only + - name: HP_MODEM_HP_REGULATOR_DBIAS + description: need_des + bitOffset: 27 + bitWidth: 5 + access: write-only + - register: + name: HP_MODEM_HP_REGULATOR1 + description: need_des + addressOffset: 96 + size: 32 + fields: + - name: HP_MODEM_HP_REGULATOR_DRV_B + description: need_des + bitOffset: 8 + bitWidth: 24 + access: write-only + - register: + name: HP_MODEM_XTAL + description: need_des + addressOffset: 100 + size: 32 + resetValue: 2147483648 + fields: + - name: HP_MODEM_XPD_XTAL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: HP_SLEEP_DIG_POWER + description: need_des + addressOffset: 104 + size: 32 + fields: + - name: HP_SLEEP_DCDC_SWITCH_PD_EN + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_HP_MEM_DSLP + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_PD_HP_MEM_PD_EN + description: need_des + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_PD_CNNT_PD_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_PD_TOP_PD_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_SLEEP_ICG_HP_FUNC + description: need_des + addressOffset: 108 + size: 32 + resetValue: 4294967295 + fields: + - name: HP_SLEEP_DIG_ICG_FUNC_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_SLEEP_ICG_HP_APB + description: need_des + addressOffset: 112 + size: 32 + resetValue: 4294967295 + fields: + - name: HP_SLEEP_DIG_ICG_APB_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_SLEEP_ICG_MODEM + description: need_des + addressOffset: 116 + size: 32 + fields: + - name: HP_SLEEP_DIG_ICG_MODEM_CODE + description: need_des + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: HP_SLEEP_HP_SYS_CNTL + description: need_des + addressOffset: 120 + size: 32 + fields: + - name: HP_SLEEP_HP_POWER_DET_BYPASS + description: need_des + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_UART_WAKEUP_EN + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_LP_PAD_HOLD_ALL + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_HP_PAD_HOLD_ALL + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_DIG_PAD_SLP_SEL + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_DIG_PAUSE_WDT + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_DIG_CPU_STALL + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: HP_SLEEP_HP_CK_POWER + description: need_des + addressOffset: 124 + size: 32 + fields: + - name: HP_SLEEP_I2C_ISO_EN + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_I2C_RETENTION + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_XPD_PLL_I2C + description: need_des + bitOffset: 23 + bitWidth: 4 + access: read-write + - name: HP_SLEEP_XPD_PLL + description: need_des + bitOffset: 27 + bitWidth: 4 + access: read-write + - register: + name: HP_SLEEP_BIAS + description: need_des + addressOffset: 128 + size: 32 + resetValue: 5242880 + fields: + - name: HP_SLEEP_DCM_VSET + description: need_des + bitOffset: 18 + bitWidth: 5 + access: read-write + - name: HP_SLEEP_DCM_MODE + description: need_des + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: HP_SLEEP_XPD_BIAS + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_DBG_ATTEN + description: need_des + bitOffset: 26 + bitWidth: 4 + access: read-write + - name: HP_SLEEP_PD_CUR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SLEEP + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_SLEEP_BACKUP + description: need_des + addressOffset: 132 + size: 32 + fields: + - name: HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE + description: need_des + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE + description: need_des + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: HP_SLEEP_RETENTION_MODE + description: need_des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: HP_MODEM2SLEEP_RETENTION_EN + description: need_des + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE2SLEEP_RETENTION_EN + description: need_des + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: HP_MODEM2SLEEP_BACKUP_CLK_SEL + description: need_des + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: HP_ACTIVE2SLEEP_BACKUP_CLK_SEL + description: need_des + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: HP_MODEM2SLEEP_BACKUP_MODE + description: need_des + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: HP_ACTIVE2SLEEP_BACKUP_MODE + description: need_des + bitOffset: 26 + bitWidth: 3 + access: read-write + - name: HP_MODEM2SLEEP_BACKUP_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HP_ACTIVE2SLEEP_BACKUP_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_SLEEP_BACKUP_CLK + description: need_des + addressOffset: 136 + size: 32 + fields: + - name: HP_SLEEP_BACKUP_ICG_FUNC_EN + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HP_SLEEP_SYSCLK + description: need_des + addressOffset: 140 + size: 32 + fields: + - name: HP_SLEEP_DIG_SYS_CLK_NO_DIV + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_ICG_SYS_CLOCK_EN + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_SYS_CLK_SLP_SEL + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_ICG_SLP_SEL + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_DIG_SYS_CLK_SEL + description: need_des + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: HP_SLEEP_HP_REGULATOR0 + description: need_des + addressOffset: 144 + size: 32 + resetValue: 3328638976 + fields: + - name: HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD + description: need_des + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD + description: need_des + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_HP_REGULATOR_XPD + description: need_des + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS + description: need_des + bitOffset: 19 + bitWidth: 4 + access: read-write + - name: HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS + description: need_des + bitOffset: 23 + bitWidth: 4 + access: read-write + - name: HP_SLEEP_HP_REGULATOR_DBIAS + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: HP_SLEEP_HP_REGULATOR1 + description: need_des + addressOffset: 148 + size: 32 + fields: + - name: HP_SLEEP_HP_REGULATOR_DRV_B + description: need_des + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: HP_SLEEP_XTAL + description: need_des + addressOffset: 152 + size: 32 + resetValue: 2147483648 + fields: + - name: HP_SLEEP_XPD_XTAL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_SLEEP_LP_REGULATOR0 + description: need_des + addressOffset: 156 + size: 32 + resetValue: 3328180224 + fields: + - name: HP_SLEEP_LP_REGULATOR_SLP_XPD + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_LP_REGULATOR_XPD + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_LP_REGULATOR_SLP_DBIAS + description: need_des + bitOffset: 23 + bitWidth: 4 + access: read-write + - name: HP_SLEEP_LP_REGULATOR_DBIAS + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: HP_SLEEP_LP_REGULATOR1 + description: need_des + addressOffset: 160 + size: 32 + fields: + - name: HP_SLEEP_LP_REGULATOR_DRV_B + description: need_des + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: HP_SLEEP_LP_DCDC_RESERVE + description: need_des + addressOffset: 164 + size: 32 + fields: + - name: PMU_HP_SLEEP_LP_DCDC_RESERVE + description: need_des + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: HP_SLEEP_LP_DIG_POWER + description: need_des + addressOffset: 168 + size: 32 + fields: + - name: HP_SLEEP_LP_PAD_SLP_SEL + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_BOD_SOURCE_SEL + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_VDDBAT_MODE + description: need_des + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: HP_SLEEP_LP_MEM_DSLP + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_PD_LP_PERI_PD_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_SLEEP_LP_CK_POWER + description: need_des + addressOffset: 172 + size: 32 + resetValue: 1073741824 + fields: + - name: HP_SLEEP_XPD_LPPLL + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_XPD_XTAL32K + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_XPD_RC32K + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_XPD_FOSC_CLK + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HP_SLEEP_PD_OSC_CLK + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_SLEEP_LP_BIAS_RESERVE + description: need_des + addressOffset: 176 + size: 32 + fields: + - name: PMU_LP_SLEEP_LP_BIAS_RESERVE + description: need_des + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: LP_SLEEP_LP_REGULATOR0 + description: need_des + addressOffset: 180 + size: 32 + resetValue: 3328180224 + fields: + - name: LP_SLEEP_LP_REGULATOR_SLP_XPD + description: need_des + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_LP_REGULATOR_XPD + description: need_des + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_LP_REGULATOR_SLP_DBIAS + description: need_des + bitOffset: 23 + bitWidth: 4 + access: read-write + - name: LP_SLEEP_LP_REGULATOR_DBIAS + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: LP_SLEEP_LP_REGULATOR1 + description: need_des + addressOffset: 184 + size: 32 + fields: + - name: LP_SLEEP_LP_REGULATOR_DRV_B + description: need_des + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: LP_SLEEP_XTAL + description: need_des + addressOffset: 188 + size: 32 + resetValue: 2147483648 + fields: + - name: LP_SLEEP_XPD_XTAL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_SLEEP_LP_DIG_POWER + description: need_des + addressOffset: 192 + size: 32 + fields: + - name: LP_SLEEP_LP_PAD_SLP_SEL + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_BOD_SOURCE_SEL + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_VDDBAT_MODE + description: need_des + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: LP_SLEEP_LP_MEM_DSLP + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_PD_LP_PERI_PD_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_SLEEP_LP_CK_POWER + description: need_des + addressOffset: 196 + size: 32 + resetValue: 1073741824 + fields: + - name: LP_SLEEP_XPD_LPPLL + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_XPD_XTAL32K + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_XPD_RC32K + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_XPD_FOSC_CLK + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_PD_OSC_CLK + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_SLEEP_BIAS + description: need_des + addressOffset: 200 + size: 32 + fields: + - name: LP_SLEEP_XPD_BIAS + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LP_SLEEP_DBG_ATTEN + description: need_des + bitOffset: 26 + bitWidth: 4 + access: read-write + - name: LP_SLEEP_PD_CUR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SLEEP + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: IMM_HP_CK_POWER + description: need_des + addressOffset: 204 + size: 32 + fields: + - name: TIE_LOW_CALI_XTAL_ICG + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIE_LOW_GLOBAL_PLL_ICG + description: need_des + bitOffset: 1 + bitWidth: 4 + access: write-only + - name: TIE_LOW_GLOBAL_XTAL_ICG + description: need_des + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TIE_LOW_I2C_RETENTION + description: need_des + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TIE_LOW_XPD_PLL_I2C + description: need_des + bitOffset: 7 + bitWidth: 4 + access: write-only + - name: TIE_LOW_XPD_PLL + description: need_des + bitOffset: 11 + bitWidth: 4 + access: write-only + - name: TIE_LOW_XPD_XTAL + description: need_des + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_CALI_XTAL_ICG + description: need_des + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: TIE_HIGH_GLOBAL_PLL_ICG + description: need_des + bitOffset: 17 + bitWidth: 4 + access: write-only + - name: TIE_HIGH_GLOBAL_XTAL_ICG + description: need_des + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_I2C_RETENTION + description: need_des + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_XPD_PLL_I2C + description: need_des + bitOffset: 23 + bitWidth: 4 + access: write-only + - name: TIE_HIGH_XPD_PLL + description: need_des + bitOffset: 27 + bitWidth: 4 + access: write-only + - name: TIE_HIGH_XPD_XTAL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: IMM_SLEEP_SYSCLK + description: need_des + addressOffset: 208 + size: 32 + fields: + - name: UPDATE_DIG_ICG_SWITCH + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: TIE_LOW_ICG_SLP_SEL + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_ICG_SLP_SEL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: UPDATE_DIG_SYS_CLK_SEL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: IMM_HP_FUNC_ICG + description: need_des + addressOffset: 212 + size: 32 + fields: + - name: UPDATE_DIG_ICG_FUNC_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: IMM_HP_APB_ICG + description: need_des + addressOffset: 216 + size: 32 + fields: + - name: UPDATE_DIG_ICG_APB_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: IMM_MODEM_ICG + description: need_des + addressOffset: 220 + size: 32 + fields: + - name: UPDATE_DIG_ICG_MODEM_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: IMM_LP_ICG + description: need_des + addressOffset: 224 + size: 32 + fields: + - name: TIE_LOW_LP_ROOTCLK_SEL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_LP_ROOTCLK_SEL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: IMM_PAD_HOLD_ALL + description: need_des + addressOffset: 228 + size: 32 + fields: + - name: PAD_SLP_SEL + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: LP_PAD_HOLD_ALL + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: HP_PAD_HOLD_ALL + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TIE_HIGH_PAD_SLP_SEL + description: need_des + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: TIE_LOW_PAD_SLP_SEL + description: need_des + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_LP_PAD_HOLD_ALL + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: TIE_LOW_LP_PAD_HOLD_ALL + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: TIE_HIGH_HP_PAD_HOLD_ALL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: TIE_LOW_HP_PAD_HOLD_ALL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: IMM_I2C_ISO + description: need_des + addressOffset: 232 + size: 32 + fields: + - name: TIE_HIGH_I2C_ISO_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: TIE_LOW_I2C_ISO_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: POWER_WAIT_TIMER0 + description: need_des + addressOffset: 236 + size: 32 + resetValue: 2143281120 + fields: + - name: DG_HP_POWERDOWN_TIMER + description: need_des + bitOffset: 5 + bitWidth: 9 + access: read-write + - name: DG_HP_POWERUP_TIMER + description: need_des + bitOffset: 14 + bitWidth: 9 + access: read-write + - name: DG_HP_WAIT_TIMER + description: need_des + bitOffset: 23 + bitWidth: 9 + access: read-write + - register: + name: POWER_WAIT_TIMER1 + description: need_des + addressOffset: 240 + size: 32 + resetValue: 2143281120 + fields: + - name: DG_LP_POWERDOWN_TIMER + description: need_des + bitOffset: 5 + bitWidth: 9 + access: read-write + - name: DG_LP_POWERUP_TIMER + description: need_des + bitOffset: 14 + bitWidth: 9 + access: read-write + - name: DG_LP_WAIT_TIMER + description: need_des + bitOffset: 23 + bitWidth: 9 + access: read-write + - register: + name: POWER_PD_TOP_CNTL + description: need_des + addressOffset: 244 + size: 32 + resetValue: 28 + fields: + - name: FORCE_TOP_RESET + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FORCE_TOP_ISO + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FORCE_TOP_PU + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FORCE_TOP_NO_RESET + description: need_des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FORCE_TOP_NO_ISO + description: need_des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FORCE_TOP_PD + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: POWER_PD_CNNT_CNTL + description: need_des + addressOffset: 248 + size: 32 + resetValue: 28 + fields: + - name: FORCE_CNNT_RESET + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FORCE_CNNT_ISO + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FORCE_CNNT_PU + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FORCE_CNNT_NO_RESET + description: need_des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FORCE_CNNT_NO_ISO + description: need_des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FORCE_CNNT_PD + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: POWER_PD_HPMEM_CNTL + description: need_des + addressOffset: 252 + size: 32 + resetValue: 28 + fields: + - name: FORCE_HP_MEM_RESET + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FORCE_HP_MEM_ISO + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FORCE_HP_MEM_PU + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FORCE_HP_MEM_NO_RESET + description: need_des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FORCE_HP_MEM_NO_ISO + description: need_des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FORCE_HP_MEM_PD + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: POWER_PD_TOP_MASK + description: need_des + addressOffset: 256 + size: 32 + fields: + - name: XPD_TOP_MASK + description: need_des + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: PD_TOP_MASK + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: POWER_PD_CNNT_MASK + description: need_des + addressOffset: 260 + size: 32 + fields: + - name: XPD_CNNT_MASK + description: need_des + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: PD_CNNT_MASK + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: POWER_PD_HPMEM_MASK + description: need_des + addressOffset: 264 + size: 32 + fields: + - name: XPD_HP_MEM_MASK + description: need_des + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: PD_HP_MEM_MASK + description: need_des + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: POWER_DCDC_SWITCH + description: need_des + addressOffset: 268 + size: 32 + resetValue: 1 + fields: + - name: FORCE_DCDC_SWITCH_PU + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FORCE_DCDC_SWITCH_PD + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: POWER_PD_LPPERI_CNTL + description: need_des + addressOffset: 272 + size: 32 + resetValue: 28 + fields: + - name: FORCE_LP_PERI_RESET + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FORCE_LP_PERI_ISO + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FORCE_LP_PERI_PU + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FORCE_LP_PERI_NO_RESET + description: need_des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FORCE_LP_PERI_NO_ISO + description: need_des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FORCE_LP_PERI_PD + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: POWER_PD_LPPERI_MASK + description: need_des + addressOffset: 276 + size: 32 + fields: + - name: XPD_LP_PERI_MASK + description: need_des + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: PD_LP_PERI_MASK + description: need_des + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: POWER_HP_PAD + description: need_des + addressOffset: 280 + size: 32 + fields: + - name: FORCE_HP_PAD_NO_ISO_ALL + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FORCE_HP_PAD_ISO_ALL + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: POWER_CK_WAIT_CNTL + description: need_des + addressOffset: 284 + size: 32 + resetValue: 16777472 + fields: + - name: PMU_WAIT_XTL_STABLE + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: PMU_WAIT_PLL_STABLE + description: need_des + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SLP_WAKEUP_CNTL0 + description: need_des + addressOffset: 288 + size: 32 + fields: + - name: SLEEP_REQ + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SLP_WAKEUP_CNTL1 + description: need_des + addressOffset: 292 + size: 32 + fields: + - name: SLEEP_REJECT_ENA + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: SLP_REJECT_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SLP_WAKEUP_CNTL2 + description: need_des + addressOffset: 296 + size: 32 + fields: + - name: WAKEUP_ENA + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - register: + name: SLP_WAKEUP_CNTL3 + description: need_des + addressOffset: 300 + size: 32 + fields: + - name: LP_MIN_SLP_VAL + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: HP_MIN_SLP_VAL + description: need_des + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SLEEP_PRT_SEL + description: need_des + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: SLP_WAKEUP_CNTL4 + description: need_des + addressOffset: 304 + size: 32 + fields: + - name: SLP_REJECT_CAUSE_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SLP_WAKEUP_CNTL5 + description: need_des + addressOffset: 308 + size: 32 + resetValue: 16777344 + fields: + - name: MODEM_WAIT_TARGET + description: need_des + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: LP_ANA_WAIT_TARGET + description: need_des + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: SLP_WAKEUP_CNTL6 + description: need_des + addressOffset: 312 + size: 32 + resetValue: 128 + fields: + - name: SOC_WAKEUP_WAIT + description: need_des + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: SOC_WAKEUP_WAIT_CFG + description: need_des + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: SLP_WAKEUP_CNTL7 + description: need_des + addressOffset: 316 + size: 32 + resetValue: 65536 + fields: + - name: ANA_WAIT_TARGET + description: need_des + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SLP_WAKEUP_CNTL8 + description: need_des + addressOffset: 320 + size: 32 + fields: + - name: LP_LITE_WAKEUP_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SLP_WAKEUP_STATUS0 + description: need_des + addressOffset: 324 + size: 32 + fields: + - name: WAKEUP_CAUSE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-only + - register: + name: SLP_WAKEUP_STATUS1 + description: need_des + addressOffset: 328 + size: 32 + fields: + - name: REJECT_CAUSE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-only + - register: + name: SLP_WAKEUP_STATUS2 + description: need_des + addressOffset: 332 + size: 32 + fields: + - name: LP_LITE_WAKEUP_CAUSE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: HP_CK_POWERON + description: need_des + addressOffset: 336 + size: 32 + resetValue: 50 + fields: + - name: I2C_POR_WAIT_TARGET + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: HP_CK_CNTL + description: need_des + addressOffset: 340 + size: 32 + resetValue: 2570 + fields: + - name: MODIFY_ICG_CNTL_WAIT + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SWITCH_ICG_CNTL_WAIT + description: need_des + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: POR_STATUS + description: need_des + addressOffset: 344 + size: 32 + resetValue: 2147483648 + fields: + - name: POR_DONE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: RF_PWC + description: need_des + addressOffset: 348 + size: 32 + resetValue: 134217728 + fields: + - name: MSPI_PHY_XPD + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SDIO_PLL_XPD + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PERIF_I2C_RSTB + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: XPD_PERIF_I2C + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: XPD_TXRF_I2C + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: XPD_RFRX_PBUS + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: XPD_CKGEN_I2C + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: BACKUP_CFG + description: need_des + addressOffset: 352 + size: 32 + resetValue: 2147483648 + fields: + - name: BACKUP_SYS_CLK_NO_DIV + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: need_des + addressOffset: 356 + size: 32 + fields: + - name: _0P1A_CNT_TARGET0_REACH_0_HP_INT_RAW + description: reg_0p1a_0_counter after xpd reach target0 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: _0P1A_CNT_TARGET1_REACH_0_HP_INT_RAW + description: reg_0p1a_1_counter after xpd reach target1 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: _0P1A_CNT_TARGET0_REACH_1_HP_INT_RAW + description: reg_0p1a_0 counter after xpd reach target0 + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: _0P1A_CNT_TARGET1_REACH_1_HP_INT_RAW + description: reg_0p1a_1_counter after xpd reach target1 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: _0P2A_CNT_TARGET0_REACH_0_HP_INT_RAW + description: reg_0p2a_0 counter after xpd reach target0 + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: _0P2A_CNT_TARGET1_REACH_0_HP_INT_RAW + description: reg_0p2a_1_counter after xpd reach target1 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: _0P2A_CNT_TARGET0_REACH_1_HP_INT_RAW + description: reg_0p2a_0 counter after xpd reach target0 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: _0P2A_CNT_TARGET1_REACH_1_HP_INT_RAW + description: reg_0p2a_1_counter after xpd reach target1 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: _0P3A_CNT_TARGET0_REACH_0_HP_INT_RAW + description: reg_0p3a_0 counter after xpd reach target0 + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: _0P3A_CNT_TARGET1_REACH_0_HP_INT_RAW + description: reg_0p3a_1_counter after xpd reach target1 + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: _0P3A_CNT_TARGET0_REACH_1_HP_INT_RAW + description: reg_0p3a_0_counter after xpd reach target0 + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: _0P3A_CNT_TARGET1_REACH_1_HP_INT_RAW + description: reg_0p3a_1_counter after xpd reach target1 + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LP_CPU_EXC_INT_RAW + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SDIO_IDLE_INT_RAW + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SW_INT_RAW + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SOC_SLEEP_REJECT_INT_RAW + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SOC_WAKEUP_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_INT_ST + description: need_des + addressOffset: 360 + size: 32 + fields: + - name: _0P1A_CNT_TARGET0_REACH_0_HP_INT_ST + description: reg_0p1a_0_counter after xpd reach target0 + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: _0P1A_CNT_TARGET1_REACH_0_HP_INT_ST + description: reg_0p1a_1_counter after xpd reach target1 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: _0P1A_CNT_TARGET0_REACH_1_HP_INT_ST + description: reg_0p1a_0 counter after xpd reach target0 + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: _0P1A_CNT_TARGET1_REACH_1_HP_INT_ST + description: reg_0p1a_1_counter after xpd reach target1 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: _0P2A_CNT_TARGET0_REACH_0_HP_INT_ST + description: reg_0p2a_0 counter after xpd reach target0 + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: _0P2A_CNT_TARGET1_REACH_0_HP_INT_ST + description: reg_0p2a_1_counter after xpd reach target1 + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: _0P2A_CNT_TARGET0_REACH_1_HP_INT_ST + description: reg_0p2a_0 counter after xpd reach target0 + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: _0P2A_CNT_TARGET1_REACH_1_HP_INT_ST + description: reg_0p2a_1_counter after xpd reach target1 + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: _0P3A_CNT_TARGET0_REACH_0_HP_INT_ST + description: reg_0p3a_0 counter after xpd reach target0 + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: _0P3A_CNT_TARGET1_REACH_0_HP_INT_ST + description: reg_0p3a_1_counter after xpd reach target1 + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: _0P3A_CNT_TARGET0_REACH_1_HP_INT_ST + description: reg_0p3a_0_counter after xpd reach target0 + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: _0P3A_CNT_TARGET1_REACH_1_HP_INT_ST + description: reg_0p3a_1_counter after xpd reach target1 + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: LP_CPU_EXC_INT_ST + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: SDIO_IDLE_INT_ST + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SW_INT_ST + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: SOC_SLEEP_REJECT_INT_ST + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: SOC_WAKEUP_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: HP_INT_ENA + description: need_des + addressOffset: 364 + size: 32 + fields: + - name: _0P1A_CNT_TARGET0_REACH_0_HP_INT_ENA + description: reg_0p1a_0_counter after xpd reach target0 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: _0P1A_CNT_TARGET1_REACH_0_HP_INT_ENA + description: reg_0p1a_1_counter after xpd reach target1 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: _0P1A_CNT_TARGET0_REACH_1_HP_INT_ENA + description: reg_0p1a_0 counter after xpd reach target0 + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: _0P1A_CNT_TARGET1_REACH_1_HP_INT_ENA + description: reg_0p1a_1_counter after xpd reach target1 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: _0P2A_CNT_TARGET0_REACH_0_HP_INT_ENA + description: reg_0p2a_0 counter after xpd reach target0 + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: _0P2A_CNT_TARGET1_REACH_0_HP_INT_ENA + description: reg_0p2a_1_counter after xpd reach target1 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: _0P2A_CNT_TARGET0_REACH_1_HP_INT_ENA + description: reg_0p2a_0 counter after xpd reach target0 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: _0P2A_CNT_TARGET1_REACH_1_HP_INT_ENA + description: reg_0p2a_1_counter after xpd reach target1 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: _0P3A_CNT_TARGET0_REACH_0_HP_INT_ENA + description: reg_0p3a_0 counter after xpd reach target0 + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: _0P3A_CNT_TARGET1_REACH_0_HP_INT_ENA + description: reg_0p3a_1_counter after xpd reach target1 + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: _0P3A_CNT_TARGET0_REACH_1_HP_INT_ENA + description: reg_0p3a_0_counter after xpd reach target0 + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: _0P3A_CNT_TARGET1_REACH_1_HP_INT_ENA + description: reg_0p3a_1_counter after xpd reach target1 + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LP_CPU_EXC_INT_ENA + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SDIO_IDLE_INT_ENA + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SW_INT_ENA + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SOC_SLEEP_REJECT_INT_ENA + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SOC_WAKEUP_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HP_INT_CLR + description: need_des + addressOffset: 368 + size: 32 + fields: + - name: _0P1A_CNT_TARGET0_REACH_0_HP_INT_CLR + description: reg_0p1a_0_counter after xpd reach target0 + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: _0P1A_CNT_TARGET1_REACH_0_HP_INT_CLR + description: reg_0p1a_1_counter after xpd reach target1 + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: _0P1A_CNT_TARGET0_REACH_1_HP_INT_CLR + description: reg_0p1a_0 counter after xpd reach target0 + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: _0P1A_CNT_TARGET1_REACH_1_HP_INT_CLR + description: reg_0p1a_1_counter after xpd reach target1 + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: _0P2A_CNT_TARGET0_REACH_0_HP_INT_CLR + description: reg_0p2a_0 counter after xpd reach target0 + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: _0P2A_CNT_TARGET1_REACH_0_HP_INT_CLR + description: reg_0p2a_1_counter after xpd reach target1 + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: _0P2A_CNT_TARGET0_REACH_1_HP_INT_CLR + description: reg_0p2a_0 counter after xpd reach target0 + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: _0P2A_CNT_TARGET1_REACH_1_HP_INT_CLR + description: reg_0p2a_1_counter after xpd reach target1 + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: _0P3A_CNT_TARGET0_REACH_0_HP_INT_CLR + description: reg_0p3a_0 counter after xpd reach target0 + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: _0P3A_CNT_TARGET1_REACH_0_HP_INT_CLR + description: reg_0p3a_1_counter after xpd reach target1 + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: _0P3A_CNT_TARGET0_REACH_1_HP_INT_CLR + description: reg_0p3a_0_counter after xpd reach target0 + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: _0P3A_CNT_TARGET1_REACH_1_HP_INT_CLR + description: reg_0p3a_1_counter after xpd reach target1 + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: LP_CPU_EXC_INT_CLR + description: need_des + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: SDIO_IDLE_INT_CLR + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: SW_INT_CLR + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: SOC_SLEEP_REJECT_INT_CLR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: SOC_WAKEUP_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: LP_INT_RAW + description: need_des + addressOffset: 372 + size: 32 + fields: + - name: LP_CPU_SLEEP_REJECT_INT_RAW + description: need_des + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: _0P1A_CNT_TARGET0_REACH_0_LP_INT_RAW + description: reg_0p1a_0_counter after xpd reach target0 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: _0P1A_CNT_TARGET1_REACH_0_LP_INT_RAW + description: reg_0p1a_1_counter after xpd reach target1 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: _0P1A_CNT_TARGET0_REACH_1_LP_INT_RAW + description: reg_0p1a_0 counter after xpd reach target0 + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: _0P1A_CNT_TARGET1_REACH_1_LP_INT_RAW + description: reg_0p1a_1_counter after xpd reach target1 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: _0P2A_CNT_TARGET0_REACH_0_LP_INT_RAW + description: reg_0p2a_0 counter after xpd reach target0 + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: _0P2A_CNT_TARGET1_REACH_0_LP_INT_RAW + description: reg_0p2a_1_counter after xpd reach target1 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: _0P2A_CNT_TARGET0_REACH_1_LP_INT_RAW + description: reg_0p2a_0 counter after xpd reach target0 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: _0P2A_CNT_TARGET1_REACH_1_LP_INT_RAW + description: reg_0p2a_1_counter after xpd reach target1 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: _0P3A_CNT_TARGET0_REACH_0_LP_INT_RAW + description: reg_0p3a_0 counter after xpd reach target0 + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: _0P3A_CNT_TARGET1_REACH_0_LP_INT_RAW + description: reg_0p3a_1_counter after xpd reach target1 + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: _0P3A_CNT_TARGET0_REACH_1_LP_INT_RAW + description: reg_0p3a_0_counter after xpd reach target0 + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: _0P3A_CNT_TARGET1_REACH_1_LP_INT_RAW + description: reg_0p3a_1_counter after xpd reach target1 + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LP_CPU_WAKEUP_INT_RAW + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SLEEP_SWITCH_ACTIVE_END_INT_RAW + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: ACTIVE_SWITCH_SLEEP_END_INT_RAW + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SLEEP_SWITCH_ACTIVE_START_INT_RAW + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ACTIVE_SWITCH_SLEEP_START_INT_RAW + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HP_SW_TRIGGER_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_INT_ST + description: need_des + addressOffset: 376 + size: 32 + fields: + - name: LP_CPU_SLEEP_REJECT_INT_ST + description: need_des + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: _0P1A_CNT_TARGET0_REACH_0_LP_INT_ST + description: reg_0p1a_0_counter after xpd reach target0 + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: _0P1A_CNT_TARGET1_REACH_0_LP_INT_ST + description: reg_0p1a_1_counter after xpd reach target1 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: _0P1A_CNT_TARGET0_REACH_1_LP_INT_ST + description: reg_0p1a_0 counter after xpd reach target0 + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: _0P1A_CNT_TARGET1_REACH_1_LP_INT_ST + description: reg_0p1a_1_counter after xpd reach target1 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: _0P2A_CNT_TARGET0_REACH_0_LP_INT_ST + description: reg_0p2a_0 counter after xpd reach target0 + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: _0P2A_CNT_TARGET1_REACH_0_LP_INT_ST + description: reg_0p2a_1_counter after xpd reach target1 + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: _0P2A_CNT_TARGET0_REACH_1_LP_INT_ST + description: reg_0p2a_0 counter after xpd reach target0 + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: _0P2A_CNT_TARGET1_REACH_1_LP_INT_ST + description: reg_0p2a_1_counter after xpd reach target1 + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: _0P3A_CNT_TARGET0_REACH_0_LP_INT_ST + description: reg_0p3a_0 counter after xpd reach target0 + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: _0P3A_CNT_TARGET1_REACH_0_LP_INT_ST + description: reg_0p3a_1_counter after xpd reach target1 + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: _0P3A_CNT_TARGET0_REACH_1_LP_INT_ST + description: reg_0p3a_0_counter after xpd reach target0 + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: _0P3A_CNT_TARGET1_REACH_1_LP_INT_ST + description: reg_0p3a_1_counter after xpd reach target1 + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: LP_CPU_WAKEUP_INT_ST + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: SLEEP_SWITCH_ACTIVE_END_INT_ST + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: ACTIVE_SWITCH_SLEEP_END_INT_ST + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SLEEP_SWITCH_ACTIVE_START_INT_ST + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: ACTIVE_SWITCH_SLEEP_START_INT_ST + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: HP_SW_TRIGGER_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: LP_INT_ENA + description: need_des + addressOffset: 380 + size: 32 + fields: + - name: LP_CPU_SLEEP_REJECT_INT_ENA + description: need_des + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: _0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA + description: reg_0p1a_0_counter after xpd reach target0 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: _0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA + description: reg_0p1a_1_counter after xpd reach target1 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: _0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA + description: reg_0p1a_0 counter after xpd reach target0 + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: _0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA + description: reg_0p1a_1_counter after xpd reach target1 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: _0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA + description: reg_0p2a_0 counter after xpd reach target0 + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: _0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA + description: reg_0p2a_1_counter after xpd reach target1 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: _0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA + description: reg_0p2a_0 counter after xpd reach target0 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: _0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA + description: reg_0p2a_1_counter after xpd reach target1 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: _0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA + description: reg_0p3a_0 counter after xpd reach target0 + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: _0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA + description: reg_0p3a_1_counter after xpd reach target1 + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: _0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA + description: reg_0p3a_0_counter after xpd reach target0 + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: _0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA + description: reg_0p3a_1_counter after xpd reach target1 + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LP_CPU_WAKEUP_INT_ENA + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SLEEP_SWITCH_ACTIVE_END_INT_ENA + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: ACTIVE_SWITCH_SLEEP_END_INT_ENA + description: need_des + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SLEEP_SWITCH_ACTIVE_START_INT_ENA + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ACTIVE_SWITCH_SLEEP_START_INT_ENA + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HP_SW_TRIGGER_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_INT_CLR + description: need_des + addressOffset: 384 + size: 32 + fields: + - name: LP_CPU_SLEEP_REJECT_LP_INT_CLR + description: need_des + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: _0P1A_CNT_TARGET0_REACH_0_LP_INT_CLR + description: reg_0p1a_0_counter after xpd reach target0 + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: _0P1A_CNT_TARGET1_REACH_0_LP_INT_CLR + description: reg_0p1a_1_counter after xpd reach target1 + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: _0P1A_CNT_TARGET0_REACH_1_LP_INT_CLR + description: reg_0p1a_0 counter after xpd reach target0 + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: _0P1A_CNT_TARGET1_REACH_1_LP_INT_CLR + description: reg_0p1a_1_counter after xpd reach target1 + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: _0P2A_CNT_TARGET0_REACH_0_LP_INT_CLR + description: reg_0p2a_0 counter after xpd reach target0 + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: _0P2A_CNT_TARGET1_REACH_0_LP_INT_CLR + description: reg_0p2a_1_counter after xpd reach target1 + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: _0P2A_CNT_TARGET0_REACH_1_LP_INT_CLR + description: reg_0p2a_0 counter after xpd reach target0 + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: _0P2A_CNT_TARGET1_REACH_1_LP_INT_CLR + description: reg_0p2a_1_counter after xpd reach target1 + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: _0P3A_CNT_TARGET0_REACH_0_LP_INT_CLR + description: reg_0p3a_0 counter after xpd reach target0 + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: _0P3A_CNT_TARGET1_REACH_0_LP_INT_CLR + description: reg_0p3a_1_counter after xpd reach target1 + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: _0P3A_CNT_TARGET0_REACH_1_LP_INT_CLR + description: reg_0p3a_0_counter after xpd reach target0 + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: _0P3A_CNT_TARGET1_REACH_1_LP_INT_CLR + description: reg_0p3a_1_counter after xpd reach target1 + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: LP_CPU_WAKEUP_INT_CLR + description: need_des + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: SLEEP_SWITCH_ACTIVE_END_INT_CLR + description: need_des + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: ACTIVE_SWITCH_SLEEP_END_INT_CLR + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: SLEEP_SWITCH_ACTIVE_START_INT_CLR + description: need_des + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: ACTIVE_SWITCH_SLEEP_START_INT_CLR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: HP_SW_TRIGGER_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: LP_CPU_PWR0 + description: need_des + addressOffset: 388 + size: 32 + resetValue: 535822336 + fields: + - name: LP_CPU_WAITI_RDY + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: LP_CPU_STALL_RDY + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: LP_CPU_FORCE_STALL + description: need_des + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: LP_CPU_SLP_WAITI_FLAG_EN + description: need_des + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: LP_CPU_SLP_STALL_FLAG_EN + description: need_des + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: LP_CPU_SLP_STALL_WAIT + description: need_des + bitOffset: 21 + bitWidth: 8 + access: read-write + - name: LP_CPU_SLP_STALL_EN + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LP_CPU_SLP_RESET_EN + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_CPU_SLP_BYPASS_INTR_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_CPU_PWR1 + description: need_des + addressOffset: 392 + size: 32 + fields: + - name: LP_CPU_SLEEP_REQ + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: LP_CPU_PWR2 + description: need_des + addressOffset: 396 + size: 32 + fields: + - name: LP_CPU_WAKEUP_EN + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - register: + name: LP_CPU_PWR3 + description: need_des + addressOffset: 400 + size: 32 + fields: + - name: LP_CPU_WAKEUP_CAUSE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-only + - register: + name: LP_CPU_PWR4 + description: need_des + addressOffset: 404 + size: 32 + fields: + - name: LP_CPU_REJECT_EN + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - register: + name: LP_CPU_PWR5 + description: need_des + addressOffset: 408 + size: 32 + fields: + - name: LP_CPU_REJECT_CAUSE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-only + - register: + name: HP_LP_CPU_COMM + description: need_des + addressOffset: 412 + size: 32 + fields: + - name: LP_TRIGGER_HP + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: HP_TRIGGER_LP + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: HP_REGULATOR_CFG + description: need_des + addressOffset: 416 + size: 32 + fields: + - name: DIG_REGULATOR_EN_CAL + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: MAIN_STATE + description: need_des + addressOffset: 420 + size: 32 + resetValue: 135268353 + fields: + - name: ENABLE_CALI_PMU_CNTL + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PMU_MAIN_LAST_ST_STATE + description: need_des + bitOffset: 11 + bitWidth: 7 + access: read-only + - name: PMU_MAIN_TAR_ST_STATE + description: need_des + bitOffset: 18 + bitWidth: 7 + access: read-only + - name: PMU_MAIN_CUR_ST_STATE + description: need_des + bitOffset: 25 + bitWidth: 7 + access: read-only + - register: + name: PWR_STATE + description: need_des + addressOffset: 424 + size: 32 + resetValue: 8396800 + fields: + - name: PMU_BACKUP_ST_STATE + description: need_des + bitOffset: 13 + bitWidth: 5 + access: read-only + - name: PMU_LP_PWR_ST_STATE + description: need_des + bitOffset: 18 + bitWidth: 5 + access: read-only + - name: PMU_HP_PWR_ST_STATE + description: need_des + bitOffset: 23 + bitWidth: 9 + access: read-only + - register: + name: CLK_STATE0 + description: need_des + addressOffset: 428 + size: 32 + resetValue: 15 + fields: + - name: STABLE_XPD_PLL_STATE + description: need_des + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: STABLE_XPD_XTAL_STATE + description: need_des + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: PMU_ANA_XPD_PLL_I2C_STATE + description: need_des + bitOffset: 4 + bitWidth: 3 + access: read-only + - name: PMU_SYS_CLK_SLP_SEL_STATE + description: need_des + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: PMU_SYS_CLK_SEL_STATE + description: need_des + bitOffset: 11 + bitWidth: 2 + access: read-only + - name: PMU_SYS_CLK_NO_DIV_STATE + description: need_des + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: PMU_ICG_SYS_CLK_EN_STATE + description: need_des + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: PMU_ICG_MODEM_SWITCH_STATE + description: need_des + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: PMU_ICG_MODEM_CODE_STATE + description: need_des + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: PMU_ICG_SLP_SEL_STATE + description: need_des + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: PMU_ICG_GLOBAL_XTAL_STATE + description: need_des + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: PMU_ICG_GLOBAL_PLL_STATE + description: need_des + bitOffset: 20 + bitWidth: 4 + access: read-only + - name: PMU_ANA_I2C_ISO_EN_STATE + description: need_des + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: PMU_ANA_I2C_RETENTION_STATE + description: need_des + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: PMU_ANA_XPD_PLL_STATE + description: need_des + bitOffset: 27 + bitWidth: 4 + access: read-only + - name: PMU_ANA_XPD_XTAL_STATE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CLK_STATE1 + description: need_des + addressOffset: 432 + size: 32 + resetValue: 4294967295 + fields: + - name: PMU_ICG_FUNC_EN_STATE + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CLK_STATE2 + description: need_des + addressOffset: 436 + size: 32 + resetValue: 4294967295 + fields: + - name: PMU_ICG_APB_EN_STATE + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: EXT_LDO_P0_0P1A + description: need_des + addressOffset: 440 + size: 32 + resetValue: 1075839232 + fields: + - name: _0P1A_FORCE_TIEH_SEL_0 + description: need_des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: _0P1A_XPD_0 + description: need_des + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: _0P1A_TIEH_SEL_0 + description: need_des + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: _0P1A_TIEH_POS_EN_0 + description: need_des + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: _0P1A_TIEH_NEG_EN_0 + description: need_des + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: _0P1A_TIEH_0 + description: need_des + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: _0P1A_TARGET1_0 + description: need_des + bitOffset: 15 + bitWidth: 8 + access: read-write + - name: _0P1A_TARGET0_0 + description: need_des + bitOffset: 23 + bitWidth: 8 + access: read-write + - name: _0P1A_LDO_CNT_PRESCALER_SEL_0 + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EXT_LDO_P0_0P1A_ANA + description: need_des + addressOffset: 444 + size: 32 + resetValue: 2969567232 + fields: + - name: ANA_0P1A_MUL_0 + description: need_des + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: ANA_0P1A_EN_VDET_0 + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: ANA_0P1A_EN_CUR_LIM_0 + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: ANA_0P1A_DREF_0 + description: need_des + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: EXT_LDO_P0_0P2A + description: need_des + addressOffset: 448 + size: 32 + resetValue: 1075838976 + fields: + - name: _0P2A_FORCE_TIEH_SEL_0 + description: need_des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: _0P2A_XPD_0 + description: need_des + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: _0P2A_TIEH_SEL_0 + description: need_des + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: _0P2A_TIEH_POS_EN_0 + description: need_des + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: _0P2A_TIEH_NEG_EN_0 + description: need_des + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: _0P2A_TIEH_0 + description: need_des + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: _0P2A_TARGET1_0 + description: need_des + bitOffset: 15 + bitWidth: 8 + access: read-write + - name: _0P2A_TARGET0_0 + description: need_des + bitOffset: 23 + bitWidth: 8 + access: read-write + - name: _0P2A_LDO_CNT_PRESCALER_SEL_0 + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EXT_LDO_P0_0P2A_ANA + description: need_des + addressOffset: 452 + size: 32 + resetValue: 2684354560 + fields: + - name: ANA_0P2A_MUL_0 + description: need_des + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: ANA_0P2A_EN_VDET_0 + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: ANA_0P2A_EN_CUR_LIM_0 + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: ANA_0P2A_DREF_0 + description: need_des + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: EXT_LDO_P0_0P3A + description: need_des + addressOffset: 456 + size: 32 + resetValue: 1075838976 + fields: + - name: _0P3A_FORCE_TIEH_SEL_0 + description: need_des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: _0P3A_XPD_0 + description: need_des + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: _0P3A_TIEH_SEL_0 + description: need_des + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: _0P3A_TIEH_POS_EN_0 + description: need_des + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: _0P3A_TIEH_NEG_EN_0 + description: need_des + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: _0P3A_TIEH_0 + description: need_des + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: _0P3A_TARGET1_0 + description: need_des + bitOffset: 15 + bitWidth: 8 + access: read-write + - name: _0P3A_TARGET0_0 + description: need_des + bitOffset: 23 + bitWidth: 8 + access: read-write + - name: _0P3A_LDO_CNT_PRESCALER_SEL_0 + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EXT_LDO_P0_0P3A_ANA + description: need_des + addressOffset: 460 + size: 32 + resetValue: 2684354560 + fields: + - name: ANA_0P3A_MUL_0 + description: need_des + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: ANA_0P3A_EN_VDET_0 + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: ANA_0P3A_EN_CUR_LIM_0 + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: ANA_0P3A_DREF_0 + description: need_des + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: EXT_LDO_P1_0P1A + description: need_des + addressOffset: 464 + size: 32 + resetValue: 1075838976 + fields: + - name: _0P1A_FORCE_TIEH_SEL_1 + description: need_des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: _0P1A_XPD_1 + description: need_des + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: _0P1A_TIEH_SEL_1 + description: need_des + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: _0P1A_TIEH_POS_EN_1 + description: need_des + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: _0P1A_TIEH_NEG_EN_1 + description: need_des + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: _0P1A_TIEH_1 + description: need_des + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: _0P1A_TARGET1_1 + description: need_des + bitOffset: 15 + bitWidth: 8 + access: read-write + - name: _0P1A_TARGET0_1 + description: need_des + bitOffset: 23 + bitWidth: 8 + access: read-write + - name: _0P1A_LDO_CNT_PRESCALER_SEL_1 + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EXT_LDO_P1_0P1A_ANA + description: need_des + addressOffset: 468 + size: 32 + resetValue: 2684354560 + fields: + - name: ANA_0P1A_MUL_1 + description: need_des + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: ANA_0P1A_EN_VDET_1 + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: ANA_0P1A_EN_CUR_LIM_1 + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: ANA_0P1A_DREF_1 + description: need_des + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: EXT_LDO_P1_0P2A + description: need_des + addressOffset: 472 + size: 32 + resetValue: 1075838976 + fields: + - name: _0P2A_FORCE_TIEH_SEL_1 + description: need_des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: _0P2A_XPD_1 + description: need_des + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: _0P2A_TIEH_SEL_1 + description: need_des + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: _0P2A_TIEH_POS_EN_1 + description: need_des + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: _0P2A_TIEH_NEG_EN_1 + description: need_des + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: _0P2A_TIEH_1 + description: need_des + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: _0P2A_TARGET1_1 + description: need_des + bitOffset: 15 + bitWidth: 8 + access: read-write + - name: _0P2A_TARGET0_1 + description: need_des + bitOffset: 23 + bitWidth: 8 + access: read-write + - name: _0P2A_LDO_CNT_PRESCALER_SEL_1 + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EXT_LDO_P1_0P2A_ANA + description: need_des + addressOffset: 476 + size: 32 + resetValue: 2684354560 + fields: + - name: ANA_0P2A_MUL_1 + description: need_des + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: ANA_0P2A_EN_VDET_1 + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: ANA_0P2A_EN_CUR_LIM_1 + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: ANA_0P2A_DREF_1 + description: need_des + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: EXT_LDO_P1_0P3A + description: need_des + addressOffset: 480 + size: 32 + resetValue: 1075838976 + fields: + - name: _0P3A_FORCE_TIEH_SEL_1 + description: need_des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: _0P3A_XPD_1 + description: need_des + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: _0P3A_TIEH_SEL_1 + description: need_des + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: _0P3A_TIEH_POS_EN_1 + description: need_des + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: _0P3A_TIEH_NEG_EN_1 + description: need_des + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: _0P3A_TIEH_1 + description: need_des + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: _0P3A_TARGET1_1 + description: need_des + bitOffset: 15 + bitWidth: 8 + access: read-write + - name: _0P3A_TARGET0_1 + description: need_des + bitOffset: 23 + bitWidth: 8 + access: read-write + - name: _0P3A_LDO_CNT_PRESCALER_SEL_1 + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EXT_LDO_P1_0P3A_ANA + description: need_des + addressOffset: 484 + size: 32 + resetValue: 2684354560 + fields: + - name: ANA_0P3A_MUL_1 + description: need_des + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: ANA_0P3A_EN_VDET_1 + description: need_des + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: ANA_0P3A_EN_CUR_LIM_1 + description: need_des + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: ANA_0P3A_DREF_1 + description: need_des + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: EXT_WAKEUP_LV + description: need_des + addressOffset: 488 + size: 32 + fields: + - name: EXT_WAKEUP_LV + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: EXT_WAKEUP_SEL + description: need_des + addressOffset: 492 + size: 32 + fields: + - name: EXT_WAKEUP_SEL + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: EXT_WAKEUP_ST + description: need_des + addressOffset: 496 + size: 32 + fields: + - name: EXT_WAKEUP_STATUS + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: EXT_WAKEUP_CNTL + description: need_des + addressOffset: 500 + size: 32 + fields: + - name: EXT_WAKEUP_STATUS_CLR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: EXT_WAKEUP_FILTER + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SDIO_WAKEUP_CNTL + description: need_des + addressOffset: 504 + size: 32 + resetValue: 1023 + fields: + - name: SDIO_ACT_DNUM + description: need_des + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: XTAL_SLP + description: need_des + addressOffset: 508 + size: 32 + resetValue: 983040 + fields: + - name: CNT_TARGET + description: need_des + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: CPU_SW_STALL + description: need_des + addressOffset: 512 + size: 32 + fields: + - name: HPCORE1_SW_STALL_CODE + description: need_des + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: HPCORE0_SW_STALL_CODE + description: need_des + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: DCM_CTRL + description: need_des + addressOffset: 516 + size: 32 + resetValue: 65536 + fields: + - name: DCDC_ON_REQ + description: SW trigger dcdc on + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: DCDC_OFF_REQ + description: SW trigger dcdc off + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DCDC_LIGHTSLP_REQ + description: SW trigger dcdc enter lightsleep + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: DCDC_DEEPSLP_REQ + description: SW trigger dcdc enter deepsleep + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: DCDC_DONE_FORCE + description: need_des + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DCDC_ON_FORCE_PU + description: need_des + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DCDC_ON_FORCE_PD + description: need_des + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DCDC_FB_RES_FORCE_PU + description: need_des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DCDC_FB_RES_FORCE_PD + description: need_des + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DCDC_LS_FORCE_PU + description: need_des + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DCDC_LS_FORCE_PD + description: need_des + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DCDC_DS_FORCE_PU + description: need_des + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DCDC_DS_FORCE_PD + description: need_des + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DCM_CUR_ST + description: need_des + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: DCDC_EN_AMUX_TEST + description: Enable analog mux to pull PAD TEST_DCDC voltage signal + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: DCM_WAIT_DELAY + description: need_des + addressOffset: 520 + size: 32 + resetValue: 4915717 + fields: + - name: DCDC_PRE_DELAY + description: DCDC pre-on/post off delay + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: DCDC_RES_OFF_DELAY + description: DCDC fb res off delay + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: DCDC_STABLE_DELAY + description: DCDC stable delay + bitOffset: 16 + bitWidth: 10 + access: read-write + - register: + name: VDDBAT_CFG + description: need_des + addressOffset: 524 + size: 32 + fields: + - name: ANA_VDDBAT_MODE + description: need_des + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: VDDBAT_SW_UPDATE + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: TOUCH_PWR_CNTL + description: need_des + addressOffset: 528 + size: 32 + resetValue: 1638720 + fields: + - name: TOUCH_WAIT_CYCLES + description: need_des + bitOffset: 5 + bitWidth: 9 + access: read-write + - name: TOUCH_SLEEP_CYCLES + description: need_des + bitOffset: 14 + bitWidth: 16 + access: read-write + - name: TOUCH_FORCE_DONE + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TOUCH_SLEEP_TIMER_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RDN_ECO + description: need_des + addressOffset: 532 + size: 32 + fields: + - name: PMU_RDN_ECO_RESULT + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PMU_RDN_ECO_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 36712768 + fields: + - name: PMU_DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: PPA + description: PPA Peripheral + groupName: PPA + baseAddress: 1342730240 + addressBlock: + - offset: 0 + size: 136 + usage: registers + interrupt: + - name: PPA + value: 96 + registers: + - register: + name: BLEND0_CLUT_DATA + description: CLUT sram data read/write register in background plane of blender + addressOffset: 0 + size: 32 + fields: + - name: RDWR_WORD_BLEND0_CLUT + description: Write and read data to/from CLUT RAM in background plane of blender engine through this field in fifo mode. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: BLEND1_CLUT_DATA + description: CLUT sram data read/write register in foreground plane of blender + addressOffset: 4 + size: 32 + fields: + - name: RDWR_WORD_BLEND1_CLUT + description: Write and read data to/from CLUT RAM in foreground plane of blender engine through this field in fifo mode. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CLUT_CONF + description: CLUT configure register + addressOffset: 12 + size: 32 + fields: + - name: APB_FIFO_MASK + description: "1'b0: fifo mode to wr/rd clut0/clut1 RAM through register PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1: memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr should be 01 to access sr clut and should be 10 to access blend0 clut and should be 11 to access blend 1 clut in memory mode." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: BLEND0_CLUT_MEM_RST + description: Write 1 then write 0 to this bit to reset BLEND0 CLUT. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BLEND1_CLUT_MEM_RST + description: Write 1 then write 0 to this bit to reset BLEND1 CLUT. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: BLEND0_CLUT_MEM_RDADDR_RST + description: Write 1 then write 0 to reset the read address of BLEND0 CLUT in fifo mode. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: BLEND1_CLUT_MEM_RDADDR_RST + description: Write 1 then write 0 to reset the read address of BLEND1 CLUT in fifo mode. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: BLEND0_CLUT_MEM_FORCE_PD + description: "1: force power down BLEND CLUT memory." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BLEND0_CLUT_MEM_FORCE_PU + description: "1: force power up BLEND CLUT memory." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BLEND0_CLUT_MEM_CLK_ENA + description: "1: Force clock on for BLEND CLUT memory." + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: Raw status interrupt + addressOffset: 16 + size: 32 + fields: + - name: SR_EOF_INT_RAW + description: The raw interrupt bit turns to high level when scaling and rotating engine calculate one frame image. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: BLEND_EOF_INT_RAW + description: The raw interrupt bit turns to high level when blending engine calculate one frame image. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SR_PARAM_CFG_ERR_INT_RAW + description: The raw interrupt bit turns to high level when the configured scaling and rotating coefficient is wrong. User can check the reasons through register PPA_SR_PARAM_ERR_ST_REG. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Masked interrupt + addressOffset: 20 + size: 32 + fields: + - name: SR_EOF_INT_ST + description: The raw interrupt status bit for the PPA_SR_EOF_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: BLEND_EOF_INT_ST + description: The raw interrupt status bit for the PPA_BLEND_EOF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SR_PARAM_CFG_ERR_INT_ST + description: The raw interrupt status bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 24 + size: 32 + fields: + - name: SR_EOF_INT_ENA + description: The interrupt enable bit for the PPA_SR_EOF_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: BLEND_EOF_INT_ENA + description: The interrupt enable bit for the PPA_BLEND_EOF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SR_PARAM_CFG_ERR_INT_ENA + description: The interrupt enable bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 28 + size: 32 + fields: + - name: SR_EOF_INT_CLR + description: Set this bit to clear the PPA_SR_EOF_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: BLEND_EOF_INT_CLR + description: Set this bit to clear the PPA_BLEND_EOF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SR_PARAM_CFG_ERR_INT_CLR + description: Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - register: + name: SR_COLOR_MODE + description: Scaling and rotating engine color mode register + addressOffset: 32 + size: 32 + fields: + - name: SR_RX_CM + description: "The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: SR_TX_CM + description: "The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888. 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: YUV_RX_RANGE + description: "YUV input range when reg_sr_rx_cm is 4'd8. 0: limit range. 1: full range" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: YUV_TX_RANGE + description: "YUV output range when reg_sr_tx_cm is 4'd8. 0: limit range. 1: full range" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: YUV2RGB_PROTOCAL + description: "YUV to RGB protocal when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: RGB2YUV_PROTOCAL + description: "RGB to YUV protocal when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709" + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: BLEND_COLOR_MODE + description: blending engine color mode register + addressOffset: 36 + size: 32 + fields: + - name: BLEND0_RX_CM + description: "The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved. 4: L8. 5: L4." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: BLEND1_RX_CM + description: "The source image color mode for foreground plane. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved. 4: L8. 5: L4. 6: A8. 7: A4." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: BLEND_TX_CM + description: "The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2: RGB565. 3: Reserved.." + bitOffset: 8 + bitWidth: 4 + access: read-write + - register: + name: SR_BYTE_ORDER + description: Scaling and rotating engine byte order register + addressOffset: 40 + size: 32 + fields: + - name: SR_RX_BYTE_SWAP_EN + description: Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SR_RX_RGB_SWAP_EN + description: Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SR_MACRO_BK_RO_BYPASS + description: Set this bit to 1 to bypass the macro block order function. This function is used to improve efficient accessing external memory. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: BLEND_BYTE_ORDER + description: Blending engine byte order register + addressOffset: 44 + size: 32 + fields: + - name: BLEND0_RX_BYTE_SWAP_EN + description: Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: BLEND1_RX_BYTE_SWAP_EN + description: Set this bit to 1 the data into Rx channel 0 would be swapped in byte. The Byte0 and Byte1 would be swapped while byte 2 and byte 3 would be swappped. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BLEND0_RX_RGB_SWAP_EN + description: Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: BLEND1_RX_RGB_SWAP_EN + description: Set this bit to 1 the data into Rx channel 0 would be swapped in rgb. It means rgb would be swap to bgr. + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: BLEND_TRANS_MODE + description: Blending engine mode configure register + addressOffset: 52 + size: 32 + fields: + - name: BLEND_EN + description: Set this bit to enable alpha blending. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: BLEND_BYPASS + description: Set this bit to bypass blender. Then background date would be output. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BLEND_FIX_PIXEL_FILL_EN + description: This bit is used to enable fix pixel filling. When this mode is enable only Tx channel is work and the output pixel is configured by PPA_OUT_FIX_PIXEL. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: UPDATE + description: Set this bit to update the transfer mode. Only the bit is set the transfer mode is valid. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: BLEND_RST + description: write 1 then write 0 to reset blending engine. + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: SR_FIX_ALPHA + description: Scaling and rotating engine alpha override register + addressOffset: 56 + size: 32 + resetValue: 128 + fields: + - name: SR_RX_FIX_ALPHA + description: The value would replace the alpha value in received pixel for Scaling and Rotating engine when PPA_SR_RX_ALPHA_CONF_EN is enabled. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SR_RX_ALPHA_MOD + description: "Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256." + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: SR_RX_ALPHA_INV + description: Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255. + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: BLEND_TX_SIZE + description: Fix pixel filling mode image size register + addressOffset: 60 + size: 32 + fields: + - name: BLEND_HB + description: The horizontal width of image block that would be filled in fix pixel filling mode. The unit is pixel + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: BLEND_VB + description: The vertical width of image block that would be filled in fix pixel filling mode. The unit is pixel + bitOffset: 14 + bitWidth: 14 + access: read-write + - register: + name: BLEND_FIX_ALPHA + description: Blending engine alpha override register + addressOffset: 64 + size: 32 + resetValue: 32896 + fields: + - name: BLEND0_RX_FIX_ALPHA + description: The value would replace the alpha value in received pixel for background plane of blender when PPA_BLEND0_RX_ALPHA_CONF_EN is enabled. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: BLEND1_RX_FIX_ALPHA + description: The value would replace the alpha value in received pixel for foreground plane of blender when PPA_BLEND1_RX_ALPHA_CONF_EN is enabled. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: BLEND0_RX_ALPHA_MOD + description: "Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: BLEND1_RX_ALPHA_MOD + description: "Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2: Original alpha multiply with PPA_SR_FIX_ALPHA/256." + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: BLEND0_RX_ALPHA_INV + description: Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: BLEND1_RX_ALPHA_INV + description: Set this bit to invert the original alpha value. When RX color mode is RGB565/RGB88. The original alpha value is 255. + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + name: BLEND_RGB + description: RGB color register + addressOffset: 72 + size: 32 + resetValue: 8421504 + fields: + - name: BLEND1_RX_B + description: blue color for A4/A8 mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: BLEND1_RX_G + description: green color for A4/A8 mode. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: BLEND1_RX_R + description: red color for A4/A8 mode. + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: BLEND_FIX_PIXEL + description: Blending engine fix pixel register + addressOffset: 76 + size: 32 + fields: + - name: BLEND_TX_FIX_PIXEL + description: The configure fix pixel in fix pixel filling mode for blender engine. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CK_FG_LOW + description: foreground color key lower threshold + addressOffset: 80 + size: 32 + resetValue: 16777215 + fields: + - name: COLORKEY_FG_B_LOW + description: color key lower threshold of foreground b channel + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: COLORKEY_FG_G_LOW + description: color key lower threshold of foreground g channel + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: COLORKEY_FG_R_LOW + description: color key lower threshold of foreground r channel + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: CK_FG_HIGH + description: foreground color key higher threshold + addressOffset: 84 + size: 32 + fields: + - name: COLORKEY_FG_B_HIGH + description: color key higher threshold of foreground b channel + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: COLORKEY_FG_G_HIGH + description: color key higher threshold of foreground g channel + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: COLORKEY_FG_R_HIGH + description: color key higher threshold of foreground r channel + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: CK_BG_LOW + description: background color key lower threshold + addressOffset: 88 + size: 32 + resetValue: 16777215 + fields: + - name: COLORKEY_BG_B_LOW + description: color key lower threshold of background b channel + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: COLORKEY_BG_G_LOW + description: color key lower threshold of background g channel + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: COLORKEY_BG_R_LOW + description: color key lower threshold of background r channel + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: CK_BG_HIGH + description: background color key higher threshold + addressOffset: 92 + size: 32 + fields: + - name: COLORKEY_BG_B_HIGH + description: color key higher threshold of background b channel + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: COLORKEY_BG_G_HIGH + description: color key higher threshold of background g channel + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: COLORKEY_BG_R_HIGH + description: color key higher threshold of background r channel + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: CK_DEFAULT + description: default value when foreground and background both in color key range + addressOffset: 96 + size: 32 + fields: + - name: COLORKEY_DEFAULT_B + description: default B channle value of color key + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: COLORKEY_DEFAULT_G + description: default G channle value of color key + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: COLORKEY_DEFAULT_R + description: default R channle value of color key + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: COLORKEY_FG_BG_REVERSE + description: "when pixel in bg ck range but not in fg ck range, 0: the result is bg, 1: the result is fg" + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: SR_SCAL_ROTATE + description: Scaling and rotating coefficient register + addressOffset: 100 + size: 32 + resetValue: 4097 + fields: + - name: SR_SCAL_X_INT + description: The integrated part of scaling coefficient in X direction. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SR_SCAL_X_FRAG + description: The fragment part of scaling coefficient in X direction. + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: SR_SCAL_Y_INT + description: The integrated part of scaling coefficient in Y direction. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: SR_SCAL_Y_FRAG + description: The fragment part of scaling coefficient in Y direction. + bitOffset: 20 + bitWidth: 4 + access: read-write + - name: SR_ROTATE_ANGLE + description: "The rotate angle. 0: 0 degree. 1: 90 degree. 2: 180 degree. 3: 270 degree." + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: SCAL_ROTATE_RST + description: Write 1 then write 0 to this bit to reset scaling and rotating engine. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SCAL_ROTATE_START + description: Write 1 to enable scaling and rotating engine after parameter is configured. + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: SR_MIRROR_X + description: "Image mirror in X direction. 0: disable, 1: enable" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SR_MIRROR_Y + description: "Image mirror in Y direction. 0: disable, 1: enable" + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: SR_MEM_PD + description: SR memory power done register + addressOffset: 104 + size: 32 + fields: + - name: SR_MEM_CLK_ENA + description: "Set this bit to force clock enable of scaling and rotating engine's data memory." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SR_MEM_FORCE_PD + description: "Set this bit to force power down scaling and rotating engine's data memory." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SR_MEM_FORCE_PU + description: "Set this bit to force power up scaling and rotating engine's data memory." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: REG_CONF + description: Register clock enable register + addressOffset: 108 + size: 32 + fields: + - name: CLK_EN + description: PPA register clock gate enable signal. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CLUT_CNT + description: BLEND CLUT write counter register + addressOffset: 112 + size: 32 + fields: + - name: BLEND0_CLUT_CNT + description: The write data counter of BLEND0 CLUT in fifo mode. + bitOffset: 0 + bitWidth: 9 + access: read-only + - name: BLEND1_CLUT_CNT + description: The write data counter of BLEND1 CLUT in fifo mode. + bitOffset: 9 + bitWidth: 9 + access: read-only + - register: + name: BLEND_ST + description: Blending engine status register + addressOffset: 116 + size: 32 + fields: + - name: BLEND_SIZE_DIFF_ST + description: "1: indicate the size of two image is different." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: SR_PARAM_ERR_ST + description: Scaling and rotating coefficient error register + addressOffset: 120 + size: 32 + fields: + - name: TX_DSCR_VB_ERR_ST + description: The error is that the scaled VB plus the offset of Y coordinate in 2DDMA receive descriptor is larger than VA in 2DDMA receive descriptor. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_DSCR_HB_ERR_ST + description: The error is that the scaled HB plus the offset of X coordinate in 2DDMA receive descriptor is larger than HA in 2DDMA receive descriptor. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: Y_RX_SCAL_EQUAL_0_ERR_ST + description: The error is that the PPA_SR_SCAL_Y_INT and PPA_SR_CAL_Y_FRAG both are 0. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: RX_DSCR_VB_ERR_ST + description: The error is that VB in 2DDMA receive descriptor plus the offset of Y coordinate in 2DDMA transmit descriptor is larger than VA in 2DDMA transmit descriptor + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: YDST_LEN_TOO_SAMLL_ERR_ST + description: The error is that the scaled image width is 0. For example. when source width is 14. scaled value is 1/16. and no rotate operation. then scaled width would be 0 as the result would be floored. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: YDST_LEN_TOO_LARGE_ERR_ST + description: The error is that the scaled width is larger than (2^13 - 1). + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: X_RX_SCAL_EQUAL_0_ERR_ST + description: The error is that the scaled image height is 0. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: RX_DSCR_HB_ERR_ST + description: The error is that the HB in 2DDMA transmit descriptor plus the offset of X coordinate in 2DDMA transmit descriptor is larger than HA in 2DDMA transmit descriptor. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: XDST_LEN_TOO_SAMLL_ERR_ST + description: The error is that the scaled image height is 0. For example. when source height is 14. scaled value is 1/16. and no rotate operation. then scaled height would be 0 as the result would be floored. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: XDST_LEN_TOO_LARGE_ERR_ST + description: The error is that the scaled image height is larger than (2^13 - 1). + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: X_YUV420_RX_SCALE_ERR_ST + description: The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable yuv420 rx + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: Y_YUV420_RX_SCALE_ERR_ST + description: The error is that the va/vb/y param in dma2d descriptor is an odd num when enable yuv420 rx + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: X_YUV420_TX_SCALE_ERR_ST + description: The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable yuv420 tx + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: Y_YUV420_TX_SCALE_ERR_ST + description: The error is that the va/vb/y param in dma2d descriptor is an odd num when enable yuv420 tx + bitOffset: 13 + bitWidth: 1 + access: read-only + - register: + name: SR_STATUS + description: SR FSM register + addressOffset: 124 + size: 32 + fields: + - name: SR_RX_DSCR_SAMPLE_STATE + description: Reserved. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: SR_RX_SCAN_STATE + description: Reserved. + bitOffset: 2 + bitWidth: 2 + access: read-only + - name: SR_TX_DSCR_SAMPLE_STATE + description: Reserved. + bitOffset: 4 + bitWidth: 2 + access: read-only + - name: SR_TX_SCAN_STATE + description: Reserved. + bitOffset: 6 + bitWidth: 3 + access: read-only + - register: + name: ECO_LOW + description: Reserved. + addressOffset: 128 + size: 32 + fields: + - name: RND_ECO_LOW + description: Reserved. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ECO_HIGH + description: Reserved. + addressOffset: 132 + size: 32 + resetValue: 4294967295 + fields: + - name: RND_ECO_HIGH + description: Reserved. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ECO_CELL_CTRL + description: Reserved. + addressOffset: 136 + size: 32 + fields: + - name: RDN_RESULT + description: Reserved. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RDN_ENA + description: Reserved. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: SRAM_CTRL + description: PPA SRAM Control Register + addressOffset: 140 + size: 32 + resetValue: 4896 + fields: + - name: MEM_AUX_CTRL + description: Control signals + bitOffset: 0 + bitWidth: 14 + access: read-write + - register: + name: DATE + description: PPA Version register + addressOffset: 256 + size: 32 + resetValue: 36716609 + fields: + - name: DATE + description: register version. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: PVT + description: PVT Peripheral + groupName: PVT + baseAddress: 1342824448 + addressBlock: + - offset: 0 + size: 496 + usage: registers + registers: + - register: + name: PMUP_BITMAP_HIGH0 + description: select valid pvt channel + addressOffset: 0 + size: 32 + fields: + - name: PUMP_BITMAP_HIGH0 + description: select valid high channel0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PMUP_BITMAP_HIGH1 + description: select valid pvt channel + addressOffset: 4 + size: 32 + fields: + - name: PUMP_BITMAP_HIGH1 + description: select valid high channel1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PMUP_BITMAP_HIGH2 + description: select valid pvt channel + addressOffset: 8 + size: 32 + fields: + - name: PUMP_BITMAP_HIGH2 + description: select valid high channel2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PMUP_BITMAP_HIGH3 + description: select valid pvt channel + addressOffset: 12 + size: 32 + fields: + - name: PUMP_BITMAP_HIGH3 + description: select valid high channel3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PMUP_BITMAP_HIGH4 + description: select valid pvt channel + addressOffset: 16 + size: 32 + fields: + - name: PUMP_BITMAP_HIGH4 + description: select valid high channel4 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PMUP_BITMAP_LOW0 + description: select valid pvt channel + addressOffset: 20 + size: 32 + fields: + - name: PUMP_BITMAP_LOW0 + description: select valid low channel0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PMUP_BITMAP_LOW1 + description: select valid pvt channel + addressOffset: 24 + size: 32 + fields: + - name: PUMP_BITMAP_LOW1 + description: select valid low channel1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PMUP_BITMAP_LOW2 + description: select valid pvt channel + addressOffset: 28 + size: 32 + fields: + - name: PUMP_BITMAP_LOW2 + description: select valid low channel2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PMUP_BITMAP_LOW3 + description: select valid pvt channel + addressOffset: 32 + size: 32 + fields: + - name: PUMP_BITMAP_LOW3 + description: select valid low channel3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PMUP_BITMAP_LOW4 + description: select valid pvt channel + addressOffset: 36 + size: 32 + fields: + - name: PUMP_BITMAP_LOW4 + description: select valid low channel4 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PMUP_DRV_CFG + description: configure pump drv + addressOffset: 40 + size: 32 + fields: + - name: PUMP_EN + description: configure pvt charge xpd + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: force register clken + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: PUMP_DRV4 + description: configure cmd4 drv + bitOffset: 11 + bitWidth: 4 + access: read-write + - name: PUMP_DRV3 + description: configure cmd3 drv + bitOffset: 15 + bitWidth: 4 + access: read-write + - name: PUMP_DRV2 + description: configure cmd2 drv + bitOffset: 19 + bitWidth: 4 + access: read-write + - name: PUMP_DRV1 + description: configure cmd1 drv + bitOffset: 23 + bitWidth: 4 + access: read-write + - name: PUMP_DRV0 + description: configure cmd0 drv + bitOffset: 27 + bitWidth: 4 + access: read-write + - register: + name: PMUP_CHANNEL_CFG + description: configure the code of valid pump channel code + addressOffset: 44 + size: 32 + fields: + - name: PUMP_CHANNEL_CODE4 + description: configure cmd4 code + bitOffset: 7 + bitWidth: 5 + access: read-write + - name: PUMP_CHANNEL_CODE3 + description: configure cmd3 code + bitOffset: 12 + bitWidth: 5 + access: read-write + - name: PUMP_CHANNEL_CODE2 + description: configure cmd2 code + bitOffset: 17 + bitWidth: 5 + access: read-write + - name: PUMP_CHANNEL_CODE1 + description: configure cmd1 code + bitOffset: 22 + bitWidth: 5 + access: read-write + - name: PUMP_CHANNEL_CODE0 + description: configure cmd0 code + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: CLK_CFG + description: configure pvt clk + addressOffset: 48 + size: 32 + fields: + - name: PUMP_CLK_DIV_NUM + description: needs field desc + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: MONITOR_CLK_PVT_EN + description: needs field desc + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CLK_SEL + description: select pvt clk + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DBIAS_CHANNEL_SEL0 + description: needs desc + addressOffset: 52 + size: 32 + resetValue: 2164392960 + fields: + - name: DBIAS_CHANNEL3_SEL + description: needs field desc + bitOffset: 4 + bitWidth: 7 + access: read-write + - name: DBIAS_CHANNEL2_SEL + description: needs field desc + bitOffset: 11 + bitWidth: 7 + access: read-write + - name: DBIAS_CHANNEL1_SEL + description: needs field desc + bitOffset: 18 + bitWidth: 7 + access: read-write + - name: DBIAS_CHANNEL0_SEL + description: needs field desc + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: DBIAS_CHANNEL_SEL1 + description: needs desc + addressOffset: 56 + size: 32 + resetValue: 2147483648 + fields: + - name: DBIAS_CHANNEL4_SEL + description: needs field desc + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: DBIAS_CHANNEL0_SEL + description: needs desc + addressOffset: 60 + size: 32 + fields: + - name: DBIAS_CHANNEL0_CFG + description: needs field desc + bitOffset: 0 + bitWidth: 17 + access: read-write + - register: + name: DBIAS_CHANNEL1_SEL + description: needs desc + addressOffset: 64 + size: 32 + fields: + - name: DBIAS_CHANNEL1_CFG + description: needs field desc + bitOffset: 0 + bitWidth: 17 + access: read-write + - register: + name: DBIAS_CHANNEL2_SEL + description: needs desc + addressOffset: 68 + size: 32 + fields: + - name: DBIAS_CHANNEL2_CFG + description: needs field desc + bitOffset: 0 + bitWidth: 17 + access: read-write + - register: + name: DBIAS_CHANNEL3_SEL + description: needs desc + addressOffset: 72 + size: 32 + fields: + - name: DBIAS_CHANNEL3_CFG + description: needs field desc + bitOffset: 0 + bitWidth: 17 + access: read-write + - register: + name: DBIAS_CHANNEL4_SEL + description: needs desc + addressOffset: 76 + size: 32 + fields: + - name: DBIAS_CHANNEL4_CFG + description: needs field desc + bitOffset: 0 + bitWidth: 17 + access: read-write + - register: + name: DBIAS_CMD0 + description: needs desc + addressOffset: 80 + size: 32 + fields: + - name: DBIAS_CMD0 + description: needs field desc + bitOffset: 0 + bitWidth: 17 + access: read-write + - register: + name: DBIAS_CMD1 + description: needs desc + addressOffset: 84 + size: 32 + fields: + - name: DBIAS_CMD1 + description: needs field desc + bitOffset: 0 + bitWidth: 17 + access: read-write + - register: + name: DBIAS_CMD2 + description: needs desc + addressOffset: 88 + size: 32 + fields: + - name: DBIAS_CMD2 + description: needs field desc + bitOffset: 0 + bitWidth: 17 + access: read-write + - register: + name: DBIAS_CMD3 + description: needs desc + addressOffset: 92 + size: 32 + fields: + - name: DBIAS_CMD3 + description: needs field desc + bitOffset: 0 + bitWidth: 17 + access: read-write + - register: + name: DBIAS_CMD4 + description: needs desc + addressOffset: 96 + size: 32 + fields: + - name: DBIAS_CMD4 + description: needs field desc + bitOffset: 0 + bitWidth: 17 + access: read-write + - register: + name: DBIAS_TIMER + description: needs desc + addressOffset: 100 + size: 32 + resetValue: 2147450880 + fields: + - name: TIMER_TARGET + description: needs field desc + bitOffset: 15 + bitWidth: 16 + access: read-write + - name: TIMER_EN + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COMB_PD_SITE0_UNIT0_VT0_CONF1 + description: needs desc + addressOffset: 104 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT0_PD_SITE0_UNIT0 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT0_PD_SITE0_UNIT0 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT0_PD_SITE0_UNIT0 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT0_PD_SITE0_UNIT0 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE0_UNIT1_VT0_CONF1 + description: needs desc + addressOffset: 108 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT0_PD_SITE0_UNIT1 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT0_PD_SITE0_UNIT1 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT0_PD_SITE0_UNIT1 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT0_PD_SITE0_UNIT1 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE0_UNIT2_VT0_CONF1 + description: needs desc + addressOffset: 112 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT0_PD_SITE0_UNIT2 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT0_PD_SITE0_UNIT2 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT0_PD_SITE0_UNIT2 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT0_PD_SITE0_UNIT2 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE0_UNIT3_VT0_CONF1 + description: needs desc + addressOffset: 116 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT0_PD_SITE0_UNIT3 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT0_PD_SITE0_UNIT3 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT0_PD_SITE0_UNIT3 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT0_PD_SITE0_UNIT3 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE0_UNIT0_VT1_CONF1 + description: needs desc + addressOffset: 120 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT1_PD_SITE0_UNIT0 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT1_PD_SITE0_UNIT0 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT1_PD_SITE0_UNIT0 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT1_PD_SITE0_UNIT0 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE0_UNIT1_VT1_CONF1 + description: needs desc + addressOffset: 124 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT1_PD_SITE0_UNIT1 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT1_PD_SITE0_UNIT1 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT1_PD_SITE0_UNIT1 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT1_PD_SITE0_UNIT1 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE0_UNIT2_VT1_CONF1 + description: needs desc + addressOffset: 128 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT1_PD_SITE0_UNIT2 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT1_PD_SITE0_UNIT2 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT1_PD_SITE0_UNIT2 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT1_PD_SITE0_UNIT2 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE0_UNIT3_VT1_CONF1 + description: needs desc + addressOffset: 132 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT1_PD_SITE0_UNIT3 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT1_PD_SITE0_UNIT3 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT1_PD_SITE0_UNIT3 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT1_PD_SITE0_UNIT3 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE0_UNIT0_VT2_CONF1 + description: needs desc + addressOffset: 136 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT2_PD_SITE0_UNIT0 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT2_PD_SITE0_UNIT0 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT2_PD_SITE0_UNIT0 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT2_PD_SITE0_UNIT0 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE0_UNIT1_VT2_CONF1 + description: needs desc + addressOffset: 140 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT2_PD_SITE0_UNIT1 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT2_PD_SITE0_UNIT1 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT2_PD_SITE0_UNIT1 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT2_PD_SITE0_UNIT1 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE0_UNIT2_VT2_CONF1 + description: needs desc + addressOffset: 144 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT2_PD_SITE0_UNIT2 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT2_PD_SITE0_UNIT2 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT2_PD_SITE0_UNIT2 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT2_PD_SITE0_UNIT2 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE0_UNIT3_VT2_CONF1 + description: needs desc + addressOffset: 148 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT2_PD_SITE0_UNIT3 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT2_PD_SITE0_UNIT3 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT2_PD_SITE0_UNIT3 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT2_PD_SITE0_UNIT3 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE1_UNIT0_VT0_CONF1 + description: needs desc + addressOffset: 152 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT0_PD_SITE1_UNIT0 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT0_PD_SITE1_UNIT0 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT0_PD_SITE1_UNIT0 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT0_PD_SITE1_UNIT0 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE1_UNIT1_VT0_CONF1 + description: needs desc + addressOffset: 156 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT0_PD_SITE1_UNIT1 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT0_PD_SITE1_UNIT1 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT0_PD_SITE1_UNIT1 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT0_PD_SITE1_UNIT1 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE1_UNIT2_VT0_CONF1 + description: needs desc + addressOffset: 160 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT0_PD_SITE1_UNIT2 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT0_PD_SITE1_UNIT2 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT0_PD_SITE1_UNIT2 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT0_PD_SITE1_UNIT2 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE1_UNIT3_VT0_CONF1 + description: needs desc + addressOffset: 164 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT0_PD_SITE1_UNIT3 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT0_PD_SITE1_UNIT3 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT0_PD_SITE1_UNIT3 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT0_PD_SITE1_UNIT3 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE1_UNIT0_VT1_CONF1 + description: needs desc + addressOffset: 168 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT1_PD_SITE1_UNIT0 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT1_PD_SITE1_UNIT0 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT1_PD_SITE1_UNIT0 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT1_PD_SITE1_UNIT0 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE1_UNIT1_VT1_CONF1 + description: needs desc + addressOffset: 172 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT1_PD_SITE1_UNIT1 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT1_PD_SITE1_UNIT1 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT1_PD_SITE1_UNIT1 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT1_PD_SITE1_UNIT1 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE1_UNIT2_VT1_CONF1 + description: needs desc + addressOffset: 176 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT1_PD_SITE1_UNIT2 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT1_PD_SITE1_UNIT2 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT1_PD_SITE1_UNIT2 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT1_PD_SITE1_UNIT2 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE1_UNIT3_VT1_CONF1 + description: needs desc + addressOffset: 180 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT1_PD_SITE1_UNIT3 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT1_PD_SITE1_UNIT3 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT1_PD_SITE1_UNIT3 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT1_PD_SITE1_UNIT3 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE1_UNIT0_VT2_CONF1 + description: needs desc + addressOffset: 184 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT2_PD_SITE1_UNIT0 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT2_PD_SITE1_UNIT0 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT2_PD_SITE1_UNIT0 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT2_PD_SITE1_UNIT0 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE1_UNIT1_VT2_CONF1 + description: needs desc + addressOffset: 188 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT2_PD_SITE1_UNIT1 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT2_PD_SITE1_UNIT1 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT2_PD_SITE1_UNIT1 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT2_PD_SITE1_UNIT1 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE1_UNIT2_VT2_CONF1 + description: needs desc + addressOffset: 192 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT2_PD_SITE1_UNIT2 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT2_PD_SITE1_UNIT2 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT2_PD_SITE1_UNIT2 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT2_PD_SITE1_UNIT2 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE1_UNIT3_VT2_CONF1 + description: needs desc + addressOffset: 196 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT2_PD_SITE1_UNIT3 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT2_PD_SITE1_UNIT3 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT2_PD_SITE1_UNIT3 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT2_PD_SITE1_UNIT3 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE2_UNIT0_VT0_CONF1 + description: needs desc + addressOffset: 200 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT0_PD_SITE2_UNIT0 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT0_PD_SITE2_UNIT0 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT0_PD_SITE2_UNIT0 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT0_PD_SITE2_UNIT0 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE2_UNIT1_VT0_CONF1 + description: needs desc + addressOffset: 204 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT0_PD_SITE2_UNIT1 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT0_PD_SITE2_UNIT1 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT0_PD_SITE2_UNIT1 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT0_PD_SITE2_UNIT1 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE2_UNIT2_VT0_CONF1 + description: needs desc + addressOffset: 208 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT0_PD_SITE2_UNIT2 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT0_PD_SITE2_UNIT2 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT0_PD_SITE2_UNIT2 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT0_PD_SITE2_UNIT2 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE2_UNIT3_VT0_CONF1 + description: needs desc + addressOffset: 212 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT0_PD_SITE2_UNIT3 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT0_PD_SITE2_UNIT3 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT0_PD_SITE2_UNIT3 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT0_PD_SITE2_UNIT3 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE2_UNIT0_VT1_CONF1 + description: needs desc + addressOffset: 216 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT1_PD_SITE2_UNIT0 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT1_PD_SITE2_UNIT0 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT1_PD_SITE2_UNIT0 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT1_PD_SITE2_UNIT0 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE2_UNIT1_VT1_CONF1 + description: needs desc + addressOffset: 220 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT1_PD_SITE2_UNIT1 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT1_PD_SITE2_UNIT1 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT1_PD_SITE2_UNIT1 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT1_PD_SITE2_UNIT1 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE2_UNIT2_VT1_CONF1 + description: needs desc + addressOffset: 224 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT1_PD_SITE2_UNIT2 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT1_PD_SITE2_UNIT2 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT1_PD_SITE2_UNIT2 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT1_PD_SITE2_UNIT2 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE2_UNIT3_VT1_CONF1 + description: needs desc + addressOffset: 228 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT1_PD_SITE2_UNIT3 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT1_PD_SITE2_UNIT3 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT1_PD_SITE2_UNIT3 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT1_PD_SITE2_UNIT3 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE2_UNIT0_VT2_CONF1 + description: needs desc + addressOffset: 232 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT2_PD_SITE2_UNIT0 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT2_PD_SITE2_UNIT0 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT2_PD_SITE2_UNIT0 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT2_PD_SITE2_UNIT0 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE2_UNIT1_VT2_CONF1 + description: needs desc + addressOffset: 236 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT2_PD_SITE2_UNIT1 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT2_PD_SITE2_UNIT1 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT2_PD_SITE2_UNIT1 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT2_PD_SITE2_UNIT1 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE2_UNIT2_VT2_CONF1 + description: needs desc + addressOffset: 240 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT2_PD_SITE2_UNIT2 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT2_PD_SITE2_UNIT2 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT2_PD_SITE2_UNIT2 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT2_PD_SITE2_UNIT2 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE2_UNIT3_VT2_CONF1 + description: needs desc + addressOffset: 244 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT2_PD_SITE2_UNIT3 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT2_PD_SITE2_UNIT3 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT2_PD_SITE2_UNIT3 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT2_PD_SITE2_UNIT3 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE3_UNIT0_VT0_CONF1 + description: needs desc + addressOffset: 248 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT0_PD_SITE3_UNIT0 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT0 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT0_PD_SITE3_UNIT0 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT0_PD_SITE3_UNIT0 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT0_PD_SITE3_UNIT0 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE3_UNIT1_VT0_CONF1 + description: needs desc + addressOffset: 252 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT0_PD_SITE3_UNIT1 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT1 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT0_PD_SITE3_UNIT1 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT0_PD_SITE3_UNIT1 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT0_PD_SITE3_UNIT1 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE3_UNIT2_VT0_CONF1 + description: needs desc + addressOffset: 256 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT0_PD_SITE3_UNIT2 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT2 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT0_PD_SITE3_UNIT2 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT0_PD_SITE3_UNIT2 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT0_PD_SITE3_UNIT2 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE3_UNIT3_VT0_CONF1 + description: needs desc + addressOffset: 260 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT0_PD_SITE3_UNIT3 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT0_PD_SITE3_UNIT3 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT0_PD_SITE3_UNIT3 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT0_PD_SITE3_UNIT3 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT0_PD_SITE3_UNIT3 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE3_UNIT0_VT1_CONF1 + description: needs desc + addressOffset: 264 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT1_PD_SITE3_UNIT0 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT0 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT1_PD_SITE3_UNIT0 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT1_PD_SITE3_UNIT0 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT1_PD_SITE3_UNIT0 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE3_UNIT1_VT1_CONF1 + description: needs desc + addressOffset: 268 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT1_PD_SITE3_UNIT1 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT1 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT1_PD_SITE3_UNIT1 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT1_PD_SITE3_UNIT1 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT1_PD_SITE3_UNIT1 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE3_UNIT2_VT1_CONF1 + description: needs desc + addressOffset: 272 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT1_PD_SITE3_UNIT2 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT2 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT1_PD_SITE3_UNIT2 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT1_PD_SITE3_UNIT2 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT1_PD_SITE3_UNIT2 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE3_UNIT3_VT1_CONF1 + description: needs desc + addressOffset: 276 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT1_PD_SITE3_UNIT3 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT1_PD_SITE3_UNIT3 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT1_PD_SITE3_UNIT3 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT1_PD_SITE3_UNIT3 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT1_PD_SITE3_UNIT3 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE3_UNIT0_VT2_CONF1 + description: needs desc + addressOffset: 280 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT2_PD_SITE3_UNIT0 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT0 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT2_PD_SITE3_UNIT0 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT2_PD_SITE3_UNIT0 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT2_PD_SITE3_UNIT0 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE3_UNIT1_VT2_CONF1 + description: needs desc + addressOffset: 284 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT2_PD_SITE3_UNIT1 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT1 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT2_PD_SITE3_UNIT1 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT2_PD_SITE3_UNIT1 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT2_PD_SITE3_UNIT1 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE3_UNIT2_VT2_CONF1 + description: needs desc + addressOffset: 288 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT2_PD_SITE3_UNIT2 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT2 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT2_PD_SITE3_UNIT2 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT2_PD_SITE3_UNIT2 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT2_PD_SITE3_UNIT2 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE3_UNIT3_VT2_CONF1 + description: needs desc + addressOffset: 292 + size: 32 + resetValue: 80 + fields: + - name: MONITOR_EN_VT2_PD_SITE3_UNIT3 + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_ERR_CNT_CLR_VT2_PD_SITE3_UNIT3 + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DELAY_LIMIT_VT2_PD_SITE3_UNIT3 + description: needs field desc + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: DELAY_NUM_O_VT2_PD_SITE3_UNIT3 + description: needs field desc + bitOffset: 23 + bitWidth: 8 + access: read-only + - name: TIMING_ERR_VT2_PD_SITE3_UNIT3 + description: needs field desc + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: COMB_PD_SITE0_UNIT0_VT0_CONF2 + description: needs desc + addressOffset: 296 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT0_PD_SITE0_UNIT0 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE0_UNIT1_VT0_CONF2 + description: needs desc + addressOffset: 300 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT0_PD_SITE0_UNIT1 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE0_UNIT2_VT0_CONF2 + description: needs desc + addressOffset: 304 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT0_PD_SITE0_UNIT2 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE0_UNIT3_VT0_CONF2 + description: needs desc + addressOffset: 308 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT0_PD_SITE0_UNIT3 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE0_UNIT0_VT1_CONF2 + description: needs desc + addressOffset: 312 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT1_PD_SITE0_UNIT0 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE0_UNIT1_VT1_CONF2 + description: needs desc + addressOffset: 316 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT1_PD_SITE0_UNIT1 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE0_UNIT2_VT1_CONF2 + description: needs desc + addressOffset: 320 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT1_PD_SITE0_UNIT2 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE0_UNIT3_VT1_CONF2 + description: needs desc + addressOffset: 324 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT1_PD_SITE0_UNIT3 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE0_UNIT0_VT2_CONF2 + description: needs desc + addressOffset: 328 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT2_PD_SITE0_UNIT0 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE0_UNIT1_VT2_CONF2 + description: needs desc + addressOffset: 332 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT2_PD_SITE0_UNIT1 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE0_UNIT2_VT2_CONF2 + description: needs desc + addressOffset: 336 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT2_PD_SITE0_UNIT2 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE0_UNIT3_VT2_CONF2 + description: needs desc + addressOffset: 340 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT2_PD_SITE0_UNIT3 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE1_UNIT0_VT0_CONF2 + description: needs desc + addressOffset: 344 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT0_PD_SITE1_UNIT0 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE1_UNIT1_VT0_CONF2 + description: needs desc + addressOffset: 348 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT0_PD_SITE1_UNIT1 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE1_UNIT2_VT0_CONF2 + description: needs desc + addressOffset: 352 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT0_PD_SITE1_UNIT2 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE1_UNIT3_VT0_CONF2 + description: needs desc + addressOffset: 356 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT0_PD_SITE1_UNIT3 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE1_UNIT0_VT1_CONF2 + description: needs desc + addressOffset: 360 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT1_PD_SITE1_UNIT0 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE1_UNIT1_VT1_CONF2 + description: needs desc + addressOffset: 364 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT1_PD_SITE1_UNIT1 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE1_UNIT2_VT1_CONF2 + description: needs desc + addressOffset: 368 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT1_PD_SITE1_UNIT2 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE1_UNIT3_VT1_CONF2 + description: needs desc + addressOffset: 372 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT1_PD_SITE1_UNIT3 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE1_UNIT0_VT2_CONF2 + description: needs desc + addressOffset: 376 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT2_PD_SITE1_UNIT0 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE1_UNIT1_VT2_CONF2 + description: needs desc + addressOffset: 380 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT2_PD_SITE1_UNIT1 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE1_UNIT2_VT2_CONF2 + description: needs desc + addressOffset: 384 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT2_PD_SITE1_UNIT2 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE1_UNIT3_VT2_CONF2 + description: needs desc + addressOffset: 388 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT2_PD_SITE1_UNIT3 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE2_UNIT0_VT0_CONF2 + description: needs desc + addressOffset: 392 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT0_PD_SITE2_UNIT0 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE2_UNIT1_VT0_CONF2 + description: needs desc + addressOffset: 396 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT0_PD_SITE2_UNIT1 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE2_UNIT2_VT0_CONF2 + description: needs desc + addressOffset: 400 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT0_PD_SITE2_UNIT2 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE2_UNIT3_VT0_CONF2 + description: needs desc + addressOffset: 404 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT0_PD_SITE2_UNIT3 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE2_UNIT0_VT1_CONF2 + description: needs desc + addressOffset: 408 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT1_PD_SITE2_UNIT0 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE2_UNIT1_VT1_CONF2 + description: needs desc + addressOffset: 412 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT1_PD_SITE2_UNIT1 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE2_UNIT2_VT1_CONF2 + description: needs desc + addressOffset: 416 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT1_PD_SITE2_UNIT2 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE2_UNIT3_VT1_CONF2 + description: needs desc + addressOffset: 420 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT1_PD_SITE2_UNIT3 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE2_UNIT0_VT2_CONF2 + description: needs desc + addressOffset: 424 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT2_PD_SITE2_UNIT0 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE2_UNIT1_VT2_CONF2 + description: needs desc + addressOffset: 428 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT2_PD_SITE2_UNIT1 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE2_UNIT2_VT2_CONF2 + description: needs desc + addressOffset: 432 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT2_PD_SITE2_UNIT2 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE2_UNIT3_VT2_CONF2 + description: needs desc + addressOffset: 436 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT2_PD_SITE2_UNIT3 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE3_UNIT0_VT0_CONF2 + description: needs desc + addressOffset: 440 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT0 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT0_PD_SITE3_UNIT0 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT0 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE3_UNIT1_VT0_CONF2 + description: needs desc + addressOffset: 444 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT1 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT0_PD_SITE3_UNIT1 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT1 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE3_UNIT2_VT0_CONF2 + description: needs desc + addressOffset: 448 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT2 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT0_PD_SITE3_UNIT2 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT2 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE3_UNIT3_VT0_CONF2 + description: needs desc + addressOffset: 452 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT0_PD_SITE3_UNIT3 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT0_PD_SITE3_UNIT3 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT0_PD_SITE3_UNIT3 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE3_UNIT0_VT1_CONF2 + description: needs desc + addressOffset: 456 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT0 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT1_PD_SITE3_UNIT0 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT0 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE3_UNIT1_VT1_CONF2 + description: needs desc + addressOffset: 460 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT1 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT1_PD_SITE3_UNIT1 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT1 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE3_UNIT2_VT1_CONF2 + description: needs desc + addressOffset: 464 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT2 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT1_PD_SITE3_UNIT2 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT2 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE3_UNIT3_VT1_CONF2 + description: needs desc + addressOffset: 468 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT1_PD_SITE3_UNIT3 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT1_PD_SITE3_UNIT3 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT1_PD_SITE3_UNIT3 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE3_UNIT0_VT2_CONF2 + description: needs desc + addressOffset: 472 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT0 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT2_PD_SITE3_UNIT0 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT0 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE3_UNIT1_VT2_CONF2 + description: needs desc + addressOffset: 476 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT1 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT2_PD_SITE3_UNIT1 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT1 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE3_UNIT2_VT2_CONF2 + description: needs desc + addressOffset: 480 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT2 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT2_PD_SITE3_UNIT2 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT2 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: COMB_PD_SITE3_UNIT3_VT2_CONF2 + description: needs desc + addressOffset: 484 + size: 32 + fields: + - name: MONITOR_EDG_MOD_VT2_PD_SITE3_UNIT3 + description: needs field desc + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DELAY_OVF_VT2_PD_SITE3_UNIT3 + description: needs field desc + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TIMING_ERR_CNT_O_VT2_PD_SITE3_UNIT3 + description: needs field desc + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: VALUE_UPDATE + description: needs field desc + addressOffset: 488 + size: 32 + fields: + - name: VALUE_UPDATE + description: needs field desc + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: BYPASS + description: needs field desc + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: version register + addressOffset: 4092 + size: 32 + resetValue: 34677040 + fields: + - name: DATE + description: version register + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: RMT + description: Remote Control + groupName: RMT + baseAddress: 1343045632 + addressBlock: + - offset: 0 + size: 208 + usage: registers + interrupt: + - name: RMT + value: 43 + registers: + - register: + dim: 4 + dimIncrement: 4 + name: TX_CH%sDATA + description: The read and write data register for CHANNEL%s by apb fifo access. + addressOffset: 0 + size: 32 + fields: + - name: CHDATA + description: Read and write data for channel %s via APB FIFO. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + dim: 4 + dimIncrement: 4 + name: RX_CH%sDATA + description: The read and write data register for CHANNEL$n by apb fifo access. + addressOffset: 16 + size: 32 + fields: + - name: CHDATA + description: Read and write data for channel 0 via APB FIFO. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + dim: 4 + dimIncrement: 4 + name: TX_CH%sCONF0 + description: Channel %s configure register 0 + addressOffset: 32 + size: 32 + resetValue: 7406080 + fields: + - name: TX_START_CH0 + description: Set this bit to start sending data on CHANNEL%s. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: MEM_RD_RST_CH0 + description: Set this bit to reset read ram address for CHANNEL%s by accessing transmitter. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: APB_MEM_RST_CH0 + description: Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TX_CONTI_MODE_CH0 + description: Set this bit to restart transmission from the first data to the last data in CHANNEL%s. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MEM_TX_WRAP_EN_CH0 + description: "This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IDLE_OUT_LV_CH0 + description: This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: IDLE_OUT_EN_CH0 + description: This is the output enable-control bit for CHANNEL%s in IDLE state. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_STOP_CH0 + description: Set this bit to stop the transmitter of CHANNEL%s sending data out. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DIV_CNT_CH0 + description: This register is used to configure the divider for clock of CHANNEL%s. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: MEM_SIZE_CH0 + description: This register is used to configure the maximum size of memory allocated to CHANNEL%s. + bitOffset: 16 + bitWidth: 4 + access: read-write + - name: CARRIER_EFF_EN_CH0 + description: "1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CARRIER_EN_CH0 + description: "This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CARRIER_OUT_LV_CH0 + description: "This bit is used to configure the position of carrier wave for CHANNEL%s.1'h0: add carrier wave on low level.1'h1: add carrier wave on high level." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: AFIFO_RST_CH0 + description: Reserved + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: CONF_UPDATE_CH0 + description: synchronization bit for CHANNEL%s + bitOffset: 24 + bitWidth: 1 + access: write-only + - register: + dim: 4 + dimIncrement: 8 + name: RX_CH%sCONF0 + description: Channel %s configure register 0 + addressOffset: 48 + size: 32 + resetValue: 830471938 + fields: + - name: DIV_CNT_CH4 + description: This register is used to configure the divider for clock of CHANNEL%s. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: IDLE_THRES_CH4 + description: "When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished." + bitOffset: 8 + bitWidth: 15 + access: read-write + - name: MEM_SIZE_CH4 + description: This register is used to configure the maximum size of memory allocated to CHANNEL%s. + bitOffset: 24 + bitWidth: 4 + access: read-write + - name: CARRIER_EN_CH4 + description: "This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CARRIER_OUT_LV_CH4 + description: "This bit is used to configure the position of carrier wave for CHANNEL%s.1'h0: add carrier wave on low level.1'h1: add carrier wave on high level." + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + dim: 4 + dimIncrement: 8 + name: RX_CH%sCONF1 + description: Channel %s configure register 1 + addressOffset: 52 + size: 32 + resetValue: 488 + fields: + - name: RX_EN_CH4 + description: Set this bit to enable receiver to receive data on CHANNEL%s. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_WR_RST_CH4 + description: Set this bit to reset write ram address for CHANNEL%s by accessing receiver. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: APB_MEM_RST_CH4 + description: Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: MEM_OWNER_CH4 + description: "This register marks the ownership of CHANNEL%s's ram block.1'h1: Receiver is using the ram. 1'h0: APB bus is using the ram." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_FILTER_EN_CH4 + description: "This is the receive filter's enable bit for CHANNEL%s." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_FILTER_THRES_CH4 + description: Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode). + bitOffset: 5 + bitWidth: 8 + access: read-write + - name: MEM_RX_WRAP_EN_CH4 + description: "This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: AFIFO_RST_CH4 + description: Reserved + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: CONF_UPDATE_CH4 + description: synchronization bit for CHANNEL%s + bitOffset: 15 + bitWidth: 1 + access: write-only + - register: + dim: 4 + dimIncrement: 4 + name: TX_CH%sSTATUS + description: Channel %s status register + addressOffset: 80 + size: 32 + fields: + - name: MEM_RADDR_EX_CH0 + description: This register records the memory address offset when transmitter of CHANNEL%s is using the RAM. + bitOffset: 0 + bitWidth: 10 + access: read-only + - name: APB_MEM_WADDR_CH0 + description: This register records the memory address offset when writes RAM over APB bus. + bitOffset: 11 + bitWidth: 10 + access: read-only + - name: STATE_CH0 + description: This register records the FSM status of CHANNEL%s. + bitOffset: 22 + bitWidth: 3 + access: read-only + - name: MEM_EMPTY_CH0 + description: This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: APB_MEM_WR_ERR_CH0 + description: This status bit will be set if the offset address out of memory size when writes via APB bus. + bitOffset: 26 + bitWidth: 1 + access: read-only + - register: + dim: 4 + dimIncrement: 4 + name: RX_CH%sSTATUS + description: Channel %s status register + addressOffset: 96 + size: 32 + resetValue: 393408 + fields: + - name: MEM_WADDR_EX_CH4 + description: This register records the memory address offset when receiver of CHANNEL%s is using the RAM. + bitOffset: 0 + bitWidth: 10 + access: read-only + - name: APB_MEM_RADDR_CH4 + description: This register records the memory address offset when reads RAM over APB bus. + bitOffset: 11 + bitWidth: 10 + access: read-only + - name: STATE_CH4 + description: This register records the FSM status of CHANNEL%s. + bitOffset: 22 + bitWidth: 3 + access: read-only + - name: MEM_OWNER_ERR_CH4 + description: This status bit will be set when the ownership of memory block is wrong. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: MEM_FULL_CH4 + description: This status bit will be set if the receiver receives more data than the memory size. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: APB_MEM_RD_ERR_CH4 + description: This status bit will be set if the offset address out of memory size when reads via APB bus. + bitOffset: 27 + bitWidth: 1 + access: read-only + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 112 + size: 32 + fields: + - name: CH0_TX_END_INT_RAW + description: The interrupt raw bit for CHANNEL0. Triggered when transmission done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CH1_TX_END_INT_RAW + description: The interrupt raw bit for CHANNEL1. Triggered when transmission done. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CH2_TX_END_INT_RAW + description: The interrupt raw bit for CHANNEL2. Triggered when transmission done. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CH3_TX_END_INT_RAW + description: The interrupt raw bit for CHANNEL3. Triggered when transmission done. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_CH0_ERR_INT_RAW + description: The interrupt raw bit for CHANNEL0. Triggered when error occurs. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TX_CH1_ERR_INT_RAW + description: The interrupt raw bit for CHANNEL1. Triggered when error occurs. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TX_CH2_ERR_INT_RAW + description: The interrupt raw bit for CHANNEL2. Triggered when error occurs. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_CH3_ERR_INT_RAW + description: The interrupt raw bit for CHANNEL3. Triggered when error occurs. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CH0_TX_THR_EVENT_INT_RAW + description: The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than configured value. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CH1_TX_THR_EVENT_INT_RAW + description: The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than configured value. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CH2_TX_THR_EVENT_INT_RAW + description: The interrupt raw bit for CHANNEL2. Triggered when transmitter sent more data than configured value. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CH3_TX_THR_EVENT_INT_RAW + description: The interrupt raw bit for CHANNEL3. Triggered when transmitter sent more data than configured value. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CH0_TX_LOOP_INT_RAW + description: The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the configured threshold value. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CH1_TX_LOOP_INT_RAW + description: The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the configured threshold value. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: CH2_TX_LOOP_INT_RAW + description: The interrupt raw bit for CHANNEL2. Triggered when the loop count reaches the configured threshold value. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CH3_TX_LOOP_INT_RAW + description: The interrupt raw bit for CHANNEL3. Triggered when the loop count reaches the configured threshold value. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CH4_RX_END_INT_RAW + description: The interrupt raw bit for CHANNEL4. Triggered when reception done. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CH5_RX_END_INT_RAW + description: The interrupt raw bit for CHANNEL5. Triggered when reception done. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: CH6_RX_END_INT_RAW + description: The interrupt raw bit for CHANNEL6. Triggered when reception done. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: CH7_RX_END_INT_RAW + description: The interrupt raw bit for CHANNEL7. Triggered when reception done. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RX_CH4_ERR_INT_RAW + description: The interrupt raw bit for CHANNEL4. Triggered when error occurs. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: RX_CH5_ERR_INT_RAW + description: The interrupt raw bit for CHANNEL5. Triggered when error occurs. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: RX_CH6_ERR_INT_RAW + description: The interrupt raw bit for CHANNEL6. Triggered when error occurs. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RX_CH7_ERR_INT_RAW + description: The interrupt raw bit for CHANNEL7. Triggered when error occurs. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: CH4_RX_THR_EVENT_INT_RAW + description: The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: CH5_RX_THR_EVENT_INT_RAW + description: The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than configured value. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: CH6_RX_THR_EVENT_INT_RAW + description: The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than configured value. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CH7_RX_THR_EVENT_INT_RAW + description: The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than configured value. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: TX_CH3_DMA_ACCESS_FAIL_INT_RAW + description: The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: RX_CH7_DMA_ACCESS_FAIL_INT_RAW + description: The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails. + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 116 + size: 32 + fields: + - name: CH0_TX_END_INT_ST + description: The masked interrupt status bit for CH0_TX_END_INT. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CH1_TX_END_INT_ST + description: The masked interrupt status bit for CH1_TX_END_INT. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CH2_TX_END_INT_ST + description: The masked interrupt status bit for CH2_TX_END_INT. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CH3_TX_END_INT_ST + description: The masked interrupt status bit for CH3_TX_END_INT. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TX_CH0_ERR_INT_ST + description: The masked interrupt status bit for CH0_ERR_INT. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TX_CH1_ERR_INT_ST + description: The masked interrupt status bit for CH1_ERR_INT. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: TX_CH2_ERR_INT_ST + description: The masked interrupt status bit for CH2_ERR_INT. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TX_CH3_ERR_INT_ST + description: The masked interrupt status bit for CH3_ERR_INT. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: CH0_TX_THR_EVENT_INT_ST + description: The masked interrupt status bit for CH0_TX_THR_EVENT_INT. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: CH1_TX_THR_EVENT_INT_ST + description: The masked interrupt status bit for CH1_TX_THR_EVENT_INT. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: CH2_TX_THR_EVENT_INT_ST + description: The masked interrupt status bit for CH2_TX_THR_EVENT_INT. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: CH3_TX_THR_EVENT_INT_ST + description: The masked interrupt status bit for CH3_TX_THR_EVENT_INT. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: CH0_TX_LOOP_INT_ST + description: The masked interrupt status bit for CH0_TX_LOOP_INT. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: CH1_TX_LOOP_INT_ST + description: The masked interrupt status bit for CH1_TX_LOOP_INT. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: CH2_TX_LOOP_INT_ST + description: The masked interrupt status bit for CH2_TX_LOOP_INT. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: CH3_TX_LOOP_INT_ST + description: The masked interrupt status bit for CH3_TX_LOOP_INT. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: CH4_RX_END_INT_ST + description: The masked interrupt status bit for CH4_RX_END_INT. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: CH5_RX_END_INT_ST + description: The masked interrupt status bit for CH5_RX_END_INT. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: CH6_RX_END_INT_ST + description: The masked interrupt status bit for CH6_RX_END_INT. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: CH7_RX_END_INT_ST + description: The masked interrupt status bit for CH7_RX_END_INT. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: RX_CH4_ERR_INT_ST + description: The masked interrupt status bit for CH4_ERR_INT. + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: RX_CH5_ERR_INT_ST + description: The masked interrupt status bit for CH5_ERR_INT. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: RX_CH6_ERR_INT_ST + description: The masked interrupt status bit for CH6_ERR_INT. + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: RX_CH7_ERR_INT_ST + description: The masked interrupt status bit for CH7_ERR_INT. + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: CH4_RX_THR_EVENT_INT_ST + description: The masked interrupt status bit for CH4_RX_THR_EVENT_INT. + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: CH5_RX_THR_EVENT_INT_ST + description: The masked interrupt status bit for CH5_RX_THR_EVENT_INT. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: CH6_RX_THR_EVENT_INT_ST + description: The masked interrupt status bit for CH6_RX_THR_EVENT_INT. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: CH7_RX_THR_EVENT_INT_ST + description: The masked interrupt status bit for CH7_RX_THR_EVENT_INT. + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: TX_CH3_DMA_ACCESS_FAIL_INT_ST + description: The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT. + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: RX_CH7_DMA_ACCESS_FAIL_INT_ST + description: The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT. + bitOffset: 29 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 120 + size: 32 + fields: + - name: CH0_TX_END_INT_ENA + description: The interrupt enable bit for CH0_TX_END_INT. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CH1_TX_END_INT_ENA + description: The interrupt enable bit for CH1_TX_END_INT. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CH2_TX_END_INT_ENA + description: The interrupt enable bit for CH2_TX_END_INT. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CH3_TX_END_INT_ENA + description: The interrupt enable bit for CH3_TX_END_INT. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_CH0_ERR_INT_ENA + description: The interrupt enable bit for CH0_ERR_INT. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TX_CH1_ERR_INT_ENA + description: The interrupt enable bit for CH1_ERR_INT. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TX_CH2_ERR_INT_ENA + description: The interrupt enable bit for CH2_ERR_INT. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_CH3_ERR_INT_ENA + description: The interrupt enable bit for CH3_ERR_INT. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CH0_TX_THR_EVENT_INT_ENA + description: The interrupt enable bit for CH0_TX_THR_EVENT_INT. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CH1_TX_THR_EVENT_INT_ENA + description: The interrupt enable bit for CH1_TX_THR_EVENT_INT. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CH2_TX_THR_EVENT_INT_ENA + description: The interrupt enable bit for CH2_TX_THR_EVENT_INT. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CH3_TX_THR_EVENT_INT_ENA + description: The interrupt enable bit for CH3_TX_THR_EVENT_INT. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CH0_TX_LOOP_INT_ENA + description: The interrupt enable bit for CH0_TX_LOOP_INT. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CH1_TX_LOOP_INT_ENA + description: The interrupt enable bit for CH1_TX_LOOP_INT. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: CH2_TX_LOOP_INT_ENA + description: The interrupt enable bit for CH2_TX_LOOP_INT. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CH3_TX_LOOP_INT_ENA + description: The interrupt enable bit for CH3_TX_LOOP_INT. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CH4_RX_END_INT_ENA + description: The interrupt enable bit for CH4_RX_END_INT. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CH5_RX_END_INT_ENA + description: The interrupt enable bit for CH5_RX_END_INT. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: CH6_RX_END_INT_ENA + description: The interrupt enable bit for CH6_RX_END_INT. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: CH7_RX_END_INT_ENA + description: The interrupt enable bit for CH7_RX_END_INT. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: CH4_ERR_INT_ENA + description: The interrupt enable bit for CH4_ERR_INT. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CH5_ERR_INT_ENA + description: The interrupt enable bit for CH5_ERR_INT. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CH6_ERR_INT_ENA + description: The interrupt enable bit for CH6_ERR_INT. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: CH7_ERR_INT_ENA + description: The interrupt enable bit for CH7_ERR_INT. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: CH4_RX_THR_EVENT_INT_ENA + description: The interrupt enable bit for CH4_RX_THR_EVENT_INT. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: CH5_RX_THR_EVENT_INT_ENA + description: The interrupt enable bit for CH5_RX_THR_EVENT_INT. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: CH6_RX_THR_EVENT_INT_ENA + description: The interrupt enable bit for CH6_RX_THR_EVENT_INT. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CH7_RX_THR_EVENT_INT_ENA + description: The interrupt enable bit for CH7_RX_THR_EVENT_INT. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: TX_CH3_DMA_ACCESS_FAIL_INT_ENA + description: The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: RX_CH7_DMA_ACCESS_FAIL_INT_ENA + description: The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT. + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 124 + size: 32 + fields: + - name: CH0_TX_END_INT_CLR + description: Set this bit to clear theCH0_TX_END_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CH1_TX_END_INT_CLR + description: Set this bit to clear theCH1_TX_END_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CH2_TX_END_INT_CLR + description: Set this bit to clear theCH2_TX_END_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CH3_TX_END_INT_CLR + description: Set this bit to clear theCH3_TX_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TX_CH0_ERR_INT_CLR + description: Set this bit to clear theCH0_ERR_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: TX_CH1_ERR_INT_CLR + description: Set this bit to clear theCH1_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TX_CH2_ERR_INT_CLR + description: Set this bit to clear theCH2_ERR_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TX_CH3_ERR_INT_CLR + description: Set this bit to clear theCH3_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: CH0_TX_THR_EVENT_INT_CLR + description: Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: CH1_TX_THR_EVENT_INT_CLR + description: Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: CH2_TX_THR_EVENT_INT_CLR + description: Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: CH3_TX_THR_EVENT_INT_CLR + description: Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: CH0_TX_LOOP_INT_CLR + description: Set this bit to clear theCH0_TX_LOOP_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: CH1_TX_LOOP_INT_CLR + description: Set this bit to clear theCH1_TX_LOOP_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: CH2_TX_LOOP_INT_CLR + description: Set this bit to clear theCH2_TX_LOOP_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: CH3_TX_LOOP_INT_CLR + description: Set this bit to clear theCH3_TX_LOOP_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: CH4_RX_END_INT_CLR + description: Set this bit to clear theCH4_RX_END_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: CH5_RX_END_INT_CLR + description: Set this bit to clear theCH5_RX_END_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: CH6_RX_END_INT_CLR + description: Set this bit to clear theCH6_RX_END_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: CH7_RX_END_INT_CLR + description: Set this bit to clear theCH7_RX_END_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: RX_CH4_ERR_INT_CLR + description: Set this bit to clear theCH4_ERR_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: RX_CH5_ERR_INT_CLR + description: Set this bit to clear theCH5_ERR_INT interrupt. + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: RX_CH6_ERR_INT_CLR + description: Set this bit to clear theCH6_ERR_INT interrupt. + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: RX_CH7_ERR_INT_CLR + description: Set this bit to clear theCH7_ERR_INT interrupt. + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: CH4_RX_THR_EVENT_INT_CLR + description: Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt. + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: CH5_RX_THR_EVENT_INT_CLR + description: Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt. + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: CH6_RX_THR_EVENT_INT_CLR + description: Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt. + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: CH7_RX_THR_EVENT_INT_CLR + description: Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt. + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: TX_CH3_DMA_ACCESS_FAIL_INT_CLR + description: Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt. + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: RX_CH7_DMA_ACCESS_FAIL_INT_CLR + description: Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt. + bitOffset: 29 + bitWidth: 1 + access: write-only + - register: + dim: 4 + dimIncrement: 4 + name: CH%sCARRIER_DUTY + description: Channel %s duty cycle configuration register + addressOffset: 128 + size: 32 + resetValue: 4194368 + fields: + - name: CARRIER_LOW_CH + description: "This register is used to configure carrier wave 's low level clock period for CHANNEL%s." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CARRIER_HIGH_CH + description: "This register is used to configure carrier wave 's high level clock period for CHANNEL%s." + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: CH%s_RX_CARRIER_RM + description: Channel %s carrier remove register + addressOffset: 144 + size: 32 + fields: + - name: CARRIER_LOW_THRES_CH + description: The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CARRIER_HIGH_THRES_CH + description: The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: CH%s_TX_LIM + description: Channel %s Tx event configuration register + addressOffset: 160 + size: 32 + resetValue: 128 + fields: + - name: TX_LIM_CH + description: This register is used to configure the maximum entries that CHANNEL%s can send out. + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: TX_LOOP_NUM_CH + description: This register is used to configure the maximum loop count when tx_conti_mode is valid. + bitOffset: 9 + bitWidth: 10 + access: read-write + - name: TX_LOOP_CNT_EN_CH + description: This register is the enabled bit for loop count. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: LOOP_COUNT_RESET_CH + description: This register is used to reset the loop count when tx_conti_mode is valid. + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: LOOP_STOP_EN_CH + description: This bit is used to enable the loop send stop function after the loop counter counts to loop number for CHANNEL%s. + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: CH%s_RX_LIM + description: Channel %s Rx event configuration register + addressOffset: 176 + size: 32 + resetValue: 128 + fields: + - name: RX_LIM_CH4 + description: This register is used to configure the maximum entries that CHANNEL%s can receive. + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SYS_CONF + description: RMT apb configuration register + addressOffset: 192 + size: 32 + resetValue: 83886096 + fields: + - name: APB_FIFO_MASK + description: "1'h1: access memory directly. 1'h0: access memory by FIFO." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_CLK_FORCE_ON + description: Set this bit to enable the clock for RMT memory. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PD + description: Set this bit to power down RMT memory. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PU + description: "1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SCLK_DIV_NUM + description: the integral part of the fractional divisor + bitOffset: 4 + bitWidth: 8 + access: read-write + - name: SCLK_DIV_A + description: the numerator of the fractional part of the fractional divisor + bitOffset: 12 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_B + description: the denominator of the fractional part of the fractional divisor + bitOffset: 18 + bitWidth: 6 + access: read-write + - name: SCLK_SEL + description: "choose the clock source of rmt_sclk. 1:CLK_80Mhz.2:CLK_8MHz.3:XTAL" + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: SCLK_ACTIVE + description: rmt_sclk switch + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TX_SIM + description: RMT TX synchronous register + addressOffset: 196 + size: 32 + fields: + - name: CH0 + description: Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CH1 + description: Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CH2 + description: Set this bit to enable CHANNEL2 to start sending data synchronously with other enabled channels. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CH3 + description: Set this bit to enable CHANNEL3 to start sending data synchronously with other enabled channels. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: EN + description: This register is used to enable multiple of channels to start sending data synchronously. + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: REF_CNT_RST + description: RMT clock divider reset register + addressOffset: 200 + size: 32 + fields: + - name: TX_REF_CNT_RST_CH0 + description: This register is used to reset the clock divider of CHANNEL0. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TX_REF_CNT_RST_CH1 + description: This register is used to reset the clock divider of CHANNEL1. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TX_REF_CNT_RST_CH2 + description: This register is used to reset the clock divider of CHANNEL2. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TX_REF_CNT_RST_CH3 + description: This register is used to reset the clock divider of CHANNEL3. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: RX_REF_CNT_RST_CH4 + description: This register is used to reset the clock divider of CHANNEL4. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: RX_REF_CNT_RST_CH5 + description: This register is used to reset the clock divider of CHANNEL5. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: RX_REF_CNT_RST_CH6 + description: This register is used to reset the clock divider of CHANNEL6. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: RX_REF_CNT_RST_CH7 + description: This register is used to reset the clock divider of CHANNEL7. + bitOffset: 7 + bitWidth: 1 + access: write-only + - register: + name: DATE + description: RMT version register + addressOffset: 204 + size: 32 + resetValue: 35655953 + fields: + - name: DATE + description: This is the version register. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: RSA + description: RSA (Rivest Shamir Adleman) Accelerator + groupName: RSA + baseAddress: 1342775296 + addressBlock: + - offset: 0 + size: 116 + usage: registers + interrupt: + - name: RSA + value: 68 + registers: + - register: + dim: 4 + dimIncrement: 4 + name: "M_MEM[%s]" + description: Represents M + addressOffset: 0 + size: 32 + - register: + dim: 4 + dimIncrement: 4 + name: "Z_MEM[%s]" + description: Represents Z + addressOffset: 512 + size: 32 + - register: + dim: 4 + dimIncrement: 4 + name: "Y_MEM[%s]" + description: Represents Y + addressOffset: 1024 + size: 32 + - register: + dim: 4 + dimIncrement: 4 + name: "X_MEM[%s]" + description: Represents X + addressOffset: 1536 + size: 32 + - register: + name: M_PRIME + description: Represents M’ + addressOffset: 2048 + size: 32 + fields: + - name: M_PRIME + description: Represents M’ + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: MODE + description: Configures RSA length + addressOffset: 2052 + size: 32 + fields: + - name: MODE + description: Configures the RSA length. + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: QUERY_CLEAN + description: RSA clean register + addressOffset: 2056 + size: 32 + fields: + - name: QUERY_CLEAN + description: "Represents whether or not the RSA memory completes initialization.\n\n0: Not complete\n\n1: Completed" + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: SET_START_MODEXP + description: Starts modular exponentiation + addressOffset: 2060 + size: 32 + fields: + - name: SET_START_MODEXP + description: "Configure whether or not to start the modular exponentiation.\n\n0: No effect\n\n1: Start" + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_START_MODMULT + description: Starts modular multiplication + addressOffset: 2064 + size: 32 + fields: + - name: SET_START_MODMULT + description: "Configure whether or not to start the modular multiplication.\n\n0: No effect\n\n1: Start" + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_START_MULT + description: Starts multiplication + addressOffset: 2068 + size: 32 + fields: + - name: SET_START_MULT + description: "Configure whether or not to start the multiplication.\n\n0: No effect\n\n1: Start" + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: QUERY_IDLE + description: Represents the RSA status + addressOffset: 2072 + size: 32 + fields: + - name: QUERY_IDLE + description: "Represents the RSA status.\n\n0: Busy\n\n1: Idle" + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: Clears RSA interrupt + addressOffset: 2076 + size: 32 + fields: + - name: CLEAR_INTERRUPT + description: Write 1 to clear the RSA interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: CONSTANT_TIME + description: Configures the constant_time option + addressOffset: 2080 + size: 32 + resetValue: 1 + fields: + - name: CONSTANT_TIME + description: "Configures the constant_time option. \n\n0: Acceleration\n\n1: No acceleration (default)" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SEARCH_ENABLE + description: Configures the search option + addressOffset: 2084 + size: 32 + fields: + - name: SEARCH_ENABLE + description: "Configure the search option. \n\n0: No acceleration (default)\n\n1: Acceleration\n\nThis option should be used together with RSA_SEARCH_POS." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SEARCH_POS + description: Configures the search position + addressOffset: 2088 + size: 32 + fields: + - name: SEARCH_POS + description: Configures the starting address to start search. This field should be used together with RSA_SEARCH_ENABLE. The field is only valid when RSA_SEARCH_ENABLE is high. + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: INT_ENA + description: Enables the RSA interrupt + addressOffset: 2092 + size: 32 + fields: + - name: INT_ENA + description: Write 1 to enable the RSA interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 2096 + size: 32 + resetValue: 538969624 + fields: + - name: DATE + description: Version control register. + bitOffset: 0 + bitWidth: 30 + access: read-write + - name: LP_ADC + description: Low-power Analog to Digital Converter + groupName: RTCADC + baseAddress: 1343385600 + addressBlock: + - offset: 0 + size: 128 + usage: registers + interrupt: + - name: LP_ADC + value: 9 + registers: + - register: + name: READER1_CTRL + description: Control the read operation of ADC1. + addressOffset: 0 + size: 32 + resetValue: 537133058 + fields: + - name: SAR1_CLK_DIV + description: Clock divider. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SAR1_CLK_GATED + description: N/A + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SAR1_SAMPLE_NUM + description: N/A + bitOffset: 19 + bitWidth: 8 + access: read-write + - name: SAR1_DATA_INV + description: Invert SAR ADC1 data. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SAR1_INT_EN + description: Enable saradc1 to send out interrupt. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SAR1_EN_PAD_FORCE_ENABLE + description: "Force enable adc en_pad to analog circuit 2'b11: force enable ." + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: READER1_STATUS + description: N/A + addressOffset: 4 + size: 32 + resetValue: 536870912 + fields: + - name: SAR1_READER_STATUS + description: N/A + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: MEAS1_CTRL1 + description: N/A + addressOffset: 8 + size: 32 + fields: + - name: FORCE_XPD_AMP + description: N/A + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: AMP_RST_FB_FORCE + description: N/A + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: AMP_SHORT_REF_FORCE + description: N/A + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: AMP_SHORT_REF_GND_FORCE + description: N/A + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: MEAS1_CTRL2 + description: ADC1 configuration registers. + addressOffset: 12 + size: 32 + fields: + - name: MEAS1_DATA_SAR + description: SAR ADC1 data. + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: MEAS1_DONE_SAR + description: SAR ADC1 conversion done indication. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: MEAS1_START_SAR + description: SAR ADC1 controller (in RTC) starts conversion. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MEAS1_START_FORCE + description: "1: SAR ADC1 controller (in RTC) is started by SW." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SAR1_EN_PAD + description: SAR ADC1 pad enable bitmap. + bitOffset: 19 + bitWidth: 12 + access: read-write + - name: SAR1_EN_PAD_FORCE + description: "1: SAR ADC1 pad enable bitmap is controlled by SW." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: MEAS1_MUX + description: SAR ADC1 MUX register. + addressOffset: 16 + size: 32 + fields: + - name: SAR1_DIG_FORCE + description: "1: SAR ADC1 controlled by DIG ADC1 CTRL." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: ATTEN1 + description: ADC1 attenuation registers. + addressOffset: 20 + size: 32 + resetValue: 4294967295 + fields: + - name: SAR1_ATTEN + description: 2-bit attenuation for each pad. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: AMP_CTRL1 + description: N/A + addressOffset: 24 + size: 32 + resetValue: 655370 + fields: + - name: SAR_AMP_WAIT1 + description: N/A + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SAR_AMP_WAIT2 + description: N/A + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: AMP_CTRL2 + description: N/A + addressOffset: 28 + size: 32 + resetValue: 655360 + fields: + - name: SAR1_DAC_XPD_FSM_IDLE + description: N/A + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: XPD_SAR_AMP_FSM_IDLE + description: N/A + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AMP_RST_FB_FSM_IDLE + description: N/A + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: AMP_SHORT_REF_FSM_IDLE + description: N/A + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: AMP_SHORT_REF_GND_FSM_IDLE + description: N/A + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: XPD_SAR_FSM_IDLE + description: N/A + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SAR_RSTB_FSM_IDLE + description: N/A + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SAR_AMP_WAIT3 + description: N/A + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: AMP_CTRL3 + description: N/A + addressOffset: 32 + size: 32 + resetValue: 7551219 + fields: + - name: SAR1_DAC_XPD_FSM + description: N/A + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: XPD_SAR_AMP_FSM + description: N/A + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: AMP_RST_FB_FSM + description: N/A + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: AMP_SHORT_REF_FSM + description: N/A + bitOffset: 12 + bitWidth: 4 + access: read-write + - name: AMP_SHORT_REF_GND_FSM + description: N/A + bitOffset: 16 + bitWidth: 4 + access: read-write + - name: XPD_SAR_FSM + description: N/A + bitOffset: 20 + bitWidth: 4 + access: read-write + - name: SAR_RSTB_FSM + description: N/A + bitOffset: 24 + bitWidth: 4 + access: read-write + - register: + name: READER2_CTRL + description: Control the read operation of ADC2. + addressOffset: 36 + size: 32 + resetValue: 1074069506 + fields: + - name: SAR2_CLK_DIV + description: Clock divider. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SAR2_WAIT_ARB_CYCLE + description: Wait arbit stable after sar_done. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: SAR2_CLK_GATED + description: N/A + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SAR2_SAMPLE_NUM + description: N/A + bitOffset: 19 + bitWidth: 8 + access: read-write + - name: SAR2_EN_PAD_FORCE_ENABLE + description: "Force enable adc en_pad to analog circuit 2'b11: force enable ." + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: SAR2_DATA_INV + description: Invert SAR ADC2 data. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SAR2_INT_EN + description: Enable saradc2 to send out interrupt. + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: READER2_STATUS + description: N/A + addressOffset: 40 + size: 32 + fields: + - name: SAR2_READER_STATUS + description: N/A + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: MEAS2_CTRL1 + description: ADC2 configuration registers. + addressOffset: 44 + size: 32 + resetValue: 117572096 + fields: + - name: SAR2_CNTL_STATE + description: saradc2_cntl_fsm. + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: SAR2_PWDET_CAL_EN + description: RTC control pwdet enable. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SAR2_PKDET_CAL_EN + description: RTC control pkdet enable. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SAR2_EN_TEST + description: SAR2_EN_TEST. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SAR2_RSTB_FORCE + description: N/A + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: SAR2_STANDBY_WAIT + description: N/A + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SAR2_RSTB_WAIT + description: N/A + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SAR2_XPD_WAIT + description: N/A + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: MEAS2_CTRL2 + description: ADC2 configuration registers. + addressOffset: 48 + size: 32 + fields: + - name: MEAS2_DATA_SAR + description: SAR ADC2 data. + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: MEAS2_DONE_SAR + description: SAR ADC2 conversion done indication. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: MEAS2_START_SAR + description: SAR ADC2 controller (in RTC) starts conversion. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MEAS2_START_FORCE + description: "1: SAR ADC2 controller (in RTC) is started by SW." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SAR2_EN_PAD + description: SAR ADC2 pad enable bitmap. + bitOffset: 19 + bitWidth: 12 + access: read-write + - name: SAR2_EN_PAD_FORCE + description: "1: SAR ADC2 pad enable bitmap is controlled by SW." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: MEAS2_MUX + description: SAR ADC2 MUX register. + addressOffset: 52 + size: 32 + fields: + - name: SAR2_PWDET_CCT + description: SAR2_PWDET_CCT. + bitOffset: 28 + bitWidth: 3 + access: read-write + - name: SAR2_RTC_FORCE + description: "In sleep, force to use rtc to control ADC." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: ATTEN2 + description: ADC1 attenuation registers. + addressOffset: 56 + size: 32 + resetValue: 4294967295 + fields: + - name: SAR2_ATTEN + description: 2-bit attenuation for each pad. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FORCE_WPD_SAR + description: "In sleep, force to use rtc to control ADC" + addressOffset: 60 + size: 32 + fields: + - name: FORCE_XPD_SAR1 + description: "2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware control." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: FORCE_XPD_SAR2 + description: "2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware control." + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: MEAS_STATUS + description: N/A + addressOffset: 64 + size: 32 + fields: + - name: SARADC_MEAS_STATUS + description: N/A + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: REG_CLKEN + description: N/A + addressOffset: 68 + size: 32 + fields: + - name: CLK_EN + description: N/A + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: COCPU_INT_RAW + description: Interrupt raw registers. + addressOffset: 72 + size: 32 + fields: + - name: COCPU_SARADC1_INT_RAW + description: "ADC1 Conversion is done, int raw." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: COCPU_SARADC2_INT_RAW + description: "ADC2 Conversion is done, int raw." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: COCPU_SARADC1_ERROR_INT_RAW + description: "An errro occurs from ADC1, int raw." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: COCPU_SARADC2_ERROR_INT_RAW + description: "An errro occurs from ADC2, int raw." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: COCPU_SARADC1_WAKE_INT_RAW + description: "A wakeup event is triggered from ADC1, int raw." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: COCPU_SARADC2_WAKE_INT_RAW + description: "A wakeup event is triggered from ADC2, int raw." + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: INT_ENA + description: Interrupt enable registers. + addressOffset: 76 + size: 32 + fields: + - name: COCPU_SARADC1_INT_ENA + description: "ADC1 Conversion is done, int enable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: COCPU_SARADC2_INT_ENA + description: "ADC2 Conversion is done, int enable." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: COCPU_SARADC1_ERROR_INT_ENA + description: "An errro occurs from ADC1, int enable." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: COCPU_SARADC2_ERROR_INT_ENA + description: "An errro occurs from ADC2, int enable." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: COCPU_SARADC1_WAKE_INT_ENA + description: "A wakeup event is triggered from ADC1, int enable." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: COCPU_SARADC2_WAKE_INT_ENA + description: "A wakeup event is triggered from ADC2, int enable." + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Interrupt status registers. + addressOffset: 80 + size: 32 + fields: + - name: COCPU_SARADC1_INT_ST + description: "ADC1 Conversion is done, int status." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: COCPU_SARADC2_INT_ST + description: "ADC2 Conversion is done, int status." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: COCPU_SARADC1_ERROR_INT_ST + description: "An errro occurs from ADC1, int status." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: COCPU_SARADC2_ERROR_INT_ST + description: "An errro occurs from ADC2, int status." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: COCPU_SARADC1_WAKE_INT_ST + description: "A wakeup event is triggered from ADC1, int status." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: COCPU_SARADC2_WAKE_INT_ST + description: "A wakeup event is triggered from ADC2, int status." + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: Interrupt clear registers. + addressOffset: 84 + size: 32 + fields: + - name: COCPU_SARADC1_INT_CLR + description: "ADC1 Conversion is done, int clear." + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: COCPU_SARADC2_INT_CLR + description: "ADC2 Conversion is done, int clear." + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: COCPU_SARADC1_ERROR_INT_CLR + description: "An errro occurs from ADC1, int clear." + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: COCPU_SARADC2_ERROR_INT_CLR + description: "An errro occurs from ADC2, int clear." + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: COCPU_SARADC1_WAKE_INT_CLR + description: "A wakeup event is triggered from ADC1, int clear." + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: COCPU_SARADC2_WAKE_INT_CLR + description: "A wakeup event is triggered from ADC2, int clear." + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA_W1TS + description: Interrupt enable assert registers. + addressOffset: 88 + size: 32 + fields: + - name: COCPU_SARADC1_INT_ENA_W1TS + description: "ADC1 Conversion is done, write 1 to assert int enable." + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: COCPU_SARADC2_INT_ENA_W1TS + description: "ADC2 Conversion is done, write 1 to assert int enable." + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: COCPU_SARADC1_ERROR_INT_ENA_W1TS + description: "An errro occurs from ADC1, write 1 to assert int enable." + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: COCPU_SARADC2_ERROR_INT_ENA_W1TS + description: "An errro occurs from ADC2, write 1 to assert int enable." + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: COCPU_SARADC1_WAKE_INT_ENA_W1TS + description: "A wakeup event is triggered from ADC1, write 1 to assert int enable." + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: COCPU_SARADC2_WAKE_INT_ENA_W1TS + description: "A wakeup event is triggered from ADC2, write 1 to assert int enable." + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA_W1TC + description: Interrupt enable deassert registers. + addressOffset: 92 + size: 32 + fields: + - name: COCPU_SARADC1_INT_ENA_W1TC + description: "ADC1 Conversion is done, write 1 to deassert int enable." + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: COCPU_SARADC2_INT_ENA_W1TC + description: "ADC2 Conversion is done, write 1 to deassert int enable." + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: COCPU_SARADC1_ERROR_INT_ENA_W1TC + description: "An errro occurs from ADC1, write 1 to deassert int enable." + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: COCPU_SARADC2_ERROR_INT_ENA_W1TC + description: "An errro occurs from ADC2, write 1 to deassert int enable." + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: COCPU_SARADC1_WAKE_INT_ENA_W1TC + description: "A wakeup event is triggered from ADC1, write 1 to deassert int enable." + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: COCPU_SARADC2_WAKE_INT_ENA_W1TC + description: "A wakeup event is triggered from ADC2, write 1 to deassert int enable." + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: WAKEUP1 + description: ADC1 wakeup configuration registers. + addressOffset: 96 + size: 32 + resetValue: 67092480 + fields: + - name: SAR1_WAKEUP_TH_LOW + description: Lower threshold. + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: SAR1_WAKEUP_TH_HIGH + description: Upper threshold. + bitOffset: 14 + bitWidth: 12 + access: read-write + - name: SAR1_WAKEUP_OVER_UPPER_TH + description: Indicates that this wakeup event arose from exceeding upper threshold. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: SAR1_WAKEUP_EN + description: Wakeup function enable. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SAR1_WAKEUP_MODE + description: "0:absolute value comparison mode. 1: relative value comparison mode." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: WAKEUP2 + description: ADC2 wakeup configuration registers. + addressOffset: 100 + size: 32 + resetValue: 67092480 + fields: + - name: SAR2_WAKEUP_TH_LOW + description: Lower threshold. + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: SAR2_WAKEUP_TH_HIGH + description: Upper threshold. + bitOffset: 14 + bitWidth: 12 + access: read-write + - name: SAR2_WAKEUP_OVER_UPPER_TH + description: Indicates that this wakeup event arose from exceeding upper threshold. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: SAR2_WAKEUP_EN + description: Wakeup function enable. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SAR2_WAKEUP_MODE + description: "0:absolute value comparison mode. 1: relative value comparison mode." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: WAKEUP_SEL + description: Wakeup source select register. + addressOffset: 104 + size: 32 + fields: + - name: SAR_WAKEUP_SEL + description: "0: ADC1. 1: ADC2." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SAR1_HW_WAKEUP + description: Hardware automatic sampling registers for wakeup function. + addressOffset: 108 + size: 32 + resetValue: 200 + fields: + - name: ADC1_HW_READ_EN_I + description: Enable hardware automatic sampling. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ADC1_HW_READ_RATE_I + description: Hardware automatic sampling rate. + bitOffset: 1 + bitWidth: 16 + access: read-write + - register: + name: SAR2_HW_WAKEUP + description: Hardware automatic sampling registers for wakeup function. + addressOffset: 112 + size: 32 + resetValue: 200 + fields: + - name: ADC2_HW_READ_EN_I + description: Enable hardware automatic sampling. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ADC2_HW_READ_RATE_I + description: Hardware automatic sampling rate. + bitOffset: 1 + bitWidth: 16 + access: read-write + - register: + name: RND_ECO_LOW + description: N/A + addressOffset: 116 + size: 32 + fields: + - name: RND_ECO_LOW + description: N/A + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RND_ECO_HIGH + description: N/A + addressOffset: 120 + size: 32 + resetValue: 4294967295 + fields: + - name: RND_ECO_HIGH + description: N/A + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RND_ECO_CS + description: N/A + addressOffset: 124 + size: 32 + fields: + - name: RND_ECO_EN + description: N/A + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RND_ECO_RESULT + description: N/A + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: LP_TIMER + description: Low-power Timer + groupName: RTC_TIMER + baseAddress: 1343299584 + addressBlock: + - offset: 0 + size: 76 + usage: registers + interrupt: + - name: LP_TIMER0 + value: 2 + - name: LP_TIMER1 + value: 3 + registers: + - register: + name: TAR0_LOW + description: need_des + addressOffset: 0 + size: 32 + fields: + - name: MAIN_TIMER_TAR_LOW0 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TAR0_HIGH + description: need_des + addressOffset: 4 + size: 32 + fields: + - name: MAIN_TIMER_TAR_HIGH0 + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MAIN_TIMER_TAR_EN0 + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: TAR1_LOW + description: need_des + addressOffset: 8 + size: 32 + fields: + - name: MAIN_TIMER_TAR_LOW1 + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TAR1_HIGH + description: need_des + addressOffset: 12 + size: 32 + fields: + - name: MAIN_TIMER_TAR_HIGH1 + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MAIN_TIMER_TAR_EN1 + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: UPDATE + description: need_des + addressOffset: 16 + size: 32 + fields: + - name: MAIN_TIMER_UPDATE + description: need_des + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: MAIN_TIMER_XTAL_OFF + description: need_des + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: MAIN_TIMER_SYS_STALL + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: MAIN_TIMER_SYS_RST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: MAIN_BUF0_LOW + description: need_des + addressOffset: 20 + size: 32 + fields: + - name: MAIN_TIMER_BUF0_LOW + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: MAIN_BUF0_HIGH + description: need_des + addressOffset: 24 + size: 32 + fields: + - name: MAIN_TIMER_BUF0_HIGH + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: MAIN_BUF1_LOW + description: need_des + addressOffset: 28 + size: 32 + fields: + - name: MAIN_TIMER_BUF1_LOW + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: MAIN_BUF1_HIGH + description: need_des + addressOffset: 32 + size: 32 + fields: + - name: MAIN_TIMER_BUF1_HIGH + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: MAIN_OVERFLOW + description: need_des + addressOffset: 36 + size: 32 + fields: + - name: MAIN_TIMER_ALARM_LOAD + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: INT_RAW + description: need_des + addressOffset: 40 + size: 32 + fields: + - name: OVERFLOW_RAW + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SOC_WAKEUP_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: need_des + addressOffset: 44 + size: 32 + fields: + - name: OVERFLOW_ST + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: SOC_WAKEUP_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: need_des + addressOffset: 48 + size: 32 + fields: + - name: OVERFLOW_ENA + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SOC_WAKEUP_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: need_des + addressOffset: 52 + size: 32 + fields: + - name: OVERFLOW_CLR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: SOC_WAKEUP_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: LP_INT_RAW + description: need_des + addressOffset: 56 + size: 32 + fields: + - name: MAIN_TIMER_OVERFLOW_LP_INT_RAW + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: MAIN_TIMER_LP_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_INT_ST + description: need_des + addressOffset: 60 + size: 32 + fields: + - name: MAIN_TIMER_OVERFLOW_LP_INT_ST + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: MAIN_TIMER_LP_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: LP_INT_ENA + description: need_des + addressOffset: 64 + size: 32 + fields: + - name: MAIN_TIMER_OVERFLOW_LP_INT_ENA + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: MAIN_TIMER_LP_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LP_INT_CLR + description: need_des + addressOffset: 68 + size: 32 + fields: + - name: MAIN_TIMER_OVERFLOW_LP_INT_CLR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: MAIN_TIMER_LP_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 34672976 + fields: + - name: DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: LP_TOUCH + description: LP_TOUCH Peripheral + groupName: RTC_TOUCH + baseAddress: 1343389696 + addressBlock: + - offset: 0 + size: 100 + usage: registers + interrupt: + - name: LP_TOUCH + value: 14 + registers: + - register: + name: INT_RAW + description: need_des + addressOffset: 0 + size: 32 + fields: + - name: SCAN_DONE_INT_RAW + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DONE_INT_RAW + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ACTIVE_INT_RAW + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INACTIVE_INT_RAW + description: need_des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TIMEOUT_INT_RAW + description: need_des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: APPROACH_LOOP_DONE_INT_RAW + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: need_des + addressOffset: 4 + size: 32 + fields: + - name: SCAN_DONE_INT_ST + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DONE_INT_ST + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ACTIVE_INT_ST + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: INACTIVE_INT_ST + description: need_des + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TIMEOUT_INT_ST + description: need_des + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: APPROACH_LOOP_DONE_INT_ST + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: need_des + addressOffset: 8 + size: 32 + fields: + - name: SCAN_DONE_INT_ENA + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DONE_INT_ENA + description: need_des + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ACTIVE_INT_ENA + description: need_des + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INACTIVE_INT_ENA + description: need_des + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TIMEOUT_INT_ENA + description: need_des + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: APPROACH_LOOP_DONE_INT_ENA + description: need_des + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: need_des + addressOffset: 12 + size: 32 + fields: + - name: SCAN_DONE_INT_CLR + description: need_des + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: DONE_INT_CLR + description: need_des + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: ACTIVE_INT_CLR + description: need_des + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: INACTIVE_INT_CLR + description: need_des + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TIMEOUT_INT_CLR + description: need_des + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: APPROACH_LOOP_DONE_INT_CLR + description: need_des + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: CHN_STATUS + description: need_des + addressOffset: 16 + size: 32 + fields: + - name: PAD_ACTIVE + description: need_des + bitOffset: 0 + bitWidth: 15 + access: read-only + - name: MEAS_DONE + description: need_des + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SCAN_CURR + description: need_des + bitOffset: 16 + bitWidth: 4 + access: read-only + - register: + name: STATUS_0 + description: need_des + addressOffset: 20 + size: 32 + fields: + - name: PAD0_DATA + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: PAD0_DEBOUNCE_CNT + description: need_des + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: PAD0_NEG_NOISE_CNT + description: need_des + bitOffset: 19 + bitWidth: 4 + access: read-only + - register: + name: STATUS_1 + description: need_des + addressOffset: 24 + size: 32 + fields: + - name: PAD1_DATA + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: PAD1_DEBOUNCE_CNT + description: need_des + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: PAD1_NEG_NOISE_CNT + description: need_des + bitOffset: 19 + bitWidth: 4 + access: read-only + - register: + name: STATUS_2 + description: need_des + addressOffset: 28 + size: 32 + fields: + - name: PAD2_DATA + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: PAD2_DEBOUNCE_CNT + description: need_des + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: PAD2_NEG_NOISE_CNT + description: need_des + bitOffset: 19 + bitWidth: 4 + access: read-only + - register: + name: STATUS_3 + description: need_des + addressOffset: 32 + size: 32 + fields: + - name: PAD3_DATA + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: PAD3_DEBOUNCE_CNT + description: need_des + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: PAD3_NEG_NOISE_CNT + description: need_des + bitOffset: 19 + bitWidth: 4 + access: read-only + - register: + name: STATUS_4 + description: need_des + addressOffset: 36 + size: 32 + fields: + - name: PAD4_DATA + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: PAD4_DEBOUNCE_CNT + description: need_des + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: PAD4_NEG_NOISE_CNT + description: need_des + bitOffset: 19 + bitWidth: 4 + access: read-only + - register: + name: STATUS_5 + description: need_des + addressOffset: 40 + size: 32 + fields: + - name: PAD5_DATA + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: PAD5_DEBOUNCE_CNT + description: need_des + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: PAD5_NEG_NOISE_CNT + description: need_des + bitOffset: 19 + bitWidth: 4 + access: read-only + - register: + name: STATUS_6 + description: need_des + addressOffset: 44 + size: 32 + fields: + - name: PAD6_DATA + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: PAD6_DEBOUNCE_CNT + description: need_des + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: PAD6_NEG_NOISE_CNT + description: need_des + bitOffset: 19 + bitWidth: 4 + access: read-only + - register: + name: STATUS_7 + description: need_des + addressOffset: 48 + size: 32 + fields: + - name: PAD7_DATA + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: PAD7_DEBOUNCE_CNT + description: need_des + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: PAD7_NEG_NOISE_CNT + description: need_des + bitOffset: 19 + bitWidth: 4 + access: read-only + - register: + name: STATUS_8 + description: need_des + addressOffset: 52 + size: 32 + fields: + - name: PAD8_DATA + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: PAD8_DEBOUNCE_CNT + description: need_des + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: PAD8_NEG_NOISE_CNT + description: need_des + bitOffset: 19 + bitWidth: 4 + access: read-only + - register: + name: STATUS_9 + description: need_des + addressOffset: 56 + size: 32 + fields: + - name: PAD9_DATA + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: PAD9_DEBOUNCE_CNT + description: need_des + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: PAD9_NEG_NOISE_CNT + description: need_des + bitOffset: 19 + bitWidth: 4 + access: read-only + - register: + name: STATUS_10 + description: need_des + addressOffset: 60 + size: 32 + fields: + - name: PAD10_DATA + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: PAD10_DEBOUNCE_CNT + description: need_des + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: PAD10_NEG_NOISE_CNT + description: need_des + bitOffset: 19 + bitWidth: 4 + access: read-only + - register: + name: STATUS_11 + description: need_des + addressOffset: 64 + size: 32 + fields: + - name: PAD11_DATA + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: PAD11_DEBOUNCE_CNT + description: need_des + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: PAD11_NEG_NOISE_CNT + description: need_des + bitOffset: 19 + bitWidth: 4 + access: read-only + - register: + name: STATUS_12 + description: need_des + addressOffset: 68 + size: 32 + fields: + - name: PAD12_DATA + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: PAD12_DEBOUNCE_CNT + description: need_des + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: PAD12_NEG_NOISE_CNT + description: need_des + bitOffset: 19 + bitWidth: 4 + access: read-only + - register: + name: STATUS_13 + description: need_des + addressOffset: 72 + size: 32 + fields: + - name: PAD13_DATA + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: PAD13_DEBOUNCE_CNT + description: need_des + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: PAD13_NEG_NOISE_CNT + description: need_des + bitOffset: 19 + bitWidth: 4 + access: read-only + - register: + name: STATUS_14 + description: need_des + addressOffset: 76 + size: 32 + fields: + - name: PAD14_DATA + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: PAD14_DEBOUNCE_CNT + description: need_des + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: PAD14_NEG_NOISE_CNT + description: need_des + bitOffset: 19 + bitWidth: 4 + access: read-only + - register: + name: STATUS_15 + description: need_des + addressOffset: 80 + size: 32 + fields: + - name: SLP_DATA + description: need_des + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: SLP_DEBOUNCE_CNT + description: need_des + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: SLP_NEG_NOISE_CNT + description: need_des + bitOffset: 19 + bitWidth: 4 + access: read-only + - register: + name: STATUS_16 + description: need_des + addressOffset: 84 + size: 32 + fields: + - name: APPROACH_PAD2_CNT + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: APPROACH_PAD1_CNT + description: need_des + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: APPROACH_PAD0_CNT + description: need_des + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: SLP_APPROACH_CNT + description: need_des + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: STATUS_17 + description: need_des + addressOffset: 88 + size: 32 + fields: + - name: DCAP_LPF + description: Reserved + bitOffset: 0 + bitWidth: 7 + access: read-only + - name: DRES_LPF + description: need_des + bitOffset: 7 + bitWidth: 2 + access: read-only + - name: DRV_LS + description: need_des + bitOffset: 9 + bitWidth: 4 + access: read-only + - name: DRV_HS + description: need_des + bitOffset: 13 + bitWidth: 5 + access: read-only + - name: DBIAS + description: need_des + bitOffset: 18 + bitWidth: 5 + access: read-only + - name: RTC_FREQ_SCAN_CNT + description: need_des + bitOffset: 23 + bitWidth: 2 + access: read-only + - register: + name: CHN_TMP_STATUS + description: need_des + addressOffset: 92 + size: 32 + fields: + - name: PAD_INACTIVE_STATUS + description: need_des + bitOffset: 0 + bitWidth: 15 + access: read-only + - name: PAD_ACTIVE_STATUS + description: need_des + bitOffset: 15 + bitWidth: 15 + access: read-only + - register: + name: DATE + description: need_des + addressOffset: 256 + size: 32 + resetValue: 2294548 + fields: + - name: RTC_DATE + description: need_des + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: RTC_CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: LP_WDT + description: Low-power Watchdog Timer + groupName: RTC_WDT + baseAddress: 1343315968 + addressBlock: + - offset: 0 + size: 56 + usage: registers + interrupt: + - name: LP_WDT + value: 1 + registers: + - register: + name: CONFIG0 + description: need_des + addressOffset: 0 + size: 32 + resetValue: 78356 + fields: + - name: WDT_CHIP_RESET_WIDTH + description: need_des + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: WDT_CHIP_RESET_EN + description: need_des + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: WDT_PAUSE_IN_SLP + description: need_des + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: WDT_APPCPU_RESET_EN + description: need_des + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: WDT_PROCPU_RESET_EN + description: need_des + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: WDT_FLASHBOOT_MOD_EN + description: need_des + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: WDT_SYS_RESET_LENGTH + description: need_des + bitOffset: 13 + bitWidth: 3 + access: read-write + - name: WDT_CPU_RESET_LENGTH + description: need_des + bitOffset: 16 + bitWidth: 3 + access: read-write + - name: WDT_STG3 + description: need_des + bitOffset: 19 + bitWidth: 3 + access: read-write + - name: WDT_STG2 + description: need_des + bitOffset: 22 + bitWidth: 3 + access: read-write + - name: WDT_STG1 + description: need_des + bitOffset: 25 + bitWidth: 3 + access: read-write + - name: WDT_STG0 + description: need_des + bitOffset: 28 + bitWidth: 3 + access: read-write + - name: WDT_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CONFIG1 + description: need_des + addressOffset: 4 + size: 32 + resetValue: 200000 + fields: + - name: WDT_STG0_HOLD + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CONFIG2 + description: need_des + addressOffset: 8 + size: 32 + resetValue: 80000 + fields: + - name: WDT_STG1_HOLD + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CONFIG3 + description: need_des + addressOffset: 12 + size: 32 + resetValue: 4095 + fields: + - name: WDT_STG2_HOLD + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CONFIG4 + description: need_des + addressOffset: 16 + size: 32 + resetValue: 4095 + fields: + - name: WDT_STG3_HOLD + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FEED + description: need_des + addressOffset: 20 + size: 32 + fields: + - name: FEED + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: WPROTECT + description: need_des + addressOffset: 24 + size: 32 + fields: + - name: WDT_WKEY + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SWD_CONFIG + description: need_des + addressOffset: 28 + size: 32 + resetValue: 314572800 + fields: + - name: SWD_RESET_FLAG + description: need_des + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SWD_AUTO_FEED_EN + description: need_des + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SWD_RST_FLAG_CLR + description: need_des + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: SWD_SIGNAL_WIDTH + description: need_des + bitOffset: 20 + bitWidth: 10 + access: read-write + - name: SWD_DISABLE + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SWD_FEED + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SWD_WPROTECT + description: need_des + addressOffset: 32 + size: 32 + fields: + - name: SWD_WKEY + description: need_des + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: INT_RAW + description: need_des + addressOffset: 36 + size: 32 + fields: + - name: SUPER_WDT_INT_RAW + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_WDT_INT_RAW + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: need_des + addressOffset: 40 + size: 32 + fields: + - name: SUPER_WDT_INT_ST + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: LP_WDT_INT_ST + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: need_des + addressOffset: 44 + size: 32 + fields: + - name: SUPER_WDT_INT_ENA + description: need_des + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LP_WDT_INT_ENA + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: need_des + addressOffset: 48 + size: 32 + fields: + - name: SUPER_WDT_INT_CLR + description: need_des + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: LP_WDT_INT_CLR + description: need_des + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: DATE + description: need_des + addressOffset: 1020 + size: 32 + resetValue: 34676864 + fields: + - name: LP_WDT_DATE + description: need_des + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: CLK_EN + description: need_des + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: SDHOST + description: SD/MMC Host Controller + groupName: SDHOST + baseAddress: 1342713856 + addressBlock: + - offset: 0 + size: 176 + usage: registers + registers: + - register: + name: CTRL + description: Control register + addressOffset: 0 + size: 32 + fields: + - name: CONTROLLER_RESET + description: "To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FIFO_RESET + description: "To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation.\nNote: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DMA_RESET + description: "To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_ENABLE + description: "Global interrupt enable/disable bit. 0: Disable; 1: Enable." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: READ_WAIT + description: For sending read-wait to SDIO cards. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SEND_IRQ_RESPONSE + description: "Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: ABORT_READ_DATA + description: "After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SEND_CCSD + description: "When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. \nNOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SEND_AUTO_STOP_CCSD + description: "Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CEATA_DEVICE_INTERRUPT_STATUS + description: "Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit." + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: CLKDIV + description: Clock divider configuration register + addressOffset: 8 + size: 32 + fields: + - name: CLK_DIVIDER0 + description: "Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CLK_DIVIDER1 + description: "Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on." + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: CLK_DIVIDER2 + description: "Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on." + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: CLK_DIVIDER3 + description: "Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on." + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: CLKSRC + description: Clock source selection register + addressOffset: 12 + size: 32 + fields: + - name: CLKSRC + description: "Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for card 1. Card 0 maps and internally routes clock divider[0:3] outputs to cclk_out[1:0] pins, depending on bit value.\n00 : Clock divider 0;\n01 : Clock divider 1;\n10 : Clock divider 2;\n11 : Clock divider 3." + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CLKENA + description: Clock enable register + addressOffset: 16 + size: 32 + fields: + - name: CCLK_ENABLE + description: "Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card.\n0: Clock disabled;\n1: Clock enabled." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: LP_ENABLE + description: "Disable clock when the card is in IDLE state. One bit per card.\n0: clock disabled;\n1: clock enabled." + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: TMOUT + description: Data and response timeout configuration register + addressOffset: 20 + size: 32 + resetValue: 4294967104 + fields: + - name: RESPONSE_TIMEOUT + description: "Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: DATA_TIMEOUT + description: "Value for card data read timeout. This value is also used for data starvation by host timeout. The timeout counter is started only after the card clock is stopped. This value is specified in number of card output clocks, i.e. sdhost_cclk_out of the selected card.\nNOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled." + bitOffset: 8 + bitWidth: 24 + access: read-write + - register: + name: CTYPE + description: Card bus width configuration register + addressOffset: 24 + size: 32 + fields: + - name: CARD_WIDTH4 + description: "One bit per card indicates if card is 1-bit or 4-bit mode.\n0: 1-bit mode;\n1: 4-bit mode.\nBit[1:0] correspond to card[1:0] respectively." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CARD_WIDTH8 + description: "One bit per card indicates if card is in 8-bit mode.\n0: Non 8-bit mode;\n1: 8-bit mode.\nBit[17:16] correspond to card[1:0] respectively." + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: BLKSIZ + description: Card data block size configuration register + addressOffset: 28 + size: 32 + resetValue: 512 + fields: + - name: BLOCK_SIZE + description: Block size. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: BYTCNT + description: Data transfer length configuration register + addressOffset: 32 + size: 32 + resetValue: 512 + fields: + - name: BYTE_COUNT + description: "Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: INTMASK + description: SDIO interrupt mask register + addressOffset: 36 + size: 32 + fields: + - name: INT_MASK + description: "These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt.\nBit 15 (EBE): End-bit error/no CRC error;\nBit 14 (ACD): Auto command done;\nBit 13 (SBE/BCI): Rx Start Bit Error;\nBit 12 (HLE): Hardware locked write error;\nBit 11 (FRUN): FIFO underrun/overrun error;\nBit 10 (HTO): Data starvation-by-host timeout;\nBit 9 (DRTO): Data read timeout;\nBit 8 (RTO): Response timeout; \nBit 7 (DCRC): Data CRC error; \nBit 6 (RCRC): Response CRC error; \nBit 5 (RXDR): Receive FIFO data request; \nBit 4 (TXDR): Transmit FIFO data request; \nBit 3 (DTO): Data transfer over; \nBit 2 (CD): Command done; \nBit 1 (RE): Response error;\nBit 0 (CD): Card detect." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SDIO_INT_MASK + description: "SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0] respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt, and 1 enables an interrupt." + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: CMDARG + description: Command argument data register + addressOffset: 40 + size: 32 + fields: + - name: CMDARG + description: Value indicates command argument to be passed to the card. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CMD + description: Command and boot configuration register + addressOffset: 44 + size: 32 + resetValue: 536870912 + fields: + - name: INDEX + description: Command index. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: RESPONSE_EXPECT + description: "0: No response expected from card; 1: Response expected from card." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RESPONSE_LENGTH + description: "0: Short response expected from card; 1: Long response expected from card." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CHECK_RESPONSE_CRC + description: "0: Do not check; 1: Check response CRC.\nSome of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DATA_EXPECTED + description: "0: No data transfer expected; 1: Data transfer expected." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: READ_WRITE + description: "0: Read from card; 1: Write to card.\nDon't care if no data is expected from card." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TRANSFER_MODE + description: "0: Block data transfer command; 1: Stream data transfer command.\nDon't care if no data expected." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SEND_AUTO_STOP + description: "0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: WAIT_PRVDATA_COMPLETE + description: "0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command.\nThe SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: STOP_ABORT_CMD + description: "0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress.\nWhen open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SEND_INITIALIZATION + description: "0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command.\nAfter powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CARD_NUMBER + description: "Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported." + bitOffset: 16 + bitWidth: 5 + access: read-write + - name: UPDATE_CLOCK_REGISTERS_ONLY + description: "0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain.\nFollowing register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA.\nChanges card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: READ_CEATA_DEVICE + description: "Read access flag.\n0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device;\n1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device.\nSoftware should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: CCS_EXPECTED + description: "Expected Command Completion Signal (CCS) configuration.\n0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device;\n1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. \nIf the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: USE_HOLE + description: "Use Hold Register.\n0: CMD and DATA sent to card bypassing HOLD Register;\n1: CMD and DATA sent to card through the HOLD Register." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: START_CMD + description: "Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RESP0 + description: Response data register + addressOffset: 48 + size: 32 + fields: + - name: RESPONSE0 + description: "Bit[31:0] of response." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RESP1 + description: Long response data register + addressOffset: 52 + size: 32 + fields: + - name: RESPONSE1 + description: "Bit[63:32] of long response." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RESP2 + description: Long response data register + addressOffset: 56 + size: 32 + fields: + - name: RESPONSE2 + description: "Bit[95:64] of long response." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RESP3 + description: Long response data register + addressOffset: 60 + size: 32 + fields: + - name: RESPONSE3 + description: "Bit[127:96] of long response." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: MINTSTS + description: Masked interrupt status register + addressOffset: 64 + size: 32 + fields: + - name: INT_STATUS_MSK + description: "Interrupt enabled only if corresponding bit in interrupt mask register is set.\nBit 15 (EBE): End-bit error/no CRC error;\nBit 14 (ACD): Auto command done;\nBit 13 (SBE/BCI): RX Start Bit Error;\nBit 12 (HLE): Hardware locked write error; \nBit 11 (FRUN): FIFO underrun/overrun error;\nBit 10 (HTO): Data starvation by host timeout (HTO);\nBit 9 (DTRO): Data read timeout; \nBit 8 (RTO): Response timeout; \nBit 7 (DCRC): Data CRC error; \nBit 6 (RCRC): Response CRC error; \nBit 5 (RXDR): Receive FIFO data request; \nBit 4 (TXDR): Transmit FIFO data request;\nBit 3 (DTO): Data transfer over; \nBit 2 (CD): Command done; \nBit 1 (RE): Response error;\nBit 0 (CD): Card detect." + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: SDIO_INTERRUPT_MSK + description: "Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. SDIO interrupt for card is enabled only if corresponding sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit enables interrupt)." + bitOffset: 16 + bitWidth: 2 + access: read-only + - register: + name: RINTSTS + description: Raw interrupt status register + addressOffset: 68 + size: 32 + fields: + - name: INT_STATUS_RAW + description: "Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status.\nBit 15 (EBE): End-bit error/no CRC error;\nBit 14 (ACD): Auto command done;\nBit 13 (SBE/BCI): RX Start Bit Error;\nBit 12 (HLE): Hardware locked write error; \nBit 11 (FRUN): FIFO underrun/overrun error;\nBit 10 (HTO): Data starvation by host timeout (HTO);\nBit 9 (DTRO): Data read timeout; \nBit 8 (RTO): Response timeout; \nBit 7 (DCRC): Data CRC error; \nBit 6 (RCRC): Response CRC error; \nBit 5 (RXDR): Receive FIFO data request; \nBit 4 (TXDR): Transmit FIFO data request;\nBit 3 (DTO): Data transfer over; \nBit 2 (CD): Command done; \nBit 1 (RE): Response error;\nBit 0 (CD): Card detect." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SDIO_INTERRUPT_RAW + description: "Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has no effect.\n0: No SDIO interrupt from card;\n1: SDIO interrupt from card." + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: STATUS + description: SD/MMC status register + addressOffset: 72 + size: 32 + resetValue: 1814 + fields: + - name: FIFO_RX_WATERMARK + description: "FIFO reached Receive watermark level, not qualified with data transfer." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: FIFO_TX_WATERMARK + description: "FIFO reached Transmit watermark level, not qualified with data transfer." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: FIFO_EMPTY + description: FIFO is empty status. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FIFO_FULL + description: FIFO is full status. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: COMMAND_FSM_STATES + description: "Command FSM states.\n0: Idle;\n1: Send init sequence; \n2: Send cmd start bit; \n3: Send cmd tx bit;\n4: Send cmd index + arg;\n5: Send cmd crc7;\n6: Send cmd end bit;\n7: Receive resp start bit;\n8: Receive resp IRQ response;\n9: Receive resp tx bit;\n10: Receive resp cmd idx;\n11: Receive resp data;\n12: Receive resp crc7;\n13: Receive resp end bit;\n14: Cmd path wait NCC;\n15: Wait, cmd-to-response turnaround." + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: DATA_3_STATUS + description: "Raw selected sdhost_card_data[3], checks whether card is present.\n0: card not present;\n1: card present." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DATA_BUSY + description: "Inverted version of raw selected sdhost_card_data[0].\n0: Card data not busy;\n1: Card data busy." + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: DATA_STATE_MC_BUSY + description: Data transmit or receive state-machine is busy. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: RESPONSE_INDEX + description: "Index of previous response, including any auto-stop sent by core." + bitOffset: 11 + bitWidth: 6 + access: read-only + - name: FIFO_COUNT + description: "FIFO count, number of filled locations in FIFO." + bitOffset: 17 + bitWidth: 13 + access: read-only + - register: + name: FIFOTH + description: FIFO configuration register + addressOffset: 76 + size: 32 + fields: + - name: TX_WMARK + description: "FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred." + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: RX_WMARK + description: "FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set." + bitOffset: 16 + bitWidth: 11 + access: read-write + - name: DMA_MULTIPLE_TRANSACTION_SIZE + description: "Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE.\n000: 1-byte transfer; \n001: 4-byte transfer; \n010: 8-byte transfer; \n011: 16-byte transfer; \n100: 32-byte transfer; \n101: 64-byte transfer; \n110: 128-byte transfer; \n111: 256-byte transfer." + bitOffset: 28 + bitWidth: 3 + access: read-write + - register: + name: CDETECT + description: Card detect register + addressOffset: 80 + size: 32 + fields: + - name: CARD_DETECT_N + description: "Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0 represents presence of card. Only NUM_CARDS number of bits are implemented." + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: WRTPRT + description: Card write protection (WP) status register + addressOffset: 84 + size: 32 + fields: + - name: WRITE_PROTECT + description: Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write protection. Only NUM_CARDS number of bits are implemented. + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: TCBCNT + description: Transferred byte count register + addressOffset: 92 + size: 32 + fields: + - name: TCBCNT + description: Number of bytes transferred by CIU unit to card. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: TBBCNT + description: Transferred byte count register + addressOffset: 96 + size: 32 + fields: + - name: TBBCNT + description: Number of bytes transferred between Host/DMA memory and BIU FIFO. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEBNCE + description: Debounce filter time configuration register + addressOffset: 100 + size: 32 + fields: + - name: DEBOUNCE_COUNT + description: "Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \\verb+~+ 25 ms to prevent the card instability when the card is inserted or removed." + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: USRID + description: User ID (scratchpad) register + addressOffset: 104 + size: 32 + fields: + - name: USRID + description: "User identification register, value set by user. Can also be used as a scratchpad register by user." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: VERID + description: Version ID (scratchpad) register + addressOffset: 108 + size: 32 + resetValue: 1412572938 + fields: + - name: VERSIONID + description: Hardware version register. Can also be read by fireware. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HCON + description: Hardware feature register + addressOffset: 112 + size: 32 + resetValue: 54807747 + fields: + - name: CARD_TYPE + description: Hardware support SDIO and MMC. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CARD_NUM + description: Support card number is 2. + bitOffset: 1 + bitWidth: 5 + access: read-only + - name: BUS_TYPE + description: Register config is APB bus. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: DATA_WIDTH + description: Regisger data widht is 32. + bitOffset: 7 + bitWidth: 3 + access: read-only + - name: ADDR_WIDTH + description: Register address width is 32. + bitOffset: 10 + bitWidth: 6 + access: read-only + - name: DMA_WIDTH + description: DMA data witdth is 32. + bitOffset: 18 + bitWidth: 3 + access: read-only + - name: RAM_INDISE + description: Inside RAM in SDMMC module. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: HOLD + description: Have a hold regiser in data path . + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: NUM_CLK_DIV + description: Have 4 clk divider in design . + bitOffset: 24 + bitWidth: 2 + access: read-only + - register: + name: UHS + description: UHS-1 register + addressOffset: 116 + size: 32 + fields: + - name: DDR + description: "DDR mode selecton,1 bit for each card.\n0-Non-DDR mdoe.\n1-DDR mdoe." + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: RST_N + description: Card reset register + addressOffset: 120 + size: 32 + resetValue: 1 + fields: + - name: CARD_RESET + description: "Hardware reset.\n1: Active mode; \n0: Reset. \nThese bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET[0] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET[1] should be set to 1'b0 to reset card1." + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: BMOD + description: Burst mode transfer configuration register + addressOffset: 128 + size: 32 + fields: + - name: SWR + description: "Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FB + description: "Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DE + description: "IDMAC Enable. When set, the IDMAC is enabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: PBL + description: "Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows:\n000: 1-byte transfer; \n001: 4-byte transfer; \n010: 8-byte transfer; \n011: 16-byte transfer; \n100: 32-byte transfer; \n101: 64-byte transfer; \n110: 128-byte transfer; \n111: 256-byte transfer.\nPBL is a read-only value and is applicable only for data access, it does not apply to descriptor access." + bitOffset: 8 + bitWidth: 3 + access: read-write + - register: + name: PLDMND + description: Poll demand configuration register + addressOffset: 132 + size: 32 + fields: + - name: PD + description: "Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal descriptor fetch operation. This is a write only ." + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: DBADDR + description: Descriptor base address register + addressOffset: 136 + size: 32 + fields: + - name: DBADDR + description: "Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: IDSTS + description: IDMAC status register + addressOffset: 140 + size: 32 + fields: + - name: TI + description: Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RI + description: Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FBE + description: "Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DU + description: "Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0[31] = 0). Writing 1 clears this bit." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CES + description: "Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits:\nEBE : End Bit Error; \nRTO : Response Timeout/Boot Ack Timeout; \nRCRC : Response CRC; \nSBE : Start Bit Error; \nDRTO : Data Read Timeout/BDS timeout; \nDCRC : Data CRC for Receive; \nRE : Response Error.\nWriting 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: NIS + description: "Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit Interrupt, IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: AIS + description: "Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus Interrupt, IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FBE_CODE + description: "Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an interrupt.\n001: Host Abort received during transmission;\n010: Host Abort received during reception;\nOthers: Reserved." + bitOffset: 10 + bitWidth: 3 + access: read-write + - name: FSM + description: "DMAC FSM present state.\n0: DMA_IDLE (idle state); \n1: DMA_SUSPEND (suspend state); \n2: DESC_RD (descriptor reading state); \n3: DESC_CHK (descriptor checking state); \n4: DMA_RD_REQ_WAIT (read-data request waiting state);\n5: DMA_WR_REQ_WAIT (write-data request waiting state); \n6: DMA_RD (data-read state); \n7: DMA_WR (data-write state); \n8: DESC_CLOSE (descriptor close state)." + bitOffset: 13 + bitWidth: 4 + access: read-write + - register: + name: IDINTEN + description: IDMAC interrupt enable register + addressOffset: 144 + size: 32 + fields: + - name: TI + description: "Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RI + description: "Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FBE + description: "Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DU + description: "Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CES + description: "Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: NI + description: "Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits:\nIDINTEN[0]: Transmit Interrupt;\nIDINTEN[1]: Receive Interrupt." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: AI + description: "Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits:\nIDINTEN[2]: Fatal Bus Error Interrupt;\nIDINTEN[4]: DU Interrupt." + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: DSCADDR + description: Host descriptor address pointer + addressOffset: 148 + size: 32 + fields: + - name: DSCADDR + description: "Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the start address of the current descriptor read by the IDMAC." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BUFADDR + description: Host buffer address pointer register + addressOffset: 152 + size: 32 + fields: + - name: BUFADDR + description: "Host Buffer Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the current Data Buffer Address being accessed by the IDMAC." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CARDTHRCTL + description: Card Threshold Control register + addressOffset: 256 + size: 32 + fields: + - name: CARDRDTHREN + description: "Card read threshold enable.\n1'b0-Card read threshold disabled.\n1'b1-Card read threshold enabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CARDCLRINTEN + description: "Busy clear interrupt generation:\n1'b0-Busy clear interrypt disabled.\n1'b1-Busy clear interrypt enabled." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CARDWRTHREN + description: "Applicable when HS400 mode is enabled.\n1'b0-Card write Threshold disabled.\n1'b1-Card write Threshold enabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CARDTHRESHOLD + description: "The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG set to 1." + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: EMMCDDR + description: eMMC DDR register + addressOffset: 268 + size: 32 + fields: + - name: HALFSTARTBIT + description: "Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be:\n1'b0-Full cycle.\n1'b1-less than one full cycle." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: HS400_MODE + description: Set 1 to enable HS400 mode. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: ENSHIFT + description: Enable Phase Shift register + addressOffset: 272 + size: 32 + fields: + - name: ENABLE_SHIFT + description: "Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card.\n2'b00-Default phase shift.\n2'b01-Enables shifted to next immediate positive edge.\n2'b10-Enables shifted to next immediate negative edge.\n2'b11-Reserved." + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: BUFFIFO + description: CPU write and read transmit data by FIFO + addressOffset: 512 + size: 32 + fields: + - name: BUFFIFO + description: CPU write and read transmit data by FIFO. This register points to the current Data FIFO . + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CLK_EDGE_SEL + description: SDIO control register. + addressOffset: 2048 + size: 32 + resetValue: 8520192 + fields: + - name: CCLKIN_EDGE_DRV_SEL + description: "It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270." + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: CCLKIN_EDGE_SAM_SEL + description: "It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270." + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: CCLKIN_EDGE_SLF_SEL + description: "It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270." + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: CCLLKIN_EDGE_H + description: The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L. + bitOffset: 9 + bitWidth: 4 + access: read-write + - name: CCLLKIN_EDGE_L + description: The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H. + bitOffset: 13 + bitWidth: 4 + access: read-write + - name: CCLLKIN_EDGE_N + description: The clock division of cclk_in. + bitOffset: 17 + bitWidth: 4 + access: read-write + - name: ESDIO_MODE + description: Enable esdio mode. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: ESD_MODE + description: Enable esd mode. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: CCLK_EN + description: Sdio clock enable. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: ULTRA_HIGH_SPEED_MODE + description: "Enable ultra high speed mode, use dll to generate clk." + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: RAW_INTS + description: SDIO raw ints register. + addressOffset: 2052 + size: 32 + fields: + - name: RAW_INTS + description: It indicates raw ints. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DLL_CLK_CONF + description: SDIO DLL clock control register. + addressOffset: 2056 + size: 32 + fields: + - name: DLL_CCLK_IN_SLF_EN + description: Clock enable of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DLL_CCLK_IN_DRV_EN + description: Clock enable of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DLL_CCLK_IN_SAM_EN + description: Clock enable of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DLL_CCLK_IN_SLF_PHASE + description: "It's used to control the phase of cclk_in_slf when ULTRA_HIGH_SPEED_MODE==1." + bitOffset: 3 + bitWidth: 6 + access: read-write + - name: DLL_CCLK_IN_DRV_PHASE + description: "It's used to control the phase of cclk_in_drv when ULTRA_HIGH_SPEED_MODE==1." + bitOffset: 9 + bitWidth: 6 + access: read-write + - name: DLL_CCLK_IN_SAM_PHASE + description: "It's used to control the phase of cclk_in_sam when ULTRA_HIGH_SPEED_MODE==1." + bitOffset: 15 + bitWidth: 6 + access: read-write + - register: + name: DLL_CONF + description: SDIO DLL configuration register. + addressOffset: 2060 + size: 32 + fields: + - name: DLL_CAL_STOP + description: Set 1 to stop calibration. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DLL_CAL_END + description: 1 means calibration finished. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SHA + description: SHA (Secure Hash Algorithm) Accelerator + groupName: SHA + baseAddress: 1342771200 + addressBlock: + - offset: 0 + size: 176 + usage: registers + interrupt: + - name: SHA + value: 70 + registers: + - register: + name: MODE + description: Initial configuration register. + addressOffset: 0 + size: 32 + fields: + - name: MODE + description: Sha mode. + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: T_STRING + description: SHA 512/t configuration register 0. + addressOffset: 4 + size: 32 + fields: + - name: T_STRING + description: Sha t_string (used if and only if mode == SHA_512/t). + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: T_LENGTH + description: SHA 512/t configuration register 1. + addressOffset: 8 + size: 32 + fields: + - name: T_LENGTH + description: Sha t_length (used if and only if mode == SHA_512/t). + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: DMA_BLOCK_NUM + description: DMA configuration register 0. + addressOffset: 12 + size: 32 + fields: + - name: DMA_BLOCK_NUM + description: Dma-sha block number. + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: START + description: Typical SHA configuration register 0. + addressOffset: 16 + size: 32 + fields: + - name: START + description: Reserved. + bitOffset: 1 + bitWidth: 31 + access: read-only + - register: + name: CONTINUE + description: Typical SHA configuration register 1. + addressOffset: 20 + size: 32 + fields: + - name: CONTINUE + description: Reserved. + bitOffset: 1 + bitWidth: 31 + access: read-only + - register: + name: BUSY + description: Busy register. + addressOffset: 24 + size: 32 + fields: + - name: STATE + description: "Sha busy state. 1'b0: idle. 1'b1: busy." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: DMA_START + description: DMA configuration register 1. + addressOffset: 28 + size: 32 + fields: + - name: DMA_START + description: Start dma-sha. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: DMA_CONTINUE + description: DMA configuration register 2. + addressOffset: 32 + size: 32 + fields: + - name: DMA_CONTINUE + description: Continue dma-sha. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: CLEAR_IRQ + description: Interrupt clear register. + addressOffset: 36 + size: 32 + fields: + - name: CLEAR_INTERRUPT + description: Clear sha interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: IRQ_ENA + description: Interrupt enable register. + addressOffset: 40 + size: 32 + fields: + - name: INTERRUPT_ENA + description: "Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Date register. + addressOffset: 44 + size: 32 + resetValue: 538972713 + fields: + - name: DATE + description: Sha date information/ sha version information. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + dim: 16 + dimIncrement: 4 + name: "H_MEM[%s]" + description: Sha H memory which contains intermediate hash or finial hash. + addressOffset: 64 + size: 32 + - register: + dim: 16 + dimIncrement: 4 + name: "M_MEM[%s]" + description: Sha M memory which contains message. + addressOffset: 128 + size: 32 + - name: SOC_ETM + description: Event Task Matrix + groupName: SOC_ETM + baseAddress: 1343049728 + addressBlock: + - offset: 0 + size: 552 + usage: registers + registers: + - register: + name: CH_ENA_AD0 + description: Channel enable status register + addressOffset: 0 + size: 32 + fields: + - name: CH_ENA0 + description: "Represents ch0 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CH_ENA1 + description: "Represents ch1 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CH_ENA2 + description: "Represents ch2 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CH_ENA3 + description: "Represents ch3 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CH_ENA4 + description: "Represents ch4 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CH_ENA5 + description: "Represents ch5 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CH_ENA6 + description: "Represents ch6 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CH_ENA7 + description: "Represents ch7 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CH_ENA8 + description: "Represents ch8 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CH_ENA9 + description: "Represents ch9 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CH_ENA10 + description: "Represents ch10 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CH_ENA11 + description: "Represents ch11 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CH_ENA12 + description: "Represents ch12 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CH_ENA13 + description: "Represents ch13 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: CH_ENA14 + description: "Represents ch14 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CH_ENA15 + description: "Represents ch15 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CH_ENA16 + description: "Represents ch16 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CH_ENA17 + description: "Represents ch17 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: CH_ENA18 + description: "Represents ch18 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: CH_ENA19 + description: "Represents ch19 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: CH_ENA20 + description: "Represents ch20 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CH_ENA21 + description: "Represents ch21 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CH_ENA22 + description: "Represents ch22 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: CH_ENA23 + description: "Represents ch23 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: CH_ENA24 + description: "Represents ch24 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: CH_ENA25 + description: "Represents ch25 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: CH_ENA26 + description: "Represents ch26 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CH_ENA27 + description: "Represents ch27 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: CH_ENA28 + description: "Represents ch28 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CH_ENA29 + description: "Represents ch29 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CH_ENA30 + description: "Represents ch30 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CH_ENA31 + description: "Represents ch31 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CH_ENA_AD0_SET + description: Channel enable set register + addressOffset: 4 + size: 32 + fields: + - name: CH_SET0 + description: "Configures whether or not to enable ch0.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CH_SET1 + description: "Configures whether or not to enable ch1.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CH_SET2 + description: "Configures whether or not to enable ch2.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CH_SET3 + description: "Configures whether or not to enable ch3.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: CH_SET4 + description: "Configures whether or not to enable ch4.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: CH_SET5 + description: "Configures whether or not to enable ch5.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CH_SET6 + description: "Configures whether or not to enable ch6.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: CH_SET7 + description: "Configures whether or not to enable ch7.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: CH_SET8 + description: "Configures whether or not to enable ch8.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: CH_SET9 + description: "Configures whether or not to enable ch9.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: CH_SET10 + description: "Configures whether or not to enable ch10.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: CH_SET11 + description: "Configures whether or not to enable ch11.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: CH_SET12 + description: "Configures whether or not to enable ch12.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: CH_SET13 + description: "Configures whether or not to enable ch13.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: CH_SET14 + description: "Configures whether or not to enable ch14.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: CH_SET15 + description: "Configures whether or not to enable ch15.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: CH_SET16 + description: "Configures whether or not to enable ch16.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: CH_SET17 + description: "Configures whether or not to enable ch17.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: CH_SET18 + description: "Configures whether or not to enable ch18.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: CH_SET19 + description: "Configures whether or not to enable ch19.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: CH_SET20 + description: "Configures whether or not to enable ch20.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: CH_SET21 + description: "Configures whether or not to enable ch21.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: CH_SET22 + description: "Configures whether or not to enable ch22.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: CH_SET23 + description: "Configures whether or not to enable ch23.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: CH_SET24 + description: "Configures whether or not to enable ch24.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: CH_SET25 + description: "Configures whether or not to enable ch25.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: CH_SET26 + description: "Configures whether or not to enable ch26.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: CH_SET27 + description: "Configures whether or not to enable ch27.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: CH_SET28 + description: "Configures whether or not to enable ch28.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: CH_SET29 + description: "Configures whether or not to enable ch29.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: CH_SET30 + description: "Configures whether or not to enable ch30.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: CH_SET31 + description: "Configures whether or not to enable ch31.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: CH_ENA_AD0_CLR + description: Channel enable clear register + addressOffset: 8 + size: 32 + fields: + - name: CH_CLR0 + description: "Configures whether or not to clear ch0 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CH_CLR1 + description: "Configures whether or not to clear ch1 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CH_CLR2 + description: "Configures whether or not to clear ch2 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CH_CLR3 + description: "Configures whether or not to clear ch3 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: CH_CLR4 + description: "Configures whether or not to clear ch4 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: CH_CLR5 + description: "Configures whether or not to clear ch5 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CH_CLR6 + description: "Configures whether or not to clear ch6 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: CH_CLR7 + description: "Configures whether or not to clear ch7 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: CH_CLR8 + description: "Configures whether or not to clear ch8 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: CH_CLR9 + description: "Configures whether or not to clear ch9 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: CH_CLR10 + description: "Configures whether or not to clear ch10 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: CH_CLR11 + description: "Configures whether or not to clear ch11 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: CH_CLR12 + description: "Configures whether or not to clear ch12 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: CH_CLR13 + description: "Configures whether or not to clear ch13 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: CH_CLR14 + description: "Configures whether or not to clear ch14 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: CH_CLR15 + description: "Configures whether or not to clear ch15 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: CH_CLR16 + description: "Configures whether or not to clear ch16 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: CH_CLR17 + description: "Configures whether or not to clear ch17 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: CH_CLR18 + description: "Configures whether or not to clear ch18 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: CH_CLR19 + description: "Configures whether or not to clear ch19 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: CH_CLR20 + description: "Configures whether or not to clear ch20 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: CH_CLR21 + description: "Configures whether or not to clear ch21 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: CH_CLR22 + description: "Configures whether or not to clear ch22 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: CH_CLR23 + description: "Configures whether or not to clear ch23 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: CH_CLR24 + description: "Configures whether or not to clear ch24 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: CH_CLR25 + description: "Configures whether or not to clear ch25 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: CH_CLR26 + description: "Configures whether or not to clear ch26 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: CH_CLR27 + description: "Configures whether or not to clear ch27 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: CH_CLR28 + description: "Configures whether or not to clear ch28 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: CH_CLR29 + description: "Configures whether or not to clear ch29 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: CH_CLR30 + description: "Configures whether or not to clear ch30 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: CH_CLR31 + description: "Configures whether or not to clear ch31 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: CH_ENA_AD1 + description: Channel enable status register + addressOffset: 12 + size: 32 + fields: + - name: CH_ENA32 + description: "Represents ch32 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CH_ENA33 + description: "Represents ch33 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CH_ENA34 + description: "Represents ch34 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CH_ENA35 + description: "Represents ch35 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CH_ENA36 + description: "Represents ch36 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CH_ENA37 + description: "Represents ch37 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CH_ENA38 + description: "Represents ch38 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CH_ENA39 + description: "Represents ch39 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CH_ENA40 + description: "Represents ch40 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CH_ENA41 + description: "Represents ch41 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CH_ENA42 + description: "Represents ch42 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CH_ENA43 + description: "Represents ch43 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CH_ENA44 + description: "Represents ch44 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CH_ENA45 + description: "Represents ch45 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: CH_ENA46 + description: "Represents ch46 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CH_ENA47 + description: "Represents ch47 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CH_ENA48 + description: "Represents ch48 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CH_ENA49 + description: "Represents ch49 enable status.\\\\0: Disable\\\\1: Enable" + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: CH_ENA_AD1_SET + description: Channel enable set register + addressOffset: 16 + size: 32 + fields: + - name: CH_SET32 + description: "Configures whether or not to enable ch32.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CH_SET33 + description: "Configures whether or not to enable ch33.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CH_SET34 + description: "Configures whether or not to enable ch34.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CH_SET35 + description: "Configures whether or not to enable ch35.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: CH_SET36 + description: "Configures whether or not to enable ch36.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: CH_SET37 + description: "Configures whether or not to enable ch37.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CH_SET38 + description: "Configures whether or not to enable ch38.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: CH_SET39 + description: "Configures whether or not to enable ch39.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: CH_SET40 + description: "Configures whether or not to enable ch40.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: CH_SET41 + description: "Configures whether or not to enable ch41.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: CH_SET42 + description: "Configures whether or not to enable ch42.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: CH_SET43 + description: "Configures whether or not to enable ch43.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: CH_SET44 + description: "Configures whether or not to enable ch44.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: CH_SET45 + description: "Configures whether or not to enable ch45.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: CH_SET46 + description: "Configures whether or not to enable ch46.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: CH_SET47 + description: "Configures whether or not to enable ch47.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: CH_SET48 + description: "Configures whether or not to enable ch48.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: CH_SET49 + description: "Configures whether or not to enable ch49.\\\\0: Invalid, No effect\\\\1: Enable" + bitOffset: 17 + bitWidth: 1 + access: write-only + - register: + name: CH_ENA_AD1_CLR + description: Channel enable clear register + addressOffset: 20 + size: 32 + fields: + - name: CH_CLR32 + description: "Configures whether or not to clear ch32 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CH_CLR33 + description: "Configures whether or not to clear ch33 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CH_CLR34 + description: "Configures whether or not to clear ch34 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CH_CLR35 + description: "Configures whether or not to clear ch35 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: CH_CLR36 + description: "Configures whether or not to clear ch36 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: CH_CLR37 + description: "Configures whether or not to clear ch37 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CH_CLR38 + description: "Configures whether or not to clear ch38 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: CH_CLR39 + description: "Configures whether or not to clear ch39 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: CH_CLR40 + description: "Configures whether or not to clear ch40 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: CH_CLR41 + description: "Configures whether or not to clear ch41 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: CH_CLR42 + description: "Configures whether or not to clear ch42 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: CH_CLR43 + description: "Configures whether or not to clear ch43 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: CH_CLR44 + description: "Configures whether or not to clear ch44 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: CH_CLR45 + description: "Configures whether or not to clear ch45 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: CH_CLR46 + description: "Configures whether or not to clear ch46 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: CH_CLR47 + description: "Configures whether or not to clear ch47 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: CH_CLR48 + description: "Configures whether or not to clear ch48 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: CH_CLR49 + description: "Configures whether or not to clear ch49 enable.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 17 + bitWidth: 1 + access: write-only + - register: + name: CH0_EVT_ID + description: Channel0 event id register + addressOffset: 24 + size: 32 + fields: + - name: CH0_EVT_ID + description: Configures ch0_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH0_TASK_ID + description: Channel0 task id register + addressOffset: 28 + size: 32 + fields: + - name: CH0_TASK_ID + description: Configures ch0_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH1_EVT_ID + description: Channel1 event id register + addressOffset: 32 + size: 32 + fields: + - name: CH1_EVT_ID + description: Configures ch1_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH1_TASK_ID + description: Channel1 task id register + addressOffset: 36 + size: 32 + fields: + - name: CH1_TASK_ID + description: Configures ch1_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH2_EVT_ID + description: Channel2 event id register + addressOffset: 40 + size: 32 + fields: + - name: CH2_EVT_ID + description: Configures ch2_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH2_TASK_ID + description: Channel2 task id register + addressOffset: 44 + size: 32 + fields: + - name: CH2_TASK_ID + description: Configures ch2_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH3_EVT_ID + description: Channel3 event id register + addressOffset: 48 + size: 32 + fields: + - name: CH3_EVT_ID + description: Configures ch3_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH3_TASK_ID + description: Channel3 task id register + addressOffset: 52 + size: 32 + fields: + - name: CH3_TASK_ID + description: Configures ch3_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH4_EVT_ID + description: Channel4 event id register + addressOffset: 56 + size: 32 + fields: + - name: CH4_EVT_ID + description: Configures ch4_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH4_TASK_ID + description: Channel4 task id register + addressOffset: 60 + size: 32 + fields: + - name: CH4_TASK_ID + description: Configures ch4_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH5_EVT_ID + description: Channel5 event id register + addressOffset: 64 + size: 32 + fields: + - name: CH5_EVT_ID + description: Configures ch5_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH5_TASK_ID + description: Channel5 task id register + addressOffset: 68 + size: 32 + fields: + - name: CH5_TASK_ID + description: Configures ch5_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH6_EVT_ID + description: Channel6 event id register + addressOffset: 72 + size: 32 + fields: + - name: CH6_EVT_ID + description: Configures ch6_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH6_TASK_ID + description: Channel6 task id register + addressOffset: 76 + size: 32 + fields: + - name: CH6_TASK_ID + description: Configures ch6_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH7_EVT_ID + description: Channel7 event id register + addressOffset: 80 + size: 32 + fields: + - name: CH7_EVT_ID + description: Configures ch7_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH7_TASK_ID + description: Channel7 task id register + addressOffset: 84 + size: 32 + fields: + - name: CH7_TASK_ID + description: Configures ch7_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH8_EVT_ID + description: Channel8 event id register + addressOffset: 88 + size: 32 + fields: + - name: CH8_EVT_ID + description: Configures ch8_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH8_TASK_ID + description: Channel8 task id register + addressOffset: 92 + size: 32 + fields: + - name: CH8_TASK_ID + description: Configures ch8_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH9_EVT_ID + description: Channel9 event id register + addressOffset: 96 + size: 32 + fields: + - name: CH9_EVT_ID + description: Configures ch9_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH9_TASK_ID + description: Channel9 task id register + addressOffset: 100 + size: 32 + fields: + - name: CH9_TASK_ID + description: Configures ch9_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH10_EVT_ID + description: Channel10 event id register + addressOffset: 104 + size: 32 + fields: + - name: CH10_EVT_ID + description: Configures ch10_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH10_TASK_ID + description: Channel10 task id register + addressOffset: 108 + size: 32 + fields: + - name: CH10_TASK_ID + description: Configures ch10_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH11_EVT_ID + description: Channel11 event id register + addressOffset: 112 + size: 32 + fields: + - name: CH11_EVT_ID + description: Configures ch11_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH11_TASK_ID + description: Channel11 task id register + addressOffset: 116 + size: 32 + fields: + - name: CH11_TASK_ID + description: Configures ch11_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH12_EVT_ID + description: Channel12 event id register + addressOffset: 120 + size: 32 + fields: + - name: CH12_EVT_ID + description: Configures ch12_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH12_TASK_ID + description: Channel12 task id register + addressOffset: 124 + size: 32 + fields: + - name: CH12_TASK_ID + description: Configures ch12_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH13_EVT_ID + description: Channel13 event id register + addressOffset: 128 + size: 32 + fields: + - name: CH13_EVT_ID + description: Configures ch13_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH13_TASK_ID + description: Channel13 task id register + addressOffset: 132 + size: 32 + fields: + - name: CH13_TASK_ID + description: Configures ch13_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH14_EVT_ID + description: Channel14 event id register + addressOffset: 136 + size: 32 + fields: + - name: CH14_EVT_ID + description: Configures ch14_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH14_TASK_ID + description: Channel14 task id register + addressOffset: 140 + size: 32 + fields: + - name: CH14_TASK_ID + description: Configures ch14_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH15_EVT_ID + description: Channel15 event id register + addressOffset: 144 + size: 32 + fields: + - name: CH15_EVT_ID + description: Configures ch15_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH15_TASK_ID + description: Channel15 task id register + addressOffset: 148 + size: 32 + fields: + - name: CH15_TASK_ID + description: Configures ch15_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH16_EVT_ID + description: Channel16 event id register + addressOffset: 152 + size: 32 + fields: + - name: CH16_EVT_ID + description: Configures ch16_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH16_TASK_ID + description: Channel16 task id register + addressOffset: 156 + size: 32 + fields: + - name: CH16_TASK_ID + description: Configures ch16_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH17_EVT_ID + description: Channel17 event id register + addressOffset: 160 + size: 32 + fields: + - name: CH17_EVT_ID + description: Configures ch17_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH17_TASK_ID + description: Channel17 task id register + addressOffset: 164 + size: 32 + fields: + - name: CH17_TASK_ID + description: Configures ch17_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH18_EVT_ID + description: Channel18 event id register + addressOffset: 168 + size: 32 + fields: + - name: CH18_EVT_ID + description: Configures ch18_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH18_TASK_ID + description: Channel18 task id register + addressOffset: 172 + size: 32 + fields: + - name: CH18_TASK_ID + description: Configures ch18_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH19_EVT_ID + description: Channel19 event id register + addressOffset: 176 + size: 32 + fields: + - name: CH19_EVT_ID + description: Configures ch19_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH19_TASK_ID + description: Channel19 task id register + addressOffset: 180 + size: 32 + fields: + - name: CH19_TASK_ID + description: Configures ch19_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH20_EVT_ID + description: Channel20 event id register + addressOffset: 184 + size: 32 + fields: + - name: CH20_EVT_ID + description: Configures ch20_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH20_TASK_ID + description: Channel20 task id register + addressOffset: 188 + size: 32 + fields: + - name: CH20_TASK_ID + description: Configures ch20_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH21_EVT_ID + description: Channel21 event id register + addressOffset: 192 + size: 32 + fields: + - name: CH21_EVT_ID + description: Configures ch21_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH21_TASK_ID + description: Channel21 task id register + addressOffset: 196 + size: 32 + fields: + - name: CH21_TASK_ID + description: Configures ch21_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH22_EVT_ID + description: Channel22 event id register + addressOffset: 200 + size: 32 + fields: + - name: CH22_EVT_ID + description: Configures ch22_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH22_TASK_ID + description: Channel22 task id register + addressOffset: 204 + size: 32 + fields: + - name: CH22_TASK_ID + description: Configures ch22_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH23_EVT_ID + description: Channel23 event id register + addressOffset: 208 + size: 32 + fields: + - name: CH23_EVT_ID + description: Configures ch23_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH23_TASK_ID + description: Channel23 task id register + addressOffset: 212 + size: 32 + fields: + - name: CH23_TASK_ID + description: Configures ch23_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH24_EVT_ID + description: Channel24 event id register + addressOffset: 216 + size: 32 + fields: + - name: CH24_EVT_ID + description: Configures ch24_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH24_TASK_ID + description: Channel24 task id register + addressOffset: 220 + size: 32 + fields: + - name: CH24_TASK_ID + description: Configures ch24_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH25_EVT_ID + description: Channel25 event id register + addressOffset: 224 + size: 32 + fields: + - name: CH25_EVT_ID + description: Configures ch25_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH25_TASK_ID + description: Channel25 task id register + addressOffset: 228 + size: 32 + fields: + - name: CH25_TASK_ID + description: Configures ch25_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH26_EVT_ID + description: Channel26 event id register + addressOffset: 232 + size: 32 + fields: + - name: CH26_EVT_ID + description: Configures ch26_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH26_TASK_ID + description: Channel26 task id register + addressOffset: 236 + size: 32 + fields: + - name: CH26_TASK_ID + description: Configures ch26_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH27_EVT_ID + description: Channel27 event id register + addressOffset: 240 + size: 32 + fields: + - name: CH27_EVT_ID + description: Configures ch27_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH27_TASK_ID + description: Channel27 task id register + addressOffset: 244 + size: 32 + fields: + - name: CH27_TASK_ID + description: Configures ch27_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH28_EVT_ID + description: Channel28 event id register + addressOffset: 248 + size: 32 + fields: + - name: CH28_EVT_ID + description: Configures ch28_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH28_TASK_ID + description: Channel28 task id register + addressOffset: 252 + size: 32 + fields: + - name: CH28_TASK_ID + description: Configures ch28_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH29_EVT_ID + description: Channel29 event id register + addressOffset: 256 + size: 32 + fields: + - name: CH29_EVT_ID + description: Configures ch29_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH29_TASK_ID + description: Channel29 task id register + addressOffset: 260 + size: 32 + fields: + - name: CH29_TASK_ID + description: Configures ch29_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH30_EVT_ID + description: Channel30 event id register + addressOffset: 264 + size: 32 + fields: + - name: CH30_EVT_ID + description: Configures ch30_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH30_TASK_ID + description: Channel30 task id register + addressOffset: 268 + size: 32 + fields: + - name: CH30_TASK_ID + description: Configures ch30_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH31_EVT_ID + description: Channel31 event id register + addressOffset: 272 + size: 32 + fields: + - name: CH31_EVT_ID + description: Configures ch31_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH31_TASK_ID + description: Channel31 task id register + addressOffset: 276 + size: 32 + fields: + - name: CH31_TASK_ID + description: Configures ch31_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH32_EVT_ID + description: Channel32 event id register + addressOffset: 280 + size: 32 + fields: + - name: CH32_EVT_ID + description: Configures ch32_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH32_TASK_ID + description: Channel32 task id register + addressOffset: 284 + size: 32 + fields: + - name: CH32_TASK_ID + description: Configures ch32_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH33_EVT_ID + description: Channel33 event id register + addressOffset: 288 + size: 32 + fields: + - name: CH33_EVT_ID + description: Configures ch33_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH33_TASK_ID + description: Channel33 task id register + addressOffset: 292 + size: 32 + fields: + - name: CH33_TASK_ID + description: Configures ch33_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH34_EVT_ID + description: Channel34 event id register + addressOffset: 296 + size: 32 + fields: + - name: CH34_EVT_ID + description: Configures ch34_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH34_TASK_ID + description: Channel34 task id register + addressOffset: 300 + size: 32 + fields: + - name: CH34_TASK_ID + description: Configures ch34_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH35_EVT_ID + description: Channel35 event id register + addressOffset: 304 + size: 32 + fields: + - name: CH35_EVT_ID + description: Configures ch35_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH35_TASK_ID + description: Channel35 task id register + addressOffset: 308 + size: 32 + fields: + - name: CH35_TASK_ID + description: Configures ch35_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH36_EVT_ID + description: Channel36 event id register + addressOffset: 312 + size: 32 + fields: + - name: CH36_EVT_ID + description: Configures ch36_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH36_TASK_ID + description: Channel36 task id register + addressOffset: 316 + size: 32 + fields: + - name: CH36_TASK_ID + description: Configures ch36_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH37_EVT_ID + description: Channel37 event id register + addressOffset: 320 + size: 32 + fields: + - name: CH37_EVT_ID + description: Configures ch37_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH37_TASK_ID + description: Channel37 task id register + addressOffset: 324 + size: 32 + fields: + - name: CH37_TASK_ID + description: Configures ch37_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH38_EVT_ID + description: Channel38 event id register + addressOffset: 328 + size: 32 + fields: + - name: CH38_EVT_ID + description: Configures ch38_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH38_TASK_ID + description: Channel38 task id register + addressOffset: 332 + size: 32 + fields: + - name: CH38_TASK_ID + description: Configures ch38_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH39_EVT_ID + description: Channel39 event id register + addressOffset: 336 + size: 32 + fields: + - name: CH39_EVT_ID + description: Configures ch39_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH39_TASK_ID + description: Channel39 task id register + addressOffset: 340 + size: 32 + fields: + - name: CH39_TASK_ID + description: Configures ch39_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH40_EVT_ID + description: Channel40 event id register + addressOffset: 344 + size: 32 + fields: + - name: CH40_EVT_ID + description: Configures ch40_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH40_TASK_ID + description: Channel40 task id register + addressOffset: 348 + size: 32 + fields: + - name: CH40_TASK_ID + description: Configures ch40_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH41_EVT_ID + description: Channel41 event id register + addressOffset: 352 + size: 32 + fields: + - name: CH41_EVT_ID + description: Configures ch41_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH41_TASK_ID + description: Channel41 task id register + addressOffset: 356 + size: 32 + fields: + - name: CH41_TASK_ID + description: Configures ch41_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH42_EVT_ID + description: Channel42 event id register + addressOffset: 360 + size: 32 + fields: + - name: CH42_EVT_ID + description: Configures ch42_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH42_TASK_ID + description: Channel42 task id register + addressOffset: 364 + size: 32 + fields: + - name: CH42_TASK_ID + description: Configures ch42_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH43_EVT_ID + description: Channel43 event id register + addressOffset: 368 + size: 32 + fields: + - name: CH43_EVT_ID + description: Configures ch43_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH43_TASK_ID + description: Channel43 task id register + addressOffset: 372 + size: 32 + fields: + - name: CH43_TASK_ID + description: Configures ch43_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH44_EVT_ID + description: Channel44 event id register + addressOffset: 376 + size: 32 + fields: + - name: CH44_EVT_ID + description: Configures ch44_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH44_TASK_ID + description: Channel44 task id register + addressOffset: 380 + size: 32 + fields: + - name: CH44_TASK_ID + description: Configures ch44_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH45_EVT_ID + description: Channel45 event id register + addressOffset: 384 + size: 32 + fields: + - name: CH45_EVT_ID + description: Configures ch45_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH45_TASK_ID + description: Channel45 task id register + addressOffset: 388 + size: 32 + fields: + - name: CH45_TASK_ID + description: Configures ch45_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH46_EVT_ID + description: Channel46 event id register + addressOffset: 392 + size: 32 + fields: + - name: CH46_EVT_ID + description: Configures ch46_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH46_TASK_ID + description: Channel46 task id register + addressOffset: 396 + size: 32 + fields: + - name: CH46_TASK_ID + description: Configures ch46_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH47_EVT_ID + description: Channel47 event id register + addressOffset: 400 + size: 32 + fields: + - name: CH47_EVT_ID + description: Configures ch47_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH47_TASK_ID + description: Channel47 task id register + addressOffset: 404 + size: 32 + fields: + - name: CH47_TASK_ID + description: Configures ch47_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH48_EVT_ID + description: Channel48 event id register + addressOffset: 408 + size: 32 + fields: + - name: CH48_EVT_ID + description: Configures ch48_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH48_TASK_ID + description: Channel48 task id register + addressOffset: 412 + size: 32 + fields: + - name: CH48_TASK_ID + description: Configures ch48_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH49_EVT_ID + description: Channel49 event id register + addressOffset: 416 + size: 32 + fields: + - name: CH49_EVT_ID + description: Configures ch49_evt_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CH49_TASK_ID + description: Channel49 task id register + addressOffset: 420 + size: 32 + fields: + - name: CH49_TASK_ID + description: Configures ch49_task_id + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: EVT_ST0 + description: Events trigger status register + addressOffset: 424 + size: 32 + fields: + - name: GPIO_EVT_CH0_RISE_EDGE_ST + description: "Represents GPIO_evt_ch0_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_CH1_RISE_EDGE_ST + description: "Represents GPIO_evt_ch1_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_CH2_RISE_EDGE_ST + description: "Represents GPIO_evt_ch2_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_CH3_RISE_EDGE_ST + description: "Represents GPIO_evt_ch3_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_CH4_RISE_EDGE_ST + description: "Represents GPIO_evt_ch4_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_CH5_RISE_EDGE_ST + description: "Represents GPIO_evt_ch5_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_CH6_RISE_EDGE_ST + description: "Represents GPIO_evt_ch6_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_CH7_RISE_EDGE_ST + description: "Represents GPIO_evt_ch7_rise_edge trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_CH0_FALL_EDGE_ST + description: "Represents GPIO_evt_ch0_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_CH1_FALL_EDGE_ST + description: "Represents GPIO_evt_ch1_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_CH2_FALL_EDGE_ST + description: "Represents GPIO_evt_ch2_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_CH3_FALL_EDGE_ST + description: "Represents GPIO_evt_ch3_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_CH4_FALL_EDGE_ST + description: "Represents GPIO_evt_ch4_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_CH5_FALL_EDGE_ST + description: "Represents GPIO_evt_ch5_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_CH6_FALL_EDGE_ST + description: "Represents GPIO_evt_ch6_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_CH7_FALL_EDGE_ST + description: "Represents GPIO_evt_ch7_fall_edge trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_CH0_ANY_EDGE_ST + description: "Represents GPIO_evt_ch0_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_CH1_ANY_EDGE_ST + description: "Represents GPIO_evt_ch1_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_CH2_ANY_EDGE_ST + description: "Represents GPIO_evt_ch2_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_CH3_ANY_EDGE_ST + description: "Represents GPIO_evt_ch3_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_CH4_ANY_EDGE_ST + description: "Represents GPIO_evt_ch4_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_CH5_ANY_EDGE_ST + description: "Represents GPIO_evt_ch5_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_CH6_ANY_EDGE_ST + description: "Represents GPIO_evt_ch6_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_CH7_ANY_EDGE_ST + description: "Represents GPIO_evt_ch7_any_edge trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_ZERO_DET_POS0_ST + description: "Represents GPIO_evt_zero_det_pos0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_ZERO_DET_NEG0_ST + description: "Represents GPIO_evt_zero_det_neg0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_ZERO_DET_POS1_ST + description: "Represents GPIO_evt_zero_det_pos1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: GPIO_EVT_ZERO_DET_NEG1_ST + description: "Represents GPIO_evt_zero_det_neg1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LEDC_EVT_DUTY_CHNG_END_CH0_ST + description: "Represents LEDC_evt_duty_chng_end_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LEDC_EVT_DUTY_CHNG_END_CH1_ST + description: "Represents LEDC_evt_duty_chng_end_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LEDC_EVT_DUTY_CHNG_END_CH2_ST + description: "Represents LEDC_evt_duty_chng_end_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LEDC_EVT_DUTY_CHNG_END_CH3_ST + description: "Represents LEDC_evt_duty_chng_end_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EVT_ST0_CLR + description: Events trigger status clear register + addressOffset: 428 + size: 32 + fields: + - name: GPIO_EVT_CH0_RISE_EDGE_ST_CLR + description: "Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_CH1_RISE_EDGE_ST_CLR + description: "Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_CH2_RISE_EDGE_ST_CLR + description: "Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_CH3_RISE_EDGE_ST_CLR + description: "Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_CH4_RISE_EDGE_ST_CLR + description: "Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_CH5_RISE_EDGE_ST_CLR + description: "Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_CH6_RISE_EDGE_ST_CLR + description: "Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_CH7_RISE_EDGE_ST_CLR + description: "Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_CH0_FALL_EDGE_ST_CLR + description: "Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_CH1_FALL_EDGE_ST_CLR + description: "Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_CH2_FALL_EDGE_ST_CLR + description: "Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_CH3_FALL_EDGE_ST_CLR + description: "Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_CH4_FALL_EDGE_ST_CLR + description: "Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_CH5_FALL_EDGE_ST_CLR + description: "Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_CH6_FALL_EDGE_ST_CLR + description: "Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_CH7_FALL_EDGE_ST_CLR + description: "Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_CH0_ANY_EDGE_ST_CLR + description: "Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_CH1_ANY_EDGE_ST_CLR + description: "Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_CH2_ANY_EDGE_ST_CLR + description: "Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_CH3_ANY_EDGE_ST_CLR + description: "Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_CH4_ANY_EDGE_ST_CLR + description: "Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_CH5_ANY_EDGE_ST_CLR + description: "Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_CH6_ANY_EDGE_ST_CLR + description: "Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_CH7_ANY_EDGE_ST_CLR + description: "Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_ZERO_DET_POS0_ST_CLR + description: "Configures whether or not to clear GPIO_evt_zero_det_pos0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_ZERO_DET_NEG0_ST_CLR + description: "Configures whether or not to clear GPIO_evt_zero_det_neg0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_ZERO_DET_POS1_ST_CLR + description: "Configures whether or not to clear GPIO_evt_zero_det_pos1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: GPIO_EVT_ZERO_DET_NEG1_ST_CLR + description: "Configures whether or not to clear GPIO_evt_zero_det_neg1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR + description: "Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR + description: "Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR + description: "Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR + description: "Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: EVT_ST1 + description: Events trigger status register + addressOffset: 432 + size: 32 + fields: + - name: LEDC_EVT_DUTY_CHNG_END_CH4_ST + description: "Represents LEDC_evt_duty_chng_end_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LEDC_EVT_DUTY_CHNG_END_CH5_ST + description: "Represents LEDC_evt_duty_chng_end_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: LEDC_EVT_DUTY_CHNG_END_CH6_ST + description: "Represents LEDC_evt_duty_chng_end_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: LEDC_EVT_DUTY_CHNG_END_CH7_ST + description: "Represents LEDC_evt_duty_chng_end_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: LEDC_EVT_OVF_CNT_PLS_CH0_ST + description: "Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: LEDC_EVT_OVF_CNT_PLS_CH1_ST + description: "Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: LEDC_EVT_OVF_CNT_PLS_CH2_ST + description: "Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: LEDC_EVT_OVF_CNT_PLS_CH3_ST + description: "Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: LEDC_EVT_OVF_CNT_PLS_CH4_ST + description: "Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: LEDC_EVT_OVF_CNT_PLS_CH5_ST + description: "Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: LEDC_EVT_OVF_CNT_PLS_CH6_ST + description: "Represents LEDC_evt_ovf_cnt_pls_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: LEDC_EVT_OVF_CNT_PLS_CH7_ST + description: "Represents LEDC_evt_ovf_cnt_pls_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: LEDC_EVT_TIME_OVF_TIMER0_ST + description: "Represents LEDC_evt_time_ovf_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: LEDC_EVT_TIME_OVF_TIMER1_ST + description: "Represents LEDC_evt_time_ovf_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: LEDC_EVT_TIME_OVF_TIMER2_ST + description: "Represents LEDC_evt_time_ovf_timer2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: LEDC_EVT_TIME_OVF_TIMER3_ST + description: "Represents LEDC_evt_time_ovf_timer3 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: LEDC_EVT_TIMER0_CMP_ST + description: "Represents LEDC_evt_timer0_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: LEDC_EVT_TIMER1_CMP_ST + description: "Represents LEDC_evt_timer1_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: LEDC_EVT_TIMER2_CMP_ST + description: "Represents LEDC_evt_timer2_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: LEDC_EVT_TIMER3_CMP_ST + description: "Represents LEDC_evt_timer3_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: TG0_EVT_CNT_CMP_TIMER0_ST + description: "Represents TG0_evt_cnt_cmp_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TG0_EVT_CNT_CMP_TIMER1_ST + description: "Represents TG0_evt_cnt_cmp_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: TG1_EVT_CNT_CMP_TIMER0_ST + description: "Represents TG1_evt_cnt_cmp_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TG1_EVT_CNT_CMP_TIMER1_ST + description: "Represents TG1_evt_cnt_cmp_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SYSTIMER_EVT_CNT_CMP0_ST + description: "Represents SYSTIMER_evt_cnt_cmp0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SYSTIMER_EVT_CNT_CMP1_ST + description: "Represents SYSTIMER_evt_cnt_cmp1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: SYSTIMER_EVT_CNT_CMP2_ST + description: "Represents SYSTIMER_evt_cnt_cmp2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_TIMER0_STOP_ST + description: "Represents MCPWM0_evt_timer0_stop trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_TIMER1_STOP_ST + description: "Represents MCPWM0_evt_timer1_stop trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_TIMER2_STOP_ST + description: "Represents MCPWM0_evt_timer2_stop trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_TIMER0_TEZ_ST + description: "Represents MCPWM0_evt_timer0_tez trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_TIMER1_TEZ_ST + description: "Represents MCPWM0_evt_timer1_tez trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EVT_ST1_CLR + description: Events trigger status clear register + addressOffset: 436 + size: 32 + fields: + - name: LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR + description: "Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR + description: "Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: LEDC_EVT_DUTY_CHNG_END_CH6_ST_CLR + description: "Configures whether or not to clear LEDC_evt_duty_chng_end_ch6 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: LEDC_EVT_DUTY_CHNG_END_CH7_ST_CLR + description: "Configures whether or not to clear LEDC_evt_duty_chng_end_ch7 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR + description: "Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR + description: "Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR + description: "Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR + description: "Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR + description: "Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR + description: "Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: LEDC_EVT_OVF_CNT_PLS_CH6_ST_CLR + description: "Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch6 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: LEDC_EVT_OVF_CNT_PLS_CH7_ST_CLR + description: "Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch7 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: LEDC_EVT_TIME_OVF_TIMER0_ST_CLR + description: "Configures whether or not to clear LEDC_evt_time_ovf_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: LEDC_EVT_TIME_OVF_TIMER1_ST_CLR + description: "Configures whether or not to clear LEDC_evt_time_ovf_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: LEDC_EVT_TIME_OVF_TIMER2_ST_CLR + description: "Configures whether or not to clear LEDC_evt_time_ovf_timer2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: LEDC_EVT_TIME_OVF_TIMER3_ST_CLR + description: "Configures whether or not to clear LEDC_evt_time_ovf_timer3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: LEDC_EVT_TIMER0_CMP_ST_CLR + description: "Configures whether or not to clear LEDC_evt_timer0_cmp trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: LEDC_EVT_TIMER1_CMP_ST_CLR + description: "Configures whether or not to clear LEDC_evt_timer1_cmp trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: LEDC_EVT_TIMER2_CMP_ST_CLR + description: "Configures whether or not to clear LEDC_evt_timer2_cmp trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: LEDC_EVT_TIMER3_CMP_ST_CLR + description: "Configures whether or not to clear LEDC_evt_timer3_cmp trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: TG0_EVT_CNT_CMP_TIMER0_ST_CLR + description: "Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: TG0_EVT_CNT_CMP_TIMER1_ST_CLR + description: "Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: TG1_EVT_CNT_CMP_TIMER0_ST_CLR + description: "Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: TG1_EVT_CNT_CMP_TIMER1_ST_CLR + description: "Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: SYSTIMER_EVT_CNT_CMP0_ST_CLR + description: "Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: SYSTIMER_EVT_CNT_CMP1_ST_CLR + description: "Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: SYSTIMER_EVT_CNT_CMP2_ST_CLR + description: "Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_TIMER0_STOP_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_timer0_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_TIMER1_STOP_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_timer1_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_TIMER2_STOP_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_timer2_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_TIMER0_TEZ_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_timer0_tez trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_TIMER1_TEZ_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_timer1_tez trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: EVT_ST2 + description: Events trigger status register + addressOffset: 440 + size: 32 + fields: + - name: MCPWM0_EVT_TIMER2_TEZ_ST + description: "Represents MCPWM0_evt_timer2_tez trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_TIMER0_TEP_ST + description: "Represents MCPWM0_evt_timer0_tep trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_TIMER1_TEP_ST + description: "Represents MCPWM0_evt_timer1_tep trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_TIMER2_TEP_ST + description: "Represents MCPWM0_evt_timer2_tep trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_OP0_TEA_ST + description: "Represents MCPWM0_evt_op0_tea trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_OP1_TEA_ST + description: "Represents MCPWM0_evt_op1_tea trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_OP2_TEA_ST + description: "Represents MCPWM0_evt_op2_tea trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_OP0_TEB_ST + description: "Represents MCPWM0_evt_op0_teb trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_OP1_TEB_ST + description: "Represents MCPWM0_evt_op1_teb trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_OP2_TEB_ST + description: "Represents MCPWM0_evt_op2_teb trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_F0_ST + description: "Represents MCPWM0_evt_f0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_F1_ST + description: "Represents MCPWM0_evt_f1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_F2_ST + description: "Represents MCPWM0_evt_f2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_F0_CLR_ST + description: "Represents MCPWM0_evt_f0_clr trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_F1_CLR_ST + description: "Represents MCPWM0_evt_f1_clr trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_F2_CLR_ST + description: "Represents MCPWM0_evt_f2_clr trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_TZ0_CBC_ST + description: "Represents MCPWM0_evt_tz0_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_TZ1_CBC_ST + description: "Represents MCPWM0_evt_tz1_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_TZ2_CBC_ST + description: "Represents MCPWM0_evt_tz2_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_TZ0_OST_ST + description: "Represents MCPWM0_evt_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_TZ1_OST_ST + description: "Represents MCPWM0_evt_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_TZ2_OST_ST + description: "Represents MCPWM0_evt_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_CAP0_ST + description: "Represents MCPWM0_evt_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_CAP1_ST + description: "Represents MCPWM0_evt_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_CAP2_ST + description: "Represents MCPWM0_evt_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_OP0_TEE1_ST + description: "Represents MCPWM0_evt_op0_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_OP1_TEE1_ST + description: "Represents MCPWM0_evt_op1_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_OP2_TEE1_ST + description: "Represents MCPWM0_evt_op2_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_OP0_TEE2_ST + description: "Represents MCPWM0_evt_op0_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_OP1_TEE2_ST + description: "Represents MCPWM0_evt_op1_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: MCPWM0_EVT_OP2_TEE2_ST + description: "Represents MCPWM0_evt_op2_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_TIMER0_STOP_ST + description: "Represents MCPWM1_evt_timer0_stop trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EVT_ST2_CLR + description: Events trigger status clear register + addressOffset: 444 + size: 32 + fields: + - name: MCPWM0_EVT_TIMER2_TEZ_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_timer2_tez trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_TIMER0_TEP_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_timer0_tep trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_TIMER1_TEP_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_timer1_tep trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_TIMER2_TEP_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_timer2_tep trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_OP0_TEA_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_op0_tea trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_OP1_TEA_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_op1_tea trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_OP2_TEA_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_op2_tea trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_OP0_TEB_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_op0_teb trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_OP1_TEB_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_op1_teb trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_OP2_TEB_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_op2_teb trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_F0_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_f0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_F1_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_f1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_F2_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_f2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_F0_CLR_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_f0_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_F1_CLR_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_f1_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_F2_CLR_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_f2_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_TZ0_CBC_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_tz0_cbc trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_TZ1_CBC_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_tz1_cbc trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_TZ2_CBC_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_tz2_cbc trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_TZ0_OST_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_tz0_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_TZ1_OST_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_tz1_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_TZ2_OST_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_tz2_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_CAP0_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_cap0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_CAP1_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_cap1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_CAP2_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_cap2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_OP0_TEE1_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_op0_tee1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_OP1_TEE1_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_op1_tee1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_OP2_TEE1_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_op2_tee1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_OP0_TEE2_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_op0_tee2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_OP1_TEE2_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_op1_tee2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: MCPWM0_EVT_OP2_TEE2_ST_CLR + description: "Configures whether or not to clear MCPWM0_evt_op2_tee2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_TIMER0_STOP_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_timer0_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: EVT_ST3 + description: Events trigger status register + addressOffset: 448 + size: 32 + fields: + - name: MCPWM1_EVT_TIMER1_STOP_ST + description: "Represents MCPWM1_evt_timer1_stop trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_TIMER2_STOP_ST + description: "Represents MCPWM1_evt_timer2_stop trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_TIMER0_TEZ_ST + description: "Represents MCPWM1_evt_timer0_tez trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_TIMER1_TEZ_ST + description: "Represents MCPWM1_evt_timer1_tez trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_TIMER2_TEZ_ST + description: "Represents MCPWM1_evt_timer2_tez trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_TIMER0_TEP_ST + description: "Represents MCPWM1_evt_timer0_tep trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_TIMER1_TEP_ST + description: "Represents MCPWM1_evt_timer1_tep trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_TIMER2_TEP_ST + description: "Represents MCPWM1_evt_timer2_tep trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_OP0_TEA_ST + description: "Represents MCPWM1_evt_op0_tea trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_OP1_TEA_ST + description: "Represents MCPWM1_evt_op1_tea trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_OP2_TEA_ST + description: "Represents MCPWM1_evt_op2_tea trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_OP0_TEB_ST + description: "Represents MCPWM1_evt_op0_teb trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_OP1_TEB_ST + description: "Represents MCPWM1_evt_op1_teb trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_OP2_TEB_ST + description: "Represents MCPWM1_evt_op2_teb trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_F0_ST + description: "Represents MCPWM1_evt_f0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_F1_ST + description: "Represents MCPWM1_evt_f1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_F2_ST + description: "Represents MCPWM1_evt_f2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_F0_CLR_ST + description: "Represents MCPWM1_evt_f0_clr trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_F1_CLR_ST + description: "Represents MCPWM1_evt_f1_clr trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_F2_CLR_ST + description: "Represents MCPWM1_evt_f2_clr trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_TZ0_CBC_ST + description: "Represents MCPWM1_evt_tz0_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_TZ1_CBC_ST + description: "Represents MCPWM1_evt_tz1_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_TZ2_CBC_ST + description: "Represents MCPWM1_evt_tz2_cbc trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_TZ0_OST_ST + description: "Represents MCPWM1_evt_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_TZ1_OST_ST + description: "Represents MCPWM1_evt_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_TZ2_OST_ST + description: "Represents MCPWM1_evt_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_CAP0_ST + description: "Represents MCPWM1_evt_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_CAP1_ST + description: "Represents MCPWM1_evt_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_CAP2_ST + description: "Represents MCPWM1_evt_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_OP0_TEE1_ST + description: "Represents MCPWM1_evt_op0_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_OP1_TEE1_ST + description: "Represents MCPWM1_evt_op1_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_OP2_TEE1_ST + description: "Represents MCPWM1_evt_op2_tee1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EVT_ST3_CLR + description: Events trigger status clear register + addressOffset: 452 + size: 32 + fields: + - name: MCPWM1_EVT_TIMER1_STOP_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_timer1_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_TIMER2_STOP_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_timer2_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_TIMER0_TEZ_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_timer0_tez trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_TIMER1_TEZ_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_timer1_tez trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_TIMER2_TEZ_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_timer2_tez trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_TIMER0_TEP_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_timer0_tep trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_TIMER1_TEP_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_timer1_tep trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_TIMER2_TEP_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_timer2_tep trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_OP0_TEA_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_op0_tea trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_OP1_TEA_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_op1_tea trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_OP2_TEA_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_op2_tea trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_OP0_TEB_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_op0_teb trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_OP1_TEB_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_op1_teb trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_OP2_TEB_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_op2_teb trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_F0_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_f0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_F1_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_f1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_F2_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_f2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_F0_CLR_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_f0_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_F1_CLR_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_f1_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_F2_CLR_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_f2_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_TZ0_CBC_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_tz0_cbc trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_TZ1_CBC_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_tz1_cbc trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_TZ2_CBC_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_tz2_cbc trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_TZ0_OST_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_tz0_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_TZ1_OST_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_tz1_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_TZ2_OST_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_tz2_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_CAP0_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_cap0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_CAP1_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_cap1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_CAP2_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_cap2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_OP0_TEE1_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_op0_tee1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_OP1_TEE1_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_op1_tee1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_OP2_TEE1_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_op2_tee1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: EVT_ST4 + description: Events trigger status register + addressOffset: 456 + size: 32 + fields: + - name: MCPWM1_EVT_OP0_TEE2_ST + description: "Represents MCPWM1_evt_op0_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_OP1_TEE2_ST + description: "Represents MCPWM1_evt_op1_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCPWM1_EVT_OP2_TEE2_ST + description: "Represents MCPWM1_evt_op2_tee2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ADC_EVT_CONV_CMPLT0_ST + description: "Represents ADC_evt_conv_cmplt0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ADC_EVT_EQ_ABOVE_THRESH0_ST + description: "Represents ADC_evt_eq_above_thresh0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ADC_EVT_EQ_ABOVE_THRESH1_ST + description: "Represents ADC_evt_eq_above_thresh1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: ADC_EVT_EQ_BELOW_THRESH0_ST + description: "Represents ADC_evt_eq_below_thresh0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: ADC_EVT_EQ_BELOW_THRESH1_ST + description: "Represents ADC_evt_eq_below_thresh1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: ADC_EVT_RESULT_DONE0_ST + description: "Represents ADC_evt_result_done0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ADC_EVT_STOPPED0_ST + description: "Represents ADC_evt_stopped0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: ADC_EVT_STARTED0_ST + description: "Represents ADC_evt_started0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: REGDMA_EVT_DONE0_ST + description: "Represents REGDMA_evt_done0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: REGDMA_EVT_DONE1_ST + description: "Represents REGDMA_evt_done1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: REGDMA_EVT_DONE2_ST + description: "Represents REGDMA_evt_done2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: REGDMA_EVT_DONE3_ST + description: "Represents REGDMA_evt_done3 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: REGDMA_EVT_ERR0_ST + description: "Represents REGDMA_evt_err0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: REGDMA_EVT_ERR1_ST + description: "Represents REGDMA_evt_err1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: REGDMA_EVT_ERR2_ST + description: "Represents REGDMA_evt_err2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: REGDMA_EVT_ERR3_ST + description: "Represents REGDMA_evt_err3 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TMPSNSR_EVT_OVER_LIMIT_ST + description: "Represents TMPSNSR_evt_over_limit trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: I2S0_EVT_RX_DONE_ST + description: "Represents I2S0_evt_rx_done trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: I2S0_EVT_TX_DONE_ST + description: "Represents I2S0_evt_tx_done trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: I2S0_EVT_X_WORDS_RECEIVED_ST + description: "Represents I2S0_evt_x_words_received trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: I2S0_EVT_X_WORDS_SENT_ST + description: "Represents I2S0_evt_x_words_sent trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: I2S1_EVT_RX_DONE_ST + description: "Represents I2S1_evt_rx_done trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: I2S1_EVT_TX_DONE_ST + description: "Represents I2S1_evt_tx_done trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: I2S1_EVT_X_WORDS_RECEIVED_ST + description: "Represents I2S1_evt_x_words_received trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: I2S1_EVT_X_WORDS_SENT_ST + description: "Represents I2S1_evt_x_words_sent trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: I2S2_EVT_RX_DONE_ST + description: "Represents I2S2_evt_rx_done trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: I2S2_EVT_TX_DONE_ST + description: "Represents I2S2_evt_tx_done trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: I2S2_EVT_X_WORDS_RECEIVED_ST + description: "Represents I2S2_evt_x_words_received trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: I2S2_EVT_X_WORDS_SENT_ST + description: "Represents I2S2_evt_x_words_sent trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EVT_ST4_CLR + description: Events trigger status clear register + addressOffset: 460 + size: 32 + fields: + - name: MCPWM1_EVT_OP0_TEE2_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_op0_tee2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_OP1_TEE2_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_op1_tee2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: MCPWM1_EVT_OP2_TEE2_ST_CLR + description: "Configures whether or not to clear MCPWM1_evt_op2_tee2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: ADC_EVT_CONV_CMPLT0_ST_CLR + description: "Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR + description: "Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR + description: "Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: ADC_EVT_EQ_BELOW_THRESH0_ST_CLR + description: "Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: ADC_EVT_EQ_BELOW_THRESH1_ST_CLR + description: "Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: ADC_EVT_RESULT_DONE0_ST_CLR + description: "Configures whether or not to clear ADC_evt_result_done0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: ADC_EVT_STOPPED0_ST_CLR + description: "Configures whether or not to clear ADC_evt_stopped0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: ADC_EVT_STARTED0_ST_CLR + description: "Configures whether or not to clear ADC_evt_started0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: REGDMA_EVT_DONE0_ST_CLR + description: "Configures whether or not to clear REGDMA_evt_done0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: REGDMA_EVT_DONE1_ST_CLR + description: "Configures whether or not to clear REGDMA_evt_done1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: REGDMA_EVT_DONE2_ST_CLR + description: "Configures whether or not to clear REGDMA_evt_done2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: REGDMA_EVT_DONE3_ST_CLR + description: "Configures whether or not to clear REGDMA_evt_done3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: REGDMA_EVT_ERR0_ST_CLR + description: "Configures whether or not to clear REGDMA_evt_err0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: REGDMA_EVT_ERR1_ST_CLR + description: "Configures whether or not to clear REGDMA_evt_err1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: REGDMA_EVT_ERR2_ST_CLR + description: "Configures whether or not to clear REGDMA_evt_err2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: REGDMA_EVT_ERR3_ST_CLR + description: "Configures whether or not to clear REGDMA_evt_err3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: TMPSNSR_EVT_OVER_LIMIT_ST_CLR + description: "Configures whether or not to clear TMPSNSR_evt_over_limit trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: I2S0_EVT_RX_DONE_ST_CLR + description: "Configures whether or not to clear I2S0_evt_rx_done trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: I2S0_EVT_TX_DONE_ST_CLR + description: "Configures whether or not to clear I2S0_evt_tx_done trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: I2S0_EVT_X_WORDS_RECEIVED_ST_CLR + description: "Configures whether or not to clear I2S0_evt_x_words_received trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: I2S0_EVT_X_WORDS_SENT_ST_CLR + description: "Configures whether or not to clear I2S0_evt_x_words_sent trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: I2S1_EVT_RX_DONE_ST_CLR + description: "Configures whether or not to clear I2S1_evt_rx_done trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: I2S1_EVT_TX_DONE_ST_CLR + description: "Configures whether or not to clear I2S1_evt_tx_done trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: I2S1_EVT_X_WORDS_RECEIVED_ST_CLR + description: "Configures whether or not to clear I2S1_evt_x_words_received trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: I2S1_EVT_X_WORDS_SENT_ST_CLR + description: "Configures whether or not to clear I2S1_evt_x_words_sent trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: I2S2_EVT_RX_DONE_ST_CLR + description: "Configures whether or not to clear I2S2_evt_rx_done trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: I2S2_EVT_TX_DONE_ST_CLR + description: "Configures whether or not to clear I2S2_evt_tx_done trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: I2S2_EVT_X_WORDS_RECEIVED_ST_CLR + description: "Configures whether or not to clear I2S2_evt_x_words_received trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: I2S2_EVT_X_WORDS_SENT_ST_CLR + description: "Configures whether or not to clear I2S2_evt_x_words_sent trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: EVT_ST5 + description: Events trigger status register + addressOffset: 464 + size: 32 + fields: + - name: ULP_EVT_ERR_INTR_ST + description: "Represents ULP_evt_err_intr trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ULP_EVT_HALT_ST + description: "Represents ULP_evt_halt trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ULP_EVT_START_INTR_ST + description: "Represents ULP_evt_start_intr trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RTC_EVT_TICK_ST + description: "Represents RTC_evt_tick trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RTC_EVT_OVF_ST + description: "Represents RTC_evt_ovf trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RTC_EVT_CMP_ST + description: "Represents RTC_evt_cmp trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_IN_DONE_CH0_ST + description: "Represents PDMA_AHB_evt_in_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_IN_DONE_CH1_ST + description: "Represents PDMA_AHB_evt_in_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_IN_DONE_CH2_ST + description: "Represents PDMA_AHB_evt_in_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST + description: "Represents PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST + description: "Represents PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST + description: "Represents PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST + description: "Represents PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST + description: "Represents PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST + description: "Represents PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST + description: "Represents PDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST + description: "Represents PDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST + description: "Represents PDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_OUT_DONE_CH0_ST + description: "Represents PDMA_AHB_evt_out_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_OUT_DONE_CH1_ST + description: "Represents PDMA_AHB_evt_out_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_OUT_DONE_CH2_ST + description: "Represents PDMA_AHB_evt_out_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_OUT_EOF_CH0_ST + description: "Represents PDMA_AHB_evt_out_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_OUT_EOF_CH1_ST + description: "Represents PDMA_AHB_evt_out_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_OUT_EOF_CH2_ST + description: "Represents PDMA_AHB_evt_out_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST + description: "Represents PDMA_AHB_evt_out_total_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST + description: "Represents PDMA_AHB_evt_out_total_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST + description: "Represents PDMA_AHB_evt_out_total_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST + description: "Represents PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST + description: "Represents PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST + description: "Represents PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST + description: "Represents PDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST + description: "Represents PDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EVT_ST5_CLR + description: Events trigger status clear register + addressOffset: 468 + size: 32 + fields: + - name: ULP_EVT_ERR_INTR_ST_CLR + description: "Configures whether or not to clear ULP_evt_err_intr trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ULP_EVT_HALT_ST_CLR + description: "Configures whether or not to clear ULP_evt_halt trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: ULP_EVT_START_INTR_ST_CLR + description: "Configures whether or not to clear ULP_evt_start_intr trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: RTC_EVT_TICK_ST_CLR + description: "Configures whether or not to clear RTC_evt_tick trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: RTC_EVT_OVF_ST_CLR + description: "Configures whether or not to clear RTC_evt_ovf trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: RTC_EVT_CMP_ST_CLR + description: "Configures whether or not to clear RTC_evt_cmp trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_IN_DONE_CH0_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_in_done_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_IN_DONE_CH1_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_in_done_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_IN_DONE_CH2_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_in_done_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_in_suc_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_in_fifo_empty_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_in_fifo_full_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_out_done_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_out_done_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_out_done_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_out_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_out_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_out_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_out_total_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_out_fifo_empty_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: EVT_ST6 + description: Events trigger status register + addressOffset: 472 + size: 32 + fields: + - name: PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST + description: "Represents PDMA_AHB_evt_out_fifo_full_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_IN_DONE_CH0_ST + description: "Represents PDMA_AXI_evt_in_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_IN_DONE_CH1_ST + description: "Represents PDMA_AXI_evt_in_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_IN_DONE_CH2_ST + description: "Represents PDMA_AXI_evt_in_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST + description: "Represents PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST + description: "Represents PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST + description: "Represents PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST + description: "Represents PDMA_AXI_evt_in_fifo_empty_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST + description: "Represents PDMA_AXI_evt_in_fifo_empty_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST + description: "Represents PDMA_AXI_evt_in_fifo_empty_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST + description: "Represents PDMA_AXI_evt_in_fifo_full_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST + description: "Represents PDMA_AXI_evt_in_fifo_full_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST + description: "Represents PDMA_AXI_evt_in_fifo_full_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_OUT_DONE_CH0_ST + description: "Represents PDMA_AXI_evt_out_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_OUT_DONE_CH1_ST + description: "Represents PDMA_AXI_evt_out_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_OUT_DONE_CH2_ST + description: "Represents PDMA_AXI_evt_out_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_OUT_EOF_CH0_ST + description: "Represents PDMA_AXI_evt_out_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_OUT_EOF_CH1_ST + description: "Represents PDMA_AXI_evt_out_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_OUT_EOF_CH2_ST + description: "Represents PDMA_AXI_evt_out_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST + description: "Represents PDMA_AXI_evt_out_total_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST + description: "Represents PDMA_AXI_evt_out_total_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST + description: "Represents PDMA_AXI_evt_out_total_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST + description: "Represents PDMA_AXI_evt_out_fifo_empty_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST + description: "Represents PDMA_AXI_evt_out_fifo_empty_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST + description: "Represents PDMA_AXI_evt_out_fifo_empty_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST + description: "Represents PDMA_AXI_evt_out_fifo_full_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST + description: "Represents PDMA_AXI_evt_out_fifo_full_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST + description: "Represents PDMA_AXI_evt_out_fifo_full_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: PMU_EVT_SLEEP_WEEKUP_ST + description: "Represents PMU_evt_sleep_weekup trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DMA2D_EVT_IN_DONE_CH0_ST + description: "Represents DMA2D_evt_in_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: DMA2D_EVT_IN_DONE_CH1_ST + description: "Represents DMA2D_evt_in_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DMA2D_EVT_IN_SUC_EOF_CH0_ST + description: "Represents DMA2D_evt_in_suc_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EVT_ST6_CLR + description: Events trigger status clear register + addressOffset: 476 + size: 32 + fields: + - name: PDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_evt_out_fifo_full_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_IN_DONE_CH0_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_in_done_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_IN_DONE_CH1_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_in_done_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_IN_DONE_CH2_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_in_done_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_IN_SUC_EOF_CH0_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_IN_SUC_EOF_CH1_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_IN_SUC_EOF_CH2_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_in_suc_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_IN_FIFO_EMPTY_CH0_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_IN_FIFO_EMPTY_CH1_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_IN_FIFO_EMPTY_CH2_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_in_fifo_empty_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_IN_FIFO_FULL_CH0_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_IN_FIFO_FULL_CH1_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_IN_FIFO_FULL_CH2_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_in_fifo_full_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_OUT_DONE_CH0_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_out_done_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_OUT_DONE_CH1_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_out_done_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_OUT_DONE_CH2_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_out_done_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_OUT_EOF_CH0_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_out_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_OUT_EOF_CH1_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_out_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_OUT_EOF_CH2_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_out_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_OUT_TOTAL_EOF_CH0_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_OUT_TOTAL_EOF_CH1_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_OUT_TOTAL_EOF_CH2_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_out_total_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_out_fifo_empty_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_OUT_FIFO_FULL_CH0_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_OUT_FIFO_FULL_CH1_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_EVT_OUT_FIFO_FULL_CH2_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_evt_out_fifo_full_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: PMU_EVT_SLEEP_WEEKUP_ST_CLR + description: "Configures whether or not to clear PMU_evt_sleep_weekup trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DMA2D_EVT_IN_DONE_CH0_ST_CLR + description: "Configures whether or not to clear DMA2D_evt_in_done_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: DMA2D_EVT_IN_DONE_CH1_ST_CLR + description: "Configures whether or not to clear DMA2D_evt_in_done_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: DMA2D_EVT_IN_SUC_EOF_CH0_ST_CLR + description: "Configures whether or not to clear DMA2D_evt_in_suc_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: EVT_ST7 + description: Events trigger status register + addressOffset: 480 + size: 32 + fields: + - name: DMA2D_EVT_IN_SUC_EOF_CH1_ST + description: "Represents DMA2D_evt_in_suc_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DMA2D_EVT_OUT_DONE_CH0_ST + description: "Represents DMA2D_evt_out_done_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DMA2D_EVT_OUT_DONE_CH1_ST + description: "Represents DMA2D_evt_out_done_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DMA2D_EVT_OUT_DONE_CH2_ST + description: "Represents DMA2D_evt_out_done_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DMA2D_EVT_OUT_EOF_CH0_ST + description: "Represents DMA2D_evt_out_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DMA2D_EVT_OUT_EOF_CH1_ST + description: "Represents DMA2D_evt_out_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DMA2D_EVT_OUT_EOF_CH2_ST + description: "Represents DMA2D_evt_out_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST + description: "Represents DMA2D_evt_out_total_eof_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST + description: "Represents DMA2D_evt_out_total_eof_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST + description: "Represents DMA2D_evt_out_total_eof_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: EVT_ST7_CLR + description: Events trigger status clear register + addressOffset: 484 + size: 32 + fields: + - name: DMA2D_EVT_IN_SUC_EOF_CH1_ST_CLR + description: "Configures whether or not to clear DMA2D_evt_in_suc_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: DMA2D_EVT_OUT_DONE_CH0_ST_CLR + description: "Configures whether or not to clear DMA2D_evt_out_done_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DMA2D_EVT_OUT_DONE_CH1_ST_CLR + description: "Configures whether or not to clear DMA2D_evt_out_done_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: DMA2D_EVT_OUT_DONE_CH2_ST_CLR + description: "Configures whether or not to clear DMA2D_evt_out_done_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: DMA2D_EVT_OUT_EOF_CH0_ST_CLR + description: "Configures whether or not to clear DMA2D_evt_out_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: DMA2D_EVT_OUT_EOF_CH1_ST_CLR + description: "Configures whether or not to clear DMA2D_evt_out_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: DMA2D_EVT_OUT_EOF_CH2_ST_CLR + description: "Configures whether or not to clear DMA2D_evt_out_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: DMA2D_EVT_OUT_TOTAL_EOF_CH0_ST_CLR + description: "Configures whether or not to clear DMA2D_evt_out_total_eof_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: DMA2D_EVT_OUT_TOTAL_EOF_CH1_ST_CLR + description: "Configures whether or not to clear DMA2D_evt_out_total_eof_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: DMA2D_EVT_OUT_TOTAL_EOF_CH2_ST_CLR + description: "Configures whether or not to clear DMA2D_evt_out_total_eof_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 9 + bitWidth: 1 + access: write-only + - register: + name: TASK_ST0 + description: Tasks trigger status register + addressOffset: 488 + size: 32 + fields: + - name: GPIO_TASK_CH0_SET_ST + description: "Represents GPIO_task_ch0_set trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: GPIO_TASK_CH1_SET_ST + description: "Represents GPIO_task_ch1_set trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: GPIO_TASK_CH2_SET_ST + description: "Represents GPIO_task_ch2_set trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: GPIO_TASK_CH3_SET_ST + description: "Represents GPIO_task_ch3_set trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: GPIO_TASK_CH4_SET_ST + description: "Represents GPIO_task_ch4_set trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: GPIO_TASK_CH5_SET_ST + description: "Represents GPIO_task_ch5_set trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: GPIO_TASK_CH6_SET_ST + description: "Represents GPIO_task_ch6_set trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: GPIO_TASK_CH7_SET_ST + description: "Represents GPIO_task_ch7_set trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: GPIO_TASK_CH0_CLEAR_ST + description: "Represents GPIO_task_ch0_clear trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: GPIO_TASK_CH1_CLEAR_ST + description: "Represents GPIO_task_ch1_clear trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: GPIO_TASK_CH2_CLEAR_ST + description: "Represents GPIO_task_ch2_clear trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GPIO_TASK_CH3_CLEAR_ST + description: "Represents GPIO_task_ch3_clear trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: GPIO_TASK_CH4_CLEAR_ST + description: "Represents GPIO_task_ch4_clear trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: GPIO_TASK_CH5_CLEAR_ST + description: "Represents GPIO_task_ch5_clear trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: GPIO_TASK_CH6_CLEAR_ST + description: "Represents GPIO_task_ch6_clear trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: GPIO_TASK_CH7_CLEAR_ST + description: "Represents GPIO_task_ch7_clear trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: GPIO_TASK_CH0_TOGGLE_ST + description: "Represents GPIO_task_ch0_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: GPIO_TASK_CH1_TOGGLE_ST + description: "Represents GPIO_task_ch1_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: GPIO_TASK_CH2_TOGGLE_ST + description: "Represents GPIO_task_ch2_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: GPIO_TASK_CH3_TOGGLE_ST + description: "Represents GPIO_task_ch3_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: GPIO_TASK_CH4_TOGGLE_ST + description: "Represents GPIO_task_ch4_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: GPIO_TASK_CH5_TOGGLE_ST + description: "Represents GPIO_task_ch5_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: GPIO_TASK_CH6_TOGGLE_ST + description: "Represents GPIO_task_ch6_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: GPIO_TASK_CH7_TOGGLE_ST + description: "Represents GPIO_task_ch7_toggle trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_TIMER0_RES_UPDATE_ST + description: "Represents LEDC_task_timer0_res_update trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_TIMER1_RES_UPDATE_ST + description: "Represents LEDC_task_timer1_res_update trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_TIMER2_RES_UPDATE_ST + description: "Represents LEDC_task_timer2_res_update trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_TIMER3_RES_UPDATE_ST + description: "Represents LEDC_task_timer3_res_update trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST + description: "Represents LEDC_task_duty_scale_update_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST + description: "Represents LEDC_task_duty_scale_update_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST + description: "Represents LEDC_task_duty_scale_update_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST + description: "Represents LEDC_task_duty_scale_update_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TASK_ST0_CLR + description: Tasks trigger status clear register + addressOffset: 492 + size: 32 + fields: + - name: GPIO_TASK_CH0_SET_ST_CLR + description: "Configures whether or not to clear GPIO_task_ch0_set trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: GPIO_TASK_CH1_SET_ST_CLR + description: "Configures whether or not to clear GPIO_task_ch1_set trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: GPIO_TASK_CH2_SET_ST_CLR + description: "Configures whether or not to clear GPIO_task_ch2_set trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: GPIO_TASK_CH3_SET_ST_CLR + description: "Configures whether or not to clear GPIO_task_ch3_set trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: GPIO_TASK_CH4_SET_ST_CLR + description: "Configures whether or not to clear GPIO_task_ch4_set trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: GPIO_TASK_CH5_SET_ST_CLR + description: "Configures whether or not to clear GPIO_task_ch5_set trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: GPIO_TASK_CH6_SET_ST_CLR + description: "Configures whether or not to clear GPIO_task_ch6_set trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: GPIO_TASK_CH7_SET_ST_CLR + description: "Configures whether or not to clear GPIO_task_ch7_set trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: GPIO_TASK_CH0_CLEAR_ST_CLR + description: "Configures whether or not to clear GPIO_task_ch0_clear trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: GPIO_TASK_CH1_CLEAR_ST_CLR + description: "Configures whether or not to clear GPIO_task_ch1_clear trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: GPIO_TASK_CH2_CLEAR_ST_CLR + description: "Configures whether or not to clear GPIO_task_ch2_clear trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: GPIO_TASK_CH3_CLEAR_ST_CLR + description: "Configures whether or not to clear GPIO_task_ch3_clear trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: GPIO_TASK_CH4_CLEAR_ST_CLR + description: "Configures whether or not to clear GPIO_task_ch4_clear trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: GPIO_TASK_CH5_CLEAR_ST_CLR + description: "Configures whether or not to clear GPIO_task_ch5_clear trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: GPIO_TASK_CH6_CLEAR_ST_CLR + description: "Configures whether or not to clear GPIO_task_ch6_clear trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: GPIO_TASK_CH7_CLEAR_ST_CLR + description: "Configures whether or not to clear GPIO_task_ch7_clear trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: GPIO_TASK_CH0_TOGGLE_ST_CLR + description: "Configures whether or not to clear GPIO_task_ch0_toggle trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: GPIO_TASK_CH1_TOGGLE_ST_CLR + description: "Configures whether or not to clear GPIO_task_ch1_toggle trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: GPIO_TASK_CH2_TOGGLE_ST_CLR + description: "Configures whether or not to clear GPIO_task_ch2_toggle trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: GPIO_TASK_CH3_TOGGLE_ST_CLR + description: "Configures whether or not to clear GPIO_task_ch3_toggle trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: GPIO_TASK_CH4_TOGGLE_ST_CLR + description: "Configures whether or not to clear GPIO_task_ch4_toggle trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: GPIO_TASK_CH5_TOGGLE_ST_CLR + description: "Configures whether or not to clear GPIO_task_ch5_toggle trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: GPIO_TASK_CH6_TOGGLE_ST_CLR + description: "Configures whether or not to clear GPIO_task_ch6_toggle trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: GPIO_TASK_CH7_TOGGLE_ST_CLR + description: "Configures whether or not to clear GPIO_task_ch7_toggle trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR + description: "Configures whether or not to clear LEDC_task_timer0_res_update trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR + description: "Configures whether or not to clear LEDC_task_timer1_res_update trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR + description: "Configures whether or not to clear LEDC_task_timer2_res_update trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR + description: "Configures whether or not to clear LEDC_task_timer3_res_update trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR + description: "Configures whether or not to clear LEDC_task_duty_scale_update_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR + description: "Configures whether or not to clear LEDC_task_duty_scale_update_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR + description: "Configures whether or not to clear LEDC_task_duty_scale_update_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR + description: "Configures whether or not to clear LEDC_task_duty_scale_update_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: TASK_ST1 + description: Tasks trigger status register + addressOffset: 496 + size: 32 + fields: + - name: LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST + description: "Represents LEDC_task_duty_scale_update_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST + description: "Represents LEDC_task_duty_scale_update_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST + description: "Represents LEDC_task_duty_scale_update_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST + description: "Represents LEDC_task_duty_scale_update_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_TIMER0_CAP_ST + description: "Represents LEDC_task_timer0_cap trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_TIMER1_CAP_ST + description: "Represents LEDC_task_timer1_cap trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_TIMER2_CAP_ST + description: "Represents LEDC_task_timer2_cap trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_TIMER3_CAP_ST + description: "Represents LEDC_task_timer3_cap trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_SIG_OUT_DIS_CH0_ST + description: "Represents LEDC_task_sig_out_dis_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_SIG_OUT_DIS_CH1_ST + description: "Represents LEDC_task_sig_out_dis_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_SIG_OUT_DIS_CH2_ST + description: "Represents LEDC_task_sig_out_dis_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_SIG_OUT_DIS_CH3_ST + description: "Represents LEDC_task_sig_out_dis_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_SIG_OUT_DIS_CH4_ST + description: "Represents LEDC_task_sig_out_dis_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_SIG_OUT_DIS_CH5_ST + description: "Represents LEDC_task_sig_out_dis_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_SIG_OUT_DIS_CH6_ST + description: "Represents LEDC_task_sig_out_dis_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_SIG_OUT_DIS_CH7_ST + description: "Represents LEDC_task_sig_out_dis_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_OVF_CNT_RST_CH0_ST + description: "Represents LEDC_task_ovf_cnt_rst_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_OVF_CNT_RST_CH1_ST + description: "Represents LEDC_task_ovf_cnt_rst_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_OVF_CNT_RST_CH2_ST + description: "Represents LEDC_task_ovf_cnt_rst_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_OVF_CNT_RST_CH3_ST + description: "Represents LEDC_task_ovf_cnt_rst_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_OVF_CNT_RST_CH4_ST + description: "Represents LEDC_task_ovf_cnt_rst_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_OVF_CNT_RST_CH5_ST + description: "Represents LEDC_task_ovf_cnt_rst_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_OVF_CNT_RST_CH6_ST + description: "Represents LEDC_task_ovf_cnt_rst_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_OVF_CNT_RST_CH7_ST + description: "Represents LEDC_task_ovf_cnt_rst_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_TIMER0_RST_ST + description: "Represents LEDC_task_timer0_rst trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_TIMER1_RST_ST + description: "Represents LEDC_task_timer1_rst trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_TIMER2_RST_ST + description: "Represents LEDC_task_timer2_rst trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_TIMER3_RST_ST + description: "Represents LEDC_task_timer3_rst trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_TIMER0_RESUME_ST + description: "Represents LEDC_task_timer0_resume trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_TIMER1_RESUME_ST + description: "Represents LEDC_task_timer1_resume trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_TIMER2_RESUME_ST + description: "Represents LEDC_task_timer2_resume trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_TIMER3_RESUME_ST + description: "Represents LEDC_task_timer3_resume trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TASK_ST1_CLR + description: Tasks trigger status clear register + addressOffset: 500 + size: 32 + fields: + - name: LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR + description: "Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR + description: "Configures whether or not to clear LEDC_task_duty_scale_update_ch5 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_DUTY_SCALE_UPDATE_CH6_ST_CLR + description: "Configures whether or not to clear LEDC_task_duty_scale_update_ch6 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_DUTY_SCALE_UPDATE_CH7_ST_CLR + description: "Configures whether or not to clear LEDC_task_duty_scale_update_ch7 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_TIMER0_CAP_ST_CLR + description: "Configures whether or not to clear LEDC_task_timer0_cap trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_TIMER1_CAP_ST_CLR + description: "Configures whether or not to clear LEDC_task_timer1_cap trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_TIMER2_CAP_ST_CLR + description: "Configures whether or not to clear LEDC_task_timer2_cap trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_TIMER3_CAP_ST_CLR + description: "Configures whether or not to clear LEDC_task_timer3_cap trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR + description: "Configures whether or not to clear LEDC_task_sig_out_dis_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR + description: "Configures whether or not to clear LEDC_task_sig_out_dis_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR + description: "Configures whether or not to clear LEDC_task_sig_out_dis_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR + description: "Configures whether or not to clear LEDC_task_sig_out_dis_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR + description: "Configures whether or not to clear LEDC_task_sig_out_dis_ch4 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR + description: "Configures whether or not to clear LEDC_task_sig_out_dis_ch5 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_SIG_OUT_DIS_CH6_ST_CLR + description: "Configures whether or not to clear LEDC_task_sig_out_dis_ch6 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_SIG_OUT_DIS_CH7_ST_CLR + description: "Configures whether or not to clear LEDC_task_sig_out_dis_ch7 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR + description: "Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR + description: "Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR + description: "Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR + description: "Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR + description: "Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR + description: "Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_OVF_CNT_RST_CH6_ST_CLR + description: "Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch6 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_OVF_CNT_RST_CH7_ST_CLR + description: "Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch7 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_TIMER0_RST_ST_CLR + description: "Configures whether or not to clear LEDC_task_timer0_rst trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_TIMER1_RST_ST_CLR + description: "Configures whether or not to clear LEDC_task_timer1_rst trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_TIMER2_RST_ST_CLR + description: "Configures whether or not to clear LEDC_task_timer2_rst trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_TIMER3_RST_ST_CLR + description: "Configures whether or not to clear LEDC_task_timer3_rst trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_TIMER0_RESUME_ST_CLR + description: "Configures whether or not to clear LEDC_task_timer0_resume trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_TIMER1_RESUME_ST_CLR + description: "Configures whether or not to clear LEDC_task_timer1_resume trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_TIMER2_RESUME_ST_CLR + description: "Configures whether or not to clear LEDC_task_timer2_resume trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_TIMER3_RESUME_ST_CLR + description: "Configures whether or not to clear LEDC_task_timer3_resume trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: TASK_ST2 + description: Tasks trigger status register + addressOffset: 504 + size: 32 + fields: + - name: LEDC_TASK_TIMER0_PAUSE_ST + description: "Represents LEDC_task_timer0_pause trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_TIMER1_PAUSE_ST + description: "Represents LEDC_task_timer1_pause trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_TIMER2_PAUSE_ST + description: "Represents LEDC_task_timer2_pause trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_TIMER3_PAUSE_ST + description: "Represents LEDC_task_timer3_pause trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_GAMMA_RESTART_CH0_ST + description: "Represents LEDC_task_gamma_restart_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_GAMMA_RESTART_CH1_ST + description: "Represents LEDC_task_gamma_restart_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_GAMMA_RESTART_CH2_ST + description: "Represents LEDC_task_gamma_restart_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_GAMMA_RESTART_CH3_ST + description: "Represents LEDC_task_gamma_restart_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_GAMMA_RESTART_CH4_ST + description: "Represents LEDC_task_gamma_restart_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_GAMMA_RESTART_CH5_ST + description: "Represents LEDC_task_gamma_restart_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_GAMMA_RESTART_CH6_ST + description: "Represents LEDC_task_gamma_restart_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_GAMMA_RESTART_CH7_ST + description: "Represents LEDC_task_gamma_restart_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_GAMMA_PAUSE_CH0_ST + description: "Represents LEDC_task_gamma_pause_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_GAMMA_PAUSE_CH1_ST + description: "Represents LEDC_task_gamma_pause_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_GAMMA_PAUSE_CH2_ST + description: "Represents LEDC_task_gamma_pause_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_GAMMA_PAUSE_CH3_ST + description: "Represents LEDC_task_gamma_pause_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_GAMMA_PAUSE_CH4_ST + description: "Represents LEDC_task_gamma_pause_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_GAMMA_PAUSE_CH5_ST + description: "Represents LEDC_task_gamma_pause_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_GAMMA_PAUSE_CH6_ST + description: "Represents LEDC_task_gamma_pause_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_GAMMA_PAUSE_CH7_ST + description: "Represents LEDC_task_gamma_pause_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_GAMMA_RESUME_CH0_ST + description: "Represents LEDC_task_gamma_resume_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_GAMMA_RESUME_CH1_ST + description: "Represents LEDC_task_gamma_resume_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_GAMMA_RESUME_CH2_ST + description: "Represents LEDC_task_gamma_resume_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_GAMMA_RESUME_CH3_ST + description: "Represents LEDC_task_gamma_resume_ch3 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_GAMMA_RESUME_CH4_ST + description: "Represents LEDC_task_gamma_resume_ch4 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_GAMMA_RESUME_CH5_ST + description: "Represents LEDC_task_gamma_resume_ch5 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_GAMMA_RESUME_CH6_ST + description: "Represents LEDC_task_gamma_resume_ch6 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LEDC_TASK_GAMMA_RESUME_CH7_ST + description: "Represents LEDC_task_gamma_resume_ch7 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: TG0_TASK_CNT_START_TIMER0_ST + description: "Represents TG0_task_cnt_start_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: TG0_TASK_ALARM_START_TIMER0_ST + description: "Represents TG0_task_alarm_start_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TG0_TASK_CNT_STOP_TIMER0_ST + description: "Represents TG0_task_cnt_stop_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TG0_TASK_CNT_RELOAD_TIMER0_ST + description: "Represents TG0_task_cnt_reload_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TASK_ST2_CLR + description: Tasks trigger status clear register + addressOffset: 508 + size: 32 + fields: + - name: LEDC_TASK_TIMER0_PAUSE_ST_CLR + description: "Configures whether or not to clear LEDC_task_timer0_pause trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_TIMER1_PAUSE_ST_CLR + description: "Configures whether or not to clear LEDC_task_timer1_pause trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_TIMER2_PAUSE_ST_CLR + description: "Configures whether or not to clear LEDC_task_timer2_pause trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_TIMER3_PAUSE_ST_CLR + description: "Configures whether or not to clear LEDC_task_timer3_pause trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR + description: "Configures whether or not to clear LEDC_task_gamma_restart_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR + description: "Configures whether or not to clear LEDC_task_gamma_restart_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR + description: "Configures whether or not to clear LEDC_task_gamma_restart_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR + description: "Configures whether or not to clear LEDC_task_gamma_restart_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR + description: "Configures whether or not to clear LEDC_task_gamma_restart_ch4 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR + description: "Configures whether or not to clear LEDC_task_gamma_restart_ch5 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_GAMMA_RESTART_CH6_ST_CLR + description: "Configures whether or not to clear LEDC_task_gamma_restart_ch6 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_GAMMA_RESTART_CH7_ST_CLR + description: "Configures whether or not to clear LEDC_task_gamma_restart_ch7 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR + description: "Configures whether or not to clear LEDC_task_gamma_pause_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR + description: "Configures whether or not to clear LEDC_task_gamma_pause_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR + description: "Configures whether or not to clear LEDC_task_gamma_pause_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR + description: "Configures whether or not to clear LEDC_task_gamma_pause_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR + description: "Configures whether or not to clear LEDC_task_gamma_pause_ch4 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR + description: "Configures whether or not to clear LEDC_task_gamma_pause_ch5 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_GAMMA_PAUSE_CH6_ST_CLR + description: "Configures whether or not to clear LEDC_task_gamma_pause_ch6 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_GAMMA_PAUSE_CH7_ST_CLR + description: "Configures whether or not to clear LEDC_task_gamma_pause_ch7 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR + description: "Configures whether or not to clear LEDC_task_gamma_resume_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR + description: "Configures whether or not to clear LEDC_task_gamma_resume_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR + description: "Configures whether or not to clear LEDC_task_gamma_resume_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR + description: "Configures whether or not to clear LEDC_task_gamma_resume_ch3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR + description: "Configures whether or not to clear LEDC_task_gamma_resume_ch4 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR + description: "Configures whether or not to clear LEDC_task_gamma_resume_ch5 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_GAMMA_RESUME_CH6_ST_CLR + description: "Configures whether or not to clear LEDC_task_gamma_resume_ch6 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: LEDC_TASK_GAMMA_RESUME_CH7_ST_CLR + description: "Configures whether or not to clear LEDC_task_gamma_resume_ch7 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: TG0_TASK_CNT_START_TIMER0_ST_CLR + description: "Configures whether or not to clear TG0_task_cnt_start_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: TG0_TASK_ALARM_START_TIMER0_ST_CLR + description: "Configures whether or not to clear TG0_task_alarm_start_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: TG0_TASK_CNT_STOP_TIMER0_ST_CLR + description: "Configures whether or not to clear TG0_task_cnt_stop_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR + description: "Configures whether or not to clear TG0_task_cnt_reload_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: TASK_ST3 + description: Tasks trigger status register + addressOffset: 512 + size: 32 + fields: + - name: TG0_TASK_CNT_CAP_TIMER0_ST + description: "Represents TG0_task_cnt_cap_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TG0_TASK_CNT_START_TIMER1_ST + description: "Represents TG0_task_cnt_start_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TG0_TASK_ALARM_START_TIMER1_ST + description: "Represents TG0_task_alarm_start_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TG0_TASK_CNT_STOP_TIMER1_ST + description: "Represents TG0_task_cnt_stop_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TG0_TASK_CNT_RELOAD_TIMER1_ST + description: "Represents TG0_task_cnt_reload_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TG0_TASK_CNT_CAP_TIMER1_ST + description: "Represents TG0_task_cnt_cap_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TG1_TASK_CNT_START_TIMER0_ST + description: "Represents TG1_task_cnt_start_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TG1_TASK_ALARM_START_TIMER0_ST + description: "Represents TG1_task_alarm_start_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TG1_TASK_CNT_STOP_TIMER0_ST + description: "Represents TG1_task_cnt_stop_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TG1_TASK_CNT_RELOAD_TIMER0_ST + description: "Represents TG1_task_cnt_reload_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TG1_TASK_CNT_CAP_TIMER0_ST + description: "Represents TG1_task_cnt_cap_timer0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TG1_TASK_CNT_START_TIMER1_ST + description: "Represents TG1_task_cnt_start_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TG1_TASK_ALARM_START_TIMER1_ST + description: "Represents TG1_task_alarm_start_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TG1_TASK_CNT_STOP_TIMER1_ST + description: "Represents TG1_task_cnt_stop_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TG1_TASK_CNT_RELOAD_TIMER1_ST + description: "Represents TG1_task_cnt_reload_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TG1_TASK_CNT_CAP_TIMER1_ST + description: "Represents TG1_task_cnt_cap_timer1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: MCPWM0_TASK_CMPR0_A_UP_ST + description: "Represents MCPWM0_task_cmpr0_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: MCPWM0_TASK_CMPR1_A_UP_ST + description: "Represents MCPWM0_task_cmpr1_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MCPWM0_TASK_CMPR2_A_UP_ST + description: "Represents MCPWM0_task_cmpr2_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: MCPWM0_TASK_CMPR0_B_UP_ST + description: "Represents MCPWM0_task_cmpr0_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: MCPWM0_TASK_CMPR1_B_UP_ST + description: "Represents MCPWM0_task_cmpr1_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: MCPWM0_TASK_CMPR2_B_UP_ST + description: "Represents MCPWM0_task_cmpr2_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: MCPWM0_TASK_GEN_STOP_ST + description: "Represents MCPWM0_task_gen_stop trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: MCPWM0_TASK_TIMER0_SYN_ST + description: "Represents MCPWM0_task_timer0_syn trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: MCPWM0_TASK_TIMER1_SYN_ST + description: "Represents MCPWM0_task_timer1_syn trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: MCPWM0_TASK_TIMER2_SYN_ST + description: "Represents MCPWM0_task_timer2_syn trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: MCPWM0_TASK_TIMER0_PERIOD_UP_ST + description: "Represents MCPWM0_task_timer0_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: MCPWM0_TASK_TIMER1_PERIOD_UP_ST + description: "Represents MCPWM0_task_timer1_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: MCPWM0_TASK_TIMER2_PERIOD_UP_ST + description: "Represents MCPWM0_task_timer2_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: MCPWM0_TASK_TZ0_OST_ST + description: "Represents MCPWM0_task_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: MCPWM0_TASK_TZ1_OST_ST + description: "Represents MCPWM0_task_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: MCPWM0_TASK_TZ2_OST_ST + description: "Represents MCPWM0_task_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TASK_ST3_CLR + description: Tasks trigger status clear register + addressOffset: 516 + size: 32 + fields: + - name: TG0_TASK_CNT_CAP_TIMER0_ST_CLR + description: "Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TG0_TASK_CNT_START_TIMER1_ST_CLR + description: "Configures whether or not to clear TG0_task_cnt_start_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TG0_TASK_ALARM_START_TIMER1_ST_CLR + description: "Configures whether or not to clear TG0_task_alarm_start_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TG0_TASK_CNT_STOP_TIMER1_ST_CLR + description: "Configures whether or not to clear TG0_task_cnt_stop_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR + description: "Configures whether or not to clear TG0_task_cnt_reload_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: TG0_TASK_CNT_CAP_TIMER1_ST_CLR + description: "Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TG1_TASK_CNT_START_TIMER0_ST_CLR + description: "Configures whether or not to clear TG1_task_cnt_start_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TG1_TASK_ALARM_START_TIMER0_ST_CLR + description: "Configures whether or not to clear TG1_task_alarm_start_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: TG1_TASK_CNT_STOP_TIMER0_ST_CLR + description: "Configures whether or not to clear TG1_task_cnt_stop_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR + description: "Configures whether or not to clear TG1_task_cnt_reload_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: TG1_TASK_CNT_CAP_TIMER0_ST_CLR + description: "Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: TG1_TASK_CNT_START_TIMER1_ST_CLR + description: "Configures whether or not to clear TG1_task_cnt_start_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TG1_TASK_ALARM_START_TIMER1_ST_CLR + description: "Configures whether or not to clear TG1_task_alarm_start_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: TG1_TASK_CNT_STOP_TIMER1_ST_CLR + description: "Configures whether or not to clear TG1_task_cnt_stop_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR + description: "Configures whether or not to clear TG1_task_cnt_reload_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: TG1_TASK_CNT_CAP_TIMER1_ST_CLR + description: "Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: MCPWM0_TASK_CMPR0_A_UP_ST_CLR + description: "Configures whether or not to clear MCPWM0_task_cmpr0_a_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: MCPWM0_TASK_CMPR1_A_UP_ST_CLR + description: "Configures whether or not to clear MCPWM0_task_cmpr1_a_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: MCPWM0_TASK_CMPR2_A_UP_ST_CLR + description: "Configures whether or not to clear MCPWM0_task_cmpr2_a_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: MCPWM0_TASK_CMPR0_B_UP_ST_CLR + description: "Configures whether or not to clear MCPWM0_task_cmpr0_b_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: MCPWM0_TASK_CMPR1_B_UP_ST_CLR + description: "Configures whether or not to clear MCPWM0_task_cmpr1_b_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: MCPWM0_TASK_CMPR2_B_UP_ST_CLR + description: "Configures whether or not to clear MCPWM0_task_cmpr2_b_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: MCPWM0_TASK_GEN_STOP_ST_CLR + description: "Configures whether or not to clear MCPWM0_task_gen_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: MCPWM0_TASK_TIMER0_SYN_ST_CLR + description: "Configures whether or not to clear MCPWM0_task_timer0_syn trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: MCPWM0_TASK_TIMER1_SYN_ST_CLR + description: "Configures whether or not to clear MCPWM0_task_timer1_syn trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: MCPWM0_TASK_TIMER2_SYN_ST_CLR + description: "Configures whether or not to clear MCPWM0_task_timer2_syn trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: MCPWM0_TASK_TIMER0_PERIOD_UP_ST_CLR + description: "Configures whether or not to clear MCPWM0_task_timer0_period_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: MCPWM0_TASK_TIMER1_PERIOD_UP_ST_CLR + description: "Configures whether or not to clear MCPWM0_task_timer1_period_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: MCPWM0_TASK_TIMER2_PERIOD_UP_ST_CLR + description: "Configures whether or not to clear MCPWM0_task_timer2_period_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: MCPWM0_TASK_TZ0_OST_ST_CLR + description: "Configures whether or not to clear MCPWM0_task_tz0_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: MCPWM0_TASK_TZ1_OST_ST_CLR + description: "Configures whether or not to clear MCPWM0_task_tz1_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: MCPWM0_TASK_TZ2_OST_ST_CLR + description: "Configures whether or not to clear MCPWM0_task_tz2_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: TASK_ST4 + description: Tasks trigger status register + addressOffset: 520 + size: 32 + fields: + - name: MCPWM0_TASK_CLR0_OST_ST + description: "Represents MCPWM0_task_clr0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MCPWM0_TASK_CLR1_OST_ST + description: "Represents MCPWM0_task_clr1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCPWM0_TASK_CLR2_OST_ST + description: "Represents MCPWM0_task_clr2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCPWM0_TASK_CAP0_ST + description: "Represents MCPWM0_task_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCPWM0_TASK_CAP1_ST + description: "Represents MCPWM0_task_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MCPWM0_TASK_CAP2_ST + description: "Represents MCPWM0_task_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: MCPWM1_TASK_CMPR0_A_UP_ST + description: "Represents MCPWM1_task_cmpr0_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: MCPWM1_TASK_CMPR1_A_UP_ST + description: "Represents MCPWM1_task_cmpr1_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: MCPWM1_TASK_CMPR2_A_UP_ST + description: "Represents MCPWM1_task_cmpr2_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: MCPWM1_TASK_CMPR0_B_UP_ST + description: "Represents MCPWM1_task_cmpr0_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: MCPWM1_TASK_CMPR1_B_UP_ST + description: "Represents MCPWM1_task_cmpr1_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: MCPWM1_TASK_CMPR2_B_UP_ST + description: "Represents MCPWM1_task_cmpr2_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: MCPWM1_TASK_GEN_STOP_ST + description: "Represents MCPWM1_task_gen_stop trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: MCPWM1_TASK_TIMER0_SYN_ST + description: "Represents MCPWM1_task_timer0_syn trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: MCPWM1_TASK_TIMER1_SYN_ST + description: "Represents MCPWM1_task_timer1_syn trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: MCPWM1_TASK_TIMER2_SYN_ST + description: "Represents MCPWM1_task_timer2_syn trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: MCPWM1_TASK_TIMER0_PERIOD_UP_ST + description: "Represents MCPWM1_task_timer0_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: MCPWM1_TASK_TIMER1_PERIOD_UP_ST + description: "Represents MCPWM1_task_timer1_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MCPWM1_TASK_TIMER2_PERIOD_UP_ST + description: "Represents MCPWM1_task_timer2_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: MCPWM1_TASK_TZ0_OST_ST + description: "Represents MCPWM1_task_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: MCPWM1_TASK_TZ1_OST_ST + description: "Represents MCPWM1_task_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: MCPWM1_TASK_TZ2_OST_ST + description: "Represents MCPWM1_task_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: MCPWM1_TASK_CLR0_OST_ST + description: "Represents MCPWM1_task_clr0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: MCPWM1_TASK_CLR1_OST_ST + description: "Represents MCPWM1_task_clr1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: MCPWM1_TASK_CLR2_OST_ST + description: "Represents MCPWM1_task_clr2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: MCPWM1_TASK_CAP0_ST + description: "Represents MCPWM1_task_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: MCPWM1_TASK_CAP1_ST + description: "Represents MCPWM1_task_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: MCPWM1_TASK_CAP2_ST + description: "Represents MCPWM1_task_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: ADC_TASK_SAMPLE0_ST + description: "Represents ADC_task_sample0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: ADC_TASK_SAMPLE1_ST + description: "Represents ADC_task_sample1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ADC_TASK_START0_ST + description: "Represents ADC_task_start0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: ADC_TASK_STOP0_ST + description: "Represents ADC_task_stop0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TASK_ST4_CLR + description: Tasks trigger status clear register + addressOffset: 524 + size: 32 + fields: + - name: MCPWM0_TASK_CLR0_OST_ST_CLR + description: "Configures whether or not to clear MCPWM0_task_clr0_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: MCPWM0_TASK_CLR1_OST_ST_CLR + description: "Configures whether or not to clear MCPWM0_task_clr1_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: MCPWM0_TASK_CLR2_OST_ST_CLR + description: "Configures whether or not to clear MCPWM0_task_clr2_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: MCPWM0_TASK_CAP0_ST_CLR + description: "Configures whether or not to clear MCPWM0_task_cap0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: MCPWM0_TASK_CAP1_ST_CLR + description: "Configures whether or not to clear MCPWM0_task_cap1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: MCPWM0_TASK_CAP2_ST_CLR + description: "Configures whether or not to clear MCPWM0_task_cap2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: MCPWM1_TASK_CMPR0_A_UP_ST_CLR + description: "Configures whether or not to clear MCPWM1_task_cmpr0_a_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: MCPWM1_TASK_CMPR1_A_UP_ST_CLR + description: "Configures whether or not to clear MCPWM1_task_cmpr1_a_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: MCPWM1_TASK_CMPR2_A_UP_ST_CLR + description: "Configures whether or not to clear MCPWM1_task_cmpr2_a_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: MCPWM1_TASK_CMPR0_B_UP_ST_CLR + description: "Configures whether or not to clear MCPWM1_task_cmpr0_b_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: MCPWM1_TASK_CMPR1_B_UP_ST_CLR + description: "Configures whether or not to clear MCPWM1_task_cmpr1_b_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: MCPWM1_TASK_CMPR2_B_UP_ST_CLR + description: "Configures whether or not to clear MCPWM1_task_cmpr2_b_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: MCPWM1_TASK_GEN_STOP_ST_CLR + description: "Configures whether or not to clear MCPWM1_task_gen_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: MCPWM1_TASK_TIMER0_SYN_ST_CLR + description: "Configures whether or not to clear MCPWM1_task_timer0_syn trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: MCPWM1_TASK_TIMER1_SYN_ST_CLR + description: "Configures whether or not to clear MCPWM1_task_timer1_syn trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: MCPWM1_TASK_TIMER2_SYN_ST_CLR + description: "Configures whether or not to clear MCPWM1_task_timer2_syn trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: MCPWM1_TASK_TIMER0_PERIOD_UP_ST_CLR + description: "Configures whether or not to clear MCPWM1_task_timer0_period_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: MCPWM1_TASK_TIMER1_PERIOD_UP_ST_CLR + description: "Configures whether or not to clear MCPWM1_task_timer1_period_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: MCPWM1_TASK_TIMER2_PERIOD_UP_ST_CLR + description: "Configures whether or not to clear MCPWM1_task_timer2_period_up trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: MCPWM1_TASK_TZ0_OST_ST_CLR + description: "Configures whether or not to clear MCPWM1_task_tz0_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: MCPWM1_TASK_TZ1_OST_ST_CLR + description: "Configures whether or not to clear MCPWM1_task_tz1_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: MCPWM1_TASK_TZ2_OST_ST_CLR + description: "Configures whether or not to clear MCPWM1_task_tz2_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: MCPWM1_TASK_CLR0_OST_ST_CLR + description: "Configures whether or not to clear MCPWM1_task_clr0_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: MCPWM1_TASK_CLR1_OST_ST_CLR + description: "Configures whether or not to clear MCPWM1_task_clr1_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: MCPWM1_TASK_CLR2_OST_ST_CLR + description: "Configures whether or not to clear MCPWM1_task_clr2_ost trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: MCPWM1_TASK_CAP0_ST_CLR + description: "Configures whether or not to clear MCPWM1_task_cap0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: MCPWM1_TASK_CAP1_ST_CLR + description: "Configures whether or not to clear MCPWM1_task_cap1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: MCPWM1_TASK_CAP2_ST_CLR + description: "Configures whether or not to clear MCPWM1_task_cap2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: ADC_TASK_SAMPLE0_ST_CLR + description: "Configures whether or not to clear ADC_task_sample0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: ADC_TASK_SAMPLE1_ST_CLR + description: "Configures whether or not to clear ADC_task_sample1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: ADC_TASK_START0_ST_CLR + description: "Configures whether or not to clear ADC_task_start0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: ADC_TASK_STOP0_ST_CLR + description: "Configures whether or not to clear ADC_task_stop0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: TASK_ST5 + description: Tasks trigger status register + addressOffset: 528 + size: 32 + fields: + - name: REGDMA_TASK_START0_ST + description: "Represents REGDMA_task_start0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REGDMA_TASK_START1_ST + description: "Represents REGDMA_task_start1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: REGDMA_TASK_START2_ST + description: "Represents REGDMA_task_start2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: REGDMA_TASK_START3_ST + description: "Represents REGDMA_task_start3 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TMPSNSR_TASK_START_SAMPLE_ST + description: "Represents TMPSNSR_task_start_sample trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TMPSNSR_TASK_STOP_SAMPLE_ST + description: "Represents TMPSNSR_task_stop_sample trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: I2S0_TASK_START_RX_ST + description: "Represents I2S0_task_start_rx trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: I2S0_TASK_START_TX_ST + description: "Represents I2S0_task_start_tx trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: I2S0_TASK_STOP_RX_ST + description: "Represents I2S0_task_stop_rx trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: I2S0_TASK_STOP_TX_ST + description: "Represents I2S0_task_stop_tx trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: I2S1_TASK_START_RX_ST + description: "Represents I2S1_task_start_rx trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: I2S1_TASK_START_TX_ST + description: "Represents I2S1_task_start_tx trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: I2S1_TASK_STOP_RX_ST + description: "Represents I2S1_task_stop_rx trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: I2S1_TASK_STOP_TX_ST + description: "Represents I2S1_task_stop_tx trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: I2S2_TASK_START_RX_ST + description: "Represents I2S2_task_start_rx trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: I2S2_TASK_START_TX_ST + description: "Represents I2S2_task_start_tx trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: I2S2_TASK_STOP_RX_ST + description: "Represents I2S2_task_stop_rx trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: I2S2_TASK_STOP_TX_ST + description: "Represents I2S2_task_stop_tx trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: ULP_TASK_WAKEUP_CPU_ST + description: "Represents ULP_task_wakeup_cpu trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: ULP_TASK_INT_CPU_ST + description: "Represents ULP_task_int_cpu trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RTC_TASK_START_ST + description: "Represents RTC_task_start trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: RTC_TASK_STOP_ST + description: "Represents RTC_task_stop trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: RTC_TASK_CLR_ST + description: "Represents RTC_task_clr trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RTC_TASK_TRIGGERFLW_ST + description: "Represents RTC_task_triggerflw trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_TASK_IN_START_CH0_ST + description: "Represents PDMA_AHB_task_in_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_TASK_IN_START_CH1_ST + description: "Represents PDMA_AHB_task_in_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_TASK_IN_START_CH2_ST + description: "Represents PDMA_AHB_task_in_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_TASK_OUT_START_CH0_ST + description: "Represents PDMA_AHB_task_out_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_TASK_OUT_START_CH1_ST + description: "Represents PDMA_AHB_task_out_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: PDMA_AHB_TASK_OUT_START_CH2_ST + description: "Represents PDMA_AHB_task_out_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_TASK_IN_START_CH0_ST + description: "Represents PDMA_AXI_task_in_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_TASK_IN_START_CH1_ST + description: "Represents PDMA_AXI_task_in_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TASK_ST5_CLR + description: Tasks trigger status clear register + addressOffset: 532 + size: 32 + fields: + - name: REGDMA_TASK_START0_ST_CLR + description: "Configures whether or not to clear REGDMA_task_start0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: REGDMA_TASK_START1_ST_CLR + description: "Configures whether or not to clear REGDMA_task_start1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: REGDMA_TASK_START2_ST_CLR + description: "Configures whether or not to clear REGDMA_task_start2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: REGDMA_TASK_START3_ST_CLR + description: "Configures whether or not to clear REGDMA_task_start3 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TMPSNSR_TASK_START_SAMPLE_ST_CLR + description: "Configures whether or not to clear TMPSNSR_task_start_sample trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: TMPSNSR_TASK_STOP_SAMPLE_ST_CLR + description: "Configures whether or not to clear TMPSNSR_task_stop_sample trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: I2S0_TASK_START_RX_ST_CLR + description: "Configures whether or not to clear I2S0_task_start_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: I2S0_TASK_START_TX_ST_CLR + description: "Configures whether or not to clear I2S0_task_start_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: I2S0_TASK_STOP_RX_ST_CLR + description: "Configures whether or not to clear I2S0_task_stop_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: I2S0_TASK_STOP_TX_ST_CLR + description: "Configures whether or not to clear I2S0_task_stop_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: I2S1_TASK_START_RX_ST_CLR + description: "Configures whether or not to clear I2S1_task_start_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: I2S1_TASK_START_TX_ST_CLR + description: "Configures whether or not to clear I2S1_task_start_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: I2S1_TASK_STOP_RX_ST_CLR + description: "Configures whether or not to clear I2S1_task_stop_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: I2S1_TASK_STOP_TX_ST_CLR + description: "Configures whether or not to clear I2S1_task_stop_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: I2S2_TASK_START_RX_ST_CLR + description: "Configures whether or not to clear I2S2_task_start_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: I2S2_TASK_START_TX_ST_CLR + description: "Configures whether or not to clear I2S2_task_start_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: I2S2_TASK_STOP_RX_ST_CLR + description: "Configures whether or not to clear I2S2_task_stop_rx trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: I2S2_TASK_STOP_TX_ST_CLR + description: "Configures whether or not to clear I2S2_task_stop_tx trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: ULP_TASK_WAKEUP_CPU_ST_CLR + description: "Configures whether or not to clear ULP_task_wakeup_cpu trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: ULP_TASK_INT_CPU_ST_CLR + description: "Configures whether or not to clear ULP_task_int_cpu trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: RTC_TASK_START_ST_CLR + description: "Configures whether or not to clear RTC_task_start trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: RTC_TASK_STOP_ST_CLR + description: "Configures whether or not to clear RTC_task_stop trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: RTC_TASK_CLR_ST_CLR + description: "Configures whether or not to clear RTC_task_clr trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: RTC_TASK_TRIGGERFLW_ST_CLR + description: "Configures whether or not to clear RTC_task_triggerflw trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_TASK_IN_START_CH0_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_task_in_start_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_TASK_IN_START_CH1_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_task_in_start_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_TASK_IN_START_CH2_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_task_in_start_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_TASK_OUT_START_CH0_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_task_out_start_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_TASK_OUT_START_CH1_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_task_out_start_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: PDMA_AHB_TASK_OUT_START_CH2_ST_CLR + description: "Configures whether or not to clear PDMA_AHB_task_out_start_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_TASK_IN_START_CH0_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_task_in_start_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_TASK_IN_START_CH1_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_task_in_start_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: TASK_ST6 + description: Tasks trigger status register + addressOffset: 536 + size: 32 + fields: + - name: PDMA_AXI_TASK_IN_START_CH2_ST + description: "Represents PDMA_AXI_task_in_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_TASK_OUT_START_CH0_ST + description: "Represents PDMA_AXI_task_out_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_TASK_OUT_START_CH1_ST + description: "Represents PDMA_AXI_task_out_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PDMA_AXI_TASK_OUT_START_CH2_ST + description: "Represents PDMA_AXI_task_out_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PMU_TASK_SLEEP_REQ_ST + description: "Represents PMU_task_sleep_req trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DMA2D_TASK_IN_START_CH0_ST + description: "Represents DMA2D_task_in_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DMA2D_TASK_IN_START_CH1_ST + description: "Represents DMA2D_task_in_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: DMA2D_TASK_IN_DSCR_READY_CH0_ST + description: "Represents DMA2D_task_in_dscr_ready_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DMA2D_TASK_IN_DSCR_READY_CH1_ST + description: "Represents DMA2D_task_in_dscr_ready_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DMA2D_TASK_OUT_START_CH0_ST + description: "Represents DMA2D_task_out_start_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DMA2D_TASK_OUT_START_CH1_ST + description: "Represents DMA2D_task_out_start_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DMA2D_TASK_OUT_START_CH2_ST + description: "Represents DMA2D_task_out_start_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DMA2D_TASK_OUT_DSCR_READY_CH0_ST + description: "Represents DMA2D_task_out_dscr_ready_ch0 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DMA2D_TASK_OUT_DSCR_READY_CH1_ST + description: "Represents DMA2D_task_out_dscr_ready_ch1 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DMA2D_TASK_OUT_DSCR_READY_CH2_ST + description: "Represents DMA2D_task_out_dscr_ready_ch2 trigger status.\\\\0: Not triggered\\\\1: Triggered" + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: TASK_ST6_CLR + description: Tasks trigger status clear register + addressOffset: 540 + size: 32 + fields: + - name: PDMA_AXI_TASK_IN_START_CH2_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_task_in_start_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_TASK_OUT_START_CH0_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_task_out_start_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_TASK_OUT_START_CH1_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_task_out_start_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: PDMA_AXI_TASK_OUT_START_CH2_ST_CLR + description: "Configures whether or not to clear PDMA_AXI_task_out_start_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: PMU_TASK_SLEEP_REQ_ST_CLR + description: "Configures whether or not to clear PMU_task_sleep_req trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: DMA2D_TASK_IN_START_CH0_ST_CLR + description: "Configures whether or not to clear DMA2D_task_in_start_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: DMA2D_TASK_IN_START_CH1_ST_CLR + description: "Configures whether or not to clear DMA2D_task_in_start_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: DMA2D_TASK_IN_DSCR_READY_CH0_ST_CLR + description: "Configures whether or not to clear DMA2D_task_in_dscr_ready_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: DMA2D_TASK_IN_DSCR_READY_CH1_ST_CLR + description: "Configures whether or not to clear DMA2D_task_in_dscr_ready_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: DMA2D_TASK_OUT_START_CH0_ST_CLR + description: "Configures whether or not to clear DMA2D_task_out_start_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: DMA2D_TASK_OUT_START_CH1_ST_CLR + description: "Configures whether or not to clear DMA2D_task_out_start_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: DMA2D_TASK_OUT_START_CH2_ST_CLR + description: "Configures whether or not to clear DMA2D_task_out_start_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: DMA2D_TASK_OUT_DSCR_READY_CH0_ST_CLR + description: "Configures whether or not to clear DMA2D_task_out_dscr_ready_ch0 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: DMA2D_TASK_OUT_DSCR_READY_CH1_ST_CLR + description: "Configures whether or not to clear DMA2D_task_out_dscr_ready_ch1 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: DMA2D_TASK_OUT_DSCR_READY_CH2_ST_CLR + description: "Configures whether or not to clear DMA2D_task_out_dscr_ready_ch2 trigger status.\\\\0: Invalid, No effect\\\\1: Clear" + bitOffset: 14 + bitWidth: 1 + access: write-only + - register: + name: CLK_EN + description: ETM clock enable register + addressOffset: 544 + size: 32 + fields: + - name: CLK_EN + description: "Configures whether or not to open register clock gate.\\\\0: Open the clock gate only when application writes registers\\\\1: Force open the clock gate for register" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: ETM date register + addressOffset: 548 + size: 32 + resetValue: 36712497 + fields: + - name: DATE + description: Configures the version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SPI0 + description: SPI (Serial Peripheral Interface) Controller 0 + groupName: SPI0 + baseAddress: 1342750720 + addressBlock: + - offset: 0 + size: 332 + usage: registers + registers: + - register: + name: SPI_MEM_CMD + description: SPI0 FSM status register + addressOffset: 0 + size: 32 + fields: + - name: SPI_MEM_MST_ST + description: "The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state." + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: SPI_MEM_SLV_ST + description: "The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state." + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: SPI_MEM_USR + description: "SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 18 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_CTRL + description: SPI0 control register. + addressOffset: 8 + size: 32 + resetValue: 2150375436 + fields: + - name: SPI_MEM_WDUMMY_DQS_ALWAYS_OUT + description: "In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_DQS is output by the MSPI controller." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WDUMMY_ALWAYS_OUT + description: "In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDUMMY_RIN + description: "In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDUMMY_WOUT + description: "In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDOUT_OCT + description: "Apply 8 signals during write-data phase 1:enable 0: disable" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDIN_OCT + description: "Apply 8 signals during read-data phase 1:enable 0: disable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FADDR_OCT + description: "Apply 8 signals during address phase 1:enable 0: disable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FCMD_QUAD + description: "Apply 4 signals during command phase 1:enable 0: disable" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FCMD_OCT + description: "Apply 8 signals during command phase 1:enable 0: disable" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FASTRD_MODE + description: "This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FREAD_DUAL + description: "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SPI_MEM_Q_POL + description: "The bit is used to set MISO line polarity, 1: high 0, low" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SPI_MEM_D_POL + description: "The bit is used to set MOSI line polarity, 1: high 0, low" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FREAD_QUAD + description: "In the read operations read-data phase apply 4 signals. 1: enable 0: disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WP + description: "Write protect signal output when SPI is idle. 1: output high, 0: output low." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FREAD_DIO + description: "In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FREAD_QIO + description: "In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DQS_IE_ALWAYS_ON + description: "When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DATA_IE_ALWAYS_ON + description: "When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_CTRL1 + description: SPI0 control1 register. + addressOffset: 12 + size: 32 + resetValue: 685768704 + fields: + - name: SPI_MEM_CLK_MODE + description: "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SPI_AR_SIZE0_1_SUPPORT_EN + description: "1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_AW_SIZE0_1_SUPPORT_EN + description: "1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SPI_AXI_RDATA_BACK_FAST + description: "1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: Reply AXI read data to AXI bus when all the read data is available." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SPI_MEM_RRESP_ECC_ERR_EN + description: "1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AR_SPLICE_EN + description: Set this bit to enable AXI Read Splice-transfer. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AW_SPLICE_EN + description: Set this bit to enable AXI Write Splice-transfer. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI_MEM_RAM0_EN + description: "When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be accessed at the same time." + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: SPI_MEM_DUAL_RAM_EN + description: "Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the same time." + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SPI_MEM_FAST_WRITE_EN + description: "Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in tx_bus_fifo_l2." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SPI_MEM_RXFIFO_RST + description: The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI. Set this bit to reset these FIFO. + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: SPI_MEM_TXFIFO_RST + description: The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_CTRL2 + description: SPI0 control2 register. + addressOffset: 16 + size: 32 + resetValue: 16788513 + fields: + - name: SPI_MEM_CS_SETUP_TIME + description: "(cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit." + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: SPI_MEM_CS_HOLD_TIME + description: "SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit." + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: SPI_MEM_ECC_CS_HOLD_TIME + description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash. + bitOffset: 10 + bitWidth: 3 + access: read-write + - name: SPI_MEM_ECC_SKIP_PAGE_CORNER + description: "1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SPI_MEM_ECC_16TO18_BYTE_EN + description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SPLIT_TRANS_EN + description: "Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CS_HOLD_DELAY + description: "These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles." + bitOffset: 25 + bitWidth: 6 + access: read-write + - name: SPI_MEM_SYNC_RESET + description: The spi0_mst_st and spi0_slv_st will be reset. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_CLOCK + description: SPI clock division control register. + addressOffset: 20 + size: 32 + resetValue: 196867 + fields: + - name: SPI_MEM_CLKCNT_L + description: In the master mode it must be equal to spi_mem_clkcnt_N. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SPI_MEM_CLKCNT_H + description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SPI_MEM_CLKCNT_N + description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SPI_MEM_CLK_EQU_SYSCLK + description: "1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module clock." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_USER + description: SPI0 user register. + addressOffset: 24 + size: 32 + fields: + - name: SPI_MEM_CS_HOLD + description: "spi cs keep low when spi is in done phase. 1: enable 0: disable." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CS_SETUP + description: "spi cs is enable when spi is in prepare phase. 1: enable 0: disable." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CK_OUT_EDGE + description: The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_DUMMY_IDLE + description: spi clock is disable in dummy phase when the bit is enable. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_DUMMY + description: This bit enable the dummy phase of an operation. + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_USER1 + description: SPI0 user1 register. + addressOffset: 28 + size: 32 + resetValue: 1543503943 + fields: + - name: SPI_MEM_USR_DUMMY_CYCLELEN + description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: SPI_MEM_USR_DBYTELEN + description: SPI0 USR_CMD read or write data byte length -1 + bitOffset: 6 + bitWidth: 3 + access: read-only + - name: SPI_MEM_USR_ADDR_BITLEN + description: The length in bits of address phase. The register value shall be (bit_num-1). + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: SPI_MEM_USER2 + description: SPI0 user2 register. + addressOffset: 32 + size: 32 + resetValue: 1879048192 + fields: + - name: SPI_MEM_USR_COMMAND_VALUE + description: The value of command. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SPI_MEM_USR_COMMAND_BITLEN + description: The length in bits of command phase. The register value shall be (bit_num-1) + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: SPI_MEM_RD_STATUS + description: SPI0 read control register. + addressOffset: 44 + size: 32 + fields: + - name: SPI_MEM_WB_MODE + description: Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: SPI_MEM_MISC + description: SPI0 misc register + addressOffset: 52 + size: 32 + fields: + - name: SPI_MEM_FSUB_PIN + description: "For SPI0, flash is connected to SUBPINs." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SSUB_PIN + description: "For SPI0, sram is connected to SUBPINs." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CK_IDLE_EDGE + description: "1: SPI_CLK line is high when idle 0: spi clk line is low when idle" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CS_KEEP_ACTIVE + description: SPI_CS line keep low when the bit is set. + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_CACHE_FCTRL + description: SPI0 bit mode control register. + addressOffset: 60 + size: 32 + resetValue: 3221225472 + fields: + - name: SPI_MEM_AXI_REQ_EN + description: "For SPI0, AXI master access enable, 1: enable, 0:disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CACHE_USR_ADDR_4BYTE + description: "For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CACHE_FLASH_USR_CMD + description: "For SPI0, cache read flash for user define command, 1: enable, 0:disable." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDIN_DUAL + description: "For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDOUT_DUAL + description: "For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FADDR_DUAL + description: "For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDIN_QUAD + description: "For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDOUT_QUAD + description: "For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FADDR_QUAD + description: "For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SPI_SAME_AW_AR_ADDR_CHK_EN + description: Set this bit to check AXI read/write the same address region. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI_CLOSE_AXI_INF_EN + description: "Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_CACHE_SCTRL + description: SPI0 external RAM control register + addressOffset: 64 + size: 32 + resetValue: 5619824 + fields: + - name: SPI_MEM_CACHE_USR_SADDR_4BYTE + description: "For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_SRAM_DIO + description: "For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_SRAM_QIO + description: "For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_WR_SRAM_DUMMY + description: "For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_RD_SRAM_DUMMY + description: "For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CACHE_SRAM_USR_RCMD + description: "For SPI0, In the external RAM mode cache read external RAM for user define command." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SRAM_RDUMMY_CYCLELEN + description: "For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1)." + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: SPI_MEM_SRAM_ADDR_BITLEN + description: "For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1)." + bitOffset: 14 + bitWidth: 6 + access: read-write + - name: SPI_MEM_CACHE_SRAM_USR_WCMD + description: "For SPI0, In the external RAM mode cache write sram for user define command" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SRAM_OCT + description: reserved + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SRAM_WDUMMY_CYCLELEN + description: "For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1)." + bitOffset: 22 + bitWidth: 6 + access: read-write + - register: + name: SPI_MEM_SRAM_CMD + description: SPI0 external RAM mode control register + addressOffset: 68 + size: 32 + resetValue: 2160066560 + fields: + - name: SPI_MEM_SCLK_MODE + description: "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SPI_MEM_SWB_MODE + description: Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit. + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: SPI_MEM_SDIN_DUAL + description: "For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SDOUT_DUAL + description: "For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SADDR_DUAL + description: "For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SDIN_QUAD + description: "For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SDOUT_QUAD + description: "For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SADDR_QUAD + description: "For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SCMD_QUAD + description: "For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SDIN_OCT + description: "For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SDOUT_OCT + description: "For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SADDR_OCT + description: "For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SCMD_OCT + description: "For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SDUMMY_RIN + description: "In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SDUMMY_WOUT + description: "In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT + description: "In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_WDUMMY_ALWAYS_OUT + description: "In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SDIN_HEX + description: "For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SDOUT_HEX + description: "For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DQS_IE_ALWAYS_ON + description: "When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DATA_IE_ALWAYS_ON + description: "When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_SRAM_DRD_CMD + description: SPI0 external RAM DDR read command control register + addressOffset: 72 + size: 32 + fields: + - name: SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE + description: "For SPI0,When cache mode is enable it is the read command value of command phase for sram." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN + description: "For SPI0,When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1)." + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: SPI_MEM_SRAM_DWR_CMD + description: SPI0 external RAM DDR write command control register + addressOffset: 76 + size: 32 + fields: + - name: SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE + description: "For SPI0,When cache mode is enable it is the write command value of command phase for sram." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN + description: "For SPI0,When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1)." + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: SPI_MEM_SRAM_CLK + description: SPI0 external RAM clock control register + addressOffset: 80 + size: 32 + resetValue: 196867 + fields: + - name: SPI_MEM_SCLKCNT_L + description: "For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SPI_MEM_SCLKCNT_H + description: "For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1)." + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SPI_MEM_SCLKCNT_N + description: "For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SPI_MEM_SCLK_EQU_SYSCLK + description: "For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_FSM + description: SPI0 FSM status register + addressOffset: 84 + size: 32 + resetValue: 512 + fields: + - name: SPI_MEM_LOCK_DELAY_TIME + description: "The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1." + bitOffset: 7 + bitWidth: 5 + access: read-write + - register: + name: SPI_MEM_INT_ENA + description: SPI0 interrupt enable register + addressOffset: 192 + size: 32 + fields: + - name: SPI_MEM_SLV_ST_END_INT_ENA + description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_MST_ST_END_INT_ENA + description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_ECC_ERR_INT_ENA + description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_MEM_PMS_REJECT_INT_ENA + description: The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AXI_RADDR_ERR_INT_ENA + description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA + description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AXI_WADDR_ERR_INT__ENA + description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DQS0_AFIFO_OVF_INT_ENA + description: The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DQS1_AFIFO_OVF_INT_ENA + description: The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SPI_MEM_BUS_FIFO1_UDF_INT_ENA + description: The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI_MEM_BUS_FIFO0_UDF_INT_ENA + description: The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_INT_CLR + description: SPI0 interrupt clear register + addressOffset: 196 + size: 32 + fields: + - name: SPI_MEM_SLV_ST_END_INT_CLR + description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SPI_MEM_MST_ST_END_INT_CLR + description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SPI_MEM_ECC_ERR_INT_CLR + description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: SPI_MEM_PMS_REJECT_INT_CLR + description: The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: SPI_MEM_AXI_RADDR_ERR_INT_CLR + description: The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR + description: The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SPI_MEM_AXI_WADDR_ERR_INT_CLR + description: The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SPI_MEM_DQS0_AFIFO_OVF_INT_CLR + description: The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: SPI_MEM_DQS1_AFIFO_OVF_INT_CLR + description: The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: SPI_MEM_BUS_FIFO1_UDF_INT_CLR + description: The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: SPI_MEM_BUS_FIFO0_UDF_INT_CLR + description: The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_INT_RAW + description: SPI0 interrupt raw register + addressOffset: 200 + size: 32 + fields: + - name: SPI_MEM_SLV_ST_END_INT_RAW + description: "The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_MST_ST_END_INT_RAW + description: "The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_ECC_ERR_INT_RAW + description: "The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN are cleared, this bit will not be triggered." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_MEM_PMS_REJECT_INT_RAW + description: "The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AXI_RADDR_ERR_INT_RAW + description: "The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW + description: "The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AXI_WADDR_ERR_INT_RAW + description: "The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DQS0_AFIFO_OVF_INT_RAW + description: "The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS1 is overflow." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DQS1_AFIFO_OVF_INT_RAW + description: "The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO connected to SPI_DQS is overflow." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SPI_MEM_BUS_FIFO1_UDF_INT_RAW + description: "The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is underflow." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI_MEM_BUS_FIFO0_UDF_INT_RAW + description: "The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is underflow." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_INT_ST + description: SPI0 interrupt status register + addressOffset: 204 + size: 32 + fields: + - name: SPI_MEM_SLV_ST_END_INT_ST + description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SPI_MEM_MST_ST_END_INT_ST + description: The status bit for SPI_MEM_MST_ST_END_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SPI_MEM_ECC_ERR_INT_ST + description: The status bit for SPI_MEM_ECC_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SPI_MEM_PMS_REJECT_INT_ST + description: The status bit for SPI_MEM_PMS_REJECT_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SPI_MEM_AXI_RADDR_ERR_INT_ST + description: The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SPI_MEM_AXI_WR_FLASH_ERR_INT_ST + description: The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SPI_MEM_AXI_WADDR_ERR_INT_ST + description: The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SPI_MEM_DQS0_AFIFO_OVF_INT_ST + description: The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SPI_MEM_DQS1_AFIFO_OVF_INT_ST + description: The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: SPI_MEM_BUS_FIFO1_UDF_INT_ST + description: The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: SPI_MEM_BUS_FIFO0_UDF_INT_ST + description: The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_DDR + description: SPI0 flash DDR mode control register + addressOffset: 212 + size: 32 + resetValue: 12320 + fields: + - name: SPI_FMEM_DDR_EN + description: "1: in DDR mode, 0 in SDR mode" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_VAR_DUMMY + description: Set the bit to enable variable dummy cycle in spi DDR mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_DDR_RDAT_SWP + description: Set the bit to reorder rx data of the word in spi DDR mode. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_DDR_WDAT_SWP + description: Set the bit to reorder tx data of the word in spi DDR mode. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_DDR_CMD_DIS + description: the bit is used to disable dual edge in command phase when DDR mode. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_OUTMINBYTELEN + description: It is the minimum output data length in the panda device. + bitOffset: 5 + bitWidth: 7 + access: read-write + - name: SPI_FMEM_TX_DDR_MSK_EN + description: "Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_RX_DDR_MSK_EN + description: "Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_USR_DDR_DQS_THD + description: The delay number of data strobe which from memory based on SPI clock. + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: SPI_FMEM_DDR_DQS_LOOP + description: "1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_CLK_DIFF_EN + description: "Set this bit to enable the differential SPI_CLK#." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_DQS_CA_IN + description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_HYPERBUS_DUMMY_2X + description: "Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_CLK_DIFF_INV + description: Set this bit to invert SPI_DIFF when accesses to flash. . + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_OCTA_RAM_ADDR + description: "Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_HYPERBUS_CA + description: "Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}." + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: SPI_SMEM_DDR + description: SPI0 external RAM DDR mode control register + addressOffset: 216 + size: 32 + resetValue: 12320 + fields: + - name: EN + description: "1: in DDR mode, 0 in SDR mode" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_VAR_DUMMY + description: Set the bit to enable variable dummy cycle in spi DDR mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RDAT_SWP + description: Set the bit to reorder rx data of the word in spi DDR mode. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: WDAT_SWP + description: Set the bit to reorder tx data of the word in spi DDR mode. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CMD_DIS + description: the bit is used to disable dual edge in command phase when DDR mode. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_OUTMINBYTELEN + description: It is the minimum output data length in the DDR psram. + bitOffset: 5 + bitWidth: 7 + access: read-write + - name: SPI_SMEM_TX_DDR_MSK_EN + description: "Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_RX_DDR_MSK_EN + description: "Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_USR_DDR_DQS_THD + description: The delay number of data strobe which from memory based on SPI clock. + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: DQS_LOOP + description: "1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_CLK_DIFF_EN + description: "Set this bit to enable the differential SPI_CLK#." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DQS_CA_IN + description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_HYPERBUS_DUMMY_2X + description: "Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_CLK_DIFF_INV + description: Set this bit to invert SPI_DIFF when accesses to external RAM. . + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_OCTA_RAM_ADDR + description: "Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_HYPERBUS_CA + description: "Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}." + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: SPI_FMEM_PMS%s_ATTR + description: MSPI flash PMS section %s attribute register + addressOffset: 256 + size: 32 + resetValue: 3 + fields: + - name: SPI_FMEM_PMS_RD_ATTR + description: "1: SPI1 flash PMS section %s read accessible. 0: Not allowed." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_PMS_WR_ATTR + description: "1: SPI1 flash PMS section %s write accessible. 0: Not allowed." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_PMS_ECC + description: "SPI1 flash PMS section %s ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS section %s is configured by registers SPI_FMEM_PMS%s_ADDR_REG and SPI_FMEM_PMS%s_SIZE_REG." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: SPI_FMEM_PMS%s_ADDR + description: SPI1 flash PMS section %s start address register + addressOffset: 272 + size: 32 + fields: + - name: S + description: SPI1 flash PMS section %s start address value + bitOffset: 0 + bitWidth: 27 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: SPI_FMEM_PMS%s_SIZE + description: SPI1 flash PMS section %s start address register + addressOffset: 288 + size: 32 + resetValue: 4096 + fields: + - name: SPI_FMEM_PMS_SIZE + description: "SPI1 flash PMS section %s address region is (SPI_FMEM_PMS%s_ADDR_S, SPI_FMEM_PMS%s_ADDR_S + SPI_FMEM_PMS%s_SIZE)" + bitOffset: 0 + bitWidth: 15 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: SPI_SMEM_PMS%s_ATTR + description: SPI1 flash PMS section %s start address register + addressOffset: 304 + size: 32 + resetValue: 3 + fields: + - name: SPI_SMEM_PMS_RD_ATTR + description: "1: SPI1 external RAM PMS section %s read accessible. 0: Not allowed." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_PMS_WR_ATTR + description: "1: SPI1 external RAM PMS section %s write accessible. 0: Not allowed." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_PMS_ECC + description: "SPI1 external RAM PMS section %s ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM PMS section %s is configured by registers SPI_SMEM_PMS%s_ADDR_REG and SPI_SMEM_PMS%s_SIZE_REG." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: SPI_SMEM_PMS%s_ADDR + description: SPI1 external RAM PMS section %s start address register + addressOffset: 320 + size: 32 + fields: + - name: S + description: SPI1 external RAM PMS section %s start address value + bitOffset: 0 + bitWidth: 27 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: SPI_SMEM_PMS%s_SIZE + description: SPI1 external RAM PMS section %s start address register + addressOffset: 336 + size: 32 + resetValue: 4096 + fields: + - name: SPI_SMEM_PMS_SIZE + description: "SPI1 external RAM PMS section %s address region is (SPI_SMEM_PMS%s_ADDR_S, SPI_SMEM_PMS%s_ADDR_S + SPI_SMEM_PMS%s_SIZE)" + bitOffset: 0 + bitWidth: 15 + access: read-write + - register: + name: SPI_MEM_PMS_REJECT + description: SPI1 access reject register + addressOffset: 356 + size: 32 + fields: + - name: SPI_MEM_REJECT_ADDR + description: This bits show the first SPI1 access error address. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. + bitOffset: 0 + bitWidth: 27 + access: read-only + - name: SPI_MEM_PM_EN + description: Set this bit to enable SPI0/1 transfer permission control function. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SPI_MEM_PMS_LD + description: "1: SPI1 write access error. 0: No write access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set." + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SPI_MEM_PMS_ST + description: "1: SPI1 read access error. 0: No read access error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set." + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: SPI_MEM_PMS_MULTI_HIT + description: "1: SPI1 access is rejected because of address miss. 0: No address miss error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set." + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: SPI_MEM_PMS_IVD + description: "1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_ECC_CTRL + description: MSPI ECC control register + addressOffset: 360 + size: 32 + resetValue: 16797696 + fields: + - name: SPI_MEM_ECC_ERR_CNT + description: This bits show the error times of MSPI ECC read. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + bitOffset: 5 + bitWidth: 6 + access: read-only + - name: SPI_FMEM_ECC_ERR_INT_NUM + description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. + bitOffset: 11 + bitWidth: 6 + access: read-write + - name: SPI_FMEM_ECC_ERR_INT_EN + description: Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_PAGE_SIZE + description: "Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes." + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: SPI_FMEM_ECC_ADDR_EN + description: "Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit should be 0. Otherwise, this bit should be 1." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_ECC_ADDR_EN + description: Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN + description: "1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR record the first ECC error information." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_MEM_ECC_ERR_BITS + description: "Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to byte 0 bit 0 to byte 15 bit 7)" + bitOffset: 25 + bitWidth: 7 + access: read-only + - register: + name: SPI_MEM_ECC_ERR_ADDR + description: MSPI ECC error address register + addressOffset: 364 + size: 32 + fields: + - name: SPI_MEM_ECC_ERR_ADDR + description: This bits show the first MSPI ECC error address. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. + bitOffset: 0 + bitWidth: 27 + access: read-only + - register: + name: SPI_MEM_AXI_ERR_ADDR + description: SPI0 AXI request error address. + addressOffset: 368 + size: 32 + fields: + - name: SPI_MEM_AXI_ERR_ADDR + description: "This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set." + bitOffset: 0 + bitWidth: 27 + access: read-only + - register: + name: SPI_SMEM_ECC_CTRL + description: MSPI ECC control register + addressOffset: 372 + size: 32 + resetValue: 524288 + fields: + - name: SPI_SMEM_ECC_ERR_INT_EN + description: Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_PAGE_SIZE + description: "Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes." + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_ECC_ADDR_EN + description: "Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the ECC region or non-ECC region of external RAM. If there is no ECC region in external RAM, this bit should be 0. Otherwise, this bit should be 1." + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: SPI_SMEM_AXI_ADDR_CTRL + description: SPI0 AXI address control register + addressOffset: 376 + size: 32 + resetValue: 4227858432 + fields: + - name: SPI_MEM_ALL_FIFO_EMPTY + description: "The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others." + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: SPI_RDATA_AFIFO_REMPTY + description: "1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending." + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: SPI_RADDR_AFIFO_REMPTY + description: "1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending." + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SPI_WDATA_AFIFO_REMPTY + description: "1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending." + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: SPI_WBLEN_AFIFO_REMPTY + description: "1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending." + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: SPI_ALL_AXI_TRANS_AFIFO_EMPTY + description: "This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_AXI_ERR_RESP_EN + description: SPI0 AXI error response enable register + addressOffset: 380 + size: 32 + fields: + - name: SPI_MEM_AW_RESP_EN_MMU_VLD + description: Set this bit to enable AXI response function for mmu valid err in axi write trans. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AW_RESP_EN_MMU_GID + description: Set this bit to enable AXI response function for mmu gid err in axi write trans. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AW_RESP_EN_AXI_SIZE + description: Set this bit to enable AXI response function for axi size err in axi write trans. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AW_RESP_EN_AXI_FLASH + description: Set this bit to enable AXI response function for axi flash err in axi write trans. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AW_RESP_EN_MMU_ECC + description: Set this bit to enable AXI response function for mmu ecc err in axi write trans. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AW_RESP_EN_MMU_SENS + description: Set this bit to enable AXI response function for mmu sens in err axi write trans. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AW_RESP_EN_AXI_WSTRB + description: Set this bit to enable AXI response function for axi wstrb err in axi write trans. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AR_RESP_EN_MMU_VLD + description: Set this bit to enable AXI response function for mmu valid err in axi read trans. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AR_RESP_EN_MMU_GID + description: Set this bit to enable AXI response function for mmu gid err in axi read trans. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AR_RESP_EN_MMU_ECC + description: Set this bit to enable AXI response function for mmu ecc err in axi read trans. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AR_RESP_EN_MMU_SENS + description: Set this bit to enable AXI response function for mmu sensitive err in axi read trans. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AR_RESP_EN_AXI_SIZE + description: Set this bit to enable AXI response function for axi size err in axi read trans. + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_TIMING_CALI + description: SPI0 flash timing calibration register + addressOffset: 384 + size: 32 + resetValue: 1 + fields: + - name: SPI_MEM_TIMING_CLK_ENA + description: The bit is used to enable timing adjust clock for all reading operations. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_TIMING_CALI + description: The bit is used to enable timing auto-calibration for all reading operations. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_EXTRA_DUMMY_CYCLELEN + description: add extra dummy spi clock cycle length for spi clock calibration. + bitOffset: 2 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DLL_TIMING_CALI + description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to flash. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: UPDATE + description: "Set this bit to update delay mode, delay num and extra dummy in MSPI." + bitOffset: 6 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_DIN_MODE + description: MSPI flash input timing delay mode control register + addressOffset: 388 + size: 32 + fields: + - name: SPI_MEM_DIN0_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DIN1_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DIN2_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DIN3_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DIN4_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk" + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DIN5_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk" + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DIN6_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk" + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DIN7_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk" + bitOffset: 21 + bitWidth: 3 + access: read-write + - name: SPI_MEM_DINS_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk" + bitOffset: 24 + bitWidth: 3 + access: read-write + - register: + name: SPI_MEM_DIN_NUM + description: MSPI flash input timing delay number control register + addressOffset: 392 + size: 32 + fields: + - name: SPI_MEM_DIN0_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SPI_MEM_DIN1_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: SPI_MEM_DIN2_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: SPI_MEM_DIN3_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: SPI_MEM_DIN4_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: SPI_MEM_DIN5_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: SPI_MEM_DIN6_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: SPI_MEM_DIN7_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: SPI_MEM_DINS_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: SPI_MEM_DOUT_MODE + description: MSPI flash output timing adjustment control register + addressOffset: 396 + size: 32 + fields: + - name: SPI_MEM_DOUT0_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DOUT1_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DOUT2_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DOUT3_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DOUT4_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DOUT5_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DOUT6_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DOUT7_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_MEM_DOUTS_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk" + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: SPI_SMEM_TIMING_CALI + description: MSPI external RAM timing calibration register + addressOffset: 400 + size: 32 + resetValue: 1 + fields: + - name: SPI_SMEM_TIMING_CLK_ENA + description: "For sram, the bit is used to enable timing adjust clock for all reading operations." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_TIMING_CALI + description: "For sram, the bit is used to enable timing auto-calibration for all reading operations." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_EXTRA_DUMMY_CYCLELEN + description: "For sram, add extra dummy spi clock cycle length for spi clock calibration." + bitOffset: 2 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DLL_TIMING_CALI + description: Set this bit to enable DLL for timing calibration in DDR mode when accessed to EXT_RAM. + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: SPI_SMEM_DIN_MODE + description: MSPI external RAM input timing delay mode control register + addressOffset: 404 + size: 32 + fields: + - name: SPI_SMEM_DIN0_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DIN1_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DIN2_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DIN3_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DIN4_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DIN5_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DIN6_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DIN7_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 21 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DINS_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 24 + bitWidth: 3 + access: read-write + - register: + name: SPI_SMEM_DIN_NUM + description: MSPI external RAM input timing delay number control register + addressOffset: 408 + size: 32 + fields: + - name: SPI_SMEM_DIN0_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_DIN1_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_DIN2_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_DIN3_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_DIN4_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_DIN5_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_DIN6_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_DIN7_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_DINS_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: SPI_SMEM_DOUT_MODE + description: MSPI external RAM output timing adjustment control register + addressOffset: 412 + size: 32 + fields: + - name: SPI_SMEM_DOUT0_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DOUT1_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DOUT2_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DOUT3_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DOUT4_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DOUT5_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DOUT6_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DOUT7_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DOUTS_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: SPI_SMEM_AC + description: MSPI external RAM ECC and SPI CS timing control register + addressOffset: 416 + size: 32 + resetValue: 2147528836 + fields: + - name: SPI_SMEM_CS_SETUP + description: "For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_CS_HOLD + description: "For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_CS_SETUP_TIME + description: "For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit." + bitOffset: 2 + bitWidth: 5 + access: read-write + - name: SPI_SMEM_CS_HOLD_TIME + description: "For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit." + bitOffset: 7 + bitWidth: 5 + access: read-write + - name: SPI_SMEM_ECC_CS_HOLD_TIME + description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold cycles in ECC mode when accessed external RAM. + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_ECC_SKIP_PAGE_CORNER + description: "1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_ECC_16TO18_BYTE_EN + description: Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_CS_HOLD_DELAY + description: "These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles." + bitOffset: 25 + bitWidth: 6 + access: read-write + - name: SPI_SMEM_SPLIT_TRANS_EN + description: "Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter whether there is an ECC region or not." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_SMEM_DIN_HEX_MODE + description: MSPI 16x external RAM input timing delay mode control register + addressOffset: 420 + size: 32 + fields: + - name: SPI_SMEM_DIN08_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DIN09_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DIN10_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DIN11_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DIN12_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DIN13_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DIN14_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DIN15_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 21 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DINS_HEX_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge" + bitOffset: 24 + bitWidth: 3 + access: read-write + - register: + name: SPI_SMEM_DIN_HEX_NUM + description: MSPI 16x external RAM input timing delay number control register + addressOffset: 424 + size: 32 + fields: + - name: SPI_SMEM_DIN08_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_DIN09_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_DIN10_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_DIN11_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_DIN12_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_DIN13_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_DIN14_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_DIN15_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_DINS_HEX_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,..." + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: SPI_SMEM_DOUT_HEX_MODE + description: MSPI 16x external RAM output timing adjustment control register + addressOffset: 428 + size: 32 + fields: + - name: SPI_SMEM_DOUT08_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DOUT09_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DOUT10_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DOUT11_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DOUT12_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DOUT13_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DOUT14_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DOUT15_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DOUTS_HEX_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge" + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_CLOCK_GATE + description: SPI0 clock gate register + addressOffset: 512 + size: 32 + resetValue: 1 + fields: + - name: SPI_CLK_EN + description: "Register clock gate enable signal. 1: Enable. 0: Disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_XTS_PLAIN_BASE + description: The base address of the memory that stores plaintext in Manual Encryption + addressOffset: 768 + size: 32 + fields: + - name: SPI_XTS_PLAIN + description: This field is only used to generate include file in c case. This field is useless. Please do not use this field. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_XTS_LINESIZE + description: Manual Encryption Line-Size register + addressOffset: 832 + size: 32 + fields: + - name: SPI_XTS_LINESIZE + description: "This bits stores the line-size parameter which will be used in manual encryption calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: 32-bytes, 2: 64-bytes, 3:reserved." + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: SPI_MEM_XTS_DESTINATION + description: Manual Encryption destination register + addressOffset: 836 + size: 32 + fields: + - name: SPI_XTS_DESTINATION + description: "This bit stores the destination parameter which will be used in manual encryption calculation. 0: flash(default), 1: psram(reserved). Only default value can be used." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_XTS_PHYSICAL_ADDRESS + description: Manual Encryption physical address register + addressOffset: 840 + size: 32 + fields: + - name: SPI_XTS_PHYSICAL_ADDRESS + description: This bits stores the physical-address parameter which will be used in manual encryption calculation. This value should aligned with byte number decided by line-size parameter. + bitOffset: 0 + bitWidth: 26 + access: read-write + - register: + name: SPI_MEM_XTS_TRIGGER + description: Manual Encryption physical address register + addressOffset: 844 + size: 32 + fields: + - name: SPI_XTS_TRIGGER + description: "Set this bit to trigger the process of manual encryption calculation. This action should only be asserted when manual encryption status is 0. After this action, manual encryption status becomes 1. After calculation is done, manual encryption status becomes 2." + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_XTS_RELEASE + description: Manual Encryption physical address register + addressOffset: 848 + size: 32 + fields: + - name: SPI_XTS_RELEASE + description: "Set this bit to release encrypted result to mspi. This action should only be asserted when manual encryption status is 2. After this action, manual encryption status will become 3." + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_XTS_DESTROY + description: Manual Encryption physical address register + addressOffset: 852 + size: 32 + fields: + - name: SPI_XTS_DESTROY + description: "Set this bit to destroy encrypted result. This action should be asserted only when manual encryption status is 3. After this action, manual encryption status will become 0." + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_XTS_STATE + description: Manual Encryption physical address register + addressOffset: 856 + size: 32 + fields: + - name: SPI_XTS_STATE + description: "This bits stores the status of manual encryption. 0: idle, 1: busy of encryption calculation, 2: encryption calculation is done but the encrypted result is invisible to mspi, 3: the encrypted result is visible to mspi." + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: SPI_MEM_XTS_DATE + description: Manual Encryption version register + addressOffset: 860 + size: 32 + resetValue: 538972176 + fields: + - name: SPI_XTS_DATE + description: This bits stores the last modified-time of manual encryption feature. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: SPI_MEM_MMU_ITEM_CONTENT + description: MSPI-MMU item content register + addressOffset: 892 + size: 32 + resetValue: 892 + fields: + - name: SPI_MMU_ITEM_CONTENT + description: MSPI-MMU item content + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_MMU_ITEM_INDEX + description: MSPI-MMU item index register + addressOffset: 896 + size: 32 + fields: + - name: SPI_MMU_ITEM_INDEX + description: MSPI-MMU item index + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_MMU_POWER_CTRL + description: MSPI MMU power control register + addressOffset: 900 + size: 32 + resetValue: 320864260 + fields: + - name: SPI_MMU_MEM_FORCE_ON + description: Set this bit to enable mmu-memory clock force on + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MMU_MEM_FORCE_PD + description: Set this bit to force mmu-memory powerdown + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MMU_MEM_FORCE_PU + description: "Set this bit to force mmu-memory powerup, in this case, the power should also be controlled by rtc." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_AUX_CTRL + description: MMU PSRAM aux control register + bitOffset: 16 + bitWidth: 14 + access: read-write + - name: SPI_MEM_RDN_ENA + description: ECO register enable bit + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI_MEM_RDN_RESULT + description: MSPI module clock domain and AXI clock domain ECO register result register + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_DPA_CTRL + description: SPI memory cryption DPA register + addressOffset: 904 + size: 32 + resetValue: 15 + fields: + - name: SPI_CRYPT_SECURITY_LEVEL + description: "Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SPI_CRYPT_CALC_D_DPA_EN + description: "Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_CRYPT_DPA_SELECT_REGISTER + description: "1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits." + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_REGISTERRND_ECO_HIGH + description: MSPI ECO high register + addressOffset: 1008 + size: 32 + resetValue: 892 + fields: + - name: SPI_MEM_REGISTERRND_ECO_HIGH + description: ECO high register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_REGISTERRND_ECO_LOW + description: MSPI ECO low register + addressOffset: 1012 + size: 32 + resetValue: 892 + fields: + - name: SPI_MEM_REGISTERRND_ECO_LOW + description: ECO low register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_DATE + description: SPI0 version control register + addressOffset: 1020 + size: 32 + resetValue: 36712704 + fields: + - name: SPI_MEM_DATE + description: SPI0 register version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SPI1 + description: SPI (Serial Peripheral Interface) Controller 1 + groupName: SPI1 + baseAddress: 1342754816 + addressBlock: + - offset: 0 + size: 172 + usage: registers + registers: + - register: + name: SPI_MEM_CMD + description: SPI1 memory command register + addressOffset: 0 + size: 32 + fields: + - name: SPI_MEM_MST_ST + description: The current status of SPI1 master FSM. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: SPI_MEM_SLV_ST + description: "The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state." + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: SPI_MEM_FLASH_PE + description: "In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR + description: "User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_HPM + description: "Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_RES + description: "This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_DP + description: "Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_CE + description: "Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_BE + description: "Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_SE + description: "Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PP + description: "Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_WRSR + description: "Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_RDSR + description: "Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_RDID + description: "Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_WRDI + description: "Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_WREN + description: "Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_READ + description: "Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_ADDR + description: SPI1 address register + addressOffset: 4 + size: 32 + fields: + - name: SPI_MEM_USR_ADDR_VALUE + description: "In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_CTRL + description: SPI1 control register. + addressOffset: 8 + size: 32 + resetValue: 2924556 + fields: + - name: SPI_MEM_FDUMMY_RIN + description: "In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDUMMY_WOUT + description: "In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDOUT_OCT + description: "Apply 8 signals during write-data phase 1:enable 0: disable" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDIN_OCT + description: "Apply 8 signals during read-data phase 1:enable 0: disable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FADDR_OCT + description: "Apply 8 signals during address phase 1:enable 0: disable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FCMD_QUAD + description: "Apply 4 signals during command phase 1:enable 0: disable" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FCMD_OCT + description: "Apply 8 signals during command phase 1:enable 0: disable" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FCS_CRC_EN + description: "For SPI1, initialize crc32 module before writing encrypted data to flash. Active low." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SPI_MEM_TX_CRC_EN + description: "For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FASTRD_MODE + description: "This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FREAD_DUAL + description: "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SPI_MEM_RESANDRES + description: "The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI_MEM_Q_POL + description: "The bit is used to set MISO line polarity, 1: high 0, low" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SPI_MEM_D_POL + description: "The bit is used to set MOSI line polarity, 1: high 0, low" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FREAD_QUAD + description: "In the read operations read-data phase apply 4 signals. 1: enable 0: disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WP + description: "Write protect signal output when SPI is idle. 1: output high, 0: output low." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WRSR_2B + description: "two bytes data will be written to status register when it is set. 1: enable 0: disable." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FREAD_DIO + description: "In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FREAD_QIO + description: "In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_CTRL1 + description: SPI1 control1 register. + addressOffset: 12 + size: 32 + resetValue: 4092 + fields: + - name: SPI_MEM_CLK_MODE + description: "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SPI_MEM_CS_HOLD_DLY_RES + description: "After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles." + bitOffset: 2 + bitWidth: 10 + access: read-write + - register: + name: SPI_MEM_CTRL2 + description: SPI1 control2 register. + addressOffset: 16 + size: 32 + fields: + - name: SPI_MEM_SYNC_RESET + description: The FSM will be reset. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_CLOCK + description: SPI1 clock division control register. + addressOffset: 20 + size: 32 + resetValue: 196867 + fields: + - name: SPI_MEM_CLKCNT_L + description: In the master mode it must be equal to spi_mem_clkcnt_N. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SPI_MEM_CLKCNT_H + description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SPI_MEM_CLKCNT_N + description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1) + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SPI_MEM_CLK_EQU_SYSCLK + description: reserved + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_USER + description: SPI1 user register. + addressOffset: 24 + size: 32 + resetValue: 2147483648 + fields: + - name: SPI_MEM_CK_OUT_EDGE + description: the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FWRITE_DUAL + description: In the write operations read-data phase apply 2 signals + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FWRITE_QUAD + description: In the write operations read-data phase apply 4 signals + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FWRITE_DIO + description: In the write operations address phase and read-data phase apply 2 signals. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FWRITE_QIO + description: In the write operations address phase and read-data phase apply 4 signals. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_MISO_HIGHPART + description: "read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_MOSI_HIGHPART + description: "write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_DUMMY_IDLE + description: SPI clock is disable in dummy phase when the bit is enable. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_MOSI + description: This bit enable the write-data phase of an operation. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_MISO + description: This bit enable the read-data phase of an operation. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_DUMMY + description: This bit enable the dummy phase of an operation. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_ADDR + description: This bit enable the address phase of an operation. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI_MEM_USR_COMMAND + description: This bit enable the command phase of an operation. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_USER1 + description: SPI1 user1 register. + addressOffset: 28 + size: 32 + resetValue: 1543503879 + fields: + - name: SPI_MEM_USR_DUMMY_CYCLELEN + description: The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1). + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: SPI_MEM_USR_ADDR_BITLEN + description: The length in bits of address phase. The register value shall be (bit_num-1). + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: SPI_MEM_USER2 + description: SPI1 user2 register. + addressOffset: 32 + size: 32 + resetValue: 1879048192 + fields: + - name: SPI_MEM_USR_COMMAND_VALUE + description: The value of command. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SPI_MEM_USR_COMMAND_BITLEN + description: The length in bits of command phase. The register value shall be (bit_num-1) + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: SPI_MEM_MOSI_DLEN + description: SPI1 send data bit length control register. + addressOffset: 36 + size: 32 + fields: + - name: SPI_MEM_USR_MOSI_DBITLEN + description: The length in bits of write-data. The register value shall be (bit_num-1). + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: SPI_MEM_MISO_DLEN + description: SPI1 receive data bit length control register. + addressOffset: 40 + size: 32 + fields: + - name: SPI_MEM_USR_MISO_DBITLEN + description: The length in bits of read-data. The register value shall be (bit_num-1). + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: SPI_MEM_RD_STATUS + description: SPI1 status register. + addressOffset: 44 + size: 32 + fields: + - name: SPI_MEM_STATUS + description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SPI_MEM_WB_MODE + description: Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: SPI_MEM_MISC + description: SPI1 misc register + addressOffset: 52 + size: 32 + resetValue: 2 + fields: + - name: SPI_MEM_CS0_DIS + description: "SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CS1_DIS + description: "SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CK_IDLE_EDGE + description: "1: spi clk line is high when idle 0: spi clk line is low when idle" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_MEM_CS_KEEP_ACTIVE + description: spi cs line keep low when the bit is set. + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_TX_CRC + description: SPI1 TX CRC data register. + addressOffset: 56 + size: 32 + resetValue: 4294967295 + fields: + - name: DATA + description: "For SPI1, the value of crc32." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SPI_MEM_CACHE_FCTRL + description: SPI1 bit mode control register. + addressOffset: 60 + size: 32 + fields: + - name: SPI_MEM_CACHE_USR_ADDR_4BYTE + description: "For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDIN_DUAL + description: "For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDOUT_DUAL + description: "For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FADDR_DUAL + description: "For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDIN_QUAD + description: "For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FDOUT_QUAD + description: "For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FADDR_QUAD + description: "For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio." + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_W0 + description: SPI1 memory data buffer0 + addressOffset: 88 + size: 32 + fields: + - name: SPI_MEM_BUF0 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W1 + description: SPI1 memory data buffer1 + addressOffset: 92 + size: 32 + fields: + - name: SPI_MEM_BUF1 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W2 + description: SPI1 memory data buffer2 + addressOffset: 96 + size: 32 + fields: + - name: SPI_MEM_BUF2 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W3 + description: SPI1 memory data buffer3 + addressOffset: 100 + size: 32 + fields: + - name: SPI_MEM_BUF3 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W4 + description: SPI1 memory data buffer4 + addressOffset: 104 + size: 32 + fields: + - name: SPI_MEM_BUF4 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W5 + description: SPI1 memory data buffer5 + addressOffset: 108 + size: 32 + fields: + - name: SPI_MEM_BUF5 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W6 + description: SPI1 memory data buffer6 + addressOffset: 112 + size: 32 + fields: + - name: SPI_MEM_BUF6 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W7 + description: SPI1 memory data buffer7 + addressOffset: 116 + size: 32 + fields: + - name: SPI_MEM_BUF7 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W8 + description: SPI1 memory data buffer8 + addressOffset: 120 + size: 32 + fields: + - name: SPI_MEM_BUF8 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W9 + description: SPI1 memory data buffer9 + addressOffset: 124 + size: 32 + fields: + - name: SPI_MEM_BUF9 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W10 + description: SPI1 memory data buffer10 + addressOffset: 128 + size: 32 + fields: + - name: SPI_MEM_BUF10 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W11 + description: SPI1 memory data buffer11 + addressOffset: 132 + size: 32 + fields: + - name: SPI_MEM_BUF11 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W12 + description: SPI1 memory data buffer12 + addressOffset: 136 + size: 32 + fields: + - name: SPI_MEM_BUF12 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W13 + description: SPI1 memory data buffer13 + addressOffset: 140 + size: 32 + fields: + - name: SPI_MEM_BUF13 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W14 + description: SPI1 memory data buffer14 + addressOffset: 144 + size: 32 + fields: + - name: SPI_MEM_BUF14 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_W15 + description: SPI1 memory data buffer15 + addressOffset: 148 + size: 32 + fields: + - name: SPI_MEM_BUF15 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_MEM_FLASH_WAITI_CTRL + description: SPI1 wait idle control register + addressOffset: 152 + size: 32 + resetValue: 327681 + fields: + - name: SPI_MEM_WAITI_EN + description: "1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WAITI_DUMMY + description: The dummy phase enable when wait flash idle (RDSR) + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WAITI_ADDR_EN + description: "1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WAITI_ADDR_CYCLELEN + description: "When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared." + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: SPI_MEM_WAITI_CMD_2B + description: "1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WAITI_DUMMY_CYCLELEN + description: The dummy cycle length when wait flash idle(RDSR). + bitOffset: 10 + bitWidth: 6 + access: read-write + - name: SPI_MEM_WAITI_CMD + description: The command value to wait flash idle(RDSR). + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SPI_MEM_FLASH_SUS_CTRL + description: SPI1 flash suspend control register + addressOffset: 156 + size: 32 + resetValue: 134225920 + fields: + - name: SPI_MEM_FLASH_PER + description: "program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PES + description: "program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PER_WAIT_EN + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PES_WAIT_EN + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_PES_PER_EN + description: "Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PES_EN + description: Set this bit to enable Auto-suspending function. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_MEM_PESR_END_MSK + description: "The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0]." + bitOffset: 6 + bitWidth: 16 + access: read-write + - name: SPI_FMEM_RD_SUS_2B + description: "1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SPI_MEM_PER_END_EN + description: "1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SPI_MEM_PES_END_EN + description: "1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SUS_TIMEOUT_CNT + description: "When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass." + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: SPI_MEM_FLASH_SUS_CMD + description: SPI1 flash suspend command register + addressOffset: 160 + size: 32 + resetValue: 357749 + fields: + - name: SPI_MEM_FLASH_PES_COMMAND + description: Program/Erase suspend command. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SPI_MEM_WAIT_PESR_COMMAND + description: Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SPI_MEM_SUS_STATUS + description: SPI1 flash suspend status register + addressOffset: 164 + size: 32 + resetValue: 2054815744 + fields: + - name: SPI_MEM_FLASH_SUS + description: "The status of flash suspend, only used in SPI1." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WAIT_PESR_CMD_2B + description: "1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_HPM_DLY_128 + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_RES_DLY_128 + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_DP_DLY_128 + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PER_DLY_128 + description: "Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PES_DLY_128 + description: "Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SPI0_LOCK_EN + description: "1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PESR_CMD_2B + description: "1: The bit length of Program/Erase Suspend/Resume command is 16. 0: The bit length of Program/Erase Suspend/Resume command is 8." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI_MEM_FLASH_PER_COMMAND + description: Program/Erase resume command. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SPI_MEM_INT_ENA + description: SPI1 interrupt enable register + addressOffset: 192 + size: 32 + fields: + - name: SPI_MEM_PER_END_INT_ENA + description: The enable bit for SPI_MEM_PER_END_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_PES_END_INT_ENA + description: The enable bit for SPI_MEM_PES_END_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WPE_END_INT_ENA + description: The enable bit for SPI_MEM_WPE_END_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SLV_ST_END_INT_ENA + description: The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_MST_ST_END_INT_ENA + description: The enable bit for SPI_MEM_MST_ST_END_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_BROWN_OUT_INT_ENA + description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_INT_CLR + description: SPI1 interrupt clear register + addressOffset: 196 + size: 32 + fields: + - name: SPI_MEM_PER_END_INT_CLR + description: The clear bit for SPI_MEM_PER_END_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SPI_MEM_PES_END_INT_CLR + description: The clear bit for SPI_MEM_PES_END_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SPI_MEM_WPE_END_INT_CLR + description: The clear bit for SPI_MEM_WPE_END_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SPI_MEM_SLV_ST_END_INT_CLR + description: The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SPI_MEM_MST_ST_END_INT_CLR + description: The clear bit for SPI_MEM_MST_ST_END_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SPI_MEM_BROWN_OUT_INT_CLR + description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - register: + name: SPI_MEM_INT_RAW + description: SPI1 interrupt raw register + addressOffset: 200 + size: 32 + fields: + - name: SPI_MEM_PER_END_INT_RAW + description: "The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MEM_PES_END_INT_RAW + description: "The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_WPE_END_INT_RAW + description: "The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_MEM_SLV_ST_END_INT_RAW + description: "The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_MEM_MST_ST_END_INT_RAW + description: "The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_MEM_BROWN_OUT_INT_RAW + description: "The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others." + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_INT_ST + description: SPI1 interrupt status register + addressOffset: 204 + size: 32 + fields: + - name: SPI_MEM_PER_END_INT_ST + description: The status bit for SPI_MEM_PER_END_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_MEM_PES_END_INT_ST + description: The status bit for SPI_MEM_PES_END_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SPI_MEM_WPE_END_INT_ST + description: The status bit for SPI_MEM_WPE_END_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SPI_MEM_SLV_ST_END_INT_ST + description: The status bit for SPI_MEM_SLV_ST_END_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SPI_MEM_MST_ST_END_INT_ST + description: The status bit for SPI_MEM_MST_ST_END_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SPI_MEM_BROWN_OUT_INT_ST + description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - register: + name: SPI_MEM_DDR + description: SPI1 DDR control register + addressOffset: 212 + size: 32 + resetValue: 32 + fields: + - name: SPI_FMEM_DDR_EN + description: "1: in ddr mode, 0 in sdr mode" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_VAR_DUMMY + description: Set the bit to enable variable dummy cycle in spi ddr mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_DDR_RDAT_SWP + description: Set the bit to reorder rx data of the word in spi ddr mode. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_DDR_WDAT_SWP + description: Set the bit to reorder tx data of the word in spi ddr mode. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_DDR_CMD_DIS + description: the bit is used to disable dual edge in command phase when ddr mode. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_OUTMINBYTELEN + description: It is the minimum output data length in the panda device. + bitOffset: 5 + bitWidth: 7 + access: read-write + - name: SPI_FMEM_USR_DDR_DQS_THD + description: The delay number of data strobe which from memory based on SPI clock. + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: SPI_FMEM_DDR_DQS_LOOP + description: "1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_CLK_DIFF_EN + description: "Set this bit to enable the differential SPI_CLK#." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_DQS_CA_IN + description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_HYPERBUS_DUMMY_2X + description: "Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_CLK_DIFF_INV + description: Set this bit to invert SPI_DIFF when accesses to flash. . + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_OCTA_RAM_ADDR + description: "Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_HYPERBUS_CA + description: "Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}." + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_TIMING_CALI + description: SPI1 timing control register + addressOffset: 384 + size: 32 + fields: + - name: SPI_MEM_TIMING_CALI + description: The bit is used to enable timing auto-calibration for all reading operations. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MEM_EXTRA_DUMMY_CYCLELEN + description: add extra dummy spi clock cycle length for spi clock calibration. + bitOffset: 2 + bitWidth: 3 + access: read-write + - register: + name: SPI_MEM_CLOCK_GATE + description: SPI1 clk_gate register + addressOffset: 512 + size: 32 + resetValue: 1 + fields: + - name: SPI_MEM_CLK_EN + description: "Register clock gate enable signal. 1: Enable. 0: Disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_DATE + description: Version control register + addressOffset: 1020 + size: 32 + resetValue: 34673216 + fields: + - name: SPI_MEM_DATE + description: Version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SPI2 + description: SPI (Serial Peripheral Interface) Controller 2 + groupName: SPI2 + baseAddress: 1343029248 + addressBlock: + - offset: 0 + size: 152 + usage: registers + interrupt: + - name: SPI2 + value: 25 + registers: + - register: + name: SPI_CMD + description: Command control register + addressOffset: 0 + size: 32 + fields: + - name: SPI_CONF_BITLEN + description: Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 18 + access: read-write + - name: SPI_UPDATE + description: "Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode." + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: SPI_USR + description: "User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf." + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: SPI_ADDR + description: Address value register + addressOffset: 4 + size: 32 + fields: + - name: SPI_USR_ADDR_VALUE + description: Address to slave. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_CTRL + description: SPI control register + addressOffset: 8 + size: 32 + resetValue: 3932160 + fields: + - name: SPI_DUMMY_OUT + description: "0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_FADDR_DUAL + description: "Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_FADDR_QUAD + description: "Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_FADDR_OCT + description: "Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_FCMD_DUAL + description: "Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SPI_FCMD_QUAD + description: "Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_FCMD_OCT + description: "Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SPI_FREAD_DUAL + description: "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SPI_FREAD_QUAD + description: "In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI_FREAD_OCT + description: "In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SPI_Q_POL + description: "The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SPI_D_POL + description: "The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SPI_HOLD_POL + description: "SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SPI_WP_POL + description: "Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_RD_BIT_ORDER + description: "In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state." + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: SPI_WR_BIT_ORDER + description: "In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state." + bitOffset: 25 + bitWidth: 2 + access: read-write + - register: + name: SPI_CLOCK + description: SPI clock control register + addressOffset: 12 + size: 32 + resetValue: 2147496003 + fields: + - name: SPI_CLKCNT_L + description: In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: SPI_CLKCNT_H + description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: SPI_CLKCNT_N + description: In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + bitOffset: 12 + bitWidth: 6 + access: read-write + - name: SPI_CLKDIV_PRE + description: In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + bitOffset: 18 + bitWidth: 4 + access: read-write + - name: SPI_CLK_EQU_SYSCLK + description: "In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_USER + description: SPI USER control register + addressOffset: 16 + size: 32 + resetValue: 2147483840 + fields: + - name: SPI_DOUTDIN + description: "Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_QPI_MODE + description: "Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_OPI_MODE + description: "Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_TSCK_I_EDGE + description: "In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_CS_HOLD + description: "spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_CS_SETUP + description: "spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_RSCK_I_EDGE + description: "In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SPI_CK_OUT_EDGE + description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_FWRITE_DUAL + description: In the write operations read-data phase apply 2 signals. Can be configured in CONF state. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SPI_FWRITE_QUAD + description: In the write operations read-data phase apply 4 signals. Can be configured in CONF state. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SPI_FWRITE_OCT + description: In the write operations read-data phase apply 8 signals. Can be configured in CONF state. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SPI_USR_CONF_NXT + description: "1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI_SIO + description: "Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SPI_USR_MISO_HIGHPART + description: "read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_USR_MOSI_HIGHPART + description: "write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: SPI_USR_DUMMY_IDLE + description: spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI_USR_MOSI + description: This bit enable the write-data phase of an operation. Can be configured in CONF state. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SPI_USR_MISO + description: This bit enable the read-data phase of an operation. Can be configured in CONF state. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SPI_USR_DUMMY + description: This bit enable the dummy phase of an operation. Can be configured in CONF state. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SPI_USR_ADDR + description: This bit enable the address phase of an operation. Can be configured in CONF state. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI_USR_COMMAND + description: This bit enable the command phase of an operation. Can be configured in CONF state. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_USER1 + description: SPI USER control register 1 + addressOffset: 20 + size: 32 + resetValue: 3091267591 + fields: + - name: SPI_USR_DUMMY_CYCLELEN + description: The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SPI_MST_WFULL_ERR_END_EN + description: "1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SPI_CS_SETUP_TIME + description: (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. + bitOffset: 17 + bitWidth: 5 + access: read-write + - name: SPI_CS_HOLD_TIME + description: delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. + bitOffset: 22 + bitWidth: 5 + access: read-write + - name: SPI_USR_ADDR_BITLEN + description: The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: SPI_USER2 + description: SPI USER control register 2 + addressOffset: 24 + size: 32 + resetValue: 2013265920 + fields: + - name: SPI_USR_COMMAND_VALUE + description: The value of command. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SPI_MST_REMPTY_ERR_END_EN + description: "1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SPI_USR_COMMAND_BITLEN + description: The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: SPI_MS_DLEN + description: SPI data bit length control register + addressOffset: 28 + size: 32 + fields: + - name: SPI_MS_DATA_BITLEN + description: The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 0 + bitWidth: 18 + access: read-write + - register: + name: SPI_MISC + description: SPI misc register + addressOffset: 32 + size: 32 + resetValue: 62 + fields: + - name: SPI_CS0_DIS + description: "SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_CS1_DIS + description: "SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_CS2_DIS + description: "SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_CS3_DIS + description: "SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_CS4_DIS + description: "SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_CS5_DIS + description: "SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_CK_DIS + description: "1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MASTER_CS_POL + description: "In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: SPI_CLK_DATA_DTR_EN + description: "1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SPI_DATA_DTR_EN + description: "1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SPI_ADDR_DTR_EN + description: "1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SPI_CMD_DTR_EN + description: "1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SPI_SLAVE_CS_POL + description: "spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SPI_DQS_IDLE_EDGE + description: The default value of spi_dqs. Can be configured in CONF state. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_CK_IDLE_EDGE + description: "1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SPI_CS_KEEP_ACTIVE + description: spi cs line keep low when the bit is set. Can be configured in CONF state. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI_QUAD_DIN_PIN_SWAP + description: "1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_DIN_MODE + description: SPI input delay mode configuration + addressOffset: 36 + size: 32 + fields: + - name: SPI_DIN0_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SPI_DIN1_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: SPI_DIN2_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: SPI_DIN3_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: SPI_DIN4_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: SPI_DIN5_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: SPI_DIN6_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: SPI_DIN7_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: SPI_TIMING_HCLK_ACTIVE + description: "1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state." + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: SPI_DIN_NUM + description: SPI input delay number configuration + addressOffset: 40 + size: 32 + fields: + - name: SPI_DIN0_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SPI_DIN1_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: SPI_DIN2_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: SPI_DIN3_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: SPI_DIN4_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: SPI_DIN5_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: SPI_DIN6_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: SPI_DIN7_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: SPI_DOUT_MODE + description: SPI output delay mode configuration + addressOffset: 44 + size: 32 + fields: + - name: SPI_DOUT0_MODE + description: "The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_DOUT1_MODE + description: "The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_DOUT2_MODE + description: "The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_DOUT3_MODE + description: "The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_DOUT4_MODE + description: "The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_DOUT5_MODE + description: "The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_DOUT6_MODE + description: "The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_DOUT7_MODE + description: "The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_D_DQS_MODE + description: "The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: SPI_DMA_CONF + description: SPI DMA control register + addressOffset: 48 + size: 32 + resetValue: 3 + fields: + - name: SPI_DMA_OUTFIFO_EMPTY + description: "Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_DMA_INFIFO_FULL + description: "Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SPI_DMA_SLV_SEG_TRANS_EN + description: "Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SPI_SLV_RX_SEG_TRANS_CLR_EN + description: "1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SPI_SLV_TX_SEG_TRANS_CLR_EN + description: "1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SPI_RX_EOF_EN + description: "1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_DMA_RX_ENA + description: Set this bit to enable SPI DMA controlled receive data mode. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SPI_DMA_TX_ENA + description: Set this bit to enable SPI DMA controlled send data mode. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SPI_RX_AFIFO_RST + description: "Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer." + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: SPI_BUF_AFIFO_RST + description: "Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer." + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: SPI_DMA_AFIFO_RST + description: "Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer." + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SPI_DMA_INT_ENA + description: SPI interrupt enable register + addressOffset: 52 + size: 32 + fields: + - name: SPI_DMA_INFIFO_FULL_ERR_INT_ENA + description: The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA + description: The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_SLV_EX_QPI_INT_ENA + description: The enable bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_SLV_EN_QPI_INT_ENA + description: The enable bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_SLV_CMD7_INT_ENA + description: The enable bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_SLV_CMD8_INT_ENA + description: The enable bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_SLV_CMD9_INT_ENA + description: The enable bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_SLV_CMDA_INT_ENA + description: The enable bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_SLV_RD_DMA_DONE_INT_ENA + description: The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SPI_SLV_WR_DMA_DONE_INT_ENA + description: The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_SLV_RD_BUF_DONE_INT_ENA + description: The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SPI_SLV_WR_BUF_DONE_INT_ENA + description: The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SPI_TRANS_DONE_INT_ENA + description: The enable bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SPI_DMA_SEG_TRANS_DONE_INT_ENA + description: The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SPI_SEG_MAGIC_ERR_INT_ENA + description: The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SPI_SLV_BUF_ADDR_ERR_INT_ENA + description: The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI_SLV_CMD_ERR_INT_ENA + description: The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA + description: The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA + description: The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SPI_APP2_INT_ENA + description: The enable bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SPI_APP1_INT_ENA + description: The enable bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: SPI_DMA_INT_CLR + description: SPI interrupt clear register + addressOffset: 56 + size: 32 + fields: + - name: SPI_DMA_INFIFO_FULL_ERR_INT_CLR + description: The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR + description: The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SPI_SLV_EX_QPI_INT_CLR + description: The clear bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SPI_SLV_EN_QPI_INT_CLR + description: The clear bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SPI_SLV_CMD7_INT_CLR + description: The clear bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SPI_SLV_CMD8_INT_CLR + description: The clear bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: SPI_SLV_CMD9_INT_CLR + description: The clear bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: SPI_SLV_CMDA_INT_CLR + description: The clear bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SPI_SLV_RD_DMA_DONE_INT_CLR + description: The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SPI_SLV_WR_DMA_DONE_INT_CLR + description: The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SPI_SLV_RD_BUF_DONE_INT_CLR + description: The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SPI_SLV_WR_BUF_DONE_INT_CLR + description: The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: SPI_TRANS_DONE_INT_CLR + description: The clear bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: SPI_DMA_SEG_TRANS_DONE_INT_CLR + description: The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SPI_SEG_MAGIC_ERR_INT_CLR + description: The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SPI_SLV_BUF_ADDR_ERR_INT_CLR + description: The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: SPI_SLV_CMD_ERR_INT_CLR + description: The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR + description: The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR + description: The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: SPI_APP2_INT_CLR + description: The clear bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: SPI_APP1_INT_CLR + description: The clear bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: write-only + - register: + name: SPI_DMA_INT_RAW + description: SPI interrupt raw register + addressOffset: 60 + size: 32 + fields: + - name: SPI_DMA_INFIFO_FULL_ERR_INT_RAW + description: "1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW + description: "1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_SLV_EX_QPI_INT_RAW + description: "The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_SLV_EN_QPI_INT_RAW + description: "The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_SLV_CMD7_INT_RAW + description: "The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_SLV_CMD8_INT_RAW + description: "The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_SLV_CMD9_INT_RAW + description: "The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_SLV_CMDA_INT_RAW + description: "The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_SLV_RD_DMA_DONE_INT_RAW + description: "The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SPI_SLV_WR_DMA_DONE_INT_RAW + description: "The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_SLV_RD_BUF_DONE_INT_RAW + description: "The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SPI_SLV_WR_BUF_DONE_INT_RAW + description: "The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SPI_TRANS_DONE_INT_RAW + description: "The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SPI_DMA_SEG_TRANS_DONE_INT_RAW + description: "The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SPI_SEG_MAGIC_ERR_INT_RAW + description: "The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SPI_SLV_BUF_ADDR_ERR_INT_RAW + description: "The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI_SLV_CMD_ERR_INT_RAW + description: "The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW + description: "The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW + description: "The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SPI_APP2_INT_RAW + description: The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SPI_APP1_INT_RAW + description: The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: SPI_DMA_INT_ST + description: SPI interrupt status register + addressOffset: 64 + size: 32 + fields: + - name: SPI_DMA_INFIFO_FULL_ERR_INT_ST + description: The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST + description: The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SPI_SLV_EX_QPI_INT_ST + description: The status bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SPI_SLV_EN_QPI_INT_ST + description: The status bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SPI_SLV_CMD7_INT_ST + description: The status bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SPI_SLV_CMD8_INT_ST + description: The status bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SPI_SLV_CMD9_INT_ST + description: The status bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SPI_SLV_CMDA_INT_ST + description: The status bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SPI_SLV_RD_DMA_DONE_INT_ST + description: The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SPI_SLV_WR_DMA_DONE_INT_ST + description: The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SPI_SLV_RD_BUF_DONE_INT_ST + description: The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SPI_SLV_WR_BUF_DONE_INT_ST + description: The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: SPI_TRANS_DONE_INT_ST + description: The status bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SPI_DMA_SEG_TRANS_DONE_INT_ST + description: The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SPI_SEG_MAGIC_ERR_INT_ST + description: The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SPI_SLV_BUF_ADDR_ERR_INT_ST + description: The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SPI_SLV_CMD_ERR_INT_ST + description: The status bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST + description: The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST + description: The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: SPI_APP2_INT_ST + description: The status bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: SPI_APP1_INT_ST + description: The status bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: read-only + - register: + name: SPI_DMA_INT_SET + description: SPI interrupt software set register + addressOffset: 68 + size: 32 + fields: + - name: SPI_DMA_INFIFO_FULL_ERR_INT_SET + description: The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET + description: The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SPI_SLV_EX_QPI_INT_SET + description: The software set bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SPI_SLV_EN_QPI_INT_SET + description: The software set bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SPI_SLV_CMD7_INT_SET + description: The software set bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SPI_SLV_CMD8_INT_SET + description: The software set bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: SPI_SLV_CMD9_INT_SET + description: The software set bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: SPI_SLV_CMDA_INT_SET + description: The software set bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SPI_SLV_RD_DMA_DONE_INT_SET + description: The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SPI_SLV_WR_DMA_DONE_INT_SET + description: The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SPI_SLV_RD_BUF_DONE_INT_SET + description: The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SPI_SLV_WR_BUF_DONE_INT_SET + description: The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: SPI_TRANS_DONE_INT_SET + description: The software set bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: SPI_DMA_SEG_TRANS_DONE_INT_SET + description: The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SPI_SEG_MAGIC_ERR_INT_SET + description: The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SPI_SLV_BUF_ADDR_ERR_INT_SET + description: The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: SPI_SLV_CMD_ERR_INT_SET + description: The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET + description: The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET + description: The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: SPI_APP2_INT_SET + description: The software set bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: SPI_APP1_INT_SET + description: The software set bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: write-only + - register: + name: SPI_W0 + description: SPI CPU-controlled buffer0 + addressOffset: 152 + size: 32 + fields: + - name: SPI_BUF0 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W1 + description: SPI CPU-controlled buffer1 + addressOffset: 156 + size: 32 + fields: + - name: SPI_BUF1 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W2 + description: SPI CPU-controlled buffer2 + addressOffset: 160 + size: 32 + fields: + - name: SPI_BUF2 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W3 + description: SPI CPU-controlled buffer3 + addressOffset: 164 + size: 32 + fields: + - name: SPI_BUF3 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W4 + description: SPI CPU-controlled buffer4 + addressOffset: 168 + size: 32 + fields: + - name: SPI_BUF4 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W5 + description: SPI CPU-controlled buffer5 + addressOffset: 172 + size: 32 + fields: + - name: SPI_BUF5 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W6 + description: SPI CPU-controlled buffer6 + addressOffset: 176 + size: 32 + fields: + - name: SPI_BUF6 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W7 + description: SPI CPU-controlled buffer7 + addressOffset: 180 + size: 32 + fields: + - name: SPI_BUF7 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W8 + description: SPI CPU-controlled buffer8 + addressOffset: 184 + size: 32 + fields: + - name: SPI_BUF8 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W9 + description: SPI CPU-controlled buffer9 + addressOffset: 188 + size: 32 + fields: + - name: SPI_BUF9 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W10 + description: SPI CPU-controlled buffer10 + addressOffset: 192 + size: 32 + fields: + - name: SPI_BUF10 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W11 + description: SPI CPU-controlled buffer11 + addressOffset: 196 + size: 32 + fields: + - name: SPI_BUF11 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W12 + description: SPI CPU-controlled buffer12 + addressOffset: 200 + size: 32 + fields: + - name: SPI_BUF12 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W13 + description: SPI CPU-controlled buffer13 + addressOffset: 204 + size: 32 + fields: + - name: SPI_BUF13 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W14 + description: SPI CPU-controlled buffer14 + addressOffset: 208 + size: 32 + fields: + - name: SPI_BUF14 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W15 + description: SPI CPU-controlled buffer15 + addressOffset: 212 + size: 32 + fields: + - name: SPI_BUF15 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_SLAVE + description: SPI slave control register + addressOffset: 224 + size: 32 + resetValue: 41943040 + fields: + - name: SPI_CLK_MODE + description: "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SPI_CLK_MODE_13 + description: "{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_RSCK_DATA_OUT + description: "It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_SLV_RDDMA_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SPI_SLV_WRDMA_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_SLV_RDBUF_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SPI_SLV_WRBUF_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SPI_SLV_LAST_BYTE_STRB + description: Represents the effective bit of the last received data byte in SPI slave FD and HD mode. + bitOffset: 12 + bitWidth: 8 + access: read-only + - name: SPI_DMA_SEG_MAGIC_VALUE + description: The magic value of BM table in master DMA seg-trans. + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: MODE + description: "Set SPI work mode. 1: slave mode 0: master mode." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI_SOFT_RESET + description: "Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state." + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: SPI_USR_CONF + description: "1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SPI_MST_FD_WAIT_DMA_TX_DATA + description: "In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer." + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: SPI_SLAVE1 + description: SPI slave control register 1 + addressOffset: 228 + size: 32 + fields: + - name: SPI_SLV_DATA_BITLEN + description: The transferred data bit length in SPI slave FD and HD mode. + bitOffset: 0 + bitWidth: 18 + access: read-write + - name: SPI_SLV_LAST_COMMAND + description: In the slave mode it is the value of command. + bitOffset: 18 + bitWidth: 8 + access: read-write + - name: SPI_SLV_LAST_ADDR + description: In the slave mode it is the value of address. + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: SPI_CLK_GATE + description: SPI module clock and register clock control + addressOffset: 232 + size: 32 + fields: + - name: SPI_CLK_EN + description: Set this bit to enable clk gate + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MST_CLK_ACTIVE + description: Set this bit to power on the SPI module clock. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MST_CLK_SEL + description: "This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: SPI_DATE + description: Version control + addressOffset: 240 + size: 32 + resetValue: 35680770 + fields: + - name: SPI_DATE + description: SPI register version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SPI3 + description: SPI (Serial Peripheral Interface) Controller 3 + groupName: SPI3 + baseAddress: 1343033344 + addressBlock: + - offset: 0 + size: 152 + usage: registers + interrupt: + - name: SPI3 + value: 26 + registers: + - register: + name: SPI_CMD + description: Command control register + addressOffset: 0 + size: 32 + fields: + - name: SPI_UPDATE + description: "Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode." + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: SPI_USR + description: "User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf." + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: SPI_ADDR + description: Address value register + addressOffset: 4 + size: 32 + fields: + - name: SPI_USR_ADDR_VALUE + description: Address to slave. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_CTRL + description: SPI control register + addressOffset: 8 + size: 32 + resetValue: 3932160 + fields: + - name: SPI_DUMMY_OUT + description: "0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_FADDR_DUAL + description: "Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_FADDR_QUAD + description: "Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_FCMD_DUAL + description: "Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SPI_FCMD_QUAD + description: "Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_FREAD_DUAL + description: "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SPI_FREAD_QUAD + description: "In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI_Q_POL + description: "The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SPI_D_POL + description: "The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SPI_HOLD_POL + description: "SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SPI_WP_POL + description: "Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_RD_BIT_ORDER + description: "In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state." + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: SPI_WR_BIT_ORDER + description: "In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state." + bitOffset: 25 + bitWidth: 2 + access: read-write + - register: + name: SPI_CLOCK + description: SPI clock control register + addressOffset: 12 + size: 32 + resetValue: 2147496003 + fields: + - name: SPI_CLKCNT_L + description: In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: SPI_CLKCNT_H + description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: SPI_CLKCNT_N + description: In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + bitOffset: 12 + bitWidth: 6 + access: read-write + - name: SPI_CLKDIV_PRE + description: In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + bitOffset: 18 + bitWidth: 4 + access: read-write + - name: SPI_CLK_EQU_SYSCLK + description: "In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_USER + description: SPI USER control register + addressOffset: 16 + size: 32 + resetValue: 2147483840 + fields: + - name: SPI_DOUTDIN + description: "Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_QPI_MODE + description: "Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_TSCK_I_EDGE + description: "In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_CS_HOLD + description: "spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_CS_SETUP + description: "spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_RSCK_I_EDGE + description: "In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SPI_CK_OUT_EDGE + description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_FWRITE_DUAL + description: In the write operations read-data phase apply 2 signals. Can be configured in CONF state. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SPI_FWRITE_QUAD + description: In the write operations read-data phase apply 4 signals. Can be configured in CONF state. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SPI_SIO + description: "Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SPI_USR_MISO_HIGHPART + description: "read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_USR_MOSI_HIGHPART + description: "write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: SPI_USR_DUMMY_IDLE + description: spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI_USR_MOSI + description: This bit enable the write-data phase of an operation. Can be configured in CONF state. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SPI_USR_MISO + description: This bit enable the read-data phase of an operation. Can be configured in CONF state. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SPI_USR_DUMMY + description: This bit enable the dummy phase of an operation. Can be configured in CONF state. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SPI_USR_ADDR + description: This bit enable the address phase of an operation. Can be configured in CONF state. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI_USR_COMMAND + description: This bit enable the command phase of an operation. Can be configured in CONF state. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_USER1 + description: SPI USER control register 1 + addressOffset: 20 + size: 32 + resetValue: 3091267591 + fields: + - name: SPI_USR_DUMMY_CYCLELEN + description: The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SPI_MST_WFULL_ERR_END_EN + description: "1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SPI_CS_SETUP_TIME + description: (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. + bitOffset: 17 + bitWidth: 5 + access: read-write + - name: SPI_CS_HOLD_TIME + description: delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. + bitOffset: 22 + bitWidth: 5 + access: read-write + - name: SPI_USR_ADDR_BITLEN + description: The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: SPI_USER2 + description: SPI USER control register 2 + addressOffset: 24 + size: 32 + resetValue: 2013265920 + fields: + - name: SPI_USR_COMMAND_VALUE + description: The value of command. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SPI_MST_REMPTY_ERR_END_EN + description: "1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SPI_USR_COMMAND_BITLEN + description: The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: SPI_MS_DLEN + description: SPI data bit length control register + addressOffset: 28 + size: 32 + fields: + - name: SPI_MS_DATA_BITLEN + description: The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 0 + bitWidth: 18 + access: read-write + - register: + name: SPI_MISC + description: SPI misc register + addressOffset: 32 + size: 32 + resetValue: 6 + fields: + - name: SPI_CS0_DIS + description: "SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_CS1_DIS + description: "SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_CS2_DIS + description: "SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_CK_DIS + description: "1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_MASTER_CS_POL + description: "In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: SPI_SLAVE_CS_POL + description: "spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SPI_CK_IDLE_EDGE + description: "1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SPI_CS_KEEP_ACTIVE + description: spi cs line keep low when the bit is set. Can be configured in CONF state. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI_QUAD_DIN_PIN_SWAP + description: "1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SPI_DIN_MODE + description: SPI input delay mode configuration + addressOffset: 36 + size: 32 + fields: + - name: SPI_DIN0_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SPI_DIN1_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: SPI_DIN2_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: SPI_DIN3_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: SPI_TIMING_HCLK_ACTIVE + description: "1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state." + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: SPI_DIN_NUM + description: SPI input delay number configuration + addressOffset: 40 + size: 32 + fields: + - name: SPI_DIN0_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SPI_DIN1_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: SPI_DIN2_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: SPI_DIN3_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 6 + bitWidth: 2 + access: read-write + - register: + name: SPI_DOUT_MODE + description: SPI output delay mode configuration + addressOffset: 44 + size: 32 + fields: + - name: SPI_DOUT0_MODE + description: "The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_DOUT1_MODE + description: "The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_DOUT2_MODE + description: "The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_DOUT3_MODE + description: "The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: SPI_DMA_CONF + description: SPI DMA control register + addressOffset: 48 + size: 32 + resetValue: 3 + fields: + - name: SPI_DMA_OUTFIFO_EMPTY + description: "Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_DMA_INFIFO_FULL + description: "Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SPI_DMA_SLV_SEG_TRANS_EN + description: "Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SPI_SLV_RX_SEG_TRANS_CLR_EN + description: "1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SPI_SLV_TX_SEG_TRANS_CLR_EN + description: "1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SPI_RX_EOF_EN + description: "1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_DMA_RX_ENA + description: Set this bit to enable SPI DMA controlled receive data mode. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SPI_DMA_TX_ENA + description: Set this bit to enable SPI DMA controlled send data mode. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SPI_RX_AFIFO_RST + description: "Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer." + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: SPI_BUF_AFIFO_RST + description: "Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer." + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: SPI_DMA_AFIFO_RST + description: "Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer." + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SPI_DMA_INT_ENA + description: SPI interrupt enable register + addressOffset: 52 + size: 32 + fields: + - name: SPI_DMA_INFIFO_FULL_ERR_INT_ENA + description: The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA + description: The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_SLV_EX_QPI_INT_ENA + description: The enable bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_SLV_EN_QPI_INT_ENA + description: The enable bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_SLV_CMD7_INT_ENA + description: The enable bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_SLV_CMD8_INT_ENA + description: The enable bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_SLV_CMD9_INT_ENA + description: The enable bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_SLV_CMDA_INT_ENA + description: The enable bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_SLV_RD_DMA_DONE_INT_ENA + description: The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SPI_SLV_WR_DMA_DONE_INT_ENA + description: The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_SLV_RD_BUF_DONE_INT_ENA + description: The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SPI_SLV_WR_BUF_DONE_INT_ENA + description: The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SPI_TRANS_DONE_INT_ENA + description: The enable bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SPI_DMA_SEG_TRANS_DONE_INT_ENA + description: The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SPI_SLV_BUF_ADDR_ERR_INT_ENA + description: The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI_SLV_CMD_ERR_INT_ENA + description: The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA + description: The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA + description: The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SPI_APP2_INT_ENA + description: The enable bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SPI_APP1_INT_ENA + description: The enable bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: SPI_DMA_INT_CLR + description: SPI interrupt clear register + addressOffset: 56 + size: 32 + fields: + - name: SPI_DMA_INFIFO_FULL_ERR_INT_CLR + description: The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR + description: The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SPI_SLV_EX_QPI_INT_CLR + description: The clear bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SPI_SLV_EN_QPI_INT_CLR + description: The clear bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SPI_SLV_CMD7_INT_CLR + description: The clear bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SPI_SLV_CMD8_INT_CLR + description: The clear bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: SPI_SLV_CMD9_INT_CLR + description: The clear bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: SPI_SLV_CMDA_INT_CLR + description: The clear bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SPI_SLV_RD_DMA_DONE_INT_CLR + description: The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SPI_SLV_WR_DMA_DONE_INT_CLR + description: The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SPI_SLV_RD_BUF_DONE_INT_CLR + description: The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SPI_SLV_WR_BUF_DONE_INT_CLR + description: The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: SPI_TRANS_DONE_INT_CLR + description: The clear bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: SPI_DMA_SEG_TRANS_DONE_INT_CLR + description: The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SPI_SLV_BUF_ADDR_ERR_INT_CLR + description: The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: SPI_SLV_CMD_ERR_INT_CLR + description: The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR + description: The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR + description: The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: SPI_APP2_INT_CLR + description: The clear bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: SPI_APP1_INT_CLR + description: The clear bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: write-only + - register: + name: SPI_DMA_INT_RAW + description: SPI interrupt raw register + addressOffset: 60 + size: 32 + fields: + - name: SPI_DMA_INFIFO_FULL_ERR_INT_RAW + description: "1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW + description: "1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_SLV_EX_QPI_INT_RAW + description: "The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_SLV_EN_QPI_INT_RAW + description: "The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_SLV_CMD7_INT_RAW + description: "The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_SLV_CMD8_INT_RAW + description: "The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_SLV_CMD9_INT_RAW + description: "The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_SLV_CMDA_INT_RAW + description: "The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_SLV_RD_DMA_DONE_INT_RAW + description: "The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SPI_SLV_WR_DMA_DONE_INT_RAW + description: "The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_SLV_RD_BUF_DONE_INT_RAW + description: "The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SPI_SLV_WR_BUF_DONE_INT_RAW + description: "The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SPI_TRANS_DONE_INT_RAW + description: "The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SPI_DMA_SEG_TRANS_DONE_INT_RAW + description: "The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SPI_SLV_BUF_ADDR_ERR_INT_RAW + description: "The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI_SLV_CMD_ERR_INT_RAW + description: "The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW + description: "The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW + description: "The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SPI_APP2_INT_RAW + description: The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SPI_APP1_INT_RAW + description: The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: SPI_DMA_INT_ST + description: SPI interrupt status register + addressOffset: 64 + size: 32 + fields: + - name: SPI_DMA_INFIFO_FULL_ERR_INT_ST + description: The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST + description: The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SPI_SLV_EX_QPI_INT_ST + description: The status bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SPI_SLV_EN_QPI_INT_ST + description: The status bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SPI_SLV_CMD7_INT_ST + description: The status bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SPI_SLV_CMD8_INT_ST + description: The status bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SPI_SLV_CMD9_INT_ST + description: The status bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SPI_SLV_CMDA_INT_ST + description: The status bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SPI_SLV_RD_DMA_DONE_INT_ST + description: The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SPI_SLV_WR_DMA_DONE_INT_ST + description: The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SPI_SLV_RD_BUF_DONE_INT_ST + description: The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SPI_SLV_WR_BUF_DONE_INT_ST + description: The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: SPI_TRANS_DONE_INT_ST + description: The status bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SPI_DMA_SEG_TRANS_DONE_INT_ST + description: The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SPI_SLV_BUF_ADDR_ERR_INT_ST + description: The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SPI_SLV_CMD_ERR_INT_ST + description: The status bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST + description: The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST + description: The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: SPI_APP2_INT_ST + description: The status bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: SPI_APP1_INT_ST + description: The status bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: read-only + - register: + name: SPI_DMA_INT_SET + description: SPI interrupt software set register + addressOffset: 68 + size: 32 + fields: + - name: SPI_DMA_INFIFO_FULL_ERR_INT_SET + description: The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SPI_DMA_OUTFIFO_EMPTY_ERR_INT_SET + description: The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SPI_SLV_EX_QPI_INT_SET + description: The software set bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SPI_SLV_EN_QPI_INT_SET + description: The software set bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SPI_SLV_CMD7_INT_SET + description: The software set bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SPI_SLV_CMD8_INT_SET + description: The software set bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: SPI_SLV_CMD9_INT_SET + description: The software set bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: SPI_SLV_CMDA_INT_SET + description: The software set bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SPI_SLV_RD_DMA_DONE_INT_SET + description: The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SPI_SLV_WR_DMA_DONE_INT_SET + description: The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SPI_SLV_RD_BUF_DONE_INT_SET + description: The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SPI_SLV_WR_BUF_DONE_INT_SET + description: The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: SPI_TRANS_DONE_INT_SET + description: The software set bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: SPI_DMA_SEG_TRANS_DONE_INT_SET + description: The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SPI_SLV_BUF_ADDR_ERR_INT_SET + description: The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: SPI_SLV_CMD_ERR_INT_SET + description: The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: SPI_MST_RX_AFIFO_WFULL_ERR_INT_SET + description: The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: SPI_MST_TX_AFIFO_REMPTY_ERR_INT_SET + description: The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: SPI_APP2_INT_SET + description: The software set bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: SPI_APP1_INT_SET + description: The software set bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: write-only + - register: + name: SPI_W0 + description: SPI CPU-controlled buffer0 + addressOffset: 152 + size: 32 + fields: + - name: SPI_BUF0 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W1 + description: SPI CPU-controlled buffer1 + addressOffset: 156 + size: 32 + fields: + - name: SPI_BUF1 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W2 + description: SPI CPU-controlled buffer2 + addressOffset: 160 + size: 32 + fields: + - name: SPI_BUF2 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W3 + description: SPI CPU-controlled buffer3 + addressOffset: 164 + size: 32 + fields: + - name: SPI_BUF3 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W4 + description: SPI CPU-controlled buffer4 + addressOffset: 168 + size: 32 + fields: + - name: SPI_BUF4 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W5 + description: SPI CPU-controlled buffer5 + addressOffset: 172 + size: 32 + fields: + - name: SPI_BUF5 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W6 + description: SPI CPU-controlled buffer6 + addressOffset: 176 + size: 32 + fields: + - name: SPI_BUF6 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W7 + description: SPI CPU-controlled buffer7 + addressOffset: 180 + size: 32 + fields: + - name: SPI_BUF7 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W8 + description: SPI CPU-controlled buffer8 + addressOffset: 184 + size: 32 + fields: + - name: SPI_BUF8 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W9 + description: SPI CPU-controlled buffer9 + addressOffset: 188 + size: 32 + fields: + - name: SPI_BUF9 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W10 + description: SPI CPU-controlled buffer10 + addressOffset: 192 + size: 32 + fields: + - name: SPI_BUF10 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W11 + description: SPI CPU-controlled buffer11 + addressOffset: 196 + size: 32 + fields: + - name: SPI_BUF11 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W12 + description: SPI CPU-controlled buffer12 + addressOffset: 200 + size: 32 + fields: + - name: SPI_BUF12 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W13 + description: SPI CPU-controlled buffer13 + addressOffset: 204 + size: 32 + fields: + - name: SPI_BUF13 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W14 + description: SPI CPU-controlled buffer14 + addressOffset: 208 + size: 32 + fields: + - name: SPI_BUF14 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_W15 + description: SPI CPU-controlled buffer15 + addressOffset: 212 + size: 32 + fields: + - name: SPI_BUF15 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SPI_SLAVE + description: SPI slave control register + addressOffset: 224 + size: 32 + fields: + - name: SPI_CLK_MODE + description: "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SPI_CLK_MODE_13 + description: "{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_RSCK_DATA_OUT + description: "It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_SLV_RDDMA_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SPI_SLV_WRDMA_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SPI_SLV_RDBUF_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SPI_SLV_WRBUF_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SPI_SLV_LAST_BYTE_STRB + description: Represents the effective bit of the last received data byte in SPI slave FD and HD mode. + bitOffset: 12 + bitWidth: 8 + access: read-only + - name: MODE + description: "Set SPI work mode. 1: slave mode 0: master mode." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI_SOFT_RESET + description: "Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state." + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: SPI_MST_FD_WAIT_DMA_TX_DATA + description: "In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer." + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: SPI_SLAVE1 + description: SPI slave control register 1 + addressOffset: 228 + size: 32 + fields: + - name: SPI_SLV_DATA_BITLEN + description: The transferred data bit length in SPI slave FD and HD mode. + bitOffset: 0 + bitWidth: 18 + access: read-write + - name: SPI_SLV_LAST_COMMAND + description: In the slave mode it is the value of command. + bitOffset: 18 + bitWidth: 8 + access: read-write + - name: SPI_SLV_LAST_ADDR + description: In the slave mode it is the value of address. + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: SPI_CLK_GATE + description: SPI module clock and register clock control + addressOffset: 232 + size: 32 + fields: + - name: SPI_CLK_EN + description: Set this bit to enable clk gate + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_MST_CLK_ACTIVE + description: Set this bit to power on the SPI module clock. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_MST_CLK_SEL + description: "This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: SPI_DATE + description: Version control + addressOffset: 240 + size: 32 + resetValue: 35680770 + fields: + - name: SPI_DATE + description: SPI register version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SYSTIMER + description: System Timer + groupName: SYSTIMER + baseAddress: 1343102976 + addressBlock: + - offset: 0 + size: 144 + usage: registers + interrupt: + - name: SYSTIMER_TARGET0 + value: 53 + - name: SYSTIMER_TARGET1 + value: 54 + - name: SYSTIMER_TARGET2 + value: 55 + registers: + - register: + name: CONF + description: Configure system timer clock + addressOffset: 0 + size: 32 + resetValue: 1174405120 + fields: + - name: SYSTIMER_CLK_FO + description: systimer clock force on + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ETM_EN + description: "enable systimer's etm task and event" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TARGET2_WORK_EN + description: target2 work enable + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TARGET1_WORK_EN + description: target1 work enable + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TARGET0_WORK_EN + description: target0 work enable + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT1_CORE1_STALL_EN + description: If timer unit1 is stalled when core1 stalled + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT1_CORE0_STALL_EN + description: If timer unit1 is stalled when core0 stalled + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT0_CORE1_STALL_EN + description: If timer unit0 is stalled when core1 stalled + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT0_CORE0_STALL_EN + description: If timer unit0 is stalled when core0 stalled + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT1_WORK_EN + description: timer unit1 work enable + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT0_WORK_EN + description: timer unit0 work enable + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: register file clk gating + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: UNIT0_OP + description: system timer unit0 value update register + addressOffset: 4 + size: 32 + fields: + - name: TIMER_UNIT0_VALUE_VALID + description: timer value is sync and valid + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: TIMER_UNIT0_UPDATE + description: update timer_unit0 + bitOffset: 30 + bitWidth: 1 + access: write-only + - register: + name: UNIT1_OP + description: system timer unit1 value update register + addressOffset: 8 + size: 32 + fields: + - name: TIMER_UNIT1_VALUE_VALID + description: timer value is sync and valid + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: TIMER_UNIT1_UPDATE + description: update timer unit1 + bitOffset: 30 + bitWidth: 1 + access: write-only + - register: + name: UNIT0_LOAD_HI + description: system timer unit0 value high load register + addressOffset: 12 + size: 32 + fields: + - name: TIMER_UNIT0_LOAD_HI + description: timer unit0 load high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: UNIT0_LOAD_LO + description: system timer unit0 value low load register + addressOffset: 16 + size: 32 + fields: + - name: TIMER_UNIT0_LOAD_LO + description: timer unit0 load low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: UNIT1_LOAD_HI + description: system timer unit1 value high load register + addressOffset: 20 + size: 32 + fields: + - name: TIMER_UNIT1_LOAD_HI + description: timer unit1 load high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: UNIT1_LOAD_LO + description: system timer unit1 value low load register + addressOffset: 24 + size: 32 + fields: + - name: TIMER_UNIT1_LOAD_LO + description: timer unit1 load low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET0_HI + description: system timer comp0 value high register + addressOffset: 28 + size: 32 + fields: + - name: TIMER_TARGET0_HI + description: timer taget0 high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: TARGET0_LO + description: system timer comp0 value low register + addressOffset: 32 + size: 32 + fields: + - name: TIMER_TARGET0_LO + description: timer taget0 low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET1_HI + description: system timer comp1 value high register + addressOffset: 36 + size: 32 + fields: + - name: TIMER_TARGET1_HI + description: timer taget1 high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: TARGET1_LO + description: system timer comp1 value low register + addressOffset: 40 + size: 32 + fields: + - name: TIMER_TARGET1_LO + description: timer taget1 low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET2_HI + description: system timer comp2 value high register + addressOffset: 44 + size: 32 + fields: + - name: TIMER_TARGET2_HI + description: timer taget2 high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: TARGET2_LO + description: system timer comp2 value low register + addressOffset: 48 + size: 32 + fields: + - name: TIMER_TARGET2_LO + description: timer taget2 low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET0_CONF + description: system timer comp0 target mode register + addressOffset: 52 + size: 32 + fields: + - name: TARGET0_PERIOD + description: target0 period + bitOffset: 0 + bitWidth: 26 + access: read-write + - name: TARGET0_PERIOD_MODE + description: Set target0 to period mode + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TARGET0_TIMER_UNIT_SEL + description: select which unit to compare + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TARGET1_CONF + description: system timer comp1 target mode register + addressOffset: 56 + size: 32 + fields: + - name: TARGET1_PERIOD + description: target1 period + bitOffset: 0 + bitWidth: 26 + access: read-write + - name: TARGET1_PERIOD_MODE + description: Set target1 to period mode + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TARGET1_TIMER_UNIT_SEL + description: select which unit to compare + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TARGET2_CONF + description: system timer comp2 target mode register + addressOffset: 60 + size: 32 + fields: + - name: TARGET2_PERIOD + description: target2 period + bitOffset: 0 + bitWidth: 26 + access: read-write + - name: TARGET2_PERIOD_MODE + description: Set target2 to period mode + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TARGET2_TIMER_UNIT_SEL + description: select which unit to compare + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: UNIT0_VALUE_HI + description: system timer unit0 value high register + addressOffset: 64 + size: 32 + fields: + - name: TIMER_UNIT0_VALUE_HI + description: timer read value high 20bits + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: UNIT0_VALUE_LO + description: system timer unit0 value low register + addressOffset: 68 + size: 32 + fields: + - name: TIMER_UNIT0_VALUE_LO + description: timer read value low 32bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: UNIT1_VALUE_HI + description: system timer unit1 value high register + addressOffset: 72 + size: 32 + fields: + - name: TIMER_UNIT1_VALUE_HI + description: timer read value high 20bits + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: UNIT1_VALUE_LO + description: system timer unit1 value low register + addressOffset: 76 + size: 32 + fields: + - name: TIMER_UNIT1_VALUE_LO + description: timer read value low 32bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: COMP0_LOAD + description: system timer comp0 conf sync register + addressOffset: 80 + size: 32 + fields: + - name: TIMER_COMP0_LOAD + description: timer comp0 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: COMP1_LOAD + description: system timer comp1 conf sync register + addressOffset: 84 + size: 32 + fields: + - name: TIMER_COMP1_LOAD + description: timer comp1 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: COMP2_LOAD + description: system timer comp2 conf sync register + addressOffset: 88 + size: 32 + fields: + - name: TIMER_COMP2_LOAD + description: timer comp2 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: UNIT0_LOAD + description: system timer unit0 conf sync register + addressOffset: 92 + size: 32 + fields: + - name: TIMER_UNIT0_LOAD + description: timer unit0 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: UNIT1_LOAD + description: system timer unit1 conf sync register + addressOffset: 96 + size: 32 + fields: + - name: TIMER_UNIT1_LOAD + description: timer unit1 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + description: systimer interrupt enable register + addressOffset: 100 + size: 32 + fields: + - name: TARGET0_INT_ENA + description: interupt0 enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TARGET1_INT_ENA + description: interupt1 enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TARGET2_INT_ENA + description: interupt2 enable + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: systimer interrupt raw register + addressOffset: 104 + size: 32 + fields: + - name: TARGET0_INT_RAW + description: interupt0 raw + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TARGET1_INT_RAW + description: interupt1 raw + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TARGET2_INT_RAW + description: interupt2 raw + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: systimer interrupt clear register + addressOffset: 108 + size: 32 + fields: + - name: TARGET0_INT_CLR + description: interupt0 clear + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TARGET1_INT_CLR + description: interupt1 clear + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TARGET2_INT_CLR + description: interupt2 clear + bitOffset: 2 + bitWidth: 1 + access: write-only + - register: + name: INT_ST + description: systimer interrupt status register + addressOffset: 112 + size: 32 + fields: + - name: TARGET0_INT_ST + description: interupt0 status + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TARGET1_INT_ST + description: interupt1 status + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TARGET2_INT_ST + description: interupt2 status + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: REAL_TARGET0_LO + description: system timer comp0 actual target value low register + addressOffset: 116 + size: 32 + fields: + - name: TARGET0_LO_RO + description: actual target value value low 32bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: REAL_TARGET0_HI + description: system timer comp0 actual target value high register + addressOffset: 120 + size: 32 + fields: + - name: TARGET0_HI_RO + description: actual target value value high 20bits + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: REAL_TARGET1_LO + description: system timer comp1 actual target value low register + addressOffset: 124 + size: 32 + fields: + - name: TARGET1_LO_RO + description: actual target value value low 32bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: REAL_TARGET1_HI + description: system timer comp1 actual target value high register + addressOffset: 128 + size: 32 + fields: + - name: TARGET1_HI_RO + description: actual target value value high 20bits + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: REAL_TARGET2_LO + description: system timer comp2 actual target value low register + addressOffset: 132 + size: 32 + fields: + - name: TARGET2_LO_RO + description: actual target value value low 32bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: REAL_TARGET2_HI + description: system timer comp2 actual target value high register + addressOffset: 136 + size: 32 + fields: + - name: TARGET2_HI_RO + description: actual target value value high 20bits + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: DATE + description: system timer version control register + addressOffset: 252 + size: 32 + resetValue: 35655795 + fields: + - name: DATE + description: systimer register version + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: TIMG0 + description: Timer Group 0 + groupName: TIMG + baseAddress: 1342971904 + addressBlock: + - offset: 0 + size: 140 + usage: registers + interrupt: + - name: TG0_T0 + value: 46 + - name: TG0_T1 + value: 47 + - name: TG0_WDT + value: 48 + registers: + - register: + dim: 2 + dimIncrement: 36 + name: T%sCONFIG + description: Timer %s configuration register + addressOffset: 0 + size: 32 + resetValue: 1610620928 + fields: + - name: USE_XTAL + description: "1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: ALARM_EN + description: "When set, the alarm is enabled. This bit is automatically cleared once an\nalarm occurs." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DIVCNT_RST + description: "When set, Timer %s 's clock divider counter will be reset." + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: DIVIDER + description: Timer %s clock (T%s_clk) prescaler value. + bitOffset: 13 + bitWidth: 16 + access: read-write + - name: AUTORELOAD + description: "When set, timer %s auto-reload at alarm is enabled." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: INCREASE + description: "When set, the timer %s time-base counter will increment every clock tick. When\ncleared, the timer %s time-base counter will decrement." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: EN + description: "When set, the timer %s time-base counter is enabled." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + dim: 2 + dimIncrement: 36 + name: T%sLO + description: "Timer %s current value, low 32 bits" + addressOffset: 4 + size: 32 + fields: + - name: LO + description: "After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter\nof timer %s can be read here." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + dim: 2 + dimIncrement: 36 + name: T%sHI + description: "Timer %s current value, high 22 bits" + addressOffset: 8 + size: 32 + fields: + - name: HI + description: "After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter\nof timer %s can be read here." + bitOffset: 0 + bitWidth: 22 + access: read-only + - register: + dim: 2 + dimIncrement: 36 + name: T%sUPDATE + description: Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG + addressOffset: 12 + size: 32 + fields: + - name: UPDATE + description: "After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + dim: 2 + dimIncrement: 36 + name: T%sALARMLO + description: "Timer %s alarm value, low 32 bits" + addressOffset: 16 + size: 32 + fields: + - name: ALARM_LO + description: "Timer %s alarm trigger time-base counter value, low 32 bits." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 2 + dimIncrement: 36 + name: T%sALARMHI + description: "Timer %s alarm value, high bits" + addressOffset: 20 + size: 32 + fields: + - name: ALARM_HI + description: "Timer %s alarm trigger time-base counter value, high 22 bits." + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + dim: 2 + dimIncrement: 36 + name: T%sLOADLO + description: "Timer %s reload value, low 32 bits" + addressOffset: 24 + size: 32 + fields: + - name: LOAD_LO + description: "Low 32 bits of the value that a reload will load onto timer %s time-base\nCounter." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 2 + dimIncrement: 36 + name: T%sLOADHI + description: "Timer %s reload value, high 22 bits" + addressOffset: 28 + size: 32 + fields: + - name: LOAD_HI + description: "High 22 bits of the value that a reload will load onto timer %s time-base\ncounter." + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + dim: 2 + dimIncrement: 36 + name: T%sLOAD + description: Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG + addressOffset: 32 + size: 32 + fields: + - name: LOAD + description: Write any value to trigger a timer %s time-base counter reload. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: WDTCONFIG0 + description: Watchdog timer configuration register + addressOffset: 72 + size: 32 + resetValue: 311296 + fields: + - name: WDT_APPCPU_RESET_EN + description: WDT reset CPU enable. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: WDT_PROCPU_RESET_EN + description: WDT reset CPU enable. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: WDT_FLASHBOOT_MOD_EN + description: "When set, Flash boot protection is enabled." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: WDT_SYS_RESET_LENGTH + description: "System reset signal length selection. 0: 100 ns, 1: 200 ns,\n2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us." + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: WDT_CPU_RESET_LENGTH + description: "CPU reset signal length selection. 0: 100 ns, 1: 200 ns,\n2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us." + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: WDT_USE_XTAL + description: "choose WDT clock:0-apb_clk, 1-xtal_clk." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: WDT_CONF_UPDATE_EN + description: update the WDT configuration registers + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: WDT_STG3 + description: "Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system." + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: WDT_STG2 + description: "Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system." + bitOffset: 25 + bitWidth: 2 + access: read-write + - name: WDT_STG1 + description: "Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system." + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: WDT_STG0 + description: "Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system." + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: WDT_EN + description: "When set, MWDT is enabled." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: WDTCONFIG1 + description: Watchdog timer prescaler register + addressOffset: 76 + size: 32 + resetValue: 65536 + fields: + - name: WDT_DIVCNT_RST + description: "When set, WDT 's clock divider counter will be reset." + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: WDT_CLK_PRESCALE + description: "MWDT clock prescaler value. MWDT clock period = 12.5 ns *\nTIMG_WDT_CLK_PRESCALE." + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: WDTCONFIG2 + description: Watchdog timer stage 0 timeout value + addressOffset: 80 + size: 32 + resetValue: 26000000 + fields: + - name: WDT_STG0_HOLD + description: "Stage 0 timeout value, in MWDT clock cycles." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG3 + description: Watchdog timer stage 1 timeout value + addressOffset: 84 + size: 32 + resetValue: 134217727 + fields: + - name: WDT_STG1_HOLD + description: "Stage 1 timeout value, in MWDT clock cycles." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG4 + description: Watchdog timer stage 2 timeout value + addressOffset: 88 + size: 32 + resetValue: 1048575 + fields: + - name: WDT_STG2_HOLD + description: "Stage 2 timeout value, in MWDT clock cycles." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG5 + description: Watchdog timer stage 3 timeout value + addressOffset: 92 + size: 32 + resetValue: 1048575 + fields: + - name: WDT_STG3_HOLD + description: "Stage 3 timeout value, in MWDT clock cycles." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTFEED + description: Write to feed the watchdog timer + addressOffset: 96 + size: 32 + fields: + - name: WDT_FEED + description: Write any value to feed the MWDT. (WO) + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: WDTWPROTECT + description: Watchdog write protect register + addressOffset: 100 + size: 32 + resetValue: 1356348065 + fields: + - name: WDT_WKEY + description: "If the register contains a different value than its reset value, write\nprotection is enabled." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RTCCALICFG + description: RTC calibration configure register + addressOffset: 104 + size: 32 + resetValue: 69632 + fields: + - name: RTC_CALI_START_CYCLING + description: "0: one-shot frequency calculation,1: periodic frequency calculation," + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RTC_CALI_CLK_SEL + description: "0:rtc slow clock. 1:clk_8m, 2:xtal_32k." + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: RTC_CALI_RDY + description: indicate one-shot frequency calculation is done. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: RTC_CALI_MAX + description: "Configure the time to calculate RTC slow clock's frequency." + bitOffset: 16 + bitWidth: 15 + access: read-write + - name: RTC_CALI_START + description: Set this bit to start one-shot frequency calculation. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RTCCALICFG1 + description: RTC calibration configure1 register + addressOffset: 108 + size: 32 + fields: + - name: RTC_CALI_CYCLING_DATA_VLD + description: indicate periodic frequency calculation is done. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RTC_CALI_VALUE + description: "When one-shot or periodic frequency calculation is done, read this value to calculate RTC slow clock's frequency." + bitOffset: 7 + bitWidth: 25 + access: read-only + - register: + name: INT_ENA_TIMERS + description: Interrupt enable bits + addressOffset: 112 + size: 32 + fields: + - name: T0_INT_ENA + description: The interrupt enable bit for the TIMG_T0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: T1_INT_ENA + description: The interrupt enable bit for the TIMG_T1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: WDT_INT_ENA + description: The interrupt enable bit for the TIMG_WDT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW_TIMERS + description: Raw interrupt status + addressOffset: 116 + size: 32 + fields: + - name: T0_INT_RAW + description: The raw interrupt status bit for the TIMG_T0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: T1_INT_RAW + description: The raw interrupt status bit for the TIMG_T1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: WDT_INT_RAW + description: The raw interrupt status bit for the TIMG_WDT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: INT_ST_TIMERS + description: Masked interrupt status + addressOffset: 120 + size: 32 + fields: + - name: T0_INT_ST + description: The masked interrupt status bit for the TIMG_T0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: T1_INT_ST + description: The masked interrupt status bit for the TIMG_T1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: WDT_INT_ST + description: The masked interrupt status bit for the TIMG_WDT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR_TIMERS + description: Interrupt clear bits + addressOffset: 124 + size: 32 + fields: + - name: T0_INT_CLR + description: Set this bit to clear the TIMG_T0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: T1_INT_CLR + description: Set this bit to clear the TIMG_T1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: WDT_INT_CLR + description: Set this bit to clear the TIMG_WDT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - register: + name: RTCCALICFG2 + description: Timer group calibration register + addressOffset: 128 + size: 32 + resetValue: 4294967192 + fields: + - name: RTC_CALI_TIMEOUT + description: RTC calibration timeout indicator + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RTC_CALI_TIMEOUT_RST_CNT + description: Cycles that release calibration timeout reset + bitOffset: 3 + bitWidth: 4 + access: read-write + - name: RTC_CALI_TIMEOUT_THRES + description: "Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered." + bitOffset: 7 + bitWidth: 25 + access: read-write + - register: + name: NTIMERS_DATE + description: Timer version control register + addressOffset: 248 + size: 32 + resetValue: 35688770 + fields: + - name: NTIMGS_DATE + description: Timer version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + name: REGCLK + description: Timer group clock gate register + addressOffset: 252 + size: 32 + resetValue: 1879048192 + fields: + - name: ETM_EN + description: "enable timer's etm task and event" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: WDT_CLK_IS_ACTIVE + description: "enable WDT's clock" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TIMER_CLK_IS_ACTIVE + description: "enable Timer 30's clock" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software." + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: TIMG1 + description: Timer Group 1 + baseAddress: 1342976000 + interrupt: + - name: TG1_T0 + value: 49 + - name: TG1_T1 + value: 50 + - name: TG1_WDT + value: 51 + derivedFrom: TIMG0 + - name: TRACE0 + description: TRACE0 Peripheral + groupName: TRACE + baseAddress: 1072709632 + addressBlock: + - offset: 0 + size: 76 + usage: registers + registers: + - register: + name: MEM_START_ADDR + description: mem start addr + addressOffset: 0 + size: 32 + fields: + - name: MEM_START_ADDR + description: The start address of trace memory + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: MEM_END_ADDR + description: mem end addr + addressOffset: 4 + size: 32 + resetValue: 4294967295 + fields: + - name: MEM_END_ADDR + description: The end address of trace memory + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: MEM_CURRENT_ADDR + description: mem current addr + addressOffset: 8 + size: 32 + fields: + - name: MEM_CURRENT_ADDR + description: "current_mem_addr,indicate that next writing addr" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: MEM_ADDR_UPDATE + description: mem addr update + addressOffset: 12 + size: 32 + fields: + - name: MEM_CURRENT_ADDR_UPDATE + description: "when set, the will \\hyperref[fielddesc:TRACEMEMCURRENTADDR]{TRACE_MEM_CURRENT_ADDR} update to \\hyperref[fielddesc:TRACEMEMSTARTADDR]{TRACE_MEM_START_ADDR}." + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: FIFO_STATUS + description: fifo status register + addressOffset: 16 + size: 32 + resetValue: 1 + fields: + - name: FIFO_EMPTY + description: "Represent whether the fifo is empty. \\\\1: empty \\\\0: not empty" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: WORK_STATUS + description: "Represent trace work status: \\\\0: idle state \\\\1: working state\\\\ 2: wait state due to hart halted or havereset \\\\3: lost state" + bitOffset: 1 + bitWidth: 2 + access: read-only + - register: + name: INTR_ENA + description: interrupt enable register + addressOffset: 20 + size: 32 + fields: + - name: FIFO_OVERFLOW_INTR_ENA + description: Set 1 enable fifo_overflow interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_FULL_INTR_ENA + description: Set 1 enable mem_full interrupt + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INTR_RAW + description: interrupt status register + addressOffset: 24 + size: 32 + fields: + - name: FIFO_OVERFLOW_INTR_RAW + description: fifo_overflow interrupt status + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: MEM_FULL_INTR_RAW + description: mem_full interrupt status + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INTR_CLR + description: interrupt clear register + addressOffset: 28 + size: 32 + fields: + - name: FIFO_OVERFLOW_INTR_CLR + description: Set 1 clear fifo overflow interrupt + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: MEM_FULL_INTR_CLR + description: Set 1 clear mem full interrupt + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: TRIGGER + description: trigger register + addressOffset: 32 + size: 32 + resetValue: 12 + fields: + - name: "ON" + description: "Configure whether or not start trace.\\\\1: start trace \\\\0: invalid\\\\" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: "OFF" + description: "Configure whether or not stop trace.\\\\1: stop trace \\\\0: invalid\\\\" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: MEM_LOOP + description: "Configure memory loop mode. \\\\1: trace will loop wrtie trace_mem. \\\\0: when mem_current_addr at mem_end_addr, it will stop at the mem_end_addr\\\\" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RESTART_ENA + description: "Configure whether or not enable auto-restart.\\\\1: enable\\\\0: disable\\\\" + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: CONFIG + description: trace configuration register + addressOffset: 36 + size: 32 + fields: + - name: DM_TRIGGER_ENA + description: "Configure whether or not enable cpu trigger action.\\\\1: enable\\\\0:disable\\\\" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RESET_ENA + description: "Configure whether or not enable trace cpu haverest, when enabeld, if cpu have reset, the encoder will output a packet to report the address of the last instruction, and upon reset deassertion, the encoder start again.\\\\1: enabeld\\\\0: disabled\\\\" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: HALT_ENA + description: "Configure whether or not enable trace cpu is halted, when enabeld, if the cpu halted, the encoder will output a packet to report the address of the last instruction, and upon halted deassertion, the encoder start again.When disabled, encoder will not report the last address before halted and first address after halted, cpu halted information will not be tracked. \\\\1: enabeld\\\\0: disabled\\\\" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: STALL_ENA + description: "Configure whether or not enable stall cpu. When enabled, when the fifo almost full, the cpu will be stalled until the packets is able to write to fifo.\\\\1: enabled.\\\\0: disabled\\\\" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FULL_ADDRESS + description: "Configure whether or not enable full-address mode.\\\\1: full address mode.\\\\0: delta address mode\\\\" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IMPLICIT_EXCEPT + description: "Configure whether or not enabel implicit exception mode. When enabled,, do not sent exception address, only exception cause in exception packets.\\\\1: enabled\\\\0: disabled\\\\" + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: FILTER_CONTROL + description: filter control register + addressOffset: 40 + size: 32 + fields: + - name: FILTER_EN + description: "Configure whether or not enable filter unit. \\\\1: enable filter.\\\\ 0: always match" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MATCH_COMP + description: "when set, the comparator must be high in order for the filter to match" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MATCH_PRIVILEGE + description: "when set, match privilege levels specified by \\hyperref[fielddesc:TRACEMATCHCHOICEPRIVILEGE]{TRACE_MATCH_CHOICE_PRIVILEGE}." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MATCH_ECAUSE + description: "when set, start matching from exception cause codes specified by \\hyperref[fielddesc:TRACEMATCHCHOICEECAUSE]{TRACE_MATCH_CHOICE_ECAUSE}, and stop matching upon return from the 1st matching exception." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MATCH_INTERRUPT + description: "when set, start matching from a trap with the interrupt level codes specified by \\hyperref[fielddesc:TRACEMATCHVALUEINTERRUPT]{TRACE_MATCH_VALUE_INTERRUPT}, and stop matching upon return from the 1st matching trap." + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: FILTER_MATCH_CONTROL + description: filter match control register + addressOffset: 44 + size: 32 + fields: + - name: MATCH_CHOICE_PRIVILEGE + description: "Select match which privilege level when \\hyperref[fielddesc:TRACEMATCHPRIVILEGE]{TRACE_MATCH_PRIVILEGE} is set. \\\\1: machine mode. \\\\0: user mode" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MATCH_VALUE_INTERRUPT + description: "Select which match which itype when \\hyperref[fielddesc:TRACEMATCHINTERRUPT]{TRACE_MATCH_INTERRUP} is set. \\\\1: match itype of 2. \\\\0: match itype or 1." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MATCH_CHOICE_ECAUSE + description: specified which ecause matched. + bitOffset: 2 + bitWidth: 6 + access: read-write + - register: + name: FILTER_COMPARATOR_CONTROL + description: filter comparator match control register + addressOffset: 48 + size: 32 + fields: + - name: P_INPUT + description: "Determines which input to compare against the primary comparator, \\\\0: iaddr, \\\\1: tval." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: P_FUNCTION + description: "Select the primary comparator function. \\\\0: equal, \\\\1: not equal, \\\\2: less than, \\\\3: less than or equal, \\\\4: greater than, \\\\5: greater than or equal, \\\\other: always match" + bitOffset: 2 + bitWidth: 3 + access: read-write + - name: P_NOTIFY + description: Generate a trace packet explicitly reporting the address that cause the primary match + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: S_INPUT + description: "Determines which input to compare against the secondary comparator, \\\\0: iaddr, \\\\1: tval." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: S_FUNCTION + description: "Select the secondary comparator function. \\\\0: equal, \\\\1: not equal, \\\\2: less than, \\\\3: less than or equal, \\\\4: greater than, \\\\5: greater than or equal, \\\\other: always match" + bitOffset: 10 + bitWidth: 3 + access: read-write + - name: S_NOTIFY + description: Generate a trace packet explicitly reporting the address that cause the secondary match + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: MATCH_MODE + description: "0: only primary matches, \\\\1: primary and secondary comparator both matches(P\\&\\&S),\\\\ 2:either primary or secondary comparator matches !(P\\&\\&S), \\\\3: set when primary matches and continue to match until after secondary comparator matches" + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: FILTER_P_COMPARATOR_MATCH + description: primary comparator match value + addressOffset: 52 + size: 32 + fields: + - name: P_MATCH + description: primary comparator match value + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FILTER_S_COMPARATOR_MATCH + description: secondary comparator match value + addressOffset: 56 + size: 32 + fields: + - name: S_MATCH + description: secondary comparator match value + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RESYNC_PROLONGED + description: resync configuration register + addressOffset: 60 + size: 32 + resetValue: 128 + fields: + - name: RESYNC_PROLONGED + description: "count number, when count to this value, send a sync package" + bitOffset: 0 + bitWidth: 24 + access: read-write + - name: RESYNC_MODE + description: "resyc mode sel: \\\\0: off, \\\\2: cycle count \\\\3: package num count" + bitOffset: 24 + bitWidth: 2 + access: read-write + - register: + name: AHB_CONFIG + description: AHB config register + addressOffset: 64 + size: 32 + fields: + - name: HBURST + description: set hburst + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: MAX_INCR + description: set max continuous access for incr mode + bitOffset: 3 + bitWidth: 3 + access: read-write + - register: + name: CLOCK_GATE + description: Clock gate control register + addressOffset: 68 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: The bit is used to enable clock gate when access all registers in this module. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 1020 + size: 32 + resetValue: 35721984 + fields: + - name: DATE + description: version control register. Note that this default value stored is the latest date when the hardware logic was updated. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: TRACE1 + description: TRACE1 Peripheral + baseAddress: 1072713728 + derivedFrom: TRACE0 + - name: LP_TSENS + description: Low-power Temperature Sensor + groupName: TSENS + baseAddress: 1343418368 + addressBlock: + - offset: 0 + size: 56 + usage: registers + interrupt: + - name: LP_TSENS + value: 15 + registers: + - register: + name: CTRL + description: Tsens configuration. + addressOffset: 0 + size: 32 + resetValue: 103424 + fields: + - name: OUT + description: Temperature sensor data out. + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: READY + description: Indicate temperature sensor out ready. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SAMPLE_EN + description: Enable sample signal for wakeup module. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: WAKEUP_MASK + description: Wake up signal mask. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: INT_EN + description: Enable temperature sensor to send out interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: IN_INV + description: Invert temperature sensor data. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: CLK_DIV + description: Temperature sensor clock divider. + bitOffset: 14 + bitWidth: 8 + access: read-write + - name: POWER_UP + description: Temperature sensor power up. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: POWER_UP_FORCE + description: "1: dump out & power up controlled by SW, 0: by FSM." + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: CTRL2 + description: Tsens configuration. + addressOffset: 4 + size: 32 + resetValue: 16386 + fields: + - name: XPD_WAIT + description: N/A + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: XPD_FORCE + description: N/A + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CLK_INV + description: N/A + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: Tsens interrupt raw registers. + addressOffset: 8 + size: 32 + fields: + - name: COCPU_TSENS_WAKE_INT_RAW + description: Tsens wakeup interrupt raw. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Tsens interrupt status registers. + addressOffset: 12 + size: 32 + fields: + - name: COCPU_TSENS_WAKE_INT_ST + description: Tsens wakeup interrupt status. + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Tsens interrupt enable registers. + addressOffset: 16 + size: 32 + fields: + - name: COCPU_TSENS_WAKE_INT_ENA + description: Tsens wakeup interrupt enable. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Tsens interrupt clear registers. + addressOffset: 20 + size: 32 + fields: + - name: COCPU_TSENS_WAKE_INT_CLR + description: Tsens wakeup interrupt clear. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: CLK_CONF + description: Tsens regbank configuration registers. + addressOffset: 24 + size: 32 + fields: + - name: CLK_EN + description: Tsens regbank clock gating enable. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: INT_ENA_W1TS + description: Tsens wakeup interrupt enable assert. + addressOffset: 28 + size: 32 + fields: + - name: COCPU_TSENS_WAKE_INT_ENA_W1TS + description: Write 1 to this field to assert interrupt enable. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA_W1TC + description: Tsens wakeup interrupt enable deassert. + addressOffset: 32 + size: 32 + fields: + - name: COCPU_TSENS_WAKE_INT_ENA_W1TC + description: Write 1 to this field to deassert interrupt enable. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: WAKEUP_CTRL + description: Tsens wakeup control registers. + addressOffset: 36 + size: 32 + resetValue: 4177920 + fields: + - name: WAKEUP_TH_LOW + description: Lower threshold. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: WAKEUP_TH_HIGH + description: Upper threshold. + bitOffset: 14 + bitWidth: 8 + access: read-write + - name: WAKEUP_OVER_UPPER_TH + description: Indicates that this wakeup event arose from exceeding upper threshold. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: WAKEUP_EN + description: Tsens wakeup enable. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: WAKEUP_MODE + description: "0:absolute value comparison mode. 1: relative value comparison mode." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAMPLE_RATE + description: Hardware automatic sampling control registers. + addressOffset: 40 + size: 32 + resetValue: 20 + fields: + - name: SAMPLE_RATE + description: Hardware automatic sampling rate. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: RND_ECO_LOW + description: N/A + addressOffset: 44 + size: 32 + fields: + - name: RND_ECO_LOW + description: N/A + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RND_ECO_HIGH + description: N/A + addressOffset: 48 + size: 32 + resetValue: 4294967295 + fields: + - name: RND_ECO_HIGH + description: N/A + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RND_ECO_CS + description: N/A + addressOffset: 52 + size: 32 + fields: + - name: RND_ECO_EN + description: N/A + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RND_ECO_RESULT + description: N/A + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TWAI0 + description: Two-Wire Automotive Interface + groupName: TWAI + baseAddress: 1343057920 + addressBlock: + - offset: 0 + size: 140 + usage: registers + interrupt: + - name: TWAI0 + value: 40 + registers: + - register: + name: MODE + description: TWAI mode register. + addressOffset: 0 + size: 32 + resetValue: 1 + fields: + - name: RESET_MODE + description: "1: reset, detection of a set reset mode bit results in aborting the current transmission/reception of a message and entering the reset mode. 0: normal, on the '1-to-0' transition of the reset mode bit, the TWAI controller returns to the operating mode." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LISTEN_ONLY_MODE + description: "1: listen only, in this mode the TWAI controller would give no acknowledge to the TWAI-bus, even if a message is received successfully. The error counters are stopped at the current value. 0: normal." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SELF_TEST_MODE + description: "1: self test, in this mode a full node test is possible without any other active node on the bus using the self reception request command. The TWAI controller will perform a successful transmission, even if there is no acknowledge received. 0: normal, an acknowledge is required for successful transmission." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ACCEPTANCE_FILTER_MODE + description: "1:single, the single acceptance filter option is enabled (one filter with the length of 32 bit is active). 0:dual, the dual acceptance filter option is enabled (two filters, each with the length of 16 bit are active)." + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: CMD + description: TWAI command register. + addressOffset: 4 + size: 32 + fields: + - name: TX_REQUEST + description: "1: present, a message shall be transmitted. 0: absent" + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ABORT_TX + description: "1: present, if not already in progress, a pending transmission request is cancelled. 0: absent" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RELEASE_BUFFER + description: "1: released, the receive buffer, representing the message memory space in the RXFIFO is released. 0: no action" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CLEAR_DATA_OVERRUN + description: "1: clear, the data overrun status bit is cleared. 0: no action." + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SELF_RX_REQUEST + description: "1: present, a message shall be transmitted and received simultaneously. 0: absent." + bitOffset: 4 + bitWidth: 1 + access: write-only + - register: + name: STATUS + description: TWAI status register. + addressOffset: 8 + size: 32 + fields: + - name: RECEIVE_BUFFER + description: "1: full, one or more complete messages are available in the RXFIFO. 0: empty, no message is available" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OVERRUN + description: "1: overrun, a message was lost because there was not enough space for that message in the RXFIFO. 0: absent, no data overrun has occurred since the last clear data overrun command was given" + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TRANSMIT_BUFFER + description: "1: released, the CPU may write a message into the transmit buffer. 0: locked, the CPU cannot access the transmit buffer, a message is either waiting for transmission or is in the process of being transmitted" + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TRANSMISSION_COMPLETE + description: "1: complete, last requested transmission has been successfully completed. 0: incomplete, previously requested transmission is not yet completed" + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: RECEIVE + description: "1: receive, the TWAI controller is receiving a message. 0: idle" + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TRANSMIT + description: "1: transmit, the TWAI controller is transmitting a message. 0: idle" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ERR + description: "1: error, at least one of the error counters has reached or exceeded the CPU warning limit defined by the Error Warning Limit Register (EWLR). 0: ok, both error counters are below the warning limit" + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: NODE_BUS_OFF + description: "1: bus-off, the TWAI controller is not involved in bus activities. 0: bus-on, the TWAI controller is involved in bus activities" + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: MISS + description: "1: current message is destroyed because of FIFO overflow." + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INTERRUPT + description: "Interrupt signals' register." + addressOffset: 12 + size: 32 + fields: + - name: RECEIVE_INT_ST + description: "1: this bit is set while the receive FIFO is not empty and the RIE bit is set within the interrupt enable register. 0: reset" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TRANSMIT_INT_ST + description: "1: this bit is set whenever the transmit buffer status changes from '0-to-1' (released) and the TIE bit is set within the interrupt enable register. 0: reset" + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ERR_WARNING_INT_ST + description: "1: this bit is set on every change (set and clear) of either the error status or bus status bits and the EIE bit is set within the interrupt enable register. 0: reset" + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: DATA_OVERRUN_INT_ST + description: "1: this bit is set on a '0-to-1' transition of the data overrun status bit and the DOIE bit is set within the interrupt enable register. 0: reset" + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TS_COUNTER_OVFL_INT_ST + description: "1: this bit is set then the timestamp counter reaches the maximum value and overflow." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ERR_PASSIVE_INT_ST + description: "1: this bit is set whenever the TWAI controller has reached the error passive status (at least one error counter exceeds the protocol-defined level of 127) or if the TWAI controller is in the error passive status and enters the error active status again and the EPIE bit is set within the interrupt enable register. 0: reset" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_ST + description: "1: this bit is set when the TWAI controller lost the arbitration and becomes a receiver and the ALIE bit is set within the interrupt enable register. 0: reset" + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BUS_ERR_INT_ST + description: "1: this bit is set when the TWAI controller detects an error on the TWAI-bus and the BEIE bit is set within the interrupt enable register. 0: reset" + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IDLE_INT_ST + description: "1: this bit is set when the TWAI controller detects state of TWAI become IDLE and this interrupt enable bit is set within the interrupt enable register. 0: reset" + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INTERRUPT_ENABLE + description: Interrupt enable register. + addressOffset: 16 + size: 32 + fields: + - name: EXT_RECEIVE_INT_ENA + description: "1: enabled, when the receive buffer status is 'full' the TWAI controller requests the respective interrupt. 0: disable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EXT_TRANSMIT_INT_ENA + description: "1: enabled, when a message has been successfully transmitted or the transmit buffer is accessible again (e.g. after an abort transmission command), the TWAI controller requests the respective interrupt. 0: disable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EXT_ERR_WARNING_INT_ENA + description: "1: enabled, if the error or bus status change (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EXT_DATA_OVERRUN_INT_ENA + description: "1: enabled, if the data overrun status bit is set (see status register. Table 14), the TWAI controllerrequests the respective interrupt. 0: disable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TS_COUNTER_OVFL_INT_ENA + description: enable the timestamp counter overflow interrupt request. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ERR_PASSIVE_INT_ENA + description: "1: enabled, if the error status of the TWAI controller changes from error active to error passive or vice versa, the respective interrupt is requested. 0: disable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: ARBITRATION_LOST_INT_ENA + description: "1: enabled, if the TWAI controller has lost arbitration, the respective interrupt is requested. 0: disable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BUS_ERR_INT_ENA + description: "1: enabled, if an bus error has been detected, the TWAI controller requests the respective interrupt. 0: disable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IDLE_INT_ENA + description: "1: enabled, if state of TWAI become IDLE, the TWAI controller requests the respective interrupt. 0: disable" + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: BUS_TIMING_0 + description: Bit timing configuration register 0. + addressOffset: 24 + size: 32 + fields: + - name: BAUD_PRESC + description: The period of the TWAI system clock is programmable and determines the individual bit timing. Software has R/W permission in reset mode and RO permission in operation mode. + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: SYNC_JUMP_WIDTH + description: The synchronization jump width defines the maximum number of clock cycles a bit period may be shortened or lengthened. Software has R/W permission in reset mode and RO in operation mode. + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: BUS_TIMING_1 + description: Bit timing configuration register 1. + addressOffset: 28 + size: 32 + fields: + - name: TIME_SEGMENT1 + description: The number of clock cycles in TSEG1 per bit timing. Software has R/W permission in reset mode and RO in operation mode. + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: TIME_SEGMENT2 + description: The number of clock cycles in TSEG2 per bit timing. Software has R/W permission in reset mode and RO in operation mode. + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: TIME_SAMPLING + description: "1: triple, the bus is sampled three times. 0: single, the bus is sampled once. Software has R/W permission in reset mode and RO in operation mode." + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: ARB_LOST_CAP + description: TWAI arbiter lost capture register. + addressOffset: 44 + size: 32 + fields: + - name: ARBITRATION_LOST_CAPTURE + description: This register contains information about the bit position of losing arbitration. + bitOffset: 0 + bitWidth: 5 + access: read-only + - register: + name: ERR_CODE_CAP + description: TWAI error info capture register. + addressOffset: 48 + size: 32 + fields: + - name: ERR_CAPTURE_CODE_SEGMENT + description: This register contains information about the location of errors on the bus. + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: ERR_CAPTURE_CODE_DIRECTION + description: "1: RX, error occurred during reception. 0: TX, error occurred during transmission." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ERR_CAPTURE_CODE_TYPE + description: "00: bit error. 01: form error. 10:stuff error. 11:other type of error." + bitOffset: 6 + bitWidth: 2 + access: read-only + - register: + name: ERR_WARNING_LIMIT + description: TWAI error threshold configuration register. + addressOffset: 52 + size: 32 + resetValue: 96 + fields: + - name: ERR_WARNING_LIMIT + description: The threshold that trigger error warning interrupt when this interrupt is enabled. Software has R/W permission in reset mode and RO in operation mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: RX_ERR_CNT + description: Rx error counter register. + addressOffset: 56 + size: 32 + fields: + - name: RX_ERR_CNT + description: The RX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: TX_ERR_CNT + description: Tx error counter register. + addressOffset: 60 + size: 32 + fields: + - name: TX_ERR_CNT + description: The TX error counter register reflects the current value of the transmit error counter. Software has R/W permission in reset mode and RO in operation mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_0 + description: Data register 0. + addressOffset: 64 + size: 32 + fields: + - name: DATA_0 + description: "In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 0 and when software initiate read operation, it is rx data register 0." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_1 + description: Data register 1. + addressOffset: 68 + size: 32 + fields: + - name: DATA_1 + description: "In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 1 and when software initiate read operation, it is rx data register 1." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_2 + description: Data register 2. + addressOffset: 72 + size: 32 + fields: + - name: DATA_2 + description: "In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 2 and when software initiate read operation, it is rx data register 2." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_3 + description: Data register 3. + addressOffset: 76 + size: 32 + fields: + - name: DATA_3 + description: "In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 3 and when software initiate read operation, it is rx data register 3." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_4 + description: Data register 4. + addressOffset: 80 + size: 32 + fields: + - name: DATA_4 + description: "In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 4 and when software initiate read operation, it is rx data register 4." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_5 + description: Data register 5. + addressOffset: 84 + size: 32 + fields: + - name: DATA_5 + description: "In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 5 and when software initiate read operation, it is rx data register 5." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_6 + description: Data register 6. + addressOffset: 88 + size: 32 + fields: + - name: DATA_6 + description: "In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 6 and when software initiate read operation, it is rx data register 6." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_7 + description: Data register 7. + addressOffset: 92 + size: 32 + fields: + - name: DATA_7 + description: "In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, when software initiate write operation, it is tx data register 7 and when software initiate read operation, it is rx data register 7." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_8 + description: Data register 8. + addressOffset: 96 + size: 32 + fields: + - name: DATA_8 + description: "In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 8 and when software initiate read operation, it is rx data register 8." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_9 + description: Data register 9. + addressOffset: 100 + size: 32 + fields: + - name: DATA_9 + description: "In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 9 and when software initiate read operation, it is rx data register 9." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_10 + description: Data register 10. + addressOffset: 104 + size: 32 + fields: + - name: DATA_10 + description: "In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 10 and when software initiate read operation, it is rx data register 10." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_11 + description: Data register 11. + addressOffset: 108 + size: 32 + fields: + - name: DATA_11 + description: "In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 11 and when software initiate read operation, it is rx data register 11." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_12 + description: Data register 12. + addressOffset: 112 + size: 32 + fields: + - name: DATA_12 + description: "In reset mode, reserved with RO. In operation mode, when software initiate write operation, it is tx data register 12 and when software initiate read operation, it is rx data register 12." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: RX_MESSAGE_COUNTER + description: Received message counter register. + addressOffset: 116 + size: 32 + fields: + - name: RX_MESSAGE_COUNTER + description: Reflects the number of messages available within the RXFIFO. The value is incremented with each receive event and decremented by the release receive buffer command. + bitOffset: 0 + bitWidth: 7 + access: read-only + - register: + name: CLOCK_DIVIDER + description: Clock divider register. + addressOffset: 124 + size: 32 + fields: + - name: CD + description: These bits are used to define the frequency at the external CLKOUT pin. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CLOCK_OFF + description: "1: Disable the external CLKOUT pin. 0: Enable the external CLKOUT pin. Software has R/W permission in reset mode and RO in operation mode." + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: SW_STANDBY_CFG + description: Software configure standby pin directly. + addressOffset: 128 + size: 32 + resetValue: 2 + fields: + - name: SW_STANDBY_EN + description: Enable standby pin. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SW_STANDBY_CLR + description: Clear standby pin. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: HW_CFG + description: Hardware configure standby pin. + addressOffset: 132 + size: 32 + fields: + - name: HW_STANDBY_EN + description: Enable function that hardware control standby pin. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: HW_STANDBY_CNT + description: Configure standby counter. + addressOffset: 136 + size: 32 + resetValue: 1 + fields: + - name: STANDBY_WAIT_CNT + description: Configure the number of cycles before standby becomes high when TWAI_HW_STANDBY_EN is enabled. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: IDLE_INTR_CNT + description: Configure idle interrupt counter. + addressOffset: 140 + size: 32 + resetValue: 1 + fields: + - name: IDLE_INTR_CNT + description: Configure the number of cycles before triggering idle interrupt. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ECO_CFG + description: ECO configuration register. + addressOffset: 144 + size: 32 + resetValue: 2 + fields: + - name: RDN_ENA + description: Enable eco module. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RDN_RESULT + description: Output of eco module. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: TIMESTAMP_DATA + description: Timestamp data register + addressOffset: 148 + size: 32 + fields: + - name: TIMESTAMP_DATA + description: Data of timestamp of a CAN frame. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: TIMESTAMP_PRESCALER + description: Timestamp configuration register + addressOffset: 152 + size: 32 + resetValue: 31 + fields: + - name: TS_DIV_NUM + description: Configures the clock division number of timestamp counter. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: TIMESTAMP_CFG + description: Timestamp configuration register + addressOffset: 156 + size: 32 + fields: + - name: TS_ENABLE + description: enable the timestamp collection function. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TWAI1 + description: Two-Wire Automotive Interface + baseAddress: 1343062016 + interrupt: + - name: TWAI1 + value: 41 + derivedFrom: TWAI0 + - name: TWAI2 + description: Two-Wire Automotive Interface + baseAddress: 1343066112 + interrupt: + - name: TWAI2 + value: 42 + derivedFrom: TWAI0 + - name: UART0 + description: UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + groupName: UART + baseAddress: 1343004672 + addressBlock: + - offset: 0 + size: 152 + usage: registers + interrupt: + - name: UART0 + value: 31 + registers: + - register: + name: FIFO + description: FIFO data register + addressOffset: 0 + size: 32 + fields: + - name: RXFIFO_RD_BYTE + description: UART 0 accesses FIFO via this register. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 4 + size: 32 + resetValue: 2 + fields: + - name: RXFIFO_FULL_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_EMPTY_INT_RAW + description: This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PARITY_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a parity error in the data. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FRM_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a data frame error . + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DSR_CHG_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CTS_CHG_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BRK_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RXFIFO_TOUT_INT_RAW + description: This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SW_XON_INT_RAW + description: This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SW_XOFF_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GLITCH_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_BRK_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_BRK_IDLE_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RS485_PARITY_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RS485_FRM_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RS485_CLASH_INT_RAW + description: This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: AT_CMD_CHAR_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: WAKEUP_INT_RAW + description: This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 8 + size: 32 + fields: + - name: RXFIFO_FULL_INT_ST + description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_EMPTY_INT_ST + description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: PARITY_ERR_INT_ST + description: This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FRM_ERR_INT_ST + description: This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_ST + description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DSR_CHG_INT_ST + description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CTS_CHG_INT_ST + description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BRK_DET_INT_ST + description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: RXFIFO_TOUT_INT_ST + description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SW_XON_INT_ST + description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SW_XOFF_INT_ST + description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: GLITCH_DET_INT_ST + description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TX_BRK_DONE_INT_ST + description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: TX_BRK_IDLE_DONE_INT_ST + description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_ST + description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: RS485_PARITY_ERR_INT_ST + description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: RS485_FRM_ERR_INT_ST + description: This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: RS485_CLASH_INT_ST + description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: AT_CMD_CHAR_DET_INT_ST + description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: WAKEUP_INT_ST + description: This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + bitOffset: 19 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 12 + size: 32 + fields: + - name: RXFIFO_FULL_INT_ENA + description: This is the enable bit for rxfifo_full_int_st register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_EMPTY_INT_ENA + description: This is the enable bit for txfifo_empty_int_st register. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PARITY_ERR_INT_ENA + description: This is the enable bit for parity_err_int_st register. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FRM_ERR_INT_ENA + description: This is the enable bit for frm_err_int_st register. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_ENA + description: This is the enable bit for rxfifo_ovf_int_st register. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DSR_CHG_INT_ENA + description: This is the enable bit for dsr_chg_int_st register. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CTS_CHG_INT_ENA + description: This is the enable bit for cts_chg_int_st register. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BRK_DET_INT_ENA + description: This is the enable bit for brk_det_int_st register. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RXFIFO_TOUT_INT_ENA + description: This is the enable bit for rxfifo_tout_int_st register. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SW_XON_INT_ENA + description: This is the enable bit for sw_xon_int_st register. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SW_XOFF_INT_ENA + description: This is the enable bit for sw_xoff_int_st register. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GLITCH_DET_INT_ENA + description: This is the enable bit for glitch_det_int_st register. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_BRK_DONE_INT_ENA + description: This is the enable bit for tx_brk_done_int_st register. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_BRK_IDLE_DONE_INT_ENA + description: This is the enable bit for tx_brk_idle_done_int_st register. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_ENA + description: This is the enable bit for tx_done_int_st register. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RS485_PARITY_ERR_INT_ENA + description: This is the enable bit for rs485_parity_err_int_st register. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RS485_FRM_ERR_INT_ENA + description: This is the enable bit for rs485_parity_err_int_st register. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RS485_CLASH_INT_ENA + description: This is the enable bit for rs485_clash_int_st register. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: AT_CMD_CHAR_DET_INT_ENA + description: This is the enable bit for at_cmd_char_det_int_st register. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: WAKEUP_INT_ENA + description: This is the enable bit for uart_wakeup_int_st register. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 16 + size: 32 + fields: + - name: RXFIFO_FULL_INT_CLR + description: Set this bit to clear the rxfifo_full_int_raw interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TXFIFO_EMPTY_INT_CLR + description: Set this bit to clear txfifo_empty_int_raw interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: PARITY_ERR_INT_CLR + description: Set this bit to clear parity_err_int_raw interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: FRM_ERR_INT_CLR + description: Set this bit to clear frm_err_int_raw interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: RXFIFO_OVF_INT_CLR + description: Set this bit to clear rxfifo_ovf_int_raw interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: DSR_CHG_INT_CLR + description: Set this bit to clear the dsr_chg_int_raw interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CTS_CHG_INT_CLR + description: Set this bit to clear the cts_chg_int_raw interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: BRK_DET_INT_CLR + description: Set this bit to clear the brk_det_int_raw interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: RXFIFO_TOUT_INT_CLR + description: Set this bit to clear the rxfifo_tout_int_raw interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SW_XON_INT_CLR + description: Set this bit to clear the sw_xon_int_raw interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SW_XOFF_INT_CLR + description: Set this bit to clear the sw_xoff_int_raw interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: GLITCH_DET_INT_CLR + description: Set this bit to clear the glitch_det_int_raw interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TX_BRK_DONE_INT_CLR + description: Set this bit to clear the tx_brk_done_int_raw interrupt.. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: TX_BRK_IDLE_DONE_INT_CLR + description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: TX_DONE_INT_CLR + description: Set this bit to clear the tx_done_int_raw interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: RS485_PARITY_ERR_INT_CLR + description: Set this bit to clear the rs485_parity_err_int_raw interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: RS485_FRM_ERR_INT_CLR + description: Set this bit to clear the rs485_frm_err_int_raw interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: RS485_CLASH_INT_CLR + description: Set this bit to clear the rs485_clash_int_raw interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: AT_CMD_CHAR_DET_INT_CLR + description: Set this bit to clear the at_cmd_char_det_int_raw interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: WAKEUP_INT_CLR + description: Set this bit to clear the uart_wakeup_int_raw interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - register: + name: CLKDIV + description: Clock divider configuration + addressOffset: 20 + size: 32 + resetValue: 694 + fields: + - name: CLKDIV + description: The integral part of the frequency divider factor. + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: CLKDIV_FRAG + description: The decimal part of the frequency divider factor. + bitOffset: 20 + bitWidth: 4 + access: read-write + - register: + name: RX_FILT + description: Rx Filter configuration + addressOffset: 24 + size: 32 + resetValue: 8 + fields: + - name: GLITCH_FILT + description: when input pulse width is lower than this value the pulse is ignored. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GLITCH_FILT_EN + description: Set this bit to enable Rx signal filter. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: STATUS + description: UART status register + addressOffset: 28 + size: 32 + resetValue: 3758145536 + fields: + - name: RXFIFO_CNT + description: Stores the byte number of valid data in Rx-FIFO. + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: DSRN + description: The register represent the level value of the internal uart dsr signal. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: CTSN + description: This register represent the level value of the internal uart cts signal. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: RXD + description: This register represent the level value of the internal uart rxd signal. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TXFIFO_CNT + description: Stores the byte number of data in Tx-FIFO. + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: DTRN + description: This bit represents the level of the internal uart dtr signal. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: RTSN + description: This bit represents the level of the internal uart rts signal. + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: TXD + description: This bit represents the level of the internal uart txd signal. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CONF0 + description: a + addressOffset: 32 + size: 32 + resetValue: 28 + fields: + - name: PARITY + description: This register is used to configure the parity check mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PARITY_EN + description: Set this bit to enable uart parity check. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BIT_NUM + description: This register is used to set the length of data. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: STOP_BIT_NUM + description: This register is used to set the length of stop bit. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: TXD_BRK + description: Set this bit to enbale transmitter to send NULL when the process of sending data is done. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: IRDA_DPLX + description: Set this bit to enable IrDA loopback mode. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IRDA_TX_EN + description: This is the start enable bit for IrDA transmitter. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: IRDA_WCTL + description: "1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: IRDA_TX_INV + description: Set this bit to invert the level of IrDA transmitter. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: IRDA_RX_INV + description: Set this bit to invert the level of IrDA receiver. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: LOOPBACK + description: Set this bit to enable uart loopback test mode. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_FLOW_EN + description: Set this bit to enable flow control function for transmitter. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: IRDA_EN + description: Set this bit to enable IrDA protocol. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RXD_INV + description: Set this bit to inverse the level value of uart rxd signal. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TXD_INV + description: Set this bit to inverse the level value of uart txd signal. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DIS_RX_DAT_OVF + description: Disable UART Rx data overflow detect. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: ERR_WR_MASK + description: "1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: AUTOBAUD_EN + description: This is the enable bit for detecting baudrate. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: MEM_CLK_EN + description: UART memory clock gate enable signal. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SW_RTS + description: This register is used to configure the software rts signal which is used in software flow control. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: RXFIFO_RST + description: Set this bit to reset the uart receive-FIFO. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TXFIFO_RST + description: Set this bit to reset the uart transmit-FIFO. + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: CONF1 + description: Configuration register 1 + addressOffset: 36 + size: 32 + resetValue: 24672 + fields: + - name: RXFIFO_FULL_THRHD + description: It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TXFIFO_EMPTY_THRHD + description: It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: CTS_INV + description: Set this bit to inverse the level value of uart cts signal. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DSR_INV + description: Set this bit to inverse the level value of uart dsr signal. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: RTS_INV + description: Set this bit to inverse the level value of uart rts signal. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: DTR_INV + description: Set this bit to inverse the level value of uart dtr signal. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SW_DTR + description: This register is used to configure the software dtr signal which is used in software flow control. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers." + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + name: HWFC_CONF + description: Hardware flow-control configuration + addressOffset: 44 + size: 32 + fields: + - name: RX_FLOW_THRHD + description: This register is used to configure the maximum amount of data that can be received when hardware flow control works. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: RX_FLOW_EN + description: This is the flow enable bit for UART receiver. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: SLEEP_CONF0 + description: UART sleep configure register 0 + addressOffset: 48 + size: 32 + fields: + - name: WK_CHAR1 + description: This register restores the specified wake up char1 to wake up + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: WK_CHAR2 + description: This register restores the specified wake up char2 to wake up + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: WK_CHAR3 + description: This register restores the specified wake up char3 to wake up + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: WK_CHAR4 + description: This register restores the specified wake up char4 to wake up + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: SLEEP_CONF1 + description: UART sleep configure register 1 + addressOffset: 52 + size: 32 + fields: + - name: WK_CHAR0 + description: This register restores the specified char0 to wake up + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: SLEEP_CONF2 + description: UART sleep configure register 2 + addressOffset: 56 + size: 32 + resetValue: 1311984 + fields: + - name: ACTIVE_THRESHOLD + description: The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: RX_WAKE_UP_THRHD + description: In wake up mode 1 this field is used to set the received data number threshold to wake up chip. + bitOffset: 10 + bitWidth: 8 + access: read-write + - name: WK_CHAR_NUM + description: This register is used to select number of wake up char. + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: WK_CHAR_MASK + description: This register is used to mask wake up char. + bitOffset: 21 + bitWidth: 5 + access: read-write + - name: WK_MODE_SEL + description: "This register is used to select wake up mode. 0: RXD toggling to wake up. 1: received data number larger than" + bitOffset: 26 + bitWidth: 2 + access: read-write + - register: + name: SWFC_CONF0 + description: Software flow-control character configuration + addressOffset: 60 + size: 32 + resetValue: 4881 + fields: + - name: XON_CHAR + description: This register stores the Xon flow control char. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: XOFF_CHAR + description: This register stores the Xoff flow control char. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: XON_XOFF_STILL_SEND + description: "In software flow control mode, UART Tx is disabled once UART Rx receives XOFF. In this status, UART Tx can not transmit XOFF even the received data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable UART Tx can transmit XON/XOFF when UART Tx is disabled." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SW_FLOW_CON_EN + description: Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: XONOFF_DEL + description: Set this bit to remove flow control char from the received data. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: FORCE_XON + description: Set this bit to enable the transmitter to go on sending data. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: FORCE_XOFF + description: Set this bit to stop the transmitter from sending data. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SEND_XON + description: Set this bit to send Xon char. It is cleared by hardware automatically. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SEND_XOFF + description: Set this bit to send Xoff char. It is cleared by hardware automatically. + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: SWFC_CONF1 + description: Software flow-control character configuration + addressOffset: 64 + size: 32 + resetValue: 57344 + fields: + - name: XON_THRESHOLD + description: When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: XOFF_THRESHOLD + description: When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char. + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: TXBRK_CONF + description: Tx Break character configuration + addressOffset: 68 + size: 32 + resetValue: 10 + fields: + - name: TX_BRK_NUM + description: This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: IDLE_CONF + description: Frame-end idle configuration + addressOffset: 72 + size: 32 + resetValue: 262400 + fields: + - name: RX_IDLE_THRHD + description: It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: TX_IDLE_NUM + description: This register is used to configure the duration time between transfers. + bitOffset: 10 + bitWidth: 10 + access: read-write + - register: + name: RS485_CONF + description: RS485 mode configuration + addressOffset: 76 + size: 32 + fields: + - name: RS485_EN + description: Set this bit to choose the rs485 mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DL0_EN + description: Set this bit to delay the stop bit by 1 bit. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DL1_EN + description: Set this bit to delay the stop bit by 1 bit. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RS485TX_RX_EN + description: Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RS485RXBY_TX_EN + description: "1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RS485_RX_DLY_NUM + description: "This register is used to delay the receiver's internal data signal." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RS485_TX_DLY_NUM + description: "This register is used to delay the transmitter's internal data signal." + bitOffset: 6 + bitWidth: 4 + access: read-write + - register: + name: AT_CMD_PRECNT + description: Pre-sequence timing configuration + addressOffset: 80 + size: 32 + resetValue: 2305 + fields: + - name: PRE_IDLE_NUM + description: This register is used to configure the idle duration time before the first at_cmd is received by receiver. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_POSTCNT + description: Post-sequence timing configuration + addressOffset: 84 + size: 32 + resetValue: 2305 + fields: + - name: POST_IDLE_NUM + description: This register is used to configure the duration time between the last at_cmd and the next data. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_GAPTOUT + description: Timeout configuration + addressOffset: 88 + size: 32 + resetValue: 11 + fields: + - name: RX_GAP_TOUT + description: This register is used to configure the duration time between the at_cmd chars. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_CHAR + description: AT escape sequence detection configuration + addressOffset: 92 + size: 32 + resetValue: 811 + fields: + - name: AT_CMD_CHAR + description: This register is used to configure the content of at_cmd char. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CHAR_NUM + description: This register is used to configure the num of continuous at_cmd chars received by receiver. + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: MEM_CONF + description: UART memory power configuration + addressOffset: 96 + size: 32 + fields: + - name: MEM_FORCE_PD + description: Set this bit to force power down UART memory. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PU + description: Set this bit to force power up UART memory. + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: TOUT_CONF + description: UART threshold and allocation configuration + addressOffset: 100 + size: 32 + resetValue: 40 + fields: + - name: RX_TOUT_EN + description: "This is the enble bit for uart receiver's timeout function." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_TOUT_FLOW_DIS + description: Set this bit to stop accumulating idle_cnt when hardware flow control works. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_TOUT_THRHD + description: This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + bitOffset: 2 + bitWidth: 10 + access: read-write + - register: + name: MEM_TX_STATUS + description: Tx-SRAM write and read offset address. + addressOffset: 104 + size: 32 + fields: + - name: TX_SRAM_WADDR + description: This register stores the offset write address in Tx-SRAM. + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: TX_SRAM_RADDR + description: This register stores the offset read address in Tx-SRAM. + bitOffset: 9 + bitWidth: 8 + access: read-only + - register: + name: MEM_RX_STATUS + description: Rx-SRAM write and read offset address. + addressOffset: 108 + size: 32 + resetValue: 65664 + fields: + - name: RX_SRAM_RADDR + description: This register stores the offset read address in RX-SRAM. + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: RX_SRAM_WADDR + description: This register stores the offset write address in Rx-SRAM. + bitOffset: 9 + bitWidth: 8 + access: read-only + - register: + name: FSM_STATUS + description: UART transmit and receive status. + addressOffset: 112 + size: 32 + fields: + - name: ST_URX_OUT + description: This is the status register of receiver. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: ST_UTX_OUT + description: This is the status register of transmitter. + bitOffset: 4 + bitWidth: 4 + access: read-only + - register: + name: POSPULSE + description: Autobaud high pulse register + addressOffset: 116 + size: 32 + resetValue: 4095 + fields: + - name: POSEDGE_MIN_CNT + description: This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process. + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: NEGPULSE + description: Autobaud low pulse register + addressOffset: 120 + size: 32 + resetValue: 4095 + fields: + - name: NEGEDGE_MIN_CNT + description: This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process. + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: LOWPULSE + description: Autobaud minimum low pulse duration register + addressOffset: 124 + size: 32 + resetValue: 4095 + fields: + - name: MIN_CNT + description: This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process. + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: HIGHPULSE + description: Autobaud minimum high pulse duration register + addressOffset: 128 + size: 32 + resetValue: 4095 + fields: + - name: MIN_CNT + description: This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process. + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: RXD_CNT + description: Autobaud edge change count register + addressOffset: 132 + size: 32 + fields: + - name: RXD_EDGE_CNT + description: This register stores the count of rxd edge change. It is used in baud rate-detect process. + bitOffset: 0 + bitWidth: 10 + access: read-only + - register: + name: CLK_CONF + description: UART core clock configuration + addressOffset: 136 + size: 32 + resetValue: 50331648 + fields: + - name: TX_SCLK_EN + description: Set this bit to enable UART Tx clock. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: RX_SCLK_EN + description: Set this bit to enable UART Rx clock. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TX_RST_CORE + description: Write 1 then write 0 to this bit to reset UART Tx. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RX_RST_CORE + description: Write 1 then write 0 to this bit to reset UART Rx. + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: UART Version register + addressOffset: 140 + size: 32 + resetValue: 36720720 + fields: + - name: DATE + description: This is the version register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: AFIFO_STATUS + description: UART AFIFO Status + addressOffset: 144 + size: 32 + resetValue: 10 + fields: + - name: TX_AFIFO_FULL + description: Full signal of APB TX AFIFO. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_AFIFO_EMPTY + description: Empty signal of APB TX AFIFO. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_AFIFO_FULL + description: Full signal of APB RX AFIFO. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: RX_AFIFO_EMPTY + description: Empty signal of APB RX AFIFO. + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: REG_UPDATE + description: UART Registers Configuration Update register + addressOffset: 152 + size: 32 + fields: + - name: REG_UPDATE + description: Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: ID + description: UART ID register + addressOffset: 156 + size: 32 + resetValue: 1280 + fields: + - name: ID + description: This register is used to configure the uart_id. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: UART1 + description: UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + baseAddress: 1343008768 + interrupt: + - name: UART1 + value: 32 + derivedFrom: UART0 + - name: UART2 + description: UART (Universal Asynchronous Receiver-Transmitter) Controller 2 + baseAddress: 1343012864 + interrupt: + - name: UART2 + value: 33 + derivedFrom: UART0 + - name: UART3 + description: UART (Universal Asynchronous Receiver-Transmitter) Controller 3 + baseAddress: 1343016960 + interrupt: + - name: UART3 + value: 34 + derivedFrom: UART0 + - name: UART4 + description: UART (Universal Asynchronous Receiver-Transmitter) Controller 4 + baseAddress: 1343021056 + interrupt: + - name: UART4 + value: 35 + derivedFrom: UART0 + - name: UHCI0 + description: Universal Host Controller Interface 0 + groupName: UHCI + baseAddress: 1343090688 + addressBlock: + - offset: 0 + size: 132 + usage: registers + interrupt: + - name: UHCI0 + value: 30 + registers: + - register: + name: CONF0 + description: UHCI Configuration Register0 + addressOffset: 0 + size: 32 + resetValue: 1760 + fields: + - name: TX_RST + description: Write 1 then write 0 to this bit to reset decode state machine. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_RST + description: Write 1 then write 0 to this bit to reset encode state machine. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UART_SEL + description: Select which uart to connect with GDMA. + bitOffset: 2 + bitWidth: 3 + access: read-write + - name: SEPER_EN + description: Set this bit to separate the data frame using a special char. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: HEAD_EN + description: Set this bit to encode the data packet with a formatting header. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CRC_REC_EN + description: Set this bit to enable UHCI to receive the 16 bit CRC. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: UART_IDLE_EOF_EN + description: If this bit is set to 1 UHCI will end the payload receiving process when UART has been in idle state. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: LEN_EOF_EN + description: If this bit is set to 1 UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: ENCODE_CRC_EN + description: Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: UART_RX_BRK_EOF_EN + description: If this bit is set to 1 UHCI will end payload receive process when NULL frame is received by UART. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: UHCI Interrupt Raw Register + addressOffset: 4 + size: 32 + fields: + - name: RX_START_INT_RAW + description: Indicates the raw interrupt of UHCI_RX_START_INT. Interrupt will be triggered when delimiter is sent successfully. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_START_INT_RAW + description: Indicates the raw interrupt of UHCI_TX_START_INT. Interrupt will be triggered when DMA detects delimiter. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_HUNG_INT_RAW + description: Indicates the raw interrupt of UHCI_RX_HUNG_INT. Interrupt will be triggered when the required time of DMA receiving data exceeds the configuration value. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_HUNG_INT_RAW + description: Indicates the raw interrupt of UHCI_TX_HUNG_INT. Interrupt will be triggered when the required time of DMA reading RAM data exceeds the configuration value. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SEND_S_REG_Q_INT_RAW + description: Indicates the raw interrupt of UHCI_SEND_S_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with single_send mode. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SEND_A_REG_Q_INT_RAW + description: Indicates the raw interrupt of UHCI_SEND_A_REG_Q_INT. Interrupt will be triggered when UHCI sends short packet successfully with always_send mode. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUT_EOF_INT_RAW + description: Indicates the raw interrupt of UHCI_OUT_EOF_INT. Interrupt will be triggered when there are errors in EOF. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: APP_CTRL0_INT_RAW + description: Indicates the raw interrupt of UHCI_APP_CTRL0_INT. Interrupt will be triggered when UHCI_APP_CTRL0_IN_SET is set to 1. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: APP_CTRL1_INT_RAW + description: Indicates the raw interrupt of UHCI_APP_CTRL1_INT. Interrupt will be triggered when UHCI_APP_CTRL1_IN_SET is set to 1. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: UHCI Interrupt Status Register + addressOffset: 8 + size: 32 + fields: + - name: RX_START_INT_ST + description: Indicates the interrupt status of UHCI_RX_START_INT. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_START_INT_ST + description: Indicates the interrupt status of UHCI_TX_START_INT. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_ST + description: Indicates the interrupt status of UHCI_RX_HUNG_INT. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_ST + description: Indicates the interrupt status of UHCI_TX_HUNG_INT. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SEND_S_REG_Q_INT_ST + description: Indicates the interrupt status of UHCI_SEND_S_REG_Q_INT. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SEND_A_REG_Q_INT_ST + description: Indicates the interrupt status of UHCI_SEND_A_REG_Q_INT. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OUTLINK_EOF_ERR_INT_ST + description: Indicates the interrupt status of UHCI_OUT_EOF_INT. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: APP_CTRL0_INT_ST + description: Indicates the interrupt status of UHCI_APP_CTRL0_INT. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: APP_CTRL1_INT_ST + description: Indicates the interrupt status of UHCI_APP_CTRL1_INT. + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: UHCI Interrupt Enable Register + addressOffset: 12 + size: 32 + fields: + - name: RX_START_INT_ENA + description: Set this bit to enable the interrupt of UHCI_RX_START_INT. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_START_INT_ENA + description: Set this bit to enable the interrupt of UHCI_TX_START_INT. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_HUNG_INT_ENA + description: Set this bit to enable the interrupt of UHCI_RX_HUNG_INT. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_HUNG_INT_ENA + description: Set this bit to enable the interrupt of UHCI_TX_HUNG_INT. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SEND_S_REG_Q_INT_ENA + description: Set this bit to enable the interrupt of UHCI_SEND_S_REG_Q_INT. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SEND_A_REG_Q_INT_ENA + description: Set this bit to enable the interrupt of UHCI_SEND_A_REG_Q_INT. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUTLINK_EOF_ERR_INT_ENA + description: Set this bit to enable the interrupt of UHCI_OUT_EOF_INT. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: APP_CTRL0_INT_ENA + description: Set this bit to enable the interrupt of UHCI_APP_CTRL0_INT. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: APP_CTRL1_INT_ENA + description: Set this bit to enable the interrupt of UHCI_APP_CTRL1_INT. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: UHCI Interrupt Clear Register + addressOffset: 16 + size: 32 + fields: + - name: RX_START_INT_CLR + description: Set this bit to clear the raw interrupt of UHCI_RX_START_INT. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TX_START_INT_CLR + description: Set this bit to clear the raw interrupt of UHCI_TX_START_INT. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_HUNG_INT_CLR + description: Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TX_HUNG_INT_CLR + description: Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SEND_S_REG_Q_INT_CLR + description: Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SEND_A_REG_Q_INT_CLR + description: Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: OUTLINK_EOF_ERR_INT_CLR + description: Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: APP_CTRL0_INT_CLR + description: Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: APP_CTRL1_INT_CLR + description: Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT. + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: CONF1 + description: UHCI Configuration Register1 + addressOffset: 20 + size: 32 + resetValue: 51 + fields: + - name: CHECK_SUM_EN + description: Set this bit to enable head checksum check when receiving. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CHECK_SEQ_EN + description: Set this bit to enable sequence number check when receiving. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CRC_DISABLE + description: "Set this bit to support CRC calculation, and data integrity check bit should 1." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SAVE_HEAD + description: Set this bit to save data packet head when UHCI receive data. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_CHECK_SUM_RE + description: Set this bit to encode data packet with checksum. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TX_ACK_NUM_RE + description: Set this bit to encode data packet with ACK when reliable data packet is ready. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: WAIT_SW_START + description: Set this bit to enable UHCI encoder transfer to ST_SW_WAIT status. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SW_START + description: Set this bit to transmit data packet if UCHI_ENCODE_STATE is ST_SW_WAIT. + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: STATE0 + description: UHCI Receive Status Register + addressOffset: 24 + size: 32 + fields: + - name: RX_ERR_CAUSE + description: "Indicates the error types when DMA receives the error frame. 3'b001: UHCI packet checksum error. 3'b010: UHCI packet sequence number error. 3'b011: UHCI packet CRC bit error. 3'b100: find 0xC0, but received packet is uncompleted. 3'b101: 0xC0 is not found, but received packet is completed. 3'b110: CRC check error." + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: DECODE_STATE + description: Indicates UHCI decoder status. + bitOffset: 3 + bitWidth: 3 + access: read-only + - register: + name: STATE1 + description: UHCI Transmit Status Register + addressOffset: 28 + size: 32 + fields: + - name: ENCODE_STATE + description: Indicates UHCI encoder status. + bitOffset: 0 + bitWidth: 3 + access: read-only + - register: + name: ESCAPE_CONF + description: UHCI Escapes Configuration Register0 + addressOffset: 32 + size: 32 + resetValue: 51 + fields: + - name: TX_C0_ESC_EN + description: Set this bit to enable resolve char 0xC0 when DMA receiving data. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_DB_ESC_EN + description: Set this bit to enable resolve char 0xDB when DMA receiving data. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TX_11_ESC_EN + description: Set this bit to enable resolve flow control char 0x11 when DMA receiving data. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_13_ESC_EN + description: Set this bit to enable resolve flow control char 0x13 when DMA receiving data. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_C0_ESC_EN + description: Set this bit to enable replacing 0xC0 with special char when DMA receiving data. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_DB_ESC_EN + description: Set this bit to enable replacing 0xDB with special char when DMA receiving data. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RX_11_ESC_EN + description: Set this bit to enable replacing 0x11 with special char when DMA receiving data. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_13_ESC_EN + description: Set this bit to enable replacing 0x13 with special char when DMA receiving data. + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: HUNG_CONF + description: UHCI Hung Configuration Register0 + addressOffset: 36 + size: 32 + resetValue: 8456208 + fields: + - name: TXFIFO_TIMEOUT + description: Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when receiving data. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TXFIFO_TIMEOUT_SHIFT + description: Configures the maximum counter value. + bitOffset: 8 + bitWidth: 3 + access: read-write + - name: TXFIFO_TIMEOUT_ENA + description: Set this bit to enable TX FIFO timeout when receiving. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RXFIFO_TIMEOUT + description: Stores the timeout value. DMA generates UHCI_TX_HUNG_INT for timeout when reading RAM data. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: RXFIFO_TIMEOUT_SHIFT + description: Configures the maximum counter value. + bitOffset: 20 + bitWidth: 3 + access: read-write + - name: RXFIFO_TIMEOUT_ENA + description: Set this bit to enable TX FIFO timeout when DMA sending data. + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: ACK_NUM + description: UHCI Ack Value Configuration Register0 + addressOffset: 40 + size: 32 + fields: + - name: ACK_NUM + description: Indicates the ACK number during software flow control. + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: LOAD + description: Set this bit to load the ACK value of UHCI_ACK_NUM. + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: RX_HEAD + description: UHCI Head Register + addressOffset: 44 + size: 32 + fields: + - name: RX_HEAD + description: Stores the head of received packet. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: QUICK_SENT + description: UCHI Quick send Register + addressOffset: 48 + size: 32 + fields: + - name: SINGLE_SEND_NUM + description: Configures single_send mode. + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SINGLE_SEND_EN + description: Set this bit to enable sending short packet with single_send mode. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: ALWAYS_SEND_NUM + description: Configures always_send mode. + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: ALWAYS_SEND_EN + description: Set this bit to enable sending short packet with always_send mode. + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: REG_Q0_WORD0 + description: UHCI Q0_WORD0 Quick Send Register + addressOffset: 52 + size: 32 + fields: + - name: SEND_Q0_WORD0 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q0_WORD1 + description: UHCI Q0_WORD1 Quick Send Register + addressOffset: 56 + size: 32 + fields: + - name: SEND_Q0_WORD1 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q1_WORD0 + description: UHCI Q1_WORD0 Quick Send Register + addressOffset: 60 + size: 32 + fields: + - name: SEND_Q1_WORD0 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q1_WORD1 + description: UHCI Q1_WORD1 Quick Send Register + addressOffset: 64 + size: 32 + fields: + - name: SEND_Q1_WORD1 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q2_WORD0 + description: UHCI Q2_WORD0 Quick Send Register + addressOffset: 68 + size: 32 + fields: + - name: SEND_Q2_WORD0 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q2_WORD1 + description: UHCI Q2_WORD1 Quick Send Register + addressOffset: 72 + size: 32 + fields: + - name: SEND_Q2_WORD1 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q3_WORD0 + description: UHCI Q3_WORD0 Quick Send Register + addressOffset: 76 + size: 32 + fields: + - name: SEND_Q3_WORD0 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q3_WORD1 + description: UHCI Q3_WORD1 Quick Send Register + addressOffset: 80 + size: 32 + fields: + - name: SEND_Q3_WORD1 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q4_WORD0 + description: UHCI Q4_WORD0 Quick Send Register + addressOffset: 84 + size: 32 + fields: + - name: SEND_Q4_WORD0 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q4_WORD1 + description: UHCI Q4_WORD1 Quick Send Register + addressOffset: 88 + size: 32 + fields: + - name: SEND_Q4_WORD1 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q5_WORD0 + description: UHCI Q5_WORD0 Quick Send Register + addressOffset: 92 + size: 32 + fields: + - name: SEND_Q5_WORD0 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q5_WORD1 + description: UHCI Q5_WORD1 Quick Send Register + addressOffset: 96 + size: 32 + fields: + - name: SEND_Q5_WORD1 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q6_WORD0 + description: UHCI Q6_WORD0 Quick Send Register + addressOffset: 100 + size: 32 + fields: + - name: SEND_Q6_WORD0 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q6_WORD1 + description: UHCI Q6_WORD1 Quick Send Register + addressOffset: 104 + size: 32 + fields: + - name: SEND_Q6_WORD1 + description: Serves as quick sending register in specified mode in UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ESC_CONF0 + description: UHCI Escapes Sequence Configuration Register0 + addressOffset: 108 + size: 32 + resetValue: 14474176 + fields: + - name: SEPER_CHAR + description: "Configures the delimiter for encoding, default value is 0xC0." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SEPER_ESC_CHAR0 + description: "Configures the first char of SLIP escape character, default value is 0xDB." + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SEPER_ESC_CHAR1 + description: "Configures the second char of SLIP escape character, default value is 0xDC." + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: ESC_CONF1 + description: UHCI Escapes Sequence Configuration Register1 + addressOffset: 112 + size: 32 + resetValue: 14539739 + fields: + - name: ESC_SEQ0 + description: "Configures the char needing encoding, which is 0xDB as flow control char by default." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: ESC_SEQ0_CHAR0 + description: "Configures the first char of SLIP escape character, default value is 0xDB." + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: ESC_SEQ0_CHAR1 + description: "Configures the second char of SLIP escape character, default value is 0xDD." + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: ESC_CONF2 + description: UHCI Escapes Sequence Configuration Register2 + addressOffset: 116 + size: 32 + resetValue: 14605073 + fields: + - name: ESC_SEQ1 + description: "Configures the char needing encoding, which is 0x11 as flow control char by default." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: ESC_SEQ1_CHAR0 + description: "Configures the first char of SLIP escape character, default value is 0xDB." + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: ESC_SEQ1_CHAR1 + description: "Configures the second char of SLIP escape character, default value is 0xDE." + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: ESC_CONF3 + description: UHCI Escapes Sequence Configuration Register3 + addressOffset: 120 + size: 32 + resetValue: 14670611 + fields: + - name: ESC_SEQ2 + description: "Configures the char needing encoding, which is 0x13 as flow control char by default." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: ESC_SEQ2_CHAR0 + description: "Configures the first char of SLIP escape character, default value is 0xDB." + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: ESC_SEQ2_CHAR1 + description: "Configures the second char of SLIP escape character, default value is 0xDF." + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: PKT_THRES + description: UCHI Packet Length Configuration Register + addressOffset: 124 + size: 32 + resetValue: 128 + fields: + - name: PKT_THRS + description: "Configures the data packet's maximum length when UHCI_HEAD_EN is 0." + bitOffset: 0 + bitWidth: 13 + access: read-write + - register: + name: DATE + description: UHCI Version Register + addressOffset: 128 + size: 32 + resetValue: 35655936 + fields: + - name: DATE + description: Configures version. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: USB_DEVICE + description: Full-speed USB Serial/JTAG Controller + groupName: USB_DEVICE + baseAddress: 1343037440 + addressBlock: + - offset: 0 + size: 140 + usage: registers + interrupt: + - name: USB_DEVICE + value: 22 + registers: + - register: + name: EP1 + description: FIFO access for the CDC-ACM data IN and OUT endpoints. + addressOffset: 0 + size: 32 + fields: + - name: RDWR_BYTE + description: "Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: EP1_CONF + description: Configuration and control registers for the CDC-ACM FIFOs. + addressOffset: 4 + size: 32 + resetValue: 2 + fields: + - name: WR_DONE + description: Set this bit to indicate writing byte data to UART Tx FIFO is done. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SERIAL_IN_EP_DATA_FREE + description: "1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SERIAL_OUT_EP_DATA_AVAIL + description: "1'b1: Indicate there is data in UART Rx FIFO." + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: INT_RAW + description: Interrupt raw status register. + addressOffset: 8 + size: 32 + resetValue: 8 + fields: + - name: JTAG_IN_FLUSH_INT_RAW + description: The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SOF_INT_RAW + description: The raw interrupt bit turns to high level when SOF frame is received. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SERIAL_OUT_RECV_PKT_INT_RAW + description: The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SERIAL_IN_EMPTY_INT_RAW + description: The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PID_ERR_INT_RAW + description: The raw interrupt bit turns to high level when pid error is detected. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CRC5_ERR_INT_RAW + description: The raw interrupt bit turns to high level when CRC5 error is detected. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CRC16_ERR_INT_RAW + description: The raw interrupt bit turns to high level when CRC16 error is detected. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: STUFF_ERR_INT_RAW + description: The raw interrupt bit turns to high level when stuff error is detected. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IN_TOKEN_REC_IN_EP1_INT_RAW + description: The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: USB_BUS_RESET_INT_RAW + description: The raw interrupt bit turns to high level when usb bus reset is detected. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OUT_EP1_ZERO_PAYLOAD_INT_RAW + description: The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OUT_EP2_ZERO_PAYLOAD_INT_RAW + description: The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RTS_CHG_INT_RAW + description: The raw interrupt bit turns to high level when level of RTS from usb serial channel is changed. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DTR_CHG_INT_RAW + description: The raw interrupt bit turns to high level when level of DTR from usb serial channel is changed. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: GET_LINE_CODE_INT_RAW + description: The raw interrupt bit turns to high level when level of GET LINE CODING request is received. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SET_LINE_CODE_INT_RAW + description: The raw interrupt bit turns to high level when level of SET LINE CODING request is received. + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Interrupt status register. + addressOffset: 12 + size: 32 + fields: + - name: JTAG_IN_FLUSH_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SOF_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SERIAL_OUT_RECV_PKT_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SERIAL_IN_EMPTY_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: PID_ERR_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: CRC5_ERR_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CRC16_ERR_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: STUFF_ERR_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IN_TOKEN_REC_IN_EP1_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: USB_BUS_RESET_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: OUT_EP1_ZERO_PAYLOAD_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: OUT_EP2_ZERO_PAYLOAD_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: RTS_CHG_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: DTR_CHG_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: GET_LINE_CODE_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SET_LINE_CODE_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable status register. + addressOffset: 16 + size: 32 + fields: + - name: JTAG_IN_FLUSH_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SOF_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SERIAL_OUT_RECV_PKT_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SERIAL_IN_EMPTY_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PID_ERR_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CRC5_ERR_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CRC16_ERR_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: STUFF_ERR_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IN_TOKEN_REC_IN_EP1_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: USB_BUS_RESET_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OUT_EP1_ZERO_PAYLOAD_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OUT_EP2_ZERO_PAYLOAD_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RTS_CHG_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DTR_CHG_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: GET_LINE_CODE_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SET_LINE_CODE_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear status register. + addressOffset: 20 + size: 32 + fields: + - name: JTAG_IN_FLUSH_INT_CLR + description: Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SOF_INT_CLR + description: Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SERIAL_OUT_RECV_PKT_INT_CLR + description: Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SERIAL_IN_EMPTY_INT_CLR + description: Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: PID_ERR_INT_CLR + description: Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: CRC5_ERR_INT_CLR + description: Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CRC16_ERR_INT_CLR + description: Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: STUFF_ERR_INT_CLR + description: Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: IN_TOKEN_REC_IN_EP1_INT_CLR + description: Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: USB_BUS_RESET_INT_CLR + description: Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: OUT_EP1_ZERO_PAYLOAD_INT_CLR + description: Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: OUT_EP2_ZERO_PAYLOAD_INT_CLR + description: Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: RTS_CHG_INT_CLR + description: Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: DTR_CHG_INT_CLR + description: Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: GET_LINE_CODE_INT_CLR + description: Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SET_LINE_CODE_INT_CLR + description: Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - register: + name: CONF0 + description: PHY hardware configuration. + addressOffset: 24 + size: 32 + resetValue: 16896 + fields: + - name: PHY_SEL + description: Select internal/external PHY + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EXCHG_PINS_OVERRIDE + description: Enable software control USB D+ D- exchange + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EXCHG_PINS + description: USB D+ D- exchange + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: VREFH + description: "Control single-end input high threshold,1.76V to 2V, step 80mV" + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: VREFL + description: "Control single-end input low threshold,0.8V to 1.04V, step 80mV" + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: VREF_OVERRIDE + description: Enable software control input threshold + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: PAD_PULL_OVERRIDE + description: Enable software control USB D+ D- pullup pulldown + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DP_PULLUP + description: Control USB D+ pull up. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DP_PULLDOWN + description: Control USB D+ pull down. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DM_PULLUP + description: Control USB D- pull up. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DM_PULLDOWN + description: Control USB D- pull down. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PULLUP_VALUE + description: Control pull up value. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: USB_PAD_ENABLE + description: Enable USB pad function. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: USB_JTAG_BRIDGE_EN + description: "Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: TEST + description: Registers used for debugging the PHY. + addressOffset: 28 + size: 32 + resetValue: 48 + fields: + - name: TEST_ENABLE + description: Enable test of the USB pad + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TEST_USB_OE + description: USB pad oen in test + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TEST_TX_DP + description: USB D+ tx value in test + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TEST_TX_DM + description: USB D- tx value in test + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TEST_RX_RCV + description: USB RCV value in test + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TEST_RX_DP + description: USB D+ rx value in test + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: TEST_RX_DM + description: USB D- rx value in test + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: JFIFO_ST + description: JTAG FIFO status and control registers. + addressOffset: 32 + size: 32 + resetValue: 68 + fields: + - name: IN_FIFO_CNT + description: JTAT in fifo counter. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_FIFO_EMPTY + description: "1: JTAG in fifo is empty." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: IN_FIFO_FULL + description: "1: JTAG in fifo is full." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: OUT_FIFO_CNT + description: JTAT out fifo counter. + bitOffset: 4 + bitWidth: 2 + access: read-only + - name: OUT_FIFO_EMPTY + description: "1: JTAG out fifo is empty." + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUT_FIFO_FULL + description: "1: JTAG out fifo is full." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IN_FIFO_RESET + description: Write 1 to reset JTAG in fifo. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: OUT_FIFO_RESET + description: Write 1 to reset JTAG out fifo. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: FRAM_NUM + description: Last received SOF frame index register. + addressOffset: 36 + size: 32 + fields: + - name: SOF_FRAME_INDEX + description: Frame index of received SOF frame. + bitOffset: 0 + bitWidth: 11 + access: read-only + - register: + name: IN_EP0_ST + description: Control IN endpoint status information. + addressOffset: 40 + size: 32 + resetValue: 1 + fields: + - name: IN_EP0_STATE + description: State of IN Endpoint 0. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_EP0_WR_ADDR + description: Write data address of IN endpoint 0. + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: IN_EP0_RD_ADDR + description: Read data address of IN endpoint 0. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: IN_EP1_ST + description: CDC-ACM IN endpoint status information. + addressOffset: 44 + size: 32 + resetValue: 1 + fields: + - name: IN_EP1_STATE + description: State of IN Endpoint 1. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_EP1_WR_ADDR + description: Write data address of IN endpoint 1. + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: IN_EP1_RD_ADDR + description: Read data address of IN endpoint 1. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: IN_EP2_ST + description: CDC-ACM interrupt IN endpoint status information. + addressOffset: 48 + size: 32 + resetValue: 1 + fields: + - name: IN_EP2_STATE + description: State of IN Endpoint 2. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_EP2_WR_ADDR + description: Write data address of IN endpoint 2. + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: IN_EP2_RD_ADDR + description: Read data address of IN endpoint 2. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: IN_EP3_ST + description: JTAG IN endpoint status information. + addressOffset: 52 + size: 32 + resetValue: 1 + fields: + - name: IN_EP3_STATE + description: State of IN Endpoint 3. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_EP3_WR_ADDR + description: Write data address of IN endpoint 3. + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: IN_EP3_RD_ADDR + description: Read data address of IN endpoint 3. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: OUT_EP0_ST + description: Control OUT endpoint status information. + addressOffset: 56 + size: 32 + fields: + - name: OUT_EP0_STATE + description: State of OUT Endpoint 0. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: OUT_EP0_WR_ADDR + description: "Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0." + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: OUT_EP0_RD_ADDR + description: Read data address of OUT endpoint 0. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: OUT_EP1_ST + description: CDC-ACM OUT endpoint status information. + addressOffset: 60 + size: 32 + fields: + - name: OUT_EP1_STATE + description: State of OUT Endpoint 1. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: OUT_EP1_WR_ADDR + description: "Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1." + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: OUT_EP1_RD_ADDR + description: Read data address of OUT endpoint 1. + bitOffset: 9 + bitWidth: 7 + access: read-only + - name: OUT_EP1_REC_DATA_CNT + description: Data count in OUT endpoint 1 when one packet is received. + bitOffset: 16 + bitWidth: 7 + access: read-only + - register: + name: OUT_EP2_ST + description: JTAG OUT endpoint status information. + addressOffset: 64 + size: 32 + fields: + - name: OUT_EP2_STATE + description: State of OUT Endpoint 2. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: OUT_EP2_WR_ADDR + description: "Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2." + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: OUT_EP2_RD_ADDR + description: Read data address of OUT endpoint 2. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: MISC_CONF + description: Clock enable control + addressOffset: 68 + size: 32 + fields: + - name: CLK_EN + description: "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: MEM_CONF + description: Memory power control + addressOffset: 72 + size: 32 + resetValue: 2 + fields: + - name: USB_MEM_PD + description: "1: power down usb memory." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: USB_MEM_CLK_EN + description: "1: Force clock on for usb memory." + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CHIP_RST + description: CDC-ACM chip reset control. + addressOffset: 76 + size: 32 + fields: + - name: RTS + description: "1: Chip reset is detected from usb serial channel. Software write 1 to clear it." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DTR + description: "1: Chip reset is detected from usb jtag channel. Software write 1 to clear it." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: USB_UART_CHIP_RST_DIS + description: Set this bit to disable chip reset from usb serial channel to reset chip. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: SET_LINE_CODE_W0 + description: W0 of SET_LINE_CODING command. + addressOffset: 80 + size: 32 + fields: + - name: DW_DTE_RATE + description: The value of dwDTERate set by host through SET_LINE_CODING command. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SET_LINE_CODE_W1 + description: W1 of SET_LINE_CODING command. + addressOffset: 84 + size: 32 + fields: + - name: BCHAR_FORMAT + description: The value of bCharFormat set by host through SET_LINE_CODING command. + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: BPARITY_TYPE + description: The value of bParityTpye set by host through SET_LINE_CODING command. + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: BDATA_BITS + description: The value of bDataBits set by host through SET_LINE_CODING command. + bitOffset: 16 + bitWidth: 8 + access: read-only + - register: + name: GET_LINE_CODE_W0 + description: W0 of GET_LINE_CODING command. + addressOffset: 88 + size: 32 + fields: + - name: GET_DW_DTE_RATE + description: The value of dwDTERate set by software which is requested by GET_LINE_CODING command. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: GET_LINE_CODE_W1 + description: W1 of GET_LINE_CODING command. + addressOffset: 92 + size: 32 + fields: + - name: GET_BDATA_BITS + description: The value of bCharFormat set by software which is requested by GET_LINE_CODING command. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GET_BPARITY_TYPE + description: The value of bParityTpye set by software which is requested by GET_LINE_CODING command. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: GET_BCHAR_FORMAT + description: The value of bDataBits set by software which is requested by GET_LINE_CODING command. + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: CONFIG_UPDATE + description: "Configuration registers' value update" + addressOffset: 96 + size: 32 + fields: + - name: CONFIG_UPDATE + description: Write 1 to this register would update the value of configure registers from APB clock domain to 48MHz clock domain. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SER_AFIFO_CONFIG + description: Serial AFIFO configure register + addressOffset: 100 + size: 32 + resetValue: 16 + fields: + - name: SERIAL_IN_AFIFO_RESET_WR + description: Write 1 to reset CDC_ACM IN async FIFO write clock domain. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SERIAL_IN_AFIFO_RESET_RD + description: Write 1 to reset CDC_ACM IN async FIFO read clock domain. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SERIAL_OUT_AFIFO_RESET_WR + description: Write 1 to reset CDC_ACM OUT async FIFO write clock domain. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SERIAL_OUT_AFIFO_RESET_RD + description: Write 1 to reset CDC_ACM OUT async FIFO read clock domain. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SERIAL_OUT_AFIFO_REMPTY + description: CDC_ACM OUTOUT async FIFO empty signal in read clock domain. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SERIAL_IN_AFIFO_WFULL + description: CDC_ACM OUT IN async FIFO empty signal in write clock domain. + bitOffset: 5 + bitWidth: 1 + access: read-only + - register: + name: BUS_RESET_ST + description: USB Bus reset status register + addressOffset: 104 + size: 32 + resetValue: 1 + fields: + - name: USB_BUS_RESET_ST + description: "USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus reset is released." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: ECO_LOW_48 + description: Reserved. + addressOffset: 108 + size: 32 + fields: + - name: RND_ECO_LOW_48 + description: Reserved. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ECO_HIGH_48 + description: Reserved. + addressOffset: 112 + size: 32 + resetValue: 4294967295 + fields: + - name: RND_ECO_HIGH_48 + description: Reserved. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ECO_CELL_CTRL_48 + description: Reserved. + addressOffset: 116 + size: 32 + fields: + - name: RDN_RESULT_48 + description: Reserved. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RDN_ENA_48 + description: Reserved. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: ECO_LOW_APB + description: Reserved. + addressOffset: 120 + size: 32 + fields: + - name: RND_ECO_LOW_APB + description: Reserved. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ECO_HIGH_APB + description: Reserved. + addressOffset: 124 + size: 32 + resetValue: 4294967295 + fields: + - name: RND_ECO_HIGH_APB + description: Reserved. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ECO_CELL_CTRL_APB + description: Reserved. + addressOffset: 128 + size: 32 + fields: + - name: RDN_RESULT_APB + description: Reserved. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RDN_ENA_APB + description: Reserved. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: SRAM_CTRL + description: PPA SRAM Control Register + addressOffset: 132 + size: 32 + resetValue: 4896 + fields: + - name: MEM_AUX_CTRL + description: Control signals + bitOffset: 0 + bitWidth: 14 + access: read-write + - register: + name: DATE + description: Date register + addressOffset: 136 + size: 32 + resetValue: 34676752 + fields: + - name: DATE + description: register version. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: USB_WRAP + description: USB_WRAP Peripheral + groupName: USB_WRAP + baseAddress: 1342701568 + addressBlock: + - offset: 0 + size: 12 + usage: registers + registers: + - register: + name: OTG_CONF + description: USB wrapper configuration registers. + addressOffset: 0 + size: 32 + resetValue: 1048576 + fields: + - name: SRP_SESSEND_OVERRIDE + description: "This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input, 1'b1: the signal is controlled by the software." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SRP_SESSEND_VALUE + description: Software over-ride value of srp session end signal. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PHY_SEL + description: "Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DFIFO_FORCE_PD + description: Force the dfifo to go into low power mode. The data in dfifo will not lost. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DBNCE_FLTR_BYPASS + description: "Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: EXCHG_PINS_OVERRIDE + description: Enable software controlle USB D+ D- exchange + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: EXCHG_PINS + description: "USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: VREFH + description: "Control single-end input high threshold,1.76V to 2V, step 80mV." + bitOffset: 7 + bitWidth: 2 + access: read-write + - name: VREFL + description: "Control single-end input low threshold,0.8V to 1.04V, step 80mV." + bitOffset: 9 + bitWidth: 2 + access: read-write + - name: VREF_OVERRIDE + description: Enable software controlle input threshold. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: PAD_PULL_OVERRIDE + description: Enable software controlle USB D+ D- pullup pulldown. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DP_PULLUP + description: Controlle USB D+ pullup. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DP_PULLDOWN + description: Controlle USB D+ pulldown. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DM_PULLUP + description: Controlle USB D+ pullup. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DM_PULLDOWN + description: Controlle USB D+ pulldown. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PULLUP_VALUE + description: "Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: USB_PAD_ENABLE + description: Enable USB pad function. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: AHB_CLK_FORCE_ON + description: Force ahb clock always on. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PHY_CLK_FORCE_ON + description: Force phy clock always on. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: PHY_TX_EDGE_SEL + description: "Select phy tx signal output clock edge. 1'b0: negedge, 1'b1: posedge." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: DFIFO_FORCE_PU + description: Disable the dfifo to go into low power mode. The data in dfifo will not lost. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: Disable auto clock gating of CSR registers. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TEST_CONF + description: USB wrapper test configuration registers. + addressOffset: 4 + size: 32 + fields: + - name: TEST_ENABLE + description: Enable test of the USB pad. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TEST_USB_OE + description: USB pad oen in test. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TEST_TX_DP + description: USB D+ tx value in test. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TEST_TX_DM + description: USB D- tx value in test. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TEST_RX_RCV + description: USB differential rx value in test. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TEST_RX_DP + description: USB D+ rx value in test. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: TEST_RX_DM + description: USB D- rx value in test. + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: Date register. + addressOffset: 1020 + size: 32 + resetValue: 587400452 + fields: + - name: USB_WRAP_DATE + description: Date register. + bitOffset: 0 + bitWidth: 32 + access: read-only diff --git a/esp32s2-ulp/svd/esp32s2-ulp.svd.yaml b/esp32s2-ulp/svd/esp32s2-ulp.svd.yaml new file mode 100644 index 0000000000..d588dbe930 --- /dev/null +++ b/esp32s2-ulp/svd/esp32s2-ulp.svd.yaml @@ -0,0 +1,1905 @@ +--- +vendor: "ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD." +vendorID: ESPRESSIF +name: ESP32-S2-ULP +series: RISC-V ULP +version: "1" +description: 32-bit RISC-V MCU +licenseText: "Copyright 2023 Espressif Systems (Shanghai) PTE LTD\n\n Licensed under the Apache License, Version 2.0 (the \"License\");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an \"AS IS\" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License." +cpu: + name: RV32IMC + revision: r0p0 + endian: little + mpuPresent: false + fpuPresent: false + nvicPrioBits: 4 + vendorSystickConfig: false +addressUnitBits: 32 +width: 32 +resetValue: 0 +resetMask: 4294967295 +peripherals: + - name: RTC_IO + description: Low-power Input/Output + groupName: RTCIO + baseAddress: 41984 + addressBlock: + - offset: 0 + size: 240 + usage: registers + registers: + - register: + name: OUT + description: RTC GPIO output register + addressOffset: 0 + size: 32 + fields: + - name: GPIO_OUT_DATA + description: "GPIO0 ~ 21 output register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc." + bitOffset: 10 + bitWidth: 22 + access: read-write + - register: + name: OUT_W1TS + description: RTC GPIO output bit set register + addressOffset: 4 + size: 32 + fields: + - name: OUT_DATA_W1TS + description: "GPIO0 ~ 21 output set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_OUT_REG." + bitOffset: 10 + bitWidth: 22 + access: write-only + - register: + name: OUT_W1TC + description: RTC GPIO output bit clear register + addressOffset: 8 + size: 32 + fields: + - name: OUT_DATA_W1TC + description: "GPIO0 ~ 21 output clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_OUT_REG." + bitOffset: 10 + bitWidth: 22 + access: write-only + - register: + name: ENABLE + description: RTC GPIO output enable register + addressOffset: 12 + size: 32 + fields: + - name: REG_RTCIO_REG_GPIO_ENABLE + description: "GPIO0 ~ 21 output enable. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. If the bit is set to 1, it means this GPIO pad is output." + bitOffset: 10 + bitWidth: 22 + access: read-write + - register: + name: ENABLE_W1TS + description: RTC GPIO output enable bit set register + addressOffset: 16 + size: 32 + fields: + - name: REG_RTCIO_REG_GPIO_ENABLE_W1TS + description: "GPIO0 ~ 21 output enable set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_ENABLE_REG." + bitOffset: 10 + bitWidth: 22 + access: write-only + - register: + name: ENABLE_W1TC + description: RTC GPIO output enable bit clear register + addressOffset: 20 + size: 32 + fields: + - name: REG_RTCIO_REG_GPIO_ENABLE_W1TC + description: "GPIO0 ~ 21 output enable clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_ENABLE_REG." + bitOffset: 10 + bitWidth: 22 + access: write-only + - register: + name: STATUS + description: RTC GPIO interrupt status register + addressOffset: 24 + size: 32 + fields: + - name: GPIO_STATUS_INT + description: "GPIO0 ~ 21 interrupt status register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. This register should be used together with RTCIO_RTC_GPIO_PINn_INT_TYPE in RTCIO_RTC_GPIO_PINn_REG. 0: no interrupt; 1: corresponding interrupt." + bitOffset: 10 + bitWidth: 22 + access: read-write + - register: + name: STATUS_W1TS + description: RTC GPIO interrupt status bit set register + addressOffset: 28 + size: 32 + fields: + - name: GPIO_STATUS_INT_W1TS + description: "GPIO0 ~ 21 interrupt set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_GPIO_STATUS_INT will be set to 1. Recommended operation: use this register to set RTCIO_GPIO_STATUS_INT." + bitOffset: 10 + bitWidth: 22 + access: write-only + - register: + name: STATUS_W1TC + description: RTC GPIO interrupt status bit clear register + addressOffset: 32 + size: 32 + fields: + - name: GPIO_STATUS_INT_W1TC + description: "GPIO0 ~ 21 interrupt clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_GPIO_STATUS_INT will be cleared. Recommended operation: use this register to clear RTCIO_GPIO_STATUS_INT." + bitOffset: 10 + bitWidth: 22 + access: write-only + - register: + name: IN + description: RTC GPIO input register + addressOffset: 36 + size: 32 + fields: + - name: GPIO_IN_NEXT + description: "GPIO0 ~ 21 input value. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. Each bit represents a pad input value, 1 for high level, and 0 for low level." + bitOffset: 10 + bitWidth: 22 + access: read-only + - register: + dim: 22 + dimIncrement: 4 + name: PIN%s + description: RTC configuration for pin %s + addressOffset: 40 + size: 32 + fields: + - name: GPIO_PIN_PAD_DRIVER + description: "Pad driver selection. 0: normal output. 1: open drain." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: GPIO_PIN_INT_TYPE + description: "GPIO interrupt type selection. 0: GPIO interrupt disabled. 1: rising edge trigger. 2: falling edge trigger. 3: any edge trigger. 4: low level trigger. 5: high level trigger." + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: GPIO_PIN_WAKEUP_ENABLE + description: GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: RTC_DEBUG_SEL + description: RTC debug select register + addressOffset: 128 + size: 32 + fields: + - name: DEBUG_SEL0 + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: DEBUG_SEL1 + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: DEBUG_SEL2 + bitOffset: 10 + bitWidth: 5 + access: read-write + - name: DEBUG_SEL3 + bitOffset: 15 + bitWidth: 5 + access: read-write + - name: DEBUG_SEL4 + bitOffset: 20 + bitWidth: 5 + access: read-write + - name: DEBUG_12M_NO_GATING + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + dim: 15 + dimIncrement: 4 + name: TOUCH_PAD%s + description: Touch pad %s configuration register + addressOffset: 132 + size: 32 + resetValue: 1375731712 + fields: + - name: FUN_IE + description: Input enable in normal execution. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: Output enable in sleep mode. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: Input enable in sleep mode. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "0: no sleep mode. 1: enable sleep mode." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: Function selection. + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: Connect the RTC pad input to digital pad input. 0 is available. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: Touch sensor power on. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: "The tie option of touch sensor. 0: tie low. 1: tie high." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: Start touch sensor. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: DAC + description: "Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4." + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: RUE + description: "Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: "Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: "Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: XTAL_32P_PAD + description: 32KHz crystal P-pad configuration register + addressOffset: 192 + size: 32 + resetValue: 1073741824 + fields: + - name: X32P_FUN_IE + description: Input enable in normal execution. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: X32P_SLP_OE + description: output enable in sleep mode. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: X32P_SLP_IE + description: input enable in sleep mode. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: X32P_SLP_SEL + description: "1: enable sleep mode. 0: no sleep mode." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: X32P_FUN_SEL + description: Function selection. + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: X32P_MUX_SEL + description: "1: use RTC GPIO. 0: use digital GPIO." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: X32P_RUE + description: "Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: X32P_RDE + description: "Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: X32P_DRV + description: "Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: XTAL_32N_PAD + description: 32KHz crystal N-pad configuration register + addressOffset: 196 + size: 32 + resetValue: 1073741824 + fields: + - name: X32N_FUN_IE + description: Input enable in normal execution. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: X32N_SLP_OE + description: Output enable in sleep mode. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: X32N_SLP_IE + description: Input enable in sleep mode. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: X32N_SLP_SEL + description: "1: enable sleep mode. 0: no sleep mode." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: X32N_FUN_SEL + description: Function selection. + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: X32N_MUX_SEL + description: "1: use RTC GPIO. 0: use digital GPIO." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: X32N_RUE + description: "Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: X32N_RDE + description: "Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: X32N_DRV + description: "Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: PAD_DAC1 + description: DAC1 configuration register + addressOffset: 200 + size: 32 + resetValue: 1073741824 + fields: + - name: PDAC1_DAC + description: Configure DAC_1 output when RTCIO_PDAC1_DAC_XPD_FORCE is set to 1. + bitOffset: 3 + bitWidth: 8 + access: read-write + - name: PDAC1_XPD_DAC + description: "When RTCIO_PDAC1_DAC_XPD_FORCE is set to 1, 1: enable DAC_1 output. 0: disable DAC_1 output." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: PDAC1_DAC_XPD_FORCE + description: "1: use RTCIO_PDAC1_XPD_DAC to control DAC_1 output. 0: use SAR ADC FSM to control DAC_1 output." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PDAC1_FUN_IE + description: Input enable in normal execution. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: PDAC1_SLP_OE + description: Output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PDAC1_SLP_IE + description: Input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: PDAC1_SLP_SEL + description: "1: enable sleep mode. 0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PDAC1_FUN_SEL + description: DAC_1 function selection. + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: PDAC1_MUX_SEL + description: "1: use RTC GPIO. 0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PDAC1_RUE + description: "Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: PDAC1_RDE + description: "Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: PDAC1_DRV + description: "Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: PAD_DAC2 + description: DAC2 configuration register + addressOffset: 204 + size: 32 + resetValue: 1073741824 + fields: + - name: PDAC2_DAC + description: Configure DAC_2 output when RTCIO_PDAC2_DAC_XPD_FORCE is set to 1. + bitOffset: 3 + bitWidth: 8 + access: read-write + - name: PDAC2_XPD_DAC + description: "When RTCIO_PDAC2_DAC_XPD_FORCE is set to 1, 1: enable DAC_2 output. 0: disable DAC_2 output." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: PDAC2_DAC_XPD_FORCE + description: "1: use RTCIO_PDAC2_XPD_DAC to control DAC_2 output. 0: use SAR ADC FSM to control DAC_2 output." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PDAC2_FUN_IE + description: Input enable in normal execution. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: PDAC2_SLP_OE + description: Output enable in sleep mode. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PDAC2_SLP_IE + description: Input enable in sleep mode. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: PDAC2_SLP_SEL + description: "1: enable sleep mode. 0: no sleep mode." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PDAC2_FUN_SEL + description: DAC_2 function selection. + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: PDAC2_MUX_SEL + description: "1: use RTC GPIO. 0: use digital GPIO." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PDAC2_RUE + description: "Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: PDAC2_RDE + description: "Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: PDAC2_DRV + description: "Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: RTC_PAD19 + description: Touch pad 19 configuration register + addressOffset: 208 + size: 32 + resetValue: 1342177280 + fields: + - name: FUN_IE + description: Input enable in normal execution. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: Output enable in sleep mode. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: Input enable in sleep mode. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode. 0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: Function selection. + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO. 0: use digital GPIO." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RUE + description: "Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: "Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: "Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: RTC_PAD20 + description: Touch pad 20 configuration register + addressOffset: 212 + size: 32 + resetValue: 1342177280 + fields: + - name: FUN_IE + description: Input enable in normal execution. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: Output enable in sleep mode. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: Input enable in sleep mode. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode. 0: no sleep mode." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: Function selection. + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO. 0: use digital GPIO." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RUE + description: "Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: "Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: "Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: RTC_PAD21 + description: Touch pad 21 configuration register + addressOffset: 216 + size: 32 + resetValue: 1342177280 + fields: + - name: FUN_IE + description: Input enable in normal execution. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: Output enable in sleep mode. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: Input enable in sleep mode. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode. 0: no sleep mode." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: Function selection. + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO. 0: use digital GPIO." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RUE + description: "Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: "Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: "Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: EXT_WAKEUP0 + description: External wake up configuration register + addressOffset: 220 + size: 32 + fields: + - name: SEL + description: "GPIO[0-17] can be used to wake up the chip when the chip is in the sleep mode. This register prompts the pad source to wake up the chip when the latter is indeep/light sleep mode. \n0: select GPIO0; 1: select GPIO2, etc" + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: XTL_EXT_CTR + description: Crystal power down enable GPIO source + addressOffset: 224 + size: 32 + fields: + - name: SEL + description: "Select the external crystal power down enable source to get into sleep mode. 0: select GPIO0. 1: select GPIO1, etc. The input value on this pin XOR RTC_CNTL_EXT_XTL_CONF_REG[30] is the crystal power down enable signal." + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: SAR_I2C_IO + description: RTC I2C pad selection + addressOffset: 228 + size: 32 + fields: + - name: SAR_DEBUG_BIT_SEL + bitOffset: 23 + bitWidth: 5 + access: read-write + - name: SAR_I2C_SCL_SEL + description: "Selects a pad the RTC I2C SCL signal connects to. 0: use TOUCH PAD0. 1: use TOUCH PAD2." + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: SAR_I2C_SDA_SEL + description: "Selects a pad the RTC I2C SDA signal connects to. 0: use TOUCH PAD1. 1: use TOUCH PAD3." + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: RTC_IO_TOUCH_CTRL + description: Touch control register + addressOffset: 232 + size: 32 + fields: + - name: IO_TOUCH_BUFSEL + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: IO_TOUCH_BUFMODE + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: RTC_IO_DATE + description: Version control register + addressOffset: 508 + size: 32 + resetValue: 26227056 + fields: + - name: IO_DATE + description: Version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: RTC_CNTL + description: Real-Time Clock Control + groupName: RTC_CNTL + baseAddress: 32768 + addressBlock: + - offset: 0 + size: 312 + usage: registers + interrupt: + - name: RISCV_START_INT + value: 6 + - name: SW_INT + value: 7 + - name: SWD_INT + value: 8 + registers: + - register: + name: ULP_CP_TIMER + description: Configure coprocessor timer + addressOffset: 248 + size: 32 + fields: + - name: ULP_CP_PC_INIT + description: ULP coprocessor PC initial address + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: ULP_CP_GPIO_WAKEUP_ENA + description: "Enable the option of ULP coprocessor woken up by\nRTC GPIO" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ULP_CP_GPIO_WAKEUP_CLR + description: "Disable the option of ULP coprocessor woken up by\nRTC GPIO" + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: ULP_CP_SLP_TIMER_EN + description: "ULP coprocessor timer enable bit. 0: Disable hardware\nTimer. 1: Enable hardware timer" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: ULP_CP_CTRL + description: ULP-FSM configuration register + addressOffset: 252 + size: 32 + resetValue: 1049088 + fields: + - name: ULP_CP_MEM_ADDR_INIT + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: ULP_CP_MEM_ADDR_SIZE + bitOffset: 11 + bitWidth: 11 + access: read-write + - name: ULP_CP_MEM_OFFSET_CLR + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: ULP_CP_CLK_FO + description: ULP-FSM clock force on + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: ULP_CP_RESET + description: ULP-FSM clock software reset + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ULP_CP_FORCE_START_TOP + description: Write 1 to start ULP-FSM by software + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: ULP_CP_START_TOP + description: Write 1 to start ULP-FSM + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COCPU_CTRL + description: ULP-RISCV configuration register + addressOffset: 256 + size: 32 + resetValue: 9046032 + fields: + - name: COCPU_CLK_FO + description: ULP-RISCV clock force on + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: COCPU_START_2_RESET_DIS + description: Time from ULP-RISCV startup to pull down reset + bitOffset: 1 + bitWidth: 6 + access: read-write + - name: COCPU_START_2_INTR_EN + description: "Time from ULP-RISCV startup to send out\nRISCV_START_INT interrupt" + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: COCPU_SHUT + description: Shut down ULP-RISCV + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: COCPU_SHUT_2_CLK_DIS + description: Time from shut down ULP-RISCV to disable clock + bitOffset: 14 + bitWidth: 8 + access: read-write + - name: COCPU_SHUT_RESET_EN + description: This bit is used to reset ULP-RISCV + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: COCPU_SEL + description: "0: select ULP-RISCV. 1: select ULP-FSM" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: COCPU_DONE_FORCE + description: "0: select ULP-FSM DONE signal. 1: select ULP-RISCV DONE\nsignal" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: COCPU_DONE + description: "DONE signal. Write 1 to this bit, ULP-RISCV will go to HALT and the\ntimer starts counting" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: COCPU_SW_INT_TRIGGER + description: Trigger ULP-RISCV register interrupt + bitOffset: 26 + bitWidth: 1 + access: write-only + - register: + name: ULP_CP_TIMER_1 + description: Configure sleep cycle of the timer + addressOffset: 304 + size: 32 + resetValue: 51200 + fields: + - name: ULP_CP_TIMER_SLP_CYCLE + description: Set sleep cycles for ULP coprocessor timer + bitOffset: 8 + bitWidth: 24 + access: read-write + - name: RTC_I2C + description: Low-power I2C (Inter-Integrated Circuit) Controller + groupName: RTC_I2C + baseAddress: 60416 + addressBlock: + - offset: 0 + size: 124 + usage: registers + registers: + - register: + name: SCL_LOW + description: Configure the low level width of SCL + addressOffset: 0 + size: 32 + resetValue: 256 + fields: + - name: PERIOD + description: "This register is used to configure how many clock cycles SCL\nremains low." + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: CTRL + description: Transmission setting + addressOffset: 4 + size: 32 + fields: + - name: SDA_FORCE_OUT + description: "SDA output mode. 0: open drain. 1: push pull." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_FORCE_OUT + description: "SCL output mode. 0: open drain. 1: push pull." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MS_MODE + description: Set this bit to configure RTC I²C as a master. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TRANS_START + description: "Set this bit to 1, RTC I2C starts sending data." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_LSB_FIRST + description: "This bit is used to control the sending mode. 0: send data from the most\nsignificant bit. 1: send data from the least significant bit." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_LSB_FIRST + description: "This bit is used to control the storage mode for received data. 0: receive\ndata from the most significant bit. 1: receive data from the least significant bit." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CLK_GATE_EN + description: RTC I²C controller clock gate. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: RESET + description: RTC I²C software reset. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: rtc i2c reg clk gating + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: STATUS + description: RTC I2C status + addressOffset: 8 + size: 32 + fields: + - name: ACK_REC + description: "The received ACK value. 0: ACK. 1: NACK." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SLAVE_RW + description: "0: master writes to slave. 1: master reads from slave." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ARB_LOST + description: "When the RTC I2C loses control of SCL line, the register changes to 1." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: BUS_BUSY + description: "0: RTC I2C bus is in idle state. 1: RTC I2C bus is busy transferring data." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SLAVE_ADDRESSED + description: "When the address sent by the master matches the address of the\nslave, then this bit will be set." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS + description: This field changes to 1 when one byte is transferred. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OP_CNT + description: Indicate which operation is working. + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: SHIFT + description: shifter content + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: SCL_MAIN_STATE_LAST + description: i2c last main status + bitOffset: 24 + bitWidth: 3 + access: read-only + - name: SCL_STATE_LAST + description: scl last status + bitOffset: 28 + bitWidth: 3 + access: read-only + - register: + name: TO + description: Configure RTC I2C timeout + addressOffset: 12 + size: 32 + resetValue: 65536 + fields: + - name: TIME_OUT + description: Timeout threshold + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: SLAVE_ADDR + description: Configure slave address + addressOffset: 16 + size: 32 + fields: + - name: SLAVE_ADDR + description: slave address + bitOffset: 0 + bitWidth: 15 + access: read-write + - name: ADDR_10BIT_EN + description: This field is used to enable the slave 10-bit addressing mode. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SCL_HIGH + description: Configure the high level width of SCL + addressOffset: 20 + size: 32 + resetValue: 256 + fields: + - name: PERIOD + description: This register is used to configure how many cycles SCL remains high. + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: SDA_DUTY + description: "Configure the SDA hold time after a negative\nSCL edge" + addressOffset: 24 + size: 32 + resetValue: 16 + fields: + - name: NUM + description: "The number of clock cycles between the SDA switch and the falling\nedge of SCL." + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: SCL_START_PERIOD + description: "Configure the delay between the SDA and SCL\nnegative edge for a start condition" + addressOffset: 28 + size: 32 + resetValue: 8 + fields: + - name: SCL_START_PERIOD + description: Number of clock cycles to wait after generating a start condition. + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: SCL_STOP_PERIOD + description: Configure the delay between SDA and SCL positive edge for a stop condition + addressOffset: 32 + size: 32 + resetValue: 8 + fields: + - name: SCL_STOP_PERIOD + description: Number of clock cycles to wait before generating a stop condition. + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: INT_CLR + description: Clear RTC I2C interrupt + addressOffset: 36 + size: 32 + fields: + - name: SLAVE_TRAN_COMP_INT_CLR + description: RTC_I2C_SLAVE_TRAN_COMP_INT interrupt clear bit + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ARBITRATION_LOST_INT_CLR + description: RTC_I2C_ARBITRATION_LOST_INT interrupt clear bit + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: MASTER_TRAN_COMP_INT_CLR + description: "RTC_I2C_MASTER_TRAN_COMP_INT interrupt\nclear bit" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TRANS_COMPLETE_INT_CLR + description: RTC_I2C_TRANS_COMPLETE_INT interrupt clear bit + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TIME_OUT_INT_CLR + description: RTC_I2C_TIME_OUT_INT interrupt clear bit + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: ACK_ERR_INT_CLR + description: RTC_I2C_ACK_ERR_INT interrupt clear bit + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: RX_DATA_INT_CLR + description: RTC_I2C_RX_DATA_INT interrupt clear bit + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TX_DATA_INT_CLR + description: RTC_I2C_TX_DATA_INT interrupt clear bit + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: DETECT_START_INT_CLR + description: RTC_I2C_DETECT_START_INT interrupt clear bit + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: INT_RAW + description: RTC I2C raw interrupt + addressOffset: 40 + size: 32 + fields: + - name: SLAVE_TRAN_COMP_INT_RAW + description: RTC_I2C_SLAVE_TRAN_COMP_INT interrupt raw bit + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_RAW + description: RTC_I2C_ARBITRATION_LOST_INT interrupt raw bit + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: MASTER_TRAN_COMP_INT_RAW + description: RTC_I2C_MASTER_TRAN_COMP_INT interrupt raw bit + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_RAW + description: RTC_I2C_TRANS_COMPLETE_INT interrupt raw bit + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_RAW + description: RTC_I2C_TIME_OUT_INT interrupt raw bit + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ACK_ERR_INT_RAW + description: RTC_I2C_ACK_ERR_INT interrupt raw bit + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: RX_DATA_INT_RAW + description: RTC_I2C_RX_DATA_INT interrupt raw bit + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TX_DATA_INT_RAW + description: RTC_I2C_TX_DATA_INT interrupt raw bit + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DETECT_START_INT_RAW + description: RTC_I2C_DETECT_START_INT interrupt raw bit + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: RTC I2C interrupt status + addressOffset: 44 + size: 32 + fields: + - name: SLAVE_TRAN_COMP_INT_ST + description: RTC_I2C_SLAVE_TRAN_COMP_INT interrupt status bit + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_ST + description: RTC_I2C_ARBITRATION_LOST_INT interrupt status bit + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: MASTER_TRAN_COMP_INT_ST + description: RTC_I2C_MASTER_TRAN_COMP_INT interrupt status bit + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_ST + description: RTC_I2C_TRANS_COMPLETE_INT interrupt status bit + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_ST + description: RTC_I2C_TIME_OUT_INT interrupt status bit + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ACK_ERR_INT_ST + description: RTC_I2C_ACK_ERR_INT interrupt status bit + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: RX_DATA_INT_ST + description: RTC_I2C_RX_DATA_INT interrupt status bit + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TX_DATA_INT_ST + description: RTC_I2C_TX_DATA_INT interrupt status bit + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DETECT_START_INT_ST + description: RTC_I2C_DETECT_START_INT interrupt status bit + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Enable RTC I2C interrupt + addressOffset: 48 + size: 32 + fields: + - name: SLAVE_TRAN_COMP_INT_ENA + description: RTC_I2C_SLAVE_TRAN_COMP_INT interrupt enable bit + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ARBITRATION_LOST_INT_ENA + description: RTC_I2C_ARBITRATION_LOST_INT interrupt enable bit + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MASTER_TRAN_COMP_INT_ENA + description: RTC_I2C_MASTER_TRAN_COMP_INT interrupt enable bit + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TRANS_COMPLETE_INT_ENA + description: RTC_I2C_TRANS_COMPLETE_INT interrupt enable bit + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TIME_OUT_INT_ENA + description: RTC_I2C_TIME_OUT_INT interrupt enable bit + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ACK_ERR_INT_ENA + description: RTC_I2C_ACK_ERR_INT interrupt enable bit + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RX_DATA_INT_ENA + description: RTC_I2C_RX_DATA_INT interrupt enable bit + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_DATA_INT_ENA + description: RTC_I2C_TX_DATA_INT interrupt enable bit + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DETECT_START_INT_ENA + description: RTC_I2C_DETECT_START_INT interrupt enable bit + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: DATA + description: RTC I2C read data + addressOffset: 52 + size: 32 + fields: + - name: RDATA + description: Data received + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: SLAVE_TX_DATA + description: The data sent by slave + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: DONE + description: RTC I2C transmission is done. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD0 + description: RTC I2C Command 0 + addressOffset: 56 + size: 32 + resetValue: 2307 + fields: + - name: COMMAND0 + description: "Content of command 0. For more information, please refer to the register\nI2C_COMD0_REG in Chapter I²C Controller" + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND0_DONE + description: "When command 0 is done, this bit changes to 1." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD1 + description: RTC I2C Command 1 + addressOffset: 60 + size: 32 + resetValue: 6401 + fields: + - name: COMMAND1 + description: "Content of command 1. For more information, please refer to the register\nI2C_COMD1_REG in Chapter I²C Controller." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND1_DONE + description: "When command 1 is done, this bit changes to 1." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD2 + description: RTC I2C Command 2 + addressOffset: 64 + size: 32 + resetValue: 2306 + fields: + - name: COMMAND2 + description: "Content of command 2. For more information, please refer to the register\nI2C_COMD2_REG in Chapter I²C Controller." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND2_DONE + description: "When command 2 is done, this bit changes to 1." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD3 + description: RTC I2C Command 3 + addressOffset: 68 + size: 32 + resetValue: 257 + fields: + - name: COMMAND3 + description: "Content of command 3. For more information, please refer to the register\nI2C_COMD3_REG in Chapter I²C Controller." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND3_DONE + description: "When command 3 is done, this bit changes to 1." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD4 + description: RTC I2C Command 4 + addressOffset: 72 + size: 32 + resetValue: 2305 + fields: + - name: COMMAND4 + description: "Content of command 4. For more information, please refer to the register\nI2C_COMD4_REG in Chapter I²C Controller." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND4_DONE + description: "When command 4 is done, this bit changes to 1." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD5 + description: RTC I2C Command 5 + addressOffset: 76 + size: 32 + resetValue: 5889 + fields: + - name: COMMAND5 + description: "Content of command 5. For more information, please refer to the register\nI2C_COMD5_REG in Chapter I²C Controller." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND5_DONE + description: "When command 5 is done, this bit changes to 1." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD6 + description: RTC I2C Command 6 + addressOffset: 80 + size: 32 + resetValue: 6401 + fields: + - name: COMMAND6 + description: "Content of command 6. For more information, please refer to the register\nI2C_COMD6_REG in Chapter I²C Controller." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND6_DONE + description: "When command 6 is done, this bit changes to 1." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD7 + description: RTC I2C Command 7 + addressOffset: 84 + size: 32 + resetValue: 2308 + fields: + - name: COMMAND7 + description: "Content of command 7. For more information, please refer to the register\nI2C_COMD7_REG in Chapter I²C Controller." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND7_DONE + description: "When command 7 is done, this bit changes to 1." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD8 + description: RTC I2C Command 8 + addressOffset: 88 + size: 32 + resetValue: 6401 + fields: + - name: COMMAND8 + description: "Content of command 8. For more information, please refer to the register\nI2C_COMD8_REG in Chapter I²C Controller." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND8_DONE + description: "When command 8 is done, this bit changes to 1." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD9 + description: RTC I2C Command 9 + addressOffset: 92 + size: 32 + resetValue: 2307 + fields: + - name: COMMAND9 + description: "Content of command 9. For more information, please refer to the register\nI2C_COMD9_REG in Chapter I²C Controller" + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND9_DONE + description: "When command 9 is done, this bit changes to 1." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD10 + description: RTC I2C Command 10 + addressOffset: 96 + size: 32 + resetValue: 257 + fields: + - name: COMMAND10 + description: "Content of command 10. For more information, please refer to the register\nI2C_COMD10_REG in Chapter I²C Controller." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND10_DONE + description: "When command 10 is done, this bit changes to 1." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD11 + description: RTC I2C Command 11 + addressOffset: 100 + size: 32 + resetValue: 2305 + fields: + - name: COMMAND11 + description: "Content of command 11. For more information, please refer to the register\nI2C_COMD11_REG in Chapter I²C Controller." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND11_DONE + description: "When command 11 is done, this bit changes to 1." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD12 + description: RTC I2C Command 12 + addressOffset: 104 + size: 32 + resetValue: 5889 + fields: + - name: COMMAND12 + description: "Content of command 12. For more information, please refer to the register\nI2C_COMD12_REG in Chapter I²C Controller." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND12_DONE + description: "When command 12 is done, this bit changes to 1." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD13 + description: RTC I2C Command 13 + addressOffset: 108 + size: 32 + resetValue: 6401 + fields: + - name: COMMAND13 + description: "Content of command 13. For more information, please refer to the register\nI2C_COMD13_REG in Chapter I²C Controller." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND13_DONE + description: "When command 13 is done, this bit changes to 1." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD14 + description: RTC I2C Command 14 + addressOffset: 112 + size: 32 + fields: + - name: COMMAND14 + description: "Content of command 14. For more information, please refer to the register\nI2C_COMD14_REG in Chapter I²C Controller." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND14_DONE + description: "When command 14 is done, this bit changes to 1." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD15 + description: RTC I2C Command 15 + addressOffset: 116 + size: 32 + fields: + - name: COMMAND15 + description: "Content of command 15. For more information, please refer to the register\nI2C_COMD15_REG in Chapter I²C Controller." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND15_DONE + description: "When command 15 is done, this bit changes to 1." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: Version control register + addressOffset: 252 + size: 32 + resetValue: 26235664 + fields: + - name: DATE + description: Version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SENS + description: SENS Peripheral + groupName: SENS + baseAddress: 51200 + addressBlock: + - offset: 0 + size: 272 + usage: registers + interrupt: + - name: TOUCH_DONE_INT + value: 0 + - name: TOUCH_INACTIVE_INT + value: 1 + - name: TOUCH_ACTIVE_INT + value: 2 + - name: SARADC1_DONE_INT + value: 3 + - name: SARADC2_DONE_INT + value: 4 + - name: TSENS_DONE_INT + value: 5 + registers: + - register: + name: SAR_SLAVE_ADDR1 + description: Configure slave addresses 0-1 of RTC I2C + addressOffset: 64 + size: 32 + fields: + - name: I2C_SLAVE_ADDR1 + description: RTC I2C slave address 1 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: I2C_SLAVE_ADDR0 + description: RTC I2C slave address 0 + bitOffset: 11 + bitWidth: 11 + access: read-write + - name: MEAS_STATUS + bitOffset: 22 + bitWidth: 8 + access: read-only + - register: + name: SAR_SLAVE_ADDR2 + description: Configure slave addresses 2-3 of RTC I2C + addressOffset: 68 + size: 32 + fields: + - name: I2C_SLAVE_ADDR3 + description: RTC I2C slave address 3 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: I2C_SLAVE_ADDR2 + description: RTC I2C slave address 2 + bitOffset: 11 + bitWidth: 11 + access: read-write + - register: + name: SAR_SLAVE_ADDR3 + description: Configure slave addresses 4-5 of RTC I2C + addressOffset: 72 + size: 32 + fields: + - name: I2C_SLAVE_ADDR5 + description: RTC I2C slave address 5 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: I2C_SLAVE_ADDR4 + description: RTC I2C slave address 4 + bitOffset: 11 + bitWidth: 11 + access: read-write + - register: + name: SAR_SLAVE_ADDR4 + description: Configure slave addresses 6-7 of RTC I2C + addressOffset: 76 + size: 32 + fields: + - name: I2C_SLAVE_ADDR7 + description: RTC I2C slave address 7 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: I2C_SLAVE_ADDR6 + description: RTC I2C slave address 6 + bitOffset: 11 + bitWidth: 11 + access: read-write + - register: + name: SAR_I2C_CTRL + description: Configure RTC I2C transmission + addressOffset: 88 + size: 32 + fields: + - name: SAR_I2C_CTRL + description: "RTC I2C control data. Active only when SENS_SAR_I2C_START_FORCE =\n1." + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SAR_I2C_START + description: Start RTC I2C. Active only when SENS_SAR_I2C_START_FORCE = 1 + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SAR_I2C_START_FORCE + description: "0: RTC I2C started by FSM. 1: RTC I2C started by software." + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: SAR_COCPU_INT_RAW + description: Interrupt raw bit of ULP-RISCV + addressOffset: 296 + size: 32 + fields: + - name: COCPU_TOUCH_DONE_INT_RAW + description: TOUCH_DONE_INT interrupt raw bit + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: COCPU_TOUCH_INACTIVE_INT_RAW + description: TOUCH_INACTIVE_INT interrupt raw bit + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: COCPU_TOUCH_ACTIVE_INT_RAW + description: TOUCH_ACTIVE_INT interrupt raw bit + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: COCPU_SARADC1_INT_RAW + description: SARADC1_DONE_INT interrupt raw bit + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: COCPU_SARADC2_INT_RAW + description: SARADC2_DONE_INT interrupt raw bit + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: COCPU_TSENS_INT_RAW + description: TSENS_DONE_INT interrupt raw bit + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: COCPU_START_INT_RAW + description: RISCV_START_INT interrupt raw bit + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: COCPU_SW_INT_RAW + description: SW_INT interrupt raw bit + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: COCPU_SWD_INT_RAW + description: SWD_INT interrupt raw bit + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: SAR_COCPU_INT_ENA + description: Interrupt enable bit of ULP-RISCV + addressOffset: 300 + size: 32 + fields: + - name: COCPU_TOUCH_DONE_INT_ENA + description: TOUCH_DONE_INT interrupt enable bit + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: COCPU_TOUCH_INACTIVE_INT_ENA + description: TOUCH_INACTIVE_INT interrupt enable bit + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: COCPU_TOUCH_ACTIVE_INT_ENA + description: TOUCH_ACTIVE_INT interrupt enable bit + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: COCPU_SARADC1_INT_ENA + description: SARADC1_DONE_INT interrupt enable bit + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: COCPU_SARADC2_INT_ENA + description: SARADC2_DONE_INT interrupt enable bit + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: COCPU_TSENS_INT_ENA + description: TSENS_DONE_INT interrupt enable bit + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: COCPU_START_INT_ENA + description: RISCV_START_INT interrupt enable bit + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: COCPU_SW_INT_ENA + description: SW_INT interrupt enable bit + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: COCPU_SWD_INT_ENA + description: SWD_INT interrupt enable bit + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: SAR_COCPU_INT_ST + description: Interrupt status bit of ULP-RISCV + addressOffset: 304 + size: 32 + fields: + - name: COCPU_TOUCH_DONE_INT_ST + description: TOUCH_DONE_INT interrupt status bit + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: COCPU_TOUCH_INACTIVE_INT_ST + description: TOUCH_INACTIVE_INT interrupt status bit + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: COCPU_TOUCH_ACTIVE_INT_ST + description: TOUCH_ACTIVE_INT interrupt status bit + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: COCPU_SARADC1_INT_ST + description: SARADC1_DONE_INT interrupt status bit + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: COCPU_SARADC2_INT_ST + description: SARADC2_DONE_INT interrupt status bit + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: COCPU_TSENS_INT_ST + description: TSENS_DONE_INT interrupt status bit + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: COCPU_START_INT_ST + description: RISCV_START_INT interrupt status bit + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: COCPU_SW_INT_ST + description: SW_INT interrupt status bit + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: COCPU_SWD_INT_ST + description: SWD_INT interrupt status bit + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: SAR_COCPU_INT_CLR + description: Interrupt clear bit of ULP-RISCV + addressOffset: 308 + size: 32 + fields: + - name: COCPU_TOUCH_DONE_INT_CLR + description: TOUCH_DONE_INT interrupt clear bit + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: COCPU_TOUCH_INACTIVE_INT_CLR + description: TOUCH_INACTIVE_INT interrupt clear bit + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: COCPU_TOUCH_ACTIVE_INT_CLR + description: TOUCH_ACTIVE_INT interrupt clear bit + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: COCPU_SARADC1_INT_CLR + description: SARADC1_DONE_INT interrupt clear bit + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: COCPU_SARADC2_INT_CLR + description: SARADC2_DONE_INT interrupt clear bit + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: COCPU_TSENS_INT_CLR + description: TSENS_DONE_INT interrupt clear bit + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: COCPU_START_INT_CLR + description: RISCV_START_INT interrupt clear bit + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: COCPU_SW_INT_CLR + description: SW_INT interrupt clear bit + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: COCPU_SWD_INT_CLR + description: SWD_INT interrupt clear bit + bitOffset: 8 + bitWidth: 1 + access: write-only diff --git a/esp32s2/svd/esp32s2.svd.yaml b/esp32s2/svd/esp32s2.svd.yaml new file mode 100644 index 0000000000..b199aee92f --- /dev/null +++ b/esp32s2/svd/esp32s2.svd.yaml @@ -0,0 +1,33272 @@ +--- +vendor: "ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD." +vendorID: ESPRESSIF +name: ESP32-S2 +series: ESP32 S-Series +version: "19" +description: 32-bit MCU & 2.4 GHz Wi-Fi +licenseText: "Copyright 2024 Espressif Systems (Shanghai) PTE LTD\n\n Licensed under the Apache License, Version 2.0 (the \"License\");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an \"AS IS\" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License." +cpu: + name: Xtensa LX7 + revision: r0p0 + endian: little + mpuPresent: false + fpuPresent: false + nvicPrioBits: 0 + vendorSystickConfig: false +addressUnitBits: 32 +width: 32 +resetValue: 0 +resetMask: 4294967295 +peripherals: + - name: AES + description: AES (Advanced Encryption Standard) Accelerator + groupName: AES + baseAddress: 1610850304 + addressBlock: + - offset: 0 + size: 188 + usage: registers + interrupt: + - name: AES + value: 56 + registers: + - register: + dim: 8 + dimIncrement: 4 + name: "KEY[%s]" + description: AES key register %s + addressOffset: 0 + size: 32 + fields: + - name: KEY + description: Stores AES keys. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: "TEXT_IN[%s]" + description: Source data register %s + addressOffset: 32 + size: 32 + fields: + - name: TEXT_IN + description: Stores the source data when the AES Accelerator operates in the Typical AES working mode. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: "TEXT_OUT[%s]" + description: Result data register %s + addressOffset: 48 + size: 32 + fields: + - name: TEXT_OUT + description: Stores the result data when the AES Accelerator operates in the Typical AES working mode. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: MODE + description: AES working mode configuration register + addressOffset: 64 + size: 32 + fields: + - name: MODE + description: "Defines the operation type of the AES Accelerator operating under the Typical AES working mode.\n&\n0x0(AES_EN_128): AES-EN-128 #\n0x1(AES_EN_192): AES-EN-192 #\n0x2(AES_EN_256): AES-EN-256 #\n0x4(AES_DE_128): AES-DE-128 #\n0x5(AES_DE_192): AES-DE-192 #\n0x6(AES_DE_256): AES-DE-256 \n&" + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: ENDIAN + description: Endian configuration register + addressOffset: 68 + size: 32 + fields: + - name: ENDIAN + description: "Defines the endianness of input and output texts.\n&\n[1:0] key endian #\n[3:2] text_in endian or in_stream endian #\n[5:4] text_out endian or out_stream endian #\n&" + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: TRIGGER + description: Operation start controlling register + addressOffset: 72 + size: 32 + fields: + - name: TRIGGER + description: Set this bit to 1 to start AES operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: STATE + description: Operation status register + addressOffset: 76 + size: 32 + fields: + - name: STATE + description: "Stores the working status of the AES Accelerator. For details, see Table 3 for Typical AES working mode and Table 9 for DMA AES working mode.\nFor typical AES; 0 = idle; 1 = busy.\nFor DMA-AES; 0 = idle; 1 = busy; 2 = calculation_done." + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + dim: 4 + dimIncrement: 4 + name: IV_%s + description: initialization vector + addressOffset: 80 + size: 32 + fields: + - name: IV + description: This register stores the %sth 32-bit piece of 128-bit initialization vector + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: H_%s + description: GCM hash subkey + addressOffset: 96 + size: 32 + fields: + - name: H + description: GCM hash subkey + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + dim: 4 + dimIncrement: 4 + name: J0_%s + description: J0 + addressOffset: 112 + size: 32 + fields: + - name: J0 + description: This register stores the %sth 32-bit piece of 128-bit J0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: T0_%s + description: T0 + addressOffset: 128 + size: 32 + fields: + - name: T0 + description: This register stores the %sth 32-bit piece of 128-bit T0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DMA_ENABLE + description: DMA enable register + addressOffset: 144 + size: 32 + fields: + - name: DMA_ENABLE + description: "Defines the working mode of the AES Accelerator. For details, see Table 1.\n1'h0: typical AES operation\n1'h1: DMA-AES operation" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: BLOCK_MODE + description: Block operation type register + addressOffset: 148 + size: 32 + fields: + - name: BLOCK_MODE + description: "Defines the operation type of the AES Accelerator operating under the DMA-AES working mode. For details, see Table 8.\n&\n3'h0(BLOCK_MODE_ECB): ECB #\n3'h1(BLOCK_MODE_CBC): CBC #\n3'h2(BLOCK_MODE_OFB): OFB #\n3'h3(BLOCK_MODE_CTR): CTR #\n3'h4(BLOCK_MODE_CFB8): CFB-8 #\n3'h5(BLOCK_MODE_CFB128): CFB-128 #\n3'h6(BLOCK_MODE_GCM): GCM\n&" + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: BLOCK_NUM + description: Block number configuration register + addressOffset: 152 + size: 32 + fields: + - name: BLOCK_NUM + description: "Stores the Block Number of plaintext or cipertext when the AES Accelerator operates under the DMA-AES working mode. For details, see Section 1.5.4." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: INC_SEL + description: Standard incrementing function register + addressOffset: 156 + size: 32 + fields: + - name: INC_SEL + description: Defines the Standard Incrementing Function for CTR block operation. Set this bit to 0 or 1 to choose INC 32 or INC 128 . + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: AAD_BLOCK_NUM + description: AAD block number configuration register + addressOffset: 160 + size: 32 + fields: + - name: AAD_BLOCK_NUM + description: Stores the ADD Block Number for the GCM operation. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REMAINDER_BIT_NUM + description: Remainder bit number of plaintext/ciphertext + addressOffset: 164 + size: 32 + fields: + - name: REMAINDER_BIT_NUM + description: Stores the Remainder Bit Number for the GCM operation. + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: CONTINUE_OP + description: Operation continue controlling register + addressOffset: 168 + size: 32 + fields: + - name: CONTINUE_OP + description: Set this bit to 1 to continue AES operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: INT_CLR + description: DMA-AES interrupt clear register + addressOffset: 172 + size: 32 + fields: + - name: INT_CLR + description: Set this bit to 1 to clear AES interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + description: DMA-AES interrupt enable register + addressOffset: 176 + size: 32 + fields: + - name: INT_ENA + description: Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 180 + size: 32 + resetValue: 538510612 + fields: + - name: DATE + description: Version control register + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: DMA_EXIT + description: Operation exit controlling register + addressOffset: 184 + size: 32 + fields: + - name: DMA_EXIT + description: Set this bit to 1 to exit AES operation. This register is only effective for DMA-AES operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: APB_SARADC + description: SAR (Successive Approximation Register) Analog-to-Digital Converter + groupName: APB_SARADC + baseAddress: 1061421056 + addressBlock: + - offset: 0 + size: 104 + usage: registers + interrupt: + - name: APB_ADC + value: 89 + registers: + - register: + name: CTRL + description: DIG ADC common configuration + addressOffset: 0 + size: 32 + resetValue: 1082098240 + fields: + - name: START_FORCE + description: "0: select FSM to start SAR ADC. 1: select software to start SAR ADC." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: START + description: Start SAR ADC by software. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: WORK_MODE + description: "0: single-channel scan mode. 1: double-channel scan mode. 2:\nalternate-channel scan mode." + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: SAR_SEL + description: "0: select SAR ADC1. 1: select SAR ADC2, only work for single-channel scan mode." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SAR_CLK_GATED + description: SAR clock gate enable bit. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SAR_CLK_DIV + description: SAR clock divider + bitOffset: 7 + bitWidth: 8 + access: read-write + - name: SAR1_PATT_LEN + description: 0 ~ 15 means length 1 ~ 16 + bitOffset: 15 + bitWidth: 4 + access: read-write + - name: SAR2_PATT_LEN + description: 0 ~ 15 means length 1 ~ 16 + bitOffset: 19 + bitWidth: 4 + access: read-write + - name: SAR1_PATT_P_CLEAR + description: Clear the pointer of pattern table for DIG ADC1 CTRL. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SAR2_PATT_P_CLEAR + description: Clear the pointer of pattern table for DIG ADC2 CTRL. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: DATA_SAR_SEL + description: "1: sar_sel will be coded to the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: DATA_TO_I2S + description: "1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: XPD_SAR_FORCE + description: Force option to xpd sar blocks. + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: WAIT_ARB_CYCLE + description: Wait arbit signal stable after sar_done. + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CTRL2 + description: DIG ADC common configuration + addressOffset: 4 + size: 32 + resetValue: 41470 + fields: + - name: MEAS_NUM_LIMIT + description: Enable limit times of SAR ADC sample. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MAX_MEAS_NUM + description: Set maximum conversion number. + bitOffset: 1 + bitWidth: 8 + access: read-write + - name: SAR1_INV + description: "1: data to DIG ADC1 CTRL is inverted, otherwise not." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SAR2_INV + description: "1: data to DIG ADC2 CTRL is inverted, otherwise not." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TIMER_SEL + description: "1: select saradc timer 0: i2s_ws trigger" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TIMER_TARGET + description: Set SAR ADC timer target. + bitOffset: 12 + bitWidth: 12 + access: read-write + - name: TIMER_EN + description: Enable SAR ADC timer trigger. + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: FSM + description: digital adc control register + addressOffset: 8 + size: 32 + resetValue: 33554432 + fields: + - name: SAMPLE_NUM + description: sample number + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SAMPLE_CYCLE + description: sample cycles + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: FSM_WAIT + description: configure saradc fsm internal parameter base on test + addressOffset: 12 + size: 32 + resetValue: 16713736 + fields: + - name: XPD_WAIT + description: xpd wait + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: RSTB_WAIT + description: reset time + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: STANDBY_WAIT + description: standby wait + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: SAR1_STATUS + description: digital adc1 status + addressOffset: 16 + size: 32 + fields: + - name: SAR1_STATUS + description: digital adc1 status + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SAR2_STATUS + description: digital adc2 status + addressOffset: 20 + size: 32 + fields: + - name: SAR2_STATUS + description: digital adc2 status + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SAR1_PATT_TAB1 + description: item 0 ~ 3 for pattern table 1 (each item one byte) + addressOffset: 24 + size: 32 + resetValue: 252645135 + fields: + - name: SAR1_PATT_TAB1 + description: item 0 ~ 3 for pattern table 1 (each item one byte) + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SAR1_PATT_TAB2 + description: Item 4 ~ 7 for pattern table 1 (each item one byte) + addressOffset: 28 + size: 32 + resetValue: 252645135 + fields: + - name: SAR1_PATT_TAB2 + description: Item 4 ~ 7 for pattern table 1 (each item one byte) + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SAR1_PATT_TAB3 + description: Item 8 ~ 11 for pattern table 1 (each item one byte) + addressOffset: 32 + size: 32 + resetValue: 252645135 + fields: + - name: SAR1_PATT_TAB3 + description: Item 8 ~ 11 for pattern table 1 (each item one byte) + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SAR1_PATT_TAB4 + description: Item 12 ~ 15 for pattern table 1 (each item one byte) + addressOffset: 36 + size: 32 + resetValue: 252645135 + fields: + - name: SAR1_PATT_TAB4 + description: Item 12 ~ 15 for pattern table 1 (each item one byte) + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SAR2_PATT_TAB1 + description: item 0 ~ 3 for pattern table 2 (each item one byte) + addressOffset: 40 + size: 32 + resetValue: 252645135 + fields: + - name: SAR2_PATT_TAB1 + description: item 0 ~ 3 for pattern table 2 (each item one byte) + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SAR2_PATT_TAB2 + description: Item 4 ~ 7 for pattern table 2 (each item one byte) + addressOffset: 44 + size: 32 + resetValue: 252645135 + fields: + - name: SAR2_PATT_TAB2 + description: Item 4 ~ 7 for pattern table 2 (each item one byte) + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SAR2_PATT_TAB3 + description: Item 8 ~ 11 for pattern table 2 (each item one byte) + addressOffset: 48 + size: 32 + resetValue: 252645135 + fields: + - name: SAR2_PATT_TAB3 + description: Item 8 ~ 11 for pattern table 2 (each item one byte) + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SAR2_PATT_TAB4 + description: Item 12 ~ 15 for pattern table 2 (each item one byte) + addressOffset: 52 + size: 32 + resetValue: 252645135 + fields: + - name: SAR2_PATT_TAB4 + description: Item 12 ~ 15 for pattern table 2 (each item one byte) + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ARB_CTRL + description: Configure the settings of DIG ADC2 arbiter + addressOffset: 56 + size: 32 + resetValue: 2304 + fields: + - name: ADC_ARB_APB_FORCE + description: ADC2 arbiter forces to enable DIG ADC2 CTRL. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ADC_ARB_RTC_FORCE + description: ADC2 arbiter forces to enable RTC ADC2 CTRL. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ADC_ARB_WIFI_FORCE + description: ADC2 arbiter forces to enable PWDET/PKDET CTRL. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ADC_ARB_GRANT_FORCE + description: ADC2 arbiter force grant. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: ADC_ARB_APB_PRIORITY + description: Set DIG ADC2 CTRL priority. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: ADC_ARB_RTC_PRIORITY + description: Set RTC ADC2 CTRL priority. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: ADC_ARB_WIFI_PRIORITY + description: Set PWDET/PKDET CTRL priority. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: ADC_ARB_FIX_PRIORITY + description: ADC2 arbiter uses fixed priority. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: FILTER_CTRL + description: Configure the settings of DIG ADC2 filter + addressOffset: 60 + size: 32 + resetValue: 541065216 + fields: + - name: ADC2_FILTER_RESET + description: Reset ADC2 filter. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ADC1_FILTER_RESET + description: Reset ADC1 filter. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ADC2_FILTER_FACTOR + description: Set filter factor for DIG ADC2 CRTL. + bitOffset: 16 + bitWidth: 7 + access: read-write + - name: ADC1_FILTER_FACTOR + description: Set filter factor for DIG ADC1 CRTL. + bitOffset: 23 + bitWidth: 7 + access: read-write + - name: ADC2_FILTER_EN + description: Enable DIG ADC2 CRTL filter. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: ADC1_FILTER_EN + description: Enable DIG ADC1 CRTL filter. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: FILTER_STATUS + description: Data status of DIG ADC2 filter + addressOffset: 64 + size: 32 + fields: + - name: ADC2_FILTER_DATA + description: ADC2 filter data. + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: ADC1_FILTER_DATA + description: ADC1 filter data. + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: THRES_CTRL + description: Configure monitor threshold for DIG ADC2 + addressOffset: 68 + size: 32 + fields: + - name: CLK_EN + description: Clock gate enable. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ADC2_THRES_MODE + description: "1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA < threshold, generate interrupt." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ADC1_THRES_MODE + description: "1: ADC_DATA > = threshold, generate interrupt. 0: ADC_DATA < threshold, generate interrupt." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ADC2_THRES + description: ADC2 threshold. + bitOffset: 4 + bitWidth: 13 + access: read-write + - name: ADC1_THRES + description: ADC1 threshold. + bitOffset: 17 + bitWidth: 13 + access: read-write + - name: ADC2_THRES_EN + description: Enable ADC2 threshold monitor. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: ADC1_THRES_EN + description: Enable ADC1 threshold monitor. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_ENA + description: Enable DIG ADC interrupts + addressOffset: 72 + size: 32 + fields: + - name: ADC2_THRES_INT_ENA + description: Enable bit of APB_SARADC_ADC2_THRES_INT interrupt. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: ADC1_THRES_INT_ENA + description: Enable bit of APB_SARADC_ADC1_THRES_INT interrupt. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ADC2_DONE_INT_ENA + description: Enable bit of APB_SARADC_ADC2_DONE_INT interrupt. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: ADC1_DONE_INT_ENA + description: Enable bit of APB_SARADC_ADC1_DONE_INT interrupt. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: DIG ADC interrupt raw bits + addressOffset: 76 + size: 32 + fields: + - name: ADC2_THRES_INT_RAW + description: Raw bit of APB_SARADC_ADC2_THRES_INT interrupt. + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: ADC1_THRES_INT_RAW + description: Raw bit of APB_SARADC_ADC1_THRES_INT interrupt. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: ADC2_DONE_INT_RAW + description: Raw bit of APB_SARADC_ADC2_DONE_INT interrupt. + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: ADC1_DONE_INT_RAW + description: Raw bit of APB_SARADC_ADC1_DONE_INT interrupt. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: DIG ADC interrupt status + addressOffset: 80 + size: 32 + fields: + - name: ADC2_THRES_INT_ST + description: Status of APB_SARADC_ADC2_THRES_INT interrupt. + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: ADC1_THRES_INT_ST + description: Status of APB_SARADC_ADC1_THRES_INT interrupt. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: ADC2_DONE_INT_ST + description: Status of APB_SARADC_ADC2_DONE_INT interrupt. + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: ADC1_DONE_INT_ST + description: Status of APB_SARADC_ADC1_DONE_INT interrupt. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: Clear DIG ADC interrupts + addressOffset: 84 + size: 32 + fields: + - name: ADC2_THRES_INT_CLR + description: Clear bit of APB_SARADC_ADC2_THRES_INT interrupt. + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: ADC1_THRES_INT_CLR + description: Clear bit of APB_SARADC_ADC1_THRES_INT interrupt. + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: ADC2_DONE_INT_CLR + description: Clear bit of APB_SARADC_ADC2_DONE_INT interrupt. + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: ADC1_DONE_INT_CLR + description: Clear bit of APB_SARADC_ADC1_DONE_INT interrupt. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: DMA_CONF + description: Configure digital ADC DMA path + addressOffset: 88 + size: 32 + resetValue: 255 + fields: + - name: APB_ADC_EOF_NUM + description: Generate dma_in_suc_eof when sample cnt = spi_eof_num. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: APB_ADC_RESET_FSM + description: Reset DIG ADC CTRL status. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: APB_ADC_TRANS + description: "Set this bit, DIG ADC CTRL uses SPI DMA." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CLKM_CONF + description: Configure DIG ADC clock + addressOffset: 92 + size: 32 + resetValue: 4 + fields: + - name: CLKM_DIV_NUM + description: Integral DIG_ADC clock divider value + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CLKM_DIV_B + description: Fractional clock divider numerator value + bitOffset: 8 + bitWidth: 6 + access: read-write + - name: CLKM_DIV_A + description: Fractional clock divider denominator value + bitOffset: 14 + bitWidth: 6 + access: read-write + - name: CLK_SEL + description: "1: select APLL. 2: select APB_CLK. Other values: disable clock." + bitOffset: 21 + bitWidth: 2 + access: read-write + - register: + name: APB_DAC_CTRL + description: Configure DAC settings + addressOffset: 96 + size: 32 + resetValue: 8292 + fields: + - name: DAC_TIMER_TARGET + description: Set DAC timer target. + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: DAC_TIMER_EN + description: Enable read dac data. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: APB_DAC_ALTER_MODE + description: Enable DAC alter mode. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: APB_DAC_TRANS + description: Enable DMA_DAC. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DAC_RESET_FIFO + description: Reset DIG DAC FIFO. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: APB_DAC_RST + description: Reset DIG DAC by software. + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: APB_CTRL_DATE + description: Version control register + addressOffset: 1020 + size: 32 + resetValue: 26243426 + fields: + - name: APB_CTRL_DATE + description: Version control register + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: BB + description: BB Peripheral + groupName: BB + baseAddress: 1061277696 + addressBlock: + - offset: 0 + size: 4 + usage: registers + registers: + - register: + name: BBPD_CTRL + description: Baseband control register + addressOffset: 84 + size: 32 + fields: + - name: DC_EST_FORCE_PD + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DC_EST_FORCE_PU + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FFT_FORCE_PD + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FFT_FORCE_PU + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DEDICATED_GPIO + description: DEDICATED_GPIO Peripheral + groupName: DEDIC_GPIO + baseAddress: 1062006784 + addressBlock: + - offset: 0 + size: 48 + usage: registers + interrupt: + - name: DEDICATED_GPIO + value: 27 + registers: + - register: + name: OUT_DRT + description: Dedicated GPIO directive output register + addressOffset: 0 + size: 32 + fields: + - name: VLAUE + description: This register is used to configure directive output value of 8-channel dedicated GPIO. + bitOffset: 0 + bitWidth: 8 + access: write-only + - register: + name: OUT_MSK + description: Dedicated GPIO mask output register + addressOffset: 4 + size: 32 + fields: + - name: OUT_VALUE + description: This register is used to configure updated output value of 8-channel dedicated GPIO. + bitOffset: 0 + bitWidth: 8 + access: write-only + - name: OUT_MSK + description: "This register is used to configure channels which would be updated. 1: corresponding channel's output would be updated." + bitOffset: 8 + bitWidth: 8 + access: write-only + - register: + name: OUT_IDV + description: Dedicated GPIO individual output register + addressOffset: 8 + size: 32 + fields: + - name: CH0 + description: "Configure channel 0 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value." + bitOffset: 0 + bitWidth: 2 + access: write-only + - name: CH1 + description: "Configure channel 1 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value." + bitOffset: 2 + bitWidth: 2 + access: write-only + - name: CH2 + description: "Configure channel 2 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value." + bitOffset: 4 + bitWidth: 2 + access: write-only + - name: CH3 + description: "Configure channel 3 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value." + bitOffset: 6 + bitWidth: 2 + access: write-only + - name: CH4 + description: "Configure channel 4 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value." + bitOffset: 8 + bitWidth: 2 + access: write-only + - name: CH5 + description: "Configure channel 5 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value." + bitOffset: 10 + bitWidth: 2 + access: write-only + - name: CH6 + description: "Configure channel 6 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value." + bitOffset: 12 + bitWidth: 2 + access: write-only + - name: CH7 + description: "Configure channel 7 output value. 0: hold output value. 1: set output value. 2: clear output value. 3: inverse output value." + bitOffset: 14 + bitWidth: 2 + access: write-only + - register: + name: OUT_SCAN + description: Dedicated GPIO output status register + addressOffset: 12 + size: 32 + fields: + - name: OUT_STATUS + description: "GPIO out value configured by DEDIC_GPIO_OUT_DRT_REG, DEDIC_GPIO_OUT_MSK_REG, DEDIC_GPIO_OUT_IDV_REG." + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: OUT_CPU + description: Dedicated GPIO output mode selection register + addressOffset: 16 + size: 32 + fields: + - name: SEL0 + description: "Select GPIO out value configured by registers or CPU instructions for channel 0. 0: Configured by registers. 1: configured by CPU instructions." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SEL1 + description: "Select GPIO out value configured by registers or CPU instructions for channel 1. 0: Configured by registers. 1: configured by CPU instructions." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SEL2 + description: "Select GPIO out value configured by registers or CPU instructions for channel 2. 0: Configured by registers. 1: configured by CPU instructions." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SEL3 + description: "Select GPIO out value configured by registers or CPU instructions for channel 3. 0: Configured by registers. 1: configured by CPU instructions." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SEL4 + description: "Select GPIO out value configured by registers or CPU instructions for channel 4. 0: Configured by registers. 1: configured by CPU instructions." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SEL5 + description: "Select GPIO out value configured by registers or CPU instructions for channel 5. 0: Configured by registers. 1: configured by CPU instructions." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SEL6 + description: "Select GPIO out value configured by registers or CPU instructions for channel 6. 0: Configured by registers. 1: configured by CPU instructions." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SEL7 + description: "Select GPIO out value configured by registers or CPU instructions for channel 7. 0: Configured by registers. 1: configured by CPU instructions." + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: IN_DLY + description: Dedicated GPIO input delay configuration register + addressOffset: 20 + size: 32 + fields: + - name: CH0 + description: "Configure GPIO0 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CH1 + description: "Configure GPIO1 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CH2 + description: "Configure GPIO2 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CH3 + description: "Configure GPIO3 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CH4 + description: "Configure GPIO4 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay." + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CH5 + description: "Configure GPIO5 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CH6 + description: "Configure GPIO6 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay." + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CH7 + description: "Configure GPIO7 input delay. 0: no delay. 1: one clock delay. 2: two clock delay. 3: three clock delay." + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: IN_SCAN + description: Dedicated GPIO input status register + addressOffset: 24 + size: 32 + fields: + - name: IN_STATUS + description: GPIO input value after configured by DEDIC_GPIO_IN_DLY_REG. + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: INTR_RCGN + description: Dedicated GPIO interrupts generation mode register + addressOffset: 28 + size: 32 + fields: + - name: INTR_MODE_CH0 + description: "Configure channel 0 interrupt generate mode. \n0/1: do not generate interrupt. \n2: low level trigger.\n3: high level trigger. \n4: falling edge trigger. \n5: raising edge trigger. \n6/7: falling and raising edge trigger." + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: INTR_MODE_CH1 + description: "Configure channel 1 interrupt generate mode. \n0/1: do not generate interrupt. \n2: low level trigger.\n3: high level trigger. \n4: falling edge trigger. \n5: raising edge trigger. \n6/7: falling and raising edge trigger." + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: INTR_MODE_CH2 + description: "Configure channel 2 interrupt generate mode. \n0/1: do not generate interrupt. \n2: low level trigger.\n3: high level trigger. \n4: falling edge trigger. \n5: raising edge trigger. \n6/7: falling and raising edge trigger." + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: INTR_MODE_CH3 + description: "Configure channel 3 interrupt generate mode. \n0/1: do not generate interrupt. \n2: low level trigger.\n3: high level trigger. \n4: falling edge trigger. \n5: raising edge trigger. \n6/7: falling and raising edge trigger." + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: INTR_MODE_CH4 + description: "Configure channel 4 interrupt generate mode. \n0/1: do not generate interrupt. \n2: low level trigger.\n3: high level trigger. \n4: falling edge trigger. \n5: raising edge trigger. \n6/7: falling and raising edge trigger." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: INTR_MODE_CH5 + description: "Configure channel 5 interrupt generate mode. \n0/1: do not generate interrupt. \n2: low level trigger.\n3: high level trigger. \n4: falling edge trigger. \n5: raising edge trigger. \n6/7: falling and raising edge trigger." + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: INTR_MODE_CH6 + description: "Configure channel 6 interrupt generate mode. \n0/1: do not generate interrupt. \n2: low level trigger.\n3: high level trigger. \n4: falling edge trigger. \n5: raising edge trigger. \n6/7: falling and raising edge trigger." + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: INTR_MODE_CH7 + description: "Configure channel 7 interrupt generate mode. \n0/1: do not generate interrupt. \n2: low level trigger.\n3: high level trigger. \n4: falling edge trigger. \n5: raising edge trigger. \n6/7: falling and raising edge trigger." + bitOffset: 21 + bitWidth: 3 + access: read-write + - register: + name: INTR_RAW + description: Raw interrupt status + addressOffset: 32 + size: 32 + fields: + - name: GPIO0 + description: This interrupt raw bit turns to high level when dedicated GPIO0 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: GPIO1 + description: This interrupt raw bit turns to high level when dedicated GPIO1 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: GPIO2 + description: This interrupt raw bit turns to high level when dedicated GPIO2 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: GPIO3 + description: This interrupt raw bit turns to high level when dedicated GPIO3 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: GPIO4 + description: This interrupt raw bit turns to high level when dedicated GPIO4 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: GPIO5 + description: This interrupt raw bit turns to high level when dedicated GPIO5 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: GPIO6 + description: This interrupt raw bit turns to high level when dedicated GPIO6 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: GPIO7 + description: This interrupt raw bit turns to high level when dedicated GPIO7 has level/edge change configured by DEDIC_GPIO_INTR_RCGN_REG. + bitOffset: 7 + bitWidth: 1 + access: read-only + - register: + name: INTR_RLS + description: Interrupt enable bits + addressOffset: 36 + size: 32 + fields: + - name: GPIO0_INT_ENA + description: The enable bit for DEDIC_GPIO0_INT_ST register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: GPIO1_INT_ENA + description: The enable bit for DEDIC_GPIO1_INT_ST register. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: GPIO2_INT_ENA + description: The enable bit for DEDIC_GPIO2_INT_ST register. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: GPIO3_INT_ENA + description: The enable bit for DEDIC_GPIO3_INT_ST register. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: GPIO4_INT_ENA + description: The enable bit for DEDIC_GPIO4_INT_ST register. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: GPIO5_INT_ENA + description: The enable bit for DEDIC_GPIO5_INT_ST register. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: GPIO6_INT_ENA + description: The enable bit for DEDIC_GPIO6_INT_ST register. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: GPIO7_INT_ENA + description: The enable bit for DEDIC_GPIO7_INT_ST register. + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: INTR_ST + description: Masked interrupt status + addressOffset: 40 + size: 32 + fields: + - name: GPIO0_INT_ST + description: This is the status bit for DEDIC_GPIO0_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: GPIO1_INT_ST + description: This is the status bit for DEDIC_GPIO1_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: GPIO2_INT_ST + description: This is the status bit for DEDIC_GPIO2_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: GPIO3_INT_ST + description: This is the status bit for DEDIC_GPIO3_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: GPIO4_INT_ST + description: This is the status bit for DEDIC_GPIO4_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: GPIO5_INT_ST + description: This is the status bit for DEDIC_GPIO5_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: GPIO6_INT_ST + description: This is the status bit for DEDIC_GPIO6_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: GPIO7_INT_ST + description: This is the status bit for DEDIC_GPIO7_INT_RAW when DEDIC_GPIO7_INT_ENA is set to 1. + bitOffset: 7 + bitWidth: 1 + access: read-only + - register: + name: INTR_CLR + description: Interrupt clear bits + addressOffset: 44 + size: 32 + fields: + - name: GPIO0_INT_CLR + description: Set this bit to clear the DEDIC_GPIO0_INT_RAW interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: GPIO1_INT_CLR + description: Set this bit to clear the DEDIC_GPIO1_INT_RAW interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: GPIO2_INT_CLR + description: Set this bit to clear the DEDIC_GPIO2_INT_RAW interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: GPIO3_INT_CLR + description: Set this bit to clear the DEDIC_GPIO3_INT_RAW interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: GPIO4_INT_CLR + description: Set this bit to clear the DEDIC_GPIO4_INT_RAW interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: GPIO5_INT_CLR + description: Set this bit to clear the DEDIC_GPIO5_INT_RAW interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: GPIO6_INT_CLR + description: Set this bit to clear the DEDIC_GPIO6_INT_RAW interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: GPIO7_INT_CLR + description: Set this bit to clear the DEDIC_GPIO7_INT_RAW interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: DS + description: Digital Signature + groupName: DS + baseAddress: 1610862592 + addressBlock: + - offset: 0 + size: 2652 + usage: registers + registers: + - register: + dim: 396 + dimIncrement: 4 + name: "C_MEM[%s]" + description: memory C + addressOffset: 0 + size: 32 + - register: + dim: 4 + dimIncrement: 4 + name: IV_%s + description: IV block data. + addressOffset: 1584 + size: 32 + fields: + - name: IV + description: IV block data. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + dim: 128 + dimIncrement: 4 + name: "X_MEM[%s]" + description: memory X + addressOffset: 2048 + size: 32 + - register: + dim: 128 + dimIncrement: 4 + name: "Z_MEM[%s]" + description: memory Z + addressOffset: 2560 + size: 32 + - register: + name: SET_START + description: Activates the DS peripheral + addressOffset: 3584 + size: 32 + fields: + - name: SET_START + description: Write 1 to this register to activate the DS peripheral. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_ME + description: Starts DS operation + addressOffset: 3588 + size: 32 + fields: + - name: SET_ME + description: Write 1 to this register to start DS operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_FINISH + description: Ends DS operation + addressOffset: 3592 + size: 32 + fields: + - name: SET_FINISH + description: Write 1 to this register to end DS operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: QUERY_BUSY + description: Status of the DS + addressOffset: 3596 + size: 32 + fields: + - name: QUERY_BUSY + description: "1: The DS peripheral is busy. 0: The DS peripheral is idle." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: QUERY_KEY_WRONG + description: Checks the reason why DS_KEY is not ready. + addressOffset: 3600 + size: 32 + fields: + - name: QUERY_KEY_WRONG + description: "1-15: HMAC was activated, but the DS peripheral did not successfully receive the DS_KEY value from the HMAC peripheral. The biggest value is 15. 0: HMAC is not activated." + bitOffset: 0 + bitWidth: 4 + access: read-only + - register: + name: QUERY_CHECK + description: Queries DS check result + addressOffset: 3604 + size: 32 + fields: + - name: MD_ERROR + description: "1: MD check fails. 0: MD check passes." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PADDING_BAD + description: "1: The padding check fails. 0: The padding check passes." + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: Version control register + addressOffset: 3616 + size: 32 + resetValue: 538510360 + fields: + - name: DATE + description: Version control register. + bitOffset: 0 + bitWidth: 30 + access: read-write + - name: EFUSE + description: eFuse Controller + groupName: EFUSE + baseAddress: 1061265408 + addressBlock: + - offset: 0 + size: 464 + usage: registers + interrupt: + - name: EFUSE + value: 46 + registers: + - register: + dim: 8 + dimIncrement: 4 + name: PGM_DATA%s + description: Register %s that stores data to be programmed. + addressOffset: 0 + size: 32 + fields: + - name: PGM_DATA + description: The content of the %sth 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 3 + dimIncrement: 4 + name: PGM_CHECK_VALUE%s + description: Register %s that stores the RS code to be programmed. + addressOffset: 32 + size: 32 + fields: + - name: PGM_RS_DATA + description: The content of the %sth 32-bit RS code to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RD_WR_DIS + description: Register 0 of BLOCK0. + addressOffset: 44 + size: 32 + fields: + - name: WR_DIS + description: Disables programming of individual eFuses. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_REPEAT_DATA0 + description: Register 1 of BLOCK0. + addressOffset: 48 + size: 32 + fields: + - name: RD_DIS + description: Disables software reading from individual eFuse blocks (BLOCK4-10). + bitOffset: 0 + bitWidth: 7 + access: read-only + - name: DIS_RTC_RAM_BOOT + description: Reserved. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DIS_ICACHE + description: Set this bit to disable Icache. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DIS_DCACHE + description: Set this bit to disable Dcache. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_ICACHE + description: Disables Icache when SoC is in Download mode. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_DCACHE + description: Disables Dcache when SoC is in Download mode. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: DIS_FORCE_DOWNLOAD + description: Set this bit to disable the function that forces chip into download mode. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: DIS_USB + description: Set this bit to disable USB OTG function. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: DIS_CAN + description: Set this bit to disable the TWAI Controller function. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DIS_BOOT_REMAP + description: Disables capability to Remap RAM to ROM address space. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED5 + description: Reserved (used for four backups method). + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: SOFT_DIS_JTAG + description: "Software disables JTAG. When software disabled, JTAG can be activated temporarily by HMAC peripheral." + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: HARD_DIS_JTAG + description: Hardware disables JTAG permanently. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_MANUAL_ENCRYPT + description: Disables flash encryption when in download boot modes. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: USB_DREFH + description: "Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse." + bitOffset: 20 + bitWidth: 2 + access: read-only + - name: USB_DREFL + description: "Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse." + bitOffset: 22 + bitWidth: 2 + access: read-only + - name: USB_EXCHG_PINS + description: Set this bit to exchange USB D+ and D- pins. + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: EXT_PHY_ENABLE + description: Set this bit to enable external USB PHY. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: USB_FORCE_NOPERSIST + description: "If set, forces USB BVALID to 1." + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED0 + description: Reserved (used for four backups method). + bitOffset: 27 + bitWidth: 2 + access: read-only + - name: VDD_SPI_MODECURLIM + description: SPI regulator switches current limit mode. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: VDD_SPI_DREFH + description: SPI regulator high voltage reference. + bitOffset: 30 + bitWidth: 2 + access: read-only + - register: + name: RD_REPEAT_DATA1 + description: Register 2 of BLOCK0. + addressOffset: 52 + size: 32 + fields: + - name: VDD_SPI_DREFM + description: SPI regulator medium voltage reference. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: VDD_SPI_DREFL + description: SPI regulator low voltage reference. + bitOffset: 2 + bitWidth: 2 + access: read-only + - name: VDD_SPI_XPD + description: "If VDD_SPI_FORCE is 1, this value determines if the VDD_SPI regulator is powered on." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: VDD_SPI_TIEH + description: "If VDD_SPI_FORCE is 1, determines VDD_SPI voltage. 0: VDD_SPI connects to 1.8 V LDO. 1: VDD_SPI connects to VDD_RTC_IO." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: VDD_SPI_FORCE + description: Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI LDO. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: VDD_SPI_EN_INIT + description: "Set SPI regulator to 0 to configure init[1:0]=0." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: VDD_SPI_ENCURLIM + description: Set SPI regulator to 1 to enable output current limit. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: VDD_SPI_DCURLIM + description: "Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d)." + bitOffset: 9 + bitWidth: 3 + access: read-only + - name: VDD_SPI_INIT + description: "Adds resistor from LDO output to ground. 0: no resistance. 1: 6 K. 2: 4 K. 3: 2 K." + bitOffset: 12 + bitWidth: 2 + access: read-only + - name: VDD_SPI_DCAP + description: Prevents SPI regulator from overshoot. + bitOffset: 14 + bitWidth: 2 + access: read-only + - name: WDT_DELAY_SEL + description: "Selects RTC watchdog timeout threshold at startup. 0: 40,000 slow clock cycles. 1: 80,000 slow clock cycles. 2: 160,000 slow clock cycles. 3: 320,000 slow clock cycles." + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: SPI_BOOT_CRYPT_CNT + description: "Enables encryption and decryption, when an SPI boot mode is set. Feature is enabled 1 or 3 bits are set in the eFuse, disabled otherwise." + bitOffset: 18 + bitWidth: 3 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE0 + description: "If set, revokes use of secure boot key digest 0." + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE1 + description: "If set, revokes use of secure boot key digest 1." + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE2 + description: "If set, revokes use of secure boot key digest 2." + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: KEY_PURPOSE_0 + description: Purpose of KEY0. Refer to Table Key Purpose Values. + bitOffset: 24 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_1 + description: Purpose of KEY1. Refer to Table Key Purpose Values. + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_REPEAT_DATA2 + description: Register 3 of BLOCK0. + addressOffset: 56 + size: 32 + fields: + - name: KEY_PURPOSE_2 + description: Purpose of KEY2. Refer to Table Key Purpose Values. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_3 + description: Purpose of KEY3. Refer to Table Key Purpose Values. + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_4 + description: Purpose of KEY4. Refer to Table Key Purpose Values. + bitOffset: 8 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_5 + description: Purpose of KEY5. Refer to Table Key Purpose Values. + bitOffset: 12 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_6 + description: Purpose of KEY6. Refer to Table Key Purpose Values. + bitOffset: 16 + bitWidth: 4 + access: read-only + - name: SECURE_BOOT_EN + description: Set this bit to enable secure boot. + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_AGGRESSIVE_REVOKE + description: Set this bit to enable aggressive secure boot key revocation mode. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED1 + description: Reserved (used for four backups method). + bitOffset: 22 + bitWidth: 6 + access: read-only + - name: FLASH_TPUW + description: "Configures flash startup delay after SoC power-up, in unit of (ms/2). When the value is 15, delay is 7.5 ms." + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_REPEAT_DATA3 + description: Register 4 of BLOCK0. + addressOffset: 60 + size: 32 + fields: + - name: DIS_DOWNLOAD_MODE + description: Set this bit to disable all download boot modes. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DIS_LEGACY_SPI_BOOT + description: Set this bit to disable Legacy SPI boot mode. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: UART_PRINT_CHANNEL + description: "Selects the default UART for printing boot messages. 0: UART0. 1: UART1." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED3 + description: Reserved (used for four backups method). + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DIS_USB_DOWNLOAD_MODE + description: Set this bit to disable use of USB OTG in UART download boot mode. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ENABLE_SECURITY_DOWNLOAD + description: Set this bit to enable secure UART download mode (read/write flash only). + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: UART_PRINT_CONTROL + description: "Set the default UART boot message output mode. 00: Enabled. 01: Enable when GPIO46 is low at reset. 10: Enable when GPIO46 is high at reset. 11: Disabled." + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: PIN_POWER_SELECTION + description: "Set default power supply for GPIO33-GPIO37, set when SPI flash is initialized. 0: VDD3P3_CPU. 1: VDD_SPI." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: FLASH_TYPE + description: "SPI flash type. 0: maximum four data lines, 1: eight data lines." + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: FORCE_SEND_RESUME + description: "If set, forces ROM code to send an SPI flash resume command during SPI boot." + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SECURE_VERSION + description: Secure version (used by ESP-IDF anti-rollback feature). + bitOffset: 11 + bitWidth: 16 + access: read-only + - name: RPT4_RESERVED2 + description: Reserved (used for four backups method). + bitOffset: 27 + bitWidth: 5 + access: read-only + - register: + name: RD_REPEAT_DATA4 + description: Register 5 of BLOCK0. + addressOffset: 64 + size: 32 + fields: + - name: RPT4_RESERVED4 + description: Reserved (used for four backups method). + bitOffset: 0 + bitWidth: 24 + access: read-only + - register: + name: RD_MAC_SPI_SYS_0 + description: Register 0 of BLOCK1. + addressOffset: 68 + size: 32 + fields: + - name: MAC_0 + description: Stores the low 32 bits of MAC address. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_MAC_SPI_SYS_1 + description: Register 1 of BLOCK1. + addressOffset: 72 + size: 32 + fields: + - name: MAC_1 + description: Stores the high 16 bits of MAC address. + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: SPI_PAD_CONF_0 + description: Stores the zeroth part of SPI_PAD_CONF. + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: RD_MAC_SPI_SYS_2 + description: Register 2 of BLOCK1. + addressOffset: 76 + size: 32 + fields: + - name: SPI_PAD_CONF_1 + description: Stores the first part of SPI_PAD_CONF. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_MAC_SPI_SYS_3 + description: Register 3 of BLOCK1. + addressOffset: 80 + size: 32 + fields: + - name: SPI_PAD_CONF_2 + description: Stores the second part of SPI_PAD_CONF. + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: SYS_DATA_PART0_0 + description: Stores the zeroth part of the zeroth part of system data. + bitOffset: 18 + bitWidth: 14 + access: read-only + - register: + name: RD_MAC_SPI_SYS_4 + description: Register 4 of BLOCK1. + addressOffset: 84 + size: 32 + fields: + - name: SYS_DATA_PART0_1 + description: Stores the fist part of the zeroth part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_MAC_SPI_SYS_5 + description: Register 5 of BLOCK1. + addressOffset: 88 + size: 32 + fields: + - name: SYS_DATA_PART0_2 + description: Stores the second part of the zeroth part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + dim: 8 + dimIncrement: 4 + name: RD_SYS_DATA_PART1_%s + description: Register %s of BLOCK2 (system). + addressOffset: 92 + size: 32 + fields: + - name: SYS_DATA_PART1 + description: Stores the %sth 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + dim: 8 + dimIncrement: 4 + name: RD_USR_DATA%s + description: Register %s of BLOCK3 (user). + addressOffset: 124 + size: 32 + fields: + - name: USR_DATA + description: Stores the %sth 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + dim: 8 + dimIncrement: 4 + name: RD_KEY0_DATA%s + description: Register %s of BLOCK4 (KEY0). + addressOffset: 156 + size: 32 + fields: + - name: KEY0_DATA + description: Stores the %sth 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + dim: 8 + dimIncrement: 4 + name: RD_KEY1_DATA%s + description: Register %s of BLOCK5 (KEY1). + addressOffset: 188 + size: 32 + fields: + - name: KEY1_DATA + description: Stores the %sth 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + dim: 8 + dimIncrement: 4 + name: RD_KEY2_DATA%s + description: Register %s of BLOCK6 (KEY2). + addressOffset: 220 + size: 32 + fields: + - name: KEY2_DATA + description: Stores the %sth 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + dim: 8 + dimIncrement: 4 + name: RD_KEY3_DATA%s + description: Register %s of BLOCK7 (KEY3). + addressOffset: 252 + size: 32 + fields: + - name: KEY3_DATA + description: Stores the %sth 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + dim: 8 + dimIncrement: 4 + name: RD_KEY4_DATA%s + description: Register %s of BLOCK8 (KEY4). + addressOffset: 284 + size: 32 + fields: + - name: KEY4_DATA + description: Stores the %sth 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + dim: 8 + dimIncrement: 4 + name: RD_KEY5_DATA%s + description: Register %s of BLOCK9 (KEY5). + addressOffset: 316 + size: 32 + fields: + - name: KEY5_DATA + description: Stores the %sth 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + dim: 8 + dimIncrement: 4 + name: RD_SYS_DATA_PART2_%s + description: Register %s of BLOCK10 (system). + addressOffset: 348 + size: 32 + fields: + - name: SYS_DATA_PART2 + description: Stores the %sth 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_REPEAT_ERR0 + description: Programming error record register 0 of BLOCK0. + addressOffset: 380 + size: 32 + fields: + - name: RD_DIS_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_RD_DIS. + bitOffset: 0 + bitWidth: 7 + access: read-only + - name: DIS_RTC_RAM_BOOT_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_DIS_RTC_RAM_BOOT. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DIS_ICACHE_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_DIS_ICACHE. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DIS_DCACHE_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_DIS_DCACHE. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_ICACHE_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_ICACHE. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_DCACHE_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_DCACHE. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: DIS_FORCE_DOWNLOAD_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_DIS_FORCE_DOWNLOAD. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: DIS_USB_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_DIS_USB. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: DIS_CAN_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_DIS_CAN. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DIS_BOOT_REMAP_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_DIS_BOOT_REMAP. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED5_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED5. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: SOFT_DIS_JTAG_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_SOFT_DIS_JTAG. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: HARD_DIS_JTAG_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_HARD_DIS_JTAG. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: USB_DREFH_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_USB_DREFH. + bitOffset: 20 + bitWidth: 2 + access: read-only + - name: USB_DREFL_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_USB_DREFL. + bitOffset: 22 + bitWidth: 2 + access: read-only + - name: USB_EXCHG_PINS_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_USB_EXCHG_PINS. + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: EXT_PHY_ENABLE_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_EXT_PHY_ENABLE. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: USB_FORCE_NOPERSIST_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_USB_FORCE_NOPERSIST. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED0_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED0. + bitOffset: 27 + bitWidth: 2 + access: read-only + - name: VDD_SPI_MODECURLIM_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_MODECURLIM. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: VDD_SPI_DREFH_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFH. + bitOffset: 30 + bitWidth: 2 + access: read-only + - register: + name: RD_REPEAT_ERR1 + description: Programming error record register 1 of BLOCK0. + addressOffset: 384 + size: 32 + fields: + - name: VDD_SPI_DREFM_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFM. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: VDD_SPI_DREFL_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFL. + bitOffset: 2 + bitWidth: 2 + access: read-only + - name: VDD_SPI_XPD_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_XPD. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: VDD_SPI_TIEH_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_TIEH. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: VDD_SPI_FORCE_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_FORCE. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: VDD_SPI_EN_INIT_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_EN_INIT. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: VDD_SPI_ENCURLIM_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_ENCURLIM. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: VDD_SPI_DCURLIM_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DCURLIM. + bitOffset: 9 + bitWidth: 3 + access: read-only + - name: VDD_SPI_INIT_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_INIT. + bitOffset: 12 + bitWidth: 2 + access: read-only + - name: VDD_SPI_DCAP_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DCAP. + bitOffset: 14 + bitWidth: 2 + access: read-only + - name: WDT_DELAY_SEL_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_WDT_DELAY_SEL. + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: SPI_BOOT_CRYPT_CNT_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_SPI_BOOT_CRYPT_CNT. + bitOffset: 18 + bitWidth: 3 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE0_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE0. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE1_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE1. + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE2_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE2. + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: KEY_PURPOSE_0_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_0. + bitOffset: 24 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_1_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_1. + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_REPEAT_ERR2 + description: Programming error record register 2 of BLOCK0. + addressOffset: 388 + size: 32 + fields: + - name: KEY_PURPOSE_2_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_2. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_3_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_3. + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_4_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_4. + bitOffset: 8 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_5_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_5. + bitOffset: 12 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_6_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_6. + bitOffset: 16 + bitWidth: 4 + access: read-only + - name: SECURE_BOOT_EN_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_EN. + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_AGGRESSIVE_REVOKE_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED1_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED1. + bitOffset: 22 + bitWidth: 6 + access: read-only + - name: FLASH_TPUW_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_FLASH_TPUW. + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_REPEAT_ERR3 + description: Programming error record register 3 of BLOCK0. + addressOffset: 392 + size: 32 + fields: + - name: DIS_DOWNLOAD_MODE_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_MODE. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DIS_LEGACY_SPI_BOOT_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_DIS_LEGACY_SPI_BOOT. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: UART_PRINT_CHANNEL_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_UART_PRINT_CHANNEL. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED3_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED3. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DIS_USB_DOWNLOAD_MODE_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_DIS_USB_DOWNLOAD_MODE. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ENABLE_SECURITY_DOWNLOAD_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_ENABLE_SECURITY_DOWNLOAD. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: UART_PRINT_CONTROL_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_UART_PRINT_CONTROL. + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: PIN_POWER_SELECTION_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_PIN_POWER_SELECTION. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: FLASH_TYPE_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_FLASH_TYPE. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: FORCE_SEND_RESUME_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_FORCE_SEND_RESUME. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SECURE_VERSION_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_SECURE_VERSION. + bitOffset: 11 + bitWidth: 16 + access: read-only + - name: RPT4_RESERVED2_ERR + description: Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED2. + bitOffset: 27 + bitWidth: 5 + access: read-only + - register: + name: RD_REPEAT_ERR4 + description: Programming error record register 4 of BLOCK0. + addressOffset: 400 + size: 32 + fields: + - name: RPT4_RESERVED4_ERR + description: "If any bit in RPT4_RESERVED4 is 1, there is a programming error in EFUSE_RPT4_RESERVED4." + bitOffset: 0 + bitWidth: 24 + access: read-only + - register: + name: RD_RS_ERR0 + description: Programming error record register 0 of BLOCK1-10. + addressOffset: 448 + size: 32 + fields: + - name: MAC_SPI_8M_ERR_NUM + description: The value of this signal means the number of error bytes in BLOCK1. + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: MAC_SPI_8M_FAIL + description: "0: Means no failure and that the data of BLOCK1 is reliable. 1: Means that programming BLOCK1 data failed and the number of error bytes is over 5." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SYS_PART1_NUM + description: The value of this signal means the number of error bytes in BLOCK2. + bitOffset: 4 + bitWidth: 3 + access: read-only + - name: SYS_PART1_FAIL + description: "0: Means no failure and that the data of BLOCK2 is reliable. 1: Means that programming BLOCK2 data failed and the number of error bytes is over 5." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: USR_DATA_ERR_NUM + description: The value of this signal means the number of error bytes in BLOCK3. + bitOffset: 8 + bitWidth: 3 + access: read-only + - name: USR_DATA_FAIL + description: "0: Means no failure and that the data of BLOCK3 is reliable. 1: Means that programming BLOCK3 data failed and the number of error bytes is over 5." + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: KEY0_ERR_NUM + description: The value of this signal means the number of error bytes in KEY0. + bitOffset: 12 + bitWidth: 3 + access: read-only + - name: KEY0_FAIL + description: "0: Means no failure and that the data of KEY0 is reliable. 1: Means that programming KEY0 failed and the number of error bytes is over 5." + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: KEY1_ERR_NUM + description: The value of this signal means the number of error bytes in KEY1. + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: KEY1_FAIL + description: "0: Means no failure and that the data of KEY1 is reliable. 1: Means that programming KEY1 failed and the number of error bytes is over 5." + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: KEY2_ERR_NUM + description: The value of this signal means the number of error bytes in KEY2. + bitOffset: 20 + bitWidth: 3 + access: read-only + - name: KEY2_FAIL + description: "0: Means no failure and that the data of KEY2 is reliable. 1: Means that programming KEY2 failed and the number of error bytes is over 5." + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: KEY3_ERR_NUM + description: The value of this signal means the number of error bytes in KEY3. + bitOffset: 24 + bitWidth: 3 + access: read-only + - name: KEY3_FAIL + description: "0: Means no failure and that the data of KEY3 is reliable. 1: Means that programming KEY3 failed and the number of error bytes is over 5." + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: KEY4_ERR_NUM + description: The value of this signal means the number of error bytes in KEY4. + bitOffset: 28 + bitWidth: 3 + access: read-only + - name: KEY4_FAIL + description: "0: Means no failure and that the data of KEY4 is reliable. 1: Means that programming KEY4 failed and the number of error bytes is over 5." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: RD_RS_ERR1 + description: Programming error record register 1 of BLOCK1-10. + addressOffset: 452 + size: 32 + fields: + - name: KEY5_ERR_NUM + description: The value of this signal means the number of error bytes in KEY5. + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: KEY5_FAIL + description: "0: Means no failure and that the data of KEY5 is reliable. 1: Means that programming user data failed and the number of error bytes is over 5." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SYS_PART2_ERR_NUM + description: The value of this signal means the number of error bytes in BLOCK10. + bitOffset: 4 + bitWidth: 3 + access: read-only + - name: SYS_PART2_FAIL + description: "0: Means no failure and that the data of BLOCK10 is reliable. 1: Means that programming BLOCK10 data failed and the number of error bytes is over 5." + bitOffset: 7 + bitWidth: 1 + access: read-only + - register: + name: CLK + description: eFuse clock configuration register. + addressOffset: 456 + size: 32 + resetValue: 2 + fields: + - name: EFUSE_MEM_FORCE_PD + description: "If set, forces eFuse SRAM into power-saving mode." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_CLK_FORCE_ON + description: "If set, forces to activate clock signal of eFuse SRAM." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EFUSE_MEM_FORCE_PU + description: "If set, forces eFuse SRAM into working mode." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EN + description: "If set, forces to enable clock signal of eFuse memory." + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: CONF + description: eFuse operation mode configuration register. + addressOffset: 460 + size: 32 + fields: + - name: OP_CODE + description: "0x5A5A: Operate programming command. 0x5AA5: Operate read command." + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: STATUS + description: eFuse status register. + addressOffset: 464 + size: 32 + fields: + - name: STATE + description: Indicates the state of the eFuse state machine. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: OTP_LOAD_SW + description: The value of OTP_LOAD_SW. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: OTP_VDDQ_C_SYNC2 + description: The value of OTP_VDDQ_C_SYNC2. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OTP_STROBE_SW + description: The value of OTP_STROBE_SW. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OTP_CSB_SW + description: The value of OTP_CSB_SW. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OTP_PGENB_SW + description: The value of OTP_PGENB_SW. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: OTP_VDDQ_IS_SW + description: The value of OTP_VDDQ_IS_SW. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: REPEAT_ERR_CNT + description: Indicates the number of error bits during programming BLOCK0. + bitOffset: 10 + bitWidth: 8 + access: read-only + - register: + name: CMD + description: eFuse command register. + addressOffset: 468 + size: 32 + fields: + - name: READ_CMD + description: Set this bit to send read command. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PGM_CMD + description: Set this bit to send programming command. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BLK_NUM + description: "The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively." + bitOffset: 2 + bitWidth: 4 + access: read-write + - register: + name: INT_RAW + description: eFuse raw interrupt register. + addressOffset: 472 + size: 32 + fields: + - name: READ_DONE_INT_RAW + description: The raw bit signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PGM_DONE_INT_RAW + description: The raw bit signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: eFuse interrupt status register. + addressOffset: 476 + size: 32 + fields: + - name: READ_DONE_INT_ST + description: The status signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PGM_DONE_INT_ST + description: The status signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: eFuse interrupt enable register. + addressOffset: 480 + size: 32 + fields: + - name: READ_DONE_INT_ENA + description: The enable signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PGM_DONE_INT_ENA + description: The enable signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: eFuse interrupt clear register. + addressOffset: 484 + size: 32 + fields: + - name: READ_DONE_INT_CLR + description: The clear signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: PGM_DONE_INT_CLR + description: The clear signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: DAC_CONF + description: Controls the eFuse programming voltage. + addressOffset: 488 + size: 32 + resetValue: 130588 + fields: + - name: DAC_CLK_DIV + description: Controls the division factor of the rising clock of the programming voltage. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: DAC_CLK_PAD_SEL + description: "Don't care." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DAC_NUM + description: Controls the rising period of the programming voltage. + bitOffset: 9 + bitWidth: 8 + access: read-write + - name: OE_CLR + description: Reduces the power supply of the programming voltage. + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: RD_TIM_CONF + description: Configures read timing parameters. + addressOffset: 492 + size: 32 + resetValue: 302055681 + fields: + - name: THR_A + description: Configures the hold time of read operation. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TRD + description: Configures the length of pulse of read operation. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: TSUR_A + description: Configures the setup time of read operation. + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: READ_INIT_NUM + description: Configures the initial read time of eFuse. + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: WR_TIM_CONF0 + description: Configuration register 0 of eFuse programming timing parameters. + addressOffset: 496 + size: 32 + resetValue: 13107457 + fields: + - name: THP_A + description: Configures the hold time of programming operation. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TPGM_INACTIVE + description: Configures the length of pulse during programming 0 to eFuse. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: TPGM + description: Configures the length of pulse during programming 1 to eFuse. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: WR_TIM_CONF1 + description: Configuration register 1 of eFuse programming timing parameters. + addressOffset: 500 + size: 32 + resetValue: 2654209 + fields: + - name: TSUP_A + description: Configures the setup time of programming operation. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: PWR_ON_NUM + description: Configures the power up time for VDDQ. + bitOffset: 8 + bitWidth: 16 + access: read-write + - register: + name: WR_TIM_CONF2 + description: Configuration register 2 of eFuse programming timing parameters. + addressOffset: 504 + size: 32 + resetValue: 400 + fields: + - name: PWR_OFF_NUM + description: Configures the power outage time for VDDQ. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: DATE + description: Version control register. + addressOffset: 508 + size: 32 + resetValue: 419959040 + fields: + - name: DATE + description: Version control register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: EXTMEM + description: External Memory + groupName: EXTMEM + baseAddress: 1635778560 + addressBlock: + - offset: 0 + size: 320 + usage: registers + registers: + - register: + name: PRO_DCACHE_CTRL + description: register description + addressOffset: 0 + size: 32 + resetValue: 256 + fields: + - name: PRO_DCACHE_ENABLE + description: "The bit is used to activate the data cache. 0: disable, 1: enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_DCACHE_SETSIZE_MODE + description: "The bit is used to configure cache memory size.0: 8KB, 1: 16KB" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PRO_DCACHE_BLOCKSIZE_MODE + description: "The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PRO_DCACHE_INVALIDATE_ENA + description: The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: PRO_DCACHE_INVALIDATE_DONE + description: The bit is used to indicate invalidate operation is finished. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: PRO_DCACHE_FLUSH_ENA + description: The bit is used to enable flush operation. It will be cleared by hardware after flush operation done. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: PRO_DCACHE_FLUSH_DONE + description: The bit is used to indicate flush operation is finished. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: PRO_DCACHE_CLEAN_ENA + description: The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PRO_DCACHE_CLEAN_DONE + description: The bit is used to indicate clean operation is finished. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: PRO_DCACHE_LOCK0_EN + description: The bit is used to enable pre-lock operation which is combined with PRO_DCACHE_LOCK0_ADDR_REG and PRO_DCACHE_LOCK0_SIZE_REG. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PRO_DCACHE_LOCK1_EN + description: The bit is used to enable pre-lock operation which is combined with PRO_DCACHE_LOCK1_ADDR_REG and PRO_DCACHE_LOCK1_SIZE_REG. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: PRO_DCACHE_AUTOLOAD_ENA + description: "The bit is used to enable and disable conditional-preload operation. It is combined with pre_dcache_autoload_done. 1: enable, 0: disable." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: PRO_DCACHE_AUTOLOAD_DONE + description: The bit is used to indicate conditional-preload operation is finished. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: PRO_DCACHE_PRELOAD_ENA + description: The bit is used to enable preload operation. It will be cleared by hardware after preload operation done. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: PRO_DCACHE_PRELOAD_DONE + description: The bit is used to indicate preload operation is finished. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: PRO_DCACHE_UNLOCK_ENA + description: The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: PRO_DCACHE_UNLOCK_DONE + description: The bit is used to indicate unlock operation is finished. + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: PRO_DCACHE_LOCK_ENA + description: The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PRO_DCACHE_LOCK_DONE + description: The bit is used to indicate lock operation is finished. + bitOffset: 25 + bitWidth: 1 + access: read-only + - register: + name: PRO_DCACHE_CTRL1 + description: register description + addressOffset: 4 + size: 32 + resetValue: 7 + fields: + - name: PRO_DCACHE_MASK_BUS0 + description: "The bit is used to disable dbus0, 0: enable, 1: disable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_DCACHE_MASK_BUS1 + description: "The bit is used to disable dbus1, 0: enable, 1: disable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PRO_DCACHE_MASK_BUS2 + description: "The bit is used to disable dbus2, 0: enable, 1: disable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: PRO_DCACHE_TAG_POWER_CTRL + description: register description + addressOffset: 8 + size: 32 + resetValue: 5 + fields: + - name: PRO_DCACHE_TAG_MEM_FORCE_ON + description: "The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_DCACHE_TAG_MEM_FORCE_PD + description: "The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: power down" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PRO_DCACHE_TAG_MEM_FORCE_PU + description: "The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: power up" + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: PRO_DCACHE_LOCK0_ADDR + description: register description + addressOffset: 12 + size: 32 + fields: + - name: PRO_DCACHE_LOCK0_ADDR + description: "The bits are used to configure the first start virtual address of data locking, which is combined with PRO_DCACHE_LOCK0_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PRO_DCACHE_LOCK0_SIZE + description: register description + addressOffset: 16 + size: 32 + fields: + - name: PRO_DCACHE_LOCK0_SIZE + description: "The bits are used to configure the first length of data locking, which is combined with PRO_DCACHE_LOCK0_ADDR_REG" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: PRO_DCACHE_LOCK1_ADDR + description: register description + addressOffset: 20 + size: 32 + fields: + - name: PRO_DCACHE_LOCK1_ADDR + description: "The bits are used to configure the second start virtual address of data locking, which is combined with PRO_DCACHE_LOCK1_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PRO_DCACHE_LOCK1_SIZE + description: register description + addressOffset: 24 + size: 32 + fields: + - name: PRO_DCACHE_LOCK1_SIZE + description: "The bits are used to configure the second length of data locking, which is combined with PRO_DCACHE_LOCK1_ADDR_REG" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: PRO_DCACHE_MEM_SYNC0 + description: register description + addressOffset: 28 + size: 32 + fields: + - name: PRO_DCACHE_MEMSYNC_ADDR + description: "The bits are used to configure the start virtual address for invalidate, flush, clean, lock and unlock operations. The manual operations will be issued if the address is validate. The auto operations will be issued if the address is invalidate. It should be combined with PRO_DCACHE_MEM_SYNC1." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PRO_DCACHE_MEM_SYNC1 + description: register description + addressOffset: 32 + size: 32 + fields: + - name: PRO_DCACHE_MEMSYNC_SIZE + description: "The bits are used to configure the length for invalidate, flush, clean, lock and unlock operations. The manual operations will be issued if it is validate. The auto operations will be issued if it is invalidate. It should be combined with PRO_DCACHE_MEM_SYNC0." + bitOffset: 0 + bitWidth: 19 + access: read-write + - register: + name: PRO_DCACHE_PRELOAD_ADDR + description: register description + addressOffset: 36 + size: 32 + fields: + - name: PRO_DCACHE_PRELOAD_ADDR + description: The bits are used to configure the start virtual address for manual pre-load operation. It should be combined with PRO_DCACHE_PRELOAD_SIZE_REG. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PRO_DCACHE_PRELOAD_SIZE + description: register description + addressOffset: 40 + size: 32 + resetValue: 512 + fields: + - name: PRO_DCACHE_PRELOAD_SIZE + description: The bits are used to configure the length for manual pre-load operation. It should be combined with PRO_DCACHE_PRELOAD_ADDR_REG.. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: PRO_DCACHE_PRELOAD_ORDER + description: "The bits are used to configure the direction of manual pre-load operation. 1: descending, 0: ascending." + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PRO_DCACHE_AUTOLOAD_CFG + description: register description + addressOffset: 44 + size: 32 + fields: + - name: PRO_DCACHE_AUTOLOAD_MODE + description: Reserved. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_DCACHE_AUTOLOAD_STEP + description: Reserved. + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: PRO_DCACHE_AUTOLOAD_ORDER + description: "The bits are used to configure the direction of conditional pre-load operation. 1: descending, 0: ascending." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PRO_DCACHE_AUTOLOAD_RQST + description: "The bits are used to configure trigger conditions for conditional pre-load. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: PRO_DCACHE_AUTOLOAD_SIZE + description: The bits are used to configure the numbers of the cache block for the issuing conditional pre-load operation. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: PRO_DCACHE_AUTOLOAD_SCT0_ENA + description: The bits are used to enable the second section for conditional pre-load operation. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: PRO_DCACHE_AUTOLOAD_SCT1_ENA + description: The bits are used to enable the first section for conditional pre-load operation. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: PRO_DCACHE_AUTOLOAD_SECTION0_ADDR + description: register description + addressOffset: 48 + size: 32 + fields: + - name: PRO_DCACHE_AUTOLOAD_SCT0_ADDR + description: The bits are used to configure the start virtual address of the first section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct0_ena. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PRO_DCACHE_AUTOLOAD_SECTION0_SIZE + description: register description + addressOffset: 52 + size: 32 + resetValue: 32768 + fields: + - name: PRO_DCACHE_AUTOLOAD_SCT0_SIZE + description: The bits are used to configure the length of the first section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct0_ena. + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: PRO_DCACHE_AUTOLOAD_SECTION1_ADDR + description: register description + addressOffset: 56 + size: 32 + fields: + - name: PRO_DCACHE_AUTOLOAD_SCT1_ADDR + description: The bits are used to configure the start virtual address of the second section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct1_ena. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PRO_DCACHE_AUTOLOAD_SECTION1_SIZE + description: register description + addressOffset: 60 + size: 32 + resetValue: 32768 + fields: + - name: PRO_DCACHE_AUTOLOAD_SCT1_SIZE + description: The bits are used to configure the length of the second section for conditional pre-load operation. It should be combined with pro_dcache_autoload_sct1_ena. + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: PRO_ICACHE_CTRL + description: register description + addressOffset: 64 + size: 32 + resetValue: 256 + fields: + - name: PRO_ICACHE_ENABLE + description: "The bit is used to activate the data cache. 0: disable, 1: enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_ICACHE_SETSIZE_MODE + description: "The bit is used to configure cache memory size.0: 8KB, 1: 16KB" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PRO_ICACHE_BLOCKSIZE_MODE + description: "The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PRO_ICACHE_INVALIDATE_ENA + description: The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: PRO_ICACHE_INVALIDATE_DONE + description: The bit is used to indicate invalidate operation is finished. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: PRO_ICACHE_LOCK0_EN + description: The bit is used to enable pre-lock operation which is combined with PRO_ICACHE_LOCK0_ADDR_REG and PRO_ICACHE_LOCK0_SIZE_REG. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PRO_ICACHE_LOCK1_EN + description: The bit is used to enable pre-lock operation which is combined with PRO_ICACHE_LOCK1_ADDR_REG and PRO_ICACHE_LOCK1_SIZE_REG. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: PRO_ICACHE_AUTOLOAD_ENA + description: "The bit is used to enable and disable conditional-preload operation. It is combined with pre_dcache_autoload_done. 1: enable, 0: disable." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: PRO_ICACHE_AUTOLOAD_DONE + description: The bit is used to indicate conditional-preload operation is finished. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: PRO_ICACHE_PRELOAD_ENA + description: The bit is used to enable preload operation. It will be cleared by hardware after preload operation done. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: PRO_ICACHE_PRELOAD_DONE + description: The bit is used to indicate preload operation is finished. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: PRO_ICACHE_UNLOCK_ENA + description: The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: PRO_ICACHE_UNLOCK_DONE + description: The bit is used to indicate unlock operation is finished. + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: PRO_ICACHE_LOCK_ENA + description: The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PRO_ICACHE_LOCK_DONE + description: The bit is used to indicate lock operation is finished. + bitOffset: 25 + bitWidth: 1 + access: read-only + - register: + name: PRO_ICACHE_CTRL1 + description: register description + addressOffset: 68 + size: 32 + resetValue: 7 + fields: + - name: PRO_ICACHE_MASK_BUS0 + description: "The bit is used to disable ibus0, 0: enable, 1: disable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_ICACHE_MASK_BUS1 + description: "The bit is used to disable ibus1, 0: enable, 1: disable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PRO_ICACHE_MASK_BUS2 + description: "The bit is used to disable ibus2, 0: enable, 1: disable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: PRO_ICACHE_TAG_POWER_CTRL + description: register description + addressOffset: 72 + size: 32 + resetValue: 5 + fields: + - name: PRO_ICACHE_TAG_MEM_FORCE_ON + description: "The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_ICACHE_TAG_MEM_FORCE_PD + description: "The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PRO_ICACHE_TAG_MEM_FORCE_PU + description: "The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power up" + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: PRO_ICACHE_LOCK0_ADDR + description: register description + addressOffset: 76 + size: 32 + fields: + - name: PRO_ICACHE_LOCK0_ADDR + description: "The bits are used to configure the first start virtual address of data locking, which is combined with PRO_ICACHE_LOCK0_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PRO_ICACHE_LOCK0_SIZE + description: register description + addressOffset: 80 + size: 32 + fields: + - name: PRO_ICACHE_LOCK0_SIZE + description: "The bits are used to configure the first length of data locking, which is combined with PRO_ICACHE_LOCK0_ADDR_REG" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: PRO_ICACHE_LOCK1_ADDR + description: register description + addressOffset: 84 + size: 32 + fields: + - name: PRO_ICACHE_LOCK1_ADDR + description: "The bits are used to configure the second start virtual address of data locking, which is combined with PRO_ICACHE_LOCK1_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PRO_ICACHE_LOCK1_SIZE + description: register description + addressOffset: 88 + size: 32 + fields: + - name: PRO_ICACHE_LOCK1_SIZE + description: "The bits are used to configure the second length of data locking, which is combined with PRO_ICACHE_LOCK1_ADDR_REG" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: PRO_ICACHE_MEM_SYNC0 + description: register description + addressOffset: 92 + size: 32 + fields: + - name: PRO_ICACHE_MEMSYNC_ADDR + description: "The bits are used to configure the start virtual address for invalidate, flush, clean, lock and unlock operations. The manual operations will be issued if the address is validate. The auto operations will be issued if the address is invalidate. It should be combined with PRO_ICACHE_MEM_SYNC1." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PRO_ICACHE_MEM_SYNC1 + description: register description + addressOffset: 96 + size: 32 + fields: + - name: PRO_ICACHE_MEMSYNC_SIZE + description: "The bits are used to configure the length for invalidate, flush, clean, lock and unlock operations. The manual operations will be issued if it is validate. The auto operations will be issued if it is invalidate. It should be combined with PRO_ICACHE_MEM_SYNC0." + bitOffset: 0 + bitWidth: 19 + access: read-write + - register: + name: PRO_ICACHE_PRELOAD_ADDR + description: register description + addressOffset: 100 + size: 32 + fields: + - name: PRO_ICACHE_PRELOAD_ADDR + description: The bits are used to configure the start virtual address for manual pre-load operation. It should be combined with PRO_ICACHE_PRELOAD_SIZE_REG. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PRO_ICACHE_PRELOAD_SIZE + description: register description + addressOffset: 104 + size: 32 + resetValue: 512 + fields: + - name: PRO_ICACHE_PRELOAD_SIZE + description: The bits are used to configure the length for manual pre-load operation. It should be combined with PRO_ICACHE_PRELOAD_ADDR_REG.. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: PRO_ICACHE_PRELOAD_ORDER + description: "The bits are used to configure the direction of manual pre-load operation. 1: descending, 0: ascending." + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PRO_ICACHE_AUTOLOAD_CFG + description: register description + addressOffset: 108 + size: 32 + fields: + - name: PRO_ICACHE_AUTOLOAD_MODE + description: Reserved. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_ICACHE_AUTOLOAD_STEP + description: Reserved. + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: PRO_ICACHE_AUTOLOAD_ORDER + description: "The bits are used to configure the direction of conditional pre-load operation. 1: descending, 0: ascending." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PRO_ICACHE_AUTOLOAD_RQST + description: "The bits are used to configure trigger conditions for conditional pre-load. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: PRO_ICACHE_AUTOLOAD_SIZE + description: The bits are used to configure the numbers of the cache block for the issuing conditional pre-load operation. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: PRO_ICACHE_AUTOLOAD_SCT0_ENA + description: The bits are used to enable the second section for conditional pre-load operation. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: PRO_ICACHE_AUTOLOAD_SCT1_ENA + description: The bits are used to enable the first section for conditional pre-load operation. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: PRO_ICACHE_AUTOLOAD_SECTION0_ADDR + description: register description + addressOffset: 112 + size: 32 + fields: + - name: PRO_ICACHE_AUTOLOAD_SCT0_ADDR + description: The bits are used to configure the start virtual address of the first section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct0_ena. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PRO_ICACHE_AUTOLOAD_SECTION0_SIZE + description: register description + addressOffset: 116 + size: 32 + resetValue: 32768 + fields: + - name: PRO_ICACHE_AUTOLOAD_SCT0_SIZE + description: The bits are used to configure the length of the first section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct0_ena. + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: PRO_ICACHE_AUTOLOAD_SECTION1_ADDR + description: register description + addressOffset: 120 + size: 32 + fields: + - name: PRO_ICACHE_AUTOLOAD_SCT1_ADDR + description: The bits are used to configure the start virtual address of the second section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct1_ena. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PRO_ICACHE_AUTOLOAD_SECTION1_SIZE + description: register description + addressOffset: 124 + size: 32 + resetValue: 32768 + fields: + - name: PRO_ICACHE_AUTOLOAD_SCT1_SIZE + description: The bits are used to configure the length of the second section for conditional pre-load operation. It should be combined with pro_icache_autoload_sct1_ena. + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: IC_PRELOAD_CNT + description: register description + addressOffset: 128 + size: 32 + fields: + - name: IC_PRELOAD_CNT + description: The bits are used to count the number of issued pre-load which include manual pre-load and conditional pre-load. + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: IC_PRELOAD_MISS_CNT + description: register description + addressOffset: 132 + size: 32 + fields: + - name: IC_PRELOAD_MISS_CNT + description: The bits are used to count the number of missed pre-load which include manual pre-load and conditional pre-load. + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: IBUS2_ABANDON_CNT + description: register description + addressOffset: 136 + size: 32 + fields: + - name: IBUS2_ABANDON_CNT + description: The bits are used to count the number of the abandoned ibus2 access. + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: IBUS1_ABANDON_CNT + description: register description + addressOffset: 140 + size: 32 + fields: + - name: IBUS1_ABANDON_CNT + description: The bits are used to count the number of the abandoned ibus1 access. + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: IBUS0_ABANDON_CNT + description: register description + addressOffset: 144 + size: 32 + fields: + - name: IBUS0_ABANDON_CNT + description: The bits are used to count the number of the abandoned ibus0 access. + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: IBUS2_ACS_MISS_CNT + description: register description + addressOffset: 148 + size: 32 + fields: + - name: IBUS2_ACS_MISS_CNT + description: The bits are used to count the number of the cache miss caused by ibus2 access. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IBUS1_ACS_MISS_CNT + description: register description + addressOffset: 152 + size: 32 + fields: + - name: IBUS1_ACS_MISS_CNT + description: The bits are used to count the number of the cache miss caused by ibus1 access. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IBUS0_ACS_MISS_CNT + description: register description + addressOffset: 156 + size: 32 + fields: + - name: IBUS0_ACS_MISS_CNT + description: The bits are used to count the number of the cache miss caused by ibus0 access. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IBUS2_ACS_CNT + description: register description + addressOffset: 160 + size: 32 + fields: + - name: IBUS2_ACS_CNT + description: The bits are used to count the number of ibus2 access icache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IBUS1_ACS_CNT + description: register description + addressOffset: 164 + size: 32 + fields: + - name: IBUS1_ACS_CNT + description: The bits are used to count the number of ibus1 access icache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IBUS0_ACS_CNT + description: register description + addressOffset: 168 + size: 32 + fields: + - name: IBUS0_ACS_CNT + description: The bits are used to count the number of ibus0 access icache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DC_PRELOAD_CNT + description: register description + addressOffset: 172 + size: 32 + fields: + - name: DC_PRELOAD_CNT + description: The bits are used to count the number of issued pre-load which include manual pre-load and conditional pre-load. + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: DC_PRELOAD_EVICT_CNT + description: register description + addressOffset: 176 + size: 32 + fields: + - name: DC_PRELOAD_EVICT_CNT + description: The bits are used to count the number of cache evictions by pre-load which include manual pre-load and conditional pre-load. + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: DC_PRELOAD_MISS_CNT + description: register description + addressOffset: 180 + size: 32 + fields: + - name: DC_PRELOAD_MISS_CNT + description: The bits are used to count the number of missed pre-load which include manual pre-load and conditional pre-load. + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: DBUS2_ABANDON_CNT + description: register description + addressOffset: 184 + size: 32 + fields: + - name: DBUS2_ABANDON_CNT + description: The bits are used to count the number of the abandoned dbus2 access. + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: DBUS1_ABANDON_CNT + description: register description + addressOffset: 188 + size: 32 + fields: + - name: DBUS1_ABANDON_CNT + description: The bits are used to count the number of the abandoned dbus1 access. + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: DBUS0_ABANDON_CNT + description: register description + addressOffset: 192 + size: 32 + fields: + - name: DBUS0_ABANDON_CNT + description: The bits are used to count the number of the abandoned dbus0 access. + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: DBUS2_ACS_WB_CNT + description: register description + addressOffset: 196 + size: 32 + fields: + - name: DBUS2_ACS_WB_CNT + description: The bits are used to count the number of cache evictions by dbus2 access cache. + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: DBUS1_ACS_WB_CNT + description: register description + addressOffset: 200 + size: 32 + fields: + - name: DBUS1_ACS_WB_CNT + description: The bits are used to count the number of cache evictions by dbus1 access cache. + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: DBUS0_ACS_WB_CNT + description: register description + addressOffset: 204 + size: 32 + fields: + - name: DBUS0_ACS_WB_CNT + description: The bits are used to count the number of cache evictions by dbus0 access cache. + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: DBUS2_ACS_MISS_CNT + description: register description + addressOffset: 208 + size: 32 + fields: + - name: DBUS2_ACS_MISS_CNT + description: The bits are used to count the number of the cache miss caused by dbus2 access. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DBUS1_ACS_MISS_CNT + description: register description + addressOffset: 212 + size: 32 + fields: + - name: DBUS1_ACS_MISS_CNT + description: The bits are used to count the number of the cache miss caused by dbus1 access. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DBUS0_ACS_MISS_CNT + description: register description + addressOffset: 216 + size: 32 + fields: + - name: DBUS0_ACS_MISS_CNT + description: The bits are used to count the number of the cache miss caused by dbus0 access. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DBUS2_ACS_CNT + description: register description + addressOffset: 220 + size: 32 + fields: + - name: DBUS2_ACS_CNT + description: The bits are used to count the number of dbus2 access dcache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DBUS1_ACS_CNT + description: register description + addressOffset: 224 + size: 32 + fields: + - name: DBUS1_ACS_CNT + description: The bits are used to count the number of dbus1 access dcache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DBUS0_ACS_CNT + description: register description + addressOffset: 228 + size: 32 + fields: + - name: DBUS0_ACS_CNT + description: The bits are used to count the number of dbus0 access dcache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CACHE_DBG_INT_ENA + description: register description + addressOffset: 232 + size: 32 + resetValue: 1 + fields: + - name: CACHE_DBG_EN + description: "The bit is used to activate the cache track function. 1: enable, 0: disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IBUS_ACS_MSK_IC_INT_ENA + description: The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IBUS_CNT_OVF_INT_ENA + description: The bit is used to enable interrupt by ibus counter overflow. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: IC_SYNC_SIZE_FAULT_INT_ENA + description: The bit is used to enable interrupt by manual sync configurations fault. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IC_PRELOAD_SIZE_FAULT_INT_ENA + description: The bit is used to enable interrupt by manual pre-load configurations fault. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: ICACHE_REJECT_INT_ENA + description: The bit is used to enable interrupt by authentication fail. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: ICACHE_SET_PRELOAD_ILG_INT_ENA + description: "The bit is used to enable interrupt by illegal writing preload registers of icache while icache is busy to issue lock,sync and pre-load operations." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: ICACHE_SET_SYNC_ILG_INT_ENA + description: "The bit is used to enable interrupt by illegal writing sync registers of icache while icache is busy to issue lock,sync and pre-load operations." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ICACHE_SET_LOCK_ILG_INT_ENA + description: "The bit is used to enable interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DBUS_ACS_MSK_DC_INT_ENA + description: The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DBUS_CNT_OVF_INT_ENA + description: The bit is used to enable interrupt by dbus counter overflow. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DC_SYNC_SIZE_FAULT_INT_ENA + description: The bit is used to enable interrupt by manual sync configurations fault. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DC_PRELOAD_SIZE_FAULT_INT_ENA + description: The bit is used to enable interrupt by manual pre-load configurations fault. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DCACHE_WRITE_FLASH_INT_ENA + description: The bit is used to enable interrupt by dcache trying to write flash. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DCACHE_REJECT_INT_ENA + description: The bit is used to enable interrupt by authentication fail. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DCACHE_SET_PRELOAD_ILG_INT_ENA + description: "The bit is used to enable interrupt by illegal writing preload registers of dcache while dcache is busy to issue lock,sync and pre-load operations." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DCACHE_SET_SYNC_ILG_INT_ENA + description: "The bit is used to enable interrupt by illegal writing sync registers of dcache while dcache is busy to issue lock,sync and pre-load operations." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: DCACHE_SET_LOCK_ILG_INT_ENA + description: "The bit is used to enable interrupt by illegal writing lock registers of dcache while dcache is busy to issue lock,sync or pre-load operations." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: MMU_ENTRY_FAULT_INT_ENA + description: The bit is used to enable interrupt by mmu entry fault. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: CACHE_DBG_INT_CLR + description: register description + addressOffset: 236 + size: 32 + fields: + - name: IBUS_ACS_MSK_IC_INT_CLR + description: The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: IBUS_CNT_OVF_INT_CLR + description: The bit is used to clear interrupt by ibus counter overflow. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: IC_SYNC_SIZE_FAULT_INT_CLR + description: The bit is used to clear interrupt by manual sync configurations fault. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: IC_PRELOAD_SIZE_FAULT_INT_CLR + description: The bit is used to clear interrupt by manual pre-load configurations fault. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: ICACHE_REJECT_INT_CLR + description: The bit is used to clear interrupt by authentication fail. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: ICACHE_SET_ILG_INT_CLR + description: "The bit is used to clear interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations." + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: DBUS_ACS_MSK_DC_INT_CLR + description: The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: DBUS_CNT_OVF_INT_CLR + description: The bit is used to clear interrupt by dbus counter overflow. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: DC_SYNC_SIZE_FAULT_INT_CLR + description: The bit is used to clear interrupt by manual sync configurations fault. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: DC_PRELOAD_SIZE_FAULT_INT_CLR + description: The bit is used to clear interrupt by manual pre-load configurations fault. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: DCACHE_WRITE_FLASH_INT_CLR + description: The bit is used to clear interrupt by dcache trying to write flash. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: DCACHE_REJECT_INT_CLR + description: The bit is used to clear interrupt by authentication fail. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: DCACHE_SET_ILG_INT_CLR + description: "The bit is used to clear interrupt by illegal writing lock registers of dcache while dcache is busy to issue lock,sync or pre-load operations." + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: MMU_ENTRY_FAULT_INT_CLR + description: The bit is used to clear interrupt by mmu entry fault. + bitOffset: 13 + bitWidth: 1 + access: write-only + - register: + name: CACHE_DBG_STATUS0 + description: register description + addressOffset: 240 + size: 32 + fields: + - name: IBUS0_ACS_MSK_ICACHE_ST + description: The bit is used to indicate interrupt by cpu access icache while the ibus0 is disabled or icache is disabled which include speculative access. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: IBUS1_ACS_MSK_ICACHE_ST + description: The bit is used to indicate interrupt by cpu access icache while the ibus1 is disabled or icache is disabled which include speculative access. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: IBUS2_ACS_MSK_ICACHE_ST + description: The bit is used to indicate interrupt by cpu access icache while the ibus2 is disabled or icache is disabled which include speculative access. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: IBUS0_ACS_CNT_OVF_ST + description: The bit is used to indicate interrupt by ibus0 counter overflow. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: IBUS1_ACS_CNT_OVF_ST + description: The bit is used to indicate interrupt by ibus1 counter overflow. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: IBUS2_ACS_CNT_OVF_ST + description: The bit is used to indicate interrupt by ibus2 counter overflow. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: IBUS0_ACS_MISS_CNT_OVF_ST + description: The bit is used to indicate interrupt by ibus0 miss counter overflow. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: IBUS1_ACS_MISS_CNT_OVF_ST + description: The bit is used to indicate interrupt by ibus1 miss counter overflow. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: IBUS2_ACS_MISS_CNT_OVF_ST + description: The bit is used to indicate interrupt by ibus2 miss counter overflow. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: IBUS0_ABANDON_CNT_OVF_ST + description: The bit is used to indicate interrupt by ibus0 abandon counter overflow. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: IBUS1_ABANDON_CNT_OVF_ST + description: The bit is used to indicate interrupt by ibus1 abandon counter overflow. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: IBUS2_ABANDON_CNT_OVF_ST + description: The bit is used to indicate interrupt by ibus2 abandon counter overflow. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: IC_PRELOAD_MISS_CNT_OVF_ST + description: The bit is used to indicate interrupt by pre-load miss counter overflow. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: IC_PRELOAD_CNT_OVF_ST + description: The bit is used to indicate interrupt by pre-load counter overflow. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: IC_SYNC_SIZE_FAULT_ST + description: The bit is used to indicate interrupt by manual sync configurations fault. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: IC_PRELOAD_SIZE_FAULT_ST + description: The bit is used to indicate interrupt by manual pre-load configurations fault. + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: ICACHE_REJECT_ST + description: The bit is used to indicate interrupt by authentication fail. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: ICACHE_SET_PRELOAD_ILG_ST + description: "The bit is used to indicate interrupt by illegal writing preload registers of icache while icache is busy to issue lock,sync and pre-load operations." + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: ICACHE_SET_SYNC_ILG_ST + description: "The bit is used to indicate interrupt by illegal writing sync registers of icache while icache is busy to issue lock,sync and pre-load operations." + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: ICACHE_SET_LOCK_ILG_ST + description: "The bit is used to indicate interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations." + bitOffset: 24 + bitWidth: 1 + access: read-only + - register: + name: CACHE_DBG_STATUS1 + description: register description + addressOffset: 244 + size: 32 + fields: + - name: DBUS0_ACS_MSK_DCACHE_ST + description: The bit is used to indicate interrupt by cpu access dcache while the dbus0 is disabled or dcache is disabled which include speculative access. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DBUS1_ACS_MSK_DCACHE_ST + description: The bit is used to indicate interrupt by cpu access dcache while the dbus1 is disabled or dcache is disabled which include speculative access. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: DBUS2_ACS_MSK_DCACHE_ST + description: The bit is used to indicate interrupt by cpu access dcache while the dbus2 is disabled or dcache is disabled which include speculative access. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: DBUS0_ACS_CNT_OVF_ST + description: The bit is used to indicate interrupt by dbus0 counter overflow. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DBUS1_ACS_CNT_OVF_ST + description: The bit is used to indicate interrupt by dbus1 counter overflow. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: DBUS2_ACS_CNT_OVF_ST + description: The bit is used to indicate interrupt by dbus2 counter overflow. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: DBUS0_ACS_MISS_CNT_OVF_ST + description: The bit is used to indicate interrupt by dbus0 miss counter overflow. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DBUS1_ACS_MISS_CNT_OVF_ST + description: The bit is used to indicate interrupt by dbus1 miss counter overflow. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: DBUS2_ACS_MISS_CNT_OVF_ST + description: The bit is used to indicate interrupt by dbus2 miss counter overflow. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: DBUS0_ACS_WB_CNT_OVF_ST + description: The bit is used to indicate interrupt by dbus0 eviction counter overflow. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: DBUS1_ACS_WB_CNT_OVF_ST + description: The bit is used to indicate interrupt by dbus1 eviction counter overflow. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: DBUS2_ACS_WB_CNT_OVF_ST + description: The bit is used to indicate interrupt by dbus2 eviction counter overflow. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DBUS0_ABANDON_CNT_OVF_ST + description: The bit is used to indicate interrupt by dbus0 abandon counter overflow. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: DBUS1_ABANDON_CNT_OVF_ST + description: The bit is used to indicate interrupt by dbus1 abandon counter overflow. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: DBUS2_ABANDON_CNT_OVF_ST + description: The bit is used to indicate interrupt by dbus2 abandon counter overflow. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: DC_PRELOAD_MISS_CNT_OVF_ST + description: The bit is used to indicate interrupt by pre-load miss counter overflow. + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: DC_PRELOAD_EVICT_CNT_OVF_ST + description: The bit is used to indicate interrupt by pre-load eviction counter overflow. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: DC_PRELOAD_CNT_OVF_ST + description: The bit is used to indicate interrupt by pre-load counter overflow. + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: DC_SYNC_SIZE_FAULT_ST + description: The bit is used to indicate interrupt by manual sync configurations fault. + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: DC_PRELOAD_SIZE_FAULT_ST + description: The bit is used to indicate interrupt by manual pre-load configurations fault. + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: DCACHE_WRITE_FLASH_ST + description: The bit is used to indicate interrupt by dcache trying to write flash. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: DCACHE_REJECT_ST + description: The bit is used to indicate interrupt by authentication fail. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: DCACHE_SET_PRELOAD_ILG_ST + description: "The bit is used to indicate interrupt by illegal writing preload registers of icache while icache is busy to issue lock,sync and pre-load operations." + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: DCACHE_SET_SYNC_ILG_ST + description: "The bit is used to indicate interrupt by illegal writing sync registers of icache while icache is busy to issue lock,sync and pre-load operations." + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: DCACHE_SET_LOCK_ILG_ST + description: "The bit is used to indicate interrupt by illegal writing lock registers of icache while icache is busy to issue lock,sync or pre-load operations." + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: MMU_ENTRY_FAULT_ST + description: The bit is used to indicate interrupt by mmu entry fault. + bitOffset: 30 + bitWidth: 1 + access: read-only + - register: + name: PRO_CACHE_ACS_CNT_CLR + description: register description + addressOffset: 248 + size: 32 + fields: + - name: PRO_DCACHE_ACS_CNT_CLR + description: "The bit is used to clear dcache counter which include DC_PRELOAD_CNT_REG, DC_PRELOAD_EVICT_CNT_REG, DC_PRELOAD_MISS_CNT_REG, DBUS0-2_ABANDON_CNT_REG, DBUS0-2_ACS_WB_CNT_REG, DBUS0-2_ACS_MISS_CNT_REG and DBUS0-2_ACS_CNT_REG." + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: PRO_ICACHE_ACS_CNT_CLR + description: "The bit is used to clear icache counter which include IC_PRELOAD_CNT_REG, IC_PRELOAD_MISS_CNT_REG, IBUS0-2_ABANDON_CNT_REG, IBUS0-2_ACS_MISS_CNT_REG and IBUS0-2_ACS_CNT_REG." + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: PRO_DCACHE_REJECT_ST + description: register description + addressOffset: 252 + size: 32 + fields: + - name: PRO_DCACHE_TAG_ATTR + description: "The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able." + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: PRO_DCACHE_CPU_ATTR + description: "The bits are used to indicate the attribute of CPU access dcache when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able." + bitOffset: 3 + bitWidth: 3 + access: read-only + - register: + name: PRO_DCACHE_REJECT_VADDR + description: register description + addressOffset: 256 + size: 32 + fields: + - name: PRO_DCACHE_CPU_VADDR + description: The bits are used to indicate the virtual address of CPU access dcache when authentication fail. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PRO_ICACHE_REJECT_ST + description: register description + addressOffset: 260 + size: 32 + fields: + - name: PRO_ICACHE_TAG_ATTR + description: "The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able." + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: PRO_ICACHE_CPU_ATTR + description: "The bits are used to indicate the attribute of CPU access icache when authentication fail. 0: invalidate, 1: execute-able, 2: read-able" + bitOffset: 3 + bitWidth: 3 + access: read-only + - register: + name: PRO_ICACHE_REJECT_VADDR + description: register description + addressOffset: 264 + size: 32 + fields: + - name: PRO_ICACHE_CPU_VADDR + description: The bits are used to indicate the virtual address of CPU access icache when authentication fail. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PRO_CACHE_MMU_FAULT_CONTENT + description: register description + addressOffset: 268 + size: 32 + fields: + - name: PRO_CACHE_MMU_FAULT_CONTENT + description: The bits are used to indicate the content of mmu entry which cause mmu fault.. + bitOffset: 0 + bitWidth: 17 + access: read-only + - name: PRO_CACHE_MMU_FAULT_CODE + description: "The bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: flush, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx" + bitOffset: 17 + bitWidth: 3 + access: read-only + - register: + name: PRO_CACHE_MMU_FAULT_VADDR + description: register description + addressOffset: 272 + size: 32 + fields: + - name: PRO_CACHE_MMU_FAULT_VADDR + description: The bits are used to indicate the virtual address which cause mmu fault.. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PRO_CACHE_WRAP_AROUND_CTRL + description: register description + addressOffset: 276 + size: 32 + fields: + - name: PRO_CACHE_FLASH_WRAP_AROUND + description: The bit is used to enable wrap around mode when read data from flash. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_SRAM_RD_WRAP_AROUND + description: The bit is used to enable wrap around mode when read data from spiram. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: PRO_CACHE_MMU_POWER_CTRL + description: register description + addressOffset: 280 + size: 32 + resetValue: 5 + fields: + - name: PRO_CACHE_MMU_MEM_FORCE_ON + description: "The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_MMU_MEM_FORCE_PD + description: "The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_MMU_MEM_FORCE_PU + description: "The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up" + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: PRO_CACHE_STATE + description: register description + addressOffset: 284 + size: 32 + fields: + - name: PRO_ICACHE_STATE + description: "The bit is used to indicate icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state" + bitOffset: 0 + bitWidth: 12 + access: read-only + - name: PRO_DCACHE_STATE + description: "The bit is used to indicate dcache main fsm is in idle state or not. 1: in idle state, 0: not in idle state" + bitOffset: 12 + bitWidth: 12 + access: read-only + - register: + name: CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE + description: register description + addressOffset: 288 + size: 32 + fields: + - name: RECORD_DISABLE_DB_ENCRYPT + description: Reserved. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RECORD_DISABLE_G0CB_DECRYPT + description: Reserved. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON + description: register description + addressOffset: 292 + size: 32 + resetValue: 7 + fields: + - name: CLK_FORCE_ON_DB_ENCRYPT + description: "The bit is used to close clock gating of encrypt clock. 1: close gating, 0: open clock gating." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CLK_FORCE_ON_G0CB_DECRYPT + description: "The bit is used to close clock gating of decrypt clock. 1: close gating, 0: open clock gating." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT + description: "The bit is used to close clock gating of encrypt and decrypt clock. 1: close gating, 0: open clock gating." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: CACHE_BRIDGE_ARBITER_CTRL + description: register description + addressOffset: 296 + size: 32 + fields: + - name: ALLOC_WB_HOLD_ARBITER + description: Reserved. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CACHE_PRELOAD_INT_CTRL + description: register description + addressOffset: 300 + size: 32 + fields: + - name: PRO_ICACHE_PRELOAD_INT_ST + description: The bit is used to indicate the interrupt by icache pre-load done. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PRO_ICACHE_PRELOAD_INT_ENA + description: The bit is used to enable the interrupt by icache pre-load done. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PRO_ICACHE_PRELOAD_INT_CLR + description: The bit is used to clear the interrupt by icache pre-load done. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: PRO_DCACHE_PRELOAD_INT_ST + description: The bit is used to indicate the interrupt by dcache pre-load done. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: PRO_DCACHE_PRELOAD_INT_ENA + description: The bit is used to enable the interrupt by dcache pre-load done. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: PRO_DCACHE_PRELOAD_INT_CLR + description: The bit is used to clear the interrupt by dcache pre-load done. + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: CACHE_SYNC_INT_CTRL + description: register description + addressOffset: 304 + size: 32 + fields: + - name: PRO_ICACHE_SYNC_INT_ST + description: The bit is used to indicate the interrupt by icache sync done. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PRO_ICACHE_SYNC_INT_ENA + description: The bit is used to enable the interrupt by icache sync done. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PRO_ICACHE_SYNC_INT_CLR + description: The bit is used to clear the interrupt by icache sync done. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: PRO_DCACHE_SYNC_INT_ST + description: The bit is used to indicate the interrupt by dcache sync done. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: PRO_DCACHE_SYNC_INT_ENA + description: The bit is used to enable the interrupt by dcache sync done. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: PRO_DCACHE_SYNC_INT_CLR + description: The bit is used to clear the interrupt by dcache sync done. + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: CACHE_CONF_MISC + description: register description + addressOffset: 308 + size: 32 + resetValue: 3 + fields: + - name: PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT + description: The bit is used to disable checking mmu entry fault by preload operation. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT + description: The bit is used to disable checking mmu entry fault by sync operation. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CLOCK_GATE + description: register description + addressOffset: 312 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: Reserved. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: PRO_EXTMEM_REG_DATE + description: register description + addressOffset: 1020 + size: 32 + resetValue: 26231168 + fields: + - name: PRO_EXTMEM_REG_DATE + description: Reserved. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: GPIO + description: General Purpose Input/Output + groupName: GPIO + baseAddress: 1061175296 + addressBlock: + - offset: 0 + size: 1588 + usage: registers + interrupt: + - name: GPIO + value: 23 + - name: GPIO_NMI + value: 24 + - name: GPIO_INTR_2 + value: 25 + - name: GPIO_NMI_2 + value: 26 + registers: + - register: + name: BT_SELECT + description: GPIO bit select register + addressOffset: 0 + size: 32 + fields: + - name: BT_SEL + description: Reserved + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: OUT + description: GPIO0 ~ 31 output register + addressOffset: 4 + size: 32 + fields: + - name: DATA_ORIG + description: GPIO0 ~ 31 output value in simple GPIO output mode. The values of bit0 ~ bit31 correspond to the output value of GPIO0 ~ GPIO31 respectively. Bit22 ~ bit25 are invalid. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: OUT_W1TS + description: GPIO0 ~ 31 output bit set register + addressOffset: 8 + size: 32 + fields: + - name: OUT_W1TS + description: "GPIO0 ~ 31 output set register. If the value 1 is written to a bit here, the corre- sponding bit in GPIO_OUT_REG will be set to 1. Recommended operation: use this register to set GPIO_OUT_REG." + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: OUT_W1TC + description: GPIO0 ~ 31 output bit clear register + addressOffset: 12 + size: 32 + fields: + - name: OUT_W1TC + description: "GPIO0 ~ 31 output clear register. If the value 1 is written to a bit here, the cor- responding bit in GPIO_OUT_REG will be cleared. Recommended operation: use this register to clear GPIO_OUT_REG." + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: OUT1 + description: GPIO32 ~ 53 output register + addressOffset: 16 + size: 32 + fields: + - name: DATA_ORIG + description: GPIO32 ~ 53 output value in simple GPIO output mode. The values of bit0 ~ bit13 correspond to GPIO32 ~ GPIO45. Bit14 ~ bit21 are invalid. + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: OUT1_W1TS + description: GPIO32 ~ 53 output bit set register + addressOffset: 20 + size: 32 + fields: + - name: OUT1_W1TS + description: "GPIO32 ~ 53 output value set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_OUT1_REG will be set to 1. Recommended operation: use this register to set GPIO_OUT1_REG." + bitOffset: 0 + bitWidth: 22 + access: write-only + - register: + name: OUT1_W1TC + description: GPIO32 ~ 53 output bit clear register + addressOffset: 24 + size: 32 + fields: + - name: OUT1_W1TC + description: "GPIO32 ~ 53 output value clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_OUT1_REG will be cleared. Recommended operation: use this register to clear GPIO_OUT1_REG." + bitOffset: 0 + bitWidth: 22 + access: write-only + - register: + name: SDIO_SELECT + description: GPIO SDIO selection register + addressOffset: 28 + size: 32 + fields: + - name: SDIO_SEL + description: Reserved + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: ENABLE + description: GPIO0 ~ 31 output enable register + addressOffset: 32 + size: 32 + fields: + - name: DATA + description: GPIO0~31 output enable register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ENABLE_W1TS + description: GPIO0 ~ 31 output enable bit set register + addressOffset: 36 + size: 32 + fields: + - name: ENABLE_W1TS + description: "GPIO0 ~ 31 output enable set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_ENABLE_REG will be set to 1. Recommended operation: use this register to set GPIO_ENABLE_REG." + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: ENABLE_W1TC + description: GPIO0 ~ 31 output enable bit clear register + addressOffset: 40 + size: 32 + fields: + - name: ENABLE_W1TC + description: "GPIO0 ~ 31 output enable clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_ENABLE_REG will be cleared. Recommended operation: use this register to clear GPIO_ENABLE_REG." + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: ENABLE1 + description: GPIO32 ~ 53 output enable register + addressOffset: 44 + size: 32 + fields: + - name: DATA + description: GPIO32~53 output enable register. + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: ENABLE1_W1TS + description: GPIO32 ~ 53 output enable bit set register + addressOffset: 48 + size: 32 + fields: + - name: ENABLE1_W1TS + description: "GPIO32 ~ 53 output enable set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_ENABLE1_REG will be set to 1. Recommended operation: use this register to set GPIO_ENABLE1_REG." + bitOffset: 0 + bitWidth: 22 + access: write-only + - register: + name: ENABLE1_W1TC + description: GPIO32 ~ 53 output enable bit clear register + addressOffset: 52 + size: 32 + fields: + - name: ENABLE1_W1TC + description: "GPIO32 ~ 53 output enable clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_ENABLE1_REG will be cleared. Recommended operation: use this register to clear GPIO_ENABLE1_REG." + bitOffset: 0 + bitWidth: 22 + access: write-only + - register: + name: STRAP + description: Bootstrap pin value register + addressOffset: 56 + size: 32 + fields: + - name: STRAPPING + description: "GPIO strapping values: bit4 ~ bit2 correspond to stripping pins GPIO45, GPIO0, and GPIO46 respectively." + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: IN + description: GPIO0 ~ 31 input register + addressOffset: 60 + size: 32 + fields: + - name: DATA_NEXT + description: "GPIO0 ~ 31 input value. Each bit represents a pad input value, 1 for high level and 0 for low level." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: IN1 + description: GPIO32 ~ 53 input register + addressOffset: 64 + size: 32 + fields: + - name: IN_DATA1_NEXT + description: GPIO32 ~ 53 input value. Each bit represents a pad input value. + bitOffset: 0 + bitWidth: 22 + access: read-only + - register: + name: STATUS + description: GPIO0 ~ 31 interrupt status register + addressOffset: 68 + size: 32 + fields: + - name: INTERRUPT + description: GPIO0 ~ 31 interrupt status register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STATUS_W1TS + description: GPIO0 ~ 31 interrupt status bit set register + addressOffset: 72 + size: 32 + fields: + - name: STATUS_W1TS + description: "GPIO0 ~ 31 interrupt status set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_STATUS_INTERRUPT will be set to 1. Recommended operation: use this register to set GPIO_STATUS_INTERRUPT." + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: STATUS_W1TC + description: GPIO0 ~ 31 interrupt status bit clear register + addressOffset: 76 + size: 32 + fields: + - name: STATUS_W1TC + description: "GPIO0 ~ 31 interrupt status clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_STATUS_INTERRUPT will be cleared. Recommended operation: use this register to clear GPIO_STATUS_INTERRUPT." + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: STATUS1 + description: GPIO32 ~ 53 interrupt status register + addressOffset: 80 + size: 32 + fields: + - name: INTERRUPT + description: GPIO32 ~ 53 interrupt status register. + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: STATUS1_W1TS + description: GPIO32 ~ 53 interrupt status bit set register + addressOffset: 84 + size: 32 + fields: + - name: STATUS1_W1TS + description: "GPIO32 ~ 53 interrupt status set register. If the value 1 is written to a bit here, the corresponding bit in GPIO_STATUS1_REG will be set to 1. Recommended operation: use this register to set GPIO_STATUS1_REG." + bitOffset: 0 + bitWidth: 22 + access: write-only + - register: + name: STATUS1_W1TC + description: GPIO32 ~ 53 interrupt status bit clear register + addressOffset: 88 + size: 32 + fields: + - name: STATUS1_W1TC + description: "GPIO32 ~ 53 interrupt status clear register. If the value 1 is written to a bit here, the corresponding bit in GPIO_STATUS1_REG will be cleared. Recommended operation: use this register to clear GPIO_STATUS1_REG." + bitOffset: 0 + bitWidth: 22 + access: write-only + - register: + name: PCPU_INT + description: GPIO0 ~ 31 PRO_CPU interrupt status register + addressOffset: 92 + size: 32 + fields: + - name: PROCPU_INT + description: GPIO0 ~ 31 PRO_CPU interrupt status. This interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high) enable signal (bit13 of GPIO_PINn_REG). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PCPU_NMI_INT + description: GPIO0 ~ 31 PRO_CPU non-maskable interrupt status register + addressOffset: 96 + size: 32 + fields: + - name: PROCPU_NMI_INT + description: GPIO0 ~ 31 PRO_CPU non-maskable interrupt status. This interrupt sta- tus is corresponding to the bit in GPIO_STATUS_REG when assert (high) enable signal (bit 14 of GPIO_PINn_REG). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CPUSDIO_INT + description: GPIO0 ~ 31 CPU SDIO interrupt status register + addressOffset: 100 + size: 32 + fields: + - name: SDIO_INT + description: GPIO0~31 CPU SDIO interrupt status. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PCPU_INT1 + description: GPIO32 ~ 53 PRO_CPU interrupt status register + addressOffset: 104 + size: 32 + fields: + - name: PROCPU1_INT + description: GPIO32 ~ 53 PRO_CPU interrupt status. This interrupt status is corresponding to the bit in GPIO_STATUS1_REG when assert (high) enable signal (bit 13 of GPIO_PINn_REG). + bitOffset: 0 + bitWidth: 22 + access: read-only + - register: + name: PCPU_NMI_INT1 + description: GPIO32 ~ 53 PRO_CPU non-maskable interrupt status register + addressOffset: 108 + size: 32 + fields: + - name: PROCPU_NMI1_INT + description: GPIO32 ~ 53 PRO_CPU non-maskable interrupt status. This interrupt status is corresponding to bit in GPIO_STATUS1_REG when assert (high) enable signal (bit 14 of GPIO_PINn_REG). + bitOffset: 0 + bitWidth: 22 + access: read-only + - register: + name: CPUSDIO_INT1 + description: GPIO32 ~ 53 CPU SDIO interrupt status register + addressOffset: 112 + size: 32 + fields: + - name: SDIO1_INT + description: GPIO32~53 CPU SDIO interrupt status. + bitOffset: 0 + bitWidth: 22 + access: read-only + - register: + dim: 54 + dimIncrement: 4 + name: PIN%s + description: Configuration for GPIO pin %s + addressOffset: 116 + size: 32 + fields: + - name: SYNC2_BYPASS + description: "For the second stage synchronization, GPIO input data can be syn- chronized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: PAD_DRIVER + description: "Pad driver selection. 0: normal output; 1: open drain output.." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SYNC1_BYPASS + description: "For the first stage synchronization, GPIO input data can be synchro- nized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge." + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: INT_TYPE + description: "Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level trigger; 5: high level trigger. (R/W)" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: "GPIO wake-up enable bit, only wakes up the CPU from Light-sleep." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CONFIG + description: Reserved + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: INT_ENA + description: "Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU non-maskable interrupt enabled." + bitOffset: 13 + bitWidth: 5 + access: read-write + - register: + name: STATUS_NEXT + description: GPIO0 ~ 31 interrupt source register + addressOffset: 332 + size: 32 + fields: + - name: STATUS_INTERRUPT_NEXT + description: "Interrupt source signal of GPIO0 ~ 31, could be rising edge interrupt, falling edge interrupt, level sensitive interrupt and any edge interrupt." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: STATUS_NEXT1 + description: GPIO32 ~ 53 interrupt source register + addressOffset: 336 + size: 32 + fields: + - name: STATUS1_INTERRUPT_NEXT + description: Interrupt source signal of GPIO32 ~ 53. + bitOffset: 0 + bitWidth: 22 + access: read-only + - register: + dim: 256 + dimIncrement: 4 + name: FUNC%s_IN_SEL_CFG + description: Peripheral function %s input selection register + addressOffset: 340 + size: 32 + fields: + - name: IN_SEL + description: "Selection control for peripheral input signal m, selects a pad from the 54 GPIO matrix pads to connect this input signal. Or selects 0x38 for a constantly high input or 0x3C for a constantly low input." + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: IN_INV_SEL + description: "Invert the input value. 1: invert enabled; 0: invert disabled." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SEL + description: "Bypass GPIO matrix. 1: route signals via GPIO matrix, 0: connect signals directly to peripheral configured in IO_MUX." + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + dim: 54 + dimIncrement: 4 + name: FUNC%s_OUT_SEL_CFG + description: Peripheral output selection for GPIO %s + addressOffset: 1364 + size: 32 + resetValue: 256 + fields: + - name: OUT_SEL + description: "Selection control for GPIO output n. If a value s (0<=s<256) is written to this field, the peripheral output signal s will be connected to GPIO output n. If a value 256 is written to this field, bit n of GPIO_OUT_REG/GPIO_OUT1_REG and GPIO_ENABLE_REG/GPIO_ENABLE1_REG will be selected as the output value and output enable." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: INV_SEL + description: "0: Do not invert the output value; 1: Invert the output value." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OEN_SEL + description: "0: Use output enable signal from peripheral; 1: Force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OEN_INV_SEL + description: "0: Do not invert the output enable signal; 1: Invert the output enable signal." + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: CLOCK_GATE + description: GPIO clock gating register + addressOffset: 1580 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: "Clock gating enable bit. If set to 1, the clock is free running." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: REG_DATE + description: Version control register + addressOffset: 1788 + size: 32 + resetValue: 26234977 + fields: + - name: DATE + description: Version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: GPIO_SD + description: Sigma-Delta Modulation + groupName: GPIOSD + baseAddress: 1061179136 + addressBlock: + - offset: 0 + size: 44 + usage: registers + registers: + - register: + dim: 8 + dimIncrement: 4 + name: SIGMADELTA%s + description: Duty-cycle configuration register of SDM%s + addressOffset: 0 + size: 32 + resetValue: 65280 + fields: + - name: SD_IN + description: This field is used to configure the duty cycle of sigma delta modulation output. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SD_PRESCALE + description: This field is used to set a divider value to divide APB clock. + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: SIGMADELTA_CG + description: Clock gating configuration register + addressOffset: 32 + size: 32 + fields: + - name: CLK_EN + description: Clock enable bit of configuration registers for sigma delta modulation. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SIGMADELTA_MISC + description: MISC register + addressOffset: 36 + size: 32 + fields: + - name: FUNCTION_CLK_EN + description: Clock enable bit of sigma delta modulation. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI_SWAP + description: Reserved. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SIGMADELTA_VERSION + description: Version control register + addressOffset: 40 + size: 32 + resetValue: 25174624 + fields: + - name: GPIO_SD_DATE + description: Version control register. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: HMAC + description: HMAC (Hash-based Message Authentication Code) Accelerator + groupName: HMAC + baseAddress: 1610866688 + addressBlock: + - offset: 0 + size: 156 + usage: registers + registers: + - register: + name: SET_START + description: HMAC start control register + addressOffset: 64 + size: 32 + fields: + - name: SET_START + description: Set this bit to enable HMAC. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_PARA_PURPOSE + description: HMAC parameter configuration register + addressOffset: 68 + size: 32 + fields: + - name: PURPOSE_SET + description: Set hmac purpose. + bitOffset: 0 + bitWidth: 4 + access: write-only + - register: + name: SET_PARA_KEY + description: HMAC key configuration register + addressOffset: 72 + size: 32 + fields: + - name: KEY_SET + description: Select hmac key. + bitOffset: 0 + bitWidth: 3 + access: write-only + - register: + name: SET_PARA_FINISH + description: HMAC configuration completion register + addressOffset: 76 + size: 32 + fields: + - name: SET_PARA_END + description: Set this bit to finish HMAC configuration. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_MESSAGE_ONE + description: HMAC one message control register + addressOffset: 80 + size: 32 + fields: + - name: SET_TEXT_ONE + description: Call SHA to calculate one message block. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_MESSAGE_ING + description: HMAC message continue register + addressOffset: 84 + size: 32 + fields: + - name: SET_TEXT_ING + description: Set this bit to show there are still some message blocks to be processed. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_MESSAGE_END + description: HMAC message end register + addressOffset: 88 + size: 32 + fields: + - name: SET_TEXT_END + description: Set this bit to start hardware padding. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_RESULT_FINISH + description: HMAC read result completion register + addressOffset: 92 + size: 32 + fields: + - name: SET_RESULT_END + description: Set this bit to end upstream and clear the calculation result. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_INVALIDATE_JTAG + description: Invalidate JTAG result register + addressOffset: 96 + size: 32 + fields: + - name: SET_INVALIDATE_JTAG + description: Set this bit to clear calculation results in JTAG re-enable function under downstream mode. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_INVALIDATE_DS + description: Invalidate digital signature result register + addressOffset: 100 + size: 32 + fields: + - name: SET_INVALIDATE_DS + description: Set this bit to clear calculation results in DS function under downstream mode. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: QUERY_ERROR + description: The matching result between key and purpose user configured + addressOffset: 104 + size: 32 + fields: + - name: QUERY_CHECK + description: "Hmac error status.\n\n0: hmac key and purpose match.\n\n1: error." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: QUERY_BUSY + description: The busy state of HMAC module + addressOffset: 108 + size: 32 + fields: + - name: BUSY_STATE + description: "The state of Hmac.\n\n1'b0: idle.\n\n1'b1: busy." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + dim: 16 + dimIncrement: 4 + name: WR_MESSAGE_%s + description: Message register %s + addressOffset: 128 + size: 32 + fields: + - name: WDATA + description: Store the %sth 32-bit of message. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + dim: 8 + dimIncrement: 4 + name: RD_RESULT_%s + description: Hash result register %s + addressOffset: 192 + size: 32 + fields: + - name: RDATA + description: Read the %sth 32-bit of hash result. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SET_MESSAGE_PAD + description: Software padding register + addressOffset: 240 + size: 32 + fields: + - name: SET_TEXT_PAD + description: Set this bit to let software do padding job. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: ONE_BLOCK + description: One block message register. + addressOffset: 244 + size: 32 + fields: + - name: SET_ONE_BLOCK + description: Set this bit to show no padding is required. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: DATE + description: Version control register + addressOffset: 248 + size: 32 + resetValue: 538510338 + fields: + - name: DATE + description: Version control register. + bitOffset: 0 + bitWidth: 30 + access: read-write + - name: I2C0 + description: I2C (Inter-Integrated Circuit) Controller 0 + groupName: I2C + baseAddress: 1061236736 + addressBlock: + - offset: 0 + size: 168 + usage: registers + interrupt: + - name: I2C_EXT0 + value: 52 + registers: + - register: + name: SCL_LOW_PERIOD + description: Configures the low level width of the SCL clock + addressOffset: 0 + size: 32 + fields: + - name: SCL_LOW_PERIOD + description: "This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 14 + access: read-write + - register: + name: CTR + description: Transmission setting + addressOffset: 4 + size: 32 + resetValue: 2571 + fields: + - name: SDA_FORCE_OUT + description: "0: direct output. 1: open drain output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_FORCE_OUT + description: "0: direct output. 1: open drain output." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SAMPLE_SCL_LEVEL + description: "This register is used to select the sample mode.\n\n1: sample SDA data on the SCL low level.\n\n0: sample SDA data on the SCL high level." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_FULL_ACK_LEVEL + description: This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MS_MODE + description: Set this bit to configure the module as an I2C Master. Clear this bit to configure the module as an I2C Slave. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TRANS_START + description: Set this bit to start sending the data in TX FIFO. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TX_LSB_FIRST + description: "This bit is used to control the sending mode for data needing to be sent.\n\n1: send data from the least significant bit.\n\n0: send data from the most significant bit." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_LSB_FIRST + description: "This bit is used to control the storage mode for received data.\n\n1: receive data from the least significant bit.\n\n0: receive data from the most significant bit." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: Reserved. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ARBITRATION_EN + description: This is the enable bit for I2C bus arbitration function. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FSM_RST + description: This register is used to reset the SCL_FSM. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: REF_ALWAYS_ON + description: This register is used to control the REF_TICK. + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: SR + description: Describe I2C work status + addressOffset: 8 + size: 32 + fields: + - name: RESP_REC + description: "The received ACK value in master mode or slave mode. 0: ACK. 1: NACK." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SLAVE_RW + description: "When in slave mode, 1: master reads from slave. 0: master writes to slave." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TIME_OUT + description: "When the I2C controller takes more than I2C_TIME_OUT clocks to receive a data bit, this field changes to 1." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: ARB_LOST + description: "When the I2C controller loses control of SCL line, this register changes to 1." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BUS_BUSY + description: "1: the I2C bus is busy transferring data. 0: the I2C bus is in idle state." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SLAVE_ADDRESSED + description: "When configured as an I2C Slave, and the address sent by the master is equal to the address of the slave, then this bit will be of high level." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS + description: This field changes to 1 when one byte is transferred. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: RXFIFO_CNT + description: This field represents the amount of data needed to be sent. + bitOffset: 8 + bitWidth: 6 + access: read-only + - name: STRETCH_CAUSE + description: "The cause of stretching SCL low in slave mode. 0: stretching SCL low at the beginning of I2C read data state. 1: stretching SCL low when I2C TX FIFO is empty in slave mode. 2: stretching SCL low when I2C RX FIFO is full in slave mode." + bitOffset: 14 + bitWidth: 2 + access: read-only + - name: TXFIFO_CNT + description: This field stores the amount of received data in RAM. + bitOffset: 18 + bitWidth: 6 + access: read-only + - name: SCL_MAIN_STATE_LAST + description: "This field indicates the states of the I2C module state machine.\n\n0: Idle. 1: Address shift. 2: ACK address. 3: RX data. 4: TX data. 5: Send ACK. 6: Wait ACK" + bitOffset: 24 + bitWidth: 3 + access: read-only + - name: SCL_STATE_LAST + description: "This field indicates the states of the state machine used to produce SCL.\n\n0: Idle. 1: Start. 2: Negative edge. 3: Low. 4: Positive edge. 5: High. 6: Stop" + bitOffset: 28 + bitWidth: 3 + access: read-only + - register: + name: TO + description: Setting time out control for receiving data + addressOffset: 12 + size: 32 + fields: + - name: TIME_OUT_VALUE + description: This register is used to configure the timeout for receiving a data bit in APB clock cycles. + bitOffset: 0 + bitWidth: 24 + access: read-write + - name: TIME_OUT_EN + description: This is the enable bit for time out control. + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: SLAVE_ADDR + description: Local slave address setting + addressOffset: 16 + size: 32 + fields: + - name: SLAVE_ADDR + description: "When configured as an I2C Slave, this field is used to configure the slave address." + bitOffset: 0 + bitWidth: 15 + access: read-write + - name: ADDR_10BIT_EN + description: This field is used to enable the slave 10-bit addressing mode in master mode. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: FIFO_ST + description: FIFO status register + addressOffset: 20 + size: 32 + fields: + - name: RXFIFO_START_ADDR + description: "This is the offset address of the last received data, as described in I2C_NONFIFO_RX_THRES." + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: RXFIFO_END_ADDR + description: "This is the offset address of the last received data, as described in I2C_NONFIFO_RX_THRES. This value refreshes when an I2C_RXFIFO_UDF_INT or I2C_TRANS_COMPLETE_INT interrupt is generated." + bitOffset: 5 + bitWidth: 5 + access: read-only + - name: TXFIFO_START_ADDR + description: "This is the offset address of the first sent data, as described in I2C_NONFIFO_TX_THRES." + bitOffset: 10 + bitWidth: 5 + access: read-only + - name: TXFIFO_END_ADDR + description: "This is the offset address of the last sent data, as described in I2C_NONFIFO_TX_THRES.\n\nThe value refreshes when an I2C_TXFIFO_OVF_INT or I2C_TRANS_COMPLETE_INT interrupt is generated." + bitOffset: 15 + bitWidth: 5 + access: read-only + - name: RX_UPDATE + description: Write 0 or 1 to I2C_RX_UPDATE to update the value of I2C_RXFIFO_END_ADDR and I2C_RXFIFO_START_ADDR. + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: TX_UPDATE + description: Write 0 or 1 to I2C_TX_UPDATE to update the value of I2C_TXFIFO_END_ADDR and I2C_TXFIFO_START_ADDR. + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: SLAVE_RW_POINT + description: The received data in I2C slave mode. + bitOffset: 22 + bitWidth: 8 + access: read-only + - register: + name: FIFO_CONF + description: FIFO configuration register + addressOffset: 24 + size: 32 + resetValue: 89473163 + fields: + - name: RXFIFO_WM_THRHD + description: "The water mark threshold of RX FIFO in non-FIFO mode. When I2C_FIFO_PRT_EN is 1 and RX FIFO counter is bigger than I2C_RXFIFO_WM_THRHD[4:0], I2C_RXFIFO_WM_INT_RAW bit will be valid." + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: TXFIFO_WM_THRHD + description: "The water mark threshold of TX FIFO in non-FIFO mode. When I2C_FIFO_PRT_EN is 1 and TX FIFO counter is smaller than I2C_TXFIFO_WM_THRHD[4:0], I2C_TXFIFO_WM_INT_RAW bit will be valid." + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: NONFIFO_EN + description: Set this bit to enable APB non-FIFO mode. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FIFO_ADDR_CFG_EN + description: "When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RX_FIFO_RST + description: Set this bit to reset RX FIFO. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_FIFO_RST + description: Set this bit to reset TX FIFO. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: NONFIFO_RX_THRES + description: "When I2C receives more than I2C_NONFIFO_RX_THRES bytes of data, it will generate an I2C_RXFIFO_UDF_INT interrupt and update the current offset address of the received data." + bitOffset: 14 + bitWidth: 6 + access: read-write + - name: NONFIFO_TX_THRES + description: "When I2C sends more than I2C_NONFIFO_TX_THRES bytes of data, it will generate an I2C_TXFIFO_OVF_INT interrupt and update the current offset address of the sent data." + bitOffset: 20 + bitWidth: 6 + access: read-write + - name: FIFO_PRT_EN + description: "The control enable bit of FIFO pointer in non-FIFO mode. This bit controls the valid bits and the interrupts of TX/RX FIFO overflow, underflow, full and empty." + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: DATA + description: RX FIFO read data + addressOffset: 28 + size: 32 + fields: + - name: FIFO_RDATA + description: The value of RX FIFO read data. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 32 + size: 32 + fields: + - name: RXFIFO_WM_INT_RAW + description: The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_WM_INT_RAW + description: The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_RAW + description: The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: END_DETECT_INT_RAW + description: The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS_DONE_INT_RAW + description: The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_RAW + description: The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: MST_TXFIFO_UDF_INT_RAW + description: The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_RAW + description: The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_RAW + description: The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TRANS_START_INT_RAW + description: The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: NACK_INT_RAW + description: The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: TXFIFO_OVF_INT_RAW + description: The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: RXFIFO_UDF_INT_RAW + description: The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SCL_ST_TO_INT_RAW + description: The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SCL_MAIN_ST_TO_INT_RAW + description: The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DET_START_INT_RAW + description: The raw interrupt bit for I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLAVE_STRETCH_INT_RAW + description: The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 36 + size: 32 + fields: + - name: RXFIFO_WM_INT_CLR + description: Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TXFIFO_WM_INT_CLR + description: Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RXFIFO_OVF_INT_CLR + description: Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: END_DETECT_INT_CLR + description: Set this bit to clear the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: BYTE_TRANS_DONE_INT_CLR + description: Set this bit to clear the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: ARBITRATION_LOST_INT_CLR + description: Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: MST_TXFIFO_UDF_INT_CLR + description: Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TRANS_COMPLETE_INT_CLR + description: Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: TIME_OUT_INT_CLR + description: Set this bit to clear the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: TRANS_START_INT_CLR + description: Set this bit to clear the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: NACK_INT_CLR + description: Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: TXFIFO_OVF_INT_CLR + description: Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: RXFIFO_UDF_INT_CLR + description: Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: SCL_ST_TO_INT_CLR + description: Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SCL_MAIN_ST_TO_INT_CLR + description: Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: DET_START_INT_CLR + description: Set this bit to clear I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: SLAVE_STRETCH_INT_CLR + description: Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 40 + size: 32 + fields: + - name: RXFIFO_WM_INT_ENA + description: The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_WM_INT_ENA + description: The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_ENA + description: The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: END_DETECT_INT_ENA + description: The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: BYTE_TRANS_DONE_INT_ENA + description: The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ARBITRATION_LOST_INT_ENA + description: The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: MST_TXFIFO_UDF_INT_ENA + description: The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TRANS_COMPLETE_INT_ENA + description: The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TIME_OUT_INT_ENA + description: The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TRANS_START_INT_ENA + description: The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: NACK_INT_ENA + description: The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TXFIFO_OVF_INT_ENA + description: The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RXFIFO_UDF_INT_ENA + description: The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SCL_ST_TO_INT_ENA + description: The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SCL_MAIN_ST_TO_INT_ENA + description: The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DET_START_INT_ENA + description: The raw interrupt bit for I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLAVE_STRETCH_INT_ENA + description: The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: INT_STATUS + description: Status of captured I2C communication events + addressOffset: 44 + size: 32 + fields: + - name: RXFIFO_WM_INT_ST + description: The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_WM_INT_ST + description: The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_ST + description: The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: END_DETECT_INT_ST + description: The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS_DONE_INT_ST + description: The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_ST + description: The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: MST_TXFIFO_UDF_INT_ST + description: The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_ST + description: The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_ST + description: The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TRANS_START_INT_ST + description: The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: NACK_INT_ST + description: The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: TXFIFO_OVF_INT_ST + description: The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: RXFIFO_UDF_INT_ST + description: The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SCL_ST_TO_INT_ST + description: The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SCL_MAIN_ST_TO_INT_ST + description: The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DET_START_INT_ST + description: The masked interrupt status bit for I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLAVE_STRETCH_INT_ST + description: The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: SDA_HOLD + description: Configures the hold time after a negative SCL edge + addressOffset: 48 + size: 32 + fields: + - name: TIME + description: "This register is used to configure the interval between changing the SDA output level and the falling edge of SCL, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: SDA_SAMPLE + description: Configures the sample time after a positive SCL edge + addressOffset: 52 + size: 32 + fields: + - name: TIME + description: "This register is used to configure the interval between the rising edge of SCL and the level sampling time of SDA, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: SCL_HIGH_PERIOD + description: Configures the high level width of the SCL clock + addressOffset: 56 + size: 32 + fields: + - name: SCL_HIGH_PERIOD + description: "This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: SCL_WAIT_HIGH_PERIOD + description: "This register is used to configure for the SCL_FSM's waiting period for SCL to go high in master mode, in I2C module clock cycles." + bitOffset: 14 + bitWidth: 14 + access: read-write + - register: + name: SCL_START_HOLD + description: Configures the interval between pulling SDA low and pulling SCL low when the master generates a START condition + addressOffset: 64 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure interval between pulling SDA low and pulling SCL low when the master generates a START condition, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: SCL_RSTART_SETUP + description: Configures the interval between the positive edge of SCL and the negative edge of SDA + addressOffset: 68 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the interval between the positive edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: SCL_STOP_HOLD + description: Configures the delay after the SCL clock edge for a stop condition + addressOffset: 72 + size: 32 + fields: + - name: TIME + description: "This register is used to configure the delay after the STOP condition, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 14 + access: read-write + - register: + name: SCL_STOP_SETUP + description: Configures the delay between the SDA and SCL positive edge for a stop condition + addressOffset: 76 + size: 32 + fields: + - name: TIME + description: "This register is used to configure the time between the positive edge of SCL and the positive edge of SDA, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: SCL_FILTER_CFG + description: SCL filter configuration register + addressOffset: 80 + size: 32 + resetValue: 16 + fields: + - name: SCL_FILTER_THRES + description: "When a pulse on the SCL input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: SCL_FILTER_EN + description: This is the filter enable bit for SCL. + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: SDA_FILTER_CFG + description: SDA filter configuration register + addressOffset: 84 + size: 32 + resetValue: 16 + fields: + - name: SDA_FILTER_THRES + description: "When a pulse on the SDA input has smaller width than this register value in I2C module clock cycles, the I2C controller will ignore that pulse." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: SDA_FILTER_EN + description: This is the filter enable bit for SDA. + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + dim: 16 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" + name: COMD%s + description: I2C command register %s + addressOffset: 88 + size: 32 + fields: + - name: COMMAND + description: "This is the content of command 0. It consists of three parts:\n\nop_code is the command, 0: RSTART. 1: WRITE. 2: READ. 3: STOP. 4: END.\n\nbyte_num represents the number of bytes that need to be sent or received.\n\nack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more information." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND_DONE + description: "When command 0 is done in I2C Master mode, this bit changes to high level." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SCL_ST_TIME_OUT + description: SCL status time out register + addressOffset: 152 + size: 32 + resetValue: 256 + fields: + - name: SCL_ST_TO + description: The threshold value of SCL_FSM state unchanged period. + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: SCL_MAIN_ST_TIME_OUT + description: SCL main status time out register + addressOffset: 156 + size: 32 + resetValue: 256 + fields: + - name: SCL_MAIN_ST_TO + description: The threshold value of SCL_MAIN_FSM state unchanged period. + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: SCL_SP_CONF + description: Power configuration register + addressOffset: 160 + size: 32 + fields: + - name: SCL_RST_SLV_EN + description: "When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to I2C_SCL_RST_SLV_NUM[4:0]." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_RST_SLV_NUM + description: Configure the pulses of SCL generated in I2C master mode. Valid when I2C_SCL_RST_SLV_EN is 1. + bitOffset: 1 + bitWidth: 5 + access: read-write + - name: SCL_PD_EN + description: "The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set I2C_SCL_FORCE_OUT and I2C_SCL_PD_EN to 1 to stretch SCL low." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SDA_PD_EN + description: "The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set I2C_SDA_FORCE_OUT and I2C_SDA_PD_EN to 1 to stretch SDA low." + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: SCL_STRETCH_CONF + description: Set SCL stretch of I2C slave + addressOffset: 164 + size: 32 + fields: + - name: STRETCH_PROTECT_NUM + description: Configure the period of I2C slave stretching SCL line. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: SLAVE_SCL_STRETCH_EN + description: "The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL output line will be stretched low when I2C_SLAVE_SCL_STRETCH_EN is 1 and stretch event happens. The stretch cause can be seen in I2C_STRETCH_CAUSE." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLAVE_SCL_STRETCH_CLR + description: Set this bit to clear the I2C slave SCL stretch function. + bitOffset: 11 + bitWidth: 1 + access: write-only + - register: + name: DATE + description: Version control register + addressOffset: 248 + size: 32 + resetValue: 419766272 + fields: + - name: DATE + description: This is the the version control register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: I2C1 + description: I2C (Inter-Integrated Circuit) Controller 1 + baseAddress: 1061318656 + interrupt: + - name: I2C_EXT1 + value: 53 + derivedFrom: I2C0 + - name: I2S0 + description: I2S (Inter-IC Sound) Controller 0 + groupName: I2S + baseAddress: 1061220352 + addressBlock: + - offset: 0 + size: 136 + usage: registers + interrupt: + - name: I2S0 + value: 35 + - name: I2S1 + value: 36 + registers: + - register: + name: CONF + description: I2S configuration register + addressOffset: 8 + size: 32 + resetValue: 787200 + fields: + - name: TX_RESET + description: Set this bit to reset transmitter. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: RX_RESET + description: Set this bit to reset receiver. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TX_FIFO_RESET + description: Set this bit to reset TX FIFO. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: RX_FIFO_RESET + description: Set this bit to reset RX FIFO. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TX_START + description: Set this bit to start transmitting data. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_START + description: Set this bit to start receiving data. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TX_SLAVE_MOD + description: Set this bit to enable slave transmitter mode. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_SLAVE_MOD + description: Set this bit to enable slave receiver mode. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TX_RIGHT_FIRST + description: Set this bit to transmit right channel data first. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RX_RIGHT_FIRST + description: Set this bit to receive right channel data first. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TX_MSB_SHIFT + description: Set this bit to enable transmitter in Phillips standard mode. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: RX_MSB_SHIFT + description: Set this bit to enable receiver in Phillips standard mode. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_SHORT_SYNC + description: Set this bit to enable transmitter in PCM standard mode. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RX_SHORT_SYNC + description: Set this bit to enable receiver in PCM standard mode. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_MONO + description: Set this bit to enable transmitter in mono mode. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RX_MONO + description: Set this bit to enable receiver in mono mode. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TX_MSB_RIGHT + description: Set this bit to place right channel data at the MSB in TX FIFO. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RX_MSB_RIGHT + description: Set this bit to place right channel data at the MSB in RX FIFO. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: TX_LSB_FIRST_DMA + description: "1:the data in DMA/APB transform from low bits. 0:the data from DMA/APB transform from high bits." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RX_LSB_FIRST_DMA + description: "1:the data in DMA/APB transform from low bits. 0:the data from DMA/APB transform from high bits." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SIG_LOOPBACK + description: Enable signal loopback mode with transmitter module and receiver module sharing the same WS and BCK signals. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TX_FIFO_RESET_ST + description: "I2S TX FIFO reset status. 1: I2S_TX_FIFO_RESET is not completed. 0: I2S_TX_FIFO_RESET is completed." + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: RX_FIFO_RESET_ST + description: "I2S RX FIFO reset status. 1: I2S_RX_FIFO_RESET is not completed. 0: I2S_RX_FIFO_RESET is completed." + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: TX_RESET_ST + description: "I2S TX reset status. 1: I2S_TX_RESET is not completed. 0: I2S_TX_RESET is completed." + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: TX_DMA_EQUAL + description: "1: Data in left channel is equal to data in right channel. 0: Data in left channel is not equal to data in right channel." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: RX_DMA_EQUAL + description: "1: Data in left channel is equal to data in right channel. 0: Data in left channel is not equal to data in right channel." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PRE_REQ_EN + description: Set this bit to enable I2S to prepare data earlier. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TX_BIG_ENDIAN + description: I2S TX byte endianness. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RX_BIG_ENDIAN + description: I2S RX byte endianness. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: RX_RESET_ST + description: "I2S RX reset status. 1: I2S_RX_RESET is not completed. 0: I2S_RX_RESET is completed." + bitOffset: 29 + bitWidth: 1 + access: read-only + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 12 + size: 32 + fields: + - name: RX_TAKE_DATA_INT_RAW + description: The raw interrupt status bit for I2S_RX_TAKE_DATA_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_PUT_DATA_INT_RAW + description: The raw interrupt status bit for I2S_TX_PUT_DATA_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_WFULL_INT_RAW + description: The raw interrupt status bit for I2S_RX_WFULL_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: RX_REMPTY_INT_RAW + description: The raw interrupt status bit for I2S_RX_REMPTY_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TX_WFULL_INT_RAW + description: The raw interrupt status bit for I2S_TX_WFULL_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TX_REMPTY_INT_RAW + description: The raw interrupt status bit for I2S_TX_REMPTY_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_RAW + description: The raw interrupt status bit for I2S_RX_HUNG_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_RAW + description: The raw interrupt status bit for I2S_TX_HUNG_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IN_DONE_INT_RAW + description: The raw interrupt status bit for I2S_IN_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: IN_SUC_EOF_INT_RAW + description: The raw interrupt status bit for I2S_IN_SUC_EOF_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: IN_ERR_EOF_INT_RAW + description: Reserved. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: OUT_DONE_INT_RAW + description: The raw interrupt status bit for I2S_OUT_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: OUT_EOF_INT_RAW + description: The raw interrupt status bit for I2S_OUT_EOF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: IN_DSCR_ERR_INT_RAW + description: The raw interrupt status bit for I2S_IN_DSCR_ERR_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: OUT_DSCR_ERR_INT_RAW + description: The raw interrupt status bit for I2S_OUT_DSCR_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: IN_DSCR_EMPTY_INT_RAW + description: The raw interrupt status bit for I2S_IN_DSCR_EMPTY_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: OUT_TOTAL_EOF_INT_RAW + description: The raw interrupt status bit for I2S_OUT_TOTAL_EOF_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: V_SYNC_INT_RAW + description: The raw interrupt status bit for I2S_V_SYNC_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 16 + size: 32 + fields: + - name: RX_TAKE_DATA_INT_ST + description: The masked interrupt status bit for I2S_RX_TAKE_DATA_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_PUT_DATA_INT_ST + description: The masked interrupt status bit for I2S_TX_PUT_DATA_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_WFULL_INT_ST + description: The masked interrupt status bit for I2S_RX_WFULL_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: RX_REMPTY_INT_ST + description: The masked interrupt status bit for I2S_RX_REMPTY_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TX_WFULL_INT_ST + description: The masked interrupt status bit for I2S_TX_WFULL_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TX_REMPTY_INT_ST + description: The masked interrupt status bit for I2S_TX_REMPTY_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_ST + description: The masked interrupt status bit for I2S_RX_HUNG_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_ST + description: The masked interrupt status bit for I2S_TX_HUNG_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IN_DONE_INT_ST + description: The masked interrupt status bit for I2S_IN_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: IN_SUC_EOF_INT_ST + description: The masked interrupt status bit for I2S_IN_SUC_EOF_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: IN_ERR_EOF_INT_ST + description: Reserved. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: OUT_DONE_INT_ST + description: The masked interrupt status bit for I2S_OUT_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: OUT_EOF_INT_ST + description: The masked interrupt status bit for I2S_OUT_EOF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: IN_DSCR_ERR_INT_ST + description: The masked interrupt status bit for I2S_IN_DSCR_ERR_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: OUT_DSCR_ERR_INT_ST + description: The masked interrupt status bit for I2S_OUT_DSCR_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: IN_DSCR_EMPTY_INT_ST + description: The masked interrupt status bit for I2S_IN_DSCR_EMPTY_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: OUT_TOTAL_EOF_INT_ST + description: The masked interrupt status bit for I2S_OUT_TOTAL_EOF_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: V_SYNC_INT_ST + description: The masked interrupt status bit for I2S_V_SYNC_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 20 + size: 32 + fields: + - name: RX_TAKE_DATA_INT_ENA + description: The interrupt enable bit for I2S_RX_TAKE_DATA_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_PUT_DATA_INT_ENA + description: The interrupt enable bit for I2S_TX_PUT_DATA_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_WFULL_INT_ENA + description: The interrupt enable bit for I2S_RX_WFULL_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_REMPTY_INT_ENA + description: The interrupt enable bit for I2S_RX_REMPTY_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_WFULL_INT_ENA + description: The interrupt enable bit for I2S_TX_WFULL_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TX_REMPTY_INT_ENA + description: The interrupt enable bit for I2S_TX_REMPTY_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RX_HUNG_INT_ENA + description: The interrupt enable bit for I2S_RX_HUNG_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_HUNG_INT_ENA + description: The interrupt enable bit for I2S_TX_HUNG_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IN_DONE_INT_ENA + description: The interrupt enable bit for I2S_IN_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF_INT_ENA + description: The interrupt enable bit for I2S_IN_SUC_EOF_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF_INT_ENA + description: Reserved. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OUT_DONE_INT_ENA + description: The interrupt enable bit for I2S_OUT_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: OUT_EOF_INT_ENA + description: The interrupt enable bit for I2S_OUT_EOF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR_INT_ENA + description: The interrupt enable bit for I2S_IN_DSCR_ERR_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR_INT_ENA + description: The interrupt enable bit for I2S_OUT_DSCR_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY_INT_ENA + description: The interrupt enable bit for I2S_IN_DSCR_EMPTY_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF_INT_ENA + description: The interrupt enable bit for I2S_OUT_TOTAL_EOF_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: V_SYNC_INT_ENA + description: The interrupt enable bit for I2S_V_SYNC_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 24 + size: 32 + fields: + - name: TAKE_DATA_INT_CLR + description: Set this bit to clear I2S_RX_TAKE_DATA_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: PUT_DATA_INT_CLR + description: Set this bit to clear I2S_TX_PUT_DATA_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_WFULL_INT_CLR + description: Set this bit to clear I2S_RX_WFULL_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: RX_REMPTY_INT_CLR + description: Set this bit to clear I2S_RX_REMPTY_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TX_WFULL_INT_CLR + description: Set this bit to clear I2S_TX_WFULL_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: TX_REMPTY_INT_CLR + description: Set this bit to clear I2S_TX_REMPTY_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: RX_HUNG_INT_CLR + description: Set this bit to clear I2S_RX_HUNG_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TX_HUNG_INT_CLR + description: Set this bit to clear I2S_TX_HUNG_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: IN_DONE_INT_CLR + description: Set this bit to clear I2S_IN_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: IN_SUC_EOF_INT_CLR + description: Set this bit to clear I2S_IN_SUC_EOF_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: IN_ERR_EOF_INT_CLR + description: Reserved. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: OUT_DONE_INT_CLR + description: Set this bit to clear I2S_OUT_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: OUT_EOF_INT_CLR + description: Set this bit to clear I2S_OUT_EOF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: IN_DSCR_ERR_INT_CLR + description: Set this bit to clear I2S_IN_DSCR_ERR_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: OUT_DSCR_ERR_INT_CLR + description: Set this bit to clear I2S_OUT_DSCR_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: IN_DSCR_EMPTY_INT_CLR + description: Set this bit to clear I2S_IN_DSCR_EMPTY_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: OUT_TOTAL_EOF_INT_CLR + description: Set this bit to clear I2S_OUT_TOTAL_EOF_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: V_SYNC_INT_CLR + description: Set this bit to clear I2S_V_SYNC_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - register: + name: TIMING + description: I2S timing register + addressOffset: 28 + size: 32 + fields: + - name: TX_BCK_IN_DELAY + description: "Number of delay cycles for BCK signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: TX_WS_IN_DELAY + description: "Number of delay cycles for WS signal into the transmitter based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: RX_BCK_IN_DELAY + description: "Number of delay cycles for BCK signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: RX_WS_IN_DELAY + description: "Number of delay cycles for WS signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: RX_SD_IN_DELAY + description: "Number of delay cycles for SD signal into the receiver based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles." + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: TX_BCK_OUT_DELAY + description: "Number of delay cycles for BCK signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: TX_WS_OUT_DELAY + description: "Number of delay cycles for WS signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles." + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: TX_SD_OUT_DELAY + description: "Number of delay cycles for SD signal out of the transmitter based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles." + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: RX_WS_OUT_DELAY + description: "Number of delay cycles for WS signal out of the receiver based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: RX_BCK_OUT_DELAY + description: "Number of delay cycles for BCK signal out of the receiver based on I2S0_CLK. 0: delayed by 0 cycle. 1: delayed by 1 cycle. 2: delayed by 2 cycles. 3: delayed by 3 cycles." + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: TX_DSYNC_SW + description: "Set this bit to synchronize signals into the transmitter by two flip-flop synchronizer. 0: the signals will be firstly clocked by rising clock edge , then clocked by falling clock edge. 1: the signals will be firstly clocked by falling clock edge, then clocked by rising clock edge." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: RX_DSYNC_SW + description: "Set this bit to synchronize signals into the receiver by two flip-flop synchronizer. 0: the signals will be clocked by rising clock edge firstly, then clocked by falling clock edge. 1: the signals will be clocked by falling clock edge firstly, then clocked by rising clock edge." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: DATA_ENABLE_DELAY + description: "Number of delay cycles for data valid flag based on I2S0_CLK. 0: delayed by 1.5 cycles. 1: delayed by 2.5 cycles. 2: delayed by 3.5 cycles. 3: delayed by 4.5 cycles." + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: TX_BCK_IN_INV + description: Set this bit to invert BCK signal input to the slave transmitter. + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: FIFO_CONF + description: I2S FIFO configuration register + addressOffset: 32 + size: 32 + resetValue: 6176 + fields: + - name: RX_DATA_NUM + description: "I2S_RX_TAKE_DATA_INT is triggered when the left and right channel data number in RX FIFO is larger than the value of I2S_RX_DATA_NUM[5:0]. (RX FIFO is almost full threshold.)" + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: TX_DATA_NUM + description: "I2S_TX_PUT_DATA_INT is triggered when the left and right channel data number in TX FIFO is smaller than the value of I2S_TX_DATA_NUM[5:0]. (TX FIFO is almost empty threshold.)" + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: DSCR_EN + description: Set this bit to enable I2S DMA mode. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_FIFO_MOD + description: Transmitter FIFO mode configuration bits + bitOffset: 13 + bitWidth: 3 + access: read-write + - name: RX_FIFO_MOD + description: Receiver FIFO mode configuration bits + bitOffset: 16 + bitWidth: 3 + access: read-write + - name: TX_FIFO_MOD_FORCE_EN + description: The bit should always be set to 1 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RX_FIFO_MOD_FORCE_EN + description: The bit should always be set to 1 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: RX_FIFO_SYNC + description: force write back rx data to memory + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: RX_24MSB_EN + description: "Only useful in rx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TX_24MSB_EN + description: "Only useful in tx 24bit mode. 1: the high 24 bits are effective in i2s fifo 0: the low 24 bits are effective in i2s fifo" + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: RXEOF_NUM + description: I2S DMA RX EOF data length + addressOffset: 36 + size: 32 + resetValue: 64 + fields: + - name: RX_EOF_NUM + description: The length of data to be received. It will trigger I2S_IN_SUC_EOF_INT. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CONF_SIGLE_DATA + description: Constant single channel data + addressOffset: 40 + size: 32 + fields: + - name: SIGLE_DATA + description: The right channel or left channel transmits constant value stored in this register according to I2S_TX_CHAN_MOD and I2S_TX_MSB_RIGHT. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CONF_CHAN + description: I2S channel configuration register + addressOffset: 44 + size: 32 + fields: + - name: TX_CHAN_MOD + description: I2S transmitter channel mode configuration bits. + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: RX_CHAN_MOD + description: I2S receiver channel mode configuration bits. + bitOffset: 3 + bitWidth: 2 + access: read-write + - register: + name: OUT_LINK + description: I2S DMA TX configuration register + addressOffset: 48 + size: 32 + fields: + - name: OUTLINK_ADDR + description: The address of first outlink descriptor. + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: OUTLINK_STOP + description: Set this bit to stop outlink descriptor. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: OUTLINK_START + description: Set this bit to start outlink descriptor. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: OUTLINK_RESTART + description: Set this bit to restart outlink descriptor. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: OUTLINK_PARK + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: IN_LINK + description: I2S DMA RX configuration register + addressOffset: 52 + size: 32 + fields: + - name: INLINK_ADDR + description: The address of first inlink descriptor. + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: INLINK_STOP + description: Set this bit to stop inlink descriptor. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: INLINK_START + description: Set this bit to start inlink descriptor. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: INLINK_RESTART + description: Set this bit to restart inlink descriptor. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: INLINK_PARK + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: OUT_EOF_DES_ADDR + description: Address of outlink descriptor that produces EOF + addressOffset: 56 + size: 32 + fields: + - name: OUT_EOF_DES_ADDR + description: The address of outlink descriptor that produces EOF. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_EOF_DES_ADDR + description: Address of inlink descriptor that produces EOF + addressOffset: 60 + size: 32 + fields: + - name: IN_SUC_EOF_DES_ADDR + description: The address of inlink descriptor that produces EOF. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_EOF_BFR_DES_ADDR + description: Address of buffer relative to the outlink descriptor that produces EOF + addressOffset: 64 + size: 32 + fields: + - name: OUT_EOF_BFR_DES_ADDR + description: The address of buffer relative to the outlink descriptor that produces EOF. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INLINK_DSCR + description: Address of current inlink descriptor + addressOffset: 72 + size: 32 + fields: + - name: INLINK_DSCR + description: The address of current inlink descriptor. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INLINK_DSCR_BF0 + description: Address of next inlink descriptor + addressOffset: 76 + size: 32 + fields: + - name: INLINK_DSCR_BF0 + description: The address of next inlink descriptor. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INLINK_DSCR_BF1 + description: Address of next inlink data buffer + addressOffset: 80 + size: 32 + fields: + - name: INLINK_DSCR_BF1 + description: The address of next inlink data buffer. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUTLINK_DSCR + description: Address of current outlink descriptor + addressOffset: 84 + size: 32 + fields: + - name: OUTLINK_DSCR + description: The address of current outlink descriptor. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUTLINK_DSCR_BF0 + description: Address of next outlink descriptor + addressOffset: 88 + size: 32 + fields: + - name: OUTLINK_DSCR_BF0 + description: The address of next outlink descriptor. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUTLINK_DSCR_BF1 + description: Address of next outlink data buffer + addressOffset: 92 + size: 32 + fields: + - name: OUTLINK_DSCR_BF1 + description: The address of next outlink data buffer. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: LC_CONF + description: I2S DMA configuration register + addressOffset: 96 + size: 32 + resetValue: 256 + fields: + - name: IN_RST + description: Set this bit to reset in-DMA FSM. Set this bit before the DMA configuration. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_RST + description: Set this bit to reset out-DMA FSM. Set this bit before the DMA configuration. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AHBM_FIFO_RST + description: Set this bit to reset AHB interface cmdFIFO of DMA. Set this bit before the DMA configuration. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: AHBM_RST + description: Set this bit to reset AHB interface of DMA. Set this bit before the DMA configuration. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUT_LOOP_TEST + description: Set this bit to loop test inlink. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IN_LOOP_TEST + description: Set this bit to loop test outlink. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUT_AUTO_WRBACK + description: Set this bit to enable outlink-written-back automatically when out buffer is transmitted done. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUT_NO_RESTART_CLR + description: Reserved. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_EOF_MODE + description: "DMA out EOF flag generation mode. 1: When DMA has popped all data from the FIFO. 0: When AHB has pushed all data to the FIFO." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: OUTDSCR_BURST_EN + description: "DMA outlink descriptor transfer mode configuration bit. 1: Prepare outlink descriptor with burst mode. 0: Prepare outlink descriptor with byte mode." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: INDSCR_BURST_EN + description: "DMA inlink descriptor transfer mode configuration bit. 1: Prepare inlink descriptor with burst mode. 0: Prepare inlink descriptor with byte mode." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OUT_DATA_BURST_EN + description: "Transmitter data transfer mode configuration bit. 1: Prepare out data with burst mode. 0: Prepare out data with byte mode." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CHECK_OWNER + description: Set this bit to enable check owner bit by hardware. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: MEM_TRANS_EN + description: Reserved. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: EXT_MEM_BK_SIZE + description: "DMA access external memory block size. 0: 16 bytes. 1: 32 bytes. 2: 64 bytes. 3: reserved." + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: OUTFIFO_PUSH + description: APB out FIFO mode register + addressOffset: 100 + size: 32 + fields: + - name: OUTFIFO_WDATA + description: APB out FIFO write data. + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: OUTFIFO_PUSH + description: APB out FIFO push. + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: INFIFO_POP + description: APB in FIFO mode register + addressOffset: 104 + size: 32 + fields: + - name: INFIFO_RDATA + description: APB in FIFO read data. + bitOffset: 0 + bitWidth: 12 + access: read-only + - name: INFIFO_POP + description: APB in FIFO pop. + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: LC_STATE0 + description: I2S DMA TX status + addressOffset: 108 + size: 32 + fields: + - name: OUTLINK_DSCR_ADDR + description: I2S DMA out descriptor address. + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: OUT_DSCR_STATE + description: I2S DMA out descriptor state. + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: OUT_STATE + description: I2S DMA out data state. + bitOffset: 20 + bitWidth: 3 + access: read-only + - name: OUTFIFO_CNT + description: The remains of I2S DMA outfifo data. + bitOffset: 23 + bitWidth: 7 + access: read-only + - name: OUT_FULL + description: I2S DMA outfifo is full. + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: OUT_EMPTY + description: I2S DMA outfifo is empty. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: LC_STATE1 + description: I2S DMA RX status + addressOffset: 112 + size: 32 + fields: + - name: INLINK_DSCR_ADDR + description: I2S DMA in descriptor address. + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: IN_DSCR_STATE + description: I2S DMA in descriptor state. + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: IN_STATE + description: I2S DMA in data state. + bitOffset: 20 + bitWidth: 3 + access: read-only + - name: INFIFO_CNT_DEBUG + description: The remains of I2S DMA infifo data. + bitOffset: 23 + bitWidth: 7 + access: read-only + - name: IN_FULL + description: I2S DMA infifo is full. + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: IN_EMPTY + description: I2S DMA infifo is empty. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: LC_HUNG_CONF + description: I2S Hung configuration register + addressOffset: 116 + size: 32 + resetValue: 2064 + fields: + - name: LC_FIFO_TIMEOUT + description: I2S_TX_HUNG_INT interrupt or I2S_RX_HUNG_INT interrupt will be triggered when FIFO hung counter is equal to this value. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: LC_FIFO_TIMEOUT_SHIFT + description: The bits are used to set the tick counter threshold. The tick counter is clocked by APB_CLK. The tick counter threshold is 88000/2^I2S_LC_FIFO_TIMEOUT_SHIFT. The tick counter is reset when it reaches the threshold. + bitOffset: 8 + bitWidth: 3 + access: read-write + - name: LC_FIFO_TIMEOUT_ENA + description: The enable bit for FIFO timeout. + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: CONF1 + description: I2S configuration register 1 + addressOffset: 160 + size: 32 + resetValue: 137 + fields: + - name: TX_PCM_CONF + description: "Compress/Decompress module configuration bits. 0: decompress transmitted data 1:compress transmitted data" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: TX_PCM_BYPASS + description: Set this bit to bypass Compress/Decompress module for transmitted data. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_PCM_CONF + description: "Compress/Decompress module configuration bits. 0: decompress received data 1:compress received data" + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: RX_PCM_BYPASS + description: Set this bit to bypass Compress/Decompress module for received data. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TX_STOP_EN + description: Set this bit to stop the output of BCK signal and WS signal when TX FIFO is empty. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TX_ZEROS_RM_EN + description: Reserved. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: PD_CONF + description: I2S power-down configuration register + addressOffset: 164 + size: 32 + resetValue: 42 + fields: + - name: FIFO_FORCE_PD + description: Force FIFO power-down. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FIFO_FORCE_PU + description: Force FIFO power-up. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PLC_MEM_FORCE_PD + description: Force I2S memory power-down. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PLC_MEM_FORCE_PU + description: Force I2S memory power-up. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DMA_RAM_FORCE_PD + description: Force DMA FIFO power-down. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DMA_RAM_FORCE_PU + description: Force DMA FIFO power-up. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DMA_RAM_CLK_FO + description: Set this bit to force on DMA RAM clock. + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: CONF2 + description: I2S configuration register 2 + addressOffset: 168 + size: 32 + fields: + - name: CAMERA_EN + description: Set this bit to enable camera mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LCD_TX_WRX2_EN + description: LCD WR double for one datum. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: LCD_TX_SDX2_EN + description: Set this bit to duplicate data pairs (Frame Form 2) in LCD mode. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DATA_ENABLE_TEST_EN + description: for debug camera mode enable + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DATA_ENABLE + description: for debug camera mode enable + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: LCD_EN + description: Set this bit to enable LCD mode. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: EXT_ADC_START_EN + description: Set this bit to enable the function that ADC mode is triggered by external signal. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: INTER_VALID_EN + description: "Set this bit to enable camera VGA reducing-resolution mode: only receive two consecutive cycle data in four consecutive clocks." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CAM_SYNC_FIFO_RESET + description: Set this bit to reset FIFO in camera mode. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CAM_CLK_LOOPBACK + description: Set this bit to loopback PCLK from I2S0I_WS_out. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: VSYNC_FILTER_EN + description: Set this bit to enable I2S VSYNC filter function. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: VSYNC_FILTER_THRES + description: Configure the I2S VSYNC filter threshold value. + bitOffset: 11 + bitWidth: 3 + access: read-write + - register: + name: CLKM_CONF + description: I2S module clock configuration register + addressOffset: 172 + size: 32 + resetValue: 4 + fields: + - name: CLKM_DIV_NUM + description: Integral I2S clock divider value. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CLKM_DIV_B + description: Fractional clock divider numerator value. + bitOffset: 8 + bitWidth: 6 + access: read-write + - name: CLKM_DIV_A + description: Fractional clock divider denominator value. + bitOffset: 14 + bitWidth: 6 + access: read-write + - name: CLK_EN + description: Set this bit to enable clock gate. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CLK_SEL + description: "Set this bit to select I2S module clock source. 0: No clock. 1: APLL_CLK. 2: PLL_160M_CLK. 3: No clock." + bitOffset: 21 + bitWidth: 2 + access: read-write + - register: + name: SAMPLE_RATE_CONF + description: I2S sample rate register + addressOffset: 176 + size: 32 + resetValue: 4260230 + fields: + - name: TX_BCK_DIV_NUM + description: Bit clock configuration bits in transmitter mode. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: RX_BCK_DIV_NUM + description: Bit clock configuration bits in receiver mode. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: TX_BITS_MOD + description: "Set the bits to configure bit length of I2S transmitter channel, the value of which can only be 8, 16, 24 and 32." + bitOffset: 12 + bitWidth: 6 + access: read-write + - name: RX_BITS_MOD + description: "Set the bits to configure bit length of I2S receiver channel, the value of which can only be 8, 16, 24 and 32." + bitOffset: 18 + bitWidth: 6 + access: read-write + - register: + name: STATE + description: I2S TX status register + addressOffset: 188 + size: 32 + resetValue: 1 + fields: + - name: TX_IDLE + description: "1: I2S TX is in idle state. 0: I2S TX is at work." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: Version control register + addressOffset: 252 + size: 32 + resetValue: 419767552 + fields: + - name: DATE + description: Version control register + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: INTERRUPT_CORE0 + description: Interrupt Controller (Core 0) + groupName: INTERRUPT_CORE0 + baseAddress: 1061953536 + addressBlock: + - offset: 0 + size: 400 + usage: registers + interrupt: + - name: WIFI_MAC + value: 0 + - name: WIFI_NMI + value: 1 + - name: WIFI_PWR + value: 2 + - name: WIFI_BB + value: 3 + - name: BT_MAC + value: 4 + - name: BT_BB + value: 5 + - name: BT_BB_NMI + value: 6 + - name: RWBT + value: 7 + - name: RWBLE + value: 8 + - name: RWBT_NMI + value: 9 + - name: RWBLE_NMI + value: 10 + - name: SLC0 + value: 11 + - name: SLC1 + value: 12 + - name: FROM_CPU_INTR0 + value: 28 + - name: FROM_CPU_INTR1 + value: 29 + - name: FROM_CPU_INTR2 + value: 30 + - name: FROM_CPU_INTR3 + value: 31 + - name: SDIO_HOST + value: 40 + - name: WDT + value: 59 + - name: CACHE_IA + value: 70 + - name: ICACHE_PRELOAD + value: 87 + - name: DCACHE_PRELOAD + value: 88 + - name: CPU_PERI_ERR + value: 91 + - name: APB_PERI_ERR + value: 92 + - name: DCACHE_SYNC + value: 93 + - name: ICACHE_SYNC + value: 94 + registers: + - register: + name: PRO_MAC_INTR_MAP + description: MAC_INTR interrupt configuration register + addressOffset: 0 + size: 32 + resetValue: 16 + fields: + - name: PRO_MAC_INTR_MAP + description: This register is used to map MAC_INTR interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_MAC_NMI_MAP + description: MAC_NMI interrupt configuration register + addressOffset: 4 + size: 32 + resetValue: 16 + fields: + - name: PRO_MAC_NMI_MAP + description: This register is used to map MAC_NMI interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_PWR_INTR_MAP + description: PWR_INTR interrupt configuration register + addressOffset: 8 + size: 32 + resetValue: 16 + fields: + - name: PRO_PWR_INTR_MAP + description: This register is used to map PWR_INTR interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_BB_INT_MAP + description: BB_INT interrupt configuration register + addressOffset: 12 + size: 32 + resetValue: 16 + fields: + - name: PRO_BB_INT_MAP + description: This register is used to map BB_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_BT_MAC_INT_MAP + description: BT_MAC_INT interrupt configuration register + addressOffset: 16 + size: 32 + resetValue: 16 + fields: + - name: PRO_BT_MAC_INT_MAP + description: This register is used to map BT_MAC_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_BT_BB_INT_MAP + description: BT_BB_INT interrupt configuration register + addressOffset: 20 + size: 32 + resetValue: 16 + fields: + - name: PRO_BT_BB_INT_MAP + description: This register is used to map BT_BB_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_BT_BB_NMI_MAP + description: BT_BB_NMI interrupt configuration register + addressOffset: 24 + size: 32 + resetValue: 16 + fields: + - name: PRO_BT_BB_NMI_MAP + description: This register is used to map BT_BB_NMI interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_RWBT_IRQ_MAP + description: RWBT_IRQ interrupt configuration register + addressOffset: 28 + size: 32 + resetValue: 16 + fields: + - name: PRO_RWBT_IRQ_MAP + description: This register is used to map RWBT_IRQ interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_RWBLE_IRQ_MAP + description: RWBLE_IRQ interrupt configuration register + addressOffset: 32 + size: 32 + resetValue: 16 + fields: + - name: PRO_RWBLE_IRQ_MAP + description: This register is used to map RWBLE_IRQ interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_RWBT_NMI_MAP + description: RWBT_NMI interrupt configuration register + addressOffset: 36 + size: 32 + resetValue: 16 + fields: + - name: PRO_RWBT_NMI_MAP + description: This register is used to map RWBT_NMI interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_RWBLE_NMI_MAP + description: RWBLE_NMI interrupt configuration register + addressOffset: 40 + size: 32 + resetValue: 16 + fields: + - name: PRO_RWBLE_NMI_MAP + description: This register is used to map RWBLE_NMI interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SLC0_INTR_MAP + description: SLC0_INTR interrupt configuration register + addressOffset: 44 + size: 32 + resetValue: 16 + fields: + - name: PRO_SLC0_INTR_MAP + description: This register is used to map SLC0_INTR interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SLC1_INTR_MAP + description: SLC1_INTR interrupt configuration register + addressOffset: 48 + size: 32 + resetValue: 16 + fields: + - name: PRO_SLC1_INTR_MAP + description: This register is used to map SLC1_INTR interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_UHCI0_INTR_MAP + description: UHCI0_INTR interrupt configuration register + addressOffset: 52 + size: 32 + resetValue: 16 + fields: + - name: PRO_UHCI0_INTR_MAP + description: This register is used to map UHCI0_INTR interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_UHCI1_INTR_MAP + description: UHCI1_INTR interrupt configuration register + addressOffset: 56 + size: 32 + resetValue: 16 + fields: + - name: PRO_UHCI1_INTR_MAP + description: This register is used to map UHCI1_INTR interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG_T0_LEVEL_INT_MAP + description: TG_T0_LEVEL_INT interrupt configuration register + addressOffset: 60 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG_T0_LEVEL_INT_MAP + description: This register is used to map TG_T0_LEVEL_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG_T1_LEVEL_INT_MAP + description: TG_T1_LEVEL_INT interrupt configuration register + addressOffset: 64 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG_T1_LEVEL_INT_MAP + description: This register is used to map TG_T1_LEVEL_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG_WDT_LEVEL_INT_MAP + description: TG_WDT_LEVEL_INT interrupt configuration register + addressOffset: 68 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG_WDT_LEVEL_INT_MAP + description: This register is used to map TG_WDT_LEVEL_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG_LACT_LEVEL_INT_MAP + description: TG_LACT_LEVEL_INT interrupt configuration register + addressOffset: 72 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG_LACT_LEVEL_INT_MAP + description: This register is used to map TG_LACT_LEVEL_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG1_T0_LEVEL_INT_MAP + description: TG1_T0_LEVEL_INT interrupt configuration register + addressOffset: 76 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG1_T0_LEVEL_INT_MAP + description: This register is used to map TG1_T0_LEVEL_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG1_T1_LEVEL_INT_MAP + description: TG1_T1_LEVEL_INT interrupt configuration register + addressOffset: 80 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG1_T1_LEVEL_INT_MAP + description: This register is used to map TG1_T1_LEVEL_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG1_WDT_LEVEL_INT_MAP + description: TG1_WDT_LEVEL_INT interrupt configuration register + addressOffset: 84 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG1_WDT_LEVEL_INT_MAP + description: This register is used to map TG1_WDT_LEVEL_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG1_LACT_LEVEL_INT_MAP + description: TG1_LACT_LEVEL_INT interrupt configuration register + addressOffset: 88 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG1_LACT_LEVEL_INT_MAP + description: This register is used to map TG1_LACT_LEVEL_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_GPIO_INTERRUPT_PRO_MAP + description: GPIO_INTERRUPT_PRO interrupt configuration register + addressOffset: 92 + size: 32 + resetValue: 16 + fields: + - name: PRO_GPIO_INTERRUPT_PRO_MAP + description: This register is used to map GPIO_INTERRUPT_PRO interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_GPIO_INTERRUPT_PRO_NMI_MAP + description: GPIO_INTERRUPT_PRO_NMI interrupt configuration register + addressOffset: 96 + size: 32 + resetValue: 16 + fields: + - name: PRO_GPIO_INTERRUPT_PRO_NMI_MAP + description: This register is used to map GPIO_INTERRUPT_PRO_NMI interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_GPIO_INTERRUPT_APP_MAP + description: GPIO_INTERRUPT_APP interrupt configuration register + addressOffset: 100 + size: 32 + resetValue: 16 + fields: + - name: PRO_GPIO_INTERRUPT_APP_MAP + description: This register is used to map GPIO_INTERRUPT_APP interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_GPIO_INTERRUPT_APP_NMI_MAP + description: GPIO_INTERRUPT_APP_NMI interrupt configuration register + addressOffset: 104 + size: 32 + resetValue: 16 + fields: + - name: PRO_GPIO_INTERRUPT_APP_NMI_MAP + description: This register is used to map GPIO_INTERRUPT_APP_NMI interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_DEDICATED_GPIO_IN_INTR_MAP + description: DEDICATED_GPIO_IN_INTR interrupt configuration register + addressOffset: 108 + size: 32 + resetValue: 16 + fields: + - name: PRO_DEDICATED_GPIO_IN_INTR_MAP + description: This register is used to map DEDICATED_GPIO_IN_INTR interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_CPU_INTR_FROM_CPU_0_MAP + description: CPU_INTR_FROM_CPU_0 interrupt configuration register + addressOffset: 112 + size: 32 + resetValue: 16 + fields: + - name: PRO_CPU_INTR_FROM_CPU_0_MAP + description: This register is used to map CPU_INTR_FROM_CPU_0 interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_CPU_INTR_FROM_CPU_1_MAP + description: CPU_INTR_FROM_CPU_1 interrupt configuration register + addressOffset: 116 + size: 32 + resetValue: 16 + fields: + - name: PRO_CPU_INTR_FROM_CPU_1_MAP + description: This register is used to map CPU_INTR_FROM_CPU_1 interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_CPU_INTR_FROM_CPU_2_MAP + description: CPU_INTR_FROM_CPU_2 interrupt configuration register + addressOffset: 120 + size: 32 + resetValue: 16 + fields: + - name: PRO_CPU_INTR_FROM_CPU_2_MAP + description: This register is used to map CPU_INTR_FROM_CPU_2 interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_CPU_INTR_FROM_CPU_3_MAP + description: CPU_INTR_FROM_CPU_3 interrupt configuration register + addressOffset: 124 + size: 32 + resetValue: 16 + fields: + - name: PRO_CPU_INTR_FROM_CPU_3_MAP + description: This register is used to map CPU_INTR_FROM_CPU_3 interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SPI_INTR_1_MAP + description: SPI_INTR_1 interrupt configuration register + addressOffset: 128 + size: 32 + resetValue: 16 + fields: + - name: PRO_SPI_INTR_1_MAP + description: This register is used to map SPI_INTR_1 interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SPI_INTR_2_MAP + description: SPI_INTR_2 interrupt configuration register + addressOffset: 132 + size: 32 + resetValue: 16 + fields: + - name: PRO_SPI_INTR_2_MAP + description: This register is used to map SPI_INTR_2 interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SPI_INTR_3_MAP + description: SPI_INTR_3 interrupt configuration register + addressOffset: 136 + size: 32 + resetValue: 16 + fields: + - name: PRO_SPI_INTR_3_MAP + description: This register is used to map SPI_INTR_3 interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_I2S0_INT_MAP + description: I2S0_INT interrupt configuration register + addressOffset: 140 + size: 32 + resetValue: 16 + fields: + - name: PRO_I2S0_INT_MAP + description: This register is used to map I2S0_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_I2S1_INT_MAP + description: I2S1_INT interrupt configuration register + addressOffset: 144 + size: 32 + resetValue: 16 + fields: + - name: PRO_I2S1_INT_MAP + description: This register is used to map I2S1_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_UART_INTR_MAP + description: UART_INT interrupt configuration register + addressOffset: 148 + size: 32 + resetValue: 16 + fields: + - name: PRO_UART_INTR_MAP + description: This register is used to map UART_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_UART1_INTR_MAP + description: UART1_INT interrupt configuration register + addressOffset: 152 + size: 32 + resetValue: 16 + fields: + - name: PRO_UART1_INTR_MAP + description: This register is used to map UART1_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_UART2_INTR_MAP + description: UART2_INT interrupt configuration register + addressOffset: 156 + size: 32 + resetValue: 16 + fields: + - name: PRO_UART2_INTR_MAP + description: This register is used to map UART2_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SDIO_HOST_INTERRUPT_MAP + description: SDIO_HOST_INTERRUPT configuration register + addressOffset: 160 + size: 32 + resetValue: 16 + fields: + - name: PRO_SDIO_HOST_INTERRUPT_MAP + description: This register is used to map SDIO_HOST_INTERRUPT signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_PWM0_INTR_MAP + description: PWM0_INTR interrupt configuration register + addressOffset: 164 + size: 32 + resetValue: 16 + fields: + - name: PRO_PWM0_INTR_MAP + description: This register is used to map PWM0_INTR interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_PWM1_INTR_MAP + description: PWM1_INTR interrupt configuration register + addressOffset: 168 + size: 32 + resetValue: 16 + fields: + - name: PRO_PWM1_INTR_MAP + description: This register is used to map PWM1_INTR interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_PWM2_INTR_MAP + description: PWM2_INTR interrupt configuration register + addressOffset: 172 + size: 32 + resetValue: 16 + fields: + - name: PRO_PWM2_INTR_MAP + description: This register is used to map PWM2_INTR interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_PWM3_INTR_MAP + description: PWM3_INTR interrupt configuration register + addressOffset: 176 + size: 32 + resetValue: 16 + fields: + - name: PRO_PWM3_INTR_MAP + description: This register is used to map PWM3_INTR interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_LEDC_INT_MAP + description: LEDC_INTR interrupt configuration register + addressOffset: 180 + size: 32 + resetValue: 16 + fields: + - name: PRO_LEDC_INT_MAP + description: This register is used to map LEDC_INTR interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_EFUSE_INT_MAP + description: EFUSE_INT interrupt configuration register + addressOffset: 184 + size: 32 + resetValue: 16 + fields: + - name: PRO_EFUSE_INT_MAP + description: This register is used to map EFUSE_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_CAN_INT_MAP + description: CAN_INT interrupt configuration register + addressOffset: 188 + size: 32 + resetValue: 16 + fields: + - name: PRO_CAN_INT_MAP + description: This register is used to map CAN_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_USB_INTR_MAP + description: USB_INT interrupt configuration register + addressOffset: 192 + size: 32 + resetValue: 16 + fields: + - name: PRO_USB_INTR_MAP + description: This register is used to map USB_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_RTC_CORE_INTR_MAP + description: RTC_CORE_INTR interrupt configuration register + addressOffset: 196 + size: 32 + resetValue: 16 + fields: + - name: PRO_RTC_CORE_INTR_MAP + description: This register is used to map RTC_CORE_INTR interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_RMT_INTR_MAP + description: RMT_INTR interrupt configuration register + addressOffset: 200 + size: 32 + resetValue: 16 + fields: + - name: PRO_RMT_INTR_MAP + description: This register is used to map RMT_INTR interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_PCNT_INTR_MAP + description: PCNT_INTR interrupt configuration register + addressOffset: 204 + size: 32 + resetValue: 16 + fields: + - name: PRO_PCNT_INTR_MAP + description: This register is used to map PCNT_INTR interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_I2C_EXT0_INTR_MAP + description: I2C_EXT0_INTR interrupt configuration register + addressOffset: 208 + size: 32 + resetValue: 16 + fields: + - name: PRO_I2C_EXT0_INTR_MAP + description: This register is used to map I2C_EXT0_INTR interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_I2C_EXT1_INTR_MAP + description: I2C_EXT1_INTR interrupt configuration register + addressOffset: 212 + size: 32 + resetValue: 16 + fields: + - name: PRO_I2C_EXT1_INTR_MAP + description: This register is used to map I2C_EXT1_INTR interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_RSA_INTR_MAP + description: RSA_INTR interrupt configuration register + addressOffset: 216 + size: 32 + resetValue: 16 + fields: + - name: PRO_RSA_INTR_MAP + description: This register is used to map RSA_INTR interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SHA_INTR_MAP + description: SHA_INTR interrupt configuration register + addressOffset: 220 + size: 32 + resetValue: 16 + fields: + - name: PRO_SHA_INTR_MAP + description: This register is used to map SHA_INTR interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_AES_INTR_MAP + description: AES_INTR interrupt configuration register + addressOffset: 224 + size: 32 + resetValue: 16 + fields: + - name: PRO_AES_INTR_MAP + description: This register is used to map AES_INTR interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SPI2_DMA_INT_MAP + description: SPI2_DMA_INT interrupt configuration register + addressOffset: 228 + size: 32 + resetValue: 16 + fields: + - name: PRO_SPI2_DMA_INT_MAP + description: This register is used to map AES_INTR interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SPI3_DMA_INT_MAP + description: SPI3_DMA_INT interrupt configuration register + addressOffset: 232 + size: 32 + resetValue: 16 + fields: + - name: PRO_SPI3_DMA_INT_MAP + description: This register is used to map SPI3_DMA_INT dma interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_WDG_INT_MAP + description: WDG_INT interrupt configuration register + addressOffset: 236 + size: 32 + resetValue: 16 + fields: + - name: PRO_WDG_INT_MAP + description: This register is used to map WDG_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TIMER_INT1_MAP + description: TIMER_INT1 interrupt configuration register + addressOffset: 240 + size: 32 + resetValue: 16 + fields: + - name: PRO_TIMER_INT1_MAP + description: This register is used to map TIMER_INT1 interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TIMER_INT2_MAP + description: TIMER_INT2 interrupt configuration register + addressOffset: 244 + size: 32 + resetValue: 16 + fields: + - name: PRO_TIMER_INT2_MAP + description: This register is used to map TIMER_INT2 interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG_T0_EDGE_INT_MAP + description: TG_T0_EDGE_INT interrupt configuration register + addressOffset: 248 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG_T0_EDGE_INT_MAP + description: This register is used to map TG_T0_EDGE_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG_T1_EDGE_INT_MAP + description: TG_T1_EDGE_INT interrupt configuration register + addressOffset: 252 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG_T1_EDGE_INT_MAP + description: This register is used to map TG_T1_EDGE_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG_WDT_EDGE_INT_MAP + description: TG_WDT_EDGE_INT interrupt configuration register + addressOffset: 256 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG_WDT_EDGE_INT_MAP + description: This register is used to map TG_WDT_EDGE_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG_LACT_EDGE_INT_MAP + description: TG_LACT_EDGE_INT interrupt configuration register + addressOffset: 260 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG_LACT_EDGE_INT_MAP + description: This register is used to map TG_LACT_EDGE_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG1_T0_EDGE_INT_MAP + description: TG1_T0_EDGE_INT interrupt configuration register + addressOffset: 264 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG1_T0_EDGE_INT_MAP + description: This register is used to map TG1_T0_EDGE_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG1_T1_EDGE_INT_MAP + description: TG1_T1_EDGE_INT interrupt configuration register + addressOffset: 268 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG1_T1_EDGE_INT_MAP + description: This register is used to map TG1_T1_EDGE_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG1_WDT_EDGE_INT_MAP + description: TG1_WDT_EDGE_INT interrupt configuration register + addressOffset: 272 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG1_WDT_EDGE_INT_MAP + description: This register is used to map TG1_WDT_EDGE_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_TG1_LACT_EDGE_INT_MAP + description: TG1_LACT_EDGE_INT interrupt configuration register + addressOffset: 276 + size: 32 + resetValue: 16 + fields: + - name: PRO_TG1_LACT_EDGE_INT_MAP + description: This register is used to map TG1_LACT_EDGE_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_CACHE_IA_INT_MAP + description: CACHE_IA_INT interrupt configuration register + addressOffset: 280 + size: 32 + resetValue: 16 + fields: + - name: PRO_CACHE_IA_INT_MAP + description: This register is used to map CACHE_IA_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SYSTIMER_TARGET0_INT_MAP + description: SYSTIMER_TARGET0_INT interrupt configuration register + addressOffset: 284 + size: 32 + resetValue: 16 + fields: + - name: PRO_SYSTIMER_TARGET0_INT_MAP + description: This register is used to map SYSTIMER_TARGET0_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SYSTIMER_TARGET1_INT_MAP + description: SYSTIMER_TARGET1_INT interrupt configuration register + addressOffset: 288 + size: 32 + resetValue: 16 + fields: + - name: PRO_SYSTIMER_TARGET1_INT_MAP + description: This register is used to map SYSTIMER_TARGET1_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SYSTIMER_TARGET2_INT_MAP + description: SYSTIMER_TARGET2_INT interrupt configuration register + addressOffset: 292 + size: 32 + resetValue: 16 + fields: + - name: PRO_SYSTIMER_TARGET2_INT_MAP + description: This register is used to map SYSTIMER_TARGET2_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_ASSIST_DEBUG_INTR_MAP + description: ASSIST_DEBUG_INTR interrupt configuration register + addressOffset: 296 + size: 32 + resetValue: 16 + fields: + - name: PRO_ASSIST_DEBUG_INTR_MAP + description: This register is used to map ASSIST_DEBUG_INTR interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_PMS_PRO_IRAM0_ILG_INTR_MAP + description: PMS_PRO_IRAM0_ILG interrupt configuration register + addressOffset: 300 + size: 32 + resetValue: 16 + fields: + - name: PRO_PMS_PRO_IRAM0_ILG_INTR_MAP + description: This register is used to map PMS_PRO_IRAM0_ILG interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_PMS_PRO_DRAM0_ILG_INTR_MAP + description: PMS_PRO_DRAM0_ILG interrupt configuration register + addressOffset: 304 + size: 32 + resetValue: 16 + fields: + - name: PRO_PMS_PRO_DRAM0_ILG_INTR_MAP + description: This register is used to map PMS_PRO_DRAM0_ILG interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_PMS_PRO_DPORT_ILG_INTR_MAP + description: PMS_PRO_DPORT_ILG interrupt configuration register + addressOffset: 308 + size: 32 + resetValue: 16 + fields: + - name: PRO_PMS_PRO_DPORT_ILG_INTR_MAP + description: This register is used to map PMS_PRO_DPORT_ILG interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_PMS_PRO_AHB_ILG_INTR_MAP + description: PMS_PRO_AHB_ILG interrupt configuration register + addressOffset: 312 + size: 32 + resetValue: 16 + fields: + - name: PRO_PMS_PRO_AHB_ILG_INTR_MAP + description: This register is used to map PMS_PRO_AHB_ILG interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_PMS_PRO_CACHE_ILG_INTR_MAP + description: PMS_PRO_CACHE_ILG interrupt configuration register + addressOffset: 316 + size: 32 + resetValue: 16 + fields: + - name: PRO_PMS_PRO_CACHE_ILG_INTR_MAP + description: This register is used to map PMS_PRO_CACHE_ILG interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_PMS_DMA_APB_I_ILG_INTR_MAP + description: PMS_DMA_APB_I_ILG interrupt configuration register + addressOffset: 320 + size: 32 + resetValue: 16 + fields: + - name: PRO_PMS_DMA_APB_I_ILG_INTR_MAP + description: This register is used to map PMS_DMA_APB_I_ILG interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_PMS_DMA_RX_I_ILG_INTR_MAP + description: PMS_DMA_RX_I_ILG interrupt configuration register + addressOffset: 324 + size: 32 + resetValue: 16 + fields: + - name: PRO_PMS_DMA_RX_I_ILG_INTR_MAP + description: This register is used to map PMS_DMA_RX_I_ILG interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_PMS_DMA_TX_I_ILG_INTR_MAP + description: PMS_DMA_TX_I_ILG interrupt configuration register + addressOffset: 328 + size: 32 + resetValue: 16 + fields: + - name: PRO_PMS_DMA_TX_I_ILG_INTR_MAP + description: This register is used to map PMS_DMA_TX_I_ILG interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SPI_MEM_REJECT_INTR_MAP + description: SPI_MEM_REJECT_INTR interrupt configuration register + addressOffset: 332 + size: 32 + resetValue: 16 + fields: + - name: PRO_SPI_MEM_REJECT_INTR_MAP + description: This register is used to map SPI_MEM_REJECT_INTR interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_DMA_COPY_INTR_MAP + description: DMA_COPY_INTR interrupt configuration register + addressOffset: 336 + size: 32 + resetValue: 16 + fields: + - name: PRO_DMA_COPY_INTR_MAP + description: This register is used to map DMA_COPY_INTR interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SPI4_DMA_INT_MAP + description: SPI4_DMA_INT interrupt configuration register + addressOffset: 340 + size: 32 + resetValue: 16 + fields: + - name: PRO_SPI4_DMA_INT_MAP + description: This register is used to map SPI4_DMA_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_SPI_INTR_4_MAP + description: SPI_INTR_4 interrupt configuration register + addressOffset: 344 + size: 32 + resetValue: 16 + fields: + - name: PRO_SPI_INTR_4_MAP + description: This register is used to map SPI_INTR_4 interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_DCACHE_PRELOAD_INT_MAP + description: DCACHE_PRELOAD_INT interrupt configuration register + addressOffset: 348 + size: 32 + resetValue: 16 + fields: + - name: PRO_DCACHE_PRELOAD_INT_MAP + description: This register is used to map DCACHE_PRELOAD_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_ICACHE_PRELOAD_INT_MAP + description: ICACHE_PRELOAD_INT interrupt configuration register + addressOffset: 352 + size: 32 + resetValue: 16 + fields: + - name: PRO_ICACHE_PRELOAD_INT_MAP + description: This register is used to map ICACHE_PRELOAD_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_APB_ADC_INT_MAP + description: APB_ADC_INT interrupt configuration register + addressOffset: 356 + size: 32 + resetValue: 16 + fields: + - name: PRO_APB_ADC_INT_MAP + description: This register is used to map APB_ADC_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_CRYPTO_DMA_INT_MAP + description: CRYPTO_DMA_INT interrupt configuration register + addressOffset: 360 + size: 32 + resetValue: 16 + fields: + - name: PRO_CRYPTO_DMA_INT_MAP + description: This register is used to map CRYPTO_DMA_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_CPU_PERI_ERROR_INT_MAP + description: CPU_PERI_ERROR_INT interrupt configuration register + addressOffset: 364 + size: 32 + resetValue: 16 + fields: + - name: PRO_CPU_PERI_ERROR_INT_MAP + description: This register is used to map CPU_PERI_ERROR_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_APB_PERI_ERROR_INT_MAP + description: APB_PERI_ERROR_INT interrupt configuration register + addressOffset: 368 + size: 32 + resetValue: 16 + fields: + - name: PRO_APB_PERI_ERROR_INT_MAP + description: This register is used to map APB_PERI_ERROR_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_DCACHE_SYNC_INT_MAP + description: DCACHE_SYNC_INT interrupt configuration register + addressOffset: 372 + size: 32 + resetValue: 16 + fields: + - name: PRO_DCACHE_SYNC_INT_MAP + description: This register is used to map DCACHE_SYNC_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_ICACHE_SYNC_INT_MAP + description: ICACHE_SYNC_INT interrupt configuration register + addressOffset: 376 + size: 32 + resetValue: 16 + fields: + - name: PRO_ICACHE_SYNC_INT_MAP + description: This register is used to map ICACHE_SYNC_INT interrupt signal to one of the CPU interrupts. + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_INTR_STATUS_0 + description: Interrupt status register 0 + addressOffset: 380 + size: 32 + fields: + - name: PRO_INTR_STATUS_0 + description: This register stores the status of the first 32 input interrupt sources. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PRO_INTR_STATUS_1 + description: Interrupt status register 1 + addressOffset: 384 + size: 32 + fields: + - name: PRO_INTR_STATUS_1 + description: This register stores the status of the second 32 input interrupt sources. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PRO_INTR_STATUS_2 + description: Interrupt status register 2 + addressOffset: 388 + size: 32 + fields: + - name: PRO_INTR_STATUS_2 + description: This register stores the status of the last 31 input interrupt sources. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CLOCK_GATE + description: NMI interrupt signals mask register + addressOffset: 392 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: "This bit is used to enable or disable the clock of interrupt matrix. 1: enable the clock. 0: disable the clock." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_NMI_MASK_HW + description: This bit is used to disable all NMI interrupt signals to CPU. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: REG_DATE + description: Version control register + addressOffset: 4092 + size: 32 + resetValue: 26231168 + fields: + - name: INTERRUPT_REG_DATE + description: This is the version register. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: IO_MUX + description: Input/Output Multiplexer + groupName: IO_MUX + baseAddress: 1061195776 + addressBlock: + - offset: 0 + size: 180 + usage: registers + registers: + - register: + name: PIN_CTRL + description: Clock output configuration register + addressOffset: 0 + size: 32 + resetValue: 10239 + fields: + - name: PIN_CLK_OUT1 + description: "Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT1. 15: disabled." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: PIN_CLK_OUT2 + description: "Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT2. 15: disabled." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: PIN_CLK_OUT3 + description: "Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT3. 15: disabled." + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: SWITCH_PRT_NUM + description: "IO pin power switch delay, delay unit is one APB clock." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: PAD_POWER_CTRL + description: "Select power voltage for GPIO33 ~ GPIO37. 1: select VDD_SPI 1.8 V. 0: select VDD3P3_CPU 3.3 V." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO0 + description: Configuration register for pin GPIO0 + addressOffset: 4 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO1 + description: Configuration register for pin GPIO1 + addressOffset: 8 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO2 + description: Configuration register for pin GPIO2 + addressOffset: 12 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO3 + description: Configuration register for pin GPIO3 + addressOffset: 16 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO4 + description: Configuration register for pin GPIO4 + addressOffset: 20 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO5 + description: Configuration register for pin GPIO5 + addressOffset: 24 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO6 + description: Configuration register for pin GPIO6 + addressOffset: 28 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO7 + description: Configuration register for pin GPIO7 + addressOffset: 32 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO8 + description: Configuration register for pin GPIO8 + addressOffset: 36 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO9 + description: Configuration register for pin GPIO9 + addressOffset: 40 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO10 + description: Configuration register for pin GPIO10 + addressOffset: 44 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO11 + description: Configuration register for pin GPIO11 + addressOffset: 48 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO12 + description: Configuration register for pin GPIO12 + addressOffset: 52 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO13 + description: Configuration register for pin GPIO13 + addressOffset: 56 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO14 + description: Configuration register for pin GPIO14 + addressOffset: 60 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO19 + description: Configuration register for pin GPIO19 + addressOffset: 80 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO20 + description: Configuration register for pin GPIO20 + addressOffset: 84 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO21 + description: Configuration register for pin GPIO21 + addressOffset: 88 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO33 + description: Configuration register for pin GPIO33 + addressOffset: 136 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO34 + description: Configuration register for pin GPIO34 + addressOffset: 140 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO35 + description: Configuration register for pin GPIO35 + addressOffset: 144 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO36 + description: Configuration register for pin GPIO36 + addressOffset: 148 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO37 + description: Configuration register for pin GPIO37 + addressOffset: 152 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO38 + description: Configuration register for pin GPIO38 + addressOffset: 156 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO45 + description: Configuration register for pin GPIO45 + addressOffset: 184 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO46 + description: Configuration register for pin GPIO46 + addressOffset: 188 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 252 + size: 32 + resetValue: 26243424 + fields: + - name: VERSION + description: Version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + name: GPIO15 + description: Configuration register for pin GPIO15 + addressOffset: 64 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO16 + description: Configuration register for pin GPIO16 + addressOffset: 68 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO17 + description: Configuration register for pin GPIO17 + addressOffset: 72 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO18 + description: Configuration register for pin GPIO18 + addressOffset: 76 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO26 + description: Configuration register for pin GPIO26 + addressOffset: 108 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO27 + description: Configuration register for pin GPIO27 + addressOffset: 112 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO28 + description: Configuration register for pin GPIO28 + addressOffset: 116 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO29 + description: Configuration register for pin GPIO29 + addressOffset: 120 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO30 + description: Configuration register for pin GPIO30 + addressOffset: 124 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO31 + description: Configuration register for pin GPIO31 + addressOffset: 128 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO32 + description: Configuration register for pin GPIO32 + addressOffset: 132 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO39 + description: Configuration register for pin GPIO39 + addressOffset: 160 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO40 + description: Configuration register for pin GPIO40 + addressOffset: 164 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO41 + description: Configuration register for pin GPIO41 + addressOffset: 168 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO42 + description: Configuration register for pin GPIO42 + addressOffset: 172 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO43 + description: Configuration register for pin GPIO43 + addressOffset: 176 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: GPIO44 + description: Configuration register for pin GPIO44 + addressOffset: 180 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pin in sleep mode. 1: Output enabled. 0: Output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pin. Set to 1 to put the pin in sleep mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pin during sleep mode. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pin during sleep mode. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pin during sleep mode. 1: Input enabled. 0: Input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pin. 1: Internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pin. 1: Internal pull-up enabled. 0: Internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pin. 1: Input enabled. 0: Input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pin. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2, etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled. 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: LEDC + description: LED Control PWM (Pulse Width Modulation) + groupName: LEDC + baseAddress: 1061261312 + addressBlock: + - offset: 0 + size: 216 + usage: registers + interrupt: + - name: LEDC + value: 45 + - name: TIMER1 + value: 60 + - name: TIMER2 + value: 61 + registers: + - register: + dim: 8 + dimIncrement: 20 + name: CH%s_CONF0 + description: Configuration register 0 for channel %s + addressOffset: 0 + size: 32 + fields: + - name: TIMER_SEL + description: "This field is used to select one of timers for channel %s.\n\n0: select timer 0.\n\n1: select timer 1.\n\n2: select timer 2.\n\n3: select timer 3." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SIG_OUT_EN + description: Set this bit to enable signal output on channel %s. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IDLE_LV + description: This bit is used to control the output value when channel %s is inactive. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PARA_UP + description: This bit is used to update register LEDC_CH%s_HPOINT and LEDC_CH%s_DUTY for channel %s. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: OVF_NUM + description: This register is used to configure the maximum times of overflow minus 1. The LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times. + bitOffset: 5 + bitWidth: 10 + access: read-write + - name: OVF_CNT_EN + description: This bit is used to enable the ovf_cnt of channel %s. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: OVF_CNT_RESET + description: Set this bit to reset the ovf_cnt of channel %s. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: OVF_CNT_RESET_ST + description: This is the status bit of LEDC_OVF_CNT_RESET_CH%s. + bitOffset: 17 + bitWidth: 1 + access: read-only + - register: + dim: 8 + dimIncrement: 20 + name: CH%s_HPOINT + description: High point register for channel %s + addressOffset: 4 + size: 32 + fields: + - name: HPOINT + description: The output value changes to high when the selected timers has reached the value specified by this register. + bitOffset: 0 + bitWidth: 14 + access: read-write + - register: + dim: 8 + dimIncrement: 20 + name: CH%s_DUTY + description: Initial duty cycle for channel %s + addressOffset: 8 + size: 32 + fields: + - name: DUTY + description: This register is used to change the output duty by controlling the Lpoint. The output value turns to low when the selected timers has reached the Lpoint. + bitOffset: 0 + bitWidth: 19 + access: read-write + - register: + dim: 8 + dimIncrement: 20 + name: CH%s_CONF1 + description: Configuration register 1 for channel %s + addressOffset: 12 + size: 32 + resetValue: 1073741824 + fields: + - name: DUTY_SCALE + description: This register is used to configure the changing step scale of duty on channel %s. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: DUTY_CYCLE + description: The duty will change every LEDC_DUTY_CYCLE_CH%s on channel %s. + bitOffset: 10 + bitWidth: 10 + access: read-write + - name: DUTY_NUM + description: This register is used to control the number of times the duty cycle will be changed. + bitOffset: 20 + bitWidth: 10 + access: read-write + - name: DUTY_INC + description: "This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase. 0: Decrease." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DUTY_START + description: Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + dim: 8 + dimIncrement: 20 + name: CH%s_DUTY_R + description: Current duty cycle for channel %s + addressOffset: 16 + size: 32 + fields: + - name: DUTY_R + description: This register stores the current duty of output signal on channel %s. + bitOffset: 0 + bitWidth: 19 + access: read-only + - register: + dim: 4 + dimIncrement: 8 + name: TIMER%s_CONF + description: Timer %s configuration + addressOffset: 160 + size: 32 + resetValue: 8388608 + fields: + - name: DUTY_RES + description: This register is used to control the range of the counter in timer %s. + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: CLK_DIV + description: This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part. + bitOffset: 4 + bitWidth: 18 + access: read-write + - name: PAUSE + description: This bit is used to suspend the counter in timer %s. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RST + description: This bit is used to reset timer %s. The counter will show 0 after reset. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TICK_SEL + description: "This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. 0: LEDC_PWM_CLK. 1: REF_TICK." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PARA_UP + description: Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES. + bitOffset: 25 + bitWidth: 1 + access: write-only + - register: + dim: 4 + dimIncrement: 8 + name: TIMER%s_VALUE + description: Timer %s current counter value + addressOffset: 164 + size: 32 + fields: + - name: CNT + description: This register stores the current counter value of timer %s. + bitOffset: 0 + bitWidth: 14 + access: read-only + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 192 + size: 32 + fields: + - name: TIMER0_OVF_INT_RAW + description: Triggered when the timer0 has reached its maximum counter value. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TIMER1_OVF_INT_RAW + description: Triggered when the timer1 has reached its maximum counter value. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TIMER2_OVF_INT_RAW + description: Triggered when the timer2 has reached its maximum counter value. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TIMER3_OVF_INT_RAW + description: Triggered when the timer3 has reached its maximum counter value. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH0_INT_RAW + description: Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH1_INT_RAW + description: Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH2_INT_RAW + description: Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH3_INT_RAW + description: Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH4_INT_RAW + description: Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH5_INT_RAW + description: Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH6_INT_RAW + description: Interrupt raw bit for channel 6. Triggered when the gradual change of duty has finished. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH7_INT_RAW + description: Interrupt raw bit for channel 7. Triggered when the gradual change of duty has finished. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH0_INT_RAW + description: Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH1_INT_RAW + description: Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH2_INT_RAW + description: Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH3_INT_RAW + description: Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH4_INT_RAW + description: Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH5_INT_RAW + description: Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH6_INT_RAW + description: Interrupt raw bit for channel 6. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH7_INT_RAW + description: Interrupt raw bit for channel 7. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7. + bitOffset: 19 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 196 + size: 32 + fields: + - name: TIMER0_OVF_INT_ST + description: This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TIMER1_OVF_INT_ST + description: This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TIMER2_OVF_INT_ST + description: This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TIMER3_OVF_INT_ST + description: This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH0_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENAIS set to 1. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH1_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENAIS set to 1. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH2_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENAIS set to 1. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH3_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENAIS set to 1. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH4_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENAIS set to 1. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH5_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENAIS set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH6_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH6_INT interrupt when LEDC_DUTY_CHNG_END_CH6_INT_ENAIS set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH7_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH7_INT interrupt when LEDC_DUTY_CHNG_END_CH7_INT_ENAIS set to 1. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH0_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH1_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH2_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH3_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH4_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH5_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH6_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH6_INT interrupt when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH7_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH7_INT interrupt when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. + bitOffset: 19 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 200 + size: 32 + fields: + - name: TIMER0_OVF_INT_ENA + description: The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMER1_OVF_INT_ENA + description: The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER2_OVF_INT_ENA + description: The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TIMER3_OVF_INT_ENA + description: The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH0_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH1_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH2_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH3_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH4_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH5_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH6_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH6_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH7_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH7_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH0_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH1_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH2_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH3_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH4_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH5_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH6_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH6_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH7_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH7_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 204 + size: 32 + fields: + - name: TIMER0_OVF_INT_CLR + description: Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TIMER1_OVF_INT_CLR + description: Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TIMER2_OVF_INT_CLR + description: Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TIMER3_OVF_INT_CLR + description: Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH0_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH1_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH2_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH3_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH4_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH5_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH6_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH6_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH7_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH7_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH0_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH1_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH2_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH3_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH4_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH5_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH6_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH6_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH7_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH7_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - register: + name: CONF + description: Global ledc configuration register + addressOffset: 208 + size: 32 + fields: + - name: APB_CLK_SEL + description: "This bit is used to select clock source for the 4 timers . 1: APB_CLK. 2: RTC8M_CLK. 3: XTAL_CLK." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CLK_EN + description: "This bit is used to control clock. 1: Force clock on for register. 0: Support clock only when application writes registers." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 252 + size: 32 + resetValue: 419898881 + fields: + - name: DATE + description: This is the version control register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: PCNT + description: Pulse Count Controller + groupName: PCNT + baseAddress: 1061253120 + addressBlock: + - offset: 0 + size: 104 + usage: registers + interrupt: + - name: PCNT + value: 51 + registers: + - register: + dim: 4 + dimIncrement: 12 + name: U%s_CONF0 + description: Configuration register 0 for unit %s + addressOffset: 0 + size: 32 + resetValue: 15376 + fields: + - name: FILTER_THRES + description: "This sets the maximum threshold, in APB_CLK cycles, for the filter.\nAny pulses with width less than this will be ignored when the filter is enabled." + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: FILTER_EN + description: "This is the enable bit for unit %s's input filter." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: THR_ZERO_EN + description: "This is the enable bit for unit %s's zero comparator." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: THR_H_LIM_EN + description: "This is the enable bit for unit %s's thr_h_lim comparator." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: THR_L_LIM_EN + description: "This is the enable bit for unit %s's thr_l_lim comparator." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: THR_THRES0_EN + description: "This is the enable bit for unit %s's thres0 comparator." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: THR_THRES1_EN + description: "This is the enable bit for unit %s's thres1 comparator." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CH0_NEG_MODE + description: "This register sets the behavior when the signal input of channel 0 detects a negative edge.\n1: Increase the counter. 2: Decrease the counter. 0, 3: No effect on counter." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CH0_POS_MODE + description: "This register sets the behavior when the signal input of channel 0 detects a positive edge.\n1: Increase the counter. 2: Decrease the counter. 0, 3: No effect on counter." + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: CH0_HCTRL_MODE + description: "This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high.\n0: No modification. 1: Invert behavior (increase -> decrease, decrease -> increase). 2, 3: Inhibit counter modification." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: CH0_LCTRL_MODE + description: "This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low.\n0: No modification. 1: Invert behavior (increase -> decrease, decrease -> increase). 2, 3: Inhibit counter modification." + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CH1_NEG_MODE + description: "This register sets the behavior when the signal input of channel 1 detects a negative edge.\n1: Increment the counter. 2: Decrement the counter. 0, 3: No effect on counter." + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CH1_POS_MODE + description: "This register sets the behavior when the signal input of channel 1 detects a positive edge.\n1: Increment the counter. 2: Decrement the counter. 0, 3: No effect on counter." + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CH1_HCTRL_MODE + description: "This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high.\n0: No modification. 1: Invert behavior (increase -> decrease, decrease -> increase). 2, 3: Inhibit counter modification." + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: CH1_LCTRL_MODE + description: "This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low.\n0: No modification. 1: Invert behavior (increase -> decrease, decrease -> increase). 2, 3: Inhibit counter modification." + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + dim: 4 + dimIncrement: 12 + name: U%s_CONF1 + description: Configuration register 1 for unit %s + addressOffset: 4 + size: 32 + fields: + - name: CNT_THRES0 + description: This register is used to configure the thres0 value for unit %s. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CNT_THRES1 + description: This register is used to configure the thres1 value for unit %s. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + dim: 4 + dimIncrement: 12 + name: U%s_CONF2 + description: Configuration register 2 for unit %s + addressOffset: 8 + size: 32 + fields: + - name: CNT_H_LIM + description: This register is used to configure the thr_h_lim value for unit %s. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CNT_L_LIM + description: This register is used to configure the thr_l_lim value for unit %s. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: U%s_CNT + description: Counter value for unit %s + addressOffset: 48 + size: 32 + fields: + - name: CNT + description: This register stores the current pulse count value for unit %s. + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: INT_RAW + description: Interrupt raw status register + addressOffset: 64 + size: 32 + fields: + - name: CNT_THR_EVENT_U0 + description: The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U1 + description: The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U2 + description: The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U3 + description: The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: Interrupt status register + addressOffset: 68 + size: 32 + fields: + - name: CNT_THR_EVENT_U0 + description: The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U1 + description: The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U2 + description: The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U3 + description: The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable register + addressOffset: 72 + size: 32 + fields: + - name: CNT_THR_EVENT_U0 + description: The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U1 + description: The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U2 + description: The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U3 + description: The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear register + addressOffset: 76 + size: 32 + fields: + - name: CNT_THR_EVENT_U0 + description: Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CNT_THR_EVENT_U1 + description: Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CNT_THR_EVENT_U2 + description: Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CNT_THR_EVENT_U3 + description: Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + dim: 4 + dimIncrement: 4 + name: U%s_STATUS + description: PNCT UNIT%s status register + addressOffset: 80 + size: 32 + fields: + - name: ZERO_MODE + description: "The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive." + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: THRES1 + description: "The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: THRES0 + description: "The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L_LIM + description: "The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: H_LIM + description: "The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ZERO + description: "The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others." + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: CTRL + description: Control register for all counters + addressOffset: 96 + size: 32 + resetValue: 85 + fields: + - name: CNT_RST_U0 + description: "Set this bit to clear unit 0's counter." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U0 + description: "Set this bit to freeze unit 1's counter." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CNT_RST_U1 + description: "Set this bit to clear unit 2's counter." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U1 + description: "Set this bit to freeze unit 3's counter." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CNT_RST_U2 + description: "Set this bit to clear unit 4's counter." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U2 + description: "Set this bit to freeze unit 5's counter." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CNT_RST_U3 + description: "Set this bit to clear unit 6's counter." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U3 + description: "Set this bit to freeze unit 7's counter." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application" + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: PCNT version control register + addressOffset: 252 + size: 32 + resetValue: 419898881 + fields: + - name: DATE + description: This is the PCNT version control register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: PMS + description: Permissions Controller + groupName: PMS + baseAddress: 1061949440 + addressBlock: + - offset: 0 + size: 268 + usage: registers + interrupt: + - name: PMS_PRO_IRAM0_ILG + value: 75 + - name: PMS_PRO_DRAM0_ILG + value: 76 + - name: PMS_PRO_DPORT_ILG + value: 77 + - name: PMS_PRO_AHB_ILG + value: 78 + - name: PMS_PRO_CACHE_ILG + value: 79 + - name: PMS_DMA_APB_I_ILG + value: 80 + - name: PMS_DMA_RX_I_ILG + value: 81 + - name: PMS_DMA_TX_I_ILG + value: 82 + registers: + - register: + name: SDIO_0 + description: SDIO permission control register 0. + addressOffset: 0 + size: 32 + fields: + - name: SDIO_LOCK + description: Lock register. Setting to 1 locks SDIO permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SDIO_1 + description: SDIO permission control register 1. + addressOffset: 4 + size: 32 + fields: + - name: SDIO_DISABLE + description: Setting to 1 disables the SDIO function. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: MAC_DUMP_0 + description: MAC dump permission control register 0. + addressOffset: 8 + size: 32 + fields: + - name: MAC_DUMP_LOCK + description: Lock register. Setting to 1 locks MAC dump permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: MAC_DUMP_1 + description: MAC dump permission control register 1. + addressOffset: 12 + size: 32 + resetValue: 228 + fields: + - name: MAC_DUMP_CONNECT + description: Configure MAC dump connection. + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: PRO_IRAM0_0 + description: IBUS permission control register 0. + addressOffset: 16 + size: 32 + fields: + - name: PRO_IRAM0_LOCK + description: Lock register. Setting to 1 locks IBUS permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: PRO_IRAM0_1 + description: IBUS permission control register 1. + addressOffset: 20 + size: 32 + resetValue: 4095 + fields: + - name: PRO_IRAM0_SRAM_0_F + description: Setting to 1 grants IBUS permission to fetch SRAM Block 0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_IRAM0_SRAM_0_R + description: Setting to 1 grants IBUS permission to read SRAM Block 0. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PRO_IRAM0_SRAM_0_W + description: Setting to 1 grants IBUS permission to write SRAM Block 0. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PRO_IRAM0_SRAM_1_F + description: Setting to 1 grants IBUS permission to fetch SRAM Block 1. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PRO_IRAM0_SRAM_1_R + description: Setting to 1 grants IBUS permission to read SRAM Block 1. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: PRO_IRAM0_SRAM_1_W + description: Setting to 1 grants IBUS permission to write SRAM Block 1. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: PRO_IRAM0_SRAM_2_F + description: Setting to 1 grants IBUS permission to fetch SRAM Block 2. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: PRO_IRAM0_SRAM_2_R + description: Setting to 1 grants IBUS permission to read SRAM Block 2. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: PRO_IRAM0_SRAM_2_W + description: Setting to 1 grants IBUS permission to write SRAM Block 2. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: PRO_IRAM0_SRAM_3_F + description: Setting to 1 grants IBUS permission to fetch SRAM Block 3. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PRO_IRAM0_SRAM_3_R + description: Setting to 1 grants IBUS permission to read SRAM Block 3. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: PRO_IRAM0_SRAM_3_W + description: Setting to 1 grants IBUS permission to write SRAM Block 3. + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: PRO_IRAM0_2 + description: IBUS permission control register 2. + addressOffset: 24 + size: 32 + resetValue: 8257536 + fields: + - name: PRO_IRAM0_SRAM_4_SPLTADDR + description: Configure the split address of SRAM Block 4-21 for IBUS access. + bitOffset: 0 + bitWidth: 17 + access: read-write + - name: PRO_IRAM0_SRAM_4_L_F + description: Setting to 1 grants IBUS permission to fetch SRAM Block 4-21 low address region. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: PRO_IRAM0_SRAM_4_L_R + description: Setting to 1 grants IBUS permission to read SRAM Block 4-21 low address region. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: PRO_IRAM0_SRAM_4_L_W + description: Setting to 1 grants IBUS permission to write SRAM Block 4-21 low address region. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PRO_IRAM0_SRAM_4_H_F + description: Setting to 1 grants IBUS permission to fetch SRAM Block 4-21 high address region. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: PRO_IRAM0_SRAM_4_H_R + description: Setting to 1 grants IBUS permission to read SRAM Block 4-21 high address region. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: PRO_IRAM0_SRAM_4_H_W + description: Setting to 1 grants IBUS permission to write SRAM Block 4-21 high address region. + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: PRO_IRAM0_3 + description: IBUS permission control register 3. + addressOffset: 28 + size: 32 + resetValue: 129024 + fields: + - name: PRO_IRAM0_RTCFAST_SPLTADDR + description: Configure the split address of RTC FAST for IBUS access. + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: PRO_IRAM0_RTCFAST_L_F + description: Setting to 1 grants IBUS permission to fetch RTC FAST low address region. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: PRO_IRAM0_RTCFAST_L_R + description: Setting to 1 grants IBUS permission to read RTC FAST low address region. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PRO_IRAM0_RTCFAST_L_W + description: Setting to 1 grants IBUS permission to write RTC FAST low address region. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: PRO_IRAM0_RTCFAST_H_F + description: Setting to 1 grants IBUS permission to fetch RTC FAST high address region. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PRO_IRAM0_RTCFAST_H_R + description: Setting to 1 grants IBUS permission to read RTC FAST high address region. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: PRO_IRAM0_RTCFAST_H_W + description: Setting to 1 grants IBUS permission to write RTC FAST high address region. + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: PRO_IRAM0_4 + description: IBUS permission control register 4. + addressOffset: 32 + size: 32 + fields: + - name: PRO_IRAM0_ILG_CLR + description: The clear signal for IBUS access interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_IRAM0_ILG_EN + description: The enable signal for IBUS access interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PRO_IRAM0_ILG_INTR + description: IBUS access interrupt signal. + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: PRO_IRAM0_5 + description: IBUS status register. + addressOffset: 36 + size: 32 + fields: + - name: PRO_IRAM0_ILG_ST + description: "Record the illegitimate information of IBUS. [21:2]: store the bits [21:2] of IBUS address. [1]: 1 means data access, 0 means instruction access. [0]: 1 means write operation, 0 means read operation." + bitOffset: 0 + bitWidth: 22 + access: read-only + - register: + name: PRO_DRAM0_0 + description: DBUS permission control register 0. + addressOffset: 40 + size: 32 + fields: + - name: PRO_DRAM0_LOCK + description: Lock register. Setting to 1 locks DBUS0 permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: PRO_DRAM0_1 + description: DBUS permission control register 1. + addressOffset: 44 + size: 32 + resetValue: 503316735 + fields: + - name: PRO_DRAM0_SRAM_0_R + description: Setting to 1 grants DBUS0 permission to read SRAM Block 0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_DRAM0_SRAM_0_W + description: Setting to 1 grants DBUS0 permission to write SRAM Block 0. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PRO_DRAM0_SRAM_1_R + description: Setting to 1 grants DBUS0 permission to read SRAM Block 1. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PRO_DRAM0_SRAM_1_W + description: Setting to 1 grants DBUS0 permission to write SRAM Block 1. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PRO_DRAM0_SRAM_2_R + description: Setting to 1 grants DBUS0 permission to read SRAM Block 2. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: PRO_DRAM0_SRAM_2_W + description: Setting to 1 grants DBUS0 permission to write SRAM Block 2. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: PRO_DRAM0_SRAM_3_R + description: Setting to 1 grants DBUS0 permission to read SRAM Block 3. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: PRO_DRAM0_SRAM_3_W + description: Setting to 1 grants DBUS0 permission to write SRAM Block 3. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: PRO_DRAM0_SRAM_4_SPLTADDR + description: Configure the split address of SRAM Block 4-21 for DBUS0 access. + bitOffset: 8 + bitWidth: 17 + access: read-write + - name: PRO_DRAM0_SRAM_4_L_R + description: Setting to 1 grants DBUS0 permission to read SRAM Block 4-21 low address region. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PRO_DRAM0_SRAM_4_L_W + description: Setting to 1 grants DBUS0 permission to write SRAM Block 4-21 low address region. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: PRO_DRAM0_SRAM_4_H_R + description: Setting to 1 grants DBUS0 permission to read SRAM Block 4-21 high address region. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: PRO_DRAM0_SRAM_4_H_W + description: Setting to 1 grants DBUS0 permission to write SRAM Block 4-21 high address region. + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: PRO_DRAM0_2 + description: DBUS permission control register 2. + addressOffset: 48 + size: 32 + resetValue: 30720 + fields: + - name: PRO_DRAM0_RTCFAST_SPLTADDR + description: Configure the split address of RTC FAST for DBUS0 access. + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: PRO_DRAM0_RTCFAST_L_R + description: Setting to 1 grants DBUS0 permission to read RTC FAST low address region. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: PRO_DRAM0_RTCFAST_L_W + description: Setting to 1 grants DBUS0 permission to write RTC FAST low address region. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PRO_DRAM0_RTCFAST_H_R + description: Setting to 1 grants DBUS0 permission to read RTC FAST high address region. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: PRO_DRAM0_RTCFAST_H_W + description: Setting to 1 grants DBUS0 permission to write RTC FAST high address region. + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: PRO_DRAM0_3 + description: DBUS permission control register 3. + addressOffset: 52 + size: 32 + fields: + - name: PRO_DRAM0_ILG_CLR + description: The clear signal for DBUS0 access interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_DRAM0_ILG_EN + description: The enable signal for DBUS0 access interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PRO_DRAM0_ILG_INTR + description: DBUS0 access interrupt signal. + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: PRO_DRAM0_4 + description: DBUS status register. + addressOffset: 56 + size: 32 + fields: + - name: PRO_DRAM0_ILG_ST + description: "Record the illegitimate information of DBUS. [25:6]: store the bits [21:2] of DBUS address. [5]: 1 means atomic access, 0 means nonatomic access. [4]: 1 means write operation, 0 means read operation. [3:0]: DBUS0 bus byte enables." + bitOffset: 0 + bitWidth: 26 + access: read-only + - register: + name: PRO_DPORT_0 + description: PeriBus1 permission control register 0. + addressOffset: 60 + size: 32 + fields: + - name: PRO_DPORT_LOCK + description: Lock register. Setting to 1 locks PeriBus1 permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: PRO_DPORT_1 + description: PeriBus1 permission control register 1. + addressOffset: 64 + size: 32 + resetValue: 61440 + fields: + - name: PRO_DPORT_APB_PERIPHERAL_FORBID + description: Setting to 1 denies PeriBus1 bus???s access to APB peripheral. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_DPORT_RTCSLOW_SPLTADDR + description: Configure the split address of RTC FAST for PeriBus1 access. + bitOffset: 1 + bitWidth: 11 + access: read-write + - name: PRO_DPORT_RTCSLOW_L_R + description: Setting to 1 grants PeriBus1 permission to read RTC FAST low address region. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PRO_DPORT_RTCSLOW_L_W + description: Setting to 1 grants PeriBus1 permission to write RTC FAST low address region. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: PRO_DPORT_RTCSLOW_H_R + description: Setting to 1 grants PeriBus1 permission to read RTC FAST high address region. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PRO_DPORT_RTCSLOW_H_W + description: Setting to 1 grants PeriBus1 permission to write RTC FAST high address region. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: PRO_DPORT_RESERVE_FIFO_VALID + description: Configure whether to enable read protection for user-configured FIFO address. + bitOffset: 16 + bitWidth: 4 + access: read-write + - register: + name: PRO_DPORT_2 + description: PeriBus1 permission control register 2. + addressOffset: 68 + size: 32 + fields: + - name: PRO_DPORT_RESERVE_FIFO_0 + description: Configure read-protection address 0. + bitOffset: 0 + bitWidth: 18 + access: read-write + - register: + name: PRO_DPORT_3 + description: PeriBus1 permission control register 3. + addressOffset: 72 + size: 32 + fields: + - name: PRO_DPORT_RESERVE_FIFO_1 + description: Configure read-protection address 1. + bitOffset: 0 + bitWidth: 18 + access: read-write + - register: + name: PRO_DPORT_4 + description: PeriBus1 permission control register 4. + addressOffset: 76 + size: 32 + fields: + - name: PRO_DPORT_RESERVE_FIFO_2 + description: Configure read-protection address 2. + bitOffset: 0 + bitWidth: 18 + access: read-write + - register: + name: PRO_DPORT_5 + description: PeriBus1 permission control register 5. + addressOffset: 80 + size: 32 + fields: + - name: PRO_DPORT_RESERVE_FIFO_3 + description: Configure read-protection address 3. + bitOffset: 0 + bitWidth: 18 + access: read-write + - register: + name: PRO_DPORT_6 + description: PeriBus1 permission control register 6. + addressOffset: 84 + size: 32 + fields: + - name: PRO_DPORT_ILG_CLR + description: The clear signal for PeriBus1 access interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_DPORT_ILG_EN + description: The enable signal for PeriBus1 access interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PRO_DPORT_ILG_INTR + description: PeriBus1 access interrupt signal. + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: PRO_DPORT_7 + description: PeriBus1 status register. + addressOffset: 88 + size: 32 + fields: + - name: PRO_DPORT_ILG_ST + description: "Record the illegitimate information of PeriBus1. [25:6]: store the bits [21:2] of PeriBus1 address. [5]: 1 means atomic access, 0 means nonatomic access. [4]: if bits [31:22] of PeriBus1 address are 0xfd, then the bit value is 1, otherwise it is 0. [3:0]: PeriBus1 byte enables." + bitOffset: 0 + bitWidth: 26 + access: read-only + - register: + name: PRO_AHB_0 + description: PeriBus2 permission control register 0. + addressOffset: 92 + size: 32 + fields: + - name: PRO_AHB_LOCK + description: Lock register. Setting to 1 locks PeriBus2 permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: PRO_AHB_1 + description: PeriBus2 permission control register 1. + addressOffset: 96 + size: 32 + resetValue: 129024 + fields: + - name: PRO_AHB_RTCSLOW_0_SPLTADDR + description: Configure the split address of RTCSlow_0 for PeriBus2 access. + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: PRO_AHB_RTCSLOW_0_L_F + description: Setting to 1 grants PeriBus2 permission to fetch RTCSlow_0 low address region. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: PRO_AHB_RTCSLOW_0_L_R + description: Setting to 1 grants PeriBus2 permission to read RTCSlow_0 low address region. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PRO_AHB_RTCSLOW_0_L_W + description: Setting to 1 grants PeriBus2 permission to write RTCSlow_0 low address region. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: PRO_AHB_RTCSLOW_0_H_F + description: Setting to 1 grants PeriBus2 permission to fetch RTCSlow_0 high address region. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PRO_AHB_RTCSLOW_0_H_R + description: Setting to 1 grants PeriBus2 permission to read RTCSlow_0 high address region. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: PRO_AHB_RTCSLOW_0_H_W + description: Setting to 1 grants PeriBus2 permission to write RTCSlow_0 high address region. + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: PRO_AHB_2 + description: PeriBus2 permission control register 2. + addressOffset: 100 + size: 32 + resetValue: 129024 + fields: + - name: PRO_AHB_RTCSLOW_1_SPLTADDR + description: Configure the split address of RTCSlow_1 for PeriBus2 access. + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: PRO_AHB_RTCSLOW_1_L_F + description: Setting to 1 grants PeriBus2 permission to fetch RTCSlow_1 low address region. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: PRO_AHB_RTCSLOW_1_L_R + description: Setting to 1 grants PeriBus2 permission to read RTCSlow_1 low address region. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PRO_AHB_RTCSLOW_1_L_W + description: Setting to 1 grants PeriBus2 permission to write RTCSlow_1 low address region. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: PRO_AHB_RTCSLOW_1_H_F + description: Setting to 1 grants PeriBus2 permission to fetch RTCSlow_1 high address region. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PRO_AHB_RTCSLOW_1_H_R + description: Setting to 1 grants PeriBus2 permission to read RTCSlow_1 high address region. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: PRO_AHB_RTCSLOW_1_H_W + description: Setting to 1 grants PeriBus2 permission to write RTCSlow_1 high address region. + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: PRO_AHB_3 + description: PeriBus2 permission control register 3. + addressOffset: 104 + size: 32 + fields: + - name: PRO_AHB_ILG_CLR + description: The clear signal for PeriBus2 access interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_AHB_ILG_EN + description: The enable signal for PeriBus2 access interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PRO_AHB_ILG_INTR + description: PeriBus2 access interrupt signal. + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: PRO_AHB_4 + description: PeriBus2 status register. + addressOffset: 108 + size: 32 + fields: + - name: PRO_AHB_ILG_ST + description: "Record the illegitimate information of PeriBus2. [31:2]: store the bits [31:2] of PeriBus2 address. [1]: 1 means data access, 0 means instruction access. [0]: 1 means write operation, 0 means read operation." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PRO_TRACE_0 + description: Trace memory permission control register 0. + addressOffset: 112 + size: 32 + fields: + - name: PRO_TRACE_LOCK + description: Lock register. Setting to 1 locks trace function permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: PRO_TRACE_1 + description: Trace memory permission control register 1. + addressOffset: 116 + size: 32 + fields: + - name: PRO_TRACE_DISABLE + description: Setting to 1 disables the trace memory function. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: PRO_CACHE_0 + description: Cache permission control register 0. + addressOffset: 120 + size: 32 + fields: + - name: PRO_CACHE_LOCK + description: Lock register. Setting to 1 locks cache permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: PRO_CACHE_1 + description: Cache permission control register 1. + addressOffset: 124 + size: 32 + fields: + - name: PRO_CACHE_CONNECT + description: Configure which SRAM Block will be occupied by Icache or Dcache. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: PRO_CACHE_2 + description: Cache permission control register 2. + addressOffset: 128 + size: 32 + fields: + - name: PRO_CACHE_ILG_CLR + description: The clear signal for cache access interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_ILG_EN + description: The enable signal for cache access interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_ILG_INTR + description: Cache access interrupt signal. + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: PRO_CACHE_3 + description: Icache status register. + addressOffset: 132 + size: 32 + fields: + - name: PRO_CACHE_ILG_ST_I + description: "Record the illegitimate information of ICache to access memory. [16]: access enable, active low. [15:4]: store the bits [11:0] of address. [3:0]: Icache bus write byte enables, active low." + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: PRO_CACHE_4 + description: Dcache status register. + addressOffset: 136 + size: 32 + fields: + - name: PRO_CACHE_ILG_ST_D + description: "Record the illegitimate information of Dcache to access memory. [16]: access enable, active low. [15:4]: store the bits [11:0] of address. [3:0]: Dcache bus write byte enables, active low." + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: DMA_APB_I_0 + description: Internal DMA permission control register 0. + addressOffset: 140 + size: 32 + fields: + - name: DMA_APB_I_LOCK + description: Lock register. Setting to 1 locks internal DMA permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APB_I_1 + description: Internal DMA permission control register 1. + addressOffset: 144 + size: 32 + resetValue: 503316735 + fields: + - name: DMA_APB_I_SRAM_0_R + description: Setting to 1 grants internal DMA permission to read SRAM Block 0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DMA_APB_I_SRAM_0_W + description: Setting to 1 grants internal DMA permission to write SRAM Block 0. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DMA_APB_I_SRAM_1_R + description: Setting to 1 grants internal DMA permission to read SRAM Block 1. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DMA_APB_I_SRAM_1_W + description: Setting to 1 grants internal DMA permission to write SRAM Block 1. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DMA_APB_I_SRAM_2_R + description: Setting to 1 grants internal DMA permission to read SRAM Block 2. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DMA_APB_I_SRAM_2_W + description: Setting to 1 grants internal DMA permission to write SRAM Block 2. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DMA_APB_I_SRAM_3_R + description: Setting to 1 grants internal DMA permission to read SRAM Block 3. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: DMA_APB_I_SRAM_3_W + description: Setting to 1 grants internal DMA permission to write SRAM Block 3. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DMA_APB_I_SRAM_4_SPLTADDR + description: Configure the split address of SRAM Block 4-21 for internal DMA access. + bitOffset: 8 + bitWidth: 17 + access: read-write + - name: DMA_APB_I_SRAM_4_L_R + description: Setting to 1 grants internal DMA permission to read SRAM Block 4-21 low address region. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: DMA_APB_I_SRAM_4_L_W + description: Setting to 1 grants internal DMA permission to write SRAM Block 4-21 low address region. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: DMA_APB_I_SRAM_4_H_R + description: Setting to 1 grants internal DMA permission to read SRAM Block 4-21 high address region. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: DMA_APB_I_SRAM_4_H_W + description: Setting to 1 grants internal DMA permission to write SRAM Block 4-21 high address region. + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: DMA_APB_I_2 + description: Internal DMA permission control register 2. + addressOffset: 148 + size: 32 + fields: + - name: DMA_APB_I_ILG_CLR + description: The clear signal for internal DMA access interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DMA_APB_I_ILG_EN + description: The enable signal for internal DMA access interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DMA_APB_I_ILG_INTR + description: Internal DMA access interrupt signal. + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: DMA_APB_I_3 + description: Internal DMA status register. + addressOffset: 152 + size: 32 + fields: + - name: DMA_APB_I_ILG_ST + description: "Record the illegitimate information of Internal DMA. [22:6]: store the bits [18:2] of address. [5]: if bits [31:19] of address are 0x7ff, then the bit value is 1, otherwise it is 0. [4]: 1 means write operation, 0 means read operation. [3:0]: Internal DMA bus byte enables." + bitOffset: 0 + bitWidth: 23 + access: read-only + - register: + name: DMA_RX_I_0 + description: RX Copy DMA permission control register 0. + addressOffset: 156 + size: 32 + fields: + - name: DMA_RX_I_LOCK + description: Lock register. Setting to 1 locks RX Copy DMA permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_RX_I_1 + description: RX Copy DMA permission control register 1. + addressOffset: 160 + size: 32 + resetValue: 503316735 + fields: + - name: DMA_RX_I_SRAM_0_R + description: Setting to 1 grants RX Copy DMA permission to read SRAM Block 0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DMA_RX_I_SRAM_0_W + description: Setting to 1 grants RX Copy DMA permission to write SRAM Block 0. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DMA_RX_I_SRAM_1_R + description: Setting to 1 grants RX Copy DMA permission to read SRAM Block 1. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DMA_RX_I_SRAM_1_W + description: Setting to 1 grants RX Copy DMA permission to write SRAM Block 1. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DMA_RX_I_SRAM_2_R + description: Setting to 1 grants RX Copy DMA permission to read SRAM Block 2. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DMA_RX_I_SRAM_2_W + description: Setting to 1 grants RX Copy DMA permission to write SRAM Block 2. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DMA_RX_I_SRAM_3_R + description: Setting to 1 grants RX Copy DMA permission to read SRAM Block 3. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: DMA_RX_I_SRAM_3_W + description: Setting to 1 grants RX Copy DMA permission to write SRAM Block 3. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DMA_RX_I_SRAM_4_SPLTADDR + description: Configure the split address of SRAM Block 4-21 for RX Copy DMA access. + bitOffset: 8 + bitWidth: 17 + access: read-write + - name: DMA_RX_I_SRAM_4_L_R + description: Setting to 1 grants RX Copy DMA permission to read SRAM Block 4-21 low address region. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: DMA_RX_I_SRAM_4_L_W + description: Setting to 1 grants RX Copy DMA permission to write SRAM Block 4-21 low address region. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: DMA_RX_I_SRAM_4_H_R + description: Setting to 1 grants RX Copy DMA permission to read SRAM Block 4-21 high address region. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: DMA_RX_I_SRAM_4_H_W + description: Setting to 1 grants RX Copy DMA permission to write SRAM Block 4~21 high address region. + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: DMA_RX_I_2 + description: RX Copy DMA permission control register 2. + addressOffset: 164 + size: 32 + fields: + - name: DMA_RX_I_ILG_CLR + description: The clear signal for RX Copy DMA access interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DMA_RX_I_ILG_EN + description: The enable signal for RX Copy DMA access interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DMA_RX_I_ILG_INTR + description: RX Copy DMA access interrupt signal. + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: DMA_RX_I_3 + description: RX Copy DMA status register. + addressOffset: 168 + size: 32 + fields: + - name: DMA_RX_I_ILG_ST + description: "Record the illegitimate information of RX Copy DMA. [22:6]: store the bits [18:2] of address. [5]: if bits [31:19] of address are 0x7ff, then the bit value is 1, otherwise it is 0. [4]: 1 means write operation, 0 means read operation. [3:0]: RX Copy DMA bus byte enables." + bitOffset: 0 + bitWidth: 23 + access: read-only + - register: + name: DMA_TX_I_0 + description: TX Copy DMA permission control register 0. + addressOffset: 172 + size: 32 + fields: + - name: DMA_TX_I_LOCK + description: Lock register. Setting to 1 locks TX Copy DMA permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_TX_I_1 + description: TX Copy DMA permission control register 1. + addressOffset: 176 + size: 32 + resetValue: 503316735 + fields: + - name: DMA_TX_I_SRAM_0_R + description: Setting to 1 grants TX Copy DMA permission to read SRAM Block 0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DMA_TX_I_SRAM_0_W + description: Setting to 1 grants TX Copy DMA permission to write SRAM Block 0. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DMA_TX_I_SRAM_1_R + description: Setting to 1 grants TX Copy DMA permission to read SRAM Block 1. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DMA_TX_I_SRAM_1_W + description: Setting to 1 grants TX Copy DMA permission to write SRAM Block 1. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DMA_TX_I_SRAM_2_R + description: Setting to 1 grants TX Copy DMA permission to read SRAM Block 2. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DMA_TX_I_SRAM_2_W + description: Setting to 1 grants TX Copy DMA permission to write SRAM Block 2. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DMA_TX_I_SRAM_3_R + description: Setting to 1 grants TX Copy DMA permission to read SRAM Block 3. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: DMA_TX_I_SRAM_3_W + description: Setting to 1 grants TX Copy DMA permission to write SRAM Block 3. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DMA_TX_I_SRAM_4_SPLTADDR + description: Configure the split address of SRAM Block 4-21 for TX Copy DMA access. + bitOffset: 8 + bitWidth: 17 + access: read-write + - name: DMA_TX_I_SRAM_4_L_R + description: Setting to 1 grants TX Copy DMA permission to read SRAM Block 4-21 low address region. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: DMA_TX_I_SRAM_4_L_W + description: Setting to 1 grants TX Copy DMA permission to write SRAM Block 4-21 low address region. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: DMA_TX_I_SRAM_4_H_R + description: Setting to 1 grants TX Copy DMA permission to read SRAM Block 4-21 high address region. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: DMA_TX_I_SRAM_4_H_W + description: Setting to 1 grants TX Copy DMA permission to write SRAM Block 4-21 high address region. + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: DMA_TX_I_2 + description: TX Copy DMA permission control register 2. + addressOffset: 180 + size: 32 + fields: + - name: DMA_TX_I_ILG_CLR + description: The clear signal for TX Copy DMA access interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DMA_TX_I_ILG_EN + description: The enable signal for TX Copy DMA access interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DMA_TX_I_ILG_INTR + description: TX Copy DMA access interrupt signal. + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: DMA_TX_I_3 + description: TX Copy DMA status register. + addressOffset: 184 + size: 32 + fields: + - name: DMA_TX_I_ILG_ST + description: "Record the illegitimate information of TX Copy DMA. [22:6]: store the bits [18:2] of address. [5]: if bits [31:19] of address are 0x7ff, then the bit value is 1, otherwise it is 0. [4]: 1 means write operation, 0 means read operation. [3:0]: TX Copy DMA bus byte enables." + bitOffset: 0 + bitWidth: 23 + access: read-only + - register: + name: PRO_BOOT_LOCATION_0 + description: Boot permission control register 0. + addressOffset: 188 + size: 32 + fields: + - name: PRO_BOOT_LOCATION_LOCK + description: Lock register. Setting to 1 locks boot remap permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: PRO_BOOT_LOCATION_1 + description: Boot permission control register 1. + addressOffset: 192 + size: 32 + fields: + - name: PRO_BOOT_REMAP + description: "If set to 1, enable boot remap function." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CACHE_SOURCE_0 + description: Cache access permission control register 0. + addressOffset: 196 + size: 32 + fields: + - name: CACHE_SOURCE_LOCK + description: Lock register. Setting to 1 locks cache access permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CACHE_SOURCE_1 + description: Cache access permission control register 1. + addressOffset: 200 + size: 32 + fields: + - name: PRO_CACHE_I_SOURCE_PRO_IRAM1 + description: xx + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_I_SOURCE_PRO_IROM0 + description: xx + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_I_SOURCE_PRO_DROM0 + description: xx + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_D_SOURCE_PRO_DRAM0 + description: xx + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_D_SOURCE_PRO_DPORT + description: xx + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_D_SOURCE_PRO_DROM0 + description: xx + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: APB_PERIPHERAL_0 + description: Peripheral access permission control register 0. + addressOffset: 204 + size: 32 + fields: + - name: APB_PERIPHERAL_LOCK + description: Lock register. Setting to 1 locks TX Copy DMA permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: APB_PERIPHERAL_1 + description: Peripheral access permission control register 1. + addressOffset: 208 + size: 32 + resetValue: 1 + fields: + - name: APB_PERIPHERAL_SPLIT_BURST + description: Setting to 1 splits the data phase of the last access and the address phase of following access. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: OCCUPY_0 + description: Occupy permission control register 0. + addressOffset: 212 + size: 32 + fields: + - name: OCCUPY_LOCK + description: Lock register. Setting to 1 locks occupy permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: OCCUPY_1 + description: Occupy permission control register 1. + addressOffset: 216 + size: 32 + fields: + - name: OCCUPY_CACHE + description: Configure whether SRAM Block 0-3 is used as cache memory. + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: OCCUPY_2 + description: Occupy permission control register 2. + addressOffset: 220 + size: 32 + fields: + - name: OCCUPY_MAC_DUMP + description: Configure whether SRAM Block 18-21 is used as mac dump. + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: OCCUPY_3 + description: Occupy permission control register 3. + addressOffset: 224 + size: 32 + fields: + - name: OCCUPY_PRO_TRACE + description: Configure one block of SRAM Block 4-21 is used as trace memory. + bitOffset: 0 + bitWidth: 18 + access: read-write + - register: + name: CACHE_TAG_ACCESS_0 + description: Cache tag permission control register 0. + addressOffset: 228 + size: 32 + fields: + - name: CACHE_TAG_ACCESS_LOCK + description: Lock register. Setting to 1 locks cache tag permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CACHE_TAG_ACCESS_1 + description: Cache tag permission control register 1. + addressOffset: 232 + size: 32 + fields: + - name: PRO_I_TAG_RD_ACS + description: Setting to 1 permits read access to Icache tag memory. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_I_TAG_WR_ACS + description: Setting to 1 permits write access to Icache tag memory. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PRO_D_TAG_RD_ACS + description: Setting to 1 permits read access to Dcache tag memory. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PRO_D_TAG_WR_ACS + description: Setting to 1 permits write access to Dcache tag memory. + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: CACHE_MMU_ACCESS_0 + description: Cache MMU permission control register 0. + addressOffset: 236 + size: 32 + fields: + - name: CACHE_MMU_ACCESS_LOCK + description: Lock register. Setting to 1 locks cache MMU permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CACHE_MMU_ACCESS_1 + description: Cache MMU permission control register 1. + addressOffset: 240 + size: 32 + resetValue: 3 + fields: + - name: PRO_MMU_RD_ACS + description: Setting to 1 permits read access to MMU memory. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_MMU_WR_ACS + description: Setting to 1 permits write access to MMU memory. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: APB_PERIPHERAL_INTR + description: PeribBus2 permission control register. + addressOffset: 244 + size: 32 + fields: + - name: APB_PERI_BYTE_ERROR_CLR + description: The clear signal for APB peripheral interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: APB_PERI_BYTE_ERROR_EN + description: The enable signal for APB peripheral access interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: APB_PERI_BYTE_ERROR_INTR + description: APB peripheral access interrupt signal. + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: APB_PERIPHERAL_STATUS + description: PeribBus2 peripheral access status register. + addressOffset: 248 + size: 32 + fields: + - name: APB_PERI_BYTE_ERROR_ADDR + description: Record the illegitimate address of APB peripheral. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CPU_PERIPHERAL_INTR + description: PeribBus1 permission control register. + addressOffset: 252 + size: 32 + fields: + - name: CPU_PERI_BYTE_ERROR_CLR + description: The clear signal for CPU peripheral access interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CPU_PERI_BYTE_ERROR_EN + description: The enable signal for CPU peripheral access interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CPU_PERI_BYTE_ERROR_INTR + description: CPU peripheral access interrupt signal. + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: CPU_PERIPHERAL_STATUS + description: PeribBus1 peripheral access status register. + addressOffset: 256 + size: 32 + fields: + - name: CPU_PERI_BYTE_ERROR_ADDR + description: Record the illegitimate address of CPU peripheral. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CLOCK_GATE + description: Clock gate register of permission control. + addressOffset: 260 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: Enable the clock of permission control module when set to 1. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control register. + addressOffset: 4092 + size: 32 + resetValue: 26235024 + fields: + - name: DATE + description: Version control register. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: RMT + description: Remote Control + groupName: RMT + baseAddress: 1061249024 + addressBlock: + - offset: 0 + size: 160 + usage: registers + interrupt: + - name: RMT + value: 50 + registers: + - register: + dim: 4 + dimIncrement: 4 + name: CH%sDATA + description: The read and write data register for CHANNEL%s by apb fifo access. + addressOffset: 0 + size: 32 + fields: + - name: DATA + description: The read and write data register for CHANNEL%s by apb fifo access. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 4 + dimIncrement: 8 + name: CH%sCONF0 + description: Channel %s configure register 0 + addressOffset: 16 + size: 32 + resetValue: 957349890 + fields: + - name: DIV_CNT + description: This register is used to configure the divider for clock of CHANNEL%s. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: IDLE_THRES + description: "When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished." + bitOffset: 8 + bitWidth: 16 + access: read-write + - name: MEM_SIZE + description: This register is used to configure the maximum size of memory allocated to CHANNEL%s. + bitOffset: 24 + bitWidth: 3 + access: read-write + - name: CARRIER_EFF_EN + description: "1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: CARRIER_EN + description: "This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CARRIER_OUT_LV + description: "This bit is used to configure the position of carrier wave for CHANNEL%s.\n\n1'h0: add carrier wave on low level.\n\n1'h1: add carrier wave on high level." + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + dim: 4 + dimIncrement: 8 + name: CH%sCONF1 + description: Channel %s configure register 1 + addressOffset: 20 + size: 32 + resetValue: 3872 + fields: + - name: TX_START + description: Set this bit to start sending data on CHANNEL%s. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_EN + description: Set this bit to enable receiver to receive data on CHANNEL%s. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MEM_WR_RST + description: Set this bit to reset write ram address for CHANNEL%s by accessing receiver. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: MEM_RD_RST + description: Set this bit to reset read ram address for CHANNEL%s by accessing transmitter. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: APB_MEM_RST + description: Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: MEM_OWNER + description: "This register marks the ownership of CHANNEL%s's ram block.\n\n1'h1: Receiver is using the ram. \n\n1'h0: Transmitter is using the ram." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TX_CONTI_MODE + description: Set this bit to restart transmission from the first data to the last data in CHANNEL%s. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_FILTER_EN + description: "This is the receive filter's enable bit for CHANNEL%s." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RX_FILTER_THRES + description: Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode). + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: CHK_RX_CARRIER_EN + description: Set this bit to enable memory loop read mode when carrier modulation is enabled for channel %s. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: REF_ALWAYS_ON + description: "This bit is used to select the base clock for CHANNEL%s.\n\n1'h1: clk_apb 1'h0:clk_ref" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: IDLE_OUT_LV + description: This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: IDLE_OUT_EN + description: This is the output enable-control bit for CHANNEL%s in IDLE state. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: TX_STOP + description: Set this bit to stop the transmitter of CHANNEL%s sending data out. + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: CH%sSTATUS + description: Channel %s status register + addressOffset: 48 + size: 32 + fields: + - name: MEM_WADDR_EX + description: This register records the memory address offset when receiver of CHANNEL%s is using the RAM. + bitOffset: 0 + bitWidth: 9 + access: read-only + - name: MEM_RADDR_EX + description: This register records the memory address offset when transmitter of CHANNEL%s is using the RAM. + bitOffset: 10 + bitWidth: 9 + access: read-only + - name: STATE + description: This register records the FSM status of CHANNEL%s. + bitOffset: 20 + bitWidth: 3 + access: read-only + - name: MEM_OWNER_ERR + description: This status bit will be set when the ownership of memory block is wrong. + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: MEM_FULL + description: This status bit will be set if the receiver receives more data than the memory size. + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: MEM_EMPTY + description: This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: APB_MEM_WR_ERR + description: This status bit will be set if the offset address out of memory size when writes via APB bus. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: APB_MEM_RD_ERR + description: This status bit will be set if the offset address out of memory size when reads via APB bus. + bitOffset: 27 + bitWidth: 1 + access: read-only + - register: + dim: 4 + dimIncrement: 4 + name: CH%sADDR + description: Channel %s address register + addressOffset: 64 + size: 32 + fields: + - name: APB_MEM_WADDR + description: This register records the memory address offset when writes RAM over APB bus. + bitOffset: 0 + bitWidth: 9 + access: read-only + - name: APB_MEM_RADDR + description: This register records the memory address offset when reads RAM over APB bus. + bitOffset: 10 + bitWidth: 9 + access: read-only + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 80 + size: 32 + fields: + - dim: 4 + dimIncrement: 3 + dimIndex: "0,1,2,3" + name: CH%s_TX_END + description: The interrupt raw bit for CHANNEL%s. Triggered when transmission done. + bitOffset: 0 + bitWidth: 1 + access: read-only + - dim: 4 + dimIncrement: 3 + dimIndex: "0,1,2,3" + name: CH%s_RX_END + description: The interrupt raw bit for CHANNEL%s. Triggered when reception done. + bitOffset: 1 + bitWidth: 1 + access: read-only + - dim: 4 + dimIncrement: 3 + dimIndex: "0,1,2,3" + name: CH%s_ERR + description: The interrupt raw bit for CHANNEL%s. Triggered when error occurs. + bitOffset: 2 + bitWidth: 1 + access: read-only + - dim: 4 + dimIncrement: 1 + dimIndex: "0,1,2,3" + name: CH%s_TX_THR_EVENT + description: The interrupt raw bit for CHANNEL%s. Triggered when transmitter sent more data than configured value. + bitOffset: 12 + bitWidth: 1 + access: read-only + - dim: 4 + dimIncrement: 1 + dimIndex: "0,1,2,3" + name: CH%s_TX_LOOP + description: The interrupt raw bit for CHANNEL%s. Triggered when the loop count reaches the configured threshold value. + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 84 + size: 32 + fields: + - dim: 4 + dimIncrement: 3 + dimIndex: "0,1,2,3" + name: CH%s_TX_END + description: The masked interrupt status bit for CH%s_TX_END_INT. + bitOffset: 0 + bitWidth: 1 + access: read-only + - dim: 4 + dimIncrement: 3 + dimIndex: "0,1,2,3" + name: CH%s_RX_END + description: The masked interrupt status bit for CH%s_RX_END_INT. + bitOffset: 1 + bitWidth: 1 + access: read-only + - dim: 4 + dimIncrement: 3 + dimIndex: "0,1,2,3" + name: CH%s_ERR + description: The masked interrupt status bit for CH%s_ERR_INT. + bitOffset: 2 + bitWidth: 1 + access: read-only + - dim: 4 + dimIncrement: 1 + dimIndex: "0,1,2,3" + name: CH%s_TX_THR_EVENT + description: The masked interrupt status bit for CH%s_TX_THR_EVENT_INT. + bitOffset: 12 + bitWidth: 1 + access: read-only + - dim: 4 + dimIncrement: 1 + dimIndex: "0,1,2,3" + name: CH%s_TX_LOOP + description: The masked interrupt status bit for CH%s_TX_LOOP_INT. + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 88 + size: 32 + fields: + - dim: 4 + dimIncrement: 3 + dimIndex: "0,1,2,3" + name: CH%s_TX_END + description: The interrupt enabled bit for CH%s_TX_END_INT. + bitOffset: 0 + bitWidth: 1 + access: read-write + - dim: 4 + dimIncrement: 3 + dimIndex: "0,1,2,3" + name: CH%s_RX_END + description: The interrupt enabled bit for CH%s_RX_END_INT. + bitOffset: 1 + bitWidth: 1 + access: read-write + - dim: 4 + dimIncrement: 3 + dimIndex: "0,1,2,3" + name: CH%s_ERR + description: The interrupt enabled bit for CH%s_ERR_INT. + bitOffset: 2 + bitWidth: 1 + access: read-write + - dim: 4 + dimIncrement: 1 + dimIndex: "0,1,2,3" + name: CH%s_TX_THR_EVENT + description: The interrupt enabled bit for CH%s_TX_THR_EVENT_INT. + bitOffset: 12 + bitWidth: 1 + access: read-write + - dim: 4 + dimIncrement: 1 + dimIndex: "0,1,2,3" + name: CH%s_TX_LOOP + description: The interrupt enabled bit for CH%s_TX_LOOP_INT. + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 92 + size: 32 + fields: + - dim: 4 + dimIncrement: 3 + dimIndex: "0,1,2,3" + name: CH%s_TX_END + description: Set this bit to clear the CH%s_TX_END_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - dim: 4 + dimIncrement: 3 + dimIndex: "0,1,2,3" + name: CH%s_RX_END + description: Set this bit to clear the CH%s_RX_END_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - dim: 4 + dimIncrement: 3 + dimIndex: "0,1,2,3" + name: CH%s_ERR + description: Set this bit to clear the CH%s_ERR_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - dim: 4 + dimIncrement: 1 + dimIndex: "0,1,2,3" + name: CH%s_TX_THR_EVENT + description: Set this bit to clear the CH%s_TX_THR_EVENT_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - dim: 4 + dimIncrement: 1 + dimIndex: "0,1,2,3" + name: CH%s_TX_LOOP + description: Set this bit to clear the CH%s_TX_LOOP_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - register: + dim: 4 + dimIncrement: 4 + name: CH%sCARRIER_DUTY + description: Channel %s duty cycle configuration register + addressOffset: 96 + size: 32 + resetValue: 4194368 + fields: + - name: CARRIER_LOW + description: "This register is used to configure carrier wave 's low level clock period for CHANNEL%s." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CARRIER_HIGH + description: "This register is used to configure carrier wave 's high level clock period for CHANNEL%s." + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: CH%s_TX_LIM + description: Channel %s Tx event configuration register + addressOffset: 112 + size: 32 + resetValue: 128 + fields: + - name: TX_LIM + description: This register is used to configure the maximum entries that CHANNEL%s can send out. + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: TX_LOOP_NUM + description: This register is used to configure the maximum loop count when tx_conti_mode is valid. + bitOffset: 9 + bitWidth: 10 + access: read-write + - name: TX_LOOP_CNT_EN + description: This register is the enabled bit for loop count. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: LOOP_COUNT_RESET + description: This register is used to reset the loop count when tx_conti_mode is valid. + bitOffset: 20 + bitWidth: 1 + access: write-only + - register: + name: APB_CONF + description: RMT apb configuration register + addressOffset: 128 + size: 32 + resetValue: 4 + fields: + - name: APB_FIFO_MASK + description: "1'h1: access memory directly. 1'h0: access memory by FIFO." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_TX_WRAP_EN + description: "This is the enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MEM_CLK_FORCE_ON + description: Set this bit to enable the clock for RMT memory. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PD + description: Set this bit to power down RMT memory. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PU + description: "1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TX_SIM + description: RMT TX synchronous register + addressOffset: 132 + size: 32 + fields: + - name: CH0 + description: Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CH1 + description: Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CH2 + description: Set this bit to enable CHANNEL2 to start sending data synchronously with other enabled channels. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CH3 + description: Set this bit to enable CHANNEL3 to start sending data synchronously with other enabled channels. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: EN + description: This register is used to enable multiple of channels to start sending data synchronously. + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: REF_CNT_RST + description: RMT clock divider reset register + addressOffset: 136 + size: 32 + fields: + - name: CH0 + description: This register is used to reset the clock divider of CHANNEL0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CH1 + description: This register is used to reset the clock divider of CHANNEL1. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CH2 + description: This register is used to reset the clock divider of CHANNEL2. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CH3 + description: This register is used to reset the clock divider of CHANNEL3. + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: CH%s_RX_CARRIER_RM + description: Channel %s carrier remove register + addressOffset: 140 + size: 32 + fields: + - name: CARRIER_LOW_THRES + description: The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CARRIER_HIGH_THRES + description: The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: DATE + description: RMT version register + addressOffset: 252 + size: 32 + resetValue: 419898881 + fields: + - name: DATE + description: This is the version register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: RNG + description: Hardware Random Number Generator + groupName: RNG + baseAddress: 1610829824 + addressBlock: + - offset: 0 + size: 4 + usage: registers + registers: + - register: + name: DATA + description: Random number data + addressOffset: 272 + size: 32 + access: read-only + - name: RSA + description: RSA (Rivest Shamir Adleman) Accelerator + groupName: RSA + baseAddress: 1610858496 + addressBlock: + - offset: 0 + size: 52 + usage: registers + interrupt: + - name: RSA + value: 54 + registers: + - register: + name: M_PRIME + description: "Register to store M'" + addressOffset: 2048 + size: 32 + fields: + - name: M_PRIME + description: "Stores M'." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: MODE + description: RSA length mode + addressOffset: 2052 + size: 32 + fields: + - name: MODE + description: Stores the mode of modular exponentiation. + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: CLEAN + description: RSA clean register + addressOffset: 2056 + size: 32 + fields: + - name: CLEAN + description: The content of this bit is 1 when memories complete initialization. + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: MODEXP_START + description: Modular exponentiation starting bit + addressOffset: 2060 + size: 32 + fields: + - name: MODEXP_START + description: Set this bit to 1 to start the modular exponentiation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: MODMULT_START + description: Modular multiplication starting bit + addressOffset: 2064 + size: 32 + fields: + - name: MODMULT_START + description: Set this bit to 1 to start the modular multiplication. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: MULT_START + description: Normal multiplication starting bit + addressOffset: 2068 + size: 32 + fields: + - name: MULT_START + description: Set this bit to 1 to start the multiplication. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: IDLE + description: RSA idle register + addressOffset: 2072 + size: 32 + fields: + - name: IDLE + description: The content of this bit is 1 when the RSA accelerator is idle. + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: CLEAR_INTERRUPT + description: RSA clear interrupt register + addressOffset: 2076 + size: 32 + fields: + - name: CLEAR_INTERRUPT + description: Set this bit to 1 to clear the RSA interrupts. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: CONSTANT_TIME + description: The constant_time option + addressOffset: 2080 + size: 32 + resetValue: 1 + fields: + - name: CONSTANT_TIME + description: Set this bit to 0 to enable the acceleration option of constant_time for modular exponentiation. Set to 1 to disable the acceleration (by default). + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SEARCH_ENABLE + description: The search option + addressOffset: 2084 + size: 32 + fields: + - name: SEARCH_ENABLE + description: Set this bit to 1 to enable the acceleration option of search for modular exponentiation. Set to 0 to disable the acceleration (by default). + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SEARCH_POS + description: The search position + addressOffset: 2088 + size: 32 + fields: + - name: SEARCH_POS + description: Is used to configure the starting address when the acceleration option of search is used. + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: INTERRUPT_ENA + description: RSA interrupt enable register + addressOffset: 2092 + size: 32 + resetValue: 1 + fields: + - name: INTERRUPT_ENA + description: Set this bit to 1 to enable the RSA interrupt. This option is enabled by default. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 2096 + size: 32 + resetValue: 538510373 + fields: + - name: DATE + description: Version control register. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + dim: 128 + dimIncrement: 4 + name: "M_MEM[%s]" + description: Represents M + addressOffset: 0 + size: 32 + access: write-only + - register: + dim: 128 + dimIncrement: 4 + name: "Z_MEM[%s]" + description: Represents Z + addressOffset: 512 + size: 32 + access: read-write + - register: + dim: 128 + dimIncrement: 4 + name: "Y_MEM[%s]" + description: Represents Y + addressOffset: 1024 + size: 32 + access: write-only + - register: + dim: 128 + dimIncrement: 4 + name: "X_MEM[%s]" + description: Represents X + addressOffset: 1536 + size: 32 + access: write-only + - name: RTC_IO + description: Low-power Input/Output + groupName: RTCIO + baseAddress: 1061192704 + addressBlock: + - offset: 0 + size: 240 + usage: registers + registers: + - register: + name: RTC_GPIO_OUT + description: RTC GPIO output register + addressOffset: 0 + size: 32 + fields: + - name: GPIO_OUT_DATA + description: "GPIO0 ~ 21 output register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc." + bitOffset: 10 + bitWidth: 22 + access: read-write + - register: + name: RTC_GPIO_OUT_W1TS + description: RTC GPIO output bit set register + addressOffset: 4 + size: 32 + fields: + - name: GPIO_OUT_DATA_W1TS + description: "GPIO0 ~ 21 output set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_OUT_REG." + bitOffset: 10 + bitWidth: 22 + access: write-only + - register: + name: RTC_GPIO_OUT_W1TC + description: RTC GPIO output bit clear register + addressOffset: 8 + size: 32 + fields: + - name: GPIO_OUT_DATA_W1TC + description: "GPIO0 ~ 21 output clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_OUT_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_OUT_REG." + bitOffset: 10 + bitWidth: 22 + access: write-only + - register: + name: RTC_GPIO_ENABLE + description: RTC GPIO output enable register + addressOffset: 12 + size: 32 + fields: + - name: REG_RTCIO_REG_GPIO_ENABLE + description: "GPIO0 ~ 21 output enable. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. If the bit is set to 1, it means this GPIO pad is output." + bitOffset: 10 + bitWidth: 22 + access: read-write + - register: + name: RTC_GPIO_ENABLE_W1TS + description: RTC GPIO output enable bit set register + addressOffset: 16 + size: 32 + fields: + - name: REG_RTCIO_REG_GPIO_ENABLE_W1TS + description: "GPIO0 ~ 21 output enable set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be set to 1. Recommended operation: use this register to set RTCIO_RTC_GPIO_ENABLE_REG." + bitOffset: 10 + bitWidth: 22 + access: write-only + - register: + name: ENABLE_W1TC + description: RTC GPIO output enable bit clear register + addressOffset: 20 + size: 32 + fields: + - name: ENABLE_W1TC + description: "GPIO0 ~ 21 output enable clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE_REG will be cleared. Recommended operation: use this register to clear RTCIO_RTC_GPIO_ENABLE_REG." + bitOffset: 10 + bitWidth: 22 + access: write-only + - register: + name: RTC_GPIO_STATUS + description: RTC GPIO interrupt status register + addressOffset: 24 + size: 32 + fields: + - name: GPIO_STATUS_INT + description: "GPIO0 ~ 21 interrupt status register. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. This register should be used together with RTCIO_RTC_GPIO_PINn_INT_TYPE in RTCIO_RTC_GPIO_PINn_REG. 0: no interrupt; 1: corresponding interrupt." + bitOffset: 10 + bitWidth: 22 + access: read-write + - register: + name: RTC_GPIO_STATUS_W1TS + description: RTC GPIO interrupt status bit set register + addressOffset: 28 + size: 32 + fields: + - name: GPIO_STATUS_INT_W1TS + description: "GPIO0 ~ 21 interrupt set register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_GPIO_STATUS_INT will be set to 1. Recommended operation: use this register to set RTCIO_GPIO_STATUS_INT." + bitOffset: 10 + bitWidth: 22 + access: write-only + - register: + name: RTC_GPIO_STATUS_W1TC + description: RTC GPIO interrupt status bit clear register + addressOffset: 32 + size: 32 + fields: + - name: GPIO_STATUS_INT_W1TC + description: "GPIO0 ~ 21 interrupt clear register. If the value 1 is written to a bit here, the corresponding bit in RTCIO_GPIO_STATUS_INT will be cleared. Recommended operation: use this register to clear RTCIO_GPIO_STATUS_INT." + bitOffset: 10 + bitWidth: 22 + access: write-only + - register: + name: RTC_GPIO_IN + description: RTC GPIO input register + addressOffset: 36 + size: 32 + fields: + - name: GPIO_IN_NEXT + description: "GPIO0 ~ 21 input value. Bit10 corresponds to GPIO0, bit11 corresponds to GPIO1, etc. Each bit represents a pad input value, 1 for high level, and 0 for low level." + bitOffset: 10 + bitWidth: 22 + access: read-only + - register: + dim: 22 + dimIncrement: 4 + name: PIN%s + description: RTC configuration for pin %s + addressOffset: 40 + size: 32 + fields: + - name: PAD_DRIVER + description: "Pad driver selection. 0: normal output. 1: open drain." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: GPIO_PIN_INT_TYPE + description: "GPIO interrupt type selection. 0: GPIO interrupt disabled. 1: rising edge trigger. 2: falling edge trigger. 3: any edge trigger. 4: low level trigger. 5: high level trigger." + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: GPIO_PIN_WAKEUP_ENABLE + description: GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep. + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: RTC_DEBUG_SEL + description: RTC debug select register + addressOffset: 128 + size: 32 + fields: + - name: RTC_DEBUG_SEL0 + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: RTC_DEBUG_SEL1 + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: RTC_DEBUG_SEL2 + bitOffset: 10 + bitWidth: 5 + access: read-write + - name: RTC_DEBUG_SEL3 + bitOffset: 15 + bitWidth: 5 + access: read-write + - name: RTC_DEBUG_SEL4 + bitOffset: 20 + bitWidth: 5 + access: read-write + - name: RTC_DEBUG_12M_NO_GATING + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + dim: 15 + dimIncrement: 4 + name: TOUCH_PAD%s + description: Touch pad %s configuration register + addressOffset: 132 + size: 32 + resetValue: 1375731712 + fields: + - name: FUN_IE + description: Input enable in normal execution. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: Output enable in sleep mode. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: Input enable in sleep mode. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "0: no sleep mode. 1: enable sleep mode." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: Function selection. + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: Connect the RTC pad input to digital pad input. 0 is available. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: Touch sensor power on. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: "The tie option of touch sensor. 0: tie low. 1: tie high." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: Start touch sensor. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: DAC + description: "Touch sensor slope control. 3-bit for each touch pad, defaults to 0x4." + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: RUE + description: "Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: "Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: "Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: XTAL_32P_PAD + description: 32KHz crystal P-pad configuration register + addressOffset: 192 + size: 32 + resetValue: 1073741824 + fields: + - name: X32P_FUN_IE + description: Input enable in normal execution. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: X32P_SLP_OE + description: output enable in sleep mode. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: X32P_SLP_IE + description: input enable in sleep mode. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: X32P_SLP_SEL + description: "1: enable sleep mode. 0: no sleep mode." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: X32P_FUN_SEL + description: Function selection. + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: X32P_MUX_SEL + description: "1: use RTC GPIO. 0: use digital GPIO." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: X32P_RUE + description: "Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: X32P_RDE + description: "Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: X32P_DRV + description: "Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: XTAL_32N_PAD + description: 32KHz crystal N-pad configuration register + addressOffset: 196 + size: 32 + resetValue: 1073741824 + fields: + - name: X32N_FUN_IE + description: Input enable in normal execution. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: X32N_SLP_OE + description: Output enable in sleep mode. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: X32N_SLP_IE + description: Input enable in sleep mode. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: X32N_SLP_SEL + description: "1: enable sleep mode. 0: no sleep mode." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: X32N_FUN_SEL + description: Function selection. + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: X32N_MUX_SEL + description: "1: use RTC GPIO. 0: use digital GPIO." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: X32N_RUE + description: "Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: X32N_RDE + description: "Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: X32N_DRV + description: "Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: PAD_DAC1 + description: DAC1 configuration register + addressOffset: 200 + size: 32 + resetValue: 1073741824 + fields: + - name: PDAC1_DAC + description: Configure DAC_1 output when RTCIO_PDAC1_DAC_XPD_FORCE is set to 1. + bitOffset: 3 + bitWidth: 8 + access: read-write + - name: PDAC1_XPD_DAC + description: "When RTCIO_PDAC1_DAC_XPD_FORCE is set to 1, 1: enable DAC_1 output. 0: disable DAC_1 output." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: PDAC1_DAC_XPD_FORCE + description: "1: use RTCIO_PDAC1_XPD_DAC to control DAC_1 output. 0: use SAR ADC FSM to control DAC_1 output." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PDAC1_FUN_IE + description: Input enable in normal execution. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: PDAC1_SLP_OE + description: Output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PDAC1_SLP_IE + description: Input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: PDAC1_SLP_SEL + description: "1: enable sleep mode. 0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PDAC1_FUN_SEL + description: DAC_1 function selection. + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: PDAC1_MUX_SEL + description: "1: use RTC GPIO. 0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PDAC1_RUE + description: "Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: PDAC1_RDE + description: "Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: PDAC1_DRV + description: "Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: PAD_DAC2 + description: DAC2 configuration register + addressOffset: 204 + size: 32 + resetValue: 1073741824 + fields: + - name: PDAC2_DAC + description: Configure DAC_2 output when RTCIO_PDAC2_DAC_XPD_FORCE is set to 1. + bitOffset: 3 + bitWidth: 8 + access: read-write + - name: PDAC2_XPD_DAC + description: "When RTCIO_PDAC2_DAC_XPD_FORCE is set to 1, 1: enable DAC_2 output. 0: disable DAC_2 output." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: PDAC2_DAC_XPD_FORCE + description: "1: use RTCIO_PDAC2_XPD_DAC to control DAC_2 output. 0: use SAR ADC FSM to control DAC_2 output." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PDAC2_FUN_IE + description: Input enable in normal execution. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: PDAC2_SLP_OE + description: Output enable in sleep mode. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PDAC2_SLP_IE + description: Input enable in sleep mode. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: PDAC2_SLP_SEL + description: "1: enable sleep mode. 0: no sleep mode." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PDAC2_FUN_SEL + description: DAC_2 function selection. + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: PDAC2_MUX_SEL + description: "1: use RTC GPIO. 0: use digital GPIO." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PDAC2_RUE + description: "Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: PDAC2_RDE + description: "Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: PDAC2_DRV + description: "Select the drive strength of the pad. 0: ~5 mA: 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: RTC_PAD19 + description: Touch pad 19 configuration register + addressOffset: 208 + size: 32 + resetValue: 1342177280 + fields: + - name: FUN_IE + description: Input enable in normal execution. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: Output enable in sleep mode. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: Input enable in sleep mode. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode. 0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: Function selection. + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO. 0: use digital GPIO." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RUE + description: "Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: "Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: "Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: RTC_PAD20 + description: Touch pad 20 configuration register + addressOffset: 212 + size: 32 + resetValue: 1342177280 + fields: + - name: FUN_IE + description: Input enable in normal execution. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: Output enable in sleep mode. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: Input enable in sleep mode. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode. 0: no sleep mode." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: Function selection. + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO. 0: use digital GPIO." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RUE + description: "Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: "Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: "Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: RTC_PAD21 + description: Touch pad 21 configuration register + addressOffset: 216 + size: 32 + resetValue: 1342177280 + fields: + - name: FUN_IE + description: Input enable in normal execution. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: Output enable in sleep mode. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: Input enable in sleep mode. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode. 0: no sleep mode." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: Function selection. + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO. 0: use digital GPIO." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RUE + description: "Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down disabled." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: "Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up disabled." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: "Select the drive strength of the pad. 0: ~5 mA. 1: ~10 mA. 2: ~20 mA. 3: ~40 mA." + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: EXT_WAKEUP0 + description: External wake up configuration register + addressOffset: 220 + size: 32 + fields: + - name: SEL + description: "GPIO[0-17] can be used to wake up the chip when the chip is in the sleep mode. This register prompts the pad source to wake up the chip when the latter is indeep/light sleep mode. \n0: select GPIO0; 1: select GPIO2, etc" + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: XTL_EXT_CTR + description: Crystal power down enable GPIO source + addressOffset: 224 + size: 32 + fields: + - name: SEL + description: "Select the external crystal power down enable source to get into sleep mode. 0: select GPIO0. 1: select GPIO1, etc. The input value on this pin XOR RTC_CNTL_EXT_XTL_CONF_REG[30] is the crystal power down enable signal." + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: SAR_I2C_IO + description: RTC I2C pad selection + addressOffset: 228 + size: 32 + fields: + - name: SAR_DEBUG_BIT_SEL + bitOffset: 23 + bitWidth: 5 + access: read-write + - name: SAR_I2C_SCL_SEL + description: "Selects a pad the RTC I2C SCL signal connects to. 0: use TOUCH PAD0. 1: use TOUCH PAD2." + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: SAR_I2C_SDA_SEL + description: "Selects a pad the RTC I2C SDA signal connects to. 0: use TOUCH PAD1. 1: use TOUCH PAD3." + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: RTC_IO_TOUCH_CTRL + description: Touch control register + addressOffset: 232 + size: 32 + fields: + - name: IO_TOUCH_BUFSEL + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: IO_TOUCH_BUFMODE + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: RTC_IO_DATE + description: Version control register + addressOffset: 508 + size: 32 + resetValue: 26227056 + fields: + - name: IO_DATE + description: Version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: RTC_CNTL + description: Real-Time Clock Control + groupName: RTC_CNTL + baseAddress: 1061191680 + addressBlock: + - offset: 0 + size: 312 + usage: registers + interrupt: + - name: RTC_CORE + value: 49 + registers: + - register: + name: OPTIONS0 + description: "Sets the power options of crystal and PLL clocks, and initiates reset by software" + addressOffset: 0 + size: 32 + resetValue: 469770240 + fields: + - name: SW_STALL_APPCPU_C0 + description: "{reg_sw_stall_appcpu_c1[5:0] , reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SW_STALL_PROCPU_C0 + description: "When RTC_CNTL_REG_SW_STALL_PROCPU_C1 is configured to 0x21, setting this bit to 0x2 stalls the CPU by SW." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: SW_APPCPU_RST + description: "APP CPU SW reset. (Note, we don’t have APP CPU for ESP32-S2)" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SW_PROCPU_RST + description: Set this bit to reset the CPU by SW. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: BB_I2C_FORCE_PD + description: Set this bit to FPD BB_I2C. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BB_I2C_FORCE_PU + description: Set this bit to FPU BB_I2C. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: BBPLL_I2C_FORCE_PD + description: Set this bit to FPD BB_PLL _I2C. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BBPLL_I2C_FORCE_PU + description: Set this bit to FPU BB_PLL _I2C. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: BBPLL_FORCE_PD + description: Set this bit to FPD BB_PLL. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: BBPLL_FORCE_PU + description: Set this bit to FPU BB_PLL. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: XTL_FORCE_PD + description: Set this bit to FPD the crystal oscillator. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: XTL_FORCE_PU + description: Set this bit to FPU the crystal oscillator. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: XTL_FORCE_ISO + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: PLL_FORCE_ISO + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ANALOG_FORCE_ISO + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: XTL_FORCE_NOISO + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: PLL_FORCE_NOISO + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: ANALOG_FORCE_NOISO + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_RST + description: Set this bit to force reset the digital system in deep-sleep. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_NORST + description: Set this bit to disable force reset to digital system in deep-sleep. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SW_SYS_RST + description: Set this bit to reset the system via SW. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SLP_TIMER0 + description: RTC timer threshold register 0 + addressOffset: 4 + size: 32 + fields: + - name: SLP_VAL_LO + description: Sets the lower 32 bits of the trigger threshold for the RTC timer. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SLP_TIMER1 + description: RTC timer threshold register 1 + addressOffset: 8 + size: 32 + fields: + - name: SLP_VAL_HI + description: Sets the higher 16 bits of the trigger threshold for the RTC timer. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MAIN_TIMER_ALARM_EN + description: Sets this bit to enable the timer alarm. + bitOffset: 16 + bitWidth: 1 + access: write-only + - register: + name: TIME_UPDATE + description: RTC timer update control register + addressOffset: 12 + size: 32 + fields: + - name: TIMER_SYS_STALL + description: Selects the triggering condition for the RTC timer. See details in Table 1-2. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: TIMER_XTL_OFF + description: Selects the triggering condition for the RTC timer. See details in Table 1-2. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: TIMER_SYS_RST + description: Selects the triggering condition for the RTC timer. See details in Table 1-2. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TIME_UPDATE + description: Selects the triggering condition for the RTC timer. See details in Table 1-2. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: TIME_LOW0 + description: Stores the lower 32 bits of RTC timer 0. + addressOffset: 16 + size: 32 + fields: + - name: TIMER_VALUE0_LOW + description: Stores the lower 32 bits of RTC timer 0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: TIME_HIGH0 + description: Stores the higher 16 bits of RTC timer 0 + addressOffset: 20 + size: 32 + fields: + - name: TIMER_VALUE0_HIGH + description: Stores the higher 16 bits of RTC timer 0. + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: STATE0 + description: Configures the sleep / reject / wakeup state + addressOffset: 24 + size: 32 + fields: + - name: SW_CPU_INT + description: Sends a SW RTC interrupt to CPU. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SLP_REJECT_CAUSE_CLR + description: Clears the RTC reject-to-sleep cause. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: APB2RTC_BRIDGE_SEL + description: "1: APB to RTC using bridge 0: APB to RTC using sync" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SDIO_ACTIVE_IND + description: Indicates the SDIO is active. + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SLP_WAKEUP + description: Sleep wakeup bit. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SLP_REJECT + description: Sleep reject bit. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SLEEP_EN + description: Sends the chip to sleep. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TIMER1 + description: Configures CPU stall options + addressOffset: 28 + size: 32 + resetValue: 672400387 + fields: + - name: CPU_STALL_EN + description: Enables CPU stalling. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CPU_STALL_WAIT + description: Sets the CPU stall waiting cycle (using the RTC fast clock). + bitOffset: 1 + bitWidth: 5 + access: read-write + - name: CK8M_WAIT + description: Sets the 8 MHz clock waiting (using the RTC slow clock). + bitOffset: 6 + bitWidth: 8 + access: read-write + - name: XTL_BUF_WAIT + description: Sets the XTAL waiting cycle (using the RTC slow clock). + bitOffset: 14 + bitWidth: 10 + access: read-write + - name: PLL_BUF_WAIT + description: Sets the PLL waiting cycle (using the RTC slow clock). + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: TIMER2 + description: Configures RTC slow clock and touch controller + addressOffset: 32 + size: 32 + resetValue: 17301504 + fields: + - name: ULPCP_TOUCH_START_WAIT + description: Sets the waiting cycle (using the RTC slow clock) before the ULP co-processor / touch controller start to work. + bitOffset: 15 + bitWidth: 9 + access: read-write + - name: MIN_TIME_CK8M_OFF + description: Sets the minimal cycle for 8 MHz clock (using the RTC slow clock) when powered down. + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: TIMER3 + description: configure some wait time for power on + addressOffset: 36 + size: 32 + resetValue: 336988680 + fields: + - name: WIFI_WAIT_TIMER + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: WIFI_POWERUP_TIMER + bitOffset: 9 + bitWidth: 7 + access: read-write + - name: ROM_RAM_WAIT_TIMER + bitOffset: 16 + bitWidth: 9 + access: read-write + - name: ROM_RAM_POWERUP_TIMER + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: TIMER4 + description: configure some wait time for power on + addressOffset: 40 + size: 32 + resetValue: 270535176 + fields: + - name: WAIT_TIMER + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: POWERUP_TIMER + bitOffset: 9 + bitWidth: 7 + access: read-write + - name: DG_WRAP_WAIT_TIMER + bitOffset: 16 + bitWidth: 9 + access: read-write + - name: DG_WRAP_POWERUP_TIMER + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: TIMER5 + description: Configures the minimal sleep cycles + addressOffset: 44 + size: 32 + resetValue: 303333376 + fields: + - name: MIN_SLP_VAL + description: Sets the minimal sleep cycles (using the RTC slow clock). + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: RTCMEM_WAIT_TIMER + bitOffset: 16 + bitWidth: 9 + access: read-write + - name: RTCMEM_POWERUP_TIMER + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: TIMER6 + description: Configure minimal sleep cycles register + addressOffset: 48 + size: 32 + resetValue: 270532608 + fields: + - name: DG_DCDC_WAIT_TIMER + bitOffset: 16 + bitWidth: 9 + access: read-write + - name: DG_DCDC_POWERUP_TIMER + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: ANA_CONF + description: Configures the power options for I2C and PLLA + addressOffset: 52 + size: 32 + resetValue: 10747904 + fields: + - name: I2C_RESET_POR_FORCE_PD + description: SLEEP_I2CPOR force pd + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: I2C_RESET_POR_FORCE_PU + description: SLEEP_I2CPOR force pu + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: GLITCH_RST_EN + description: Set this bit to enable a reset when the system detects a glitch. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SAR_I2C_FORCE_PD + description: Sets this bit to FPD the SAR_I2C. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SAR_I2C_FORCE_PU + description: Sets this bit to FPU the SAR_I2C. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: PLLA_FORCE_PD + description: Sets this bit to FPD the PLLA. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: PLLA_FORCE_PU + description: Sets this bit to FPU the PLLA. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: BBPLL_CAL_SLP_START + description: start BBPLL calibration during sleep + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PVTMON_PU + description: "1: PVTMON power up , otherwise power down" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TXRF_I2C_PU + description: "1: TXRF_I2C power up , otherwise power down" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RFRX_PBUS_PU + description: "1: RFRX_PBUS power up , otherwise power down" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CKGEN_I2C_PU + description: "1: CKGEN_I2C power up , otherwise power down" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: PLL_I2C_PU + description: "1. PLL_I2C power up ,otherwise power down" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RESET_STATE + description: "Indicates the CPU reset source. For more information about the reset cause, please refer to Table \\ref{table:resetreasons} in Chapter \\ref{module:ResetandClock} \\textit{\\nameref{module:ResetandClock}}." + addressOffset: 56 + size: 32 + resetValue: 12288 + fields: + - name: RESET_CAUSE_PROCPU + description: Stores the CPU reset cause. + bitOffset: 0 + bitWidth: 6 + access: read-only + - name: RESET_CAUSE_APPCPU + description: reset cause of APP CPU + bitOffset: 6 + bitWidth: 6 + access: read-only + - name: APPCPU_STAT_VECTOR_SEL + description: APP CPU state vector sel + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PROCPU_STAT_VECTOR_SEL + description: Selects the CPU state vector. + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: WAKEUP_STATE + description: Wakeup bitmap enabling register + addressOffset: 60 + size: 32 + resetValue: 393216 + fields: + - name: WAKEUP_ENA + description: Enables the wakeup bitmap. + bitOffset: 15 + bitWidth: 17 + access: read-write + - register: + name: INT_ENA_RTC + description: RTC interrupt enabling register + addressOffset: 64 + size: 32 + fields: + - name: SLP_WAKEUP_INT_ENA + description: Enables interruption when the chip wakes up from sleep. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_REJECT_INT_ENA + description: Enables interruption when the chip rejects to go to sleep. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SDIO_IDLE_INT_ENA + description: Enables interruption when the SDIO idles. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: WDT_INT_ENA + description: Enables the RTC watchdog interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TOUCH_SCAN_DONE_INT_ENA + description: Enables interruption upon the completion of a touch scanning. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ULP_CP_INT_ENA + description: Enables the ULP co-processor interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TOUCH_DONE_INT_ENA + description: Enables interruption upon the completion of a single touch. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TOUCH_ACTIVE_INT_ENA + description: Enables interruption when a touch is detected. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TOUCH_INACTIVE_INT_ENA + description: Enables interruption when a touch is released. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_INT_ENA + description: Enables the brown out interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: MAIN_TIMER_INT_ENA + description: Enables the RTC main timer interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SARADC1_INT_ENA + description: Enables the SAR ADC 1 interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TSENS_INT_ENA + description: Enables the touch sensor interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: COCPU_INT_ENA + description: Enables the ULP-RISCV interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SARADC2_INT_ENA + description: Enables the SAR ADC 2 interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SWD_INT_ENA + description: Enables the super watchdog interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: XTAL32K_DEAD_INT_ENA + description: Enables interruption when the 32 kHz crystal is dead. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: COCPU_TRAP_INT_ENA + description: Enables interruption when the ULP-RISCV is trapped. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: TOUCH_TIMEOUT_INT_ENA + description: Enables interruption when touch sensor times out. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: GLITCH_DET_INT_ENA + description: Enables interruption when a glitch is detected. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW_RTC + description: RTC interrupt raw register + addressOffset: 68 + size: 32 + fields: + - name: SLP_WAKEUP_INT_RAW + description: Stores the raw interrupt triggered when the chip wakes up from sleep. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SLP_REJECT_INT_RAW + description: Stores the raw interrupt triggered when the chip rejects to go to sleep. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SDIO_IDLE_INT_RAW + description: Stores the raw interrupt triggered when the SDIO idles. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: WDT_INT_RAW + description: Stores the raw RTC watchdog interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TOUCH_SCAN_DONE_INT_RAW + description: Stores the raw interrupt triggered upon the completion of a touch scanning. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ULP_CP_INT_RAW + description: Stores the raw ULP co-processor interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: TOUCH_DONE_INT_RAW + description: Stores the raw interrupt triggered upon the completion of a single touch. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TOUCH_ACTIVE_INT_RAW + description: Stores the raw interrupt triggered when a touch is detected. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TOUCH_INACTIVE_INT_RAW + description: Stores the raw interrupt triggered when a touch is released. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: BROWN_OUT_INT_RAW + description: Stores the raw brown out interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: MAIN_TIMER_INT_RAW + description: Stores the raw RTC main timer interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SARADC1_INT_RAW + description: Stores the raw SAR ADC 1 interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TSENS_INT_RAW + description: Stores the raw touch sensor interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: COCPU_INT_RAW + description: Stores the raw ULP-RISCV interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SARADC2_INT_RAW + description: Stores the raw SAR ADC 2 interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SWD_INT_RAW + description: Stores the raw super watchdog interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: XTAL32K_DEAD_INT_RAW + description: Stores the raw interrupt triggered when the 32 kHz crystal is dead. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: COCPU_TRAP_INT_RAW + description: Stores the raw interrupt triggered when the ULP-RISCV is trapped. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: TOUCH_TIMEOUT_INT_RAW + description: Stores the raw interrupt triggered when touch sensor times out. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: GLITCH_DET_INT_RAW + description: Stores the raw interrupt triggered when a glitch is detected. + bitOffset: 19 + bitWidth: 1 + access: read-only + - register: + name: INT_ST_RTC + description: RTC interrupt state register + addressOffset: 72 + size: 32 + fields: + - name: SLP_WAKEUP_INT_ST + description: Stores the status of the interrupt triggered when the chip wakes up from sleep. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SLP_REJECT_INT_ST + description: Stores the status of the interrupt triggered when the chip rejects to go to sleep. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SDIO_IDLE_INT_ST + description: Stores the status of the interrupt triggered when the SDIO idles. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: WDT_INT_ST + description: Stores the status of the RTC watchdog interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TOUCH_SCAN_DONE_INT_ST + description: Stores the status of the interrupt triggered upon the completion of a touch scanning. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ULP_CP_INT_ST + description: Stores the status of the ULP co-processor interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: TOUCH_DONE_INT_ST + description: Stores the status of the interrupt triggered upon the completion of a single touch. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TOUCH_ACTIVE_INT_ST + description: Stores the status of the interrupt triggered when a touch is detected. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TOUCH_INACTIVE_INT_ST + description: Stores the status of the interrupt triggered when a touch is released. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: BROWN_OUT_INT_ST + description: Stores the status of the brown out interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: MAIN_TIMER_INT_ST + description: Stores the status of the RTC main timer interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SARADC1_INT_ST + description: Stores the status of the SAR ADC 1 interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TSENS_INT_ST + description: Stores the status of the touch sensor interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: COCPU_INT_ST + description: Stores the status of the ULP-RISCV interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SARADC2_INT_ST + description: Stores the status of the SAR ADC 2 interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SWD_INT_ST + description: Stores the status of the super watchdog interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: XTAL32K_DEAD_INT_ST + description: Stores the status of the interrupt triggered when the 32 kHz crystal is dead. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: COCPU_TRAP_INT_ST + description: Stores the status of the interrupt triggered when the ULP-RISCV is trapped. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: TOUCH_TIMEOUT_INT_ST + description: Stores the status of the interrupt triggered when touch sensor times out. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: GLITCH_DET_INT_ST + description: Stores the status of the interrupt triggered when a glitch is detected. + bitOffset: 19 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR_RTC + description: RTC interrupt clear register + addressOffset: 76 + size: 32 + fields: + - name: SLP_WAKEUP_INT_CLR + description: Clears the interrupt triggered when the chip wakes up from sleep. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SLP_REJECT_INT_CLR + description: Clears the interrupt triggered when the chip rejects to go to sleep. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SDIO_IDLE_INT_CLR + description: Clears the interrupt triggered when the SDIO idles. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: WDT_INT_CLR + description: Enables the RTC watchdog interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TOUCH_SCAN_DONE_INT_CLR + description: Clears the interrupt triggered upon the completion of a touch scanning. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: ULP_CP_INT_CLR + description: Enables the ULP co-processor interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TOUCH_DONE_INT_CLR + description: Clears the interrupt triggered upon the completion of a single touch. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TOUCH_ACTIVE_INT_CLR + description: Clears the interrupt triggered when a touch is detected. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: TOUCH_INACTIVE_INT_CLR + description: Clears the interrupt triggered when a touch is released. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: BROWN_OUT_INT_CLR + description: Clears the brown out interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: MAIN_TIMER_INT_CLR + description: Clears the RTC main timer interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SARADC1_INT_CLR + description: Clears the SAR ADC 1 interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TSENS_INT_CLR + description: Clears the touch sensor interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: COCPU_INT_CLR + description: Clears the ULP-RISCV interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SARADC2_INT_CLR + description: Clears the SAR ADC 2 interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SWD_INT_CLR + description: Clears the super watchdog interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: XTAL32K_DEAD_INT_CLR + description: Clears the interrupt triggered when the 32 kHz crystal is dead. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: COCPU_TRAP_INT_CLR + description: Clears the interrupt triggered when the ULP-RISCV is trapped. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: TOUCH_TIMEOUT_INT_CLR + description: Clears the interrupt triggered when touch sensor times out. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: GLITCH_DET_INT_CLR + description: Clears the interrupt triggered when a glitch is detected. + bitOffset: 19 + bitWidth: 1 + access: write-only + - register: + name: STORE0 + description: Reservation register 0 + addressOffset: 80 + size: 32 + fields: + - name: SCRATCH0 + description: Reservation register 0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE1 + description: Reservation register 1 + addressOffset: 84 + size: 32 + fields: + - name: SCRATCH1 + description: Reservation register 1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE2 + description: Reservation register 2 + addressOffset: 88 + size: 32 + fields: + - name: SCRATCH2 + description: Reservation register 2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE3 + description: Reservation register 3 + addressOffset: 92 + size: 32 + fields: + - name: SCRATCH3 + description: Reservation register 3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: EXT_XTL_CONF + description: 32 kHz crystal oscillator configuration register + addressOffset: 96 + size: 32 + resetValue: 420992 + fields: + - name: XTAL32K_WDT_EN + description: Set this bit to enable the 32 kHz crystal watchdog. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: XTAL32K_WDT_CLK_FO + description: Set this bit to FPU the 32 kHz crystal watchdog clock. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: XTAL32K_WDT_RESET + description: Set this bit to reset the 32 kHz crystal watchdog by SW. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: XTAL32K_EXT_CLK_FO + description: Set this bit to FPU the external clock of 32 kHz crystal. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: XTAL32K_AUTO_BACKUP + description: Set this bit to switch to the backup clock when the 32 kHz crystal is dead. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: XTAL32K_AUTO_RESTART + description: Set this bit to restart the 32 kHz crystal automatically when the 32 kHz crystal is dead. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: XTAL32K_AUTO_RETURN + description: Set this bit to switch back to 32 kHz crystal when the 32 kHz crystal is restarted. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: XTAL32K_XPD_FORCE + description: Set 1 to allow the software to FPD the 32 kHz crystal. Set 0 to allow the FSM to FPD the 32 kHz crystal. (R/W) + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: ENCKINIT_XTAL_32K + description: Applies an internal clock to help the 32 kHz crystal to start. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DBUF_XTAL_32K + description: "0: single-end buffer 1: differential buffer" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DGM_XTAL_32K + description: xtal_32k gm control + bitOffset: 10 + bitWidth: 3 + access: read-write + - name: DRES_XTAL_32K + description: DRES_XTAL_32K + bitOffset: 13 + bitWidth: 3 + access: read-write + - name: XPD_XTAL_32K + description: XPD_XTAL_32K + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DAC_XTAL_32K + description: DAC_XTAL_32K + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: WDT_STATE + description: Stores the status of the 32 kHz watchdog. + bitOffset: 20 + bitWidth: 3 + access: read-only + - name: XTAL32K_GPIO_SEL + description: "Selects the 32 kHz crystal clock. 0: selects the external 32 kHz clock. 1: selects clock from the RTC GPIO X32P_C." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: XTL_EXT_CTR_LV + description: "0: powers down XTAL at high level 1: powers down XTAL at low level" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: XTL_EXT_CTR_EN + description: Enables the GPIO to power down the crystal oscillator. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EXT_WAKEUP_CONF + description: GPIO wakeup configuration register + addressOffset: 100 + size: 32 + fields: + - name: GPIO_WAKEUP_FILTER + description: Set this bit to enable the GPIO wakeup event filter. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: EXT_WAKEUP0_LV + description: "0: external wakeup 0 at low level 1: external wakeup 0 at high level" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: EXT_WAKEUP1_LV + description: "0: external wakeup 1 at low level 1: external wakeup 1 at high level" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SLP_REJECT_CONF + description: Configures sleep / reject options + addressOffset: 104 + size: 32 + fields: + - name: SLEEP_REJECT_ENA + description: Set this bit to enable reject-to-sleep. + bitOffset: 13 + bitWidth: 17 + access: read-write + - name: LIGHT_SLP_REJECT_EN + description: Set this bit to enable reject-to-light-sleep. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DEEP_SLP_REJECT_EN + description: Set this bit to enable reject-to-deep-sleep. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CPU_PERIOD_CONF + description: CPU sel option + addressOffset: 108 + size: 32 + fields: + - name: CPUSEL_CONF + description: CPU sel option + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CPUPERIOD_SEL + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: SDIO_ACT_CONF + description: configure sdio active register + addressOffset: 112 + size: 32 + fields: + - name: SDIO_ACT_DNUM + description: configure sdio act dnum + bitOffset: 22 + bitWidth: 10 + access: read-write + - register: + name: CLK_CONF + description: RTC clock configuration register + addressOffset: 116 + size: 32 + resetValue: 22557208 + fields: + - name: CK8M_DIV_SEL_VLD + description: "Synchronizes the reg_ck8m_div_sel. Not that you have to invalidate the bus before switching clock, and validate the new clock." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CK8M_DIV + description: "Set the CK8M_D256_OUT divider. 00: divided by 128 01: divided by 256 10: divided by 512 11: divided by 1024." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: ENB_CK8M + description: Set this bit to disable CK8M and CK8M_D256_OUT. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: ENB_CK8M_DIV + description: "Selects the CK8M_D256_OUT. 1: CK8M 0: CK8M divided by 256." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DIG_XTAL32K_EN + description: Set this bit to enable CK_XTAL_32K clock for the digital core. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DIG_CLK8M_D256_EN + description: Set this bit to enable CK8M_D256_OUT clock for the digital core. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DIG_CLK8M_EN + description: Set this bit to enable 8 MHz clock for the digital core. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CK8M_DIV_SEL + description: "Stores the 8 MHz divider, which is reg_ck8m_div_sel + 1" + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: XTAL_FORCE_NOGATING + description: Set this bit to force no gating to crystal during sleep + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CK8M_FORCE_NOGATING + description: Set this bit to disable force gating to 8 MHz crystal during sleep. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CK8M_DFREQ + description: CK8M_DFREQ + bitOffset: 17 + bitWidth: 8 + access: read-write + - name: CK8M_FORCE_PD + description: Set this bit to FPD the 8 MHz clock. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: CK8M_FORCE_PU + description: Set this bit to FPU the 8 MHz clock. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: FAST_CLK_RTC_SEL + description: "Set this bit to select the RTC fast clock. 0: XTAL div 4, 1: CK8M." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ANA_CLK_RTC_SEL + description: "Set this bit to select the RTC slow clock. 0: 90K rtc_clk 1: 32k XTAL 2: 8md256." + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: SLOW_CLK_CONF + description: RTC slow clock configuration register + addressOffset: 120 + size: 32 + resetValue: 4194304 + fields: + - name: ANA_CLK_DIV_VLD + description: "Synchronizes the reg_rtc_ana_clk_div bus. Note that you have to invalidate the bus before switching clock, and validate the new clock." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: ANA_CLK_DIV + description: Set the rtc_clk divider. + bitOffset: 23 + bitWidth: 8 + access: read-write + - name: SLOW_CLK_NEXT_EDGE + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SDIO_CONF + description: configure vddsdio register + addressOffset: 124 + size: 32 + resetValue: 45137418 + fields: + - name: SDIO_TIMER_TARGET + description: timer count to apply reg_sdio_dcap after sdio power on + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SDIO_DTHDRV + description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge current set to 3 after several us. + bitOffset: 9 + bitWidth: 2 + access: read-write + - name: SDIO_DCAP + description: ability to prevent LDO from overshoot + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: SDIO_INITI + description: "add resistor from ldo output to ground. 0: no res 1: 6k 2: 4k 3: 2k" + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: SDIO_EN_INITI + description: "0 to set init[1:0]=0" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SDIO_DCURLIM + description: tune current limit threshold when tieh = 0. About 800mA/(8+d) + bitOffset: 16 + bitWidth: 3 + access: read-write + - name: SDIO_MODECURLIM + description: select current limit mode + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SDIO_ENCURLIM + description: enable current limit + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SDIO_REG_PD_EN + description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SDIO_FORCE + description: "1: use SW option to control SDIO_REG 0: use state machine" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SDIO_TIEH + description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1 + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: REG1P8_READY + description: read only register for REG1P8_READY + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: DREFL_SDIO + description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1 + bitOffset: 25 + bitWidth: 2 + access: read-write + - name: DREFM_SDIO + description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1 + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: DREFH_SDIO + description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1 + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: XPD_SDIO + description: SW option for XPD_VOOSDIO. Only active when reg_sdio_force = 1 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: BIAS_CONF + description: configure power register + addressOffset: 128 + size: 32 + resetValue: 67584 + fields: + - name: BIAS_BUF_IDLE + description: open bias buf when system in active + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: BIAS_BUF_WAKE + description: open bias buf when rtc in wakeup + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: BIAS_BUF_DEEP_SLP + description: open bias buf when rtc in deep sleep + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: BIAS_BUF_MONITOR + description: open bias buf when rtc in monitor state + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: PD_CUR_DEEP_SLP + description: xpd cur when rtc in sleep_state + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PD_CUR_MONITOR + description: xpd cur when rtc in monitor state + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: BIAS_SLEEP_DEEP_SLP + description: bias_sleep when rtc in sleep_state + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: BIAS_SLEEP_MONITOR + description: bias_sleep when rtc in monitor state + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: DBG_ATTEN_DEEP_SLP + description: DBG_ATTEN when rtc in sleep state + bitOffset: 18 + bitWidth: 4 + access: read-write + - name: DBG_ATTEN_MONITOR + description: DBG_ATTEN when rtc in monitor state + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: ENB_SCK_XTAL + description: ENB_SCK_XTAL + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: INC_HEARTBEAT_REFRESH + description: INC_HEARTBEAT_REFRESH + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: DEC_HEARTBEAT_PERIOD + description: DEC_HEARTBEAT_PERIOD + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: INC_HEARTBEAT_PERIOD + description: INC_HEARTBEAT_PERIOD + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: DEC_HEARTBEAT_WIDTH + description: DEC_HEARTBEAT_WIDTH + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: RST_BIAS_I2C + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: REG + description: RTC/DIG regulator configuration register + addressOffset: 132 + size: 32 + resetValue: 2835358720 + fields: + - name: DIG_REG_DBIAS_SLP + description: Configures the regulation factor for the digital system voltage regulator when the CPU is in sleep status. + bitOffset: 8 + bitWidth: 3 + access: read-write + - name: DIG_REG_DBIAS_WAK + description: Configures the regulation factor for the digital system voltage regulator when the CPU is in active status. + bitOffset: 11 + bitWidth: 3 + access: read-write + - name: SCK_DCAP + description: Configures the frequency of the RTC clocks. + bitOffset: 14 + bitWidth: 8 + access: read-write + - name: DBIAS_SLP + description: Configures the regulation factor for the low-power voltage regulator when the CPU is in sleep status. + bitOffset: 22 + bitWidth: 3 + access: read-write + - name: DBIAS_WAK + description: Configures the regulation factor for the low-power voltage regulator when the CPU is in active status. + bitOffset: 25 + bitWidth: 3 + access: read-write + - name: DBOOST_FORCE_PD + description: RTC_DBOOST force power down + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DBOOST_FORCE_PU + description: RTC_DBOOST force power up + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: REGULATOR_FORCE_PD + description: "Set this bit to FPD the RTC_REG, which means decreasing its voltage to 0.8 V or lower." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: REGULATOR_FORCE_PU + description: Set this bit to FPU the RTC_REG. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: PWC + description: RTC power configuraiton register + addressOffset: 136 + size: 32 + resetValue: 76069 + fields: + - name: FASTMEM_FORCE_NOISO + description: Set this bit to disable the force isolation to the RTC fast memory. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FASTMEM_FORCE_ISO + description: Set this bit to force isolate the RTC fast memory. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SLOWMEM_FORCE_NOISO + description: Set this bit to disable the force isolation to the RTC slow memory. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLOWMEM_FORCE_ISO + description: Set this bit to force isolate the RTC slow memory. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FORCE_ISO + description: Set this bit to force isolate the RTC peripherals. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FORCE_NOISO + description: Set this bit to disable the force isolation to the RTC peripherals. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FASTMEM_FOLW_CPU + description: Set 1 to FPD the RTC fast memory when the CPU is powered down. Set 0 to FPD the RTC fast memory when the RTC main state machine is powered down. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FASTMEM_FORCE_LPD + description: Set this bit to force not retain the RTC fast memory. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FASTMEM_FORCE_LPU + description: Set this bit to force retain the RTC fast memory. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLOWMEM_FOLW_CPU + description: Set 1 to FPD the RTC slow memory when the CPU is powered down. Set 0 to FPD the RTC slow memory when the RTC main state machine is powered down. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLOWMEM_FORCE_LPD + description: Set this bit to force not retain the RTC slow memory. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLOWMEM_FORCE_LPU + description: Set this bit to force retain the RTC slow memory. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FASTMEM_FORCE_PD + description: Set this bit to FPD the RTC fast memory. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FASTMEM_FORCE_PU + description: Set this bit to FPU the RTC fast memory. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FASTMEM_PD_EN + description: Set this bit to enable PD for the RTC fast memory in sleep. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLOWMEM_FORCE_PD + description: Set this bit to FPD the RTC slow memory. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLOWMEM_FORCE_PU + description: Set this bit to FPU the RTC slow memory. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SLOWMEM_PD_EN + description: Set this bit to enable PD for the RTC slow memory in sleep. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: FORCE_PD + description: Set this bit to FPD the RTC peripherals. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: FORCE_PU + description: Set this bit to FPU the RTC peripherals. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PD_EN + description: Set this bit to enable PD for the RTC peripherals in sleep. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: PAD_FORCE_HOLD + description: Set this bit the force hold the RTC GPIOs. + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + name: DIG_PWC + description: Digital system power configuraiton register + addressOffset: 140 + size: 32 + resetValue: 5592400 + fields: + - name: LSLP_MEM_FORCE_PD + description: Set this bit to FPD the memories in the digital system in sleep. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: LSLP_MEM_FORCE_PU + description: Set this bit to FPU the memories in the digital system. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ROM0_FORCE_PD + description: ROM force power down + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: ROM0_FORCE_PU + description: ROM force power up + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: INTER_RAM0_FORCE_PD + description: internal SRAM 0 force power down + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: INTER_RAM0_FORCE_PU + description: internal SRAM 0 force power up + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: INTER_RAM1_FORCE_PD + description: internal SRAM 1 force power down + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: INTER_RAM1_FORCE_PU + description: internal SRAM 1 force power up + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: INTER_RAM2_FORCE_PD + description: internal SRAM 2 force power down + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: INTER_RAM2_FORCE_PU + description: internal SRAM 2 force power up + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: INTER_RAM3_FORCE_PD + description: internal SRAM 3 force power down + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: INTER_RAM3_FORCE_PU + description: internal SRAM 3 force power up + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: INTER_RAM4_FORCE_PD + description: internal SRAM 4 force power down + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: INTER_RAM4_FORCE_PU + description: internal SRAM 4 force power up + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: WIFI_FORCE_PD + description: Set this bit to FPD the Wi-Fi circuit. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: WIFI_FORCE_PU + description: Set this bit to FPU the Wi-Fi circuit. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_PD + description: Set this bit to FPD the digital system. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_PU + description: Set this bit to FPD the DC-DC convertor in the digital system. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: DG_DCDC_FORCE_PD + description: Set this bit to FPD the DC-DC convertor in the digital system. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: DG_DCDC_FORCE_PU + description: Set this bit to FPU the DC-DC convertor in the digital system. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: DG_DCDC_PD_EN + description: Set this bit to enable PD for the DC-DC convertor in the digital system. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: ROM0_PD_EN + description: enable power down ROM in sleep + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: INTER_RAM0_PD_EN + description: enable power down internal SRAM 0 in sleep + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: INTER_RAM1_PD_EN + description: enable power down internal SRAM 1 in sleep + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: INTER_RAM2_PD_EN + description: enable power down internal SRAM 2 in sleep + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: INTER_RAM3_PD_EN + description: enable power down internal SRAM 3 in sleep + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: INTER_RAM4_PD_EN + description: enable power down internal SRAM 4 in sleep + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: WIFI_PD_EN + description: Set this bit to enable PD for the Wi-Fi circuit in sleep. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DG_WRAP_PD_EN + description: Set this bit to enable PD for the digital system in sleep. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DIG_ISO + description: Digital system ISO configuration register + addressOffset: 144 + size: 32 + resetValue: 2863288320 + fields: + - name: FORCE_OFF + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FORCE_ON + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DG_PAD_AUTOHOLD + description: Indicates the auto-hold status of the digital GPIOs. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: CLR_DG_PAD_AUTOHOLD + description: Se this bit to clear the auto-hold enabler for the digital GPIOs. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: DG_PAD_AUTOHOLD_EN + description: Se this bit to allow the digital GPIOs to enter the autohold status. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DG_PAD_FORCE_NOISO + description: Set this bit to disable the force isolation to the digital GPIOs. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DG_PAD_FORCE_ISO + description: Set this bit to force isolate the digital GPIOs. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DG_PAD_FORCE_UNHOLD + description: Set this bit the force unhold the digital GPIOs. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DG_PAD_FORCE_HOLD + description: Set this bit the force hold the digital GPIOs. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: ROM0_FORCE_ISO + description: ROM force ISO + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ROM0_FORCE_NOISO + description: ROM force no ISO + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: INTER_RAM0_FORCE_ISO + description: internal SRAM 0 force ISO + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: INTER_RAM0_FORCE_NOISO + description: internal SRAM 0 force no ISO + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: INTER_RAM1_FORCE_ISO + description: internal SRAM 1 force ISO + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: INTER_RAM1_FORCE_NOISO + description: internal SRAM 1 force no ISO + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: INTER_RAM2_FORCE_ISO + description: internal SRAM 2 force ISO + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: INTER_RAM2_FORCE_NOISO + description: internal SRAM 2 force no ISO + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: INTER_RAM3_FORCE_ISO + description: internal SRAM 3 force ISO + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: INTER_RAM3_FORCE_NOISO + description: internal SRAM 3 force no ISO + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: INTER_RAM4_FORCE_ISO + description: internal SRAM 4 force ISO + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: INTER_RAM4_FORCE_NOISO + description: internal SRAM 4 force no ISO + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: WIFI_FORCE_ISO + description: Set this bit to force isolate the Wi-Fi circuits. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: WIFI_FORCE_NOISO + description: Set this bit to disable the force isolation to the Wi-Fi circuits. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_ISO + description: Set this bit to force isolate the digital system. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_NOISO + description: Set this bit to disable the force isolation to the digital system. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: WDTCONFIG0 + description: RTC watchdog configuration register + addressOffset: 148 + size: 32 + resetValue: 78356 + fields: + - name: WDT_CHIP_RESET_WIDTH + description: chip reset siginal pulse width + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: WDT_CHIP_RESET_EN + description: wdt reset whole chip enable + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: WDT_PAUSE_IN_SLP + description: Set this bit to pause the watchdog in sleep. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: WDT_APPCPU_RESET_EN + description: enable WDT reset APP CPU + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: WDT_PROCPU_RESET_EN + description: Set this bit to allow the watchdog to be able to reset CPU. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: WDT_FLASHBOOT_MOD_EN + description: Set this bit to enable watchdog when the chip boots from flash. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: WDT_SYS_RESET_LENGTH + description: Sets the length of the system reset counter. + bitOffset: 13 + bitWidth: 3 + access: read-write + - name: WDT_CPU_RESET_LENGTH + description: Sets the length of the CPU reset counter. + bitOffset: 16 + bitWidth: 3 + access: read-write + - name: WDT_STG3 + description: "1: enable at the interrupt stage 2: enable at the CPU stage 3: enable at the system stage 4: enable at the system and RTC stage." + bitOffset: 19 + bitWidth: 3 + access: read-write + - name: WDT_STG2 + description: "1: enable at the interrupt stage 2: enable at the CPU stage 3: enable at the system stage 4: enable at the system and RTC stage." + bitOffset: 22 + bitWidth: 3 + access: read-write + - name: WDT_STG1 + description: "1: enable at the interrupt stage 2: enable at the CPU stage 3: enable at the system stage 4: enable at the system and RTC stage." + bitOffset: 25 + bitWidth: 3 + access: read-write + - name: WDT_STG0 + description: "1: enable at the interrupt stage 2: enable at the CPU stage 3: enable at the system stage 4: enable at the system and RTC stage." + bitOffset: 28 + bitWidth: 3 + access: read-write + - name: WDT_EN + description: Set this bit to enable the RTC watchdog. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: WDTCONFIG1 + description: Configures the hold time of RTC watchdog at level 1 + addressOffset: 152 + size: 32 + resetValue: 200000 + fields: + - name: WDT_STG0_HOLD + description: Configures the hold time of RTC watchdog at level 1. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG2 + description: Configures the hold time of RTC watchdog at level 2 + addressOffset: 156 + size: 32 + resetValue: 80000 + fields: + - name: WDT_STG1_HOLD + description: Configures the hold time of RTC watchdog at level 2. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG3 + description: Configures the hold time of RTC watchdog at level 3 + addressOffset: 160 + size: 32 + resetValue: 4095 + fields: + - name: WDT_STG2_HOLD + description: Configures the hold time of RTC watchdog at level 3. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG4 + description: Configures the hold time of RTC watchdog at level 4 + addressOffset: 164 + size: 32 + resetValue: 4095 + fields: + - name: WDT_STG3_HOLD + description: Configures the hold time of RTC watchdog at level 4. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTFEED + description: RTC watchdog SW feed configuration register + addressOffset: 168 + size: 32 + fields: + - name: WDT_FEED + description: Set 1 to feed the RTC watchdog. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: WDTWPROTECT + description: RTC watchdog write protection configuration register + addressOffset: 172 + size: 32 + resetValue: 1356348065 + fields: + - name: WDT_WKEY + description: Sets the write protection key of the watchdog. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SWD_CONF + description: Super watchdog configuration register + addressOffset: 176 + size: 32 + resetValue: 78643200 + fields: + - name: SWD_RESET_FLAG + description: Indicates the super watchdog reset flag. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SWD_FEED_INT + description: Receiving this interrupt leads to feeding the super watchdog via SW. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SWD_SIGNAL_WIDTH + description: Adjusts the signal width sent to the super watchdog. + bitOffset: 18 + bitWidth: 10 + access: read-write + - name: SWD_RST_FLAG_CLR + description: Set to reset the super watchdog reset flag. + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: SWD_FEED + description: Set to feed the super watchdog via SW. + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: SWD_DISABLE + description: Set this bit to disable super watchdog. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SWD_AUTO_FEED_EN + description: Set this bit to enable automatic watchdog feeding upon interrupts. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SWD_WPROTECT + description: Super watchdog write protection configuration register + addressOffset: 180 + size: 32 + resetValue: 2401055018 + fields: + - name: SWD_WKEY + description: Sets the write protection key of the super watchdog. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SW_CPU_STALL + description: CPU stall configuration register + addressOffset: 184 + size: 32 + fields: + - name: SW_STALL_APPCPU_C1 + description: "{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU" + bitOffset: 20 + bitWidth: 6 + access: read-write + - name: SW_STALL_PROCPU_C1 + description: Set this bit to allow the SW to be able to send the CPU into stalling. + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: STORE4 + description: Reservation register 4 + addressOffset: 188 + size: 32 + fields: + - name: SCRATCH4 + description: Reservation register 4. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE5 + description: Reservation register 5 + addressOffset: 192 + size: 32 + fields: + - name: SCRATCH5 + description: Reservation register 5. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE6 + description: Reservation register 6 + addressOffset: 196 + size: 32 + fields: + - name: SCRATCH6 + description: Reservation register 6. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE7 + description: Reservation register 7 + addressOffset: 200 + size: 32 + fields: + - name: SCRATCH7 + description: Reservation register 7. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOW_POWER_ST + description: RTC main state machine status register + addressOffset: 204 + size: 32 + fields: + - name: XPD_ROM0 + description: rom0 power down + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: XPD_DIG_DCDC + description: External DCDC power down + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: PERI_ISO + description: rtc peripheral iso + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: XPD_RTC_PERI + description: rtc peripheral power down + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: WIFI_ISO + description: wifi iso + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: XPD_WIFI + description: wifi wrap power down + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: DIG_ISO + description: digital wrap iso + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: XPD_DIG + description: digital wrap power down + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TOUCH_STATE_START + description: touch should start to work + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: TOUCH_STATE_SWITCH + description: touch is about to working. Switch rtc main state + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: TOUCH_STATE_SLP + description: touch is in sleep state + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TOUCH_STATE_DONE + description: touch is done + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: COCPU_STATE_START + description: ulp/cocpu should start to work + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: COCPU_STATE_SWITCH + description: ulp/cocpu is about to working. Switch rtc main state + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: COCPU_STATE_SLP + description: ulp/cocpu is in sleep state + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: COCPU_STATE_DONE + description: ulp/cocpu is done + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: MAIN_STATE_XTAL_ISO + description: no use any more + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: MAIN_STATE_PLL_ON + description: rtc main state machine is in states that pll should be running + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: RDY_FOR_WAKEUP + description: Indicates the RTC is ready to be triggered by any wakeup source. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: MAIN_STATE_WAIT_END + description: rtc main state machine has been waited for some cycles + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: IN_WAKEUP_STATE + description: rtc main state machine is in the states of wakeup process + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: IN_LOW_POWER_STATE + description: rtc main state machine is in the states of low power + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: MAIN_STATE_IN_WAIT_8M + description: rtc main state machine is in wait 8m state + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: MAIN_STATE_IN_WAIT_PLL + description: rtc main state machine is in wait pll state + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: MAIN_STATE_IN_WAIT_XTL + description: rtc main state machine is in wait xtal state + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: MAIN_STATE_IN_SLP + description: rtc main state machine is in sleep state + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: MAIN_STATE_IN_IDLE + description: rtc main state machine is in idle state + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: MAIN_STATE + description: rtc main state machine status + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: DIAG0 + description: debug register + addressOffset: 208 + size: 32 + fields: + - name: LOW_POWER_DIAG1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PAD_HOLD + description: Configures the hold options for RTC GPIOs + addressOffset: 212 + size: 32 + fields: + - name: TOUCH_PAD0_HOLD + description: Sets the touch GPIO 0 to hold. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD1_HOLD + description: Sets the touch GPIO 1 to hold. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD2_HOLD + description: Sets the touch GPIO 2 to hold. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD3_HOLD + description: Sets the touch GPIO 3 to hold. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD4_HOLD + description: Sets the touch GPIO 4 to hold. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD5_HOLD + description: Sets the touch GPIO 5 to hold. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD6_HOLD + description: Sets the touch GPIO 6 to hold. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD7_HOLD + description: Sets the touch GPIO 7 to hold. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD8_HOLD + description: Sets the touch GPIO 8 to hold. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD9_HOLD + description: Sets the touch GPIO 9 to hold. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD10_HOLD + description: Sets the touch GPIO 10 to hold. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD11_HOLD + description: Sets the touch GPIO 11 to hold. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD12_HOLD + description: Sets the touch GPIO 12 to hold. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD13_HOLD + description: Sets the touch GPIO 13 to hold. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD14_HOLD + description: Sets the touch GPIO 14 to hold. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: X32P_HOLD + description: Sets the x32p to hold. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: X32N_HOLD + description: Sets the x32n to hold. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PDAC1_HOLD + description: Sets the pdac1 to hold. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: PDAC2_HOLD + description: Sets the pdac2 to hold. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: PAD19_HOLD + description: Sets the RTG GPIO 19 to hold. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PAD20_HOLD + description: Sets the RTG GPIO 20 to hold. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: PAD21_HOLD + description: Sets the RTG GPIO 21 to hold. + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + name: DIG_PAD_HOLD + description: Configures the hold option for digital GPIOs + addressOffset: 216 + size: 32 + fields: + - name: DIG_PAD_HOLD + description: Set GPIO 21 to GPIO 45 to hold. (See bitmap to locate any GPIO). + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: EXT_WAKEUP1 + description: EXT1 wakeup configuration register + addressOffset: 220 + size: 32 + fields: + - name: SEL + description: Selects a RTC GPIO to be the EXT1 wakeup source. + bitOffset: 0 + bitWidth: 22 + access: read-write + - name: STATUS_CLR + description: Clears the EXT1 wakeup status. + bitOffset: 22 + bitWidth: 1 + access: write-only + - register: + name: EXT_WAKEUP1_STATUS + description: EXT1 wakeup source register + addressOffset: 224 + size: 32 + fields: + - name: EXT_WAKEUP1_STATUS + description: Indicates the EXT1 wakeup status. + bitOffset: 0 + bitWidth: 22 + access: read-only + - register: + name: BROWN_OUT + description: Brownout configuration register + addressOffset: 228 + size: 32 + resetValue: 67055601 + fields: + - name: BROWN_OUT2_ENA + description: Enables the brown_out2 to initiate a chip reset. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: INT_WAIT + description: Configures the waiting cycle before sending an interrupt. + bitOffset: 4 + bitWidth: 10 + access: read-write + - name: CLOSE_FLASH_ENA + description: Set this bit to enable PD the flash when a brown-out happens. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PD_RF_ENA + description: Set this bit to enable PD the RF circuits when a brown-out happens. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RST_WAIT + description: Configures the waiting cycle before the reset after a brown-out. + bitOffset: 16 + bitWidth: 10 + access: read-write + - name: RST_ENA + description: Enables to reset brown-out. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RST_SEL + description: "Selects the reset type when a brown-out happens. 1: chip reset 0: system reset." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: CNT_CLR + description: Clears the brown-out counter. + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: ENA + description: Set this bit to enable brown-out detection. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DET + description: Indicates the status of the brown-out signal. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: TIME_LOW1 + description: Stores the lower 32 bits of RTC timer 1 + addressOffset: 232 + size: 32 + fields: + - name: TIMER_VALUE1_LOW + description: Stores the lower 32 bits of RTC timer 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: TIME_HIGH1 + description: Stores the higher 16 bits of RTC timer 1 + addressOffset: 236 + size: 32 + fields: + - name: TIMER_VALUE1_HIGH + description: Stores the higher 16 bits of RTC timer. + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: XTAL32K_CLK_FACTOR + description: Configures the divider factor for the backup clock of 32 kHz crystal oscillator + addressOffset: 240 + size: 32 + fields: + - name: XTAL32K_CLK_FACTOR + description: Configures the divider factor for the 32 kHz crystal oscillator. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: XTAL32K_CONF + description: 32 kHz crystal oscillator configuration register + addressOffset: 244 + size: 32 + resetValue: 267386880 + fields: + - name: XTAL32K_RETURN_WAIT + description: Defines the waiting cycles before returning to the normal 32 kHz crystal oscillator. + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: XTAL32K_RESTART_WAIT + description: Defines the maximum waiting cycle before restarting the 32 kHz crystal oscillator. + bitOffset: 4 + bitWidth: 16 + access: read-write + - name: XTAL32K_WDT_TIMEOUT + description: "Defines the maximum waiting period for clock detection. If no clock is detected after this period, the 32 kHz crystal oscillator can be regarded as dead." + bitOffset: 20 + bitWidth: 8 + access: read-write + - name: XTAL32K_STABLE_THRES + description: "Defines the maximum allowed restarting period, within which the 32 kHz crystal oscillator can be regarded as stable." + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: ULP_CP_TIMER + description: Configure coprocessor timer + addressOffset: 248 + size: 32 + fields: + - name: ULP_CP_PC_INIT + description: ULP coprocessor PC initial address + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: ULP_CP_GPIO_WAKEUP_ENA + description: "Enable the option of ULP coprocessor woken up by\nRTC GPIO" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ULP_CP_GPIO_WAKEUP_CLR + description: "Disable the option of ULP coprocessor woken up by\nRTC GPIO" + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: ULP_CP_SLP_TIMER_EN + description: "ULP coprocessor timer enable bit. 0: Disable hardware\nTimer. 1: Enable hardware timer" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: ULP_CP_CTRL + description: ULP-FSM configuration register + addressOffset: 252 + size: 32 + resetValue: 1049088 + fields: + - name: ULP_CP_MEM_ADDR_INIT + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: ULP_CP_MEM_ADDR_SIZE + bitOffset: 11 + bitWidth: 11 + access: read-write + - name: ULP_CP_MEM_OFFSET_CLR + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: ULP_CP_CLK_FO + description: ULP-FSM clock force on + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: ULP_CP_RESET + description: ULP-FSM clock software reset + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ULP_CP_FORCE_START_TOP + description: Write 1 to start ULP-FSM by software + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: ULP_CP_START_TOP + description: Write 1 to start ULP-FSM + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COCPU_CTRL + description: ULP-RISCV configuration register + addressOffset: 256 + size: 32 + resetValue: 9046032 + fields: + - name: COCPU_CLK_FO + description: ULP-RISCV clock force on + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: COCPU_START_2_RESET_DIS + description: Time from ULP-RISCV startup to pull down reset + bitOffset: 1 + bitWidth: 6 + access: read-write + - name: COCPU_START_2_INTR_EN + description: "Time from ULP-RISCV startup to send out\nRISCV_START_INT interrupt" + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: COCPU_SHUT + description: Shut down ULP-RISCV + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: COCPU_SHUT_2_CLK_DIS + description: Time from shut down ULP-RISCV to disable clock + bitOffset: 14 + bitWidth: 8 + access: read-write + - name: COCPU_SHUT_RESET_EN + description: This bit is used to reset ULP-RISCV + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: COCPU_SEL + description: "0: select ULP-RISCV. 1: select ULP-FSM" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: COCPU_DONE_FORCE + description: "0: select ULP-FSM DONE signal. 1: select ULP-RISCV DONE\nsignal" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: COCPU_DONE + description: "DONE signal. Write 1 to this bit, ULP-RISCV will go to HALT and the\ntimer starts counting" + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: COCPU_SW_INT_TRIGGER + description: Trigger ULP-RISCV register interrupt + bitOffset: 26 + bitWidth: 1 + access: write-only + - register: + name: TOUCH_CTRL1 + description: Touch control register + addressOffset: 260 + size: 32 + resetValue: 268435712 + fields: + - name: TOUCH_SLEEP_CYCLES + description: Set sleep cycles for touch timer. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: TOUCH_MEAS_NUM + description: "Configure measurement length (in 8 MHz), i.e., charge/discharge times." + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: TOUCH_CTRL2 + description: Touch control register + addressOffset: 264 + size: 32 + resetValue: 540876 + fields: + - name: TOUCH_DRANGE + description: TOUCH attenuation. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: TOUCH_DREFL + description: "TOUCH reference voltage low. 0: 0.5 V 1: 0.6 V 2: 0.7 V 3: 0.8 V." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: TOUCH_DREFH + description: "TOUCH reference voltage high. 0: 2.4 V 1: 2.5 V 2: 2.6 V 3: 2.7 V." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: TOUCH_XPD_BIAS + description: TOUCH BIAS power switch. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TOUCH_REFC + description: Touch pad 0 reference capacitance. + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: TOUCH_DBIAS + description: "0: Use bandgap bias. 1: Use self bias." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TOUCH_SLP_TIMER_EN + description: Touch timer enable bit. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TOUCH_START_FSM_EN + description: "0: TOUCH_START and TOUCH_XPD are controlled by soft- ware. 1: TOUCH_START and TOUCH_XPD are controlled by the Touch FSM." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TOUCH_START_EN + description: "1: Start the Touch FSM, only valid when RTC_CNTL_TOUCH_START_FORCE = 1." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TOUCH_START_FORCE + description: "0: Start the Touch FSM by timer. 1: Start Touch FSM by software." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: TOUCH_XPD_WAIT + description: The waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD. + bitOffset: 17 + bitWidth: 8 + access: read-write + - name: TOUCH_SLP_CYC_DIV + description: "When a touch pad is active, sleep cycle could be divided by this number." + bitOffset: 25 + bitWidth: 2 + access: read-write + - name: TOUCH_TIMER_FORCE_DONE + description: Force touch timer done. + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: TOUCH_RESET + description: Reset TOUCH FSM via software. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TOUCH_CLK_FO + description: Touch clock force on. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TOUCH_CLKGATE_EN + description: Touch clock enable bit. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TOUCH_SCAN_CTRL + description: Configure touch scan settings + addressOffset: 268 + size: 32 + resetValue: 4026532098 + fields: + - name: TOUCH_DENOISE_RES + description: "Denoise resolution. 0: 12-bit; 1: 10-bit; 2: 8-bit; 3: 4-bit." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: TOUCH_DENOISE_EN + description: Touch pad 0 will be used to denoise. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TOUCH_INACTIVE_CONNECTION + description: "Inactive touch pads connect to 0: HighZ, 1: GND." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TOUCH_SHIELD_PAD_EN + description: Touch pad 14 will be used as shield_pad. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TOUCH_SCAN_PAD_MAP + description: Pad enable map for touch scan mode. + bitOffset: 10 + bitWidth: 15 + access: read-write + - name: TOUCH_BUFDRV + description: Touch 14 buffer driver strength. + bitOffset: 25 + bitWidth: 3 + access: read-write + - name: TOUCH_OUT_RING + description: Select out one pad as guard_ring. + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: TOUCH_SLP_THRES + description: Configure the settings of touch sleep pad + addressOffset: 272 + size: 32 + resetValue: 2013265920 + fields: + - name: TOUCH_SLP_TH + description: Set the threshold for touch sleep pad. + bitOffset: 0 + bitWidth: 22 + access: read-write + - name: TOUCH_SLP_APPROACH_EN + description: Enable the proximity mode of touch sleep pad. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TOUCH_SLP_PAD + description: Select sleep pad. + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: TOUCH_APPROACH + description: Configure touch approach settings + addressOffset: 276 + size: 32 + resetValue: 1342177280 + fields: + - name: TOUCH_SLP_CHANNEL_CLR + description: Clear touch sleep channel. + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: MEAS_TIME + description: "Set the total measurement times for the pads in\nproximity mode. Range: 0 – 255." + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: TOUCH_FILTER_CTRL + description: Configure touch filter settings + addressOffset: 280 + size: 32 + resetValue: 2527758336 + fields: + - name: TOUCH_SMOOTH_LVL + description: "0: Raw data. 1: IIR1/2. 2: IIR1/4. 3: IIR1/8." + bitOffset: 9 + bitWidth: 2 + access: read-write + - name: TOUCH_JITTER_STEP + description: "Touch jitter step. Range: 0 – 15." + bitOffset: 11 + bitWidth: 4 + access: read-write + - name: TOUCH_NEG_NOISE_LIMIT + description: Negative threshold counter limit. + bitOffset: 15 + bitWidth: 4 + access: read-write + - name: TOUCH_NEG_NOISE_THRES + description: Negative noise threshold. + bitOffset: 19 + bitWidth: 2 + access: read-write + - name: TOUCH_NOISE_THRES + description: Active noise threshold. + bitOffset: 21 + bitWidth: 2 + access: read-write + - name: TOUCH_HYSTERESIS + description: Touch hysteresis. + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: TOUCH_DEBOUNCE + description: Debounce counter. + bitOffset: 25 + bitWidth: 3 + access: read-write + - name: TOUCH_FILTER_MODE + description: "Set filter mode. 0: IIR 1/2; 1: IIR 1/4; 2: IIR 1/8; 3: IIR 1/16; 4: IIR 1/32; 5: IIR 1/64; 6: IIR 1/128; 7: Jitter." + bitOffset: 28 + bitWidth: 3 + access: read-write + - name: TOUCH_FILTER_EN + description: Enable touch filter. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USB_CONF + description: configure usb control register + addressOffset: 284 + size: 32 + fields: + - name: USB_VREFH + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: USB_VREFL + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: USB_VREF_OVERRIDE + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: USB_PAD_PULL_OVERRIDE + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: USB_DP_PULLUP + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: USB_DP_PULLDOWN + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: USB_DM_PULLUP + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: USB_DM_PULLDOWN + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: USB_PULLUP_VALUE + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: USB_PAD_ENABLE_OVERRIDE + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: USB_PAD_ENABLE + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: USB_TXM + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: USB_TXP + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: USB_TX_EN + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: USB_TX_EN_OVERRIDE + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: USB_RESET_DISABLE + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: IO_MUX_RESET_DISABLE + bitOffset: 18 + bitWidth: 1 + access: read-write + - register: + name: TOUCH_TIMEOUT_CTRL + description: Configure touch timeout settings + addressOffset: 288 + size: 32 + resetValue: 8388607 + fields: + - name: TOUCH_TIMEOUT_NUM + description: Set touch timeout threshold. + bitOffset: 0 + bitWidth: 22 + access: read-write + - name: TOUCH_TIMEOUT_EN + description: Enable touch timeout. + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: SLP_REJECT_CAUSE + description: Stores the reject-to-sleep cause. + addressOffset: 292 + size: 32 + fields: + - name: REJECT_CAUSE + description: Stores the reject-to-sleep cause. + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: OPTIONS1 + description: RTC option register + addressOffset: 296 + size: 32 + fields: + - name: FORCE_DOWNLOAD_BOOT + description: Set this bit to force the chip to boot from the download mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SLP_WAKEUP_CAUSE + description: Stores the sleep-to-wakeup cause. + addressOffset: 300 + size: 32 + fields: + - name: WAKEUP_CAUSE + description: Stores the wakeup cause. + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: ULP_CP_TIMER_1 + description: Configure sleep cycle of the timer + addressOffset: 304 + size: 32 + resetValue: 51200 + fields: + - name: ULP_CP_TIMER_SLP_CYCLE + description: Set sleep cycles for ULP coprocessor timer + bitOffset: 8 + bitWidth: 24 + access: read-write + - register: + name: DATE + addressOffset: 312 + size: 32 + resetValue: 26239377 + fields: + - name: CNTL_DATE + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: RTC_I2C + description: Low-power I2C (Inter-Integrated Circuit) Controller + groupName: RTC_I2C + baseAddress: 1061194752 + addressBlock: + - offset: 0 + size: 124 + usage: registers + registers: + - register: + name: SCL_LOW + description: Configure the low level width of SCL + addressOffset: 0 + size: 32 + resetValue: 256 + fields: + - name: PERIOD + description: "This register is used to configure how many clock cycles SCL\nremains low." + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: CTRL + description: Transmission setting + addressOffset: 4 + size: 32 + fields: + - name: SDA_FORCE_OUT + description: "SDA output mode. 0: open drain. 1: push pull." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_FORCE_OUT + description: "SCL output mode. 0: open drain. 1: push pull." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MS_MODE + description: Set this bit to configure RTC I²C as a master. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TRANS_START + description: "Set this bit to 1, RTC I2C starts sending data." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_LSB_FIRST + description: "This bit is used to control the sending mode. 0: send data from the most\nsignificant bit. 1: send data from the least significant bit." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_LSB_FIRST + description: "This bit is used to control the storage mode for received data. 0: receive\ndata from the most significant bit. 1: receive data from the least significant bit." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CLK_GATE_EN + description: RTC I²C controller clock gate. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: RESET + description: RTC I²C software reset. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: rtc i2c reg clk gating + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: STATUS + description: RTC I2C status + addressOffset: 8 + size: 32 + fields: + - name: ACK_REC + description: "The received ACK value. 0: ACK. 1: NACK." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SLAVE_RW + description: "0: master writes to slave. 1: master reads from slave." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ARB_LOST + description: "When the RTC I2C loses control of SCL line, the register changes to 1." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: BUS_BUSY + description: "0: RTC I2C bus is in idle state. 1: RTC I2C bus is busy transferring data." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SLAVE_ADDRESSED + description: "When the address sent by the master matches the address of the\nslave, then this bit will be set." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS + description: This field changes to 1 when one byte is transferred. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OP_CNT + description: Indicate which operation is working. + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: SHIFT + description: shifter content + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: SCL_MAIN_STATE_LAST + description: i2c last main status + bitOffset: 24 + bitWidth: 3 + access: read-only + - name: SCL_STATE_LAST + description: scl last status + bitOffset: 28 + bitWidth: 3 + access: read-only + - register: + name: TO + description: Configure RTC I2C timeout + addressOffset: 12 + size: 32 + resetValue: 65536 + fields: + - name: TIME_OUT + description: Timeout threshold + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: SLAVE_ADDR + description: Configure slave address + addressOffset: 16 + size: 32 + fields: + - name: SLAVE_ADDR + description: slave address + bitOffset: 0 + bitWidth: 15 + access: read-write + - name: ADDR_10BIT_EN + description: This field is used to enable the slave 10-bit addressing mode. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SCL_HIGH + description: Configure the high level width of SCL + addressOffset: 20 + size: 32 + resetValue: 256 + fields: + - name: PERIOD + description: This register is used to configure how many cycles SCL remains high. + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: SDA_DUTY + description: "Configure the SDA hold time after a negative\nSCL edge" + addressOffset: 24 + size: 32 + resetValue: 16 + fields: + - name: NUM + description: "The number of clock cycles between the SDA switch and the falling\nedge of SCL." + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: SCL_START_PERIOD + description: "Configure the delay between the SDA and SCL\nnegative edge for a start condition" + addressOffset: 28 + size: 32 + resetValue: 8 + fields: + - name: SCL_START_PERIOD + description: Number of clock cycles to wait after generating a start condition. + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: SCL_STOP_PERIOD + description: Configure the delay between SDA and SCL positive edge for a stop condition + addressOffset: 32 + size: 32 + resetValue: 8 + fields: + - name: SCL_STOP_PERIOD + description: Number of clock cycles to wait before generating a stop condition. + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: INT_CLR + description: Clear RTC I2C interrupt + addressOffset: 36 + size: 32 + fields: + - name: SLAVE_TRAN_COMP_INT_CLR + description: RTC_I2C_SLAVE_TRAN_COMP_INT interrupt clear bit + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ARBITRATION_LOST_INT_CLR + description: RTC_I2C_ARBITRATION_LOST_INT interrupt clear bit + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: MASTER_TRAN_COMP_INT_CLR + description: "RTC_I2C_MASTER_TRAN_COMP_INT interrupt\nclear bit" + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TRANS_COMPLETE_INT_CLR + description: RTC_I2C_TRANS_COMPLETE_INT interrupt clear bit + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TIME_OUT_INT_CLR + description: RTC_I2C_TIME_OUT_INT interrupt clear bit + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: ACK_ERR_INT_CLR + description: RTC_I2C_ACK_ERR_INT interrupt clear bit + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: RX_DATA_INT_CLR + description: RTC_I2C_RX_DATA_INT interrupt clear bit + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TX_DATA_INT_CLR + description: RTC_I2C_TX_DATA_INT interrupt clear bit + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: DETECT_START_INT_CLR + description: RTC_I2C_DETECT_START_INT interrupt clear bit + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: INT_RAW + description: RTC I2C raw interrupt + addressOffset: 40 + size: 32 + fields: + - name: SLAVE_TRAN_COMP_INT_RAW + description: RTC_I2C_SLAVE_TRAN_COMP_INT interrupt raw bit + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_RAW + description: RTC_I2C_ARBITRATION_LOST_INT interrupt raw bit + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: MASTER_TRAN_COMP_INT_RAW + description: RTC_I2C_MASTER_TRAN_COMP_INT interrupt raw bit + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_RAW + description: RTC_I2C_TRANS_COMPLETE_INT interrupt raw bit + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_RAW + description: RTC_I2C_TIME_OUT_INT interrupt raw bit + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ACK_ERR_INT_RAW + description: RTC_I2C_ACK_ERR_INT interrupt raw bit + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: RX_DATA_INT_RAW + description: RTC_I2C_RX_DATA_INT interrupt raw bit + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TX_DATA_INT_RAW + description: RTC_I2C_TX_DATA_INT interrupt raw bit + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DETECT_START_INT_RAW + description: RTC_I2C_DETECT_START_INT interrupt raw bit + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: RTC I2C interrupt status + addressOffset: 44 + size: 32 + fields: + - name: SLAVE_TRAN_COMP_INT_ST + description: RTC_I2C_SLAVE_TRAN_COMP_INT interrupt status bit + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_ST + description: RTC_I2C_ARBITRATION_LOST_INT interrupt status bit + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: MASTER_TRAN_COMP_INT_ST + description: RTC_I2C_MASTER_TRAN_COMP_INT interrupt status bit + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_ST + description: RTC_I2C_TRANS_COMPLETE_INT interrupt status bit + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_ST + description: RTC_I2C_TIME_OUT_INT interrupt status bit + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ACK_ERR_INT_ST + description: RTC_I2C_ACK_ERR_INT interrupt status bit + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: RX_DATA_INT_ST + description: RTC_I2C_RX_DATA_INT interrupt status bit + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TX_DATA_INT_ST + description: RTC_I2C_TX_DATA_INT interrupt status bit + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DETECT_START_INT_ST + description: RTC_I2C_DETECT_START_INT interrupt status bit + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Enable RTC I2C interrupt + addressOffset: 48 + size: 32 + fields: + - name: SLAVE_TRAN_COMP_INT_ENA + description: RTC_I2C_SLAVE_TRAN_COMP_INT interrupt enable bit + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ARBITRATION_LOST_INT_ENA + description: RTC_I2C_ARBITRATION_LOST_INT interrupt enable bit + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MASTER_TRAN_COMP_INT_ENA + description: RTC_I2C_MASTER_TRAN_COMP_INT interrupt enable bit + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TRANS_COMPLETE_INT_ENA + description: RTC_I2C_TRANS_COMPLETE_INT interrupt enable bit + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TIME_OUT_INT_ENA + description: RTC_I2C_TIME_OUT_INT interrupt enable bit + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ACK_ERR_INT_ENA + description: RTC_I2C_ACK_ERR_INT interrupt enable bit + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RX_DATA_INT_ENA + description: RTC_I2C_RX_DATA_INT interrupt enable bit + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_DATA_INT_ENA + description: RTC_I2C_TX_DATA_INT interrupt enable bit + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DETECT_START_INT_ENA + description: RTC_I2C_DETECT_START_INT interrupt enable bit + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: DATA + description: RTC I2C read data + addressOffset: 52 + size: 32 + fields: + - name: RDATA + description: Data received + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: SLAVE_TX_DATA + description: The data sent by slave + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: DONE + description: RTC I2C transmission is done. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + dim: 16 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" + name: CMD%s + description: RTC I2C Command %s + addressOffset: 56 + size: 32 + resetValue: 2307 + fields: + - name: COMMAND + description: "Content of command 0. For more information, please refer to the register\nI2C_COMD0_REG in Chapter I²C Controller" + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND_DONE + description: "When command 0 is done, this bit changes to 1." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: Version control register + addressOffset: 252 + size: 32 + resetValue: 26235664 + fields: + - name: DATE + description: Version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SENS + description: SENS Peripheral + groupName: SENS + baseAddress: 1061193728 + addressBlock: + - offset: 0 + size: 272 + usage: registers + registers: + - register: + name: SAR_READER1_CTRL + description: RTC ADC1 data and sampling control + addressOffset: 0 + size: 32 + resetValue: 537133058 + fields: + - name: SAR1_CLK_DIV + description: Clock divider. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SAR1_CLK_GATED + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SAR1_SAMPLE_NUM + bitOffset: 19 + bitWidth: 8 + access: read-write + - name: SAR1_DATA_INV + description: Invert SAR ADC1 data. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SAR1_INT_EN + description: Enable SAR ADC1 to send out interrupt. + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: SAR_READER1_STATUS + description: saradc1 status for debug + addressOffset: 4 + size: 32 + fields: + - name: SAR1_READER_STATUS + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SAR_MEAS1_CTRL1 + description: Configure RTC ADC1 controller + addressOffset: 8 + size: 32 + fields: + - name: RTC_SARADC_RESET + description: SAR ADC software reset. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RTC_SARADC_CLKGATE_EN + description: Enable bit of SAR ADC clock gate. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: FORCE_XPD_AMP + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: AMP_RST_FB_FORCE + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: AMP_SHORT_REF_FORCE + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: AMP_SHORT_REF_GND_FORCE + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: SAR_MEAS1_CTRL2 + description: Control RTC ADC1 conversion and status + addressOffset: 12 + size: 32 + fields: + - name: MEAS1_DATA_SAR + description: SAR ADC1 data + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: MEAS1_DONE_SAR + description: Indicate SAR ADC1 conversion is done. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: MEAS1_START_SAR + description: "SAR ADC1 controller (in RTC) starts conversion, active only when SENS_MEAS1_START_FORCE = 1." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MEAS1_START_FORCE + description: "1: SAR ADC1 controller (in RTC) is started by software. 0: SAR ADC1 controller is started by ULP coprocessor." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SAR1_EN_PAD + description: "SAR ADC1 pad enable bitmap, active only when SENS_SAR1_EN_PAD_FORCE = 1." + bitOffset: 19 + bitWidth: 12 + access: read-write + - name: SAR1_EN_PAD_FORCE + description: "1: SAR ADC1 pad enable bitmap is controlled by software. 0: SAR ADC1 pad enable bitmap is controlled by ULP coprocessor." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAR_MEAS1_MUX + description: Select the controller for SAR ADC1 + addressOffset: 16 + size: 32 + fields: + - name: SAR1_DIG_FORCE + description: "1: SAR ADC1 controlled by DIG ADC1 CTRL" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAR_ATTEN1 + description: Configure SAR ADC1 attenuation + addressOffset: 20 + size: 32 + resetValue: 4294967295 + fields: + - name: SAR1_ATTEN + description: "2-bit attenuation for each pad. [1:0] is used for channel 0, [3:2] is used for channel 1, etc." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SAR_AMP_CTRL1 + description: AMP control + addressOffset: 24 + size: 32 + resetValue: 655370 + fields: + - name: SAR_AMP_WAIT1 + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SAR_AMP_WAIT2 + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SAR_AMP_CTRL2 + description: AMP control + addressOffset: 28 + size: 32 + resetValue: 655360 + fields: + - name: SAR1_DAC_XPD_FSM_IDLE + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: XPD_SAR_AMP_FSM_IDLE + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AMP_RST_FB_FSM_IDLE + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: AMP_SHORT_REF_FSM_IDLE + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: AMP_SHORT_REF_GND_FSM_IDLE + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: XPD_SAR_FSM_IDLE + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SAR_RSTB_FSM_IDLE + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SAR_AMP_WAIT3 + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SAR_AMP_CTRL3 + description: AMP control register + addressOffset: 32 + size: 32 + resetValue: 7551219 + fields: + - name: SAR1_DAC_XPD_FSM + description: "Control of DAC. 4’b0010: disable DAC. 4’b0000: power up DAC by FSM. 4’b0011: power up DAC by software." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: XPD_SAR_AMP_FSM + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: AMP_RST_FB_FSM + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: AMP_SHORT_REF_FSM + bitOffset: 12 + bitWidth: 4 + access: read-write + - name: AMP_SHORT_REF_GND_FSM + bitOffset: 16 + bitWidth: 4 + access: read-write + - name: XPD_SAR_FSM + bitOffset: 20 + bitWidth: 4 + access: read-write + - name: SAR_RSTB_FSM + bitOffset: 24 + bitWidth: 4 + access: read-write + - register: + name: SAR_READER2_CTRL + description: RTC ADC2 data and sampling control + addressOffset: 36 + size: 32 + resetValue: 1074069506 + fields: + - name: SAR2_CLK_DIV + description: clock divider + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SAR2_WAIT_ARB_CYCLE + description: wait arbit stable after sar_done + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: SAR2_CLK_GATED + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SAR2_SAMPLE_NUM + bitOffset: 19 + bitWidth: 8 + access: read-write + - name: SAR2_DATA_INV + description: Invert SAR ADC2 data + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SAR2_INT_EN + description: enable saradc2 to send out interrupt + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: SAR_READER2_STATUS + description: saradc2 status for debug + addressOffset: 40 + size: 32 + fields: + - name: SAR2_READER_STATUS + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SAR_MEAS2_CTRL1 + description: configure rtc saradc2 + addressOffset: 44 + size: 32 + resetValue: 117572096 + fields: + - name: SAR2_CNTL_STATE + description: saradc2_cntl_fsm + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: SAR2_PWDET_CAL_EN + description: rtc control pwdet enable + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SAR2_PKDET_CAL_EN + description: rtc control pkdet enable + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SAR2_EN_TEST + description: SAR2_EN_TEST + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SAR2_RSTB_FORCE + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: SAR2_STANDBY_WAIT + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SAR2_RSTB_WAIT + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SAR2_XPD_WAIT + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: SAR_MEAS2_CTRL2 + description: Control RTC ADC2 conversion and status + addressOffset: 48 + size: 32 + fields: + - name: MEAS2_DATA_SAR + description: SAR ADC2 data. + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: MEAS2_DONE_SAR + description: Indicate SAR ADC2 conversion is done. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: MEAS2_START_SAR + description: "SAR ADC2 controller (in RTC) starts conversion, active only when SENS_MEAS2_START_FORCE = 1." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MEAS2_START_FORCE + description: "1: SAR ADC2 controller (in RTC) is started by software. 0: SAR ADC2 controller is started by ULP coprocessor." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SAR2_EN_PAD + description: "SAR ADC2 pad enable bitmap, active only whenSENS_SAR2_EN_PAD_FORCE = 1." + bitOffset: 19 + bitWidth: 12 + access: read-write + - name: SAR2_EN_PAD_FORCE + description: "1: SAR ADC2 pad enable bitmap is controlled by software. 0: SAR ADC2 pad enable bitmap is controlled by ULP coprocessor." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAR_MEAS2_MUX + description: Select the controller for SAR ADC2 + addressOffset: 52 + size: 32 + fields: + - name: SAR2_PWDET_CCT + description: "SAR2_PWDET_CCT, PA power detector capacitance tuning." + bitOffset: 28 + bitWidth: 3 + access: read-write + - name: SAR2_RTC_FORCE + description: "In sleep, force to use RTC to control ADC." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAR_ATTEN2 + description: Configure SAR ADC2 attenuation + addressOffset: 56 + size: 32 + resetValue: 4294967295 + fields: + - name: SAR2_ATTEN + description: "2-bit attenuation for each pad. [1:0] is used for channel 0, [3:2] is used for channel 1, etc." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SAR_POWER_XPD_SAR + description: configure saradc’s power by sw + addressOffset: 60 + size: 32 + fields: + - name: FORCE_XPD_SAR + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: SARCLK_EN + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAR_SLAVE_ADDR1 + description: Configure slave addresses 0-1 of RTC I2C + addressOffset: 64 + size: 32 + fields: + - name: I2C_SLAVE_ADDR1 + description: RTC I2C slave address 1 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: I2C_SLAVE_ADDR0 + description: RTC I2C slave address 0 + bitOffset: 11 + bitWidth: 11 + access: read-write + - name: MEAS_STATUS + bitOffset: 22 + bitWidth: 8 + access: read-only + - register: + name: SAR_SLAVE_ADDR2 + description: Configure slave addresses 2-3 of RTC I2C + addressOffset: 68 + size: 32 + fields: + - name: I2C_SLAVE_ADDR3 + description: RTC I2C slave address 3 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: I2C_SLAVE_ADDR2 + description: RTC I2C slave address 2 + bitOffset: 11 + bitWidth: 11 + access: read-write + - register: + name: SAR_SLAVE_ADDR3 + description: Configure slave addresses 4-5 of RTC I2C + addressOffset: 72 + size: 32 + fields: + - name: I2C_SLAVE_ADDR5 + description: RTC I2C slave address 5 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: I2C_SLAVE_ADDR4 + description: RTC I2C slave address 4 + bitOffset: 11 + bitWidth: 11 + access: read-write + - register: + name: SAR_SLAVE_ADDR4 + description: Configure slave addresses 6-7 of RTC I2C + addressOffset: 76 + size: 32 + fields: + - name: I2C_SLAVE_ADDR7 + description: RTC I2C slave address 7 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: I2C_SLAVE_ADDR6 + description: RTC I2C slave address 6 + bitOffset: 11 + bitWidth: 11 + access: read-write + - register: + name: SAR_TSENS_CTRL + description: Temperature sensor data control + addressOffset: 80 + size: 32 + resetValue: 102400 + fields: + - name: TSENS_OUT + description: Temperature sensor data out. + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: TSENS_READY + description: Indicate temperature sensor out ready. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TSENS_INT_EN + description: Enable temperature sensor to send out interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TSENS_IN_INV + description: Invert temperature sensor data. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TSENS_CLK_DIV + description: Temperature sensor clock divider. + bitOffset: 14 + bitWidth: 8 + access: read-write + - name: TSENS_POWER_UP + description: Temperature sensor power up. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TSENS_POWER_UP_FORCE + description: "1: dump out and power up controlled by software. 0: by FSM." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TSENS_DUMP_OUT + description: Temperature sensor dump out only active when SENS_TSENS_POWER_UP_FORCE = 1. + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: SAR_TSENS_CTRL2 + description: Temperature sensor control + addressOffset: 84 + size: 32 + resetValue: 16386 + fields: + - name: TSENS_XPD_WAIT + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: TSENS_XPD_FORCE + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: TSENS_CLK_INV + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TSENS_CLKGATE_EN + description: Enable temperature sensor clock. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TSENS_RESET + description: Reset temperature sensor. + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: SAR_I2C_CTRL + description: Configure RTC I2C transmission + addressOffset: 88 + size: 32 + fields: + - name: SAR_I2C_CTRL + description: "RTC I2C control data. Active only when SENS_SAR_I2C_START_FORCE =\n1." + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SAR_I2C_START + description: Start RTC I2C. Active only when SENS_SAR_I2C_START_FORCE = 1 + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SAR_I2C_START_FORCE + description: "0: RTC I2C started by FSM. 1: RTC I2C started by software." + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: SAR_TOUCH_CONF + description: Touch sensor configuration register + addressOffset: 92 + size: 32 + resetValue: 4293951487 + fields: + - name: TOUCH_OUTEN + description: Enable touch controller output. + bitOffset: 0 + bitWidth: 15 + access: read-write + - name: TOUCH_STATUS_CLR + description: Clear all touch active status. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: TOUCH_DATA_SEL + description: "0 and 1: touch_raw_data; 2: base_line; 3: touch_smooth_data." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: TOUCH_DENOISE_END + description: Touch denoise done. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: TOUCH_UNIT_END + description: Indicate the completion of sampling. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: TOUCH_APPROACH_PAD2 + description: Indicate which pad is selected as proximity pad2 + bitOffset: 20 + bitWidth: 4 + access: read-write + - name: TOUCH_APPROACH_PAD1 + description: Indicate which pad is selected as proximity pad1 + bitOffset: 24 + bitWidth: 4 + access: read-write + - name: TOUCH_APPROACH_PAD0 + description: Indicate which pad is selected as proximity pad0 + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: SAR_TOUCH_THRES1 + description: Finger threshold for touch pad 1 + addressOffset: 96 + size: 32 + fields: + - name: TOUCH_OUT_TH1 + description: Finger threshold for touch pad 1 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES2 + description: Finger threshold for touch pad 2 + addressOffset: 100 + size: 32 + fields: + - name: TOUCH_OUT_TH2 + description: Finger threshold for touch pad 2 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES3 + description: Finger threshold for touch pad 3 + addressOffset: 104 + size: 32 + fields: + - name: TOUCH_OUT_TH3 + description: Finger threshold for touch pad 3 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES4 + description: Finger threshold for touch pad 4 + addressOffset: 108 + size: 32 + fields: + - name: TOUCH_OUT_TH4 + description: Finger threshold for touch pad 4 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES5 + description: Finger threshold for touch pad 5 + addressOffset: 112 + size: 32 + fields: + - name: TOUCH_OUT_TH5 + description: Finger threshold for touch pad 5 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES6 + description: Finger threshold for touch pad 6 + addressOffset: 116 + size: 32 + fields: + - name: TOUCH_OUT_TH6 + description: Finger threshold for touch pad 6 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES7 + description: Finger threshold for touch pad 7 + addressOffset: 120 + size: 32 + fields: + - name: TOUCH_OUT_TH7 + description: Finger threshold for touch pad 7 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES8 + description: Finger threshold for touch pad 8 + addressOffset: 124 + size: 32 + fields: + - name: TOUCH_OUT_TH8 + description: Finger threshold for touch pad 8 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES9 + description: Finger threshold for touch pad 9 + addressOffset: 128 + size: 32 + fields: + - name: TOUCH_OUT_TH9 + description: Finger threshold for touch pad 9 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES10 + description: Finger threshold for touch pad 10 + addressOffset: 132 + size: 32 + fields: + - name: TOUCH_OUT_TH10 + description: Finger threshold for touch pad 10 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES11 + description: Finger threshold for touch pad 11 + addressOffset: 136 + size: 32 + fields: + - name: TOUCH_OUT_TH11 + description: Finger threshold for touch pad 11 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES12 + description: Finger threshold for touch pad 12 + addressOffset: 140 + size: 32 + fields: + - name: TOUCH_OUT_TH12 + description: Finger threshold for touch pad 12 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES13 + description: Finger threshold for touch pad 13 + addressOffset: 144 + size: 32 + fields: + - name: TOUCH_OUT_TH13 + description: Finger threshold for touch pad 13 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES14 + description: Finger threshold for touch pad 14 + addressOffset: 148 + size: 32 + fields: + - name: TOUCH_OUT_TH14 + description: Finger threshold for touch pad 14 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_CHN_ST + description: Touch channel status register + addressOffset: 212 + size: 32 + fields: + - name: TOUCH_PAD_ACTIVE + description: Touch active status + bitOffset: 0 + bitWidth: 15 + access: read-only + - name: TOUCH_CHANNEL_CLR + description: Clear touch channel + bitOffset: 15 + bitWidth: 15 + access: write-only + - name: TOUCH_MEAS_DONE + description: Signal flag that indicates one touch pad is done. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: SAR_TOUCH_STATUS0 + description: Status of touch controller + addressOffset: 216 + size: 32 + fields: + - name: TOUCH_DENOISE_DATA + description: Denoise measure value from touch sensor 0. + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: TOUCH_SCAN_CURR + description: Current pad in scan status + bitOffset: 22 + bitWidth: 4 + access: read-only + - register: + name: SAR_TOUCH_STATUS1 + description: Touch pad 1 status + addressOffset: 220 + size: 32 + fields: + - name: TOUCH_PAD1_DATA + description: "The data of touch pad 1, depending on the setting of SENS_TOUCH_DATA_SEL." + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: TOUCH_PAD1_DEBOUNCE + description: Touch pad 1 debounce value. + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS2 + description: Touch pad 2 status + addressOffset: 224 + size: 32 + fields: + - name: TOUCH_PAD2_DATA + description: "The data of touch pad 2, depending on the setting of SENS_TOUCH_DATA_SEL." + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: TOUCH_PAD2_DEBOUNCE + description: Touch pad 2 debounce value. + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS3 + description: Touch pad 3 status + addressOffset: 228 + size: 32 + fields: + - name: TOUCH_PAD3_DATA + description: "The data of touch pad 3, depending on the setting of SENS_TOUCH_DATA_SEL." + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: TOUCH_PAD3_DEBOUNCE + description: Touch pad 3 debounce value. + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS4 + description: Touch pad 4 status + addressOffset: 232 + size: 32 + fields: + - name: TOUCH_PAD4_DATA + description: "The data of touch pad 4, depending on the setting of SENS_TOUCH_DATA_SEL." + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: TOUCH_PAD4_DEBOUNCE + description: Touch pad 4 debounce value. + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS5 + description: Touch pad 5 status + addressOffset: 236 + size: 32 + fields: + - name: TOUCH_PAD5_DATA + description: "The data of touch pad 5, depending on the setting of SENS_TOUCH_DATA_SEL." + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: TOUCH_PAD5_DEBOUNCE + description: Touch pad 5 debounce value. + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS6 + description: Touch pad 6 status + addressOffset: 240 + size: 32 + fields: + - name: TOUCH_PAD6_DATA + description: "The data of touch pad 6, depending on the setting of SENS_TOUCH_DATA_SEL." + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: TOUCH_PAD6_DEBOUNCE + description: Touch pad 6 debounce value. + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS7 + description: Touch pad 7 status + addressOffset: 244 + size: 32 + fields: + - name: TOUCH_PAD7_DATA + description: "The data of touch pad 7, depending on the setting of SENS_TOUCH_DATA_SEL." + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: TOUCH_PAD7_DEBOUNCE + description: Touch pad 7 debounce value. + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS8 + description: Touch pad 8 status + addressOffset: 248 + size: 32 + fields: + - name: TOUCH_PAD8_DATA + description: "The data of touch pad 8, depending on the setting of SENS_TOUCH_DATA_SEL." + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: TOUCH_PAD8_DEBOUNCE + description: Touch pad 8 debounce value. + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS9 + description: Touch pad 9 status + addressOffset: 252 + size: 32 + fields: + - name: TOUCH_PAD9_DATA + description: "The data of touch pad 9, depending on the setting of SENS_TOUCH_DATA_SEL." + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: TOUCH_PAD9_DEBOUNCE + description: Touch pad 9 debounce value. + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS10 + description: Touch pad 10 status + addressOffset: 256 + size: 32 + fields: + - name: TOUCH_PAD10_DATA + description: "The data of touch pad 10, depending on the setting of SENS_TOUCH_DATA_SEL." + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: TOUCH_PAD10_DEBOUNCE + description: Touch pad 10 debounce value. + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS11 + description: Touch pad 11 status + addressOffset: 260 + size: 32 + fields: + - name: TOUCH_PAD11_DATA + description: "The data of touch pad 11, depending on the setting of SENS_TOUCH_DATA_SEL." + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: TOUCH_PAD11_DEBOUNCE + description: Touch pad 11 debounce value. + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS12 + description: Touch pad 12 status + addressOffset: 264 + size: 32 + fields: + - name: TOUCH_PAD12_DATA + description: "The data of touch pad 12, depending on the setting of SENS_TOUCH_DATA_SEL." + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: TOUCH_PAD12_DEBOUNCE + description: Touch pad 12 debounce value. + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS13 + description: Touch pad 13 status + addressOffset: 268 + size: 32 + fields: + - name: TOUCH_PAD13_DATA + description: "The data of touch pad 13, depending on the setting of SENS_TOUCH_DATA_SEL." + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: TOUCH_PAD13_DEBOUNCE + description: Touch pad 13 debounce value. + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS14 + description: Touch pad 14 status + addressOffset: 272 + size: 32 + fields: + - name: TOUCH_PAD14_DATA + description: "The data of touch pad 14, depending on the setting of SENS_TOUCH_DATA_SEL." + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: TOUCH_PAD14_DEBOUNCE + description: Touch pad 14 debounce value. + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS15 + description: Touch sleep pad status + addressOffset: 276 + size: 32 + fields: + - name: TOUCH_SLP_DATA + description: "The data of touch sleep pad, depending on the setting of SENS_TOUCH_DATA_SEL." + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: TOUCH_SLP_DEBOUNCE + description: Touch sleep pad debouce value. + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS16 + description: Touch approach count status + addressOffset: 280 + size: 32 + fields: + - name: TOUCH_APPROACH_PAD2_CNT + description: Count status of proximity pad 2. + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: TOUCH_APPROACH_PAD1_CNT + description: Count status of proximity pad 1. + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: TOUCH_APPROACH_PAD0_CNT + description: Count status of proximity pad 0. + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: TOUCH_SLP_APPROACH_CNT + description: Count status of sleep pad in proximity mode. + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: SAR_DAC_CTRL1 + description: DAC control + addressOffset: 284 + size: 32 + fields: + - name: SW_FSTEP + description: Frequency step for CW generator can be used to adjust the frequency. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SW_TONE_EN + description: "0: disable CW generator. 1: enable CW generator." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DEBUG_BIT_SEL + bitOffset: 17 + bitWidth: 5 + access: read-write + - name: DAC_DIG_FORCE + description: "0: DAC1 and DAC2 do not use DMA. 1: DAC1 and DAC2 use DMA." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: DAC_CLK_FORCE_LOW + description: "1: force PDAC_CLK to low" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: DAC_CLK_FORCE_HIGH + description: "1: force PDAC_CLK to high" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: DAC_CLK_INV + description: "1: invert PDAC_CLK." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: DAC_RESET + description: Reset DAC by software. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: DAC_CLKGATE_EN + description: DAC clock gate enable bit. + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: SAR_DAC_CTRL2 + description: DAC output control + addressOffset: 288 + size: 32 + resetValue: 50331648 + fields: + - name: DAC_DC1 + description: DC offset for DAC1 CW generator. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: DAC_DC2 + description: DC offset for DAC2 CW generator. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: DAC_SCALE1 + description: "DAC1 scaling. 00: no scale. 01: scale to 1/2. 10: scale to 1/4. 11: scale to 1/8." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DAC_SCALE2 + description: "DAC2 scaling. 00: no scale. 01: scale to 1/2. 10: scale to 1/4. 11: scale to 1/8." + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DAC_INV1 + description: "Invert DAC1. 00: do not invert any bits. 01: invert all bits. 10: invert MSB. 11: invert all bits except MSB." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DAC_INV2 + description: "Invert DAC2. 00: do not invert any bits. 01: invert all bits. 10: invert MSB. 11: invert all bits except MSB." + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: DAC_CW_EN1 + description: "1: select CW generator as source for PDAC1_DAC. 0: select register RT- CIO_PDAC1_DAC as source for PDAC1_DAC." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: DAC_CW_EN2 + description: "1: select CW generator as source for PDAC2_DAC. 0: select register RT- CIO_PDAC2_DAC as source for PDAC2_DAC." + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: SAR_COCPU_STATE + description: ULP-RISCV status + addressOffset: 292 + size: 32 + fields: + - name: COCPU_DBG_TRIGGER + description: Trigger ULP-RISCV debug registers + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: COCPU_CLK_EN + description: Check ULP-RISCV whether clk on + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: COCPU_RESET_N + description: Check ULP-RISCV whether in reset state + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: COCPU_EOI + description: Check ULP-RISCV whether in interrupt state + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: COCPU_TRAP + description: Check ULP-RISCV whether in trap state + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: COCPU_EBREAK + description: Check ULP-RISCV whether in ebreak + bitOffset: 30 + bitWidth: 1 + access: read-only + - register: + name: SAR_COCPU_INT_RAW + description: Interrupt raw bit of ULP-RISCV + addressOffset: 296 + size: 32 + fields: + - name: COCPU_TOUCH_DONE_INT_RAW + description: TOUCH_DONE_INT interrupt raw bit + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: COCPU_TOUCH_INACTIVE_INT_RAW + description: TOUCH_INACTIVE_INT interrupt raw bit + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: COCPU_TOUCH_ACTIVE_INT_RAW + description: TOUCH_ACTIVE_INT interrupt raw bit + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: COCPU_SARADC1_INT_RAW + description: SARADC1_DONE_INT interrupt raw bit + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: COCPU_SARADC2_INT_RAW + description: SARADC2_DONE_INT interrupt raw bit + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: COCPU_TSENS_INT_RAW + description: TSENS_DONE_INT interrupt raw bit + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: COCPU_START_INT_RAW + description: RISCV_START_INT interrupt raw bit + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: COCPU_SW_INT_RAW + description: SW_INT interrupt raw bit + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: COCPU_SWD_INT_RAW + description: SWD_INT interrupt raw bit + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: SAR_COCPU_INT_ENA + description: Interrupt enable bit of ULP-RISCV + addressOffset: 300 + size: 32 + fields: + - name: COCPU_TOUCH_DONE_INT_ENA + description: TOUCH_DONE_INT interrupt enable bit + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: COCPU_TOUCH_INACTIVE_INT_ENA + description: TOUCH_INACTIVE_INT interrupt enable bit + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: COCPU_TOUCH_ACTIVE_INT_ENA + description: TOUCH_ACTIVE_INT interrupt enable bit + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: COCPU_SARADC1_INT_ENA + description: SARADC1_DONE_INT interrupt enable bit + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: COCPU_SARADC2_INT_ENA + description: SARADC2_DONE_INT interrupt enable bit + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: COCPU_TSENS_INT_ENA + description: TSENS_DONE_INT interrupt enable bit + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: COCPU_START_INT_ENA + description: RISCV_START_INT interrupt enable bit + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: COCPU_SW_INT_ENA + description: SW_INT interrupt enable bit + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: COCPU_SWD_INT_ENA + description: SWD_INT interrupt enable bit + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: SAR_COCPU_INT_ST + description: Interrupt status bit of ULP-RISCV + addressOffset: 304 + size: 32 + fields: + - name: COCPU_TOUCH_DONE_INT_ST + description: TOUCH_DONE_INT interrupt status bit + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: COCPU_TOUCH_INACTIVE_INT_ST + description: TOUCH_INACTIVE_INT interrupt status bit + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: COCPU_TOUCH_ACTIVE_INT_ST + description: TOUCH_ACTIVE_INT interrupt status bit + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: COCPU_SARADC1_INT_ST + description: SARADC1_DONE_INT interrupt status bit + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: COCPU_SARADC2_INT_ST + description: SARADC2_DONE_INT interrupt status bit + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: COCPU_TSENS_INT_ST + description: TSENS_DONE_INT interrupt status bit + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: COCPU_START_INT_ST + description: RISCV_START_INT interrupt status bit + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: COCPU_SW_INT_ST + description: SW_INT interrupt status bit + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: COCPU_SWD_INT_ST + description: SWD_INT interrupt status bit + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: SAR_COCPU_INT_CLR + description: Interrupt clear bit of ULP-RISCV + addressOffset: 308 + size: 32 + fields: + - name: COCPU_TOUCH_DONE_INT_CLR + description: TOUCH_DONE_INT interrupt clear bit + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: COCPU_TOUCH_INACTIVE_INT_CLR + description: TOUCH_INACTIVE_INT interrupt clear bit + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: COCPU_TOUCH_ACTIVE_INT_CLR + description: TOUCH_ACTIVE_INT interrupt clear bit + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: COCPU_SARADC1_INT_CLR + description: SARADC1_DONE_INT interrupt clear bit + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: COCPU_SARADC2_INT_CLR + description: SARADC2_DONE_INT interrupt clear bit + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: COCPU_TSENS_INT_CLR + description: TSENS_DONE_INT interrupt clear bit + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: COCPU_START_INT_CLR + description: RISCV_START_INT interrupt clear bit + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: COCPU_SW_INT_CLR + description: SW_INT interrupt clear bit + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: COCPU_SWD_INT_CLR + description: SWD_INT interrupt clear bit + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: SAR_COCPU_DEBUG + description: ULP-RISCV debug register + addressOffset: 312 + size: 32 + fields: + - name: COCPU_PC + description: ULP-RISCV Program counter + bitOffset: 0 + bitWidth: 13 + access: read-only + - name: COCPU_MEM_VLD + description: ULP-RISCV memory valid output + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: COCPU_MEM_RDY + description: ULP-RISCV memory ready input + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: COCPU_MEM_WEN + description: ULP-RISCV memory write enable output + bitOffset: 15 + bitWidth: 4 + access: read-only + - name: COCPU_MEM_ADDR + description: ULP-RISCV memory address output + bitOffset: 19 + bitWidth: 13 + access: read-only + - register: + name: SAR_HALL_CTRL + description: hall control + addressOffset: 316 + size: 32 + resetValue: 2684354560 + fields: + - name: XPD_HALL + description: Power on hall sensor and connect to VP and VN + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: XPD_HALL_FORCE + description: "1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HALL_PHASE + description: Reverse phase of hall sensor + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HALL_PHASE_FORCE + description: "1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAR_NOUSE + description: sar nouse + addressOffset: 320 + size: 32 + fields: + - name: SAR_NOUSE + description: sar nouse + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SAR_IO_MUX_CONF + description: Configure and reset IO MUX + addressOffset: 324 + size: 32 + fields: + - name: IOMUX_RESET + description: Reset IO MUX by software + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: IOMUX_CLK_GATE_EN + description: IO MUX clock gate enable bit + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SARDATE + description: Version Control Register + addressOffset: 328 + size: 32 + resetValue: 26239296 + fields: + - name: SAR_DATE + description: Version Control Register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SHA + description: SHA (Secure Hash Algorithm) Accelerator + groupName: SHA + baseAddress: 1610854400 + addressBlock: + - offset: 0 + size: 240 + usage: registers + interrupt: + - name: SHA + value: 55 + registers: + - register: + name: MODE + description: Defines the algorithm of SHA accelerator + addressOffset: 0 + size: 32 + fields: + - name: MODE + description: Defines the SHA algorithm. + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: T_STRING + description: String content register for calculating initial Hash Value (only effective for SHA-512/t) + addressOffset: 4 + size: 32 + fields: + - name: T_STRING + description: Defines t_string for calculating the initial Hash value for SHA-512/t. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: T_LENGTH + description: String length register for calculating initial Hash Value (only effective for SHA-512/t) + addressOffset: 8 + size: 32 + fields: + - name: T_LENGTH + description: Defines t_length for calculating the initial Hash value for SHA-512/t. + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: DMA_BLOCK_NUM + description: Block number register (only effective for DMA-SHA) + addressOffset: 12 + size: 32 + fields: + - name: DMA_BLOCK_NUM + description: Defines the DMA-SHA block number. + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: START + description: Starts the SHA accelerator for Typical SHA operation + addressOffset: 16 + size: 32 + fields: + - name: START + description: Write 1 to start Typical SHA calculation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: CONTINUE + description: Continues SHA operation (only effective in Typical SHA mode) + addressOffset: 20 + size: 32 + fields: + - name: CONTINUE_OP + description: Write 1 to continue Typical SHA calculation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: BUSY + description: Indicates if SHA Accelerator is busy or not + addressOffset: 24 + size: 32 + fields: + - name: STATE + description: "Indicates the states of SHA accelerator.\n1'h0: idle\n1'h1: busy" + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: DMA_START + description: Starts the SHA accelerator for DMA-SHA operation + addressOffset: 28 + size: 32 + fields: + - name: DMA_START + description: Write 1 to start DMA-SHA calculation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: DMA_CONTINUE + description: Continues SHA operation (only effective in DMA-SHA mode) + addressOffset: 32 + size: 32 + fields: + - name: DMA_CONTINUE + description: Write 1 to continue DMA-SHA calculation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: INT_CLEAR + description: DMA-SHA interrupt clear register + addressOffset: 36 + size: 32 + fields: + - name: CLEAR_INTERRUPT + description: Clears DMA-SHA interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + description: DMA-SHA interrupt enable register + addressOffset: 40 + size: 32 + fields: + - name: INTERRUPT_ENA + description: Enables DMA-SHA interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 44 + size: 32 + resetValue: 538510338 + fields: + - name: DATE + description: Version control register. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + dim: 16 + dimIncrement: 4 + name: H_MEM%s + description: Hash value + addressOffset: 64 + size: 32 + fields: + - name: H + description: Stores the %sth 32-bit piece of the Hash value. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 32 + dimIncrement: 4 + name: M_MEM%s + description: Message + addressOffset: 128 + size: 32 + fields: + - name: M + description: Stores the %sth 32-bit piece of the message. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: SPI0 + description: SPI (Serial Peripheral Interface) Controller 0 + groupName: SPI + baseAddress: 1061171200 + addressBlock: + - offset: 0 + size: 264 + usage: registers + interrupt: + - name: SPI0_REJECT_CACHE + value: 83 + registers: + - register: + name: CMD + description: Command control register + addressOffset: 0 + size: 32 + fields: + - name: CONF_BITLEN + description: Define the spi_clk cycles of SPI_CONF state. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 23 + access: read-write + - name: USR + description: "User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf." + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: ADDR + description: Address value + addressOffset: 4 + size: 32 + fields: + - name: USR_ADDR_VALUE + description: "[31:8]:address to slave, [7:0]:Reserved. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CTRL + description: SPI control register + addressOffset: 8 + size: 32 + resetValue: 2883584 + fields: + - name: EXT_HOLD_EN + description: "Set the bit to hold spi. The bit is combined with SPI_USR_PREP_HOLD,SPI_USR_CMD_HOLD,SPI_USR_ADDR_HOLD,SPI_USR_DUMMY_HOLD,SPI_USR_DIN_HOLD,SPI_USR_DOUT_HOLD and SPI_USR_HOLD_POL. Can be configured in CONF state." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DUMMY_OUT + description: In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FADDR_DUAL + description: "Apply 2-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FADDR_QUAD + description: "Apply 4-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FADDR_OCT + description: "Apply 8-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FCMD_DUAL + description: "Apply 2-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FCMD_QUAD + description: "Apply 4-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FCMD_OCT + description: "Apply 8-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FREAD_DUAL + description: "In the read operations, read-data phase is in 2-bit mode. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: FREAD_QUAD + description: "In the read operations read-data phase is in 4-bit mode. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: FREAD_OCT + description: "In the read operations read-data phase is in 8-bit mode. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: Q_POL + description: "The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: D_POL + description: "The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: WP + description: "Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: RD_BIT_ORDER + description: "In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: WR_BIT_ORDER + description: "In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state." + bitOffset: 26 + bitWidth: 1 + access: read-write + - register: + name: CTRL1 + description: SPI control register 1 + addressOffset: 12 + size: 32 + resetValue: 16400 + fields: + - name: CLK_MODE + description: "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CLK_MODE_13 + description: "{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RSCK_DATA_OUT + description: "It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: W16_17_WR_ENA + description: "1:SPI_BUF16~SPI_BUF17 can be written 0:SPI_BUF16~SPI_BUF17 can not be written. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CS_HOLD_DELAY + description: SPI cs signal is delayed by spi clock cycles. Can be configured in CONF state. + bitOffset: 14 + bitWidth: 6 + access: read-write + - register: + name: CTRL2 + description: SPI control register 2 + addressOffset: 16 + size: 32 + resetValue: 8192 + fields: + - name: CS_SETUP_TIME + description: (cycles+1) of prepare phase by spi clock this bits are combined with SPI_CS_SETUP bit. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 13 + access: read-write + - name: CS_HOLD_TIME + description: delay cycles of cs pin by spi clock this bits are combined with SPI_CS_HOLD bit. Can be configured in CONF state. + bitOffset: 13 + bitWidth: 13 + access: read-write + - name: CS_DELAY_MODE + description: "spi_cs signal is delayed by spi_clk . 0: zero 1: if SPI_CK_OUT_EDGE or SPI_CK_IDLE_EDGE is set 1 delayed by half cycle else delayed by one cycle 2: if SPI_CK_OUT_EDGE or SPI_CK_IDLE_EDGE is set 1 delayed by one cycle, else delayed by half cycle 3: delayed one cycle. Can be configured in CONF state." + bitOffset: 26 + bitWidth: 3 + access: read-write + - name: CS_DELAY_NUM + description: spi_cs signal is delayed by system clock cycles. Can be configured in CONF state. + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: CLOCK + description: SPI clock control register + addressOffset: 20 + size: 32 + resetValue: 2147496003 + fields: + - name: CLKCNT_L + description: In the master mode it must be equal to SPI_CLKCNT_N. In the slave mode it must be 0. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: CLKCNT_H + description: In the master mode it must be floor((SPI_CLKCNT_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: CLKCNT_N + description: In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(SPI_CLKDIV_PRE+1)/(SPI_CLKCNT_N+1). Can be configured in CONF state. + bitOffset: 12 + bitWidth: 6 + access: read-write + - name: CLKDIV_PRE + description: In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + bitOffset: 18 + bitWidth: 13 + access: read-write + - name: CLK_EQU_SYSCLK + description: "In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USER + description: SPI USER control register + addressOffset: 24 + size: 32 + resetValue: 2147483840 + fields: + - name: DOUTDIN + description: "Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: QPI_MODE + description: "Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OPI_MODE + description: "Just for master mode. 1: spi controller is in OPI mode (all in 8-bit mode). 0: others. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TSCK_I_EDGE + description: "In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CS_HOLD + description: "spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CS_SETUP + description: "spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RSCK_I_EDGE + description: "In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CK_OUT_EDGE + description: the bit combined with SPI_DOUT_MODE register to set mosi signal delay mode. Can be configured in CONF state. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RD_BYTE_ORDER + description: "In read-data (MISO) phase 1: big-endian 0: little_endian. Can be configured in CONF state." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: WR_BYTE_ORDER + description: "In command address write-data (MOSI) phases 1: big-endian 0: litte_endian. Can be configured in CONF state." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FWRITE_DUAL + description: In the write operations read-data phase is in 2-bit mode. Can be configured in CONF state. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FWRITE_QUAD + description: In the write operations read-data phase is in 4-bit mode. Can be configured in CONF state. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FWRITE_OCT + description: In the write operations read-data phase is in 8-bit mode. Can be configured in CONF state. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: USR_CONF_NXT + description: "1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SIO + description: "Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: USR_HOLD_POL + description: "It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low. Can be configured in CONF state." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: USR_DOUT_HOLD + description: spi is hold at data out state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: USR_DIN_HOLD + description: spi is hold at data in state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: USR_DUMMY_HOLD + description: spi is hold at dummy state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: USR_ADDR_HOLD + description: spi is hold at address state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: USR_CMD_HOLD + description: spi is hold at command state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: USR_PREP_HOLD + description: spi is hold at prepare state the bit are combined with SPI_USR_HOLD_POL bit. Can be configured in CONF state. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: USR_MISO_HIGHPART + description: "read-data phase only access to high-part of the buffer SPI_BUF8~SPI_BUF17. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: USR_MOSI_HIGHPART + description: "write-data phase only access to high-part of the buffer SPI_BUF8~SPI_BUF17. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: USR_DUMMY_IDLE + description: spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: USR_MOSI + description: This bit enable the write-data phase of an operation. Can be configured in CONF state. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: USR_MISO + description: This bit enable the read-data phase of an operation. Can be configured in CONF state. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: USR_DUMMY + description: This bit enable the dummy phase of an operation. Can be configured in CONF state. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: USR_ADDR + description: This bit enable the address phase of an operation. Can be configured in CONF state. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: USR_COMMAND + description: This bit enable the command phase of an operation. Can be configured in CONF state. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USER1 + description: SPI USER control register 1 + addressOffset: 28 + size: 32 + resetValue: 3087007751 + fields: + - name: USR_DUMMY_CYCLELEN + description: The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: USR_ADDR_BITLEN + description: The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: USER2 + description: SPI USER control register 2 + addressOffset: 32 + size: 32 + resetValue: 1879048192 + fields: + - name: USR_COMMAND_VALUE + description: The value of command. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: USR_COMMAND_BITLEN + description: The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: MOSI_DLEN + description: MOSI length + addressOffset: 36 + size: 32 + fields: + - name: USR_MOSI_DBITLEN + description: The length in bits of write-data. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 0 + bitWidth: 23 + access: read-write + - register: + name: MISO_DLEN + description: MISO length + addressOffset: 40 + size: 32 + fields: + - name: USR_MISO_DBITLEN + description: The length in bits of read-data. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 0 + bitWidth: 23 + access: read-write + - register: + name: MISC + description: SPI misc register + addressOffset: 44 + size: 32 + resetValue: 62 + fields: + - name: CS0_DIS + description: "SPI CS0 pin enable, 1: disable CS0, 0: SPI_CS0 signal is from/to CS0 pin. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CS1_DIS + description: "SPI CS1 pin enable, 1: disable CS1, 0: SPI_CS1 signal is from/to CS1 pin. Can be configured in CONF state." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CS2_DIS + description: "SPI CS2 pin enable, 1: disable CS2, 0: SPI_CS2 signal is from/to CS2 pin. Can be configured in CONF state." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CS3_DIS + description: "SPI CS3 pin enable, 1: disable CS3, 0: SPI_CS3 signal is from/to CS3 pin. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CS4_DIS + description: "SPI CS4 pin enable, 1: disable CS4, 0: SPI_CS4 signal is from/to CS4 pin. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CS5_DIS + description: "SPI CS5 pin enable, 1: disable CS5, 0: SPI_CS5 signal is from/to CS5 pin. Can be configured in CONF state." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CK_DIS + description: "1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: MASTER_CS_POL + description: "In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ SPI_MASTER_CS_POL. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: CLK_DATA_DTR_EN + description: "1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DATA_DTR_EN + description: "1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: ADDR_DTR_EN + description: "1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: CMD_DTR_EN + description: "1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: CD_DATA_SET + description: "1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST[3:0] is in SPI_DOUT or SPI_DIN state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CD_DUMMY_SET + description: "1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST[3:0] is in SPI_DUMMY state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CD_ADDR_SET + description: "1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST[3:0] is in SPI_SEND_ADDR state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SLAVE_CS_POL + description: "spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: DQS_IDLE_EDGE + description: The default value of spi_dqs. Can be configured in CONF state. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: CD_CMD_SET + description: "1: spi_cd = !SPI_CD_IDLE_EDGE when SPI_ST[3:0] is in SPI_SEND_CMD state. 0: spi_cd = SPI_CD_IDLE_EDGE. Can be configured in CONF state." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: CD_IDLE_EDGE + description: The default value of spi_cd. Can be configured in CONF state. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CK_IDLE_EDGE + description: "1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CS_KEEP_ACTIVE + description: spi cs line keep low when the bit is set. Can be configured in CONF state. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: QUAD_DIN_PIN_SWAP + description: "1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SLAVE + description: SPI slave control register + addressOffset: 48 + size: 32 + resetValue: 512 + fields: + - name: TRANS_DONE + description: The interrupt raw bit for the completion of any operation in both the master mode and the slave mode. Can not be changed by CONF_buf. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: INT_RD_BUF_DONE_EN + description: "SPI_SLV_RD_BUF_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: INT_WR_BUF_DONE_EN + description: "SPI_SLV_WR_BUF_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: INT_RD_DMA_DONE_EN + description: "SPI_SLV_RD_DMA_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: INT_WR_DMA_DONE_EN + description: "SPI_SLV_WR_DMA_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: INT_TRANS_DONE_EN + description: "SPI_TRANS_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: INT_DMA_SEG_TRANS_EN + description: "SPI_DMA_SEG_TRANS_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SEG_MAGIC_ERR_INT_EN + description: "1: Enable seg magic value error interrupt. 0: Others. Can be configured in CONF state." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TRANS_CNT + description: The operations counter in both the master mode and the slave mode. + bitOffset: 23 + bitWidth: 4 + access: read-only + - name: TRANS_DONE_AUTO_CLR_EN + description: "SPI_TRANS_DONE auto clear enable, clear it 3 apb cycles after the pos edge of SPI_TRANS_DONE. 0:disable. 1: enable. Can be configured in CONF state." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: MODE + description: "Set SPI work mode. 1: slave mode 0: master mode." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SOFT_RESET + description: "Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SLAVE1 + description: SPI slave control register 1 + addressOffset: 52 + size: 32 + fields: + - name: SLV_ADDR_ERR_CLR + description: "1: Clear SPI_SLV_ADDR_ERR. 0: not valid. Can be changed by CONF_buf." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLV_CMD_ERR_CLR + description: "1: Clear SPI_SLV_CMD_ERR. 0: not valid. Can be changed by CONF_buf." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SLV_NO_QPI_EN + description: "1: spi slave QPI mode is not supported. 0: spi slave QPI mode is supported." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SLV_ADDR_ERR + description: "1: The address value of the last SPI transfer is not supported by SPI slave. 0: The address value is supported or no address value is received." + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SLV_CMD_ERR + description: "1: The command value of the last SPI transfer is not supported by SPI slave. 0: The command value is supported or no command value is received." + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SLV_WR_DMA_DONE + description: The interrupt raw bit for the completion of dma write operation in the slave mode. Can not be changed by CONF_buf. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLV_LAST_COMMAND + description: In the slave mode it is the value of command. + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SLV_LAST_ADDR + description: In the slave mode it is the value of address. + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: SLV_WRBUF_DLEN + description: SPI slave Wr_BUF interrupt and CONF control register + addressOffset: 56 + size: 32 + resetValue: 3623878656 + fields: + - name: SLV_WR_BUF_DONE + description: The interrupt raw bit for the completion of write-buffer operation in the slave mode. Can not be changed by CONF_buf. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: CONF_BASE_BITLEN + description: "The basic spi_clk cycles of CONF state. The real cycle length of CONF state, if SPI_USR_CONF is enabled, is SPI_CONF_BASE_BITLEN[6:0] + SPI_CONF_BITLEN[23:0]." + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: SLV_RDBUF_DLEN + description: SPI magic error and slave control register + addressOffset: 60 + size: 32 + fields: + - name: SLV_DMA_RD_BYTELEN + description: In the slave mode it is the length in bytes for read operations. The register value shall be byte_num. + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: SLV_RD_BUF_DONE + description: The interrupt raw bit for the completion of read-buffer operation in the slave mode. Can not be changed by CONF_buf. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SEG_MAGIC_ERR + description: "1: The recent magic value in CONF buffer is not right in master DMA seg-trans mode. 0: others." + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: SLV_RD_BYTE + description: SPI interrupt control register + addressOffset: 64 + size: 32 + resetValue: 167772160 + fields: + - name: SLV_DATA_BYTELEN + description: "The full-duplex or half-duplex data byte length of the last SPI transfer in slave mode. In half-duplex mode, this value is controlled by bits [23:20]." + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: SLV_RDDMA_BYTELEN_EN + description: "1: SPI_SLV_DATA_BYTELEN stores data byte length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others" + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SLV_WRDMA_BYTELEN_EN + description: "1: SPI_SLV_DATA_BYTELEN stores data byte length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SLV_RDBUF_BYTELEN_EN + description: "1: SPI_SLV_DATA_BYTELEN stores data byte length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SLV_WRBUF_BYTELEN_EN + description: "1: SPI_SLV_DATA_BYTELEN stores data byte length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: DMA_SEG_MAGIC_VALUE + description: The magic value of BM table in master DMA seg-trans. + bitOffset: 24 + bitWidth: 4 + access: read-write + - name: SLV_RD_DMA_DONE + description: The interrupt raw bit for the completion of Rd-DMA operation in the slave mode. Can not be changed by CONF_buf. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: USR_CONF + description: "1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: FSM + description: SPI master status and DMA read byte control register + addressOffset: 68 + size: 32 + fields: + - name: ST + description: "The status of spi state machine. 0: idle state, 1: preparation state, 2: send command state, 3: send data state, 4: red data state, 5:write data state, 6: wait state, 7: done state." + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: MST_DMA_RD_BYTELEN + description: Define the master DMA read byte length in non seg-conf-trans or seg-conf-trans mode. Invalid when SPI_RX_EOF_EN is 0. Can be configured in CONF state.. + bitOffset: 12 + bitWidth: 20 + access: read-write + - register: + name: HOLD + description: SPI hold register + addressOffset: 72 + size: 32 + fields: + - name: INT_HOLD_ENA + description: "This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set, if the other SPI is busy, the SPI will be hold. 1(3): hold at idle phase 2: hold at prepare phase. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: VAL + description: "spi hold output value, which should be used with SPI_HOLD_OUT_EN. Can be configured in CONF state." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_EN + description: Enable set spi output hold value to spi_hold_reg. It can be used to hold spi state machine with SPI_EXT_HOLD_EN and other usr hold signals. Can be configured in CONF state. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUT_TIME + description: set the hold cycles of output spi_hold signal when SPI_HOLD_OUT_EN is enable. Can be configured in CONF state. + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: DMA_SEG_TRANS_DONE + description: "1: spi master DMA full-duplex/half-duplex seg-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-trans is not ended or not occurred. Can not be changed by CONF_buf." + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: DMA_CONF + description: SPI DMA control register + addressOffset: 76 + size: 32 + resetValue: 512 + fields: + - name: IN_RST + description: The bit is used to reset in dma fsm and in data fifo pointer. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_RST + description: The bit is used to reset out dma fsm and out data fifo pointer. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: AHBM_FIFO_RST + description: Reset spi dma ahb master fifo pointer. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: AHBM_RST + description: Reset spi dma ahb master. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: IN_LOOP_TEST + description: Set bit to test in link. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUT_LOOP_TEST + description: Set bit to test out link. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_AUTO_WRBACK + description: "when the bit is set, DMA continue to use the next inlink node when the length of inlink is 0." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: OUT_EOF_MODE + description: "out eof flag generation mode . 1: when dma pop all data from fifo 0:when ahb push all data to fifo." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OUTDSCR_BURST_EN + description: read descriptor use burst mode when read data for memory. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: INDSCR_BURST_EN + description: read descriptor use burst mode when write data to memory. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: OUT_DATA_BURST_EN + description: spi dma read data from memory in burst mode. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: MEM_TRANS_EN + description: "1: Internal memory data transfer enable bit. Send SPI DMA RX buffer data to SPI DMA TX buffer. 0: Disable this function." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DMA_RX_STOP + description: spi dma read data stop when in continue tx/rx mode. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DMA_TX_STOP + description: spi dma write data stop when in continue tx/rx mode. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DMA_CONTINUE + description: spi dma continue tx/rx data. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SLV_LAST_SEG_POP_CLR + description: "1: Clear spi_slv_seg_frt_pop_mask. 0 : others" + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: DMA_SLV_SEG_TRANS_EN + description: "Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SLV_RX_SEG_TRANS_CLR_EN + description: "1: spi_dma_infifo_full_vld is cleared by spi slave CMD5. 0: spi_dma_infifo_full_vld is cleared by SPI_TRANS_DONE." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SLV_TX_SEG_TRANS_CLR_EN + description: "1: spi_dma_outfifo_empty_vld is cleared by spi slave CMD6. 0: spi_dma_outfifo_empty_vld is cleared by SPI_TRANS_DONE." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: RX_EOF_EN + description: "1: SPI_IN_SUC_EOF_INT_RAW is set when the number of dma pushed data bytes is equal to the value of SPI_SLV_DMA_RD_BYTELEN[19:0]/ SPI_MST_DMA_RD_BYTELEN[19:0] in spi dma transition. 0: SPI_IN_SUC_EOF_INT_RAW is set by SPI_TRANS_DONE in non-seg-trans or SPI_DMA_SEG_TRANS_DONE in seg-trans." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: DMA_INFIFO_FULL_CLR + description: "1:Clear spi_dma_infifo_full_vld. 0: Do not control it." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: DMA_OUTFIFO_EMPTY_CLR + description: "1:Clear spi_dma_outfifo_empty_vld. 0: Do not control it." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: EXT_MEM_BK_SIZE + description: Select the external memory block size. + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: DMA_SEG_TRANS_CLR + description: "1: End slave seg-trans, which acts as 0x05 command. 2 or more end seg-trans signals will induce error in DMA RX. 0: others. Will be cleared in 1 APB CLK cycles by hardware.." + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: DMA_OUT_LINK + description: SPI DMA TX link configuration + addressOffset: 80 + size: 32 + fields: + - name: OUTLINK_ADDR + description: The address of the first outlink descriptor. + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: OUTLINK_STOP + description: Set the bit to stop to use outlink descriptor. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: OUTLINK_START + description: Set the bit to start to use outlink descriptor. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: OUTLINK_RESTART + description: Set the bit to mount on new outlink descriptors. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DMA_TX_ENA + description: spi dma write data status bit. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DMA_IN_LINK + description: SPI DMA RX link configuration + addressOffset: 84 + size: 32 + fields: + - name: INLINK_ADDR + description: The address of the first inlink descriptor. + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: INLINK_AUTO_RET + description: "when the bit is set, the inlink descriptor returns to the first link node when a packet is error." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: INLINK_STOP + description: Set the bit to stop to use inlink descriptor. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: INLINK_START + description: Set the bit to start to use inlink descriptor. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: INLINK_RESTART + description: Set the bit to mount on new inlink descriptors. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DMA_RX_ENA + description: SPI DMA read data status bit. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DMA_INT_ENA + description: SPI DMA interrupt enable register + addressOffset: 88 + size: 32 + fields: + - name: INLINK_DSCR_EMPTY_INT_ENA + description: The enable bit for lack of enough inlink descriptors. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUTLINK_DSCR_ERROR_INT_ENA + description: The enable bit for outlink descriptor error. Can be configured in CONF state. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: INLINK_DSCR_ERROR_INT_ENA + description: The enable bit for inlink descriptor error. Can be configured in CONF state. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DONE_INT_ENA + description: The enable bit for completing usage of a inlink descriptor. Can be configured in CONF state. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF_INT_ENA + description: The enable bit for receiving error. Can be configured in CONF state. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF_INT_ENA + description: The enable bit for completing receiving all the packets from host. Can be configured in CONF state. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUT_DONE_INT_ENA + description: The enable bit for completing usage of a outlink descriptor . Can be configured in CONF state. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUT_EOF_INT_ENA + description: The enable bit for sending a packet to host done. Can be configured in CONF state. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF_INT_ENA + description: The enable bit for sending all the packets to host done. Can be configured in CONF state. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: INFIFO_FULL_ERR_INT_ENA + description: The enable bit for infifo full error interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OUTFIFO_EMPTY_ERR_INT_ENA + description: The enable bit for outfifo empty error interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLV_CMD6_INT_ENA + description: The enable bit for SPI slave CMD6 interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SLV_CMD7_INT_ENA + description: The enable bit for SPI slave CMD7 interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SLV_CMD8_INT_ENA + description: The enable bit for SPI slave CMD8 interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLV_CMD9_INT_ENA + description: The enable bit for SPI slave CMD9 interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLV_CMDA_INT_ENA + description: The enable bit for SPI slave CMDA interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: DMA_INT_RAW + description: SPI DMA interrupt raw register + addressOffset: 92 + size: 32 + fields: + - name: INLINK_DSCR_EMPTY_INT_RAW + description: The raw bit for lack of enough inlink descriptors. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUTLINK_DSCR_ERROR_INT_RAW + description: The raw bit for outlink descriptor error. Can be configured in CONF state. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: INLINK_DSCR_ERROR_INT_RAW + description: The raw bit for inlink descriptor error. Can be configured in CONF state. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: IN_DONE_INT_RAW + description: The raw bit for completing usage of a inlink descriptor. Can be configured in CONF state. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: IN_ERR_EOF_INT_RAW + description: The raw bit for receiving error. Can be configured in CONF state. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: IN_SUC_EOF_INT_RAW + description: The raw bit for completing receiving all the packets from host. Can be configured in CONF state. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OUT_DONE_INT_RAW + description: The raw bit for completing usage of a outlink descriptor. Can be configured in CONF state. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUT_EOF_INT_RAW + description: The raw bit for sending a packet to host done. Can be configured in CONF state. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OUT_TOTAL_EOF_INT_RAW + description: The raw bit for sending all the packets to host done. Can be configured in CONF state. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: INFIFO_FULL_ERR_INT_RAW + description: "1:SPI_DMA_INFIFO_FULL and spi_push_data_prep are valid, which means that DMA Rx buffer is full but push is valid. 0: Others. Can not be changed by CONF_buf." + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY_ERR_INT_RAW + description: "1:SPI_DMA_OUTFIFO_EMPTY and spi_pop_data_prep are valid, which means that there is no data to pop but pop is valid. 0: Others. Can not be changed by CONF_buf." + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SLV_CMD6_INT_RAW + description: The raw bit for SPI slave CMD6 interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SLV_CMD7_INT_RAW + description: The raw bit for SPI slave CMD7 interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SLV_CMD8_INT_RAW + description: The raw bit for SPI slave CMD8 interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLV_CMD9_INT_RAW + description: The raw bit for SPI slave CMD9 interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLV_CMDA_INT_RAW + description: The raw bit for SPI slave CMDA interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: DMA_INT_ST + description: SPI DMA interrupt status register + addressOffset: 96 + size: 32 + fields: + - name: INLINK_DSCR_EMPTY_INT_ST + description: The status bit for lack of enough inlink descriptors. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUTLINK_DSCR_ERROR_INT_ST + description: The status bit for outlink descriptor error. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: INLINK_DSCR_ERROR_INT_ST + description: The status bit for inlink descriptor error. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: IN_DONE_INT_ST + description: The status bit for completing usage of a inlink descriptor. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: IN_ERR_EOF_INT_ST + description: The status bit for receiving error. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: IN_SUC_EOF_INT_ST + description: The status bit for completing receiving all the packets from host. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OUT_DONE_INT_ST + description: The status bit for completing usage of a outlink descriptor. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUT_EOF_INT_ST + description: The status bit for sending a packet to host done. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OUT_TOTAL_EOF_INT_ST + description: The status bit for sending all the packets to host done. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: INFIFO_FULL_ERR_INT_ST + description: The status bit for infifo full error. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY_ERR_INT_ST + description: The status bit for outfifo empty error. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SLV_CMD6_INT_ST + description: The status bit for SPI slave CMD6 interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SLV_CMD7_INT_ST + description: The status bit for SPI slave CMD7 interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SLV_CMD8_INT_ST + description: The status bit for SPI slave CMD8 interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLV_CMD9_INT_ST + description: The status bit for SPI slave CMD9 interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLV_CMDA_INT_ST + description: The status bit for SPI slave CMDA interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: DMA_INT_CLR + description: SPI DMA interrupt clear register + addressOffset: 100 + size: 32 + fields: + - name: INLINK_DSCR_EMPTY_INT_CLR + description: The clear bit for lack of enough inlink descriptors. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUTLINK_DSCR_ERROR_INT_CLR + description: The clear bit for outlink descriptor error. Can be configured in CONF state. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: INLINK_DSCR_ERROR_INT_CLR + description: The clear bit for inlink descriptor error. Can be configured in CONF state. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DONE_INT_CLR + description: The clear bit for completing usage of a inlink descriptor. Can be configured in CONF state. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF_INT_CLR + description: The clear bit for receiving error. Can be configured in CONF state. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF_INT_CLR + description: The clear bit for completing receiving all the packets from host. Can be configured in CONF state. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUT_DONE_INT_CLR + description: The clear bit for completing usage of a outlink descriptor. Can be configured in CONF state. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUT_EOF_INT_CLR + description: The clear bit for sending a packet to host done. Can be configured in CONF state. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF_INT_CLR + description: The clear bit for sending all the packets to host done. Can be configured in CONF state. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: INFIFO_FULL_ERR_INT_CLR + description: "1: Clear SPI_INFIFO_FULL_ERR_INT_RAW. 0: not valid. Can be changed by CONF_buf." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OUTFIFO_EMPTY_ERR_INT_CLR + description: "1: Clear SPI_OUTFIFO_EMPTY_ERR_INT_RAW signal. 0: not valid. Can be changed by CONF_buf." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLV_CMD6_INT_CLR + description: The clear bit for SPI slave CMD6 interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SLV_CMD7_INT_CLR + description: The clear bit for SPI slave CMD7 interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SLV_CMD8_INT_CLR + description: The clear bit for SPI slave CMD8 interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLV_CMD9_INT_CLR + description: The clear bit for SPI slave CMD9 interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLV_CMDA_INT_CLR + description: The clear bit for SPI slave CMDA interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: IN_ERR_EOF_DES_ADDR + description: The latest SPI DMA RX descriptor address receiving error + addressOffset: 104 + size: 32 + fields: + - name: DMA_IN_ERR_EOF_DES_ADDR + description: The inlink descriptor address when spi dma produce receiving error. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_SUC_EOF_DES_ADDR + description: The latest SPI DMA eof RX descriptor address + addressOffset: 108 + size: 32 + fields: + - name: DMA_IN_SUC_EOF_DES_ADDR + description: The last inlink descriptor address when spi dma produce from_suc_eof. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INLINK_DSCR + description: Current SPI DMA RX descriptor pointer + addressOffset: 112 + size: 32 + fields: + - name: DMA_INLINK_DSCR + description: The content of current in descriptor pointer. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INLINK_DSCR_BF0 + description: Next SPI DMA RX descriptor pointer + addressOffset: 116 + size: 32 + fields: + - name: DMA_INLINK_DSCR_BF0 + description: The content of next in descriptor pointer. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INLINK_DSCR_BF1 + description: Current SPI DMA RX buffer pointer + addressOffset: 120 + size: 32 + fields: + - name: DMA_INLINK_DSCR_BF1 + description: The content of current in descriptor data buffer pointer. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_EOF_BFR_DES_ADDR + description: The latest SPI DMA eof TX buffer address + addressOffset: 124 + size: 32 + fields: + - name: DMA_OUT_EOF_BFR_DES_ADDR + description: The address of buffer relative to the outlink descriptor that produce eof. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_EOF_DES_ADDR + description: The latest SPI DMA eof TX descriptor address + addressOffset: 128 + size: 32 + fields: + - name: DMA_OUT_EOF_DES_ADDR + description: The last outlink descriptor address when spi dma produce to_eof. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUTLINK_DSCR + description: Current SPI DMA TX descriptor pointer + addressOffset: 132 + size: 32 + fields: + - name: DMA_OUTLINK_DSCR + description: The content of current out descriptor pointer. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUTLINK_DSCR_BF0 + description: Next SPI DMA TX descriptor pointer + addressOffset: 136 + size: 32 + fields: + - name: DMA_OUTLINK_DSCR_BF0 + description: The content of next out descriptor pointer. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUTLINK_DSCR_BF1 + description: Current SPI DMA TX buffer pointer + addressOffset: 140 + size: 32 + fields: + - name: DMA_OUTLINK_DSCR_BF1 + description: The content of current out descriptor data buffer pointer. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DMA_OUTSTATUS + description: SPI DMA TX status + addressOffset: 144 + size: 32 + resetValue: 2147483648 + fields: + - name: DMA_OUTDSCR_ADDR + description: SPI dma out descriptor address. + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: DMA_OUTDSCR_STATE + description: SPI dma out descriptor state. + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: DMA_OUT_STATE + description: SPI dma out data state. + bitOffset: 20 + bitWidth: 3 + access: read-only + - name: DMA_OUTFIFO_CNT + description: The remains of SPI dma outfifo data. + bitOffset: 23 + bitWidth: 7 + access: read-only + - name: DMA_OUTFIFO_FULL + description: SPI dma outfifo is full. + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: DMA_OUTFIFO_EMPTY + description: SPI dma outfifo is empty. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: DMA_INSTATUS + description: SPI DMA RX status + addressOffset: 148 + size: 32 + resetValue: 2147483648 + fields: + - name: DMA_INDSCR_ADDR + description: SPI dma in descriptor address. + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: DMA_INDSCR_STATE + description: SPI dma in descriptor state. + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: DMA_IN_STATE + description: SPI dma in data state. + bitOffset: 20 + bitWidth: 3 + access: read-only + - name: DMA_INFIFO_CNT + description: The remains of SPI dma infifo data. + bitOffset: 23 + bitWidth: 7 + access: read-only + - name: DMA_INFIFO_FULL + description: SPI dma infifo is full. + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: DMA_INFIFO_EMPTY + description: SPI dma infifo is empty. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: W0 + description: Data buffer 0 + addressOffset: 152 + size: 32 + fields: + - name: BUF0 + description: "32 bits data buffer 0, transferred in the unit of byte. Byte addressable in slave half-duplex mode." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W1 + description: Data buffer 1 + addressOffset: 156 + size: 32 + fields: + - name: BUF1 + description: "32 bits data buffer 1, transferred in the unit of byte. Byte addressable in slave half-duplex mode." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W2 + description: Data buffer 2 + addressOffset: 160 + size: 32 + fields: + - name: BUF2 + description: "32 bits data buffer 2, transferred in the unit of byte. Byte addressable in slave half-duplex mode." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W3 + description: Data buffer 3 + addressOffset: 164 + size: 32 + fields: + - name: BUF3 + description: "32 bits data buffer 3, transferred in the unit of byte. Byte addressable in slave half-duplex mode." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W4 + description: Data buffer 4 + addressOffset: 168 + size: 32 + fields: + - name: BUF4 + description: "32 bits data buffer 4, transferred in the unit of byte. Byte addressable in slave half-duplex mode." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W5 + description: Data buffer 5 + addressOffset: 172 + size: 32 + fields: + - name: BUF5 + description: "32 bits data buffer 5, transferred in the unit of byte. Byte addressable in slave half-duplex mode." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W6 + description: Data buffer 6 + addressOffset: 176 + size: 32 + fields: + - name: BUF6 + description: "32 bits data buffer 6, transferred in the unit of byte. Byte addressable in slave half-duplex mode." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W7 + description: Data buffer 7 + addressOffset: 180 + size: 32 + fields: + - name: BUF7 + description: "32 bits data buffer 7, transferred in the unit of byte. Byte addressable in slave half-duplex mode." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W8 + description: Data buffer 8 + addressOffset: 184 + size: 32 + fields: + - name: BUF8 + description: "32 bits data buffer 8, transferred in the unit of byte. Byte addressable in slave half-duplex mode." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W9 + description: Data buffer 9 + addressOffset: 188 + size: 32 + fields: + - name: BUF9 + description: "32 bits data buffer 9, transferred in the unit of byte. Byte addressable in slave half-duplex mode." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W10 + description: Data buffer 10 + addressOffset: 192 + size: 32 + fields: + - name: BUF10 + description: "32 bits data buffer 10, transferred in the unit of byte. Byte addressable in slave half-duplex mode." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W11 + description: Data buffer 11 + addressOffset: 196 + size: 32 + fields: + - name: BUF11 + description: "32 bits data buffer 11, transferred in the unit of byte. Byte addressable in slave half-duplex mode." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W12 + description: Data buffer 12 + addressOffset: 200 + size: 32 + fields: + - name: BUF12 + description: "32 bits data buffer 12, transferred in the unit of byte. Byte addressable in slave half-duplex mode." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W13 + description: Data buffer 13 + addressOffset: 204 + size: 32 + fields: + - name: BUF13 + description: "32 bits data buffer 13, transferred in the unit of byte. Byte addressable in slave half-duplex mode." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W14 + description: Data buffer 14 + addressOffset: 208 + size: 32 + fields: + - name: BUF14 + description: "32 bits data buffer 14, transferred in the unit of byte. Byte addressable in slave half-duplex mode." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W15 + description: Data buffer 15 + addressOffset: 212 + size: 32 + fields: + - name: BUF15 + description: "32 bits data buffer 15, transferred in the unit of byte. Byte addressable in slave half-duplex mode." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W16 + description: Data buffer 16 + addressOffset: 216 + size: 32 + fields: + - name: BUF16 + description: "32 bits data buffer 16, transferred in the unit of byte. Byte addressable in slave half-duplex mode." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W17 + description: Data buffer 17 + addressOffset: 220 + size: 32 + fields: + - name: BUF17 + description: "32 bits data buffer 17, transferred in the unit of byte. Byte addressable in slave half-duplex mode." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DIN_MODE + description: SPI input delay mode configuration + addressOffset: 224 + size: 32 + fields: + - name: DIN0_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: DIN1_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: DIN2_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: DIN3_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: DIN4_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: DIN5_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: DIN6_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: DIN7_MODE + description: "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 21 + bitWidth: 3 + access: read-write + - name: TIMING_CLK_ENA + description: "1:enable hclk in spi_timing.v. 0: disable it. Can be configured in CONF state." + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: DIN_NUM + description: SPI input delay number configuration + addressOffset: 228 + size: 32 + fields: + - name: DIN0_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DIN1_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DIN2_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DIN3_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DIN4_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: DIN5_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DIN6_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DIN7_NUM + description: "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: DOUT_MODE + description: SPI output delay mode configuration + addressOffset: 232 + size: 32 + fields: + - name: DOUT0_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: DOUT1_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: DOUT2_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: DOUT3_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state." + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: DOUT4_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: DOUT5_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state." + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: DOUT6_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state." + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: DOUT7_MODE + description: "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state." + bitOffset: 21 + bitWidth: 3 + access: read-write + - register: + name: DOUT_NUM + description: SPI output delay number configuration + addressOffset: 236 + size: 32 + fields: + - name: DOUT0_NUM + description: "the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DOUT1_NUM + description: "the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DOUT2_NUM + description: "the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DOUT3_NUM + description: "the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DOUT4_NUM + description: "the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: DOUT5_NUM + description: "the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DOUT6_NUM + description: "the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DOUT7_NUM + description: "the output signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: LCD_CTRL + description: LCD frame control register + addressOffset: 240 + size: 32 + fields: + - name: LCD_HB_FRONT + description: It is the horizontal blank front porch of a frame. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: LCD_VA_HEIGHT + description: It is the vertical active height of a frame. Can be configured in CONF state. + bitOffset: 11 + bitWidth: 10 + access: read-write + - name: LCD_VT_HEIGHT + description: It is the vertical total height of a frame. Can be configured in CONF state. + bitOffset: 21 + bitWidth: 10 + access: read-write + - name: LCD_MODE_EN + description: "1: Enable LCD mode output vsync, hsync, de. 0: Disable. Can be configured in CONF state." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LCD_CTRL1 + description: LCD frame control1 register + addressOffset: 244 + size: 32 + fields: + - name: LCD_VB_FRONT + description: It is the vertical blank front porch of a frame. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: LCD_HA_WIDTH + description: It is the horizontal active width of a frame. Can be configured in CONF state. + bitOffset: 8 + bitWidth: 12 + access: read-write + - name: LCD_HT_WIDTH + description: It is the horizontal total width of a frame. Can be configured in CONF state. + bitOffset: 20 + bitWidth: 12 + access: read-write + - register: + name: LCD_CTRL2 + description: LCD frame control2 register + addressOffset: 248 + size: 32 + resetValue: 65537 + fields: + - name: LCD_VSYNC_WIDTH + description: It is the position of spi_vsync active pulse in a line. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: VSYNC_IDLE_POL + description: It is the idle value of spi_vsync. Can be configured in CONF state. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: LCD_HSYNC_WIDTH + description: It is the position of spi_hsync active pulse in a line. Can be configured in CONF state. + bitOffset: 16 + bitWidth: 7 + access: read-write + - name: HSYNC_IDLE_POL + description: It is the idle value of spi_hsync. Can be configured in CONF state. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: LCD_HSYNC_POSITION + description: It is the position of spi_hsync active pulse in a line. Can be configured in CONF state. + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: LCD_D_MODE + description: LCD delay number + addressOffset: 252 + size: 32 + fields: + - name: D_DQS_MODE + description: "the output spi_dqs is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: D_CD_MODE + description: "the output spi_cd is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: D_DE_MODE + description: "the output spi_de is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: D_HSYNC_MODE + description: "the output spi_hsync is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state." + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: D_VSYNC_MODE + description: "the output spi_vsync is delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the spi_clk. Can be configured in CONF state." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: DE_IDLE_POL + description: It is the idle value of spi_de. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: HS_BLANK_EN + description: "1: The pulse of spi_hsync is out in vertical blanking lines in seg-trans or one trans. 0: spi_hsync pulse is valid only in active region lines in seg-trans." + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: LCD_D_NUM + description: LCD delay mode + addressOffset: 256 + size: 32 + fields: + - name: D_DQS_NUM + description: "the output spi_dqs is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: D_CD_NUM + description: "the output spi_cd is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: D_DE_NUM + description: "the output spi_de is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: D_HSYNC_NUM + description: "the output spi_hsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: D_VSYNC_NUM + description: "the output spi_vsync is delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 8 + bitWidth: 2 + access: read-write + - register: + name: REG_DATE + description: SPI version control + addressOffset: 1020 + size: 32 + resetValue: 26243648 + fields: + - name: DATE + description: SPI register version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SPI1 + description: SPI (Serial Peripheral Interface) Controller 1 + baseAddress: 1061167104 + interrupt: + - name: SPI1 + value: 32 + derivedFrom: SPI0 + - name: SPI2 + description: SPI (Serial Peripheral Interface) Controller 2 + baseAddress: 1061306368 + interrupt: + - name: SPI2 + value: 33 + - name: SPI2_DMA + value: 57 + derivedFrom: SPI0 + - name: SPI3 + description: SPI (Serial Peripheral Interface) Controller 3 + baseAddress: 1061310464 + interrupt: + - name: SPI3 + value: 34 + - name: SPI3_DMA + value: 58 + derivedFrom: SPI0 + - name: SPI4 + description: SPI (Serial Peripheral Interface) Controller 4 + baseAddress: 1061384192 + interrupt: + - name: SPI4_DMA + value: 85 + - name: SPI4 + value: 86 + derivedFrom: SPI0 + - name: SYSCON + description: SYSCON Peripheral + groupName: SYSCON + baseAddress: 1061314560 + addressBlock: + - offset: 0 + size: 160 + usage: registers + registers: + - register: + name: SYSCLK_CONF + addressOffset: 0 + size: 32 + fields: + - name: CLK_320M_EN + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CLK_EN + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RST_TICK_CNT + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: TICK_CONF + addressOffset: 4 + size: 32 + resetValue: 67367 + fields: + - name: XTAL_TICK_NUM + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CK8M_TICK_NUM + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: TICK_ENABLE + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: CLK_OUT_EN + addressOffset: 8 + size: 32 + resetValue: 2047 + fields: + - name: CLK20_OEN + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CLK22_OEN + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CLK44_OEN + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CLK_BB_OEN + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CLK80_OEN + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CLK160_OEN + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CLK_320M_OEN + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CLK_ADC_INF_OEN + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_DAC_CPU_OEN + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CLK40X_BB_OEN + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CLK_XTAL_OEN + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: HOST_INF_SEL + addressOffset: 12 + size: 32 + fields: + - name: PERI_IO_SWAP + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: EXT_MEM_PMS_LOCK + addressOffset: 16 + size: 32 + fields: + - name: EXT_MEM_PMS_LOCK + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: FLASH_ACE0_ATTR + addressOffset: 20 + size: 32 + resetValue: 7 + fields: + - name: FLASH_ACE0_ATTR + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: FLASH_ACE1_ATTR + addressOffset: 24 + size: 32 + resetValue: 7 + fields: + - name: FLASH_ACE1_ATTR + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: FLASH_ACE2_ATTR + addressOffset: 28 + size: 32 + resetValue: 7 + fields: + - name: FLASH_ACE2_ATTR + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: FLASH_ACE3_ATTR + addressOffset: 32 + size: 32 + resetValue: 7 + fields: + - name: FLASH_ACE3_ATTR + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: FLASH_ACE0_ADDR + addressOffset: 36 + size: 32 + fields: + - name: S + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FLASH_ACE1_ADDR + addressOffset: 40 + size: 32 + resetValue: 268435456 + fields: + - name: S + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FLASH_ACE2_ADDR + addressOffset: 44 + size: 32 + resetValue: 536870912 + fields: + - name: S + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FLASH_ACE3_ADDR + addressOffset: 48 + size: 32 + resetValue: 805306368 + fields: + - name: S + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FLASH_ACE0_SIZE + addressOffset: 52 + size: 32 + resetValue: 4096 + fields: + - name: FLASH_ACE0_SIZE + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: FLASH_ACE1_SIZE + addressOffset: 56 + size: 32 + resetValue: 4096 + fields: + - name: FLASH_ACE1_SIZE + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: FLASH_ACE2_SIZE + addressOffset: 60 + size: 32 + resetValue: 4096 + fields: + - name: FLASH_ACE2_SIZE + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: FLASH_ACE3_SIZE + addressOffset: 64 + size: 32 + resetValue: 4096 + fields: + - name: FLASH_ACE3_SIZE + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: SRAM_ACE0_ATTR + addressOffset: 68 + size: 32 + resetValue: 7 + fields: + - name: SRAM_ACE0_ATTR + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: SRAM_ACE1_ATTR + addressOffset: 72 + size: 32 + resetValue: 7 + fields: + - name: SRAM_ACE1_ATTR + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: SRAM_ACE2_ATTR + addressOffset: 76 + size: 32 + resetValue: 7 + fields: + - name: SRAM_ACE2_ATTR + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: SRAM_ACE3_ATTR + addressOffset: 80 + size: 32 + resetValue: 7 + fields: + - name: SRAM_ACE3_ATTR + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: SRAM_ACE0_ADDR + addressOffset: 84 + size: 32 + fields: + - name: S + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SRAM_ACE1_ADDR + addressOffset: 88 + size: 32 + resetValue: 268435456 + fields: + - name: S + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SRAM_ACE2_ADDR + addressOffset: 92 + size: 32 + resetValue: 536870912 + fields: + - name: S + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SRAM_ACE3_ADDR + addressOffset: 96 + size: 32 + resetValue: 805306368 + fields: + - name: S + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SRAM_ACE0_SIZE + addressOffset: 100 + size: 32 + resetValue: 4096 + fields: + - name: SRAM_ACE0_SIZE + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: SRAM_ACE1_SIZE + addressOffset: 104 + size: 32 + resetValue: 4096 + fields: + - name: SRAM_ACE1_SIZE + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: SRAM_ACE2_SIZE + addressOffset: 108 + size: 32 + resetValue: 4096 + fields: + - name: SRAM_ACE2_SIZE + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: SRAM_ACE3_SIZE + addressOffset: 112 + size: 32 + resetValue: 4096 + fields: + - name: SRAM_ACE3_SIZE + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: SPI_MEM_PMS_CTRL + addressOffset: 116 + size: 32 + fields: + - name: SPI_MEM_REJECT_INT + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_MEM_REJECT_CLR + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SPI_MEM_REJECT_CDE + bitOffset: 2 + bitWidth: 5 + access: read-only + - register: + name: SPI_MEM_REJECT_ADDR + addressOffset: 120 + size: 32 + fields: + - name: SPI_MEM_REJECT_ADDR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SDIO_CTRL + addressOffset: 124 + size: 32 + fields: + - name: SDIO_WIN_ACCESS_EN + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: REDCY_SIG0 + addressOffset: 128 + size: 32 + fields: + - name: REDCY_SIG0 + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: REDCY_ANDOR + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: REDCY_SIG1 + addressOffset: 132 + size: 32 + fields: + - name: REDCY_SIG1 + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: REDCY_NANDOR + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: WIFI_BB_CFG + addressOffset: 136 + size: 32 + fields: + - name: WIFI_BB_CFG + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WIFI_BB_CFG_2 + addressOffset: 140 + size: 32 + fields: + - name: WIFI_BB_CFG_2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WIFI_CLK_EN + addressOffset: 144 + size: 32 + resetValue: 4294762544 + fields: + - name: WIFI_CLK_EN + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WIFI_RST_EN + addressOffset: 148 + size: 32 + resetValue: 4294762544 + fields: + - name: WIFI_RST + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FRONT_END_MEM_PD + addressOffset: 152 + size: 32 + resetValue: 21 + fields: + - name: AGC_MEM_FORCE_PU + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: AGC_MEM_FORCE_PD + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PBUS_MEM_FORCE_PU + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PBUS_MEM_FORCE_PD + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DC_MEM_FORCE_PU + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DC_MEM_FORCE_PD + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: DATE + addressOffset: 1020 + size: 32 + resetValue: 26243088 + fields: + - name: DATE + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: SYSTEM + description: System Configuration Registers + groupName: SYSTEM + baseAddress: 1061945344 + addressBlock: + - offset: 0 + size: 148 + usage: registers + registers: + - register: + name: ROM_CTRL_0 + description: System ROM configuration register 0 + addressOffset: 0 + size: 32 + resetValue: 3 + fields: + - name: ROM_FO + description: This field is used to force on clock gate of internal ROM. + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: ROM_CTRL_1 + description: System ROM configuration register 1 + addressOffset: 4 + size: 32 + resetValue: 12 + fields: + - name: ROM_FORCE_PD + description: This field is used to power down internal ROM. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: ROM_FORCE_PU + description: This field is used to power up internal ROM. + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: SRAM_CTRL_0 + description: System SRAM configuration register 0 + addressOffset: 8 + size: 32 + resetValue: 4194303 + fields: + - name: SRAM_FO + description: This field is used to force on clock gate of internal SRAM. + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SRAM_CTRL_1 + description: System SRAM configuration register 1 + addressOffset: 12 + size: 32 + fields: + - name: SRAM_FORCE_PD + description: This field is used to power down internal SRAM. + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: CPU_PERI_CLK_EN + description: CPU peripheral clock enable register + addressOffset: 16 + size: 32 + fields: + - name: CLK_EN_DEDICATED_GPIO + description: Set this bit to enable clock of DEDICATED GPIO module. + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: CPU_PERI_RST_EN + description: CPU peripheral reset register + addressOffset: 20 + size: 32 + resetValue: 128 + fields: + - name: RST_EN_DEDICATED_GPIO + description: Set this bit to reset DEDICATED GPIO module. + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: CPU_PER_CONF + description: CPU peripheral clock configuration register + addressOffset: 24 + size: 32 + resetValue: 12 + fields: + - name: CPUPERIOD_SEL + description: This field is used to select the clock frequency of CPU or CPU period. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: PLL_FREQ_SEL + description: This field is used to select the PLL clock frequency based on CPU period. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CPU_WAIT_MODE_FORCE_ON + description: "Set this bit to force on CPU wait mode. In this mode, the clock gate of CPU is turned off until any interrupts happen. This mode could also be force on via WAITI instruction." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CPU_WAITI_DELAY_NUM + description: Sets the number of delay cycles to enter CPU wait mode after a WAITI instruction. + bitOffset: 4 + bitWidth: 4 + access: read-write + - register: + name: JTAG_CTRL_0 + description: JTAG configuration register 0 + addressOffset: 28 + size: 32 + fields: + - name: CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 + description: Stores the 0 to 31 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: JTAG_CTRL_1 + description: JTAG configuration register 1 + addressOffset: 32 + size: 32 + fields: + - name: CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 + description: Stores the 32 to 63 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: JTAG_CTRL_2 + description: JTAG configuration register 2 + addressOffset: 36 + size: 32 + fields: + - name: CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 + description: Stores the 64 to 95 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: JTAG_CTRL_3 + description: JTAG configuration register 3 + addressOffset: 40 + size: 32 + fields: + - name: CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 + description: Stores the 96 to 127 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: JTAG_CTRL_4 + description: JTAG configuration register 4 + addressOffset: 44 + size: 32 + fields: + - name: CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 + description: Stores the 128 to 159 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: JTAG_CTRL_5 + description: JTAG configuration register 5 + addressOffset: 48 + size: 32 + fields: + - name: CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 + description: Stores the 160 to 191 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: JTAG_CTRL_6 + description: JTAG configuration register 6 + addressOffset: 52 + size: 32 + fields: + - name: CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 + description: Stores the 192 to 223 bits of the 256 bits register used to cancel the temporary disable of eFuse to JTAG. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: JTAG_CTRL_7 + description: JTAG configuration register 7 + addressOffset: 56 + size: 32 + fields: + - name: CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 + description: Stores the 0 to 224 bits of the 255 bits register used to cancel the temporary disable of eFuse to JTAG. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: MEM_PD_MASK + description: Memory power-related controlling register (under low-sleep) + addressOffset: 60 + size: 32 + resetValue: 1 + fields: + - name: LSLP_MEM_PD_MASK + description: Set this bit to allow the memory to work as usual when the chip enters the light-sleep state. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: PERIP_CLK_EN0 + description: System peripheral clock (for hardware accelerators) enable register + addressOffset: 64 + size: 32 + resetValue: 4190232687 + fields: + - name: TIMERS_CLK_EN + description: Set this bit to enable clock of timers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI01_CLK_EN + description: Set this bit to enable clock of SPI0 and SPI1. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UART_CLK_EN + description: Set this bit to enable clock of UART0. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: WDG_CLK_EN + description: Set this bit to enable clock of WDG. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: I2S0_CLK_EN + description: Set this bit to enable clock of I2S0. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: UART1_CLK_EN + description: Set this bit to enable clock of UART1. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI2_CLK_EN + description: Set this bit to enable clock of SPI2. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: I2C_EXT0_CLK_EN + description: Set this bit to enable clock of I2C EXT0. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: UHCI0_CLK_EN + description: Set this bit to enable clock of UHCI0. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RMT_CLK_EN + description: Set this bit to enable clock of remote controller. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PCNT_CLK_EN + description: Set this bit to enable clock of pulse count. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: LEDC_CLK_EN + description: Set this bit to enable clock of LED PWM. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: UHCI1_CLK_EN + description: Set this bit to enable clock of UHCI1. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TIMERGROUP_CLK_EN + description: Set this bit to enable clock of timer group0. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: EFUSE_CLK_EN + description: Set this bit to enable clock of eFuse. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TIMERGROUP1_CLK_EN + description: Set this bit to enable clock of timer group1. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI3_CLK_EN + description: Set this bit to enable clock of SPI3. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PWM0_CLK_EN + description: Set this bit to enable clock of PWM0. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: I2C_EXT1_CLK_EN + description: Set this bit to enable clock of I2C EXT1. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TWAI_CLK_EN + description: Set this bit to enable clock of CAN. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PWM1_CLK_EN + description: Set this bit to enable clock of PWM1. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: I2S1_CLK_EN + description: Set this bit to enable clock of I2S1. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI2_DMA_CLK_EN + description: Set this bit to enable clock of SPI2 DMA. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: USB_CLK_EN + description: Set this bit to enable clock of USB. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: UART_MEM_CLK_EN + description: Set this bit to enable clock of UART memory. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PWM2_CLK_EN + description: Set this bit to enable clock of PWM2. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PWM3_CLK_EN + description: Set this bit to enable clock of PWM3. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI3_DMA_CLK_EN + description: Set this bit to enable clock of SPI3 DMA. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: APB_SARADC_CLK_EN + description: Set this bit to enable clock of SAR ADC. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SYSTIMER_CLK_EN + description: Set this bit to enable clock of system timer. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ADC2_ARB_CLK_EN + description: Set this bit to enable clock of aribiter of ADC2. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI4_CLK_EN + description: Set this bit to enable clock of SPI4. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: PERIP_CLK_EN1 + description: System peripheral clock (for hardware accelerators) enable register 1 + addressOffset: 68 + size: 32 + fields: + - name: CRYPTO_AES_CLK_EN + description: Set this bit to enable clock of cryptography AES. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CRYPTO_SHA_CLK_EN + description: Set this bit to enable clock of cryptography SHA. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CRYPTO_RSA_CLK_EN + description: Set this bit to enable clock of cryptography RSA. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CRYPTO_DS_CLK_EN + description: Set this bit to enable clock of cryptography Digital Signature. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CRYPTO_HMAC_CLK_EN + description: Set this bit to enable clock of cryptography HMAC. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CRYPTO_DMA_CLK_EN + description: Set this bit to enable clock of cryptography DMA. + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: PERIP_RST_EN0 + description: System peripheral (hardware accelerators) reset register 0 + addressOffset: 72 + size: 32 + fields: + - name: TIMERS_RST + description: Set this bit to reset timers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI01_RST + description: Set this bit to reset SPI0 and SPI1. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UART_RST + description: Set this bit to reset UART0. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: WDG_RST + description: Set this bit to reset WDG. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: I2S0_RST + description: Set this bit to reset I2S0. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: UART1_RST + description: Set this bit to reset UART1. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI2_RST + description: Set this bit to reset SPI2. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: I2C_EXT0_RST + description: Set this bit to reset I2C EXT0. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: UHCI0_RST + description: Set this bit to reset UHCI0. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RMT_RST + description: Set this bit to reset remote controller. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PCNT_RST + description: Set this bit to reset pulse count. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: LEDC_RST + description: Set this bit to reset LED PWM. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: UHCI1_RST + description: Set this bit to reset UHCI1. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TIMERGROUP_RST + description: Set this bit to reset timer group0. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: EFUSE_RST + description: Set this bit to reset eFuse. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TIMERGROUP1_RST + description: Set this bit to reset timer group1. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI3_RST + description: Set this bit to reset SPI3. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PWM0_RST + description: Set this bit to reset PWM0. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: I2C_EXT1_RST + description: Set this bit to reset I2C EXT1. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TWAI_RST + description: Set this bit to reset CAN. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PWM1_RST + description: Set this bit to reset PWM1. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: I2S1_RST + description: Set this bit to reset I2S1. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI2_DMA_RST + description: Set this bit to reset SPI2 DMA. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: USB_RST + description: Set this bit to reset USB. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: UART_MEM_RST + description: Set this bit to reset UART memory. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PWM2_RST + description: Set this bit to reset PWM2. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PWM3_RST + description: Set this bit to reset PWM3. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI3_DMA_RST + description: Set this bit to reset SPI3 DMA. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: APB_SARADC_RST + description: Set this bit to reset SAR ADC. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SYSTIMER_RST + description: Set this bit to reset system timer. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ADC2_ARB_RST + description: Set this bit to reset aribiter of ADC2. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI4_RST + description: Set this bit to reset SPI4. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: PERIP_RST_EN1 + description: System peripheral (hardware accelerators) reset register 1 + addressOffset: 76 + size: 32 + resetValue: 126 + fields: + - name: CRYPTO_AES_RST + description: Set this bit to reset cryptography AES. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CRYPTO_SHA_RST + description: Set this bit to reset cryptography SHA. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CRYPTO_RSA_RST + description: Set this bit to reset cryptography RSA. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CRYPTO_DS_RST + description: Set this bit to reset cryptography digital signature. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CRYPTO_HMAC_RST + description: Set this bit to reset cryptography HMAC. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CRYPTO_DMA_RST + description: Set this bit to reset cryptography DMA. + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: LPCK_DIV_INT + description: Low power clock divider integer register + addressOffset: 80 + size: 32 + resetValue: 255 + fields: + - name: LPCK_DIV_NUM + description: This field is used to set the integer number of the divider value. + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: BT_LPCK_DIV_FRAC + description: Divider fraction configuration register for low-power clock + addressOffset: 84 + size: 32 + resetValue: 33554432 + fields: + - name: LPCLK_SEL_RTC_SLOW + description: Set this bit to select RTC slow clock as the low power clock. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: LPCLK_SEL_8M + description: Set this bit to select 8m clock as the low power clock. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LPCLK_SEL_XTAL + description: Set this bit to select xtal clock as the low power clock. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LPCLK_SEL_XTAL32K + description: Set this bit to select xtal32k clock as the low power clock. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LPCLK_RTC_EN + description: Set this bit to enable the RTC low power clock. + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_0 + description: CPU interrupt controlling register 0 + addressOffset: 88 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_0 + description: Set this bit to generate CPU interrupt 0. This bit needs to be reset by software in the ISR process. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_1 + description: CPU interrupt controlling register 1 + addressOffset: 92 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_1 + description: Set this bit to generate CPU interrupt 1. This bit needs to be reset by software in the ISR process. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_2 + description: CPU interrupt controlling register 2 + addressOffset: 96 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_2 + description: Set this bit to generate CPU interrupt 2. This bit needs to be reset by software in the ISR process. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_3 + description: CPU interrupt controlling register 3 + addressOffset: 100 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_3 + description: Set this bit to generate CPU interrupt 3. This bit needs to be reset by software in the ISR process. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: RSA_PD_CTRL + description: RSA memory remapping register + addressOffset: 104 + size: 32 + resetValue: 1 + fields: + - name: RSA_MEM_PD + description: "Set this bit to power down RSA memory. This bit has the lowest priority. When Digital Signature occupies the RSA, this bit is invalid." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RSA_MEM_FORCE_PU + description: Set this bit to force power up RSA memory. This bit has the second highest priority. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RSA_MEM_FORCE_PD + description: Set this bit to force power down RSA memory. This bit has the highest priority. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: BUSTOEXTMEM_ENA + description: EDMA enable register + addressOffset: 108 + size: 32 + resetValue: 1 + fields: + - name: BUSTOEXTMEM_ENA + description: Set this bit to enable bus to EDMA. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CACHE_CONTROL + description: Cache control register + addressOffset: 112 + size: 32 + resetValue: 3 + fields: + - name: PRO_ICACHE_CLK_ON + description: Set this bit to enable clock of i-cache. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_DCACHE_CLK_ON + description: Set this bit to enable clock of d-cache. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PRO_CACHE_RESET + description: Set this bit to reset cache. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL + description: External memory encrypt and decrypt controlling register + addressOffset: 116 + size: 32 + fields: + - name: ENABLE_SPI_MANUAL_ENCRYPT + description: Set this bit to enable Manual Encryption under SPI Boot mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ENABLE_DOWNLOAD_DB_ENCRYPT + description: Set this bit to enable Auto Encryption under Download Boot mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ENABLE_DOWNLOAD_G0CB_DECRYPT + description: Set this bit to enable Auto Decryption under Download Boot mode. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ENABLE_DOWNLOAD_MANUAL_ENCRYPT + description: Set this bit to enable Manual Encryption under Download Boot mode. + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: RTC_FASTMEM_CONFIG + description: RTC fast memory configuration register + addressOffset: 120 + size: 32 + resetValue: 2146435072 + fields: + - name: RTC_MEM_CRC_START + description: Set this bit to start the CRC of RTC memory. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RTC_MEM_CRC_ADDR + description: This field is used to set address of RTC memory for CRC. + bitOffset: 9 + bitWidth: 11 + access: read-write + - name: RTC_MEM_CRC_LEN + description: This field is used to set length of RTC memory for CRC based on start address. + bitOffset: 20 + bitWidth: 11 + access: read-write + - name: RTC_MEM_CRC_FINISH + description: This bit stores the status of RTC memory CRC. High level means finished while low level means not finished. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: RTC_FASTMEM_CRC + description: RTC fast memory CRC controlling register + addressOffset: 124 + size: 32 + fields: + - name: RTC_MEM_CRC_RES + description: This field stores the CRC result of RTC memory. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: Redundant_ECO_Ctrl + description: Redundant ECO control register + addressOffset: 128 + size: 32 + fields: + - name: REDUNDANT_ECO_DRIVE + description: The redundant ECO drive bit to avoid optimization in circuits. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REDUNDANT_ECO_RESULT + description: The redundant ECO result bit to avoid optimization in circuits. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: CLOCK_GATE + description: Clock gate control register + addressOffset: 132 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: Set this bit to enable clock of this module. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SRAM_CTRL_2 + description: System SRAM configuration register 2 + addressOffset: 136 + size: 32 + resetValue: 4194303 + fields: + - name: SRAM_FORCE_PU + description: This field is used to power up internal SRAM. + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SYSCLK_CONF + description: SoC clock configuration register + addressOffset: 140 + size: 32 + resetValue: 1 + fields: + - name: PRE_DIV_CNT + description: "This field is used to set the count of prescaler of XTAL\\_CLK." + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: SOC_CLK_SEL + description: This field is used to select SOC clock. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CLK_XTAL_FREQ + description: This field is used to read XTAL frequency in MHz. + bitOffset: 12 + bitWidth: 7 + access: read-only + - name: CLK_DIV_EN + description: "Not used, extends from ESP32." + bitOffset: 19 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: Version control register + addressOffset: 4092 + size: 32 + resetValue: 26247200 + fields: + - name: DATE + description: Version control register. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SYSTIMER + description: System Timer + groupName: SYSTIMER + baseAddress: 1061302272 + addressBlock: + - offset: 0 + size: 84 + usage: registers + interrupt: + - name: SYSTIMER_TARGET0 + value: 71 + - name: SYSTIMER_TARGET1 + value: 72 + - name: SYSTIMER_TARGET2 + value: 73 + registers: + - register: + name: CONF + description: Configure system timer clock + addressOffset: 0 + size: 32 + fields: + - name: CLK_FO + description: System timer clock force enable. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: Register clock enable. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LOAD + description: Load value to system timer + addressOffset: 4 + size: 32 + fields: + - name: TIMER_LOAD + description: "Set this bit to 1, the value stored in SYSTIMER_TIMER_LOAD_HI and in\nSYSTIMER_TIMER_LOAD_LO will be loaded to system timer" + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: LOAD_HI + description: High 32 bits to be loaded to system timer + addressOffset: 8 + size: 32 + fields: + - name: TIMER_LOAD_HI + description: "The value to be loaded into system timer, high 32 bits." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOAD_LO + description: Low 32 bits to be loaded to system timer + addressOffset: 12 + size: 32 + fields: + - name: TIMER_LOAD_LO + description: "The value to be loaded into system timer, low 32 bits." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STEP + description: System timer accumulation step + addressOffset: 16 + size: 32 + resetValue: 1104 + fields: + - name: TIMER_XTAL_STEP + description: Set system timer increment step when using XTAL_CLK. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: TIMER_PLL_STEP + description: Set system timer increment step when using PLL_CLK + bitOffset: 10 + bitWidth: 10 + access: read-write + - register: + name: TARGET0_HI + description: "System timer target 0, high 32 bits" + addressOffset: 20 + size: 32 + fields: + - name: TIMER_TARGET0_HI + description: "System timer target 0, high 32 bits." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET0_LO + description: "System timer target 0, low 32 bits" + addressOffset: 24 + size: 32 + fields: + - name: TIMER_TARGET0_LO + description: "System timer target 0, low 32 bits." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET1_HI + description: "System timer target 1, high 32 bits" + addressOffset: 28 + size: 32 + fields: + - name: TIMER_TARGET1_HI + description: "System timer target 1, high 32 bits." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET1_LO + description: "System timer target 1, low 32 bits" + addressOffset: 32 + size: 32 + fields: + - name: TIMER_TARGET1_LO + description: "System timer target 1, low 32 bits." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET2_HI + description: "System timer target 2, high 32 bits" + addressOffset: 36 + size: 32 + fields: + - name: TIMER_TARGET2_HI + description: "System timer target 2, high 32 bits." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET2_LO + description: "System timer target 2, low 32 bits" + addressOffset: 40 + size: 32 + fields: + - name: TIMER_TARGET2_LO + description: "System timer target 2, low 32 bits." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET0_CONF + description: Configure work mode for system timer target 0 + addressOffset: 44 + size: 32 + fields: + - name: TARGET0_PERIOD + description: "Set alarm period for system timer target 0, only valid in periodic\nalarms mode." + bitOffset: 0 + bitWidth: 30 + access: read-write + - name: TARGET0_PERIOD_MODE + description: "Set work mode for system timer target 0. 0: work in a timedelay alarm mode; 1: work in periodic alarms mode." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TARGET0_WORK_EN + description: System timer target 0 work enable. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TARGET1_CONF + description: Configure work mode for system timer target 1 + addressOffset: 48 + size: 32 + fields: + - name: TARGET1_PERIOD + description: "Set alarm period for system timer target 1, only valid in periodic\nalarms mode." + bitOffset: 0 + bitWidth: 30 + access: read-write + - name: TARGET1_PERIOD_MODE + description: "Set work mode for system timer target 1. 0: work in a timedelay alarm mode; 1: work in periodic alarms mode." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TARGET1_WORK_EN + description: System timer target 1 work enable. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TARGET2_CONF + description: Configure work mode for system timer target 2 + addressOffset: 52 + size: 32 + fields: + - name: TARGET2_PERIOD + description: "Set alarm period for system timer target 2, only valid in periodic\nalarms mode." + bitOffset: 0 + bitWidth: 30 + access: read-write + - name: TARGET2_PERIOD_MODE + description: "Set work mode for system timer target 2. 0: work in a timedelay alarm mode; 1: work in periodic alarms mode." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TARGET2_WORK_EN + description: System timer target 2 work enable. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: UNIT0_OP + description: Read out system timer value + addressOffset: 56 + size: 32 + fields: + - name: TIMER_UNIT0_VALUE_VALID + description: "Check if it is valid to read out timer value from registers. 0: Not\nready to read timer value from registers; 1: Ready to read timer value from registers" + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: TIMER_UNIT0_UPDATE + description: Update system timer value to registers. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: UNIT0_VALUE_HI + description: "System timer value, high 32 bits" + addressOffset: 60 + size: 32 + fields: + - name: TIMER_VALUE_HI + description: "System timer value, high 32 bits." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: UNIT0_VALUE_LO + description: "System timer value, low 32 bits" + addressOffset: 64 + size: 32 + fields: + - name: TIMER_VALUE_LO + description: "System timer value, low 32 bits." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: INT_ENA + description: System timer interrupt enable + addressOffset: 68 + size: 32 + fields: + - name: TARGET0_INT_ENA + description: Interrupt enable bit of system timer target 0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TARGET1_INT_ENA + description: Interrupt enable bit of system timer target 1. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TARGET2_INT_ENA + description: Interrupt enable bit of system timer target 2. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: System timer interrupt raw + addressOffset: 72 + size: 32 + fields: + - name: INT0_RAW + description: Interrupt raw bit of system timer target 0. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: INT1_RAW + description: Interrupt raw bit of system timer target 1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: INT2_RAW + description: Interrupt raw bit of system timer target 2. + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: System timer interrupt clear + addressOffset: 76 + size: 32 + fields: + - name: TARGET0_INT_CLR + description: Interrupt clear bit of system timer target 0. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TARGET1_INT_CLR + description: Interrupt clear bit of system timer target 1. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TARGET2_INT_CLR + description: Interrupt clear bit of system timer target 2. + bitOffset: 2 + bitWidth: 1 + access: write-only + - register: + name: DATE + description: Version control register + addressOffset: 252 + size: 32 + resetValue: 25194848 + fields: + - name: DATE + description: Version control register + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: TIMG0 + description: Timer Group 0 + groupName: TIMG + baseAddress: 1061285888 + addressBlock: + - offset: 0 + size: 180 + usage: registers + interrupt: + - name: TG0_T0_LEVEL + value: 15 + - name: TG0_T1_LEVEL + value: 16 + - name: TG0_WDT_LEVEL + value: 17 + - name: TG0_LACT_LEVEL + value: 18 + - name: TG0_T0_EDGE + value: 62 + - name: TG0_T1_EDGE + value: 63 + - name: TG0_WDT_EDGE + value: 64 + - name: TG0_LACT_EDGE + value: 65 + registers: + - register: + dim: 2 + dimIncrement: 36 + name: T%sCONFIG + description: Timer %s configuration register + addressOffset: 0 + size: 32 + resetValue: 1610620928 + fields: + - name: USE_XTAL + description: "1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: ALARM_EN + description: "When set, the alarm is enabled. This bit is automatically cleared once an alarm occurs." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: LEVEL_INT_EN + description: "When set, an alarm will generate a level type interrupt." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: EDGE_INT_EN + description: "When set, an alarm will generate an edge type interrupt." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DIVIDER + description: Timer %s clock (T%s_clk) prescaler value. + bitOffset: 13 + bitWidth: 16 + access: read-write + - name: AUTORELOAD + description: "When set, timer %s auto-reload at alarm is enabled." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: INCREASE + description: "When set, the timer %s time-base counter will increment every clock tick. When cleared, the timer %s time-base counter will decrement." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: EN + description: "When set, the timer %s time-base counter is enabled." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + dim: 2 + dimIncrement: 36 + name: T%sLO + description: "Timer %s current value, low 32 bits" + addressOffset: 4 + size: 32 + fields: + - name: LO + description: "After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter of timer %s can be read here." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + dim: 2 + dimIncrement: 36 + name: T%sHI + description: "Timer %s current value, high 32 bits" + addressOffset: 8 + size: 32 + fields: + - name: HI + description: "After writing to TIMG_T%sUPDATE_REG, the high 32 bits of the time-base counter of timer %s can be read here." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + dim: 2 + dimIncrement: 36 + name: T%sUPDATE + description: Write to copy current timer value to TIMG_T%sLO_REG or TIMGn_T%sHI_REG + addressOffset: 12 + size: 32 + fields: + - name: UPDATE + description: "After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + dim: 2 + dimIncrement: 36 + name: T%sALARMLO + description: "Timer %s alarm value, low 32 bits" + addressOffset: 16 + size: 32 + fields: + - name: ALARM_LO + description: "Timer %s alarm trigger time-base counter value, low 32 bits." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 2 + dimIncrement: 36 + name: T%sALARMHI + description: "Timer %s alarm value, high bits" + addressOffset: 20 + size: 32 + fields: + - name: ALARM_HI + description: "Timer %s alarm trigger time-base counter value, high 32 bits." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 2 + dimIncrement: 36 + name: T%sLOADLO + description: "Timer %s reload value, low 32 bits" + addressOffset: 24 + size: 32 + fields: + - name: LOAD_LO + description: Low 32 bits of the value that a reload will load onto timer %s time-base counter. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 2 + dimIncrement: 36 + name: T%sLOADHI + description: "Timer %s reload value, high 32 bits" + addressOffset: 28 + size: 32 + fields: + - name: LOAD_HI + description: High 32 bits of the value that a reload will load onto timer %s time-base counter. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 2 + dimIncrement: 36 + name: T%sLOAD + description: Write to reload timer from TIMG_T%sLOADLO_REG or TIMG_T%sLOADHI_REG + addressOffset: 32 + size: 32 + fields: + - name: LOAD + description: Write any value to trigger a timer %s time-base counter reload. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: WDTCONFIG0 + description: Watchdog timer configuration register + addressOffset: 72 + size: 32 + resetValue: 311296 + fields: + - name: WDT_APPCPU_RESET_EN + description: Reserved. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: WDT_PROCPU_RESET_EN + description: WDT reset CPU enable. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: WDT_FLASHBOOT_MOD_EN + description: "When set, Flash boot protection is enabled." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: WDT_SYS_RESET_LENGTH + description: "System reset signal length selection. 0: 100 ns. 1: 200 ns. 2: 300 ns. 3: 400 ns. 4: 500 ns. 5: 800 ns. 6: 1.6 us. 7: 3.2 us." + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: WDT_CPU_RESET_LENGTH + description: "CPU reset signal length selection. 0: 100 ns. 1: 200 ns. 2: 300 ns. 3: 400 ns. 4: 500 ns. 5: 800 ns. 6: 1.6 us. 7: 3.2 us." + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: WDT_LEVEL_INT_EN + description: "When set, a level type interrupt will occur at the timeout of a stage configured to generate an interrupt." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: WDT_EDGE_INT_EN + description: "When set, an edge type interrupt will occur at the timeout of a stage configured to generate an interrupt." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: WDT_STG3 + description: "Stage 3 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system." + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: WDT_STG2 + description: "Stage 2 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system." + bitOffset: 25 + bitWidth: 2 + access: read-write + - name: WDT_STG1 + description: "Stage 1 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system." + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: WDT_STG0 + description: "Stage 0 configuration. 0: off. 1: interrupt. 2: reset CPU. 3: reset system." + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: WDT_EN + description: "When set, MWDT is enabled." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: WDTCONFIG1 + description: Watchdog timer prescaler register + addressOffset: 76 + size: 32 + resetValue: 65536 + fields: + - name: WDT_CLK_PRESCALE + description: MWDT clock prescaler value. MWDT clock period = 12.5 ns * TIMG_WDT_CLK_PRESCALE. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: WDTCONFIG2 + description: Watchdog timer stage 0 timeout value + addressOffset: 80 + size: 32 + resetValue: 26000000 + fields: + - name: WDT_STG0_HOLD + description: "Stage 0 timeout value, in MWDT clock cycles." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG3 + description: Watchdog timer stage 1 timeout value + addressOffset: 84 + size: 32 + resetValue: 134217727 + fields: + - name: WDT_STG1_HOLD + description: "Stage 1 timeout value, in MWDT clock cycles." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG4 + description: Watchdog timer stage 2 timeout value + addressOffset: 88 + size: 32 + resetValue: 1048575 + fields: + - name: WDT_STG2_HOLD + description: "Stage 2 timeout value, in MWDT clock cycles." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG5 + description: Watchdog timer stage 3 timeout value + addressOffset: 92 + size: 32 + resetValue: 1048575 + fields: + - name: WDT_STG3_HOLD + description: "Stage 3 timeout value, in MWDT clock cycles." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTFEED + description: Write to feed the watchdog timer + addressOffset: 96 + size: 32 + fields: + - name: WDT_FEED + description: Write any value to feed the MWDT. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: WDTWPROTECT + description: Watchdog write protect register + addressOffset: 100 + size: 32 + resetValue: 1356348065 + fields: + - name: WDT_WKEY + description: "If the register contains a different value than its reset value, write protection is enabled." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RTCCALICFG + description: RTC calibration configuration register + addressOffset: 104 + size: 32 + resetValue: 77824 + fields: + - name: RTC_CALI_START_CYCLING + description: "When set, periodic calibration is enabled." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RTC_CALI_CLK_SEL + description: "Used to select the clock to be calibrated. 0: RTC_CLK. 1: RTC20M_D256_CLK. 2: XTAL32K_CLK." + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: RTC_CALI_RDY + description: Set this bit to mark the completion of calibration. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: RTC_CALI_MAX + description: "Calibration time, in cycles of the clock to be calibrated." + bitOffset: 16 + bitWidth: 15 + access: read-write + - name: RTC_CALI_START + description: Set this bit to starts calibration. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RTCCALICFG1 + description: RTC calibration configuration register 1 + addressOffset: 108 + size: 32 + fields: + - name: RTC_CALI_CYCLING_DATA_VLD + description: Periodic calibration valid signal. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RTC_CALI_VALUE + description: "Calibration value when cycles of clock to be calibrated reach TIMG_RTC_CALI_MAX, in unit of XTAL_CLK clock cycles." + bitOffset: 7 + bitWidth: 25 + access: read-only + - register: + name: LACTCONFIG + description: LACT configuration register + addressOffset: 112 + size: 32 + resetValue: 1610621696 + fields: + - name: LACT_USE_REFTICK + description: Reserved. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: LACT_RTC_ONLY + description: Reserved. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: LACT_CPST_EN + description: Reserved. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: LACT_LAC_EN + description: Reserved. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: LACT_ALARM_EN + description: Reserved. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: LACT_LEVEL_INT_EN + description: Reserved. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: LACT_EDGE_INT_EN + description: Reserved. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: LACT_DIVIDER + description: Reserved. + bitOffset: 13 + bitWidth: 16 + access: read-write + - name: LACT_AUTORELOAD + description: Reserved. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LACT_INCREASE + description: Reserved. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LACT_EN + description: Reserved. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LACTRTC + description: LACT RTC register + addressOffset: 116 + size: 32 + fields: + - name: LACT_RTC_STEP_LEN + description: Reserved. + bitOffset: 6 + bitWidth: 26 + access: read-write + - register: + name: LACTLO + description: LACT low register + addressOffset: 120 + size: 32 + fields: + - name: LACT_LO + description: Reserved. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: LACTHI + description: LACT high register + addressOffset: 124 + size: 32 + fields: + - name: LACT_HI + description: Reserved. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: LACTUPDATE + description: LACT update register + addressOffset: 128 + size: 32 + fields: + - name: LACT_UPDATE + description: Reserved. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: LACTALARMLO + description: LACT alarm low register + addressOffset: 132 + size: 32 + fields: + - name: LACT_ALARM_LO + description: Reserved. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LACTALARMHI + description: LACT alarm high register + addressOffset: 136 + size: 32 + fields: + - name: LACT_ALARM_HI + description: Reserved. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LACTLOADLO + description: LACT load low register + addressOffset: 140 + size: 32 + fields: + - name: LACT_LOAD_LO + description: Reserved. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LACTLOADHI + description: Timer LACT load high register + addressOffset: 144 + size: 32 + fields: + - name: LACT_LOAD_HI + description: Reserved. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LACTLOAD + description: Timer LACT load register + addressOffset: 148 + size: 32 + fields: + - name: LACT_LOAD + description: Reserved. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: INT_ENA_TIMERS + description: Interrupt enable bits + addressOffset: 152 + size: 32 + fields: + - name: T0_INT_ENA + description: The interrupt enable bit for the TIMG_T0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: T1_INT_ENA + description: The interrupt enable bit for the TIMG_T1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: WDT_INT_ENA + description: The interrupt enable bit for the TIMG_WDT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: LACT_INT_ENA + description: The interrupt enable bit for the TIMG_LACT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW_TIMERS + description: Raw interrupt status + addressOffset: 156 + size: 32 + fields: + - name: T0_INT_RAW + description: The raw interrupt status bit for the TIMG_T0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: T1_INT_RAW + description: The raw interrupt status bit for the TIMG_T1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: WDT_INT_RAW + description: The raw interrupt status bit for the TIMG_WDT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: LACT_INT_RAW + description: The raw interrupt status bit for the TIMG_LACT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_ST_TIMERS + description: Masked interrupt status + addressOffset: 160 + size: 32 + fields: + - name: T0_INT_ST + description: The masked interrupt status bit for the TIMG_T0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: T1_INT_ST + description: The masked interrupt status bit for the TIMG_T1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: WDT_INT_ST + description: The masked interrupt status bit for the TIMG_WDT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: LACT_INT_ST + description: The masked interrupt status bit for the TIMG_LACT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR_TIMERS + description: Interrupt clear bits + addressOffset: 164 + size: 32 + fields: + - name: T0_INT_CLR + description: Set this bit to clear the TIMG_T0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: T1_INT_CLR + description: Set this bit to clear the TIMG_T1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: WDT_INT_CLR + description: Set this bit to clear the TIMG_WDT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: LACT_INT_CLR + description: Set this bit to clear the TIMG_LACT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: RTCCALICFG2 + description: Timer group calibration register + addressOffset: 168 + size: 32 + resetValue: 4294967192 + fields: + - name: RTC_CALI_TIMEOUT + description: RTC calibration timeout indicator + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RTC_CALI_TIMEOUT_RST_CNT + description: Cycles that release calibration timeout reset + bitOffset: 3 + bitWidth: 4 + access: read-write + - name: RTC_CALI_TIMEOUT_THRES + description: "Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered." + bitOffset: 7 + bitWidth: 25 + access: read-write + - register: + name: TIMERS_DATE + description: Version control register + addressOffset: 248 + size: 32 + resetValue: 26243681 + fields: + - name: TIMERS_DATE + description: Version control register. + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + name: REGCLK + description: Timer group clock gate register + addressOffset: 252 + size: 32 + fields: + - name: CLK_EN + description: "Register clock gate signal. 1: Registers can be read and written to by software. 0: Registers can not be read or written to by software." + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: TIMG1 + description: Timer Group 1 + baseAddress: 1061289984 + interrupt: + - name: TG1_T0_LEVEL + value: 19 + - name: TG1_T1_LEVEL + value: 20 + - name: TG1_WDT_LEVEL + value: 21 + - name: TG1_LACT_LEVEL + value: 22 + - name: TG1_T0_EDGE + value: 66 + - name: TG1_T1_EDGE + value: 67 + - name: TG1_WDT_EDGE + value: 68 + - name: TG1_LACT_EDGE + value: 69 + derivedFrom: TIMG0 + - name: TWAI0 + description: Two-Wire Automotive Interface + groupName: TWAI + baseAddress: 1061335040 + addressBlock: + - offset: 0 + size: 108 + usage: registers + interrupt: + - name: TWAI0 + value: 47 + registers: + - register: + name: MODE + description: Mode Register + addressOffset: 0 + size: 32 + resetValue: 1 + fields: + - name: RESET_MODE + description: "This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LISTEN_ONLY_MODE + description: "1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SELF_TEST_MODE + description: "1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_FILTER_MODE + description: "This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode." + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: CMD + description: Command Register + addressOffset: 4 + size: 32 + fields: + - name: TX_REQ + description: Set the bit to 1 to allow the driving nodes start transmission. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ABORT_TX + description: Set the bit to 1 to cancel a pending transmission request. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RELEASE_BUF + description: Set the bit to 1 to release the RX buffer. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CLR_OVERRUN + description: Set the bit to 1 to clear the data overrun status bit. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SELF_RX_REQ + description: Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously. + bitOffset: 4 + bitWidth: 1 + access: write-only + - register: + name: STATUS + description: Status register + addressOffset: 8 + size: 32 + fields: + - name: RX_BUF_ST + description: "1: The data in the RX buffer is not empty, with at least one received data packet." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OVERRUN_ST + description: "1: The RX FIFO is full and data overrun has occurred." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TX_BUF_ST + description: "1: The TX buffer is empty, the CPU may write a message into it." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_COMPLETE + description: "1: The TWAI controller has successfully received a packet from the bus." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: RX_ST + description: "1: The TWAI Controller is receiving a message from the bus." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TX_ST + description: "1: The TWAI Controller is transmitting a message to the bus." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ERR_ST + description: "1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG." + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BUS_OFF_ST + description: "1: In bus-off status, the TWAI Controller is no longer involved in bus activities." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: MISS_ST + description: "This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete" + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INT_RAW + description: Interrupt Register + addressOffset: 12 + size: 32 + fields: + - name: RX_INT_ST + description: "Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_INT_ST + description: "Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ERR_WARN_INT_ST + description: "Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0)." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: OVERRUN_INT_ST + description: "Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: ERR_PASSIVE_INT_ST + description: "Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ARB_LOST_INT_ST + description: "Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated." + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BUS_ERR_INT_ST + description: "Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus." + bitOffset: 7 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt Enable Register + addressOffset: 16 + size: 32 + fields: + - name: RX_INT_ENA + description: Set this bit to 1 to enable receive interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_INT_ENA + description: Set this bit to 1 to enable transmit interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ERR_WARN_INT_ENA + description: Set this bit to 1 to enable error warning interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OVERRUN_INT_ENA + description: Set this bit to 1 to enable data overrun interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ERR_PASSIVE_INT_ENA + description: Set this bit to 1 to enable error passive interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: ARB_LOST_INT_ENA + description: Set this bit to 1 to enable arbitration lost interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BUS_ERR_INT_ENA + description: Set this bit to 1 to enable error interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: BUS_TIMING_0 + description: Bus Timing Register 0 + addressOffset: 24 + size: 32 + fields: + - name: BAUD_PRESC + description: "Baud Rate Prescaler, determines the frequency dividing ratio." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: SYNC_JUMP_WIDTH + description: "Synchronization Jump Width (SJW), 1 \\verb+~+ 14 Tq wide." + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: BUS_TIMING_1 + description: Bus Timing Register 1 + addressOffset: 28 + size: 32 + fields: + - name: TIME_SEG1 + description: The width of PBS1. + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: TIME_SEG2 + description: The width of PBS2. + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: TIME_SAMP + description: "The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times" + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: ARB_LOST_CAP + description: Arbitration Lost Capture Register + addressOffset: 44 + size: 32 + fields: + - name: ARB_LOST_CAP + description: This register contains information about the bit position of lost arbitration. + bitOffset: 0 + bitWidth: 5 + access: read-only + - register: + name: ERR_CODE_CAP + description: Error Code Capture Register + addressOffset: 48 + size: 32 + fields: + - name: ECC_SEGMENT + description: "This register contains information about the location of errors, see Table 181 for details." + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: ECC_DIRECTION + description: "This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ECC_TYPE + description: "This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error" + bitOffset: 6 + bitWidth: 2 + access: read-only + - register: + name: ERR_WARNING_LIMIT + description: Error Warning Limit Register + addressOffset: 52 + size: 32 + resetValue: 96 + fields: + - name: ERR_WARNING_LIMIT + description: "Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid)." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: RX_ERR_CNT + description: Receive Error Counter Register + addressOffset: 56 + size: 32 + fields: + - name: RX_ERR_CNT + description: "The RX error counter register, reflects value changes under reception status." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: TX_ERR_CNT + description: Transmit Error Counter Register + addressOffset: 60 + size: 32 + fields: + - name: TX_ERR_CNT + description: "The TX error counter register, reflects value changes under transmission status." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_0 + description: Data register 0 + addressOffset: 64 + size: 32 + fields: + - name: TX_BYTE_0 + description: "In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_1 + description: Data register 1 + addressOffset: 68 + size: 32 + fields: + - name: TX_BYTE_1 + description: "In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_2 + description: Data register 2 + addressOffset: 72 + size: 32 + fields: + - name: TX_BYTE_2 + description: "In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_3 + description: Data register 3 + addressOffset: 76 + size: 32 + fields: + - name: TX_BYTE_3 + description: "In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_4 + description: Data register 4 + addressOffset: 80 + size: 32 + fields: + - name: TX_BYTE_4 + description: "In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_5 + description: Data register 5 + addressOffset: 84 + size: 32 + fields: + - name: TX_BYTE_5 + description: "In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_6 + description: Data register 6 + addressOffset: 88 + size: 32 + fields: + - name: TX_BYTE_6 + description: "In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_7 + description: Data register 7 + addressOffset: 92 + size: 32 + fields: + - name: TX_BYTE_7 + description: "In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_8 + description: Data register 8 + addressOffset: 96 + size: 32 + fields: + - name: TX_BYTE_8 + description: Stored the 8th byte information of the data to be transmitted under operating mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_9 + description: Data register 9 + addressOffset: 100 + size: 32 + fields: + - name: TX_BYTE_9 + description: Stored the 9th byte information of the data to be transmitted under operating mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_10 + description: Data register 10 + addressOffset: 104 + size: 32 + fields: + - name: TX_BYTE_10 + description: Stored the 10th byte information of the data to be transmitted under operating mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_11 + description: Data register 11 + addressOffset: 108 + size: 32 + fields: + - name: TX_BYTE_11 + description: Stored the 11th byte information of the data to be transmitted under operating mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_12 + description: Data register 12 + addressOffset: 112 + size: 32 + fields: + - name: TX_BYTE_12 + description: Stored the 12th byte information of the data to be transmitted under operating mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: RX_MESSAGE_CNT + description: Receive Message Counter Register + addressOffset: 116 + size: 32 + fields: + - name: RX_MESSAGE_COUNTER + description: This register reflects the number of messages available within the RX FIFO. + bitOffset: 0 + bitWidth: 7 + access: read-only + - register: + name: CLOCK_DIVIDER + description: Clock Divider register + addressOffset: 124 + size: 32 + fields: + - name: CD + description: These bits are used to configure frequency dividing coefficients of the external CLKOUT pin. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CLOCK_OFF + description: "This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: UART0 + description: UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + groupName: UART + baseAddress: 1061158912 + addressBlock: + - offset: 0 + size: 124 + usage: registers + interrupt: + - name: UART0 + value: 37 + registers: + - register: + name: FIFO + description: FIFO data register + addressOffset: 0 + size: 32 + fields: + - name: RXFIFO_RD_BYTE + description: UART 0 accesses FIFO via this register. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 4 + size: 32 + fields: + - name: RXFIFO_FULL_INT_RAW + description: This interrupt raw bit turns to high level when the receiver receives more data than what UART_RXFIFO_FULL_THRHD specifies. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_EMPTY_INT_RAW + description: This interrupt raw bit turns to high level when the amount of data in TX FIFO is less than what UART_TXFIFO_EMPTY_THRHD specifies. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: PARITY_ERR_INT_RAW + description: This interrupt raw bit turns to high level when the receiver detects a parity error in the data. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FRM_ERR_INT_RAW + description: This interrupt raw bit turns to high level when the receiver detects a data frame error. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_RAW + description: This interrupt raw bit turns to high level when the receiver receives more data than the capacity of RX FIFO. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DSR_CHG_INT_RAW + description: This interrupt raw bit turns to high level when the receiver detects the edge change of DSRn signal. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CTS_CHG_INT_RAW + description: This interrupt raw bit turns to high level when the receiver detects the edge change of CTSn signal. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BRK_DET_INT_RAW + description: This interrupt raw bit turns to high level when the receiver detects a 0 after the stop bit. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: RXFIFO_TOUT_INT_RAW + description: This interrupt raw bit turns to high level when the receiver takes more time than UART_RX_TOUT_THRHD to receive a byte. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SW_XON_INT_RAW + description: This interrupt raw bit turns to high level when the receiver receives an XON character and UART_SW_FLOW_CON_EN is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SW_XOFF_INT_RAW + description: This interrupt raw bit turns to high level when the receiver receives an XOFF character and UART_SW_FLOW_CON_EN is set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: GLITCH_DET_INT_RAW + description: This interrupt raw bit turns to high level when the receiver detects a glitch in the middle of a start bit. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TX_BRK_DONE_INT_RAW + description: "This interrupt raw bit turns to high level when the transmitter completes sending NULL characters, after all data in TX FIFO are sent." + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: TX_BRK_IDLE_DONE_INT_RAW + description: This interrupt raw bit turns to high level when the transmitter has kept the shortest duration after sending the last data. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_RAW + description: This interrupt raw bit turns to high level when the transmitter has sent out all data in FIFO. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: RS485_PARITY_ERR_INT_RAW + description: This interrupt raw bit turns to high level when the receiver detects a parity error from the echo of the transmitter in RS485 mode. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: RS485_FRM_ERR_INT_RAW + description: This interrupt raw bit turns to high level when the receiver detects a data frame error from the echo of the transmitter in RS485 mode. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: RS485_CLASH_INT_RAW + description: This interrupt raw bit turns to high level when a collision is detected between the transmitter and the receiver in RS485 mode. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: AT_CMD_CHAR_DET_INT_RAW + description: This interrupt raw bit turns to high level when the receiver detects the configured UART_AT_CMD CHAR. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: WAKEUP_INT_RAW + description: This interrupt raw bit turns to high level when input RXD edge changes more times than what UART_ACTIVE_THRESHOLD specifies in Light-sleep mode. + bitOffset: 19 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 8 + size: 32 + fields: + - name: RXFIFO_FULL_INT_ST + description: This is the status bit for UART_RXFIFO_FULL_INT when UART_RXFIFO_FULL_INT_ENA is set to 1. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_EMPTY_INT_ST + description: This is the status bit for UART_TXFIFO_EMPTY_INT when UART_TXFIFO_EMPTY_INT_ENA is set to 1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: PARITY_ERR_INT_ST + description: This is the status bit for UART_PARITY_ERR_INT when UART_PARITY_ERR_INT_ENA is set to 1. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FRM_ERR_INT_ST + description: This is the status bit for UART_FRM_ERR_INT when UART_FRM_ERR_INT_ENA is set to 1. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_ST + description: This is the status bit for UART_RXFIFO_OVF_INT when UART_RXFIFO_OVF_INT_ENA is set to 1. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DSR_CHG_INT_ST + description: This is the status bit for UART_DSR_CHG_INT when UART_DSR_CHG_INT_ENA is set to 1. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CTS_CHG_INT_ST + description: This is the status bit for UART_CTS_CHG_INT when UART_CTS_CHG_INT_ENA is set to 1. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BRK_DET_INT_ST + description: This is the status bit for UART_BRK_DET_INT when UART_BRK_DET_INT_ENA is set to 1. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: RXFIFO_TOUT_INT_ST + description: This is the status bit for UART_RXFIFO_TOUT_INT when UART_RXFIFO_TOUT_INT_ENA is set to 1. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SW_XON_INT_ST + description: This is the status bit for UART_SW_XON_INT when UART_SW_XON_INT_ENA is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SW_XOFF_INT_ST + description: This is the status bit for UART_SW_XOFF_INT when UART_SW_XOFF_INT_ENA is set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: GLITCH_DET_INT_ST + description: This is the status bit for UART_GLITCH_DET_INT when UART_GLITCH_DET_INT_ENA is set to 1. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TX_BRK_DONE_INT_ST + description: This is the status bit for UART_TX_BRK_DONE_INT when UART_TX_BRK_DONE_INT_ENA is set to 1. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: TX_BRK_IDLE_DONE_INT_ST + description: This is the status bit for UART_TX_BRK_IDLE_DONE_INT when UART_TX_BRK_IDLE_DONE_INT_ENA is set to 1. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_ST + description: This is the status bit for UART_TX_DONE_INT when UART_TX_DONE_INT_ENA is set to 1. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: RS485_PARITY_ERR_INT_ST + description: This is the status bit for UART_RS485_PARITY_ERR_INT when UART_RS485_PARITY_INT_ENA is set to 1. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: RS485_FRM_ERR_INT_ST + description: This is the status bit for UART_RS485_FRM_ERR_INT when UART_RS485_FRM_ERR_INT_ENA is set to 1. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: RS485_CLASH_INT_ST + description: This is the status bit for UART_RS485_CLASH_INT when UART_RS485_CLASH_INT_ENA is set to 1. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: AT_CMD_CHAR_DET_INT_ST + description: This is the status bit for UART_AT_CMD_CHAR_DET_INT when UART_AT_CMD_CHAR_DET_INT_ENA is set to 1. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: WAKEUP_INT_ST + description: This is the status bit for UART_WAKEUP_INT when UART_WAKEUP_INT_ENA is set to 1. + bitOffset: 19 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 12 + size: 32 + fields: + - name: RXFIFO_FULL_INT_ENA + description: This is the enable bit for UART_RXFIFO_FULL_INT. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_EMPTY_INT_ENA + description: This is the enable bit for UART_TXFIFO_EMPTY_INT. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PARITY_ERR_INT_ENA + description: This is the enable bit for UART_PARITY_ERR_INT. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FRM_ERR_INT_ENA + description: This is the enable bit for UART_FRM_ERR_INT. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_ENA + description: This is the enable bit for UART_RXFIFO_OVF_INT. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DSR_CHG_INT_ENA + description: This is the enable bit for UART_DSR_CHG_INT. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CTS_CHG_INT_ENA + description: This is the enable bit for UART_CTS_CHG_INT. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BRK_DET_INT_ENA + description: This is the enable bit for UART_BRK_DET_INT. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RXFIFO_TOUT_INT_ENA + description: This is the enable bit for UART_RXFIFO_TOUT_INT. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SW_XON_INT_ENA + description: This is the enable bit for UART_SW_XON_INT. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SW_XOFF_INT_ENA + description: This is the enable bit for UART_SW_XOFF_INT. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GLITCH_DET_INT_ENA + description: This is the enable bit for UART_GLITCH_DET_INT. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_BRK_DONE_INT_ENA + description: This is the enable bit for UART_TX_BRK_DONE_INT. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_BRK_IDLE_DONE_INT_ENA + description: This is the enable bit for UART_TX_BRK_IDLE_DONE_INT. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_ENA + description: This is the enable bit for UART_TX_DONE_INT. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RS485_PARITY_ERR_INT_ENA + description: This is the enable bit for UART_RS485_PARITY_ERR_INT. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RS485_FRM_ERR_INT_ENA + description: This is the enable bit for UART_RS485_PARITY_ERR_INT. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RS485_CLASH_INT_ENA + description: This is the enable bit for UART_RS485_CLASH_INT. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: AT_CMD_CHAR_DET_INT_ENA + description: This is the enable bit for UART_AT_CMD_CHAR_DET_INT. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: WAKEUP_INT_ENA + description: This is the enable bit for UART_WAKEUP_INT. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 16 + size: 32 + fields: + - name: RXFIFO_FULL_INT_CLR + description: Set this bit to clear UART_THE RXFIFO_FULL_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TXFIFO_EMPTY_INT_CLR + description: Set this bit to clear UART_TXFIFO_EMPTY_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: PARITY_ERR_INT_CLR + description: Set this bit to clear UART_PARITY_ERR_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: FRM_ERR_INT_CLR + description: Set this bit to clear UART_FRM_ERR_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: RXFIFO_OVF_INT_CLR + description: Set this bit to clear UART_UART_RXFIFO_OVF_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: DSR_CHG_INT_CLR + description: Set this bit to clear UART_DSR_CHG_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CTS_CHG_INT_CLR + description: Set this bit to clear UART_CTS_CHG_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: BRK_DET_INT_CLR + description: Set this bit to clear UART_BRK_DET_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: RXFIFO_TOUT_INT_CLR + description: Set this bit to clear UART_RXFIFO_TOUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SW_XON_INT_CLR + description: Set this bit to clear UART_SW_XON_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SW_XOFF_INT_CLR + description: Set this bit to clear UART_SW_XOFF_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: GLITCH_DET_INT_CLR + description: Set this bit to clear UART_GLITCH_DET_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TX_BRK_DONE_INT_CLR + description: Set this bit to clear UART_TX_BRK_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: TX_BRK_IDLE_DONE_INT_CLR + description: Set this bit to clear UART_TX_BRK_IDLE_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: TX_DONE_INT_CLR + description: Set this bit to clear UART_TX_DONE_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: RS485_PARITY_ERR_INT_CLR + description: Set this bit to clear UART_RS485_PARITY_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: RS485_FRM_ERR_INT_CLR + description: Set this bit to clear UART_RS485_FRM_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: RS485_CLASH_INT_CLR + description: Set this bit to clear UART_RS485_CLASH_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: AT_CMD_CHAR_DET_INT_CLR + description: Set this bit to clear UART_AT_CMD_CHAR_DET_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: WAKEUP_INT_CLR + description: Set this bit to clear UART_WAKEUP_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - register: + name: CLKDIV + description: Clock divider configuration + addressOffset: 20 + size: 32 + resetValue: 694 + fields: + - name: CLKDIV + description: The integral part of the frequency divisor. + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: FRAG + description: The fractional part of the frequency divisor. + bitOffset: 20 + bitWidth: 4 + access: read-write + - register: + name: AUTOBAUD + description: Autobaud configuration register + addressOffset: 24 + size: 32 + resetValue: 4096 + fields: + - name: EN + description: This is the enable bit for baud rate detection. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: GLITCH_FILT + description: "When input pulse width is lower than this value, the pulse is ignored.\nThis register is used in autobaud detection." + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: STATUS + description: UART status register + addressOffset: 28 + size: 32 + fields: + - name: RXFIFO_CNT + description: Stores the number of valid data bytes in RX FIFO. + bitOffset: 0 + bitWidth: 10 + access: read-only + - name: DSRN + description: This register represents the level of the internal UART DSR signal. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: CTSN + description: This register represents the level of the internal UART CTS signal. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: RXD + description: This register represents the level of the internal UART RXD signal. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TXFIFO_CNT + description: Stores the number of data bytes in TX FIFO. + bitOffset: 16 + bitWidth: 10 + access: read-only + - name: DTRN + description: This bit represents the level of the internal UART DTR signal. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: RTSN + description: This bit represents the level of the internal UART RTS signal. + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: TXD + description: This bit represents the level of the internal UART TXD signal. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CONF0 + description: Configuration register 0 + addressOffset: 32 + size: 32 + resetValue: 402653212 + fields: + - name: PARITY + description: "This register is used to configure the parity check mode.\n0: even. 1: odd." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PARITY_EN + description: Set this bit to enable UART parity check. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BIT_NUM + description: "This register is used to set the length of data.\n0: 5 bits. 1: 6 bits. 2: 7 bits. 3: 8 bits." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: STOP_BIT_NUM + description: "This register is used to set the length of stop bit.\n1: 1 bit. 2: 1.5 bits. 3: 2 bits." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: SW_RTS + description: This register is used to configure the software RTS signal which is used in software flow control. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SW_DTR + description: This register is used to configure the software DTR signal which is used in software flow control. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TXD_BRK + description: Set this bit to enable the transmitter to send NULL characters when the process of sending data is done. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: IRDA_DPLX + description: Set this bit to enable IrDA loopback mode. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: IRDA_TX_EN + description: This is the start enable bit for IrDA transmitter. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: IRDA_WCTL + description: "1: The IrDA transmitter's 11th bit is the same as 10th bit. 0: Set IrDA transmitter's 11th bit to 0." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: IRDA_TX_INV + description: Set this bit to invert the level of IrDA transmitter. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: IRDA_RX_INV + description: Set this bit to invert the level of IrDA receiver. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: LOOPBACK + description: Set this bit to enable UART loopback test mode. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TX_FLOW_EN + description: Set this bit to enable flow control function for the transmitter. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: IRDA_EN + description: Set this bit to enable IrDA protocol. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RXFIFO_RST + description: Set this bit to reset the UART RX FIFO. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: TXFIFO_RST + description: Set this bit to reset the UART TX FIFO. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RXD_INV + description: Set this bit to invert the level of UART RXD signal. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: CTS_INV + description: Set this bit to invert the level of UART CTS signal. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: DSR_INV + description: Set this bit to invert the level of UART DSR signal. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: TXD_INV + description: Set this bit to invert the level of UART TXD signal. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RTS_INV + description: Set this bit to invert the level of UART RTS signal. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: DTR_INV + description: Set this bit to invert the level of UART DTR signal. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "1: Force clock on for registers. 0: Support clock only when application writes registers." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: ERR_WR_MASK + description: "1: The receiver stops storing data into FIFO when data is wrong. 0: The receiver stores the data even if the received data is wrong." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TICK_REF_ALWAYS_ON + description: "This register is used to select the clock. \n1: APB_CLK. \n0: REF_TICK." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: MEM_CLK_EN + description: "The signal to enable UART RAM clock gating.\n1: UART RAM powers on, the data of which can be read and written.\n0: UART RAM powers down." + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: CONF1 + description: Configuration register 1 + addressOffset: 36 + size: 32 + resetValue: 49248 + fields: + - name: RXFIFO_FULL_THRHD + description: An UART_RXFIFO_FULL_INT interrupt is generated when the receiver receives more data than this register’s value. + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: TXFIFO_EMPTY_THRHD + description: "An UART_TXFIFO_EMPTY_INT interrupt is generated when the number of data bytes in TX FIFO is less than this register's value." + bitOffset: 9 + bitWidth: 9 + access: read-write + - name: RX_TOUT_FLOW_DIS + description: Set this bit to stop accumulating idle_cnt when hardware flow control works. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: RX_FLOW_EN + description: "This is the flow enable bit for UART receiver.\n1: Choose software flow control with configuring sw_rts signal. 0: Disable software flow control." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: RX_TOUT_EN + description: "This is the enable bit for UART receiver's timeout function." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LOWPULSE + description: Autobaud minimum low pulse duration register + addressOffset: 40 + size: 32 + resetValue: 1048575 + fields: + - name: MIN_CNT + description: This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate detection. + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: HIGHPULSE + description: Autobaud minimum high pulse duration register + addressOffset: 44 + size: 32 + resetValue: 1048575 + fields: + - name: MIN_CNT + description: This register stores the value of the maximum duration time for the high level pulse. It is used in baud rate detection. + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: RXD_CNT + description: Autobaud edge change count register + addressOffset: 48 + size: 32 + fields: + - name: RXD_EDGE_CNT + description: "This register stores the count of RXD edge change. It is used in baud rate detection. As baud rate registers UART_REG_LOWPULSE_MIN_CNT, UART_REG_HIGHPULSE_MIN_CNT, UART_REG_POSEDGE_MIN_CNT, and UART_REG_NEGEDGE_MIN_CNT always record the minimal value, UART_REG_RXD_EDGE_CNT indicates the statistic number of RXD edge to find out the minimal value for these baud rate registers." + bitOffset: 0 + bitWidth: 10 + access: read-only + - register: + name: FLOW_CONF + description: Software flow control configuration + addressOffset: 52 + size: 32 + fields: + - name: SW_FLOW_CON_EN + description: "Set this bit to enable software flow control. When UART receives flow control characters XON or XOFF, which can be configured by UART_XON_CHAR or UART_XOFF_CHAR respectively, UART_SW_XON_INT or UART_SW_XOFF_INT interrupts can be triggered if enabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: XONOFF_DEL + description: Set this bit to remove flow control characters from the received data. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FORCE_XON + description: Set this bit to force the transmitter to send data. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FORCE_XOFF + description: Set this bit to stop the transmitter from sending data. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SEND_XON + description: Set this bit to send an XON character. This bit is cleared by hardware automatically. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SEND_XOFF + description: Set this bit to send an XOFF character. This bit is cleared by hardware automatically. + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: SLEEP_CONF + description: Sleep mode configuration + addressOffset: 56 + size: 32 + resetValue: 240 + fields: + - name: ACTIVE_THRESHOLD + description: "The UART is activated from Light-sleep mode when the input RXD edge changes more times than this register's value." + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: SWFC_CONF0 + description: Software flow control character configuration + addressOffset: 60 + size: 32 + resetValue: 9952 + fields: + - name: XOFF_THRESHOLD + description: "When the number of data bytes in RX FIFO is more than this register's value with UART_SW_FLOW_CON_EN set to 1, the transmitter sends an XOFF character." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: XOFF_CHAR + description: This register stores the XOFF flow control character. + bitOffset: 9 + bitWidth: 8 + access: read-write + - register: + name: SWFC_CONF1 + description: Software flow-control character configuration + addressOffset: 64 + size: 32 + resetValue: 8704 + fields: + - name: XON_THRESHOLD + description: "When the number of data bytes in RX FIFO is less than this register's value with UART_SW_FLOW_CON_EN set to 1, the transmitter sends an XON character." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: XON_CHAR + description: This register stores the XON flow control character. + bitOffset: 9 + bitWidth: 8 + access: read-write + - register: + name: IDLE_CONF + description: Frame end idle time configuration + addressOffset: 68 + size: 32 + resetValue: 10748160 + fields: + - name: RX_IDLE_THRHD + description: "A frame end signal is generated when the receiver takes more time to receive one byte data than this register's value, in the unit of bit time (the time it takes to transfer one bit)." + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: TX_IDLE_NUM + description: "This register is used to configure the duration time between transfers, in the unit of bit time (the time it takes to transfer one bit)." + bitOffset: 10 + bitWidth: 10 + access: read-write + - name: TX_BRK_NUM + description: This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when UART_TXD_BRK is set to 1. + bitOffset: 20 + bitWidth: 8 + access: read-write + - register: + name: RS485_CONF + description: RS485 mode configuration + addressOffset: 72 + size: 32 + fields: + - name: RS485_EN + description: Set this bit to choose RS485 mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DL0_EN + description: Set this bit to delay the stop bit by 1 bit. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DL1_EN + description: Set this bit to delay the stop bit by 1 bit. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RS485TX_RX_EN + description: Set this bit to enable the receiver could receive data when the transmitter is transmitting data in RS485 mode. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RS485RXBY_TX_EN + description: "1: enable RS485 transmitter to send data when RS485 receiver line is busy. \n0: RS485 transmitter should not send data when its receiver is busy." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RS485_RX_DLY_NUM + description: "This register is used to delay the receiver's internal data signal." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RS485_TX_DLY_NUM + description: "This register is used to delay the transmitter's internal data signal." + bitOffset: 6 + bitWidth: 4 + access: read-write + - register: + name: AT_CMD_PRECNT + description: Pre-sequence timing configuration + addressOffset: 76 + size: 32 + resetValue: 2305 + fields: + - name: PRE_IDLE_NUM + description: "This register is used to configure the idle duration time before the first AT_CMD is received by the receiver. \nIt will not take the next data received as AT_CMD character when the duration is less than this register's value." + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_POSTCNT + description: Post-sequence timing configuration + addressOffset: 80 + size: 32 + resetValue: 2305 + fields: + - name: POST_IDLE_NUM + description: "This register is used to configure the duration time between the last AT_CMD and the next data.\nIt will not take the previous data as AT_CMD character when the duration is less than this register's value." + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_GAPTOUT + description: Timeout configuration + addressOffset: 84 + size: 32 + resetValue: 11 + fields: + - name: RX_GAP_TOUT + description: "This register is used to configure the duration time between the AT_CMD characters.\nIt will not take the data as continuous AT_CMD characters when the duration time is less than this register's value." + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_CHAR + description: AT escape sequence selection configuration + addressOffset: 88 + size: 32 + resetValue: 811 + fields: + - name: AT_CMD_CHAR + description: This register is used to configure the content of AT_CMD character. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CHAR_NUM + description: This register is used to configure the number of continuous AT_CMD characters received by the receiver. + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: MEM_CONF + description: UART threshold and allocation configuration + addressOffset: 92 + size: 32 + resetValue: 655378 + fields: + - name: RX_SIZE + description: This register is used to configure the amount of RAM allocated for RX FIFO. The default number is 128 bytes. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: TX_SIZE + description: This register is used to configure the amount of RAM allocated for TX FIFO. The default number is 128 bytes. + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: RX_FLOW_THRHD + description: This register is used to configure the maximum amount of data bytes that can be received when hardware flow control works. + bitOffset: 7 + bitWidth: 9 + access: read-write + - name: RX_TOUT_THRHD + description: "This register is used to configure the threshold time that the receiver takes to receive one byte, in the unit of bit time (the time it takes to transfer one bit).\nThe UART_RXFIFO_TOUT_INT interrupt will be triggered when the receiver takes more time to receive one byte with UART RX_TOUT_EN set to 1." + bitOffset: 16 + bitWidth: 10 + access: read-write + - name: MEM_FORCE_PD + description: Set this bit to force power down UART RAM. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PU + description: Set this bit to force power up UART RAM. + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: MEM_TX_STATUS + description: TX FIFO write and read offset address + addressOffset: 96 + size: 32 + fields: + - name: APB_TX_WADDR + description: This register stores the offset address in TX FIFO when software writes TX FIFO via APB. + bitOffset: 0 + bitWidth: 10 + access: read-only + - name: TX_RADDR + description: This register stores the offset address in TX FIFO when TX FSM reads data via Tx_FIFO_Ctrl. + bitOffset: 11 + bitWidth: 10 + access: read-only + - register: + name: MEM_RX_STATUS + description: RX FIFO write and read offset address + addressOffset: 100 + size: 32 + fields: + - name: APB_RX_RADDR + description: This register stores the offset address in RX_FIFO when software reads data from RX FIFO via APB. + bitOffset: 0 + bitWidth: 10 + access: read-only + - name: RX_WADDR + description: This register stores the offset address in RX FIFO when Rx_FIFO_Ctrl writes RX FIFO. + bitOffset: 11 + bitWidth: 10 + access: read-only + - register: + name: FSM_STATUS + description: UART transmitter and receiver status + addressOffset: 104 + size: 32 + fields: + - name: ST_URX_OUT + description: This is the status register of the receiver. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: ST_UTX_OUT + description: This is the status register of the transmitter. + bitOffset: 4 + bitWidth: 4 + access: read-only + - register: + name: POSPULSE + description: Autobaud high pulse register + addressOffset: 108 + size: 32 + resetValue: 1048575 + fields: + - name: POSEDGE_MIN_CNT + description: This register stores the minimal input clock count between two positive edges. It is used in baud rate detection. + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: NEGPULSE + description: Autobaud low pulse register + addressOffset: 112 + size: 32 + resetValue: 1048575 + fields: + - name: NEGEDGE_MIN_CNT + description: This register stores the minimal input clock count between two negative edges. It is used in baud rate detection. + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: DATE + description: UART version control register + addressOffset: 116 + size: 32 + resetValue: 403187712 + fields: + - name: DATE + description: This is the version control register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ID + description: UART ID register + addressOffset: 120 + size: 32 + resetValue: 1280 + fields: + - name: ID + description: This register is used to configure the UART_ID. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: UART1 + description: UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + baseAddress: 1061224448 + interrupt: + - name: UART1 + value: 38 + - name: UART2 + value: 39 + derivedFrom: UART0 + - name: UHCI0 + description: Universal Host Controller Interface 0 + groupName: UHCI + baseAddress: 1061240832 + addressBlock: + - offset: 0 + size: 188 + usage: registers + interrupt: + - name: UHCI0 + value: 13 + - name: UHCI1 + value: 14 + registers: + - register: + name: CONF0 + description: UHCI configuration register + addressOffset: 0 + size: 32 + resetValue: 3604736 + fields: + - name: IN_RST + description: Set this bit to reset in DMA FSM. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_RST + description: Set this bit to reset out DMA FSM. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AHBM_FIFO_RST + description: Set this bit to reset AHB interface cmdFIFO of DMA. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: AHBM_RST + description: Set this bit to reset AHB interface of DMA. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: IN_LOOP_TEST + description: Reserved. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUT_LOOP_TEST + description: Reserved. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUT_AUTO_WRBACK + description: Set this bit to enable automatic outlink writeback when all the data in TX FIFO has been transmitted. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUT_NO_RESTART_CLR + description: Reserved. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_EOF_MODE + description: "This register is used to specify the generation mode of UHCI_OUT_EOF_INT interrupt. \n1: When DMA has popped all data from FIFO.\n0: When AHB has pushed all data to FIFO." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: UART0_CE + description: Set this bit to link up UHCI and UART0. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: UART1_CE + description: Set this bit to link up UHCI and UART1. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OUTDSCR_BURST_EN + description: "This register is used to specify DMA transmit descriptor transfer mode.\n1: burst mode.\n0: byte mode." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: INDSCR_BURST_EN + description: "This register is used to specify DMA receive descriptor transfer mode.\n1: burst mode.\n0: byte mode." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: MEM_TRANS_EN + description: "1: UHCI transmitted data would be write back into DMA INFIFO." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SEPER_EN + description: Set this bit to separate the data frame using a special character. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: HEAD_EN + description: Set this bit to encode the data packet with a formatting header. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: CRC_REC_EN + description: Set this bit to enable UHCI to receive the 16 bit CRC. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: UART_IDLE_EOF_EN + description: "If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: LEN_EOF_EN + description: "If this bit is set to 1, UHCI decoder stops receiving payload data when the number of received data bytes has reached the specified value. \nThe value is payload length indicated by UCHI packet header when UHCI_HEAD_EN is 1 or the value is a configuration value when UHCI_HEAD_EN is 0. \nIf this bit is set to 0, UHCI decoder stops receiving payload data upon receiving 0xC0." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: ENCODE_CRC_EN + description: Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to the end of the payload. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "1: Force clock on for registers. 0: Support clock only when application writes registers." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: UART_RX_BRK_EOF_EN + description: "If this bit is set to 1, UHCI stops receiving payload data when a NULL frame is received by UART." + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 4 + size: 32 + fields: + - name: RX_START_INT_RAW + description: This is the interrupt raw bit for UHCI_RX_START_INT interrupt. The interrupt is triggered when a separator has been sent. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_START_INT_RAW + description: This is the interrupt raw bit for UHCI_TX_START_INT interrupt. The interrupt is triggered when DMA detects a separator. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_RAW + description: This is the interrupt raw bit for UHCI_RX_HUNG_INT interrupt. The interrupt is triggered when DMA takes more time to receive data than the configure value. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_RAW + description: This is the interrupt raw bit for UHCI_TX_HUNG_INT interrupt. The interrupt is triggered when DMA takes more time to read data from RAM than the configured value. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: IN_DONE_INT_RAW + description: This is the interrupt raw bit for UHCI_IN_DONE_INT interrupt. The interrupt is triggered when an receive descriptor is completed. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: IN_SUC_EOF_INT_RAW + description: This is the interrupt raw bit for UHCI_IN_SUC_EOF_INT interrupt. The interrupt is triggered when a data packet has been received successfully. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: IN_ERR_EOF_INT_RAW + description: This is the interrupt raw bit for UHCI_IN_ERR_EOF_INT interrupt. The interrupt is triggered when there are some errors in EOF in the receive descriptor. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUT_DONE_INT_RAW + description: This is the interrupt raw bit for UHCI_OUT_DONE_INT interrupt. The interrupt is triggered when an transmit descriptor is completed. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OUT_EOF_INT_RAW + description: "This is the interrupt raw bit for UHCI_OUT_EOF_INT interrupt. The interrupt is triggered when the current descriptor's EOF bit is 1." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: IN_DSCR_ERR_INT_RAW + description: This is the interrupt raw bit for UHCI_IN_DSCR_ERR_INT interrupt. The interrupt is triggered when there are some errors in the receive descriptor. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: OUT_DSCR_ERR_INT_RAW + description: This is the interrupt raw bit for UHCI_OUT_DSCR_ERR_INT interrupt. The interrupt is triggered when there are some errors in the transmit descriptor. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: IN_DSCR_EMPTY_INT_RAW + description: This is the interrupt raw bit for UHCI_IN_DSCR_EMPTY_INT interrupt. The interrupt is triggered when there are not enough inlinks for DMA. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: OUTLINK_EOF_ERR_INT_RAW + description: This is the interrupt raw bit for UHCI_OUTLINK_EOF_ERR_INT interrupt. The interrupt is triggered when there are some errors in EOF in the transmit descriptor. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: OUT_TOTAL_EOF_INT_RAW + description: This is the interrupt raw bit for UHCI_OUT_TOTAL_EOF_INT interrupt. The interrupt is triggered when all data in the last buffer address has been sent out. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SEND_S_REG_Q_INT_RAW + description: This is the interrupt raw bit for UHCI_SEND_S_REG_Q_INT interrupt. The interrupt is triggered when DMA has sent out a short packet using single_send mode. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SEND_A_REG_Q_INT_RAW + description: This is the interrupt raw bit for UHCI_SEND_A_REG_Q_INT interrupt. The interrupt is triggered when DMA has sent out a short packet using always_send mode. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: DMA_INFIFO_FULL_WM_INT_RAW + description: This is the interrupt raw bit for UHCI_DMA_INFIFO_FULL_WM_INT interrupt. The interrupt is triggered when the number of data bytes in DMA RX FIFO has reached the configured threshold value. + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 8 + size: 32 + fields: + - name: RX_START_INT_ST + description: This is the masked interrupt bit for UHCI_RX_START_INT interrupt when UHCI_RX_START_INT_ENA is set to 1. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_START_INT_ST + description: This is the masked interrupt bit for UHCI_TX_START_INT interrupt when UHCI_TX_START_INT_ENA is set to 1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_ST + description: This is the masked interrupt bit for UHCI_RX_HUNG_INT interrupt when UHCI_RX_HUNG_INT_ENA is set to 1. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_ST + description: This is the masked interrupt bit for UHCI_TX_HUNG_INT interrupt when UHCI_TX_HUNG_INT_ENA is set to 1. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: IN_DONE_INT_ST + description: This is the masked interrupt bit for UHCI_IN_DONE_INT interrupt when UHCI_IN_DONE_INT_ENA is set to 1. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: IN_SUC_EOF_INT_ST + description: This is the masked interrupt bit for UHCI_IN_SUC_EOF_INT interrupt when UHCI_IN_SUC_EOF_INT_ENA is set to 1. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: IN_ERR_EOF_INT_ST + description: This is the masked interrupt bit for UHCI_IN_ERR_EOF_INT interrupt when UHCI_IN_ERR_EOF_INT_ENA is set to 1. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUT_DONE_INT_ST + description: This is the masked interrupt bit for UHCI_OUT_DONE_INT interrupt when UHCI_OUT_DONE_INT_ENA is set to 1. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OUT_EOF_INT_ST + description: This is the masked interrupt bit for UHCI_OUT_EOF_INT interrupt when UHCI_OUT_EOF_INT_ENA is set to 1. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: IN_DSCR_ERR_INT_ST + description: This is the masked interrupt bit for UHCI_IN_DSCR_ERR_INT interrupt when UHCI_IN_DSCR_ERR_INT is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: OUT_DSCR_ERR_INT_ST + description: This is the masked interrupt bit for UHCI_OUT_DSCR_ERR_INT interrupt when UHCI_OUT_DSCR_ERR_INT_ENA is set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: IN_DSCR_EMPTY_INT_ST + description: This is the masked interrupt bit for UHCI_IN_DSCR_EMPTY_INT interrupt when UHCI_IN_DSCR_EMPTY_INT_ENA is set to 1. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: OUTLINK_EOF_ERR_INT_ST + description: This is the masked interrupt bit for UHCI_OUTLINK_EOF_ERR_INT interrupt when UHCI_OUTLINK_EOF_ERR_INT_ENA is set to 1. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: OUT_TOTAL_EOF_INT_ST + description: This is the masked interrupt bit for UHCI_OUT_TOTAL_EOF_INT interrupt when UHCI_OUT_TOTAL_EOF_INT_ENA is set to 1. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SEND_S_REG_Q_INT_ST + description: This is the masked interrupt bit for UHCI_SEND_S_REG_Q_INT interrupt when UHCI_SEND_S_REG_Q_INT_ENA is set to 1. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SEND_A_REG_Q_INT_ST + description: This is the masked interrupt bit for UHCI_SEND_A_REG_Q_INT interrupt when UHCI_SEND_A_REG_Q_INT_ENA is set to 1. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: DMA_INFIFO_FULL_WM_INT_ST + description: This is the masked interrupt bit for UHCI_DMA_INFIFO_FULL_WM_INT INTERRUPT when UHCI_DMA_INFIFO_FULL_WM_INT_ENA is set to 1. + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 12 + size: 32 + fields: + - name: RX_START_INT_ENA + description: This is the interrupt enable bit for UHCI_RX_START_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_START_INT_ENA + description: This is the interrupt enable bit for UHCI_TX_START_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_HUNG_INT_ENA + description: This is the interrupt enable bit for UHCI_RX_HUNG_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_HUNG_INT_ENA + description: This is the interrupt enable bit for UHCI_TX_HUNG_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: IN_DONE_INT_ENA + description: This is the interrupt enable bit for UHCI_IN_DONE_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF_INT_ENA + description: This is the interrupt enable bit for UHCI_IN_SUC_EOF_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF_INT_ENA + description: This is the interrupt enable bit for UHCI_IN_ERR_EOF_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUT_DONE_INT_ENA + description: This is the interrupt enable bit for UHCI_OUT_DONE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: OUT_EOF_INT_ENA + description: This is the interrupt enable bit for UHCI_OUT_EOF_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR_INT_ENA + description: This is the interrupt enable bit for UHCI_IN_DSCR_ERR_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR_INT_ENA + description: This is the interrupt enable bit for UHCI_OUT_DSCR_ERR_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY_INT_ENA + description: This is the interrupt enable bit for UHCI_IN_DSCR_EMPTY_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: OUTLINK_EOF_ERR_INT_ENA + description: This is the interrupt enable bit for UHCI_OUTLINK_EOF_ERR_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF_INT_ENA + description: This is the interrupt enable bit for UHCI_OUT_TOTAL_EOF_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SEND_S_REG_Q_INT_ENA + description: This is the interrupt enable bit for UHCI_SEND_S_REG_Q_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SEND_A_REG_Q_INT_ENA + description: This is the interrupt enable bit for UHCI_SEND_A_REG_Q_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DMA_INFIFO_FULL_WM_INT_ENA + description: This is the interrupt enable bit for UHCI_DMA_INFIFO_FULL_WM_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 16 + size: 32 + fields: + - name: RX_START_INT_CLR + description: Set this bit to clear UHCI_RX_START_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TX_START_INT_CLR + description: Set this bit to clear UHCI_TX_START_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_HUNG_INT_CLR + description: Set this bit to clear UHCI_RX_HUNG_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TX_HUNG_INT_CLR + description: Set this bit to clear UHCI_TX_HUNG_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: IN_DONE_INT_CLR + description: Set this bit to clear UHCI_IN_DONE_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: IN_SUC_EOF_INT_CLR + description: Set this bit to clear UHCI_IN_SUC_EOF_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: IN_ERR_EOF_INT_CLR + description: Set this bit to clear UHCI_IN_ERR_EOF_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: OUT_DONE_INT_CLR + description: Set this bit to clear UHCI_OUT_DONE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: OUT_EOF_INT_CLR + description: Set this bit to clear UHCI_OUT_EOF_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: IN_DSCR_ERR_INT_CLR + description: Set this bit to clear UHCI_IN_DSCR_ERR_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: OUT_DSCR_ERR_INT_CLR + description: Set this bit to clear UHCI_OUT_DSCR_ERR_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: IN_DSCR_EMPTY_INT_CLR + description: Set this bit to clear UHCI_IN_DSCR_EMPTY_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: OUTLINK_EOF_ERR_INT_CLR + description: Set this bit to clear UHCI_OUTLINK_EOF_ERR_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: OUT_TOTAL_EOF_INT_CLR + description: Set this bit to clear UHCI_OUT_TOTAL_EOF_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SEND_S_REG_Q_INT_CLR + description: Set this bit to clear UHCI_SEND_S_REG_Q_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SEND_A_REG_Q_INT_CLR + description: Set this bit to clear UHCI_SEND_A_REG_Q_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: DMA_INFIFO_FULL_WM_INT_CLR + description: Set this bit to clear UHCI_DMA_INFIFO_FULL_WM_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - register: + name: DMA_OUT_STATUS + description: DMA data-output status register + addressOffset: 20 + size: 32 + resetValue: 2 + fields: + - name: OUT_FULL + description: "1: DMA TX FIFO is full." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUT_EMPTY + description: "1: DMA TX FIFO is empty." + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: DMA_OUT_PUSH + description: Push control register of TX FIFO + addressOffset: 24 + size: 32 + fields: + - name: OUTFIFO_WDATA + description: This is the data that need to be pushed into TX FIFO. + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: OUTFIFO_PUSH + description: Set this bit to push data into TX FIFO. + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: DMA_IN_STATUS + description: UHCI data-input status register + addressOffset: 28 + size: 32 + resetValue: 2 + fields: + - name: IN_FULL + description: Data-input FIFO full signal. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: IN_EMPTY + description: Data-input FIFO empty signal. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_ERR_CAUSE + description: "This register indicates the error type when DMA has received a packet with error.\n3'b001: Checksum error in the HCI packet; \n3'b010: Sequence number error in the HCI packet;\n3'b011: CRC bit error in the HCI packet;\n3'b100: 0xC0 is found but the received HCI packet is not end;\n3'b101: 0xC0 is not found when the HCI packet has been received;\n3'b110: CRC check error." + bitOffset: 4 + bitWidth: 3 + access: read-only + - register: + name: DMA_IN_POP + description: Pop control register of RX FIFO + addressOffset: 32 + size: 32 + fields: + - name: INFIFO_RDATA + description: This register stores the data popping from RX FIFO. + bitOffset: 0 + bitWidth: 12 + access: read-only + - name: INFIFO_POP + description: Set this bit to pop data from RX FIFO. + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: DMA_OUT_LINK + description: Link descriptor address and control + addressOffset: 36 + size: 32 + fields: + - name: OUTLINK_ADDR + description: "This register is used to specify the least significant 20 bits of the first transmit descriptor's address." + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: OUTLINK_STOP + description: Set this bit to stop dealing with the transmit descriptor. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: OUTLINK_START + description: Set this bit to start a new transmit descriptor. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: OUTLINK_RESTART + description: Set this bit to restart the transmit descriptor from the last address. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: OUTLINK_PARK + description: "1: the transmit descriptor's FSM is in idle state.\n0: the transmit descriptor's FSM is working." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: DMA_IN_LINK + description: Link descriptor address and control + addressOffset: 40 + size: 32 + resetValue: 1048576 + fields: + - name: INLINK_ADDR + description: "This register is used to specify the least significant 20 bits of the first receive descriptor's address." + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: INLINK_AUTO_RET + description: "This is the enable bit to return to current receive descriptor's address, when there are some errors in current packet." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: INLINK_STOP + description: Set this bit to stop dealing with the receive descriptors. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: INLINK_START + description: Set this bit to start dealing with the receive descriptors. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: INLINK_RESTART + description: Set this bit to restart new receive descriptors. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: INLINK_PARK + description: "1: the receive descriptor's FSM is in idle state.\n0: the receive descriptor's FSM is working." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CONF1 + description: UHCI configuration register + addressOffset: 44 + size: 32 + resetValue: 51 + fields: + - name: CHECK_SUM_EN + description: This is the enable bit to check header checksum when UHCI receives a data packet. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CHECK_SEQ_EN + description: This is the enable bit to check sequence number when UHCI receives a data packet. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CRC_DISABLE + description: Set this bit to support CRC calculation. Data Integrity check present bit in UHCI packet frame should be 1. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SAVE_HEAD + description: Set this bit to save the packet header when UHCI receives a data packet. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_CHECK_SUM_RE + description: Set this bit to encode the data packet with a checksum. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TX_ACK_NUM_RE + description: Set this bit to encode the data packet with an acknowledgement when a reliable packet is to be transmit. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CHECK_OWNER + description: "1: Check the link list descriptor when link list owner is DMA controller; 0: Always check link list descriptor." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: WAIT_SW_START + description: The UHCI encoder will jump to ST_SW_WAIT status if this register is set to 1. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SW_START + description: "If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DMA_INFIFO_FULL_THRS + description: This field is used to generate the UHCI_DMA_INFIFO_FULL_WM_INT interrupt when the counter value of DMA RX FIFO exceeds the value of the register. + bitOffset: 9 + bitWidth: 12 + access: read-write + - register: + name: STATE0 + description: UHCI decoder status register + addressOffset: 48 + size: 32 + fields: + - name: INLINK_DSCR_ADDR + description: "This register stores the current receive descriptor's address." + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: IN_DSCR_STATE + description: Reserved. + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: IN_STATE + description: Reserved. + bitOffset: 20 + bitWidth: 3 + access: read-only + - name: INFIFO_CNT_DEBUG + description: This register stores the number of data bytes in RX FIFO. + bitOffset: 23 + bitWidth: 5 + access: read-only + - name: DECODE_STATE + description: UHCI decoder status. + bitOffset: 28 + bitWidth: 3 + access: read-only + - register: + name: STATE1 + description: UHCI encoder status register + addressOffset: 52 + size: 32 + fields: + - name: OUTLINK_DSCR_ADDR + description: "This register stores the current transmit descriptor's address." + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: OUT_DSCR_STATE + description: Reserved. + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: OUT_STATE + description: Reserved. + bitOffset: 20 + bitWidth: 3 + access: read-only + - name: OUTFIFO_CNT + description: This register stores the number of data bytes in TX FIFO. + bitOffset: 23 + bitWidth: 5 + access: read-only + - name: ENCODE_STATE + description: UHCI encoder status. + bitOffset: 28 + bitWidth: 3 + access: read-only + - register: + name: DMA_OUT_EOF_DES_ADDR + description: Outlink descriptor address when EOF occurs + addressOffset: 56 + size: 32 + fields: + - name: OUT_EOF_DES_ADDR + description: This register stores the address of the transmit descriptor when the EOF bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DMA_IN_SUC_EOF_DES_ADDR + description: Inlink descriptor address when EOF occurs + addressOffset: 60 + size: 32 + fields: + - name: IN_SUC_EOF_DES_ADDR + description: This register stores the address of the receive descriptor when received successful EOF. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DMA_IN_ERR_EOF_DES_ADDR + description: Inlink descriptor address when errors occur + addressOffset: 64 + size: 32 + fields: + - name: IN_ERR_EOF_DES_ADDR + description: This register stores the address of the receive descriptor when there are some errors in this descriptor. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DMA_OUT_EOF_BFR_DES_ADDR + description: Outlink descriptor address before the last transmit descriptor + addressOffset: 68 + size: 32 + fields: + - name: OUT_EOF_BFR_DES_ADDR + description: This register stores the address of the transmit descriptor before the last transmit descriptor. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: AHB_TEST + description: AHB test register + addressOffset: 72 + size: 32 + fields: + - name: AHB_TESTMODE + description: Reserved. + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: AHB_TESTADDR + description: Reserved. + bitOffset: 4 + bitWidth: 2 + access: read-write + - register: + name: DMA_IN_DSCR + description: The third word of the next receive descriptor + addressOffset: 76 + size: 32 + fields: + - name: INLINK_DSCR + description: This register stores the third word of the next receive descriptor. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DMA_IN_DSCR_BF0 + description: The third word of current receive descriptor + addressOffset: 80 + size: 32 + fields: + - name: INLINK_DSCR_BF0 + description: This register stores the third word of the current receive descriptor. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DMA_OUT_DSCR + description: The third word of the next transmit descriptor + addressOffset: 88 + size: 32 + fields: + - name: OUTLINK_DSCR + description: This register stores the third word of the next transmit descriptor. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DMA_OUT_DSCR_BF0 + description: The third word of current transmit descriptor + addressOffset: 92 + size: 32 + fields: + - name: OUTLINK_DSCR_BF0 + description: This register stores the third word of the current transmit descriptor. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: ESCAPE_CONF + description: Escape character configuration + addressOffset: 100 + size: 32 + resetValue: 51 + fields: + - name: TX_C0_ESC_EN + description: Set this bit to decode character 0xC0 when DMA receives data. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_DB_ESC_EN + description: Set this bit to decode character 0xDB when DMA receives data. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TX_11_ESC_EN + description: Set this bit to decode flow control character 0x11 when DMA receives data. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_13_ESC_EN + description: Set this bit to decode flow control character 0x13 when DMA receives data. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_C0_ESC_EN + description: Set this bit to replace 0xC0 by special characters when DMA sends data. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_DB_ESC_EN + description: Set this bit to replace 0xDB by special characters when DMA sends data. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RX_11_ESC_EN + description: Set this bit to replace flow control character 0x11 by special characters when DMA sends data. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_13_ESC_EN + description: Set this bit to replace flow control character 0x13 by special characters when DMA sends data. + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: HUNG_CONF + description: Timeout configuration + addressOffset: 104 + size: 32 + resetValue: 8456208 + fields: + - name: TXFIFO_TIMEOUT + description: This register stores the timeout value. UHCI produce the UHCI_TX_HUNG_INT interrupt when DMA takes more time to receive data. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TXFIFO_TIMEOUT_SHIFT + description: This register is used to configure the maximum tick count. + bitOffset: 8 + bitWidth: 3 + access: read-write + - name: TXFIFO_TIMEOUT_ENA + description: This is the enable bit for TX FIFO receive timeout. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RXFIFO_TIMEOUT + description: This register stores the timeout value. UHCI produce the UHCI_RX_HUNG_INT interrupt when DMA takes more time to read data from RAM. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: RXFIFO_TIMEOUT_SHIFT + description: This register is used to configure the maximum tick count. + bitOffset: 20 + bitWidth: 3 + access: read-write + - name: RXFIFO_TIMEOUT_ENA + description: This is the enable bit for DMA send timeout. + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: RX_HEAD + description: UHCI packet header register + addressOffset: 112 + size: 32 + fields: + - name: RX_HEAD + description: This register stores the header of the current received packet. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: QUICK_SENT + description: UHCI quick_sent configuration register + addressOffset: 116 + size: 32 + fields: + - name: SINGLE_SEND_NUM + description: This register is used to specify the single_send mode. + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SINGLE_SEND_EN + description: Set this bit to enable single_send mode to send short packets. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ALWAYS_SEND_NUM + description: This register is used to specify the always_send mode. + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: ALWAYS_SEND_EN + description: Set this bit to enable always_send mode to send short packets. + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: Q0_WORD0 + description: Q0_WORD0 quick_sent register + addressOffset: 120 + size: 32 + fields: + - name: SEND_Q0_WORD0 + description: This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q0_WORD1 + description: Q0_WORD1 quick_sent register + addressOffset: 124 + size: 32 + fields: + - name: SEND_Q0_WORD1 + description: This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q1_WORD0 + description: Q1_WORD0 quick_sent register + addressOffset: 128 + size: 32 + fields: + - name: SEND_Q1_WORD0 + description: This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q1_WORD1 + description: Q1_WORD1 quick_sent register + addressOffset: 132 + size: 32 + fields: + - name: SEND_Q1_WORD1 + description: This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q2_WORD0 + description: Q2_WORD0 quick_sent register + addressOffset: 136 + size: 32 + fields: + - name: SEND_Q2_WORD0 + description: This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q2_WORD1 + description: Q2_WORD1 quick_sent register + addressOffset: 140 + size: 32 + fields: + - name: SEND_Q2_WORD1 + description: This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q3_WORD0 + description: Q3_WORD0 quick_sent register + addressOffset: 144 + size: 32 + fields: + - name: SEND_Q3_WORD0 + description: This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q3_WORD1 + description: Q3_WORD1 quick_sent register + addressOffset: 148 + size: 32 + fields: + - name: SEND_Q3_WORD1 + description: This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q4_WORD0 + description: Q4_WORD0 quick_sent register + addressOffset: 152 + size: 32 + fields: + - name: SEND_Q4_WORD0 + description: This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q4_WORD1 + description: Q4_WORD1 quick_sent register + addressOffset: 156 + size: 32 + fields: + - name: SEND_Q4_WORD1 + description: This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q5_WORD0 + description: Q5_WORD0 quick_sent register + addressOffset: 160 + size: 32 + fields: + - name: SEND_Q5_WORD0 + description: This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q5_WORD1 + description: Q5_WORD1 quick_sent register + addressOffset: 164 + size: 32 + fields: + - name: SEND_Q5_WORD1 + description: This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q6_WORD0 + description: Q6_WORD0 quick_sent register + addressOffset: 168 + size: 32 + fields: + - name: SEND_Q6_WORD0 + description: This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Q6_WORD1 + description: Q6_WORD1 quick_sent register + addressOffset: 172 + size: 32 + fields: + - name: SEND_Q6_WORD1 + description: This register is used as a quick_sent register when mode is specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ESC_CONF0 + description: Escape sequence configuration register 0 + addressOffset: 176 + size: 32 + resetValue: 14474176 + fields: + - name: SEPER_CHAR + description: This register is used to define separators to encode data packets. The default value is 0xC0. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SEPER_ESC_CHAR0 + description: This register is used to define the first character of SLIP escape sequence. The default value is 0xDB. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SEPER_ESC_CHAR1 + description: This register is used to define the second character of SLIP escape sequence. The default value is 0xDC. + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: ESC_CONF1 + description: Escape sequence configuration register 1 + addressOffset: 180 + size: 32 + resetValue: 14539739 + fields: + - name: ESC_SEQ0 + description: This register is used to define a character that need to be encoded. The default value is 0xDB that used as the first character of SLIP escape sequence. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: ESC_SEQ0_CHAR0 + description: This register is used to define the first character of SLIP escape sequence. The default value is 0xDB. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: ESC_SEQ0_CHAR1 + description: This register is used to define the second character of SLIP escape sequence. The default value is 0xDD. + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: ESC_CONF2 + description: Escape sequence configuration register 2 + addressOffset: 184 + size: 32 + resetValue: 14605073 + fields: + - name: ESC_SEQ1 + description: This register is used to define a character that need to be encoded. The default value is 0x11 that used as a flow control character. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: ESC_SEQ1_CHAR0 + description: This register is used to define the first character of SLIP escape sequence. The default value is 0xDB. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: ESC_SEQ1_CHAR1 + description: This register is used to define the second character of SLIP escape sequence. The default value is 0xDE. + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: ESC_CONF3 + description: Escape sequence configuration register 3 + addressOffset: 188 + size: 32 + resetValue: 14670611 + fields: + - name: ESC_SEQ2 + description: This register is used to define a character that need to be decoded. The default value is 0x13 that used as a flow control character. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: ESC_SEQ2_CHAR0 + description: This register is used to define the first character of SLIP escape sequence. The default value is 0xDB. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: ESC_SEQ2_CHAR1 + description: This register is used to define the second character of SLIP escape sequence. The default value is 0xDF. + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: PKT_THRES + description: Configure register for packet length + addressOffset: 192 + size: 32 + resetValue: 128 + fields: + - name: PKT_THRS + description: This register is used to configure the maximum value of the packet length when UHCI_HEAD_EN is 0. + bitOffset: 0 + bitWidth: 13 + access: read-write + - register: + name: DATE + description: UHCI version control register + addressOffset: 252 + size: 32 + resetValue: 403124225 + fields: + - name: DATE + description: This is the version control register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: USB0 + description: USB OTG (On-The-Go) + groupName: USB + baseAddress: 1611137024 + addressBlock: + - offset: 0 + size: 672 + usage: registers + interrupt: + - name: USB + value: 48 + registers: + - register: + name: GOTGCTL + addressOffset: 0 + size: 32 + fields: + - name: SESREQSCS + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SESREQ + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: VBVALIDOVEN + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: VBVALIDOVVAL + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: AVALIDOVEN + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: AVALIDOVVAL + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BVALIDOVEN + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BVALIDOVVAL + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: HSTNEGSCS + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: HNPREQ + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: HSTSETHNPEN + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DEVHNPEN + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: EHEN + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DBNCEFLTRBYPASS + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CONIDSTS + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: DBNCTIME + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: ASESVLD + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: BSESVLD + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: OTGVER + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CURMOD + bitOffset: 21 + bitWidth: 1 + access: read-only + - register: + name: GOTGINT + addressOffset: 4 + size: 32 + fields: + - name: SESENDDET + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SESREQSUCSTSCHNG + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: HSTNEGSUCSTSCHNG + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: HSTNEGDET + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: ADEVTOUTCHG + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: DBNCEDONE + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: GAHBCFG + addressOffset: 8 + size: 32 + fields: + - name: GLBLLNTRMSK + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: HBSTLEN + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: DMAEN + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: NPTXFEMPLVL + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: PTXFEMPLVL + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REMMEMSUPP + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: NOTIALLDMAWRIT + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: AHBSINGLE + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: INVDESCENDIANESS + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: GUSBCFG + addressOffset: 12 + size: 32 + resetValue: 5184 + fields: + - name: TOUTCAL + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: PHYIF + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ULPI_UTMI_SEL + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: FSINTF + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: PHYSEL + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SRPCAP + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: HNPCAP + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: USBTRDTIM + bitOffset: 10 + bitWidth: 4 + access: read-write + - name: TERMSELDLPULSE + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TXENDDELAY + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: FORCEHSTMODE + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: FORCEDEVMODE + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CORRUPTTXPKT + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: GRSTCTL + addressOffset: 16 + size: 32 + fields: + - name: CSFTRST + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PIUFSSFTRST + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FRMCNTRRST + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RXFFLSH + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TXFFLSH + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TXFNUM + bitOffset: 6 + bitWidth: 5 + access: read-write + - name: DMAREQ + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: AHBIDLE + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: GINTSTS + addressOffset: 20 + size: 32 + fields: + - name: CURMOD_INT + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: MODEMIS + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OTGINT + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SOF + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RXFLVI + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: NPTXFEMP + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: GINNAKEFF + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: GOUTNAKEFF + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: ERLYSUSP + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: USBSUSP + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: USBRST + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: ENUMDONE + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: ISOOUTDROP + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: EOPF + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: EPMIS + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: IEPINT + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: OEPINT + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: INCOMPISOIN + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: INCOMPIP + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: FETSUSP + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RESETDET + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: PRTLNT + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: HCHLNT + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: PTXFEMP + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: CONIDSTSCHNG + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DISCONNINT + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SESSREQINT + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: WKUPINT + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: GINTMSK + addressOffset: 24 + size: 32 + fields: + - name: MODEMISMSK + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OTGINTMSK + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SOFMSK + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RXFLVIMSK + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: NPTXFEMPMSK + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: GINNAKEFFMSK + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: GOUTNACKEFFMSK + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: ERLYSUSPMSK + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: USBSUSPMSK + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: USBRSTMSK + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: ENUMDONEMSK + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: ISOOUTDROPMSK + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: EOPFMSK + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: EPMISMSK + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: IEPINTMSK + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: OEPINTMSK + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: INCOMPISOINMSK + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: INCOMPIPMSK + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: FETSUSPMSK + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RESETDETMSK + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: PRTLNTMSK + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: HCHINTMSK + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PTXFEMPMSK + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CONIDSTSCHNGMSK + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DISCONNINTMSK + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SESSREQINTMSK + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: WKUPINTMSK + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: GRXSTSR + addressOffset: 28 + size: 32 + fields: + - name: G_CHNUM + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: G_BCNT + bitOffset: 4 + bitWidth: 11 + access: read-only + - name: G_DPID + bitOffset: 15 + bitWidth: 2 + access: read-only + - name: G_PKTSTS + bitOffset: 17 + bitWidth: 4 + access: read-only + - name: G_FN + bitOffset: 21 + bitWidth: 4 + access: read-only + - register: + name: GRXSTSP + addressOffset: 32 + size: 32 + fields: + - name: CHNUM + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: BCNT + bitOffset: 4 + bitWidth: 11 + access: read-only + - name: DPID + bitOffset: 15 + bitWidth: 2 + access: read-only + - name: PKTSTS + bitOffset: 17 + bitWidth: 4 + access: read-only + - name: FN + bitOffset: 21 + bitWidth: 4 + access: read-only + - register: + name: GRXFSIZ + addressOffset: 36 + size: 32 + resetValue: 256 + fields: + - name: RXFDEP + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: GNPTXFSIZ + addressOffset: 40 + size: 32 + resetValue: 16777472 + fields: + - name: NPTXFSTADDR + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: NPTXFDEP + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: GNPTXSTS + addressOffset: 44 + size: 32 + resetValue: 262400 + fields: + - name: NPTXFSPCAVAIL + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: NPTXQSPCAVAIL + bitOffset: 16 + bitWidth: 4 + access: read-only + - name: NPTXQTOP + bitOffset: 24 + bitWidth: 7 + access: read-only + - register: + name: GSNPSID + addressOffset: 64 + size: 32 + resetValue: 1330921482 + fields: + - name: SYNOPSYSID + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: GHWCFG1 + addressOffset: 68 + size: 32 + fields: + - name: EPDIR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: GHWCFG2 + addressOffset: 72 + size: 32 + resetValue: 575527216 + fields: + - name: OTGMODE + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: OTGARCH + bitOffset: 3 + bitWidth: 2 + access: read-only + - name: SINGPNT + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: HSPHYTYPE + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: FSPHYTYPE + bitOffset: 8 + bitWidth: 2 + access: read-only + - name: NUMDEVEPS + bitOffset: 10 + bitWidth: 4 + access: read-only + - name: NUMHSTCHNL + bitOffset: 14 + bitWidth: 4 + access: read-only + - name: PERIOSUPPORT + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: DYNFIFOSIZING + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: MULTIPROCINTRPT + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: NPTXQDEPTH + bitOffset: 22 + bitWidth: 2 + access: read-only + - name: PTXQDEPTH + bitOffset: 24 + bitWidth: 2 + access: read-only + - name: TKNQDEPTH + bitOffset: 26 + bitWidth: 5 + access: read-only + - name: OTG_ENABLE_IC_USB + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: GHWCFG3 + addressOffset: 76 + size: 32 + resetValue: 16778421 + fields: + - name: XFERSIZEWIDTH + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: PKTSIZEWIDTH + bitOffset: 4 + bitWidth: 3 + access: read-only + - name: OTGEN + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: I2CINTSEL + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: VNDCTLSUPT + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: OPTFEATURE + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: RSTTYPE + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: ADPSUPPORT + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: HSICMODE + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: BCSUPPORT + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: LPMMODE + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: DFIFODEPTH + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: GHWCFG4 + addressOffset: 80 + size: 32 + resetValue: 3555762224 + fields: + - name: G_NUMDEVPERIOEPS + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: G_PARTIALPWRDN + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: G_AHBFREQ + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: G_HIBERNATION + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: G_EXTENDEDHIBERNATION + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: G_ACGSUPT + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: G_ENHANCEDLPMSUPT + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: G_PHYDATAWIDTH + bitOffset: 14 + bitWidth: 2 + access: read-only + - name: G_NUMCTLEPS + bitOffset: 16 + bitWidth: 4 + access: read-only + - name: G_IDDQFLTR + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: G_VBUSVALIDFLTR + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: G_AVALIDFLTR + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: G_BVALIDFLTR + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: G_SESSENDFLTR + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: G_DEDFIFOMODE + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: G_INEPS + bitOffset: 26 + bitWidth: 4 + access: read-only + - name: G_DESCDMAENABLED + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: G_DESCDMA + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: GDFIFOCFG + addressOffset: 92 + size: 32 + fields: + - name: GDFIFOCFG + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: EPINFOBASEADDR + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: HPTXFSIZ + addressOffset: 256 + size: 32 + resetValue: 268435968 + fields: + - name: PTXFSTADDR + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: PTXFSIZE + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: DIEPTXF1 + addressOffset: 260 + size: 32 + resetValue: 268435968 + fields: + - name: INEP1TXFSTADDR + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: INEP1TXFDEP + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: DIEPTXF2 + addressOffset: 264 + size: 32 + resetValue: 268435968 + fields: + - name: INEP2TXFSTADDR + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: INEP2TXFDEP + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: DIEPTXF3 + addressOffset: 268 + size: 32 + resetValue: 268435968 + fields: + - name: INEP3TXFSTADDR + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: INEP3TXFDEP + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: DIEPTXF4 + addressOffset: 272 + size: 32 + resetValue: 268435968 + fields: + - name: INEP4TXFSTADDR + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: INEP4TXFDEP + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: HCFG + addressOffset: 1024 + size: 32 + fields: + - name: H_FSLSPCLKSEL + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: H_FSLSSUPP + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_ENA32KHZS + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_DESCDMA + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: H_FRLISTEN + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: H_PERSCHEDENA + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: H_MODECHTIMEN + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HFIR + addressOffset: 1028 + size: 32 + resetValue: 6103 + fields: + - name: FRINT + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: HFIRRLDCTRL + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: HFNUM + addressOffset: 1032 + size: 32 + resetValue: 16383 + fields: + - name: FRNUM + bitOffset: 0 + bitWidth: 14 + access: read-only + - name: FRREM + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: HPTXSTS + addressOffset: 1040 + size: 32 + resetValue: 524544 + fields: + - name: PTXFSPCAVAIL + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: PTXQSPCAVAIL + bitOffset: 16 + bitWidth: 5 + access: read-only + - name: PTXQTOP + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: HAINT + addressOffset: 1044 + size: 32 + fields: + - name: HAINT + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: HAINTMSK + addressOffset: 1048 + size: 32 + fields: + - name: HAINTMSK + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: HFLBADDR + addressOffset: 1052 + size: 32 + fields: + - name: HFLBADDR + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HPRT + addressOffset: 1088 + size: 32 + fields: + - name: PRTCONNSTS + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PRTCONNDET + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PRTENA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PRTENCHNG + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PRTOVRCURRACT + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: PRTOVRCURRCHNG + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: PRTRES + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: PRTSUSP + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: PRTRST + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: PRTLNSTS + bitOffset: 10 + bitWidth: 2 + access: read-only + - name: PRTPWR + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PRTTSTCTL + bitOffset: 13 + bitWidth: 4 + access: read-write + - name: PRTSPD + bitOffset: 17 + bitWidth: 2 + access: read-only + - register: + name: HCCHAR0 + addressOffset: 1280 + size: 32 + fields: + - name: H_MPS0 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: H_EPNUM0 + bitOffset: 11 + bitWidth: 4 + access: read-write + - name: H_EPDIR0 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: H_LSPDDEV0 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: H_EPTYPE0 + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: H_EC0 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: H_DEVADDR0 + bitOffset: 22 + bitWidth: 7 + access: read-write + - name: H_ODDFRM0 + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: H_CHDIS0 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: H_CHENA0 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCINT0 + addressOffset: 1288 + size: 32 + fields: + - name: H_XFERCOMPL0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTD0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERR0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALL0 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NACK0 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACK0 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYET0 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERR0 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERR0 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUN0 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERR0 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTR0 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_XCS_XACT_ERR0 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTR0 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCINTMSK0 + addressOffset: 1292 + size: 32 + fields: + - name: H_XFERCOMPLMSK0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTDMSK0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERRMSK0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALLMSK0 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NAKMSK0 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACKMSK0 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYETMSK0 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERRMSK0 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERRMSK0 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUNMSK0 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERRMSK0 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTRMSK0 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTRMSK0 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCTSIZ0 + addressOffset: 1296 + size: 32 + fields: + - name: H_XFERSIZE0 + bitOffset: 0 + bitWidth: 19 + access: read-write + - name: H_PKTCNT0 + bitOffset: 19 + bitWidth: 10 + access: read-write + - name: H_PID0 + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: H_DOPNG0 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCDMA0 + addressOffset: 1300 + size: 32 + fields: + - name: H_DMAADDR0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HCDMAB0 + addressOffset: 1308 + size: 32 + fields: + - name: H_HCDMAB0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HCCHAR1 + addressOffset: 1312 + size: 32 + fields: + - name: H_MPS1 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: H_EPNUM1 + bitOffset: 11 + bitWidth: 4 + access: read-write + - name: H_EPDIR1 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: H_LSPDDEV1 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: H_EPTYPE1 + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: H_EC1 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: H_DEVADDR1 + bitOffset: 22 + bitWidth: 7 + access: read-write + - name: H_ODDFRM1 + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: H_CHDIS1 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: H_CHENA1 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCINT1 + addressOffset: 1320 + size: 32 + fields: + - name: H_XFERCOMPL1 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTD1 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERR1 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALL1 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NACK1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACK1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYET1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERR1 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERR1 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUN1 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERR1 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTR1 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_XCS_XACT_ERR1 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTR1 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCINTMSK1 + addressOffset: 1324 + size: 32 + fields: + - name: H_XFERCOMPLMSK1 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTDMSK1 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERRMSK1 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALLMSK1 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NAKMSK1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACKMSK1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYETMSK1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERRMSK1 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERRMSK1 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUNMSK1 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERRMSK1 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTRMSK1 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTRMSK1 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCTSIZ1 + addressOffset: 1328 + size: 32 + fields: + - name: H_XFERSIZE1 + bitOffset: 0 + bitWidth: 19 + access: read-write + - name: H_PKTCNT1 + bitOffset: 19 + bitWidth: 10 + access: read-write + - name: H_PID1 + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: H_DOPNG1 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCDMA1 + addressOffset: 1332 + size: 32 + fields: + - name: H_DMAADDR1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HCDMAB1 + addressOffset: 1340 + size: 32 + fields: + - name: H_HCDMAB1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HCCHAR2 + addressOffset: 1344 + size: 32 + fields: + - name: H_MPS2 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: H_EPNUM2 + bitOffset: 11 + bitWidth: 4 + access: read-write + - name: H_EPDIR2 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: H_LSPDDEV2 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: H_EPTYPE2 + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: H_EC2 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: H_DEVADDR2 + bitOffset: 22 + bitWidth: 7 + access: read-write + - name: H_ODDFRM2 + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: H_CHDIS2 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: H_CHENA2 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCINT2 + addressOffset: 1352 + size: 32 + fields: + - name: H_XFERCOMPL2 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTD2 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERR2 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALL2 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NACK2 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACK2 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYET2 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERR2 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERR2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUN2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERR2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTR2 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_XCS_XACT_ERR2 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTR2 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCINTMSK2 + addressOffset: 1356 + size: 32 + fields: + - name: H_XFERCOMPLMSK2 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTDMSK2 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERRMSK2 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALLMSK2 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NAKMSK2 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACKMSK2 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYETMSK2 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERRMSK2 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERRMSK2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUNMSK2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERRMSK2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTRMSK2 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTRMSK2 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCTSIZ2 + addressOffset: 1360 + size: 32 + fields: + - name: H_XFERSIZE2 + bitOffset: 0 + bitWidth: 19 + access: read-write + - name: H_PKTCNT2 + bitOffset: 19 + bitWidth: 10 + access: read-write + - name: H_PID2 + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: H_DOPNG2 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCDMA2 + addressOffset: 1364 + size: 32 + fields: + - name: H_DMAADDR2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HCDMAB2 + addressOffset: 1372 + size: 32 + fields: + - name: H_HCDMAB2 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HCCHAR3 + addressOffset: 1376 + size: 32 + fields: + - name: H_MPS3 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: H_EPNUM3 + bitOffset: 11 + bitWidth: 4 + access: read-write + - name: H_EPDIR3 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: H_LSPDDEV3 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: H_EPTYPE3 + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: H_EC3 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: H_DEVADDR3 + bitOffset: 22 + bitWidth: 7 + access: read-write + - name: H_ODDFRM3 + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: H_CHDIS3 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: H_CHENA3 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCINT3 + addressOffset: 1384 + size: 32 + fields: + - name: H_XFERCOMPL3 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTD3 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERR3 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALL3 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NACK3 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACK3 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYET3 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERR3 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERR3 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUN3 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERR3 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTR3 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_XCS_XACT_ERR3 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTR3 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCINTMSK3 + addressOffset: 1388 + size: 32 + fields: + - name: H_XFERCOMPLMSK3 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTDMSK3 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERRMSK3 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALLMSK3 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NAKMSK3 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACKMSK3 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYETMSK3 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERRMSK3 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERRMSK3 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUNMSK3 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERRMSK3 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTRMSK3 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTRMSK3 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCTSIZ3 + addressOffset: 1392 + size: 32 + fields: + - name: H_XFERSIZE3 + bitOffset: 0 + bitWidth: 19 + access: read-write + - name: H_PKTCNT3 + bitOffset: 19 + bitWidth: 10 + access: read-write + - name: H_PID3 + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: H_DOPNG3 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCDMA3 + addressOffset: 1396 + size: 32 + fields: + - name: H_DMAADDR3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HCDMAB3 + addressOffset: 1404 + size: 32 + fields: + - name: H_HCDMAB3 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HCCHAR4 + addressOffset: 1408 + size: 32 + fields: + - name: H_MPS4 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: H_EPNUM4 + bitOffset: 11 + bitWidth: 4 + access: read-write + - name: H_EPDIR4 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: H_LSPDDEV4 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: H_EPTYPE4 + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: H_EC4 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: H_DEVADDR4 + bitOffset: 22 + bitWidth: 7 + access: read-write + - name: H_ODDFRM4 + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: H_CHDIS4 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: H_CHENA4 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCINT4 + addressOffset: 1416 + size: 32 + fields: + - name: H_XFERCOMPL4 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTD4 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERR4 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALL4 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NACK4 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACK4 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYET4 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERR4 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERR4 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUN4 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERR4 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTR4 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_XCS_XACT_ERR4 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTR4 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCINTMSK4 + addressOffset: 1420 + size: 32 + fields: + - name: H_XFERCOMPLMSK4 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTDMSK4 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERRMSK4 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALLMSK4 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NAKMSK4 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACKMSK4 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYETMSK4 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERRMSK4 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERRMSK4 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUNMSK4 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERRMSK4 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTRMSK4 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTRMSK4 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCTSIZ4 + addressOffset: 1424 + size: 32 + fields: + - name: H_XFERSIZE4 + bitOffset: 0 + bitWidth: 19 + access: read-write + - name: H_PKTCNT4 + bitOffset: 19 + bitWidth: 10 + access: read-write + - name: H_PID4 + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: H_DOPNG4 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCDMA4 + addressOffset: 1428 + size: 32 + fields: + - name: H_DMAADDR4 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HCDMAB4 + addressOffset: 1436 + size: 32 + fields: + - name: H_HCDMAB4 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HCCHAR5 + addressOffset: 1440 + size: 32 + fields: + - name: H_MPS5 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: H_EPNUM5 + bitOffset: 11 + bitWidth: 4 + access: read-write + - name: H_EPDIR5 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: H_LSPDDEV5 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: H_EPTYPE5 + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: H_EC5 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: H_DEVADDR5 + bitOffset: 22 + bitWidth: 7 + access: read-write + - name: H_ODDFRM5 + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: H_CHDIS5 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: H_CHENA5 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCINT5 + addressOffset: 1448 + size: 32 + fields: + - name: H_XFERCOMPL5 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTD5 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERR5 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALL5 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NACK5 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACK5 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYET5 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERR5 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERR5 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUN5 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERR5 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTR5 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_XCS_XACT_ERR5 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTR5 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCINTMSK5 + addressOffset: 1452 + size: 32 + fields: + - name: H_XFERCOMPLMSK5 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTDMSK5 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERRMSK5 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALLMSK5 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NAKMSK5 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACKMSK5 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYETMSK5 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERRMSK5 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERRMSK5 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUNMSK5 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERRMSK5 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTRMSK5 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTRMSK5 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCTSIZ5 + addressOffset: 1456 + size: 32 + fields: + - name: H_XFERSIZE5 + bitOffset: 0 + bitWidth: 19 + access: read-write + - name: H_PKTCNT5 + bitOffset: 19 + bitWidth: 10 + access: read-write + - name: H_PID5 + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: H_DOPNG5 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCDMA5 + addressOffset: 1460 + size: 32 + fields: + - name: H_DMAADDR5 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HCDMAB5 + addressOffset: 1468 + size: 32 + fields: + - name: H_HCDMAB5 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HCCHAR6 + addressOffset: 1472 + size: 32 + fields: + - name: H_MPS6 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: H_EPNUM6 + bitOffset: 11 + bitWidth: 4 + access: read-write + - name: H_EPDIR6 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: H_LSPDDEV6 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: H_EPTYPE6 + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: H_EC6 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: H_DEVADDR6 + bitOffset: 22 + bitWidth: 7 + access: read-write + - name: H_ODDFRM6 + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: H_CHDIS6 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: H_CHENA6 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCINT6 + addressOffset: 1480 + size: 32 + fields: + - name: H_XFERCOMPL6 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTD6 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERR6 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALL6 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NACK6 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACK6 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYET6 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERR6 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERR6 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUN6 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERR6 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTR6 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_XCS_XACT_ERR6 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTR6 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCINTMSK6 + addressOffset: 1484 + size: 32 + fields: + - name: H_XFERCOMPLMSK6 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTDMSK6 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERRMSK6 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALLMSK6 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NAKMSK6 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACKMSK6 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYETMSK6 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERRMSK6 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERRMSK6 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUNMSK6 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERRMSK6 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTRMSK6 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTRMSK6 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCTSIZ6 + addressOffset: 1488 + size: 32 + fields: + - name: H_XFERSIZE6 + bitOffset: 0 + bitWidth: 19 + access: read-write + - name: H_PKTCNT6 + bitOffset: 19 + bitWidth: 10 + access: read-write + - name: H_PID6 + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: H_DOPNG6 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCDMA6 + addressOffset: 1492 + size: 32 + fields: + - name: H_DMAADDR6 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HCDMAB6 + addressOffset: 1500 + size: 32 + fields: + - name: H_HCDMAB6 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HCCHAR7 + addressOffset: 1504 + size: 32 + fields: + - name: H_MPS7 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: H_EPNUM7 + bitOffset: 11 + bitWidth: 4 + access: read-write + - name: H_EPDIR7 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: H_LSPDDEV7 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: H_EPTYPE7 + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: H_EC7 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: H_DEVADDR7 + bitOffset: 22 + bitWidth: 7 + access: read-write + - name: H_ODDFRM7 + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: H_CHDIS7 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: H_CHENA7 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCINT7 + addressOffset: 1512 + size: 32 + fields: + - name: H_XFERCOMPL7 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTD7 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERR7 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALL7 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NACK7 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACK7 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYET7 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERR7 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERR7 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUN7 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERR7 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTR7 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_XCS_XACT_ERR7 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTR7 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCINTMSK7 + addressOffset: 1516 + size: 32 + fields: + - name: H_XFERCOMPLMSK7 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTDMSK7 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERRMSK7 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALLMSK7 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NAKMSK7 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACKMSK7 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYETMSK7 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERRMSK7 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERRMSK7 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUNMSK7 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERRMSK7 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTRMSK7 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTRMSK7 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCTSIZ7 + addressOffset: 1520 + size: 32 + fields: + - name: H_XFERSIZE7 + bitOffset: 0 + bitWidth: 19 + access: read-write + - name: H_PKTCNT7 + bitOffset: 19 + bitWidth: 10 + access: read-write + - name: H_PID7 + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: H_DOPNG7 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCDMA7 + addressOffset: 1524 + size: 32 + fields: + - name: H_DMAADDR7 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HCDMAB7 + addressOffset: 1532 + size: 32 + fields: + - name: H_HCDMAB7 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DCFG + addressOffset: 2048 + size: 32 + resetValue: 135266304 + fields: + - name: NZSTSOUTHSHK + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ENA32KHZSUSP + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DEVADDR + bitOffset: 4 + bitWidth: 7 + access: read-write + - name: PERFRLINT + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: ENDEVOUTNAK + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: XCVRDLY + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: ERRATICINTMSK + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: EPMISCNT + bitOffset: 18 + bitWidth: 5 + access: read-write + - name: DESCDMA + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: PERSCHINTVL + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: RESVALID + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: DCTL + addressOffset: 2052 + size: 32 + resetValue: 8192 + fields: + - name: RMTWKUPSIG + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SFTDISCON + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: GNPINNAKSTS + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: GOUTNAKSTS + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TSTCTL + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: SGNPINNAK + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: CGNPINNAK + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SGOUTNAK + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: CGOUTNAK + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: PWRONPRGDONE + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: GMC + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: IGNRFRMNUM + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: NAKONBBLE + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ENCOUNTONBNA + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: DEEPSLEEPBESLREJECT + bitOffset: 18 + bitWidth: 1 + access: read-write + - register: + name: DSTS + addressOffset: 2056 + size: 32 + resetValue: 2 + fields: + - name: SUSPSTS + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ENUMSPD + bitOffset: 1 + bitWidth: 2 + access: read-only + - name: ERRTICERR + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SOFFN + bitOffset: 8 + bitWidth: 14 + access: read-only + - name: DEVLNSTS + bitOffset: 22 + bitWidth: 2 + access: read-only + - register: + name: DIEPMSK + addressOffset: 2064 + size: 32 + fields: + - name: DI_XFERCOMPLMSK + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DI_EPDISBLDMSK + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DI_AHBERMSK + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TIMEOUTMSK + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: INTKNTXFEMPMSK + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: INTKNEPMISMSK + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: INEPNAKEFFMSK + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TXFIFOUNDRNMSK + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BNAININTRMSK + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DI_NAKMSK + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: DOEPMSK + addressOffset: 2068 + size: 32 + fields: + - name: XFERCOMPLMSK + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EPDISBLDMSK + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AHBERMSK + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SETUPMSK + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTTKNEPDISMSK + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: STSPHSERCVDMSK + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BACK2BACKSETUP + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTPKTERRMSK + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BNAOUTINTRMSK + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: BBLEERRMSK + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: NAKMSK + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: NYETMSK + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DAINT + addressOffset: 2072 + size: 32 + fields: + - name: INEPINT0 + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: INEPINT1 + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: INEPINT2 + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: INEPINT3 + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: INEPINT4 + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: INEPINT5 + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: INEPINT6 + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUTEPINT0 + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: OUTEPINT1 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: OUTEPINT2 + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: OUTEPINT3 + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: OUTEPINT4 + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: OUTEPINT5 + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: OUTEPINT6 + bitOffset: 22 + bitWidth: 1 + access: read-only + - register: + name: DAINTMSK + addressOffset: 2076 + size: 32 + fields: + - name: INEPMSK0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: INEPMSK1 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: INEPMSK2 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INEPMSK3 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: INEPMSK4 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: INEPMSK5 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: INEPMSK6 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTEPMSK0 + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: OUTEPMSK1 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: OUTEPMSK2 + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: OUTEPMSK3 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: OUTEPMSK4 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: OUTEPMSK5 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: OUTEPMSK6 + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: DVBUSDIS + addressOffset: 2088 + size: 32 + resetValue: 6103 + fields: + - name: DVBUSDIS + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: DVBUSPULSE + addressOffset: 2092 + size: 32 + resetValue: 1464 + fields: + - name: DVBUSPULSE + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: DTHRCTL + addressOffset: 2096 + size: 32 + resetValue: 134348832 + fields: + - name: NONISOTHREN + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ISOTHREN + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TXTHRLEN + bitOffset: 2 + bitWidth: 9 + access: read-write + - name: AHBTHRRATIO + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: RXTHREN + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RXTHRLEN + bitOffset: 17 + bitWidth: 9 + access: read-write + - name: ARBPRKEN + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: DIEPEMPMSK + addressOffset: 2100 + size: 32 + fields: + - name: D_INEPTXFEMPMSK + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: DIEPCTL0 + addressOffset: 2304 + size: 32 + resetValue: 32768 + fields: + - name: D_MPS0 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: D_USBACTEP0 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: D_NAKSTS0 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: D_EPTYPE0 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: D_STALL0 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: D_TXFNUM0 + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: D_CNAK0 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DI_SNAK0 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: D_EPDIS0 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: D_EPENA0 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DIEPINT0 + addressOffset: 2312 + size: 32 + fields: + - name: D_XFERCOMPL0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: D_EPDISBLD0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: D_AHBERR0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: D_TIMEOUT0 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: D_INTKNTXFEMP0 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: D_INTKNEPMIS0 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: D_INEPNAKEFF0 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: D_TXFEMP0 + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: D_TXFIFOUNDRN0 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: D_BNAINTR0 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: D_PKTDRPSTS0 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: D_BBLEERR0 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: D_NAKINTRPT0 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: D_NYETINTRPT0 + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DIEPTSIZ0 + addressOffset: 2320 + size: 32 + fields: + - name: D_XFERSIZE0 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: D_PKTCNT0 + bitOffset: 19 + bitWidth: 2 + access: read-write + - register: + name: DIEPDMA0 + addressOffset: 2324 + size: 32 + fields: + - name: D_DMAADDR0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DTXFSTS0 + addressOffset: 2328 + size: 32 + fields: + - name: D_INEPTXFSPCAVAIL0 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: DIEPDMAB0 + addressOffset: 2332 + size: 32 + fields: + - name: D_DMABUFFERADDR0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DIEPCTL1 + addressOffset: 2336 + size: 32 + resetValue: 32768 + fields: + - name: D_MPS1 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: D_USBACTEP1 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: D_NAKSTS1 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: D_EPTYPE1 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: D_STALL1 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: D_TXFNUM1 + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: D_CNAK1 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DI_SNAK1 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: DI_SETD0PID1 + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DI_SETD1PID1 + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: D_EPDIS1 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: D_EPENA1 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DIEPINT1 + addressOffset: 2344 + size: 32 + fields: + - name: D_XFERCOMPL1 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: D_EPDISBLD1 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: D_AHBERR1 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: D_TIMEOUT1 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: D_INTKNTXFEMP1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: D_INTKNEPMIS1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: D_INEPNAKEFF1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: D_TXFEMP1 + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: D_TXFIFOUNDRN1 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: D_BNAINTR1 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: D_PKTDRPSTS1 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: D_BBLEERR1 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: D_NAKINTRPT1 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: D_NYETINTRPT1 + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DIEPTSIZ1 + addressOffset: 2352 + size: 32 + fields: + - name: D_XFERSIZE1 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: D_PKTCNT1 + bitOffset: 19 + bitWidth: 2 + access: read-write + - register: + name: DIEPDMA1 + addressOffset: 2356 + size: 32 + fields: + - name: D_DMAADDR1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DTXFSTS1 + addressOffset: 2360 + size: 32 + fields: + - name: D_INEPTXFSPCAVAIL1 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: DIEPDMAB1 + addressOffset: 2364 + size: 32 + fields: + - name: D_DMABUFFERADDR1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DIEPCTL2 + addressOffset: 2368 + size: 32 + resetValue: 32768 + fields: + - name: D_MPS2 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: D_USBACTEP2 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: D_NAKSTS2 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: D_EPTYPE2 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: D_STALL2 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: D_TXFNUM2 + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: D_CNAK2 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DI_SNAK2 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: DI_SETD0PID2 + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DI_SETD1PID2 + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: D_EPDIS2 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: D_EPENA2 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DIEPINT2 + addressOffset: 2376 + size: 32 + fields: + - name: D_XFERCOMPL2 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: D_EPDISBLD2 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: D_AHBERR2 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: D_TIMEOUT2 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: D_INTKNTXFEMP2 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: D_INTKNEPMIS2 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: D_INEPNAKEFF2 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: D_TXFEMP2 + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: D_TXFIFOUNDRN2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: D_BNAINTR2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: D_PKTDRPSTS2 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: D_BBLEERR2 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: D_NAKINTRPT2 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: D_NYETINTRPT2 + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DIEPTSIZ2 + addressOffset: 2384 + size: 32 + fields: + - name: D_XFERSIZE2 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: D_PKTCNT2 + bitOffset: 19 + bitWidth: 2 + access: read-write + - register: + name: DIEPDMA2 + addressOffset: 2388 + size: 32 + fields: + - name: D_DMAADDR2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DTXFSTS2 + addressOffset: 2392 + size: 32 + fields: + - name: D_INEPTXFSPCAVAIL2 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: DIEPDMAB2 + addressOffset: 2396 + size: 32 + fields: + - name: D_DMABUFFERADDR2 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DIEPCTL3 + addressOffset: 2400 + size: 32 + resetValue: 32768 + fields: + - name: DI_MPS3 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DI_USBACTEP3 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: DI_NAKSTS3 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: DI_EPTYPE3 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: DI_STALL3 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: DI_TXFNUM3 + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: DI_CNAK3 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DI_SNAK3 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: DI_SETD0PID3 + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DI_SETD1PID3 + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: DI_EPDIS3 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DI_EPENA3 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DIEPINT3 + addressOffset: 2408 + size: 32 + fields: + - name: D_XFERCOMPL3 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: D_EPDISBLD3 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: D_AHBERR3 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: D_TIMEOUT3 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: D_INTKNTXFEMP3 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: D_INTKNEPMIS3 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: D_INEPNAKEFF3 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: D_TXFEMP3 + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: D_TXFIFOUNDRN3 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: D_BNAINTR3 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: D_PKTDRPSTS3 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: D_BBLEERR3 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: D_NAKINTRPT3 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: D_NYETINTRPT3 + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DIEPTSIZ3 + addressOffset: 2416 + size: 32 + fields: + - name: D_XFERSIZE3 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: D_PKTCNT3 + bitOffset: 19 + bitWidth: 2 + access: read-write + - register: + name: DIEPDMA3 + addressOffset: 2420 + size: 32 + fields: + - name: D_DMAADDR3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DTXFSTS3 + addressOffset: 2424 + size: 32 + fields: + - name: D_INEPTXFSPCAVAIL3 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: DIEPDMAB3 + addressOffset: 2428 + size: 32 + fields: + - name: D_DMABUFFERADDR3 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DIEPCTL4 + addressOffset: 2432 + size: 32 + resetValue: 32768 + fields: + - name: D_MPS4 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: D_USBACTEP4 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: D_NAKSTS4 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: D_EPTYPE4 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: D_STALL4 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: D_TXFNUM4 + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: D_CNAK4 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DI_SNAK4 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: DI_SETD0PID4 + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DI_SETD1PID4 + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: D_EPDIS4 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: D_EPENA4 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DIEPINT4 + addressOffset: 2440 + size: 32 + fields: + - name: D_XFERCOMPL4 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: D_EPDISBLD4 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: D_AHBERR4 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: D_TIMEOUT4 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: D_INTKNTXFEMP4 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: D_INTKNEPMIS4 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: D_INEPNAKEFF4 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: D_TXFEMP4 + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: D_TXFIFOUNDRN4 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: D_BNAINTR4 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: D_PKTDRPSTS4 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: D_BBLEERR4 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: D_NAKINTRPT4 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: D_NYETINTRPT4 + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DIEPTSIZ4 + addressOffset: 2448 + size: 32 + fields: + - name: D_XFERSIZE4 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: D_PKTCNT4 + bitOffset: 19 + bitWidth: 2 + access: read-write + - register: + name: DIEPDMA4 + addressOffset: 2452 + size: 32 + fields: + - name: D_DMAADDR4 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DTXFSTS4 + addressOffset: 2456 + size: 32 + fields: + - name: D_INEPTXFSPCAVAIL4 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: DIEPDMAB4 + addressOffset: 2460 + size: 32 + fields: + - name: D_DMABUFFERADDR4 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DIEPCTL5 + addressOffset: 2464 + size: 32 + resetValue: 32768 + fields: + - name: DI_MPS5 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DI_USBACTEP5 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: DI_NAKSTS5 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: DI_EPTYPE5 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: DI_STALL5 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: DI_TXFNUM5 + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: DI_CNAK5 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DI_SNAK5 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: DI_SETD0PID5 + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DI_SETD1PID5 + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: DI_EPDIS5 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DI_EPENA5 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DIEPINT5 + addressOffset: 2472 + size: 32 + fields: + - name: D_XFERCOMPL5 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: D_EPDISBLD5 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: D_AHBERR5 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: D_TIMEOUT5 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: D_INTKNTXFEMP5 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: D_INTKNEPMIS5 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: D_INEPNAKEFF5 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: D_TXFEMP5 + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: D_TXFIFOUNDRN5 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: D_BNAINTR5 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: D_PKTDRPSTS5 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: D_BBLEERR5 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: D_NAKINTRPT5 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: D_NYETINTRPT5 + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DIEPTSIZ5 + addressOffset: 2480 + size: 32 + fields: + - name: D_XFERSIZE5 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: D_PKTCNT5 + bitOffset: 19 + bitWidth: 2 + access: read-write + - register: + name: DIEPDMA5 + addressOffset: 2484 + size: 32 + fields: + - name: D_DMAADDR5 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DTXFSTS5 + addressOffset: 2488 + size: 32 + fields: + - name: D_INEPTXFSPCAVAIL5 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: DIEPDMAB5 + addressOffset: 2492 + size: 32 + fields: + - name: D_DMABUFFERADDR5 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DIEPCTL6 + addressOffset: 2496 + size: 32 + resetValue: 32768 + fields: + - name: D_MPS6 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: D_USBACTEP6 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: D_NAKSTS6 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: D_EPTYPE6 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: D_STALL6 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: D_TXFNUM6 + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: D_CNAK6 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DI_SNAK6 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: DI_SETD0PID6 + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DI_SETD1PID6 + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: D_EPDIS6 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: D_EPENA6 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DIEPINT6 + addressOffset: 2504 + size: 32 + fields: + - name: D_XFERCOMPL6 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: D_EPDISBLD6 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: D_AHBERR6 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: D_TIMEOUT6 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: D_INTKNTXFEMP6 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: D_INTKNEPMIS6 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: D_INEPNAKEFF6 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: D_TXFEMP6 + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: D_TXFIFOUNDRN6 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: D_BNAINTR6 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: D_PKTDRPSTS6 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: D_BBLEERR6 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: D_NAKINTRPT6 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: D_NYETINTRPT6 + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DIEPTSIZ6 + addressOffset: 2512 + size: 32 + fields: + - name: D_XFERSIZE6 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: D_PKTCNT6 + bitOffset: 19 + bitWidth: 2 + access: read-write + - register: + name: DIEPDMA6 + addressOffset: 2516 + size: 32 + fields: + - name: D_DMAADDR6 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DTXFSTS6 + addressOffset: 2520 + size: 32 + fields: + - name: D_INEPTXFSPCAVAIL6 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: DIEPDMAB6 + addressOffset: 2524 + size: 32 + fields: + - name: D_DMABUFFERADDR6 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DOEPCTL0 + addressOffset: 2816 + size: 32 + resetValue: 32768 + fields: + - name: MPS0 + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: USBACTEP0 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: NAKSTS0 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: EPTYPE0 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: SNP0 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: STALL0 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CNAK0 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DO_SNAK0 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: EPDIS0 + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: EPENA0 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DOEPINT0 + addressOffset: 2824 + size: 32 + fields: + - name: XFERCOMPL0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EPDISBLD0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AHBERR0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SETUP0 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTTKNEPDIS0 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: STSPHSERCVD0 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BACK2BACKSETUP0 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTPKTERR0 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BNAINTR0 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PKTDRPSTS0 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: BBLEERR0 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: NAKINTRPT0 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: NYEPINTRPT0 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: STUPPKTRCVD0 + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: DOEPTSIZ0 + addressOffset: 2832 + size: 32 + fields: + - name: XFERSIZE0 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: PKTCNT0 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SUPCNT0 + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: DOEPDMA0 + addressOffset: 2836 + size: 32 + fields: + - name: DMAADDR0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPDMAB0 + addressOffset: 2844 + size: 32 + fields: + - name: DMABUFFERADDR0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPCTL1 + addressOffset: 2848 + size: 32 + resetValue: 32768 + fields: + - name: MPS1 + bitOffset: 0 + bitWidth: 11 + access: read-only + - name: USBACTEP1 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: NAKSTS1 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: EPTYPE1 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: SNP1 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: STALL1 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CNAK1 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DO_SNAK1 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: DO_SETD0PID1 + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DO_SETD1PID1 + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: EPDIS1 + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: EPENA1 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DOEPINT1 + addressOffset: 2856 + size: 32 + fields: + - name: XFERCOMPL1 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EPDISBLD1 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AHBERR1 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SETUP1 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTTKNEPDIS1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: STSPHSERCVD1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BACK2BACKSETUP1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTPKTERR1 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BNAINTR1 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PKTDRPSTS1 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: BBLEERR1 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: NAKINTRPT1 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: NYEPINTRPT1 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: STUPPKTRCVD1 + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: DOEPTSIZ1 + addressOffset: 2864 + size: 32 + fields: + - name: XFERSIZE1 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: PKTCNT1 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SUPCNT1 + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: DOEPDMA1 + addressOffset: 2868 + size: 32 + fields: + - name: DMAADDR1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPDMAB1 + addressOffset: 2876 + size: 32 + fields: + - name: DMABUFFERADDR1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPCTL2 + addressOffset: 2880 + size: 32 + resetValue: 32768 + fields: + - name: MPS2 + bitOffset: 0 + bitWidth: 11 + access: read-only + - name: USBACTEP2 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: NAKSTS2 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: EPTYPE2 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: SNP2 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: STALL2 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CNAK2 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DO_SNAK2 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: DO_SETD0PID2 + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DO_SETD1PID2 + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: EPDIS2 + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: EPENA2 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DOEPINT2 + addressOffset: 2888 + size: 32 + fields: + - name: XFERCOMPL2 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EPDISBLD2 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AHBERR2 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SETUP2 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTTKNEPDIS2 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: STSPHSERCVD2 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BACK2BACKSETUP2 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTPKTERR2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BNAINTR2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PKTDRPSTS2 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: BBLEERR2 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: NAKINTRPT2 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: NYEPINTRPT2 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: STUPPKTRCVD2 + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: DOEPTSIZ2 + addressOffset: 2896 + size: 32 + fields: + - name: XFERSIZE2 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: PKTCNT2 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SUPCNT2 + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: DOEPDMA2 + addressOffset: 2900 + size: 32 + fields: + - name: DMAADDR2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPDMAB2 + addressOffset: 2908 + size: 32 + fields: + - name: DMABUFFERADDR2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPCTL3 + addressOffset: 2912 + size: 32 + resetValue: 32768 + fields: + - name: MPS3 + bitOffset: 0 + bitWidth: 11 + access: read-only + - name: USBACTEP3 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: NAKSTS3 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: EPTYPE3 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: SNP3 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: STALL3 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CNAK3 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DO_SNAK3 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: DO_SETD0PID3 + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DO_SETD1PID3 + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: EPDIS3 + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: EPENA3 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DOEPINT3 + addressOffset: 2920 + size: 32 + fields: + - name: XFERCOMPL3 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EPDISBLD3 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AHBERR3 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SETUP3 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTTKNEPDIS3 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: STSPHSERCVD3 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BACK2BACKSETUP3 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTPKTERR3 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BNAINTR3 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PKTDRPSTS3 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: BBLEERR3 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: NAKINTRPT3 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: NYEPINTRPT3 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: STUPPKTRCVD3 + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: DOEPTSIZ3 + addressOffset: 2928 + size: 32 + fields: + - name: XFERSIZE3 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: PKTCNT3 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SUPCNT3 + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: DOEPDMA3 + addressOffset: 2932 + size: 32 + fields: + - name: DMAADDR3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPDMAB3 + addressOffset: 2940 + size: 32 + fields: + - name: DMABUFFERADDR3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPCTL4 + addressOffset: 2944 + size: 32 + resetValue: 32768 + fields: + - name: MPS4 + bitOffset: 0 + bitWidth: 11 + access: read-only + - name: USBACTEP4 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: NAKSTS4 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: EPTYPE4 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: SNP4 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: STALL4 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CNAK4 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DO_SNAK4 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: DO_SETD0PID4 + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DO_SETD1PID4 + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: EPDIS4 + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: EPENA4 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DOEPINT4 + addressOffset: 2952 + size: 32 + fields: + - name: XFERCOMPL4 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EPDISBLD4 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AHBERR4 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SETUP4 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTTKNEPDIS4 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: STSPHSERCVD4 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BACK2BACKSETUP4 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTPKTERR4 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BNAINTR4 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PKTDRPSTS4 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: BBLEERR4 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: NAKINTRPT4 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: NYEPINTRPT4 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: STUPPKTRCVD4 + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: DOEPTSIZ4 + addressOffset: 2960 + size: 32 + fields: + - name: XFERSIZE4 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: PKTCNT4 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SUPCNT4 + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: DOEPDMA4 + addressOffset: 2964 + size: 32 + fields: + - name: DMAADDR4 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPDMAB4 + addressOffset: 2972 + size: 32 + fields: + - name: DMABUFFERADDR4 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPCTL5 + addressOffset: 2976 + size: 32 + resetValue: 32768 + fields: + - name: MPS5 + bitOffset: 0 + bitWidth: 11 + access: read-only + - name: USBACTEP5 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: NAKSTS5 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: EPTYPE5 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: SNP5 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: STALL5 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CNAK5 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DO_SNAK5 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: DO_SETD0PID5 + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DO_SETD1PID5 + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: EPDIS5 + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: EPENA5 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DOEPINT5 + addressOffset: 2984 + size: 32 + fields: + - name: XFERCOMPL5 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EPDISBLD5 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AHBERR5 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SETUP5 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTTKNEPDIS5 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: STSPHSERCVD5 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BACK2BACKSETUP5 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTPKTERR5 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BNAINTR5 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PKTDRPSTS5 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: BBLEERR5 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: NAKINTRPT5 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: NYEPINTRPT5 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: STUPPKTRCVD5 + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: DOEPTSIZ5 + addressOffset: 2992 + size: 32 + fields: + - name: XFERSIZE5 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: PKTCNT5 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SUPCNT5 + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: DOEPDMA5 + addressOffset: 2996 + size: 32 + fields: + - name: DMAADDR5 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPDMAB5 + addressOffset: 3004 + size: 32 + fields: + - name: DMABUFFERADDR5 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPCTL6 + addressOffset: 3008 + size: 32 + resetValue: 32768 + fields: + - name: MPS6 + bitOffset: 0 + bitWidth: 11 + access: read-only + - name: USBACTEP6 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: NAKSTS6 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: EPTYPE6 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: SNP6 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: STALL6 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CNAK6 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DO_SNAK6 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: DO_SETD0PID6 + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DO_SETD1PID6 + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: EPDIS6 + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: EPENA6 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DOEPINT6 + addressOffset: 3016 + size: 32 + fields: + - name: XFERCOMPL6 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EPDISBLD6 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AHBERR6 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SETUP6 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTTKNEPDIS6 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: STSPHSERCVD6 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BACK2BACKSETUP6 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTPKTERR6 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BNAINTR6 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PKTDRPSTS6 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: BBLEERR6 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: NAKINTRPT6 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: NYEPINTRPT6 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: STUPPKTRCVD6 + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: DOEPTSIZ6 + addressOffset: 3024 + size: 32 + fields: + - name: XFERSIZE6 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: PKTCNT6 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SUPCNT6 + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: DOEPDMA6 + addressOffset: 3028 + size: 32 + fields: + - name: DMAADDR6 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPDMAB6 + addressOffset: 3036 + size: 32 + fields: + - name: DMABUFFERADDR6 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PCGCCTL + addressOffset: 3584 + size: 32 + fields: + - name: STOPPCLK + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: GATEHCLK + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PWRCLMP + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RSTPDWNMODULE + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PHYSLEEP + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: L1SUSPENDED + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: RESETAFTERSUSP + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: USB_WRAP + description: USB_WRAP Peripheral + groupName: USB_WRAP + baseAddress: 1061392384 + addressBlock: + - offset: 0 + size: 12 + usage: registers + registers: + - register: + name: OTG_CONF + description: USB OTG Wrapper Configure Register + addressOffset: 0 + size: 32 + resetValue: 1835008 + fields: + - name: SRP_SESSEND_OVERRIDE + description: "This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input. 1'b1: the signal is controlled by the software." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SRP_SESSEND_VALUE + description: Software over-ride value of srp session end signal. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PHY_SEL + description: "Select internal external PHY. 1'b0: Select internal PHY. 1'b1: Select external PHY." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DFIFO_FORCE_PD + description: Force the dfifo to go into low power mode. The data in dfifo will not lost. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DBNCE_FLTR_BYPASS + description: "Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: EXCHG_PINS_OVERRIDE + description: Enable software controlle USB D+ D- exchange + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: EXCHG_PINS + description: "USB D+ D- exchange. 1'b0: don't change. 1'b1: exchange D+ D-" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: VREFH + description: "Control single-end input high threshold,1.76V to 2V, step 80mV" + bitOffset: 7 + bitWidth: 2 + access: read-write + - name: VREFL + description: "Control single-end input low threshold,0.8V to 1.04V, step 80mV" + bitOffset: 9 + bitWidth: 2 + access: read-write + - name: VREF_OVERRIDE + description: Enable software controlle input threshold + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: PAD_PULL_OVERRIDE + description: Enable software controlle USB D+ D- pullup pulldown + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DP_PULLUP + description: Controlle USB D+ pullup + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DP_PULLDOWN + description: Controlle USB D+ pulldown + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DM_PULLUP + description: Controlle USB D+ pullup + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DM_PULLDOWN + description: Controlle USB D+ pulldown + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PULLUP_VALUE + description: "Controlle pullup value. 1'b0: typical value is 2.4K. 1'b1: typical value is 1.2K." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: USB_PAD_ENABLE + description: Enable USB pad function + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: AHB_CLK_FORCE_ON + description: Force ahb clock always on + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PHY_CLK_FORCE_ON + description: Force phy clock always on + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: PHY_TX_EDGE_SEL + description: "Select phy tx signal output clock edge. 1'b0: negedge. 1'b1: posedge." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: DFIFO_FORCE_PU + description: Disable the dfifo to go into low power mode. The data in dfifo will not lost. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: Disable auto clock gating of CSR registers + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TEST_CONF + description: USB Internal PHY Testing Register + addressOffset: 4 + size: 32 + fields: + - name: TEST_ENABLE + description: Enable test of the USB pad + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TEST_USB_OE + description: USB pad oen in test + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TEST_TX_DP + description: USB D+ tx value in test + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TEST_TX_DM + description: USB D- tx value in test + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TEST_RX_RCV + description: USB differential rx value in test + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TEST_RX_DP + description: USB D+ rx value in test + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: TEST_RX_DM + description: USB D- rx value in test + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: Version Control Register + addressOffset: 1020 + size: 32 + resetValue: 34611216 + fields: + - name: USB_WRAP_DATE + description: Date register + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: XTS_AES + description: XTS-AES-128 Flash Encryption + groupName: XTS_AES + baseAddress: 1610850560 + addressBlock: + - offset: 0 + size: 96 + usage: registers + registers: + - register: + dim: 16 + dimIncrement: 4 + name: PLAIN_%s + description: Plaintext register %s + addressOffset: 256 + size: 32 + fields: + - name: PLAIN + description: This register stores %sth 32-bit piece of plaintext. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LINESIZE + description: Configures the size of target memory space + addressOffset: 320 + size: 32 + fields: + - name: LINESIZE + description: "Configures the data size of a single encryption. 0: 128 bits. 1: 256 bits. 2: 512 bits." + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: DESTINATION + description: Configures the type of the external memory + addressOffset: 324 + size: 32 + fields: + - name: DESTINATION + description: "Configures the type of the external memory. Currently, it must be set to 0, as the Manual Encryption block only supports flash encryption. Errors may occur if users write 1. 0: flash. 1: external RAM." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: PHYSICAL_ADDRESS + description: Physical address + addressOffset: 328 + size: 32 + fields: + - name: PHYSICAL_ADDRESS + description: Physical address. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: TRIGGER + description: Activates AES algorithm + addressOffset: 332 + size: 32 + fields: + - name: TRIGGER + description: Set to enable manual encryption. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: RELEASE + description: Release control + addressOffset: 336 + size: 32 + fields: + - name: RELEASE + description: Set to grant SPI1 access to encrypted result. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: DESTROY + description: Destroys control + addressOffset: 340 + size: 32 + fields: + - name: DESTROY + description: Set to destroy encrypted result. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: STATE + description: Status register + addressOffset: 344 + size: 32 + fields: + - name: STATE + description: "Indicates the status of the Manual Encryption block. 0x0 (XTS_AES_IDLE): idle. 0x1 (XTS_AES_BUSY): busy with encryption. 0x2 (XTS_AES_DONE): encryption is completed, but the encrypted result is not accessible to SPI. 0X3 (XTS_AES_RELEASE): encrypted result is accessible to SPI." + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: DATE + description: Version control register + addressOffset: 348 + size: 32 + resetValue: 538510612 + fields: + - name: DATE + description: Version control register. + bitOffset: 0 + bitWidth: 30 + access: read-only diff --git a/esp32s3-ulp/svd/esp32s3-ulp.svd.yaml b/esp32s3-ulp/svd/esp32s3-ulp.svd.yaml new file mode 100644 index 0000000000..dbb9bb1353 --- /dev/null +++ b/esp32s3-ulp/svd/esp32s3-ulp.svd.yaml @@ -0,0 +1,3359 @@ +--- +vendor: "ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD." +vendorID: ESPRESSIF +name: ESP32-S3-ULP +series: RISC-V ULP +version: "1" +description: 32-bit RISC-V MCU +licenseText: "Copyright 2023 Espressif Systems (Shanghai) PTE LTD\n\n Licensed under the Apache License, Version 2.0 (the \"License\");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an \"AS IS\" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License." +cpu: + name: RV32IMC + revision: r0p0 + endian: little + mpuPresent: false + fpuPresent: false + nvicPrioBits: 4 + vendorSystickConfig: false +addressUnitBits: 32 +width: 32 +resetValue: 0 +resetMask: 4294967295 +peripherals: + - name: RTC_CNTL + description: Real-Time Clock Control + groupName: RTC_CNTL + baseAddress: 32768 + addressBlock: + - offset: 0 + size: 348 + usage: registers + interrupt: + - name: RISCV_START_INT + value: 6 + - name: SW_INT + value: 7 + - name: SWD_INT + value: 8 + registers: + - register: + name: RTC_ULP_CP_TIMER + description: configure ulp + addressOffset: 252 + size: 32 + fields: + - name: ULP_CP_PC_INIT + description: ULP-coprocessor PC initial address + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: ULP_CP_GPIO_WAKEUP_ENA + description: ULP-coprocessor wakeup by GPIO enable + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ULP_CP_GPIO_WAKEUP_CLR + description: ULP-coprocessor wakeup by GPIO state clear + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: ULP_CP_SLP_TIMER_EN + description: ULP-coprocessor timer enable bit + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RTC_ULP_CP_CTRL + description: configure ulp + addressOffset: 256 + size: 32 + resetValue: 1049088 + fields: + - name: ULP_CP_MEM_ADDR_INIT + description: No public + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: ULP_CP_MEM_ADDR_SIZE + description: No public + bitOffset: 11 + bitWidth: 11 + access: read-write + - name: ULP_CP_MEM_OFFST_CLR + description: No public + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: ULP_CP_CLK_FO + description: ulp coprocessor clk force on + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: ULP_CP_RESET + description: ulp coprocessor clk software reset + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ULP_CP_FORCE_START_TOP + description: "1: ULP-coprocessor is started by SW" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: ULP_CP_START_TOP + description: Write 1 to start ULP-coprocessor + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COCPU_CTRL + description: configure ulp-riscv + addressOffset: 260 + size: 32 + resetValue: 9046032 + fields: + - name: COCPU_CLK_FO + description: cocpu clk force on + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: COCPU_START_2_RESET_DIS + description: time from start cocpu to pull down reset + bitOffset: 1 + bitWidth: 6 + access: read-write + - name: COCPU_START_2_INTR_EN + description: time from start cocpu to give start interrupt + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: COCPU_SHUT + description: to shut cocpu + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: COCPU_SHUT_2_CLK_DIS + description: time from shut cocpu to disable clk + bitOffset: 14 + bitWidth: 8 + access: read-write + - name: COCPU_SHUT_RESET_EN + description: to reset cocpu + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: COCPU_SEL + description: "1: old ULP 0: new riscV" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: COCPU_DONE_FORCE + description: "1: select riscv done 0: select ulp done" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: COCPU_DONE + description: done signal used by riscv to control timer. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: COCPU_SW_INT_TRIGGER + description: trigger cocpu register interrupt + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: COCPU_CLKGATE_EN + description: open ulp-riscv clk gate + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: RTC_ULP_CP_TIMER_1 + description: configure ulp sleep time + addressOffset: 308 + size: 32 + resetValue: 51200 + fields: + - name: ULP_CP_TIMER_SLP_CYCLE + description: sleep cycles for ULP-coprocessor timer + bitOffset: 8 + bitWidth: 24 + access: read-write + - name: RTC_I2C + description: Low-power I2C (Inter-Integrated Circuit) Controller + groupName: RTC_I2C + baseAddress: 60416 + addressBlock: + - offset: 0 + size: 124 + usage: registers + registers: + - register: + name: SCL_LOW + description: configure low scl period + addressOffset: 0 + size: 32 + resetValue: 256 + fields: + - name: PERIOD + description: time period that scl =0 + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: CTRL + description: configure i2c ctrl + addressOffset: 4 + size: 32 + fields: + - name: SDA_FORCE_OUT + description: "1=push pull,0=open drain" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_FORCE_OUT + description: "1=push pull,0=open drain" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MS_MODE + description: "1=master,0=slave" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TRANS_START + description: force start + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_LSB_FIRST + description: transit lsb first + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_LSB_FIRST + description: receive lsb first + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: I2C_CTRL_CLK_GATE_EN + description: configure i2c ctrl clk enable + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: I2C_RESET + description: rtc i2c sw reset + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: I2CCLK_EN + description: rtc i2c reg clk gating + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: STATUS + description: get i2c status + addressOffset: 8 + size: 32 + fields: + - name: ACK_REC + description: ack response + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SLAVE_RW + description: slave read or write + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ARB_LOST + description: arbitration is lost + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: BUS_BUSY + description: bus is busy + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SLAVE_ADDRESSED + description: slave reg sub address + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS + description: One byte transit done + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OP_CNT + description: which operation is working + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: SHIFT + description: shifter content + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: SCL_MAIN_STATE_LAST + description: i2c last main status + bitOffset: 24 + bitWidth: 3 + access: read-only + - name: SCL_STATE_LAST + description: scl last status + bitOffset: 28 + bitWidth: 3 + access: read-only + - register: + name: TO + description: configure time out + addressOffset: 12 + size: 32 + resetValue: 65536 + fields: + - name: TIME_OUT + description: time out threshold + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: SLAVE_ADDR + description: configure slave id + addressOffset: 16 + size: 32 + fields: + - name: SLAVE_ADDR + description: slave address + bitOffset: 0 + bitWidth: 15 + access: read-write + - name: ADDR_10BIT_EN + description: i2c 10bit mode enable + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SCL_HIGH + description: configure high scl period + addressOffset: 20 + size: 32 + resetValue: 256 + fields: + - name: PERIOD + description: time period that scl = 1 + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: SDA_DUTY + description: configure sda duty + addressOffset: 24 + size: 32 + resetValue: 16 + fields: + - name: NUM + description: time period for SDA to toggle after SCL goes low + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: SCL_START_PERIOD + description: configure scl start period + addressOffset: 28 + size: 32 + resetValue: 8 + fields: + - name: SCL_START_PERIOD + description: time period for SCL to toggle after I2C start is triggered + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: SCL_STOP_PERIOD + description: configure scl stop period + addressOffset: 32 + size: 32 + resetValue: 8 + fields: + - name: SCL_STOP_PERIOD + description: time period for SCL to stop after I2C end is triggered + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: INT_CLR + description: interrupt clear register + addressOffset: 36 + size: 32 + fields: + - name: SLAVE_TRAN_COMP_INT_CLR + description: clear slave transit complete interrupt + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ARBITRATION_LOST_INT_CLR + description: clear arbitration lost interrupt + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: MASTER_TRAN_COMP_INT_CLR + description: clear master transit complete interrupt + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TRANS_COMPLETE_INT_CLR + description: clear transit complete interrupt + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TIME_OUT_INT_CLR + description: clear time out interrupt + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: ACK_ERR_INT_CLR + description: clear ack error interrupt + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: RX_DATA_INT_CLR + description: clear receive data interrupt + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TX_DATA_INT_CLR + description: clear transit load data complete interrupt + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: DETECT_START_INT_CLR + description: clear detect start interrupt + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: INT_RAW + description: interrupt raw register + addressOffset: 40 + size: 32 + fields: + - name: SLAVE_TRAN_COMP_INT_RAW + description: slave transit complete interrupt raw + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_RAW + description: arbitration lost interrupt raw + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: MASTER_TRAN_COMP_INT_RAW + description: master transit complete interrupt raw + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_RAW + description: transit complete interrupt raw + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_RAW + description: time out interrupt raw + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ACK_ERR_INT_RAW + description: ack error interrupt raw + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: RX_DATA_INT_RAW + description: receive data interrupt raw + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TX_DATA_INT_RAW + description: transit data interrupt raw + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DETECT_START_INT_RAW + description: detect start interrupt raw + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: interrupt state register + addressOffset: 44 + size: 32 + fields: + - name: SLAVE_TRAN_COMP_INT_ST + description: slave transit complete interrupt state + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_ST + description: arbitration lost interrupt state + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: MASTER_TRAN_COMP_INT_ST + description: master transit complete interrupt state + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_ST + description: transit complete interrupt state + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_ST + description: time out interrupt state + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ACK_ERR_INT_ST + description: ack error interrupt state + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: RX_DATA_INT_ST + description: receive data interrupt state + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TX_DATA_INT_ST + description: transit data interrupt state + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DETECT_START_INT_ST + description: detect start interrupt state + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: interrupt enable register + addressOffset: 48 + size: 32 + fields: + - name: SLAVE_TRAN_COMP_INT_ENA + description: enable slave transit complete interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ARBITRATION_LOST_INT_ENA + description: enable arbitration lost interrupt + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MASTER_TRAN_COMP_INT_ENA + description: enable master transit complete interrupt + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TRANS_COMPLETE_INT_ENA + description: enable transit complete interrupt + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TIME_OUT_INT_ENA + description: enable time out interrupt + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ACK_ERR_INT_ENA + description: enable eack error interrupt + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RX_DATA_INT_ENA + description: enable receive data interrupt + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_DATA_INT_ENA + description: enable transit data interrupt + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DETECT_START_INT_ENA + description: enable detect start interrupt + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: DATA + description: get i2c data status + addressOffset: 52 + size: 32 + fields: + - name: I2C_RDATA + description: data received + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: SLAVE_TX_DATA + description: data sent by slave + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: I2C_DONE + description: i2c done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD0 + description: i2c commond0 register + addressOffset: 56 + size: 32 + resetValue: 2307 + fields: + - name: COMMAND0 + description: command0 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND0_DONE + description: command0_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD1 + description: i2c commond1 register + addressOffset: 60 + size: 32 + resetValue: 6401 + fields: + - name: COMMAND1 + description: command1 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND1_DONE + description: command1_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD2 + description: i2c commond2 register + addressOffset: 64 + size: 32 + resetValue: 2306 + fields: + - name: COMMAND2 + description: command2 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND2_DONE + description: command2_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD3 + description: i2c commond3 register + addressOffset: 68 + size: 32 + resetValue: 257 + fields: + - name: COMMAND3 + description: command3 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND3_DONE + description: command3_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD4 + description: i2c commond4 register + addressOffset: 72 + size: 32 + resetValue: 2305 + fields: + - name: COMMAND4 + description: command4 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND4_DONE + description: command4_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD5 + description: i2c commond5_register + addressOffset: 76 + size: 32 + resetValue: 5889 + fields: + - name: COMMAND5 + description: command5 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND5_DONE + description: command5_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD6 + description: i2c commond6 register + addressOffset: 80 + size: 32 + resetValue: 6401 + fields: + - name: COMMAND6 + description: command6 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND6_DONE + description: command6_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD7 + description: i2c commond7 register + addressOffset: 84 + size: 32 + resetValue: 2308 + fields: + - name: COMMAND7 + description: command7 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND7_DONE + description: command7_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD8 + description: i2c commond8 register + addressOffset: 88 + size: 32 + resetValue: 6401 + fields: + - name: COMMAND8 + description: command8 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND8_DONE + description: command8_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD9 + description: i2c commond9 register + addressOffset: 92 + size: 32 + resetValue: 2307 + fields: + - name: COMMAND9 + description: command9 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND9_DONE + description: command9_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD10 + description: i2c commond10 register + addressOffset: 96 + size: 32 + resetValue: 257 + fields: + - name: COMMAND10 + description: command10 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND10_DONE + description: command10_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD11 + description: i2c commond11 register + addressOffset: 100 + size: 32 + resetValue: 2305 + fields: + - name: COMMAND11 + description: command11 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND11_DONE + description: command11_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD12 + description: i2c commond12 register + addressOffset: 104 + size: 32 + resetValue: 5889 + fields: + - name: COMMAND12 + description: command12 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND12_DONE + description: command12_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD13 + description: i2c commond13 register + addressOffset: 108 + size: 32 + resetValue: 6401 + fields: + - name: COMMAND13 + description: command13 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND13_DONE + description: command13_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD14 + description: i2c commond14 register + addressOffset: 112 + size: 32 + fields: + - name: COMMAND14 + description: command14 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND14_DONE + description: command14_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD15 + description: i2c commond15 register + addressOffset: 116 + size: 32 + fields: + - name: COMMAND15 + description: command15 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND15_DONE + description: command15_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: version register + addressOffset: 252 + size: 32 + resetValue: 26235664 + fields: + - name: I2C_DATE + description: version + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: RTC_IO + description: Low-power Input/Output + groupName: RTC_IO + baseAddress: 41984 + addressBlock: + - offset: 0 + size: 240 + usage: registers + registers: + - register: + name: OUT + description: RTC GPIO 0 ~ 21 output data register + addressOffset: 0 + size: 32 + fields: + - name: DATA + description: RTC GPIO 0 ~ 21 output data + bitOffset: 10 + bitWidth: 22 + access: read-write + - register: + name: OUT_W1TS + description: one set RTC GPIO output data + addressOffset: 4 + size: 32 + fields: + - name: OUT_DATA_W1TS + description: RTC GPIO 0 ~ 21 output data write 1 to set + bitOffset: 10 + bitWidth: 22 + access: write-only + - register: + name: OUT_W1TC + description: one clear RTC GPIO output data + addressOffset: 8 + size: 32 + fields: + - name: OUT_DATA_W1TC + description: RTC GPIO 0 ~ 21 output data write 1 to clear + bitOffset: 10 + bitWidth: 22 + access: write-only + - register: + name: ENABLE + description: Configure RTC GPIO output enable + addressOffset: 12 + size: 32 + fields: + - name: GPIO_ENABLE + description: RTC GPIO 0 ~ 21 enable + bitOffset: 10 + bitWidth: 22 + access: read-write + - register: + name: ENABLE_W1TS + description: one set RTC GPIO output enable + addressOffset: 16 + size: 32 + fields: + - name: GPIO_ENABLE_W1TS + description: RTC GPIO 0 ~ 21 enable write 1 to set + bitOffset: 10 + bitWidth: 22 + access: write-only + - register: + name: ENABLE_W1TC + description: one clear RTC GPIO output enable + addressOffset: 20 + size: 32 + fields: + - name: GPIO_ENABLE_W1TC + description: RTC GPIO 0 ~ 21 enable write 1 to clear + bitOffset: 10 + bitWidth: 22 + access: write-only + - register: + name: STATUS + description: RTC GPIO 0 ~ 21 interrupt status + addressOffset: 24 + size: 32 + fields: + - name: INT + description: RTC GPIO 0 ~ 21 interrupt status + bitOffset: 10 + bitWidth: 22 + access: read-write + - register: + name: STATUS_W1TS + description: One set RTC GPIO 0 ~ 21 interrupt status + addressOffset: 28 + size: 32 + fields: + - name: GPIO_STATUS_INT_W1TS + description: RTC GPIO 0 ~ 21 interrupt status write 1 to set + bitOffset: 10 + bitWidth: 22 + access: write-only + - register: + name: STATUS_W1TC + description: One clear RTC GPIO 0 ~ 21 interrupt status + addressOffset: 32 + size: 32 + fields: + - name: GPIO_STATUS_INT_W1TC + description: RTC GPIO 0 ~ 21 interrupt status write 1 to clear + bitOffset: 10 + bitWidth: 22 + access: write-only + - register: + name: IN + description: RTC GPIO input data + addressOffset: 36 + size: 32 + fields: + - name: NEXT + description: RTC GPIO input data + bitOffset: 10 + bitWidth: 22 + access: read-only + - register: + name: PIN0 + description: configure RTC GPIO0 + addressOffset: 40 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output, if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: RTC GPIO wakeup enable bit + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PIN1 + description: configure RTC GPIO1 + addressOffset: 44 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output, if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: RTC GPIO wakeup enable bit + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PIN2 + description: configure RTC GPIO2 + addressOffset: 48 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output, if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: RTC GPIO wakeup enable bit + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PIN3 + description: configure RTC GPIO3 + addressOffset: 52 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output, if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: RTC GPIO wakeup enable bit + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PIN4 + description: configure RTC GPIO4 + addressOffset: 56 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output, if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: RTC GPIO wakeup enable bit + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PIN5 + description: configure RTC GPIO5 + addressOffset: 60 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output, if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: RTC GPIO wakeup enable bit + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PIN6 + description: configure RTC GPIO6 + addressOffset: 64 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output, if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: RTC GPIO wakeup enable bit + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PIN7 + description: configure RTC GPIO7 + addressOffset: 68 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output, if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: RTC GPIO wakeup enable bit + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PIN8 + description: configure RTC GPIO8 + addressOffset: 72 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output, if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: RTC GPIO wakeup enable bit + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PIN9 + description: configure RTC GPIO9 + addressOffset: 76 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output, if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: RTC GPIO wakeup enable bit + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PIN10 + description: configure RTC GPIO10 + addressOffset: 80 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output, if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: RTC GPIO wakeup enable bit + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PIN11 + description: configure RTC GPIO11 + addressOffset: 84 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output, if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: RTC GPIO wakeup enable bit + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PIN12 + description: configure RTC GPIO12 + addressOffset: 88 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output, if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: RTC GPIO wakeup enable bit + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PIN13 + description: configure RTC GPIO13 + addressOffset: 92 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output, if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: RTC GPIO wakeup enable bit + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PIN14 + description: configure RTC GPIO14 + addressOffset: 96 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output, if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: RTC GPIO wakeup enable bit + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PIN15 + description: configure RTC GPIO15 + addressOffset: 100 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output, if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: RTC GPIO wakeup enable bit + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PIN16 + description: configure RTC GPIO16 + addressOffset: 104 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output, if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: RTC GPIO wakeup enable bit + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PIN17 + description: configure RTC GPIO17 + addressOffset: 108 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output, if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: RTC GPIO wakeup enable bit + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PIN18 + description: configure RTC GPIO18 + addressOffset: 112 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output, if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: RTC GPIO wakeup enable bit + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PIN19 + description: configure RTC GPIO19 + addressOffset: 116 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output, if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: RTC GPIO wakeup enable bit + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PIN20 + description: configure RTC GPIO20 + addressOffset: 120 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output, if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: RTC GPIO wakeup enable bit + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PIN21 + description: configure RTC GPIO21 + addressOffset: 124 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output, if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: RTC GPIO wakeup enable bit + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: RTC_DEBUG_SEL + description: configure rtc debug + addressOffset: 128 + size: 32 + fields: + - name: DEBUG_SEL0 + description: configure rtc debug + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: DEBUG_SEL1 + description: configure rtc debug + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: DEBUG_SEL2 + description: configure rtc debug + bitOffset: 10 + bitWidth: 5 + access: read-write + - name: DEBUG_SEL3 + description: configure rtc debug + bitOffset: 15 + bitWidth: 5 + access: read-write + - name: DEBUG_SEL4 + description: configure rtc debug + bitOffset: 20 + bitWidth: 5 + access: read-write + - name: DEBUG_12M_NO_GATING + description: configure rtc debug + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: TOUCH_PAD0 + description: configure RTC PAD0 + addressOffset: 132 + size: 32 + resetValue: 1342177280 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD1 + description: configure RTC PAD1 + addressOffset: 136 + size: 32 + resetValue: 1207959552 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD2 + description: configure RTC PAD2 + addressOffset: 140 + size: 32 + resetValue: 1342177280 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD3 + description: configure RTC PAD3 + addressOffset: 144 + size: 32 + resetValue: 1207959552 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD4 + description: configure RTC PAD4 + addressOffset: 148 + size: 32 + resetValue: 1342177280 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD5 + description: configure RTC PAD5 + addressOffset: 152 + size: 32 + resetValue: 1342177280 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD6 + description: configure RTC PAD6 + addressOffset: 156 + size: 32 + resetValue: 1207959552 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD7 + description: configure RTC PAD7 + addressOffset: 160 + size: 32 + resetValue: 1073741824 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD8 + description: configure RTC PAD8 + addressOffset: 164 + size: 32 + resetValue: 1073741824 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD9 + description: configure RTC PAD9 + addressOffset: 168 + size: 32 + resetValue: 1073741824 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD10 + description: configure RTC PAD10 + addressOffset: 172 + size: 32 + resetValue: 1073741824 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD11 + description: configure RTC PAD11 + addressOffset: 176 + size: 32 + resetValue: 1073741824 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD12 + description: configure RTC PAD12 + addressOffset: 180 + size: 32 + resetValue: 1073741824 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD13 + description: configure RTC PAD13 + addressOffset: 184 + size: 32 + resetValue: 1073741824 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD14 + description: configure RTC PAD14 + addressOffset: 188 + size: 32 + resetValue: 1073741824 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: XTAL_32P_PAD + description: configure RTC PAD15 + addressOffset: 192 + size: 32 + resetValue: 1073741824 + fields: + - name: X32P_FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: X32P_SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: X32P_SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: X32P_SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: X32P_FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: X32P_MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: X32P_RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: X32P_RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: X32P_DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: XTAL_32N_PAD + description: configure RTC PAD16 + addressOffset: 196 + size: 32 + resetValue: 1073741824 + fields: + - name: X32N_FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: X32N_SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: X32N_SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: X32N_SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: X32N_FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: X32N_MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: X32N_RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: X32N_RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: X32N_DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: PAD_DAC1 + description: configure RTC PAD17 + addressOffset: 200 + size: 32 + resetValue: 1073741824 + fields: + - name: PDAC1_DAC + description: PDAC1_DAC + bitOffset: 3 + bitWidth: 8 + access: read-write + - name: PDAC1_XPD_DAC + description: PDAC1_XPD_DAC + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: PDAC1_DAC_XPD_FORCE + description: "1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC,0: use SAR ADC FSM to control PDAC1_XPD_DAC" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PDAC1_FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: PDAC1_SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PDAC1_SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: PDAC1_SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PDAC1_FUN_SEL + description: PDAC1 function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: PDAC1_MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PDAC1_RUE + description: PDAC1_RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: PDAC1_RDE + description: PDAC1_RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: PDAC1_DRV + description: PDAC1_DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: PAD_DAC2 + description: configure RTC PAD18 + addressOffset: 204 + size: 32 + resetValue: 1073741824 + fields: + - name: PDAC2_DAC + description: PDAC2_DAC + bitOffset: 3 + bitWidth: 8 + access: read-write + - name: PDAC2_XPD_DAC + description: PDAC2_XPD_DAC + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: PDAC2_DAC_XPD_FORCE + description: "1: use reg_pdac2_xpd_dac to control PDAC2_XPD_DAC,0: use SAR ADC FSM to control PDAC2_XPD_DAC" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PDAC2_FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: PDAC2_SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PDAC2_SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: PDAC2_SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PDAC2_FUN_SEL + description: PDAC1 function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: PDAC2_MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PDAC2_RUE + description: PDAC2_RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: PDAC2_RDE + description: PDAC2_RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: PDAC2_DRV + description: PDAC2_DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: RTC_PAD19 + description: configure RTC PAD19 + addressOffset: 208 + size: 32 + resetValue: 1342177280 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: RTC_PAD20 + description: configure RTC PAD20 + addressOffset: 212 + size: 32 + resetValue: 1342177280 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: RTC_PAD21 + description: configure RTC PAD21 + addressOffset: 216 + size: 32 + resetValue: 1342177280 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: EXT_WAKEUP0 + description: configure EXT0 wakeup + addressOffset: 220 + size: 32 + fields: + - name: SEL + description: "******* Description configure***" + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: XTL_EXT_CTR + description: configure gpio pd XTAL + addressOffset: 224 + size: 32 + fields: + - name: SEL + description: select RTC GPIO 0 ~ 17 to control XTAL + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: SAR_I2C_IO + description: configure rtc i2c mux + addressOffset: 228 + size: 32 + fields: + - name: SAR_DEBUG_BIT_SEL + description: "******* Description configure***" + bitOffset: 23 + bitWidth: 5 + access: read-write + - name: SAR_I2C_SCL_SEL + description: "******* Description configure***" + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: SAR_I2C_SDA_SEL + description: "******* Description configure***" + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_CTRL + description: configure touch pad bufmode + addressOffset: 232 + size: 32 + fields: + - name: IO_TOUCH_BUFSEL + description: BUF_SEL when touch work without fsm + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: IO_TOUCH_BUFMODE + description: BUF_MODE when touch work without fsm + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: version + addressOffset: 508 + size: 32 + resetValue: 34607488 + fields: + - name: DATE + description: version + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SENS + description: SENS Peripheral + groupName: SENS + baseAddress: 51200 + addressBlock: + - offset: 0 + size: 284 + usage: registers + interrupt: + - name: TOUCH_DONE_INT + value: 0 + - name: TOUCH_INACTIVE_INT + value: 1 + - name: TOUCH_ACTIVE_INT + value: 2 + - name: SARADC1_DONE_INT + value: 3 + - name: SARADC2_DONE_INT + value: 4 + - name: TSENS_DONE_INT + value: 5 + - name: TOUCH_TIME_OUT_INT + value: 9 + - name: TOUCH_APPROACH_LOOP_DONE_INT + value: 10 + - name: TOUCH_SCAN_DONE_INT + value: 11 + registers: + - register: + name: SAR_SLAVE_ADDR1 + description: configure i2c slave address + addressOffset: 64 + size: 32 + fields: + - name: SAR_I2C_SLAVE_ADDR1 + description: configure i2c slave address1 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: SAR_I2C_SLAVE_ADDR0 + description: configure i2c slave address0 + bitOffset: 11 + bitWidth: 11 + access: read-write + - name: SAR_SARADC_MEAS_STATUS + description: no public + bitOffset: 22 + bitWidth: 8 + access: read-only + - register: + name: SAR_SLAVE_ADDR2 + description: configure i2c slave address + addressOffset: 68 + size: 32 + fields: + - name: SAR_I2C_SLAVE_ADDR3 + description: configure i2c slave address3 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: SAR_I2C_SLAVE_ADDR2 + description: configure i2c slave address2 + bitOffset: 11 + bitWidth: 11 + access: read-write + - register: + name: SAR_SLAVE_ADDR3 + description: configure i2c slave address + addressOffset: 72 + size: 32 + fields: + - name: SAR_I2C_SLAVE_ADDR5 + description: configure i2c slave address5 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: SAR_I2C_SLAVE_ADDR4 + description: configure i2c slave address4 + bitOffset: 11 + bitWidth: 11 + access: read-write + - register: + name: SAR_SLAVE_ADDR4 + description: configure i2c slave address + addressOffset: 76 + size: 32 + fields: + - name: SAR_I2C_SLAVE_ADDR7 + description: configure i2c slave address7 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: SAR_I2C_SLAVE_ADDR6 + description: configure i2c slave address6 + bitOffset: 11 + bitWidth: 11 + access: read-write + - register: + name: SAR_I2C_CTRL + description: configure rtc i2c controller by sw + addressOffset: 88 + size: 32 + fields: + - name: SAR_I2C_CTRL + description: I2C control data only active when reg_sar_i2c_start_force = 1 + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SAR_I2C_START + description: start I2C only active when reg_sar_i2c_start_force = 1 + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SAR_I2C_START_FORCE + description: "1: I2C started by SW 0: I2C started by FSM" + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: SAR_COCPU_INT_RAW + description: the interrupt raw of ulp + addressOffset: 232 + size: 32 + fields: + - name: SAR_COCPU_TOUCH_DONE_INT_RAW + description: int from touch done + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TOUCH_INACTIVE_INT_RAW + description: int from touch inactive + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TOUCH_ACTIVE_INT_RAW + description: int from touch active + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_SARADC1_INT_RAW + description: int from saradc1 + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_SARADC2_INT_RAW + description: int from saradc2 + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TSENS_INT_RAW + description: int from tsens + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_START_INT_RAW + description: int from start + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_SW_INT_RAW + description: int from software + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_SWD_INT_RAW + description: int from super watch dog + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TOUCH_TIMEOUT_INT_RAW + description: int from timeout done + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW + description: int from approach loop done + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW + description: int from touch scan done + bitOffset: 11 + bitWidth: 1 + access: read-only + - register: + name: SAR_COCPU_INT_ENA + description: the interrupt enable of ulp + addressOffset: 236 + size: 32 + fields: + - name: SAR_COCPU_TOUCH_DONE_INT_ENA + description: int enable of touch done + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SAR_COCPU_TOUCH_INACTIVE_INT_ENA + description: int enable of from touch inactive + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SAR_COCPU_TOUCH_ACTIVE_INT_ENA + description: int enable of touch active + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SAR_COCPU_SARADC1_INT_ENA + description: int enable of from saradc1 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SAR_COCPU_SARADC2_INT_ENA + description: int enable of from saradc2 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SAR_COCPU_TSENS_INT_ENA + description: int enable of tsens + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SAR_COCPU_START_INT_ENA + description: int enable of start + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SAR_COCPU_SW_INT_ENA + description: int enable of software + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SAR_COCPU_SWD_INT_ENA + description: int enable of super watch dog + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SAR_COCPU_TOUCH_TIMEOUT_INT_ENA + description: int enable of timeout done + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA + description: int enable of approach loop done + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA + description: int enable of touch scan done + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: SAR_COCPU_INT_ST + description: the interrupt state of ulp + addressOffset: 240 + size: 32 + fields: + - name: SAR_COCPU_TOUCH_DONE_INT_ST + description: int state of touch done + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TOUCH_INACTIVE_INT_ST + description: int state of from touch inactive + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TOUCH_ACTIVE_INT_ST + description: int state of touch active + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_SARADC1_INT_ST + description: int state of from saradc1 + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_SARADC2_INT_ST + description: int state of from saradc2 + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TSENS_INT_ST + description: int state of tsens + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_START_INT_ST + description: int state of start + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_SW_INT_ST + description: int state of software + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_SWD_INT_ST + description: int state of super watch dog + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TOUCH_TIMEOUT_INT_ST + description: int state of timeout done + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST + description: int state of approach loop done + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TOUCH_SCAN_DONE_INT_ST + description: int state of touch scan done + bitOffset: 11 + bitWidth: 1 + access: read-only + - register: + name: SAR_COCPU_INT_CLR + description: the interrupt clear of ulp + addressOffset: 244 + size: 32 + fields: + - name: SAR_COCPU_TOUCH_DONE_INT_CLR + description: int clear of touch done + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_TOUCH_INACTIVE_INT_CLR + description: int clear of from touch inactive + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_TOUCH_ACTIVE_INT_CLR + description: int clear of touch active + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_SARADC1_INT_CLR + description: int clear of from saradc1 + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_SARADC2_INT_CLR + description: int clear of from saradc2 + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_TSENS_INT_CLR + description: int clear of tsens + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_START_INT_CLR + description: int clear of start + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_SW_INT_CLR + description: int clear of software + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_SWD_INT_CLR + description: int clear of super watch dog + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_TOUCH_TIMEOUT_INT_CLR + description: int clear of timeout done + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR + description: int clear of approach loop done + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR + description: int clear of touch scan done + bitOffset: 11 + bitWidth: 1 + access: write-only diff --git a/esp32s3/svd/esp32s3.svd.yaml b/esp32s3/svd/esp32s3.svd.yaml new file mode 100644 index 0000000000..18b6fe3aa4 --- /dev/null +++ b/esp32s3/svd/esp32s3.svd.yaml @@ -0,0 +1,49533 @@ +--- +vendor: "ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD." +vendorID: ESPRESSIF +name: ESP32-S3 +series: ESP32 S-Series +version: "21" +description: 32-bit MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE) +licenseText: "Copyright 2024 Espressif Systems (Shanghai) PTE LTD\n\n Licensed under the Apache License, Version 2.0 (the \"License\");\n you may not use this file except in compliance with the License.\n You may obtain a copy of the License at\n\n http://www.apache.org/licenses/LICENSE-2.0\n\n Unless required by applicable law or agreed to in writing, software\n distributed under the License is distributed on an \"AS IS\" BASIS,\n WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n See the License for the specific language governing permissions and\n limitations under the License." +cpu: + name: Xtensa LX7 + revision: r0p0 + endian: little + mpuPresent: false + fpuPresent: true + nvicPrioBits: 0 + vendorSystickConfig: false +addressUnitBits: 32 +width: 32 +resetValue: 0 +resetMask: 4294967295 +peripherals: + - name: AES + description: AES (Advanced Encryption Standard) Accelerator + groupName: AES + baseAddress: 1610850304 + addressBlock: + - offset: 0 + size: 184 + usage: registers + registers: + - register: + dim: 8 + dimIncrement: 4 + name: "KEY[%s]" + description: AES key register %s + addressOffset: 0 + size: 32 + fields: + - name: KEY + description: Stores AES keys. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: "TEXT_IN[%s]" + description: Source data register %s + addressOffset: 32 + size: 32 + fields: + - name: TEXT_IN + description: Stores the source data when the AES accelerator operates in the Typical AES working mode. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: "TEXT_OUT[%s]" + description: Result data register %s + addressOffset: 48 + size: 32 + fields: + - name: TEXT_OUT + description: Stores the result data when the AES accelerator operates in the Typical AES working mode. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: MODE + description: AES Mode register + addressOffset: 64 + size: 32 + fields: + - name: MODE + description: Defines the key length and the encryption/decryption of the AES accelerator. + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: TRIGGER + description: AES trigger register + addressOffset: 72 + size: 32 + fields: + - name: TRIGGER + description: Set this bit to 1 to start AES calculation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: STATE + description: AES state register + addressOffset: 76 + size: 32 + fields: + - name: STATE + description: "Stores the working status of the AES accelerator. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done." + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + dim: 4 + dimIncrement: 4 + name: "IV_MEM[%s]" + description: The memory that stores initialization vector + addressOffset: 80 + size: 32 + - register: + dim: 4 + dimIncrement: 4 + name: "H_MEM[%s]" + description: The memory that stores GCM hash subkey + addressOffset: 96 + size: 32 + - register: + dim: 4 + dimIncrement: 4 + name: "J0_MEM[%s]" + description: The memory that stores J0 + addressOffset: 112 + size: 32 + - register: + dim: 4 + dimIncrement: 4 + name: "T0_MEM[%s]" + description: The memory that stores T0 + addressOffset: 128 + size: 32 + - register: + name: DMA_ENABLE + description: AES accelerator working mode register + addressOffset: 144 + size: 32 + fields: + - name: DMA_ENABLE + description: "Defines the working mode of the AES accelerator. 1'b0: typical AES working mode, 1'b1: DMA-AES working mode." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: BLOCK_MODE + description: AES cipher block mode register + addressOffset: 148 + size: 32 + fields: + - name: BLOCK_MODE + description: "Defines the block cipher mode of the AES accelerator operating under the DMA-AES working mode. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: reserved, 0x7: reserved." + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: BLOCK_NUM + description: AES block number register + addressOffset: 152 + size: 32 + fields: + - name: BLOCK_NUM + description: Stores the Block Number of plaintext or ciphertext when the AES accelerator operates under the DMA-AES working mode. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: INC_SEL + description: Standard incrementing function configure register + addressOffset: 156 + size: 32 + fields: + - name: INC_SEL + description: Defines the Standard Incrementing Function for CTR block operation. Set this bit to 0 or 1 to choose INC32 or INC128. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: AAD_BLOCK_NUM + description: Additional Authential Data block number register + addressOffset: 160 + size: 32 + fields: + - name: AAD_BLOCK_NUM + description: Those bits stores the number of AAD block. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REMAINDER_BIT_NUM + description: AES remainder bit number register + addressOffset: 164 + size: 32 + fields: + - name: REMAINDER_BIT_NUM + description: Those bits stores the number of remainder bit. + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: CONTINUE + description: AES continue register + addressOffset: 168 + size: 32 + fields: + - name: CONTINUE + description: Set this bit to 1 to continue GCM operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: INT_CLR + description: AES Interrupt clear register + addressOffset: 172 + size: 32 + fields: + - name: INT_CLEAR + description: Set this bit to 1 to clear AES interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + description: DMA-AES Interrupt enable register + addressOffset: 176 + size: 32 + fields: + - name: INT_ENA + description: Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. This field is only effective for DMA-AES operation. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: AES version control register + addressOffset: 180 + size: 32 + resetValue: 538513936 + fields: + - name: DATE + description: This bits stores the version information of AES. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: DMA_EXIT + description: AES-DMA exit config + addressOffset: 184 + size: 32 + fields: + - name: DMA_EXIT + description: Set this bit to 1 to exit AES operation. This field is only effective for DMA-AES operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: APB_CTRL + description: APB (Advanced Peripheral Bus) Controller + groupName: APB_CTRL + baseAddress: 1610768384 + addressBlock: + - offset: 0 + size: 204 + usage: registers + registers: + - register: + name: SYSCLK_CONF + description: "******* Description ***********" + addressOffset: 0 + size: 32 + resetValue: 1 + fields: + - name: PRE_DIV_CNT + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: CLK_320M_EN + description: "******* Description ***********" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "******* Description ***********" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RST_TICK_CNT + description: "******* Description ***********" + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: TICK_CONF + description: "******* Description ***********" + addressOffset: 4 + size: 32 + resetValue: 67367 + fields: + - name: XTAL_TICK_NUM + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CK8M_TICK_NUM + description: "******* Description ***********" + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: TICK_ENABLE + description: "******* Description ***********" + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: CLK_OUT_EN + description: "******* Description ***********" + addressOffset: 8 + size: 32 + resetValue: 2047 + fields: + - name: CLK20_OEN + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CLK22_OEN + description: "******* Description ***********" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CLK44_OEN + description: "******* Description ***********" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CLK_BB_OEN + description: "******* Description ***********" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CLK80_OEN + description: "******* Description ***********" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CLK160_OEN + description: "******* Description ***********" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CLK_320M_OEN + description: "******* Description ***********" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CLK_ADC_INF_OEN + description: "******* Description ***********" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_DAC_CPU_OEN + description: "******* Description ***********" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CLK40X_BB_OEN + description: "******* Description ***********" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CLK_XTAL_OEN + description: "******* Description ***********" + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: WIFI_BB_CFG + description: "******* Description ***********" + addressOffset: 12 + size: 32 + fields: + - name: WIFI_BB_CFG + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WIFI_BB_CFG_2 + description: "******* Description ***********" + addressOffset: 16 + size: 32 + fields: + - name: WIFI_BB_CFG_2 + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WIFI_CLK_EN + description: "******* Description ***********" + addressOffset: 20 + size: 32 + resetValue: 4294762544 + fields: + - name: WIFI_CLK_EN + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WIFI_RST_EN + description: "******* Description ***********" + addressOffset: 24 + size: 32 + fields: + - name: WIFI_RST + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HOST_INF_SEL + description: "******* Description ***********" + addressOffset: 28 + size: 32 + fields: + - name: PERI_IO_SWAP + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: EXT_MEM_PMS_LOCK + description: "******* Description ***********" + addressOffset: 32 + size: 32 + fields: + - name: EXT_MEM_PMS_LOCK + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: EXT_MEM_WRITEBACK_BYPASS + description: "******* Description ***********" + addressOffset: 36 + size: 32 + fields: + - name: WRITEBACK_BYPASS + description: Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: FLASH_ACE0_ATTR + description: "******* Description ***********" + addressOffset: 40 + size: 32 + resetValue: 255 + fields: + - name: FLASH_ACE0_ATTR + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: FLASH_ACE1_ATTR + description: "******* Description ***********" + addressOffset: 44 + size: 32 + resetValue: 255 + fields: + - name: FLASH_ACE1_ATTR + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: FLASH_ACE2_ATTR + description: "******* Description ***********" + addressOffset: 48 + size: 32 + resetValue: 255 + fields: + - name: FLASH_ACE2_ATTR + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: FLASH_ACE3_ATTR + description: "******* Description ***********" + addressOffset: 52 + size: 32 + resetValue: 255 + fields: + - name: FLASH_ACE3_ATTR + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: FLASH_ACE0_ADDR + description: "******* Description ***********" + addressOffset: 56 + size: 32 + fields: + - name: S + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FLASH_ACE1_ADDR + description: "******* Description ***********" + addressOffset: 60 + size: 32 + resetValue: 268435456 + fields: + - name: S + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FLASH_ACE2_ADDR + description: "******* Description ***********" + addressOffset: 64 + size: 32 + resetValue: 536870912 + fields: + - name: S + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FLASH_ACE3_ADDR + description: "******* Description ***********" + addressOffset: 68 + size: 32 + resetValue: 805306368 + fields: + - name: S + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FLASH_ACE0_SIZE + description: "******* Description ***********" + addressOffset: 72 + size: 32 + resetValue: 4096 + fields: + - name: FLASH_ACE0_SIZE + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: FLASH_ACE1_SIZE + description: "******* Description ***********" + addressOffset: 76 + size: 32 + resetValue: 4096 + fields: + - name: FLASH_ACE1_SIZE + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: FLASH_ACE2_SIZE + description: "******* Description ***********" + addressOffset: 80 + size: 32 + resetValue: 4096 + fields: + - name: FLASH_ACE2_SIZE + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: FLASH_ACE3_SIZE + description: "******* Description ***********" + addressOffset: 84 + size: 32 + resetValue: 4096 + fields: + - name: FLASH_ACE3_SIZE + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: SRAM_ACE0_ATTR + description: "******* Description ***********" + addressOffset: 88 + size: 32 + resetValue: 255 + fields: + - name: SRAM_ACE0_ATTR + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SRAM_ACE1_ATTR + description: "******* Description ***********" + addressOffset: 92 + size: 32 + resetValue: 255 + fields: + - name: SRAM_ACE1_ATTR + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SRAM_ACE2_ATTR + description: "******* Description ***********" + addressOffset: 96 + size: 32 + resetValue: 255 + fields: + - name: SRAM_ACE2_ATTR + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SRAM_ACE3_ATTR + description: "******* Description ***********" + addressOffset: 100 + size: 32 + resetValue: 255 + fields: + - name: SRAM_ACE3_ATTR + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SRAM_ACE0_ADDR + description: "******* Description ***********" + addressOffset: 104 + size: 32 + fields: + - name: S + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SRAM_ACE1_ADDR + description: "******* Description ***********" + addressOffset: 108 + size: 32 + resetValue: 268435456 + fields: + - name: S + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SRAM_ACE2_ADDR + description: "******* Description ***********" + addressOffset: 112 + size: 32 + resetValue: 536870912 + fields: + - name: S + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SRAM_ACE3_ADDR + description: "******* Description ***********" + addressOffset: 116 + size: 32 + resetValue: 805306368 + fields: + - name: S + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SRAM_ACE0_SIZE + description: "******* Description ***********" + addressOffset: 120 + size: 32 + resetValue: 4096 + fields: + - name: SRAM_ACE0_SIZE + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: SRAM_ACE1_SIZE + description: "******* Description ***********" + addressOffset: 124 + size: 32 + resetValue: 4096 + fields: + - name: SRAM_ACE1_SIZE + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: SRAM_ACE2_SIZE + description: "******* Description ***********" + addressOffset: 128 + size: 32 + resetValue: 4096 + fields: + - name: SRAM_ACE2_SIZE + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: SRAM_ACE3_SIZE + description: "******* Description ***********" + addressOffset: 132 + size: 32 + resetValue: 4096 + fields: + - name: SRAM_ACE3_SIZE + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: SPI_MEM_PMS_CTRL + description: "******* Description ***********" + addressOffset: 136 + size: 32 + fields: + - name: SPI_MEM_REJECT_INT + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SPI_MEM_REJECT_CLR + description: "******* Description ***********" + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SPI_MEM_REJECT_CDE + description: "******* Description ***********" + bitOffset: 2 + bitWidth: 5 + access: read-only + - register: + name: SPI_MEM_REJECT_ADDR + description: "******* Description ***********" + addressOffset: 140 + size: 32 + fields: + - name: SPI_MEM_REJECT_ADDR + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SDIO_CTRL + description: "******* Description ***********" + addressOffset: 144 + size: 32 + fields: + - name: SDIO_WIN_ACCESS_EN + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: REDCY_SIG0 + description: "******* Description ***********" + addressOffset: 148 + size: 32 + fields: + - name: REDCY_SIG0 + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: REDCY_ANDOR + description: "******* Description ***********" + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: REDCY_SIG1 + description: "******* Description ***********" + addressOffset: 152 + size: 32 + fields: + - name: REDCY_SIG1 + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 31 + access: read-write + - name: REDCY_NANDOR + description: "******* Description ***********" + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: FRONT_END_MEM_PD + description: "******* Description ***********" + addressOffset: 156 + size: 32 + resetValue: 85 + fields: + - name: AGC_MEM_FORCE_PU + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: AGC_MEM_FORCE_PD + description: "******* Description ***********" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PBUS_MEM_FORCE_PU + description: "******* Description ***********" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PBUS_MEM_FORCE_PD + description: "******* Description ***********" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DC_MEM_FORCE_PU + description: "******* Description ***********" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DC_MEM_FORCE_PD + description: "******* Description ***********" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FREQ_MEM_FORCE_PU + description: "******* Description ***********" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FREQ_MEM_FORCE_PD + description: "******* Description ***********" + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: SPI_MEM_ECC_CTRL + description: "******* Description ***********" + addressOffset: 160 + size: 32 + resetValue: 2097152 + fields: + - name: FLASH_PAGE_SIZE + description: "Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes." + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: SRAM_PAGE_SIZE + description: "Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes." + bitOffset: 20 + bitWidth: 2 + access: read-write + - register: + name: CLKGATE_FORCE_ON + description: "******* Description ***********" + addressOffset: 168 + size: 32 + resetValue: 16383 + fields: + - name: ROM_CLKGATE_FORCE_ON + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SRAM_CLKGATE_FORCE_ON + description: "******* Description ***********" + bitOffset: 3 + bitWidth: 11 + access: read-write + - register: + name: MEM_POWER_DOWN + description: "******* Description ***********" + addressOffset: 172 + size: 32 + fields: + - name: ROM_POWER_DOWN + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SRAM_POWER_DOWN + description: "******* Description ***********" + bitOffset: 3 + bitWidth: 11 + access: read-write + - register: + name: MEM_POWER_UP + description: "******* Description ***********" + addressOffset: 176 + size: 32 + resetValue: 16383 + fields: + - name: ROM_POWER_UP + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SRAM_POWER_UP + description: "******* Description ***********" + bitOffset: 3 + bitWidth: 11 + access: read-write + - register: + name: RETENTION_CTRL + description: "******* Description ***********" + addressOffset: 180 + size: 32 + fields: + - name: RETENTION_CPU_LINK_ADDR + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 27 + access: read-write + - name: NOBYPASS_CPU_ISO_RST + description: "******* Description ***********" + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: RETENTION_CTRL1 + description: "******* Description ***********" + addressOffset: 184 + size: 32 + fields: + - name: RETENTION_TAG_LINK_ADDR + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 27 + access: read-write + - register: + name: RETENTION_CTRL2 + description: "******* Description ***********" + addressOffset: 188 + size: 32 + resetValue: 2093040 + fields: + - name: RET_ICACHE_SIZE + description: "******* Description ***********" + bitOffset: 4 + bitWidth: 8 + access: read-write + - name: RET_ICACHE_VLD_SIZE + description: "******* Description ***********" + bitOffset: 13 + bitWidth: 8 + access: read-write + - name: RET_ICACHE_START_POINT + description: "******* Description ***********" + bitOffset: 22 + bitWidth: 8 + access: read-write + - name: RET_ICACHE_ENABLE + description: "******* Description ***********" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RETENTION_CTRL3 + description: "******* Description ***********" + addressOffset: 192 + size: 32 + resetValue: 4194288 + fields: + - name: RET_DCACHE_SIZE + description: "******* Description ***********" + bitOffset: 4 + bitWidth: 9 + access: read-write + - name: RET_DCACHE_VLD_SIZE + description: "******* Description ***********" + bitOffset: 13 + bitWidth: 9 + access: read-write + - name: RET_DCACHE_START_POINT + description: "******* Description ***********" + bitOffset: 22 + bitWidth: 9 + access: read-write + - name: RET_DCACHE_ENABLE + description: "******* Description ***********" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RETENTION_CTRL4 + description: "******* Description ***********" + addressOffset: 196 + size: 32 + resetValue: 4294967295 + fields: + - name: RETENTION_INV_CFG + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RETENTION_CTRL5 + description: "******* Description ***********" + addressOffset: 200 + size: 32 + fields: + - name: RETENTION_DISABLE + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: "******* Description ***********" + addressOffset: 1020 + size: 32 + resetValue: 34607440 + fields: + - name: DATE + description: Version control + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: APB_SARADC + description: SAR (Successive Approximation Register) Analog-to-Digital Converter + groupName: APB_SARADC + baseAddress: 1610874880 + addressBlock: + - offset: 0 + size: 112 + usage: registers + interrupt: + - name: APB_ADC + value: 65 + registers: + - register: + name: CTRL + description: configure apb saradc controller + addressOffset: 0 + size: 32 + resetValue: 1082098240 + fields: + - name: SARADC_START_FORCE + description: enable start saradc by sw + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SARADC_START + description: start saradc by sw + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SARADC_WORK_MODE + description: "0: single mode, 1: double mode, 2: alternate mode" + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: SARADC_SAR_SEL + description: "0: SAR1, 1: SAR2, only work for single SAR mode" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SARADC_SAR_CLK_GATED + description: enable SAR CLK gate when saradc idle + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SARADC_SAR_CLK_DIV + description: SAR clock divider + bitOffset: 7 + bitWidth: 8 + access: read-write + - name: SARADC_SAR1_PATT_LEN + description: 0 ~ 15 means length 1 ~ 16 + bitOffset: 15 + bitWidth: 4 + access: read-write + - name: SARADC_SAR2_PATT_LEN + description: 0 ~ 15 means length 1 ~ 16 + bitOffset: 19 + bitWidth: 4 + access: read-write + - name: SARADC_SAR1_PATT_P_CLEAR + description: clear the pointer of pattern table for DIG ADC1 CTRL + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SARADC_SAR2_PATT_P_CLEAR + description: clear the pointer of pattern table for DIG ADC2 CTRL + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SARADC_DATA_SAR_SEL + description: "1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: SARADC_DATA_TO_I2S + description: "1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SARADC_XPD_SAR_FORCE + description: force option to xpd sar blocks + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: SARADC_WAIT_ARB_CYCLE + description: wait arbit signal stable after sar_done + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CTRL2 + description: configure apb saradc controller + addressOffset: 4 + size: 32 + resetValue: 41470 + fields: + - name: SARADC_MEAS_NUM_LIMIT + description: enable apb saradc limit the sample num + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SARADC_MAX_MEAS_NUM + description: max conversion number + bitOffset: 1 + bitWidth: 8 + access: read-write + - name: SARADC_SAR1_INV + description: "1: data to DIG ADC1 CTRL is inverted, otherwise not" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SARADC_SAR2_INV + description: "1: data to DIG ADC2 CTRL is inverted, otherwise not" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SARADC_TIMER_SEL + description: "1: select saradc timer 0: i2s_ws trigger" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SARADC_TIMER_TARGET + description: to set saradc timer target + bitOffset: 12 + bitWidth: 12 + access: read-write + - name: SARADC_TIMER_EN + description: to enable saradc timer trigger + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: FILTER_CTRL1 + description: configure saradc filter + addressOffset: 8 + size: 32 + fields: + - name: FILTER_FACTOR1 + description: apb saradc factor1 + bitOffset: 26 + bitWidth: 3 + access: read-write + - name: FILTER_FACTOR0 + description: apb saradc factor0 + bitOffset: 29 + bitWidth: 3 + access: read-write + - register: + name: FSM_WAIT + description: configure apb saradc fsm + addressOffset: 12 + size: 32 + resetValue: 16713736 + fields: + - name: SARADC_XPD_WAIT + description: the cycle which saradc controller in xpd state + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SARADC_RSTB_WAIT + description: the cycle which saradc controller in rst state + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SARADC_STANDBY_WAIT + description: the cycle which saradc controller in standby state + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: SAR1_STATUS + description: saradc1 status for debug + addressOffset: 16 + size: 32 + fields: + - name: SARADC_SAR1_STATUS + description: saradc1 status + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SAR2_STATUS + description: saradc2 status for debug + addressOffset: 20 + size: 32 + fields: + - name: SARADC_SAR2_STATUS + description: saradc2 status + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SAR1_PATT_TAB1 + description: configure apb saradc pattern table + addressOffset: 24 + size: 32 + fields: + - name: SARADC_SAR1_PATT_TAB1 + description: item 0 ~ 3 for pattern table 1 (each item 6bit) + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: SAR1_PATT_TAB2 + description: configure apb saradc pattern table + addressOffset: 28 + size: 32 + fields: + - name: SARADC_SAR1_PATT_TAB2 + description: Item 4 ~ 7 for pattern table 1 (each item 6bit) + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: SAR1_PATT_TAB3 + description: configure apb saradc pattern table + addressOffset: 32 + size: 32 + fields: + - name: SARADC_SAR1_PATT_TAB3 + description: Item 8 ~ 11 for pattern table 1 (each item 6bit) + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: SAR1_PATT_TAB4 + description: configure apb saradc pattern table + addressOffset: 36 + size: 32 + fields: + - name: SARADC_SAR1_PATT_TAB4 + description: Item 12 ~ 15 for pattern table 1 (each item 6bit) + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: SAR2_PATT_TAB1 + description: configure apb saradc pattern table + addressOffset: 40 + size: 32 + fields: + - name: SARADC_SAR2_PATT_TAB1 + description: item 0 ~ 3 for pattern table 2 (each item 6bit) + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: SAR2_PATT_TAB2 + description: configure apb saradc pattern table + addressOffset: 44 + size: 32 + fields: + - name: SARADC_SAR2_PATT_TAB2 + description: Item 4 ~ 7 for pattern table 2 (each item 6bit) + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: SAR2_PATT_TAB3 + description: configure apb saradc pattern table + addressOffset: 48 + size: 32 + fields: + - name: SARADC_SAR2_PATT_TAB3 + description: Item 8 ~ 11 for pattern table 2 (each item 6bit) + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: SAR2_PATT_TAB4 + description: configure apb saradc pattern table + addressOffset: 52 + size: 32 + fields: + - name: SARADC_SAR2_PATT_TAB4 + description: Item 12 ~ 15 for pattern table 2 (each item 6bit) + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: ARB_CTRL + description: configure apb saradc arbit + addressOffset: 56 + size: 32 + resetValue: 2304 + fields: + - name: ADC_ARB_APB_FORCE + description: adc2 arbiter force to enableapb controller + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ADC_ARB_RTC_FORCE + description: adc2 arbiter force to enable rtc controller + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ADC_ARB_WIFI_FORCE + description: adc2 arbiter force to enable wifi controller + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ADC_ARB_GRANT_FORCE + description: adc2 arbiter force grant + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: ADC_ARB_APB_PRIORITY + description: Set adc2 arbiterapb priority + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: ADC_ARB_RTC_PRIORITY + description: Set adc2 arbiter rtc priority + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: ADC_ARB_WIFI_PRIORITY + description: Set adc2 arbiter wifi priority + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: ADC_ARB_FIX_PRIORITY + description: adc2 arbiter uses fixed priority + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: FILTER_CTRL0 + description: configure apb saradc arbit + addressOffset: 60 + size: 32 + resetValue: 7028736 + fields: + - name: FILTER_CHANNEL1 + description: configure the filter1 channel + bitOffset: 14 + bitWidth: 5 + access: read-write + - name: FILTER_CHANNEL0 + description: configure the filter0 channel + bitOffset: 19 + bitWidth: 5 + access: read-write + - name: FILTER_RESET + description: enable apb_adc1_filter + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: APB_SARADC1_DATA_STATUS + description: get apb saradc sample data + addressOffset: 64 + size: 32 + fields: + - name: APB_SARADC1_DATA + description: apbsaradc sample data + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: THRES0_CTRL + description: configure apb saradc thres monitor + addressOffset: 68 + size: 32 + resetValue: 262125 + fields: + - name: THRES0_CHANNEL + description: configure which channel thres0 monitor + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: THRES0_HIGH + description: thres0 monitor high thres + bitOffset: 5 + bitWidth: 13 + access: read-write + - name: THRES0_LOW + description: thres0 monitor low thres + bitOffset: 18 + bitWidth: 13 + access: read-write + - register: + name: THRES1_CTRL + description: configure apb saradc thres monitor + addressOffset: 72 + size: 32 + resetValue: 262125 + fields: + - name: THRES1_CHANNEL + description: configure which channel thres0 monitor + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: THRES1_HIGH + description: thres1 monitor high thres + bitOffset: 5 + bitWidth: 13 + access: read-write + - name: THRES1_LOW + description: thres1 monitor low thres + bitOffset: 18 + bitWidth: 13 + access: read-write + - register: + name: THRES_CTRL + description: configure thres monitor enable + addressOffset: 88 + size: 32 + fields: + - name: THRES_ALL_EN + description: enable thres0 to monitor all channel + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: THRES3_EN + description: no public + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: THRES2_EN + description: no public + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: THRES1_EN + description: enable thres1 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: THRES0_EN + description: enable thres0 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_ENA + description: enable interrupt + addressOffset: 92 + size: 32 + fields: + - name: THRES1_LOW_INT_ENA + description: interrupt of thres1 low + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: THRES0_LOW_INT_ENA + description: interrupt of thres0 low + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: THRES1_HIGH_INT_ENA + description: interrupt of thres1 high + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: THRES0_HIGH_INT_ENA + description: interrupt of thres0 high + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: APB_SARADC2_DONE_INT_ENA + description: interrupt of sar2 done + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: APB_SARADC1_DONE_INT_ENA + description: interrupt of sar1 done + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: raw of interrupt + addressOffset: 96 + size: 32 + fields: + - name: THRES1_LOW_INT_RAW + description: interrupt of thres1 low + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: THRES0_LOW_INT_RAW + description: interrupt of thres0 low + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: THRES1_HIGH_INT_RAW + description: interrupt of thres1 high + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: THRES0_HIGH_INT_RAW + description: interrupt of thres0 high + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: APB_SARADC2_DONE_INT_RAW + description: interrupt of sar2 done + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: APB_SARADC1_DONE_INT_RAW + description: interrupt of sar1 done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: state of interrupt + addressOffset: 100 + size: 32 + fields: + - name: THRES1_LOW_INT_ST + description: interrupt of thres1 low + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: THRES0_LOW_INT_ST + description: interrupt of thres0 low + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: THRES1_HIGH_INT_ST + description: interrupt of thres1 high + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: THRES0_HIGH_INT_ST + description: interrupt of thres0 high + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: APB_SARADC2_DONE_INT_ST + description: interrupt of sar2 done + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: APB_SARADC1_DONE_INT_ST + description: interrupt of sar1 done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: clear interrupt + addressOffset: 104 + size: 32 + fields: + - name: THRES1_LOW_INT_CLR + description: interrupt of thres1 low + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: THRES0_LOW_INT_CLR + description: interrupt of thres0 low + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: THRES1_HIGH_INT_CLR + description: interrupt of thres1 high + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: THRES0_HIGH_INT_CLR + description: interrupt of thres0 high + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: APB_SARADC2_DONE_INT_CLR + description: interrupt of sar2 done + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: APB_SARADC1_DONE_INT_CLR + description: interrupt of sar1 done + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: DMA_CONF + description: configure apb saradc dma + addressOffset: 108 + size: 32 + resetValue: 255 + fields: + - name: APB_ADC_EOF_NUM + description: the dma_in_suc_eof gen when sample cnt = spi_eof_num + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: APB_ADC_RESET_FSM + description: reset_apb_adc_state + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: APB_ADC_TRANS + description: enable apb_adc use spi_dma + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CLKM_CONF + description: configure apb saradc clock + addressOffset: 112 + size: 32 + resetValue: 4 + fields: + - name: CLKM_DIV_NUM + description: Integral clock divider value + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CLKM_DIV_B + description: Fractional clock divider numerator value + bitOffset: 8 + bitWidth: 6 + access: read-write + - name: CLKM_DIV_A + description: Fractional clock divider denominator value + bitOffset: 14 + bitWidth: 6 + access: read-write + - name: CLK_EN + description: no public + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CLK_SEL + description: Set this bit to enable clk_apll + bitOffset: 21 + bitWidth: 2 + access: read-write + - register: + name: APB_SARADC2_DATA_STATUS + description: get apb saradc2 sample data + addressOffset: 120 + size: 32 + fields: + - name: APB_SARADC2_DATA + description: apb saradc2 sample data + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: APB_CTRL_DATE + description: version + addressOffset: 1020 + size: 32 + resetValue: 34607488 + fields: + - name: APB_CTRL_DATE + description: version + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: BB + description: BB Peripheral + groupName: BB + baseAddress: 1610731520 + addressBlock: + - offset: 0 + size: 4 + usage: registers + registers: + - register: + name: BBPD_CTRL + description: Baseband control register + addressOffset: 84 + size: 32 + fields: + - name: DC_EST_FORCE_PD + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DC_EST_FORCE_PU + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FFT_FORCE_PD + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FFT_FORCE_PU + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ASSIST_DEBUG + description: Debug Assist + groupName: DEBUG_ASSIST + baseAddress: 1611456512 + addressBlock: + - offset: 0 + size: 348 + usage: registers + interrupt: + - name: ASSIST_DEBUG + value: 83 + registers: + - register: + name: CORE_0_MONTR_ENA + description: core0 monitor enable configuration register + addressOffset: 0 + size: 32 + fields: + - name: CORE_0_AREA_DRAM0_0_RD_ENA + description: Core0 dram0 area0 read monitor enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_0_WR_ENA + description: Core0 dram0 area0 write monitor enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_1_RD_ENA + description: Core0 dram0 area1 read monitor enable + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_1_WR_ENA + description: Core0 dram0 area1 write monitor enable + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_0_RD_ENA + description: Core0 PIF area0 read monitor enable + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_0_WR_ENA + description: Core0 PIF area0 write monitor enable + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_1_RD_ENA + description: Core0 PIF area1 read monitor enable + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_1_WR_ENA + description: Core0 PIF area1 write monitor enable + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CORE_0_SP_SPILL_MIN_ENA + description: Core0 stackpoint overflow monitor enable + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CORE_0_SP_SPILL_MAX_ENA + description: Core0 stackpoint underflow monitor enable + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CORE_0_IRAM0_EXCEPTION_MONITOR_ENA + description: IBUS busy monitor enable + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CORE_0_DRAM0_EXCEPTION_MONITOR_ENA + description: DBUS busy monitor enbale + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_INTR_RAW + description: core0 monitor interrupt status register + addressOffset: 4 + size: 32 + fields: + - name: CORE_0_AREA_DRAM0_0_RD_RAW + description: Core0 dram0 area0 read monitor interrupt status + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_DRAM0_0_WR_RAW + description: Core0 dram0 area0 write monitor interrupt status + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_DRAM0_1_RD_RAW + description: Core0 dram0 area1 read monitor interrupt status + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_DRAM0_1_WR_RAW + description: Core0 dram0 area1 write monitor interrupt status + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_PIF_0_RD_RAW + description: Core0 PIF area0 read monitor interrupt status + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_PIF_0_WR_RAW + description: Core0 PIF area0 write monitor interrupt status + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_PIF_1_RD_RAW + description: Core0 PIF area1 read monitor interrupt status + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: CORE_0_AREA_PIF_1_WR_RAW + description: Core0 PIF area1 write monitor interrupt status + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: CORE_0_SP_SPILL_MIN_RAW + description: Core0 stackpoint overflow monitor interrupt status + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: CORE_0_SP_SPILL_MAX_RAW + description: Core0 stackpoint underflow monitor interrupt status + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: CORE_0_IRAM0_EXCEPTION_MONITOR_RAW + description: IBUS busy monitor interrupt status + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: CORE_0_DRAM0_EXCEPTION_MONITOR_RAW + description: DBUS busy monitor initerrupt status + bitOffset: 11 + bitWidth: 1 + access: read-only + - register: + name: CORE_0_INTR_ENA + description: core0 monitor interrupt enable register + addressOffset: 8 + size: 32 + fields: + - name: CORE_0_AREA_DRAM0_0_RD_INTR_ENA + description: Core0 dram0 area0 read monitor interrupt enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_0_WR_INTR_ENA + description: Core0 dram0 area0 write monitor interrupt enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_1_RD_INTR_ENA + description: Core0 dram0 area1 read monitor interrupt enable + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_1_WR_INTR_ENA + description: Core0 dram0 area1 write monitor interrupt enable + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_0_RD_INTR_ENA + description: Core0 PIF area0 read monitor interrupt enable + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_0_WR_INTR_ENA + description: Core0 PIF area0 write monitor interrupt enable + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_1_RD_INTR_ENA + description: Core0 PIF area1 read monitor interrupt enable + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_1_WR_INTR_ENA + description: Core0 PIF area1 write monitor interrupt enable + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CORE_0_SP_SPILL_MIN_INTR_ENA + description: Core0 stackpoint overflow monitor interrupt enable + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CORE_0_SP_SPILL_MAX_INTR_ENA + description: Core0 stackpoint underflow monitor interrupt enable + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA + description: IBUS busy monitor interrupt enable + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA + description: DBUS busy monitor interrupt enbale + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_INTR_CLR + description: core0 monitor interrupt clr register + addressOffset: 12 + size: 32 + fields: + - name: CORE_0_AREA_DRAM0_0_RD_CLR + description: Core0 dram0 area0 read monitor interrupt clr + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_0_WR_CLR + description: Core0 dram0 area0 write monitor interrupt clr + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_1_RD_CLR + description: Core0 dram0 area1 read monitor interrupt clr + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_DRAM0_1_WR_CLR + description: Core0 dram0 area1 write monitor interrupt clr + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_0_RD_CLR + description: Core0 PIF area0 read monitor interrupt clr + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_0_WR_CLR + description: Core0 PIF area0 write monitor interrupt clr + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_1_RD_CLR + description: Core0 PIF area1 read monitor interrupt clr + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CORE_0_AREA_PIF_1_WR_CLR + description: Core0 PIF area1 write monitor interrupt clr + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CORE_0_SP_SPILL_MIN_CLR + description: Core0 stackpoint overflow monitor interrupt clr + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CORE_0_SP_SPILL_MAX_CLR + description: Core0 stackpoint underflow monitor interrupt clr + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CORE_0_IRAM0_EXCEPTION_MONITOR_CLR + description: IBUS busy monitor interrupt clr + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CORE_0_DRAM0_EXCEPTION_MONITOR_CLR + description: DBUS busy monitor interrupt clr + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_AREA_DRAM0_0_MIN + description: core0 dram0 region0 addr configuration register + addressOffset: 16 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_AREA_DRAM0_0_MIN + description: Core0 dram0 region0 start addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_DRAM0_0_MAX + description: core0 dram0 region0 addr configuration register + addressOffset: 20 + size: 32 + fields: + - name: CORE_0_AREA_DRAM0_0_MAX + description: Core0 dram0 region0 end addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_DRAM0_1_MIN + description: core0 dram0 region1 addr configuration register + addressOffset: 24 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_AREA_DRAM0_1_MIN + description: Core0 dram0 region1 start addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_DRAM0_1_MAX + description: core0 dram0 region1 addr configuration register + addressOffset: 28 + size: 32 + fields: + - name: CORE_0_AREA_DRAM0_1_MAX + description: Core0 dram0 region1 end addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_PIF_0_MIN + description: core0 PIF region0 addr configuration register + addressOffset: 32 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_AREA_PIF_0_MIN + description: Core0 PIF region0 start addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_PIF_0_MAX + description: core0 PIF region0 addr configuration register + addressOffset: 36 + size: 32 + fields: + - name: CORE_0_AREA_PIF_0_MAX + description: Core0 PIF region0 end addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_PIF_1_MIN + description: core0 PIF region1 addr configuration register + addressOffset: 40 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_AREA_PIF_1_MIN + description: Core0 PIF region1 start addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_PIF_1_MAX + description: core0 PIF region1 addr configuration register + addressOffset: 44 + size: 32 + fields: + - name: CORE_0_AREA_PIF_1_MAX + description: Core0 PIF region1 end addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_AREA_SP + description: core0 area sp status register + addressOffset: 48 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_AREA_SP + description: the stackpointer when first touch region monitor interrupt + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_AREA_PC + description: core0 area pc status register + addressOffset: 52 + size: 32 + fields: + - name: CORE_0_AREA_PC + description: the PC when first touch region monitor interrupt + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_SP_UNSTABLE + description: core0 sp unstable configuration register + addressOffset: 56 + size: 32 + resetValue: 11 + fields: + - name: CORE_0_SP_UNSTABLE + description: "unstable period when window change,during this period no check stackpointer" + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CORE_0_SP_MIN + description: core0 sp region configuration regsiter + addressOffset: 60 + size: 32 + fields: + - name: CORE_0_SP_MIN + description: stack min value + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_SP_MAX + description: core0 sp region configuration regsiter + addressOffset: 64 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_SP_MAX + description: stack max value + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_0_SP_PC + description: core0 sp pc status register + addressOffset: 68 + size: 32 + fields: + - name: CORE_0_SP_PC + description: the PC when first touch stack monitor interrupt + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_RCD_PDEBUGENABLE + description: core0 pdebug configuration register + addressOffset: 72 + size: 32 + fields: + - name: CORE_0_RCD_PDEBUGENABLE + description: "Core0 Pdebugenable,set 1 to open core0 Pdebug interface,then can get core0 PC" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_RCD_RECORDING + description: core0 pdebug status register + addressOffset: 76 + size: 32 + fields: + - name: CORE_0_RCD_RECORDING + description: "Pdebug record enable,set 1 to record core0 pdebug interface signal" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_RCD_PDEBUGINST + description: core0 pdebug status register + addressOffset: 80 + size: 32 + fields: + - name: CORE_0_RCD_PDEBUGINST + description: core0 pdebuginst + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_RCD_PDEBUGSTATUS + description: core0 pdebug status register + addressOffset: 84 + size: 32 + fields: + - name: CORE_0_RCD_PDEBUGSTATUS + description: core0 pdebugstatus + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: CORE_0_RCD_PDEBUGDATA + description: core0 pdebug status register + addressOffset: 88 + size: 32 + fields: + - name: CORE_0_RCD_PDEBUGDATA + description: core0_pdebugdata + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_RCD_PDEBUGPC + description: core0 pdebug status register + addressOffset: 92 + size: 32 + fields: + - name: CORE_0_RCD_PDEBUGPC + description: core0_pdebugPC + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_RCD_PDEBUGLS0STAT + description: core0 pdebug status register + addressOffset: 96 + size: 32 + fields: + - name: CORE_0_RCD_PDEBUGLS0STAT + description: core0_pdebug_s0stat + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_RCD_PDEBUGLS0ADDR + description: core0 pdebug status register + addressOffset: 100 + size: 32 + fields: + - name: CORE_0_RCD_PDEBUGLS0ADDR + description: core0_pdebug_s0addr + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_RCD_PDEBUGLS0DATA + description: core0 pdebug status register + addressOffset: 104 + size: 32 + fields: + - name: CORE_0_RCD_PDEBUGLS0DATA + description: core0_pdebug_s0data + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_RCD_SP + description: core0 pdebug status register + addressOffset: 108 + size: 32 + fields: + - name: CORE_0_RCD_SP + description: core0_stack pointer + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_IRAM0_EXCEPTION_MONITOR_0 + description: core0 bus busy status regsiter + addressOffset: 112 + size: 32 + fields: + - name: CORE_0_IRAM0_RECORDING_ADDR_0 + description: "The first iram0's addr[25:2] status when trigger IRAM busy interrupt" + bitOffset: 0 + bitWidth: 24 + access: read-only + - name: CORE_0_IRAM0_RECORDING_WR_0 + description: "The first iram0's wr status when trigger IRAM busy interrupt" + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: CORE_0_IRAM0_RECORDING_LOADSTORE_0 + description: "The first iram0's loadstore status when trigger IRAM busy interrupt" + bitOffset: 25 + bitWidth: 1 + access: read-only + - register: + name: CORE_0_IRAM0_EXCEPTION_MONITOR_1 + description: core0 bus busy status regsiter + addressOffset: 116 + size: 32 + fields: + - name: CORE_0_IRAM0_RECORDING_ADDR_1 + description: "The second iram0's addr[25:2] status when trigger IRAM busy interrupt" + bitOffset: 0 + bitWidth: 24 + access: read-only + - name: CORE_0_IRAM0_RECORDING_WR_1 + description: "The second iram0's wr status when trigger IRAM busy interrupt" + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: CORE_0_IRAM0_RECORDING_LOADSTORE_1 + description: "The second iram0's loadstore status when trigger IRAM busy interrupt" + bitOffset: 25 + bitWidth: 1 + access: read-only + - register: + name: CORE_0_DRAM0_EXCEPTION_MONITOR_0 + description: core0 bus busy status regsiter + addressOffset: 120 + size: 32 + fields: + - name: CORE_0_DRAM0_RECORDING_ADDR_0 + description: "The first dram0's addr[25:4] status when trigger DRAM busy interrupt" + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: CORE_0_DRAM0_RECORDING_WR_0 + description: "The first dram0's wr status when trigger DRAM busy interrupt" + bitOffset: 22 + bitWidth: 1 + access: read-only + - register: + name: CORE_0_DRAM0_EXCEPTION_MONITOR_1 + description: core0 bus busy status regsiter + addressOffset: 124 + size: 32 + fields: + - name: CORE_0_DRAM0_RECORDING_BYTEEN_0 + description: "The first dram0's byteen status when trigger DRAM busy interrupt" + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: CORE_0_DRAM0_EXCEPTION_MONITOR_2 + description: core0 bus busy status regsiter + addressOffset: 128 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_DRAM0_RECORDING_PC_0 + description: "The first dram0's PC status when trigger DRAM busy interrupt" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_DRAM0_EXCEPTION_MONITOR_3 + description: core0 bus busy status regsiter + addressOffset: 132 + size: 32 + fields: + - name: CORE_0_DRAM0_RECORDING_ADDR_1 + description: "The second dram0's addr[25:4] status when trigger DRAM busy interrupt" + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: CORE_0_DRAM0_RECORDING_WR_1 + description: "The second dram0's wr status when trigger DRAM busy interrupt" + bitOffset: 22 + bitWidth: 1 + access: read-only + - register: + name: CORE_0_DRAM0_EXCEPTION_MONITOR_4 + description: core0 bus busy configuration regsiter + addressOffset: 136 + size: 32 + fields: + - name: CORE_0_DRAM0_RECORDING_BYTEEN_1 + description: "The second dram0's byteen status when trigger DRAM busy interrupt" + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: CORE_0_DRAM0_EXCEPTION_MONITOR_5 + description: core0 bus busy configuration regsiter + addressOffset: 140 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_DRAM0_RECORDING_PC_1 + description: "The second dram0's PC status when trigger DRAM busy interrupt" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_1_MONTR_ENA + description: Core1 monitor enable configuration register + addressOffset: 144 + size: 32 + fields: + - name: CORE_1_AREA_DRAM0_0_RD_ENA + description: Core1 dram0 area0 read monitor enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_1_AREA_DRAM0_0_WR_ENA + description: Core1 dram0 area0 write monitor enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CORE_1_AREA_DRAM0_1_RD_ENA + description: Core1 dram0 area1 read monitor enable + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CORE_1_AREA_DRAM0_1_WR_ENA + description: Core1 dram0 area1 write monitor enable + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CORE_1_AREA_PIF_0_RD_ENA + description: Core1 PIF area0 read monitor enable + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CORE_1_AREA_PIF_0_WR_ENA + description: Core1 PIF area0 write monitor enable + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CORE_1_AREA_PIF_1_RD_ENA + description: Core1 PIF area1 read monitor enable + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CORE_1_AREA_PIF_1_WR_ENA + description: Core1 PIF area1 write monitor enable + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CORE_1_SP_SPILL_MIN_ENA + description: Core1 stackpoint overflow monitor enable + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CORE_1_SP_SPILL_MAX_ENA + description: Core1 stackpoint underflow monitor enable + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CORE_1_IRAM0_EXCEPTION_MONITOR_ENA + description: IBUS busy monitor enable + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CORE_1_DRAM0_EXCEPTION_MONITOR_ENA + description: DBUS busy monitor enbale + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: CORE_1_INTR_RAW + description: Core1 monitor interrupt status register + addressOffset: 148 + size: 32 + fields: + - name: CORE_1_AREA_DRAM0_0_RD_RAW + description: Core1 dram0 area0 read monitor interrupt status + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_1_AREA_DRAM0_0_WR_RAW + description: Core1 dram0 area0 write monitor interrupt status + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CORE_1_AREA_DRAM0_1_RD_RAW + description: Core1 dram0 area1 read monitor interrupt status + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CORE_1_AREA_DRAM0_1_WR_RAW + description: Core1 dram0 area1 write monitor interrupt status + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: CORE_1_AREA_PIF_0_RD_RAW + description: Core1 PIF area0 read monitor interrupt status + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: CORE_1_AREA_PIF_0_WR_RAW + description: Core1 PIF area0 write monitor interrupt status + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CORE_1_AREA_PIF_1_RD_RAW + description: Core1 PIF area1 read monitor interrupt status + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: CORE_1_AREA_PIF_1_WR_RAW + description: Core1 PIF area1 write monitor interrupt status + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: CORE_1_SP_SPILL_MIN_RAW + description: Core1 stackpoint overflow monitor interrupt status + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: CORE_1_SP_SPILL_MAX_RAW + description: Core1 stackpoint underflow monitor interrupt status + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: CORE_1_IRAM0_EXCEPTION_MONITOR_RAW + description: IBUS busy monitor interrupt status + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: CORE_1_DRAM0_EXCEPTION_MONITOR_RAW + description: DBUS busy monitor initerrupt status + bitOffset: 11 + bitWidth: 1 + access: read-only + - register: + name: CORE_1_INTR_ENA + description: Core1 monitor interrupt enable register + addressOffset: 152 + size: 32 + fields: + - name: CORE_1_AREA_DRAM0_0_RD_INTR_ENA + description: Core1 dram0 area0 read monitor interrupt enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_1_AREA_DRAM0_0_WR_INTR_ENA + description: Core1 dram0 area0 write monitor interrupt enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CORE_1_AREA_DRAM0_1_RD_INTR_ENA + description: Core1 dram0 area1 read monitor interrupt enable + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CORE_1_AREA_DRAM0_1_WR_INTR_ENA + description: Core1 dram0 area1 write monitor interrupt enable + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CORE_1_AREA_PIF_0_RD_INTR_ENA + description: Core1 PIF area0 read monitor interrupt enable + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CORE_1_AREA_PIF_0_WR_INTR_ENA + description: Core1 PIF area0 write monitor interrupt enable + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CORE_1_AREA_PIF_1_RD_INTR_ENA + description: Core1 PIF area1 read monitor interrupt enable + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CORE_1_AREA_PIF_1_WR_INTR_ENA + description: Core1 PIF area1 write monitor interrupt enable + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CORE_1_SP_SPILL_MIN_INTR_ENA + description: Core1 stackpoint overflow monitor interrupt enable + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CORE_1_SP_SPILL_MAX_INTR_ENA + description: Core1 stackpoint underflow monitor interrupt enable + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CORE_1_IRAM0_EXCEPTION_MONITOR_INTR_ENA + description: IBUS busy monitor interrupt enable + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CORE_1_DRAM0_EXCEPTION_MONITOR_INTR_ENA + description: DBUS busy monitor interrupt enbale + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: CORE_1_INTR_CLR + description: Core1 monitor interrupt clr register + addressOffset: 156 + size: 32 + fields: + - name: CORE_1_AREA_DRAM0_0_RD_CLR + description: Core1 dram0 area0 read monitor interrupt clr + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_1_AREA_DRAM0_0_WR_CLR + description: Core1 dram0 area0 write monitor interrupt clr + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CORE_1_AREA_DRAM0_1_RD_CLR + description: Core1 dram0 area1 read monitor interrupt clr + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CORE_1_AREA_DRAM0_1_WR_CLR + description: Core1 dram0 area1 write monitor interrupt clr + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CORE_1_AREA_PIF_0_RD_CLR + description: Core1 PIF area0 read monitor interrupt clr + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CORE_1_AREA_PIF_0_WR_CLR + description: Core1 PIF area0 write monitor interrupt clr + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CORE_1_AREA_PIF_1_RD_CLR + description: Core1 PIF area1 read monitor interrupt clr + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CORE_1_AREA_PIF_1_WR_CLR + description: Core1 PIF area1 write monitor interrupt clr + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CORE_1_SP_SPILL_MIN_CLR + description: Core1 stackpoint overflow monitor interrupt clr + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CORE_1_SP_SPILL_MAX_CLR + description: Core1 stackpoint underflow monitor interrupt clr + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CORE_1_IRAM0_EXCEPTION_MONITOR_CLR + description: IBUS busy monitor interrupt clr + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CORE_1_DRAM0_EXCEPTION_MONITOR_CLR + description: DBUS busy monitor interrupt clr + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: CORE_1_AREA_DRAM0_0_MIN + description: Core1 dram0 region0 addr configuration register + addressOffset: 160 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_1_AREA_DRAM0_0_MIN + description: Core1 dram0 region0 start addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_1_AREA_DRAM0_0_MAX + description: Core1 dram0 region0 addr configuration register + addressOffset: 164 + size: 32 + fields: + - name: CORE_1_AREA_DRAM0_0_MAX + description: Core1 dram0 region0 end addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_1_AREA_DRAM0_1_MIN + description: Core1 dram0 region1 addr configuration register + addressOffset: 168 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_1_AREA_DRAM0_1_MIN + description: Core1 dram0 region1 start addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_1_AREA_DRAM0_1_MAX + description: Core1 dram0 region1 addr configuration register + addressOffset: 172 + size: 32 + fields: + - name: CORE_1_AREA_DRAM0_1_MAX + description: Core1 dram0 region1 end addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_1_AREA_PIF_0_MIN + description: Core1 PIF region0 addr configuration register + addressOffset: 176 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_1_AREA_PIF_0_MIN + description: Core1 PIF region0 start addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_1_AREA_PIF_0_MAX + description: Core1 PIF region0 addr configuration register + addressOffset: 180 + size: 32 + fields: + - name: CORE_1_AREA_PIF_0_MAX + description: Core1 PIF region0 end addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_1_AREA_PIF_1_MIN + description: Core1 PIF region1 addr configuration register + addressOffset: 184 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_1_AREA_PIF_1_MIN + description: Core1 PIF region1 start addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_1_AREA_PIF_1_MAX + description: Core1 PIF region1 addr configuration register + addressOffset: 188 + size: 32 + fields: + - name: CORE_1_AREA_PIF_1_MAX + description: Core1 PIF region1 end addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_1_AREA_PC + description: Core1 area sp status register + addressOffset: 192 + size: 32 + fields: + - name: CORE_1_AREA_PC + description: the stackpointer when first touch region monitor interrupt + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_1_AREA_SP + description: Core1 area pc status register + addressOffset: 196 + size: 32 + fields: + - name: CORE_1_AREA_SP + description: the PC when first touch region monitor interrupt + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_1_SP_UNSTABLE + description: Core1 sp unstable configuration register + addressOffset: 200 + size: 32 + resetValue: 11 + fields: + - name: CORE_1_SP_UNSTABLE + description: "unstable period when window change,during this period no check stackpointer" + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: CORE_1_SP_MIN + description: Core1 sp region configuration regsiter + addressOffset: 204 + size: 32 + fields: + - name: CORE_1_SP_MIN + description: stack min value + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_1_SP_MAX + description: Core1 sp region configuration regsiter + addressOffset: 208 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_1_SP_MAX + description: stack max value + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CORE_1_SP_PC + description: Core1 sp pc status register + addressOffset: 212 + size: 32 + fields: + - name: CORE_1_SP_PC + description: the PC when first touch stack monitor interrupt + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_1_RCD_PDEBUGENABLE + description: Core1 pdebug configuration register + addressOffset: 216 + size: 32 + fields: + - name: CORE_1_RCD_PDEBUGENABLE + description: "Core1 Pdebugenable,set 1 to open Core1 Pdebug interface, then can get Core1 PC" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_1_RCD_RECORDING + description: Core1 pdebug status register + addressOffset: 220 + size: 32 + fields: + - name: CORE_1_RCD_RECORDING + description: "Pdebug record enable,set 1 to record Core1 pdebug interface signal" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_1_RCD_PDEBUGINST + description: Core1 pdebug status register + addressOffset: 224 + size: 32 + fields: + - name: CORE_1_RCD_PDEBUGINST + description: Core1 pdebuginst + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_1_RCD_PDEBUGSTATUS + description: Core1 pdebug status register + addressOffset: 228 + size: 32 + fields: + - name: CORE_1_RCD_PDEBUGSTATUS + description: Core1 pdebugstatus + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: CORE_1_RCD_PDEBUGDATA + description: Core1 pdebug status register + addressOffset: 232 + size: 32 + fields: + - name: CORE_1_RCD_PDEBUGDATA + description: Core1_pdebugdata + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_1_RCD_PDEBUGPC + description: Core1 pdebug status register + addressOffset: 236 + size: 32 + fields: + - name: CORE_1_RCD_PDEBUGPC + description: Core1_pdebugPC + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_1_RCD_PDEBUGLS0STAT + description: Core1 pdebug status register + addressOffset: 240 + size: 32 + fields: + - name: CORE_1_RCD_PDEBUGLS0STAT + description: Core1_pdebug_s0stat + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_1_RCD_PDEBUGLS0ADDR + description: Core1 pdebug status register + addressOffset: 244 + size: 32 + fields: + - name: CORE_1_RCD_PDEBUGLS0ADDR + description: Core1_pdebug_s0addr + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_1_RCD_PDEBUGLS0DATA + description: Core1 pdebug status register + addressOffset: 248 + size: 32 + fields: + - name: CORE_1_RCD_PDEBUGLS0DATA + description: Core1_pdebug_s0data + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_1_RCD_SP + description: Core1 pdebug status register + addressOffset: 252 + size: 32 + fields: + - name: CORE_1_RCD_SP + description: Core1_stack pointer + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_1_IRAM0_EXCEPTION_MONITOR_0 + description: Core1 bus busy status regsiter + addressOffset: 256 + size: 32 + fields: + - name: CORE_1_IRAM0_RECORDING_ADDR_0 + description: "The first iram0's addr[25:2] status when trigger IRAM busy interrupt" + bitOffset: 0 + bitWidth: 24 + access: read-only + - name: CORE_1_IRAM0_RECORDING_WR_0 + description: "The first iram0's wr status when trigger IRAM busy interrupt" + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: CORE_1_IRAM0_RECORDING_LOADSTORE_0 + description: "The first iram0's loadstore status when trigger IRAM busy interrupt" + bitOffset: 25 + bitWidth: 1 + access: read-only + - register: + name: CORE_1_IRAM0_EXCEPTION_MONITOR_1 + description: Core1 bus busy status regsiter + addressOffset: 260 + size: 32 + fields: + - name: CORE_1_IRAM0_RECORDING_ADDR_1 + description: "The second iram0's addr[25:2] status when trigger IRAM busy interrupt" + bitOffset: 0 + bitWidth: 24 + access: read-only + - name: CORE_1_IRAM0_RECORDING_WR_1 + description: "The second iram0's wr status when trigger IRAM busy interrupt" + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: CORE_1_IRAM0_RECORDING_LOADSTORE_1 + description: "The second iram0's loadstore status when trigger IRAM busy interrupt" + bitOffset: 25 + bitWidth: 1 + access: read-only + - register: + name: CORE_1_DRAM0_EXCEPTION_MONITOR_0 + description: Core1 bus busy status regsiter + addressOffset: 264 + size: 32 + fields: + - name: CORE_1_DRAM0_RECORDING_ADDR_0 + description: "The first dram0's addr[25:4] status when trigger DRAM busy interrupt" + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: CORE_1_DRAM0_RECORDING_WR_0 + description: "The first dram0's wr status when trigger DRAM busy interrupt" + bitOffset: 22 + bitWidth: 1 + access: read-only + - register: + name: CORE_1_DRAM0_EXCEPTION_MONITOR_1 + description: Core1 bus busy status regsiter + addressOffset: 268 + size: 32 + fields: + - name: CORE_1_DRAM0_RECORDING_BYTEEN_0 + description: "The first dram0's byteen status when trigger DRAM busy interrupt" + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: CORE_1_DRAM0_EXCEPTION_MONITOR_2 + description: Core1 bus busy status regsiter + addressOffset: 272 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_1_DRAM0_RECORDING_PC_0 + description: "The first dram0's PC status when trigger DRAM busy interrupt" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_1_DRAM0_EXCEPTION_MONITOR_3 + description: Core1 bus busy status regsiter + addressOffset: 276 + size: 32 + fields: + - name: CORE_1_DRAM0_RECORDING_ADDR_1 + description: "The second dram0's addr[25:4] status when trigger DRAM busy interrupt" + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: CORE_1_DRAM0_RECORDING_WR_1 + description: "The second dram0's wr status when trigger DRAM busy interrupt" + bitOffset: 22 + bitWidth: 1 + access: read-only + - register: + name: CORE_1_DRAM0_EXCEPTION_MONITOR_4 + description: Core1 bus busy status regsiter + addressOffset: 280 + size: 32 + fields: + - name: CORE_1_DRAM0_RECORDING_BYTEEN_1 + description: "The second dram0's byteen status when trigger DRAM busy interrupt" + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: CORE_1_DRAM0_EXCEPTION_MONITOR_5 + description: Core1 bus busy status regsiter + addressOffset: 284 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_1_DRAM0_RECORDING_PC_1 + description: "The second dram0's PC status when trigger DRAM busy interrupt" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 + description: bus busy configuration register + addressOffset: 288 + size: 32 + resetValue: 1048575 + fields: + - name: CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 + description: busy monitor window cycle + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 + description: bus busy configuration register + addressOffset: 292 + size: 32 + resetValue: 1048575 + fields: + - name: CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 + description: "non busy cycle,for example: when cycle=100 and cycle=10,it means that in 100 cycle, if busy access success time less than 10, it will trigger interrutpt" + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: LOG_SETTING + description: log set register + addressOffset: 296 + size: 32 + resetValue: 64 + fields: + - name: LOG_ENA + description: "bus moniter enable: [0]Core1,[1]core1,[2]dma" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: LOG_MODE + description: "check_mode:0:write,1:word,2:halword,3:byte,4:doubleword,5:4word" + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: LOG_MEM_LOOP_ENABLE + description: "mem_loop enable,1 means that loop write" + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: LOG_DATA_0 + description: log check data register + addressOffset: 300 + size: 32 + fields: + - name: LOG_DATA_0 + description: check data0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOG_DATA_1 + description: log check data register + addressOffset: 304 + size: 32 + fields: + - name: LOG_DATA_1 + description: check data1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOG_DATA_2 + description: log check data register + addressOffset: 308 + size: 32 + fields: + - name: LOG_DATA_2 + description: check data2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOG_DATA_3 + description: log check data register + addressOffset: 312 + size: 32 + fields: + - name: LOG_DATA_3 + description: check data3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOG_DATA_MASK + description: log check data mask register + addressOffset: 316 + size: 32 + fields: + - name: LOG_DATA_SIZE + description: data mask + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: LOG_MIN + description: log check region configuration register + addressOffset: 320 + size: 32 + fields: + - name: LOG_MIN + description: check region min addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOG_MAX + description: log check region configuration register + addressOffset: 324 + size: 32 + fields: + - name: LOG_MAX + description: check region max addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOG_MEM_START + description: log mem region configuration register + addressOffset: 328 + size: 32 + fields: + - name: LOG_MEM_START + description: mem start addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOG_MEM_END + description: log mem region configuration register + addressOffset: 332 + size: 32 + fields: + - name: LOG_MEM_END + description: mem end addr + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOG_MEM_WRITING_ADDR + description: log mem addr status register + addressOffset: 336 + size: 32 + fields: + - name: LOG_MEM_WRITING_ADDR + description: "mem current addr, it means next writing addr" + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: LOG_MEM_FULL_FLAG + description: log mem status register + addressOffset: 340 + size: 32 + fields: + - name: LOG_MEM_FULL_FLAG + description: "when it's 1,show that mem write loop morte than one time." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: version register + addressOffset: 508 + size: 32 + resetValue: 33566784 + fields: + - name: DATE + description: version register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: DMA + description: DMA (Direct Memory Access) Controller + groupName: DMA + baseAddress: 1610870784 + addressBlock: + - offset: 0 + size: 800 + usage: registers + interrupt: + - name: DMA_IN_CH0 + value: 66 + - name: DMA_IN_CH1 + value: 67 + - name: DMA_IN_CH2 + value: 68 + - name: DMA_IN_CH3 + value: 69 + - name: DMA_IN_CH4 + value: 70 + - name: DMA_OUT_CH0 + value: 71 + - name: DMA_OUT_CH1 + value: 72 + - name: DMA_OUT_CH2 + value: 73 + - name: DMA_OUT_CH3 + value: 74 + - name: DMA_OUT_CH4 + value: 75 + - name: DMA_APBPERI_PMS + value: 84 + - name: BACKUP_PMS_VIOLATE + value: 93 + - name: DMA_EXTMEM_REJECT + value: 98 + registers: + - cluster: + dim: 5 + dimIncrement: 192 + dimIndex: "0,1,2,3,4" + name: CH%s + description: "Cluster CH%s, containing IN_CONF0_CH?, IN_CONF1_CH?, IN_INT_RAW_CH?, IN_INT_ST_CH?, IN_INT_ENA_CH?, IN_INT_CLR_CH?, INFIFO_STATUS_CH?, IN_POP_CH?, IN_LINK_CH?, IN_STATE_CH?, IN_SUC_EOF_DES_ADDR_CH?, IN_ERR_EOF_DES_ADDR_CH?, IN_DSCR_CH?, IN_DSCR_BF0_CH?, IN_DSCR_BF1_CH?, IN_WIGHT_CH?, IN_PRI_CH?, IN_PERI_SEL_CH?, OUT_CONF0_CH?, OUT_CONF1_CH?, OUT_INT_RAW_CH?, OUT_INT_ST_CH?, OUT_INT_ENA_CH?, OUT_INT_CLR_CH?, OUTFIFO_STATUS_CH?, OUT_PUSH_CH?, OUT_LINK_CH?, OUT_STATE_CH?, OUT_EOF_DES_ADDR_CH?, OUT_EOF_BFR_DES_ADDR_CH?, OUT_DSCR_CH?, OUT_DSCR_BF0_CH?, OUT_DSCR_BF1_CH?, OUT_WIGHT_CH?, OUT_PRI_CH?, OUT_PERI_SEL_CH?" + addressOffset: 0 + children: + - register: + name: IN_CONF0 + description: Configure 0 register of Rx channel 0 + addressOffset: 0 + size: 32 + fields: + - name: IN_RST + description: This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_LOOP_TEST + description: reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: INDSCR_BURST_EN + description: Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DATA_BURST_EN + description: Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MEM_TRANS_EN + description: Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: IN_CONF1 + description: Configure 1 register of Rx channel 0 + addressOffset: 4 + size: 32 + resetValue: 12 + fields: + - name: DMA_INFIFO_FULL_THRS + description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register. + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: IN_CHECK_OWNER + description: Set this bit to enable checking the owner attribute of the link descriptor. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: IN_EXT_MEM_BK_SIZE + description: "Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved" + bitOffset: 13 + bitWidth: 2 + access: read-write + - cluster: + name: IN_INT + description: "Cluster IN_INT, containing IN_INT_RAW, IN_INT_ST, IN_INT_ENA, IN_INT_CLR" + addressOffset: 8 + children: + - register: + name: RAW + description: Raw status interrupt of Rx channel 0 + addressOffset: 0 + size: 32 + fields: + - name: IN_DONE + description: The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF + description: "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF + description: "The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR + description: "The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY + description: "The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: INFIFO_FULL_WM + description: The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L1 + description: This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L1 + description: This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L3 + description: This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L3 + description: This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: ST + description: Masked interrupt of Rx channel 0 + addressOffset: 4 + size: 32 + fields: + - name: IN_DONE + description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: IN_SUC_EOF + description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: IN_ERR_EOF + description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: IN_DSCR_ERR + description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: IN_DSCR_EMPTY + description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: INFIFO_FULL_WM + description: The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: INFIFO_OVF_L1 + description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: INFIFO_UDF_L1 + description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: INFIFO_OVF_L3 + description: The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: INFIFO_UDF_L3 + description: The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - register: + name: ENA + description: Interrupt enable bits of Rx channel 0 + addressOffset: 8 + size: 32 + fields: + - name: IN_DONE + description: The interrupt enable bit for the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: IN_SUC_EOF + description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: IN_ERR_EOF + description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IN_DSCR_ERR + description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: IN_DSCR_EMPTY + description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: INFIFO_FULL_WM + description: The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L1 + description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L1 + description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: INFIFO_OVF_L3 + description: The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: INFIFO_UDF_L3 + description: The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: CLR + description: Interrupt clear bits of Rx channel 0 + addressOffset: 12 + size: 32 + fields: + - name: IN_DONE + description: Set this bit to clear the IN_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: IN_SUC_EOF + description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: IN_ERR_EOF + description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: IN_DSCR_ERR + description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: IN_DSCR_EMPTY + description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: DMA_INFIFO_FULL_WM + description: Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: INFIFO_OVF_L1 + description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: INFIFO_UDF_L1 + description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: INFIFO_OVF_L3 + description: Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: INFIFO_UDF_L3 + description: Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - register: + name: INFIFO_STATUS + description: Receive FIFO status of Rx channel 0 + addressOffset: 24 + size: 32 + resetValue: 251658298 + fields: + - name: INFIFO_FULL_L1 + description: L1 Rx FIFO full signal for Rx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: INFIFO_EMPTY_L1 + description: L1 Rx FIFO empty signal for Rx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: INFIFO_FULL_L2 + description: L2 Rx FIFO full signal for Rx channel 0. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: INFIFO_EMPTY_L2 + description: L2 Rx FIFO empty signal for Rx channel 0. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: INFIFO_FULL_L3 + description: L3 Rx FIFO full signal for Rx channel 0. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: INFIFO_EMPTY_L3 + description: L3 Rx FIFO empty signal for Rx channel 0. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: INFIFO_CNT_L1 + description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. + bitOffset: 6 + bitWidth: 6 + access: read-only + - name: INFIFO_CNT_L2 + description: The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0. + bitOffset: 12 + bitWidth: 7 + access: read-only + - name: INFIFO_CNT_L3 + description: The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0. + bitOffset: 19 + bitWidth: 5 + access: read-only + - name: IN_REMAIN_UNDER_1B_L3 + description: reserved + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: IN_REMAIN_UNDER_2B_L3 + description: reserved + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: IN_REMAIN_UNDER_3B_L3 + description: reserved + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: IN_REMAIN_UNDER_4B_L3 + description: reserved + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: IN_BUF_HUNGRY + description: reserved + bitOffset: 28 + bitWidth: 1 + access: read-only + - register: + name: IN_POP + description: Pop control register of Rx channel 0 + addressOffset: 28 + size: 32 + resetValue: 2048 + fields: + - name: INFIFO_RDATA + description: This register stores the data popping from DMA FIFO. + bitOffset: 0 + bitWidth: 12 + access: read-only + - name: INFIFO_POP + description: Set this bit to pop data from DMA FIFO. + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: IN_LINK + description: Link descriptor configure and control register of Rx channel 0 + addressOffset: 32 + size: 32 + resetValue: 17825792 + fields: + - name: INLINK_ADDR + description: "This register stores the 20 least significant bits of the first inlink descriptor's address." + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: INLINK_AUTO_RET + description: "Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: INLINK_STOP + description: Set this bit to stop dealing with the inlink descriptors. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: INLINK_START + description: Set this bit to start dealing with the inlink descriptors. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: INLINK_RESTART + description: Set this bit to mount a new inlink descriptor. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: INLINK_PARK + description: "1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working." + bitOffset: 24 + bitWidth: 1 + access: read-only + - register: + name: IN_STATE + description: Receive status of Rx channel 0 + addressOffset: 36 + size: 32 + fields: + - name: INLINK_DSCR_ADDR + description: "This register stores the current inlink descriptor's address." + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: IN_DSCR_STATE + description: reserved + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: IN_STATE + description: reserved + bitOffset: 20 + bitWidth: 3 + access: read-only + - register: + name: IN_SUC_EOF_DES_ADDR + description: Inlink descriptor address when EOF occurs of Rx channel 0 + addressOffset: 40 + size: 32 + fields: + - name: IN_SUC_EOF_DES_ADDR + description: This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_ERR_EOF_DES_ADDR + description: Inlink descriptor address when errors occur of Rx channel 0 + addressOffset: 44 + size: 32 + fields: + - name: IN_ERR_EOF_DES_ADDR + description: This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR + description: Current inlink descriptor address of Rx channel 0 + addressOffset: 48 + size: 32 + fields: + - name: INLINK_DSCR + description: The address of the current inlink descriptor x. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_BF0 + description: The last inlink descriptor address of Rx channel 0 + addressOffset: 52 + size: 32 + fields: + - name: INLINK_DSCR_BF0 + description: The address of the last inlink descriptor x-1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_DSCR_BF1 + description: The second-to-last inlink descriptor address of Rx channel 0 + addressOffset: 56 + size: 32 + fields: + - name: INLINK_DSCR_BF1 + description: The address of the second-to-last inlink descriptor x-2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IN_WIGHT + description: Weight register of Rx channel 0 + addressOffset: 60 + size: 32 + resetValue: 3840 + fields: + - name: RX_WEIGHT + description: The weight of Rx channel 0. + bitOffset: 8 + bitWidth: 4 + access: read-write + - register: + name: IN_PRI + description: Priority register of Rx channel 0 + addressOffset: 68 + size: 32 + fields: + - name: RX_PRI + description: "The priority of Rx channel 0. The larger of the value, the higher of the priority." + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: IN_PERI_SEL + description: Peripheral selection of Rx channel 0 + addressOffset: 72 + size: 32 + resetValue: 63 + fields: + - name: PERI_IN_SEL + description: "This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT." + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: OUT_CONF0 + description: Configure 0 register of Tx channel 0 + addressOffset: 96 + size: 32 + resetValue: 8 + fields: + - name: OUT_RST + description: This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_LOOP_TEST + description: reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_AUTO_WRBACK + description: Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_EOF_MODE + description: "EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTDSCR_BURST_EN + description: Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUT_DATA_BURST_EN + description: Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: OUT_CONF1 + description: Configure 1 register of Tx channel 0 + addressOffset: 100 + size: 32 + fields: + - name: OUT_CHECK_OWNER + description: Set this bit to enable checking the owner attribute of the link descriptor. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: OUT_EXT_MEM_BK_SIZE + description: "Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved" + bitOffset: 13 + bitWidth: 2 + access: read-write + - cluster: + name: OUT_INT + description: "Cluster OUT_INT, containing OUT_INT_RAW, OUT_INT_ST, OUT_INT_ENA, OUT_INT_CLR" + addressOffset: 104 + children: + - register: + name: RAW + description: Raw status interrupt of Tx channel 0 + addressOffset: 0 + size: 32 + fields: + - name: OUT_DONE + description: The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_EOF + description: The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR + description: "The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF + description: The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF_L1 + description: This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF_L1 + description: This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF_L3 + description: This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF_L3 + description: This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow. + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: ST + description: Masked interrupt of Tx channel 0 + addressOffset: 4 + size: 32 + fields: + - name: OUT_DONE + description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUT_EOF + description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: OUT_DSCR_ERR + description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: OUT_TOTAL_EOF + description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: OUTFIFO_OVF_L1 + description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: OUTFIFO_UDF_L1 + description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OUTFIFO_OVF_L3 + description: The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUTFIFO_UDF_L3 + description: The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - register: + name: ENA + description: Interrupt enable bits of Tx channel 0 + addressOffset: 8 + size: 32 + fields: + - name: OUT_DONE + description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: OUT_EOF + description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OUT_DSCR_ERR + description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OUT_TOTAL_EOF + description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF_L1 + description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF_L1 + description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUTFIFO_OVF_L3 + description: The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTFIFO_UDF_L3 + description: The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: CLR + description: Interrupt clear bits of Tx channel 0 + addressOffset: 12 + size: 32 + fields: + - name: OUT_DONE + description: Set this bit to clear the OUT_DONE_CH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: OUT_EOF + description: Set this bit to clear the OUT_EOF_CH_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: OUT_DSCR_ERR + description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: OUT_TOTAL_EOF + description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: OUTFIFO_OVF_L1 + description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: OUTFIFO_UDF_L1 + description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: OUTFIFO_OVF_L3 + description: Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: OUTFIFO_UDF_L3 + description: Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - register: + name: OUTFIFO_STATUS + description: Transmit FIFO status of Tx channel 0 + addressOffset: 120 + size: 32 + resetValue: 125829162 + fields: + - name: OUTFIFO_FULL_L1 + description: L1 Tx FIFO full signal for Tx channel 0. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY_L1 + description: L1 Tx FIFO empty signal for Tx channel 0. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: OUTFIFO_FULL_L2 + description: L2 Tx FIFO full signal for Tx channel 0. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY_L2 + description: L2 Tx FIFO empty signal for Tx channel 0. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: OUTFIFO_FULL_L3 + description: L3 Tx FIFO full signal for Tx channel 0. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: OUTFIFO_EMPTY_L3 + description: L3 Tx FIFO empty signal for Tx channel 0. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OUTFIFO_CNT_L1 + description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. + bitOffset: 6 + bitWidth: 5 + access: read-only + - name: OUTFIFO_CNT_L2 + description: The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0. + bitOffset: 11 + bitWidth: 7 + access: read-only + - name: OUTFIFO_CNT_L3 + description: The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0. + bitOffset: 18 + bitWidth: 5 + access: read-only + - name: OUT_REMAIN_UNDER_1B_L3 + description: reserved + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: OUT_REMAIN_UNDER_2B_L3 + description: reserved + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: OUT_REMAIN_UNDER_3B_L3 + description: reserved + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: OUT_REMAIN_UNDER_4B_L3 + description: reserved + bitOffset: 26 + bitWidth: 1 + access: read-only + - register: + name: OUT_PUSH + description: Push control register of Rx channel 0 + addressOffset: 124 + size: 32 + fields: + - name: OUTFIFO_WDATA + description: This register stores the data that need to be pushed into DMA FIFO. + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: OUTFIFO_PUSH + description: Set this bit to push data into DMA FIFO. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: OUT_LINK + description: Link descriptor configure and control register of Tx channel 0 + addressOffset: 128 + size: 32 + resetValue: 8388608 + fields: + - name: OUTLINK_ADDR + description: "This register stores the 20 least significant bits of the first outlink descriptor's address." + bitOffset: 0 + bitWidth: 20 + access: read-write + - name: OUTLINK_STOP + description: Set this bit to stop dealing with the outlink descriptors. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: OUTLINK_START + description: Set this bit to start dealing with the outlink descriptors. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: OUTLINK_RESTART + description: Set this bit to restart a new outlink from the last address. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: OUTLINK_PARK + description: "1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working." + bitOffset: 23 + bitWidth: 1 + access: read-only + - register: + name: OUT_STATE + description: Transmit status of Tx channel 0 + addressOffset: 132 + size: 32 + fields: + - name: OUTLINK_DSCR_ADDR + description: "This register stores the current outlink descriptor's address." + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: OUT_DSCR_STATE + description: reserved + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: OUT_STATE + description: reserved + bitOffset: 20 + bitWidth: 3 + access: read-only + - register: + name: OUT_EOF_DES_ADDR + description: Outlink descriptor address when EOF occurs of Tx channel 0 + addressOffset: 136 + size: 32 + fields: + - name: OUT_EOF_DES_ADDR + description: This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_EOF_BFR_DES_ADDR + description: The last outlink descriptor address when EOF occurs of Tx channel 0 + addressOffset: 140 + size: 32 + fields: + - name: OUT_EOF_BFR_DES_ADDR + description: This register stores the address of the outlink descriptor before the last outlink descriptor. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR + description: Current inlink descriptor address of Tx channel 0 + addressOffset: 144 + size: 32 + fields: + - name: OUTLINK_DSCR + description: The address of the current outlink descriptor y. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_BF0 + description: The last inlink descriptor address of Tx channel 0 + addressOffset: 148 + size: 32 + fields: + - name: OUTLINK_DSCR_BF0 + description: The address of the last outlink descriptor y-1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_DSCR_BF1 + description: The second-to-last inlink descriptor address of Tx channel 0 + addressOffset: 152 + size: 32 + fields: + - name: OUTLINK_DSCR_BF1 + description: The address of the second-to-last inlink descriptor x-2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: OUT_WIGHT + description: Weight register of Rx channel 0 + addressOffset: 156 + size: 32 + resetValue: 3840 + fields: + - name: TX_WEIGHT + description: The weight of Tx channel 0. + bitOffset: 8 + bitWidth: 4 + access: read-write + - register: + name: OUT_PRI + description: Priority register of Tx channel 0. + addressOffset: 164 + size: 32 + fields: + - name: TX_PRI + description: "The priority of Tx channel 0. The larger of the value, the higher of the priority." + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: OUT_PERI_SEL + description: Peripheral selection of Tx channel 0 + addressOffset: 168 + size: 32 + resetValue: 63 + fields: + - name: PERI_OUT_SEL + description: "This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT." + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: AHB_TEST + description: reserved + addressOffset: 960 + size: 32 + fields: + - name: AHB_TESTMODE + description: reserved + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: AHB_TESTADDR + description: reserved + bitOffset: 4 + bitWidth: 2 + access: read-write + - register: + name: PD_CONF + description: reserved + addressOffset: 964 + size: 32 + resetValue: 32 + fields: + - name: DMA_RAM_FORCE_PD + description: Set this bit to force power down DMA internal memory. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DMA_RAM_FORCE_PU + description: Set this bit to force power up DMA internal memory + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DMA_RAM_CLK_FO + description: "1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA." + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: MISC_CONF + description: MISC register + addressOffset: 968 + size: 32 + fields: + - name: AHBM_RST_INTER + description: "Set this bit, then clear this bit to reset the internal ahb FSM." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: AHBM_RST_EXTER + description: "Set this bit, then clear this bit to reset the external ahb FSM." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ARB_PRI_DIS + description: Set this bit to disable priority arbitration function. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers." + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + dim: 5 + dimIncrement: 8 + name: IN_SRAM_SIZE_CH%s + description: Receive L2 FIFO depth of Rx channel 0 + addressOffset: 972 + size: 32 + resetValue: 14 + fields: + - name: IN_SIZE + description: "This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes." + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + dim: 5 + dimIncrement: 8 + name: OUT_SRAM_SIZE_CH%s + description: Transmit L2 FIFO depth of Tx channel 0 + addressOffset: 976 + size: 32 + resetValue: 14 + fields: + - name: OUT_SIZE + description: "This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes." + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: EXTMEM_REJECT_ADDR + description: Reject address accessing external RAM + addressOffset: 1012 + size: 32 + fields: + - name: EXTMEM_REJECT_ADDR + description: This register store the first address rejected by permission control when accessing external RAM. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: EXTMEM_REJECT_ST + description: Reject status accessing external RAM + addressOffset: 1016 + size: 32 + fields: + - name: EXTMEM_REJECT_ATRR + description: "The reject accessing. Bit 0: if this bit is 1, the rejected accessing is READ. Bit 1: if this bit is 1, the rejected accessing is WRITE." + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: EXTMEM_REJECT_CHANNEL_NUM + description: The register indicate the reject accessing from which channel. + bitOffset: 2 + bitWidth: 4 + access: read-only + - name: EXTMEM_REJECT_PERI_NUM + description: This register indicate reject accessing from which peripheral. + bitOffset: 6 + bitWidth: 6 + access: read-only + - register: + name: EXTMEM_REJECT_INT_RAW + description: Raw interrupt status of external RAM permission + addressOffset: 1020 + size: 32 + fields: + - name: EXTMEM_REJECT_INT_RAW + description: The raw interrupt bit turns to high level when accessing external RAM is rejected by permission control. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: EXTMEM_REJECT_INT_ST + description: Masked interrupt status of external RAM permission + addressOffset: 1024 + size: 32 + fields: + - name: EXTMEM_REJECT_INT_ST + description: The raw interrupt status bit for the EXTMEM_REJECT_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: EXTMEM_REJECT_INT_ENA + description: Interrupt enable bits of external RAM permission + addressOffset: 1028 + size: 32 + fields: + - name: EXTMEM_REJECT_INT_ENA + description: The interrupt enable bit for the EXTMEM_REJECT_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: EXTMEM_REJECT_INT_CLR + description: Interrupt clear bits of external RAM permission + addressOffset: 1032 + size: 32 + fields: + - name: EXTMEM_REJECT_INT_CLR + description: Set this bit to clear the EXTMEM_REJECT_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: DATE + description: Version control register + addressOffset: 1036 + size: 32 + resetValue: 34607488 + fields: + - name: DATE + description: register version. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: DS + description: Digital Signature + groupName: DS + baseAddress: 1610862592 + addressBlock: + - offset: 0 + size: 2652 + usage: registers + registers: + - register: + dim: 396 + dimIncrement: 4 + name: "C_MEM[%s]" + description: Memory C + addressOffset: 0 + size: 32 + - register: + dim: 4 + dimIncrement: 4 + name: IV_%s + description: IV block data + addressOffset: 1584 + size: 32 + fields: + - name: IV + description: Stores IV block data + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 128 + dimIncrement: 4 + name: "X_MEM[%s]" + description: Memory X + addressOffset: 2048 + size: 32 + - register: + dim: 128 + dimIncrement: 4 + name: "Z_MEM[%s]" + description: Memory Z + addressOffset: 2560 + size: 32 + - register: + name: SET_START + description: Activates the DS peripheral + addressOffset: 3584 + size: 32 + fields: + - name: SET_START + description: Write 1 to this register to active the DS peripheral + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_ME + description: Starts DS operation + addressOffset: 3588 + size: 32 + fields: + - name: SET_ME + description: Write 1 to this register to start DS operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_FINISH + description: Ends DS operation + addressOffset: 3592 + size: 32 + fields: + - name: SET_FINISH + description: Write 1 to this register to end DS operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: QUERY_BUSY + description: Status of the DS perihperal + addressOffset: 3596 + size: 32 + fields: + - name: QUERY_BUSY + description: "Stores the status of the DS peripheral. 1: The DS peripheral is busy. 0: The DS peripheral is idle." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: QUERY_KEY_WRONG + description: Checks the reason why DS_KEY is not ready + addressOffset: 3600 + size: 32 + fields: + - name: QUERY_KEY_WRONG + description: "1-15: HMAC was activated, but the DS peripheral did not successfully receive the DS_KEY from the HMAC peripheral. (The biggest value is 15). 0: HMAC is not activated." + bitOffset: 0 + bitWidth: 4 + access: read-only + - register: + name: QUERY_CHECK + description: Queries DS check result + addressOffset: 3604 + size: 32 + fields: + - name: MD_ERROR + description: "MD checkout result. 1: The MD check fails. 0: The MD check passes." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PADDING_BAD + description: "padding checkout result. 1: The padding check fails. 0: The padding check passes." + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: DS version control register + addressOffset: 3616 + size: 32 + resetValue: 538513943 + fields: + - name: DATE + description: ds version information + bitOffset: 0 + bitWidth: 30 + access: read-write + - name: EFUSE + description: eFuse Controller + groupName: EFUSE + baseAddress: 1610641408 + addressBlock: + - offset: 0 + size: 460 + usage: registers + interrupt: + - name: EFUSE + value: 36 + registers: + - register: + name: PGM_DATA0 + description: Register 0 that stores data to be programmed. + addressOffset: 0 + size: 32 + fields: + - name: PGM_DATA_0 + description: The content of the 0th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA1 + description: Register 1 that stores data to be programmed. + addressOffset: 4 + size: 32 + fields: + - name: PGM_DATA_1 + description: The content of the 1st 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA2 + description: Register 2 that stores data to be programmed. + addressOffset: 8 + size: 32 + fields: + - name: PGM_DATA_2 + description: The content of the 2nd 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA3 + description: Register 3 that stores data to be programmed. + addressOffset: 12 + size: 32 + fields: + - name: PGM_DATA_3 + description: The content of the 3rd 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA4 + description: Register 4 that stores data to be programmed. + addressOffset: 16 + size: 32 + fields: + - name: PGM_DATA_4 + description: The content of the 4th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA5 + description: Register 5 that stores data to be programmed. + addressOffset: 20 + size: 32 + fields: + - name: PGM_DATA_5 + description: The content of the 5th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA6 + description: Register 6 that stores data to be programmed. + addressOffset: 24 + size: 32 + fields: + - name: PGM_DATA_6 + description: The content of the 6th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_DATA7 + description: Register 7 that stores data to be programmed. + addressOffset: 28 + size: 32 + fields: + - name: PGM_DATA_7 + description: The content of the 7th 32-bit data to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_CHECK_VALUE0 + description: Register 0 that stores the RS code to be programmed. + addressOffset: 32 + size: 32 + fields: + - name: PGM_RS_DATA_0 + description: The content of the 0th 32-bit RS code to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_CHECK_VALUE1 + description: Register 1 that stores the RS code to be programmed. + addressOffset: 36 + size: 32 + fields: + - name: PGM_RS_DATA_1 + description: The content of the 1st 32-bit RS code to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PGM_CHECK_VALUE2 + description: Register 2 that stores the RS code to be programmed. + addressOffset: 40 + size: 32 + fields: + - name: PGM_RS_DATA_2 + description: The content of the 2nd 32-bit RS code to be programmed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RD_WR_DIS + description: BLOCK0 data register 0. + addressOffset: 44 + size: 32 + fields: + - name: WR_DIS + description: Disable programming of individual eFuses. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_REPEAT_DATA0 + description: BLOCK0 data register 1. + addressOffset: 48 + size: 32 + fields: + - name: RD_DIS + description: Set this bit to disable reading from BlOCK4-10. + bitOffset: 0 + bitWidth: 7 + access: read-only + - name: DIS_RTC_RAM_BOOT + description: Set this bit to disable boot from RTC RAM. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DIS_ICACHE + description: Set this bit to disable Icache. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DIS_DCACHE + description: Set this bit to disable Dcache. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_ICACHE + description: "Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7)." + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_DCACHE + description: "Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, 2, 3, 6, 7)." + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: DIS_FORCE_DOWNLOAD + description: Set this bit to disable the function that forces chip into download mode. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: DIS_USB + description: Set this bit to disable USB function. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: DIS_CAN + description: Set this bit to disable CAN function. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DIS_APP_CPU + description: Disable app cpu. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SOFT_DIS_JTAG + description: Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module. + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: DIS_PAD_JTAG + description: Set this bit to disable JTAG in the hard way. JTAG is disabled permanently. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_MANUAL_ENCRYPT + description: Set this bit to disable flash encryption when in download boot modes. + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: USB_DREFH + description: "Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse." + bitOffset: 21 + bitWidth: 2 + access: read-only + - name: USB_DREFL + description: "Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse." + bitOffset: 23 + bitWidth: 2 + access: read-only + - name: USB_EXCHG_PINS + description: Set this bit to exchange USB D+ and D- pins. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: EXT_PHY_ENABLE + description: Set this bit to enable external PHY. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: BTLC_GPIO_ENABLE + description: Bluetooth GPIO signal output security level control. + bitOffset: 27 + bitWidth: 2 + access: read-only + - name: VDD_SPI_MODECURLIM + description: SPI regulator switches current limit mode. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: VDD_SPI_DREFH + description: SPI regulator high voltage reference. + bitOffset: 30 + bitWidth: 2 + access: read-only + - register: + name: RD_REPEAT_DATA1 + description: BLOCK0 data register 2. + addressOffset: 52 + size: 32 + fields: + - name: VDD_SPI_DREFM + description: SPI regulator medium voltage reference. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: VDD_SPI_DREFL + description: SPI regulator low voltage reference. + bitOffset: 2 + bitWidth: 2 + access: read-only + - name: VDD_SPI_XPD + description: SPI regulator power up signal. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: VDD_SPI_TIEH + description: SPI regulator output is short connected to VDD3P3_RTC_IO. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: VDD_SPI_FORCE + description: Set this bit and force to use the configuration of eFuse to configure VDD_SPI. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: VDD_SPI_EN_INIT + description: "Set SPI regulator to 0 to configure init[1:0]=0." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: VDD_SPI_ENCURLIM + description: Set SPI regulator to 1 to enable output current limit. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: VDD_SPI_DCURLIM + description: "Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d)." + bitOffset: 9 + bitWidth: 3 + access: read-only + - name: VDD_SPI_INIT + description: "Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K." + bitOffset: 12 + bitWidth: 2 + access: read-only + - name: VDD_SPI_DCAP + description: Prevents SPI regulator from overshoot. + bitOffset: 14 + bitWidth: 2 + access: read-only + - name: WDT_DELAY_SEL + description: "Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000." + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: SPI_BOOT_CRYPT_CNT + description: "Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable." + bitOffset: 18 + bitWidth: 3 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE0 + description: Set this bit to enable revoking first secure boot key. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE1 + description: Set this bit to enable revoking second secure boot key. + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE2 + description: Set this bit to enable revoking third secure boot key. + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: KEY_PURPOSE_0 + description: Purpose of Key0. + bitOffset: 24 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_1 + description: Purpose of Key1. + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_REPEAT_DATA2 + description: BLOCK0 data register 3. + addressOffset: 56 + size: 32 + fields: + - name: KEY_PURPOSE_2 + description: Purpose of Key2. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_3 + description: Purpose of Key3. + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_4 + description: Purpose of Key4. + bitOffset: 8 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_5 + description: Purpose of Key5. + bitOffset: 12 + bitWidth: 4 + access: read-only + - name: RPT4_RESERVED0 + description: Reserved (used for four backups method). + bitOffset: 16 + bitWidth: 4 + access: read-only + - name: SECURE_BOOT_EN + description: Set this bit to enable secure boot. + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_AGGRESSIVE_REVOKE + description: Set this bit to enable revoking aggressive secure boot. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: DIS_USB_JTAG + description: Set this bit to disable function of usb switch to jtag in module of usb device. + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: DIS_USB_DEVICE + description: Set this bit to disable usb device. + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: STRAP_JTAG_SEL + description: Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: USB_PHY_SEL + description: "This bit is used to switch internal PHY and external PHY for USB OTG and USB Device. 0: internal PHY is assigned to USB Device while external PHY is assigned to USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned to USB Device." + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: POWER_GLITCH_DSENSE + description: Sample delay configuration of power glitch. + bitOffset: 26 + bitWidth: 2 + access: read-only + - name: FLASH_TPUW + description: "Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value. Otherwise, the waiting time is twice the configurable value." + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_REPEAT_DATA3 + description: BLOCK0 data register 4. + addressOffset: 60 + size: 32 + fields: + - name: DIS_DOWNLOAD_MODE + description: "Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7)." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DIS_LEGACY_SPI_BOOT + description: "Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4)." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: UART_PRINT_CHANNEL + description: "Selectes the default UART print channel. 0: UART0. 1: UART1." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FLASH_ECC_MODE + description: "Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DIS_USB_DOWNLOAD_MODE + description: Set this bit to disable UART download mode through USB. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ENABLE_SECURITY_DOWNLOAD + description: Set this bit to enable secure UART download mode. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: UART_PRINT_CONTROL + description: "Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled." + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: PIN_POWER_SELECTION + description: "GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: FLASH_TYPE + description: "Set the maximum lines of SPI flash. 0: four lines. 1: eight lines." + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: FLASH_PAGE_SIZE + description: Set Flash page size. + bitOffset: 10 + bitWidth: 2 + access: read-only + - name: FLASH_ECC_EN + description: Set 1 to enable ECC for flash boot. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: FORCE_SEND_RESUME + description: Set this bit to force ROM code to send a resume command during SPI boot. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SECURE_VERSION + description: Secure version (used by ESP-IDF anti-rollback feature). + bitOffset: 14 + bitWidth: 16 + access: read-only + - name: POWERGLITCH_EN + description: Set this bit to enable power glitch function. + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED1 + description: Reserved (used for four backups method). + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: RD_REPEAT_DATA4 + description: BLOCK0 data register 5. + addressOffset: 64 + size: 32 + fields: + - name: RPT4_RESERVED2 + description: Reserved (used for four backups method). + bitOffset: 0 + bitWidth: 24 + access: read-only + - register: + name: RD_MAC_SPI_SYS_0 + description: BLOCK1 data register 0. + addressOffset: 68 + size: 32 + fields: + - name: MAC_0 + description: Stores the low 32 bits of MAC address. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_MAC_SPI_SYS_1 + description: BLOCK1 data register 1. + addressOffset: 72 + size: 32 + fields: + - name: MAC_1 + description: Stores the high 16 bits of MAC address. + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: SPI_PAD_CONF_0 + description: Stores the zeroth part of SPI_PAD_CONF. + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: RD_MAC_SPI_SYS_2 + description: BLOCK1 data register 2. + addressOffset: 76 + size: 32 + fields: + - name: SPI_PAD_CONF_1 + description: Stores the first part of SPI_PAD_CONF. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_MAC_SPI_SYS_3 + description: BLOCK1 data register 3. + addressOffset: 80 + size: 32 + fields: + - name: SPI_PAD_CONF_2 + description: Stores the second part of SPI_PAD_CONF. + bitOffset: 0 + bitWidth: 18 + access: read-only + - name: SYS_DATA_PART0_0 + description: Stores the fist 14 bits of the zeroth part of system data. + bitOffset: 18 + bitWidth: 14 + access: read-only + - register: + name: RD_MAC_SPI_SYS_4 + description: BLOCK1 data register 4. + addressOffset: 84 + size: 32 + fields: + - name: SYS_DATA_PART0_1 + description: Stores the fist 32 bits of the zeroth part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_MAC_SPI_SYS_5 + description: BLOCK1 data register 5. + addressOffset: 88 + size: 32 + fields: + - name: SYS_DATA_PART0_2 + description: Stores the second 32 bits of the zeroth part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA0 + description: Register 0 of BLOCK2 (system). + addressOffset: 92 + size: 32 + fields: + - name: SYS_DATA_PART1_0 + description: Stores the zeroth 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA1 + description: Register 1 of BLOCK2 (system). + addressOffset: 96 + size: 32 + fields: + - name: SYS_DATA_PART1_1 + description: Stores the first 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA2 + description: Register 2 of BLOCK2 (system). + addressOffset: 100 + size: 32 + fields: + - name: SYS_DATA_PART1_2 + description: Stores the second 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA3 + description: Register 3 of BLOCK2 (system). + addressOffset: 104 + size: 32 + fields: + - name: SYS_DATA_PART1_3 + description: Stores the third 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA4 + description: Register 4 of BLOCK2 (system). + addressOffset: 108 + size: 32 + fields: + - name: SYS_DATA_PART1_4 + description: Stores the fourth 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA5 + description: Register 5 of BLOCK2 (system). + addressOffset: 112 + size: 32 + fields: + - name: SYS_DATA_PART1_5 + description: Stores the fifth 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA6 + description: Register 6 of BLOCK2 (system). + addressOffset: 116 + size: 32 + fields: + - name: SYS_DATA_PART1_6 + description: Stores the sixth 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART1_DATA7 + description: Register 7 of BLOCK2 (system). + addressOffset: 120 + size: 32 + fields: + - name: SYS_DATA_PART1_7 + description: Stores the seventh 32 bits of the first part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA0 + description: Register 0 of BLOCK3 (user). + addressOffset: 124 + size: 32 + fields: + - name: USR_DATA0 + description: Stores the zeroth 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA1 + description: Register 1 of BLOCK3 (user). + addressOffset: 128 + size: 32 + fields: + - name: USR_DATA1 + description: Stores the first 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA2 + description: Register 2 of BLOCK3 (user). + addressOffset: 132 + size: 32 + fields: + - name: USR_DATA2 + description: Stores the second 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA3 + description: Register 3 of BLOCK3 (user). + addressOffset: 136 + size: 32 + fields: + - name: USR_DATA3 + description: Stores the third 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA4 + description: Register 4 of BLOCK3 (user). + addressOffset: 140 + size: 32 + fields: + - name: USR_DATA4 + description: Stores the fourth 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA5 + description: Register 5 of BLOCK3 (user). + addressOffset: 144 + size: 32 + fields: + - name: USR_DATA5 + description: Stores the fifth 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA6 + description: Register 6 of BLOCK3 (user). + addressOffset: 148 + size: 32 + fields: + - name: USR_DATA6 + description: Stores the sixth 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_USR_DATA7 + description: Register 7 of BLOCK3 (user). + addressOffset: 152 + size: 32 + fields: + - name: USR_DATA7 + description: Stores the seventh 32 bits of BLOCK3 (user). + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA0 + description: Register 0 of BLOCK4 (KEY0). + addressOffset: 156 + size: 32 + fields: + - name: KEY0_DATA0 + description: Stores the zeroth 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA1 + description: Register 1 of BLOCK4 (KEY0). + addressOffset: 160 + size: 32 + fields: + - name: KEY0_DATA1 + description: Stores the first 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA2 + description: Register 2 of BLOCK4 (KEY0). + addressOffset: 164 + size: 32 + fields: + - name: KEY0_DATA2 + description: Stores the second 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA3 + description: Register 3 of BLOCK4 (KEY0). + addressOffset: 168 + size: 32 + fields: + - name: KEY0_DATA3 + description: Stores the third 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA4 + description: Register 4 of BLOCK4 (KEY0). + addressOffset: 172 + size: 32 + fields: + - name: KEY0_DATA4 + description: Stores the fourth 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA5 + description: Register 5 of BLOCK4 (KEY0). + addressOffset: 176 + size: 32 + fields: + - name: KEY0_DATA5 + description: Stores the fifth 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA6 + description: Register 6 of BLOCK4 (KEY0). + addressOffset: 180 + size: 32 + fields: + - name: KEY0_DATA6 + description: Stores the sixth 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY0_DATA7 + description: Register 7 of BLOCK4 (KEY0). + addressOffset: 184 + size: 32 + fields: + - name: KEY0_DATA7 + description: Stores the seventh 32 bits of KEY0. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA0 + description: Register 0 of BLOCK5 (KEY1). + addressOffset: 188 + size: 32 + fields: + - name: KEY1_DATA0 + description: Stores the zeroth 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA1 + description: Register 1 of BLOCK5 (KEY1). + addressOffset: 192 + size: 32 + fields: + - name: KEY1_DATA1 + description: Stores the first 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA2 + description: Register 2 of BLOCK5 (KEY1). + addressOffset: 196 + size: 32 + fields: + - name: KEY1_DATA2 + description: Stores the second 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA3 + description: Register 3 of BLOCK5 (KEY1). + addressOffset: 200 + size: 32 + fields: + - name: KEY1_DATA3 + description: Stores the third 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA4 + description: Register 4 of BLOCK5 (KEY1). + addressOffset: 204 + size: 32 + fields: + - name: KEY1_DATA4 + description: Stores the fourth 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA5 + description: Register 5 of BLOCK5 (KEY1). + addressOffset: 208 + size: 32 + fields: + - name: KEY1_DATA5 + description: Stores the fifth 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA6 + description: Register 6 of BLOCK5 (KEY1). + addressOffset: 212 + size: 32 + fields: + - name: KEY1_DATA6 + description: Stores the sixth 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY1_DATA7 + description: Register 7 of BLOCK5 (KEY1). + addressOffset: 216 + size: 32 + fields: + - name: KEY1_DATA7 + description: Stores the seventh 32 bits of KEY1. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA0 + description: Register 0 of BLOCK6 (KEY2). + addressOffset: 220 + size: 32 + fields: + - name: KEY2_DATA0 + description: Stores the zeroth 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA1 + description: Register 1 of BLOCK6 (KEY2). + addressOffset: 224 + size: 32 + fields: + - name: KEY2_DATA1 + description: Stores the first 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA2 + description: Register 2 of BLOCK6 (KEY2). + addressOffset: 228 + size: 32 + fields: + - name: KEY2_DATA2 + description: Stores the second 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA3 + description: Register 3 of BLOCK6 (KEY2). + addressOffset: 232 + size: 32 + fields: + - name: KEY2_DATA3 + description: Stores the third 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA4 + description: Register 4 of BLOCK6 (KEY2). + addressOffset: 236 + size: 32 + fields: + - name: KEY2_DATA4 + description: Stores the fourth 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA5 + description: Register 5 of BLOCK6 (KEY2). + addressOffset: 240 + size: 32 + fields: + - name: KEY2_DATA5 + description: Stores the fifth 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA6 + description: Register 6 of BLOCK6 (KEY2). + addressOffset: 244 + size: 32 + fields: + - name: KEY2_DATA6 + description: Stores the sixth 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY2_DATA7 + description: Register 7 of BLOCK6 (KEY2). + addressOffset: 248 + size: 32 + fields: + - name: KEY2_DATA7 + description: Stores the seventh 32 bits of KEY2. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA0 + description: Register 0 of BLOCK7 (KEY3). + addressOffset: 252 + size: 32 + fields: + - name: KEY3_DATA0 + description: Stores the zeroth 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA1 + description: Register 1 of BLOCK7 (KEY3). + addressOffset: 256 + size: 32 + fields: + - name: KEY3_DATA1 + description: Stores the first 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA2 + description: Register 2 of BLOCK7 (KEY3). + addressOffset: 260 + size: 32 + fields: + - name: KEY3_DATA2 + description: Stores the second 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA3 + description: Register 3 of BLOCK7 (KEY3). + addressOffset: 264 + size: 32 + fields: + - name: KEY3_DATA3 + description: Stores the third 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA4 + description: Register 4 of BLOCK7 (KEY3). + addressOffset: 268 + size: 32 + fields: + - name: KEY3_DATA4 + description: Stores the fourth 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA5 + description: Register 5 of BLOCK7 (KEY3). + addressOffset: 272 + size: 32 + fields: + - name: KEY3_DATA5 + description: Stores the fifth 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA6 + description: Register 6 of BLOCK7 (KEY3). + addressOffset: 276 + size: 32 + fields: + - name: KEY3_DATA6 + description: Stores the sixth 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY3_DATA7 + description: Register 7 of BLOCK7 (KEY3). + addressOffset: 280 + size: 32 + fields: + - name: KEY3_DATA7 + description: Stores the seventh 32 bits of KEY3. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA0 + description: Register 0 of BLOCK8 (KEY4). + addressOffset: 284 + size: 32 + fields: + - name: KEY4_DATA0 + description: Stores the zeroth 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA1 + description: Register 1 of BLOCK8 (KEY4). + addressOffset: 288 + size: 32 + fields: + - name: KEY4_DATA1 + description: Stores the first 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA2 + description: Register 2 of BLOCK8 (KEY4). + addressOffset: 292 + size: 32 + fields: + - name: KEY4_DATA2 + description: Stores the second 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA3 + description: Register 3 of BLOCK8 (KEY4). + addressOffset: 296 + size: 32 + fields: + - name: KEY4_DATA3 + description: Stores the third 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA4 + description: Register 4 of BLOCK8 (KEY4). + addressOffset: 300 + size: 32 + fields: + - name: KEY4_DATA4 + description: Stores the fourth 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA5 + description: Register 5 of BLOCK8 (KEY4). + addressOffset: 304 + size: 32 + fields: + - name: KEY4_DATA5 + description: Stores the fifth 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA6 + description: Register 6 of BLOCK8 (KEY4). + addressOffset: 308 + size: 32 + fields: + - name: KEY4_DATA6 + description: Stores the sixth 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY4_DATA7 + description: Register 7 of BLOCK8 (KEY4). + addressOffset: 312 + size: 32 + fields: + - name: KEY4_DATA7 + description: Stores the seventh 32 bits of KEY4. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA0 + description: Register 0 of BLOCK9 (KEY5). + addressOffset: 316 + size: 32 + fields: + - name: KEY5_DATA0 + description: Stores the zeroth 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA1 + description: Register 1 of BLOCK9 (KEY5). + addressOffset: 320 + size: 32 + fields: + - name: KEY5_DATA1 + description: Stores the first 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA2 + description: Register 2 of BLOCK9 (KEY5). + addressOffset: 324 + size: 32 + fields: + - name: KEY5_DATA2 + description: Stores the second 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA3 + description: Register 3 of BLOCK9 (KEY5). + addressOffset: 328 + size: 32 + fields: + - name: KEY5_DATA3 + description: Stores the third 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA4 + description: Register 4 of BLOCK9 (KEY5). + addressOffset: 332 + size: 32 + fields: + - name: KEY5_DATA4 + description: Stores the fourth 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA5 + description: Register 5 of BLOCK9 (KEY5). + addressOffset: 336 + size: 32 + fields: + - name: KEY5_DATA5 + description: Stores the fifth 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA6 + description: Register 6 of BLOCK9 (KEY5). + addressOffset: 340 + size: 32 + fields: + - name: KEY5_DATA6 + description: Stores the sixth 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_KEY5_DATA7 + description: Register 7 of BLOCK9 (KEY5). + addressOffset: 344 + size: 32 + fields: + - name: KEY5_DATA7 + description: Stores the seventh 32 bits of KEY5. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA0 + description: Register 0 of BLOCK10 (system). + addressOffset: 348 + size: 32 + fields: + - name: SYS_DATA_PART2_0 + description: Stores the 0th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA1 + description: Register 1 of BLOCK9 (KEY5). + addressOffset: 352 + size: 32 + fields: + - name: SYS_DATA_PART2_1 + description: Stores the 1st 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA2 + description: Register 2 of BLOCK10 (system). + addressOffset: 356 + size: 32 + fields: + - name: SYS_DATA_PART2_2 + description: Stores the 2nd 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA3 + description: Register 3 of BLOCK10 (system). + addressOffset: 360 + size: 32 + fields: + - name: SYS_DATA_PART2_3 + description: Stores the 3rd 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA4 + description: Register 4 of BLOCK10 (system). + addressOffset: 364 + size: 32 + fields: + - name: SYS_DATA_PART2_4 + description: Stores the 4th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA5 + description: Register 5 of BLOCK10 (system). + addressOffset: 368 + size: 32 + fields: + - name: SYS_DATA_PART2_5 + description: Stores the 5th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA6 + description: Register 6 of BLOCK10 (system). + addressOffset: 372 + size: 32 + fields: + - name: SYS_DATA_PART2_6 + description: Stores the 6th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_SYS_PART2_DATA7 + description: Register 7 of BLOCK10 (system). + addressOffset: 376 + size: 32 + fields: + - name: SYS_DATA_PART2_7 + description: Stores the 7th 32 bits of the 2nd part of system data. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RD_REPEAT_ERR0 + description: Programming error record register 0 of BLOCK0. + addressOffset: 380 + size: 32 + fields: + - name: RD_DIS_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 0 + bitWidth: 7 + access: read-only + - name: DIS_RTC_RAM_BOOT_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DIS_ICACHE_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DIS_DCACHE_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_ICACHE_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_DCACHE_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: DIS_FORCE_DOWNLOAD_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: DIS_USB_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: DIS_CAN_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DIS_APP_CPU_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SOFT_DIS_JTAG_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: DIS_PAD_JTAG_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: USB_DREFH_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 21 + bitWidth: 2 + access: read-only + - name: USB_DREFL_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 23 + bitWidth: 2 + access: read-only + - name: USB_EXCHG_PINS_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: EXT_PHY_ENABLE_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: BTLC_GPIO_ENABLE_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 27 + bitWidth: 2 + access: read-only + - name: VDD_SPI_MODECURLIM_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: VDD_SPI_DREFH_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 30 + bitWidth: 2 + access: read-only + - register: + name: RD_REPEAT_ERR1 + description: Programming error record register 1 of BLOCK0. + addressOffset: 384 + size: 32 + fields: + - name: VDD_SPI_DREFM_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: VDD_SPI_DREFL_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 2 + bitWidth: 2 + access: read-only + - name: VDD_SPI_XPD_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: VDD_SPI_TIEH_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: VDD_SPI_FORCE_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: VDD_SPI_EN_INIT_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: VDD_SPI_ENCURLIM_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: VDD_SPI_DCURLIM_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 9 + bitWidth: 3 + access: read-only + - name: VDD_SPI_INIT_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 12 + bitWidth: 2 + access: read-only + - name: VDD_SPI_DCAP_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 14 + bitWidth: 2 + access: read-only + - name: WDT_DELAY_SEL_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 16 + bitWidth: 2 + access: read-only + - name: SPI_BOOT_CRYPT_CNT_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 18 + bitWidth: 3 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE0_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE1_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_KEY_REVOKE2_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: KEY_PURPOSE_0_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 24 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_1_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_REPEAT_ERR2 + description: Programming error record register 2 of BLOCK0. + addressOffset: 388 + size: 32 + fields: + - name: KEY_PURPOSE_2_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_3_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_4_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 8 + bitWidth: 4 + access: read-only + - name: KEY_PURPOSE_5_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 12 + bitWidth: 4 + access: read-only + - name: RPT4_RESERVED0_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 16 + bitWidth: 4 + access: read-only + - name: SECURE_BOOT_EN_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: SECURE_BOOT_AGGRESSIVE_REVOKE_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: DIS_USB_JTAG_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: DIS_USB_DEVICE_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: STRAP_JTAG_SEL_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: USB_PHY_SEL_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: POWER_GLITCH_DSENSE_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 26 + bitWidth: 2 + access: read-only + - name: FLASH_TPUW_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: RD_REPEAT_ERR3 + description: Programming error record register 3 of BLOCK0. + addressOffset: 392 + size: 32 + fields: + - name: DIS_DOWNLOAD_MODE_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DIS_LEGACY_SPI_BOOT_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: UART_PRINT_CHANNEL_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FLASH_ECC_MODE_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DIS_USB_DOWNLOAD_MODE_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ENABLE_SECURITY_DOWNLOAD_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: UART_PRINT_CONTROL_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: PIN_POWER_SELECTION_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: FLASH_TYPE_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: FLASH_PAGE_SIZE_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 10 + bitWidth: 2 + access: read-only + - name: FLASH_ECC_EN_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: FORCE_SEND_RESUME_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SECURE_VERSION_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 14 + bitWidth: 16 + access: read-only + - name: POWERGLITCH_EN_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: RPT4_RESERVED1_ERR + description: Reserved. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: RD_REPEAT_ERR4 + description: Programming error record register 4 of BLOCK0. + addressOffset: 400 + size: 32 + fields: + - name: RPT4_RESERVED2_ERR + description: "If any bits in this filed are 1, then it indicates a programming error." + bitOffset: 0 + bitWidth: 24 + access: read-only + - register: + name: RD_RS_ERR0 + description: Programming error record register 0 of BLOCK1-10. + addressOffset: 448 + size: 32 + fields: + - name: MAC_SPI_8M_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: MAC_SPI_8M_FAIL + description: "0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SYS_PART1_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 4 + bitWidth: 3 + access: read-only + - name: SYS_PART1_FAIL + description: "0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: USR_DATA_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 8 + bitWidth: 3 + access: read-only + - name: USR_DATA_FAIL + description: "0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: KEY0_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 12 + bitWidth: 3 + access: read-only + - name: KEY0_FAIL + description: "0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6." + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: KEY1_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 16 + bitWidth: 3 + access: read-only + - name: KEY1_FAIL + description: "0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6." + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: KEY2_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 20 + bitWidth: 3 + access: read-only + - name: KEY2_FAIL + description: "0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6." + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: KEY3_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 24 + bitWidth: 3 + access: read-only + - name: KEY3_FAIL + description: "0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6." + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: KEY4_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 28 + bitWidth: 3 + access: read-only + - name: KEY4_FAIL + description: "0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6." + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: RD_RS_ERR1 + description: Programming error record register 1 of BLOCK1-10. + addressOffset: 452 + size: 32 + fields: + - name: KEY5_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: KEY5_FAIL + description: "0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SYS_PART2_ERR_NUM + description: The value of this signal means the number of error bytes. + bitOffset: 4 + bitWidth: 3 + access: read-only + - name: SYS_PART2_FAIL + description: "0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6." + bitOffset: 7 + bitWidth: 1 + access: read-only + - register: + name: CLK + description: eFuse clcok configuration register. + addressOffset: 456 + size: 32 + resetValue: 2 + fields: + - name: EFUSE_MEM_FORCE_PD + description: Set this bit to force eFuse SRAM into power-saving mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_CLK_FORCE_ON + description: Set this bit and force to activate clock signal of eFuse SRAM. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EFUSE_MEM_FORCE_PU + description: Set this bit to force eFuse SRAM into working mode. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: EN + description: Set this bit and force to enable clock signal of eFuse memory. + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: CONF + description: eFuse operation mode configuraiton register + addressOffset: 460 + size: 32 + fields: + - name: OP_CODE + description: "0x5A5A: Operate programming command 0x5AA5: Operate read command." + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: STATUS + description: eFuse status register. + addressOffset: 464 + size: 32 + fields: + - name: STATE + description: Indicates the state of the eFuse state machine. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: OTP_LOAD_SW + description: The value of OTP_LOAD_SW. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: OTP_VDDQ_C_SYNC2 + description: The value of OTP_VDDQ_C_SYNC2. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OTP_STROBE_SW + description: The value of OTP_STROBE_SW. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OTP_CSB_SW + description: The value of OTP_CSB_SW. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: OTP_PGENB_SW + description: The value of OTP_PGENB_SW. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: OTP_VDDQ_IS_SW + description: The value of OTP_VDDQ_IS_SW. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: REPEAT_ERR_CNT + description: Indicates the number of error bits during programming BLOCK0. + bitOffset: 10 + bitWidth: 8 + access: read-only + - register: + name: CMD + description: eFuse command register. + addressOffset: 468 + size: 32 + fields: + - name: READ_CMD + description: Set this bit to send read command. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PGM_CMD + description: Set this bit to send programming command. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BLK_NUM + description: "The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively." + bitOffset: 2 + bitWidth: 4 + access: read-write + - register: + name: INT_RAW + description: eFuse raw interrupt register. + addressOffset: 472 + size: 32 + fields: + - name: READ_DONE_INT_RAW + description: The raw bit signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PGM_DONE_INT_RAW + description: The raw bit signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: eFuse interrupt status register. + addressOffset: 476 + size: 32 + fields: + - name: READ_DONE_INT_ST + description: The status signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PGM_DONE_INT_ST + description: The status signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: eFuse interrupt enable register. + addressOffset: 480 + size: 32 + fields: + - name: READ_DONE_INT_ENA + description: The enable signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PGM_DONE_INT_ENA + description: The enable signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: eFuse interrupt clear register. + addressOffset: 484 + size: 32 + fields: + - name: READ_DONE_INT_CLR + description: The clear signal for read_done interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: PGM_DONE_INT_CLR + description: The clear signal for pgm_done interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: DAC_CONF + description: Controls the eFuse programming voltage. + addressOffset: 488 + size: 32 + resetValue: 130588 + fields: + - name: DAC_CLK_DIV + description: Controls the division factor of the rising clock of the programming voltage. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: DAC_CLK_PAD_SEL + description: "Don't care." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DAC_NUM + description: Controls the rising period of the programming voltage. + bitOffset: 9 + bitWidth: 8 + access: read-write + - name: OE_CLR + description: Reduces the power supply of the programming voltage. + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: RD_TIM_CONF + description: Configures read timing parameters. + addressOffset: 492 + size: 32 + resetValue: 301989888 + fields: + - name: READ_INIT_NUM + description: Configures the initial read time of eFuse. + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: WR_TIM_CONF1 + description: Configurarion register 1 of eFuse programming timing parameters. + addressOffset: 500 + size: 32 + resetValue: 2654208 + fields: + - name: PWR_ON_NUM + description: Configures the power up time for VDDQ. + bitOffset: 8 + bitWidth: 16 + access: read-write + - register: + name: WR_TIM_CONF2 + description: Configurarion register 2 of eFuse programming timing parameters. + addressOffset: 504 + size: 32 + resetValue: 400 + fields: + - name: PWR_OFF_NUM + description: Configures the power outage time for VDDQ. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: DATE + description: eFuse version register. + addressOffset: 508 + size: 32 + resetValue: 34607760 + fields: + - name: DATE + description: Stores eFuse version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: EXTMEM + description: External Memory + groupName: EXTMEM + baseAddress: 1611415552 + addressBlock: + - offset: 0 + size: 380 + usage: registers + registers: + - register: + name: DCACHE_CTRL + description: "******* Description ***********" + addressOffset: 0 + size: 32 + fields: + - name: DCACHE_ENABLE + description: "The bit is used to activate the data cache. 0: disable, 1: enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DCACHE_SIZE_MODE + description: "The bit is used to configure cache memory size.0: 32KB, 1: 64KB" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DCACHE_BLOCKSIZE_MODE + description: "The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 bytes" + bitOffset: 3 + bitWidth: 2 + access: read-write + - register: + name: DCACHE_CTRL1 + description: "******* Description ***********" + addressOffset: 4 + size: 32 + resetValue: 3 + fields: + - name: DCACHE_SHUT_CORE0_BUS + description: "The bit is used to disable core0 dbus, 0: enable, 1: disable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DCACHE_SHUT_CORE1_BUS + description: "The bit is used to disable core1 dbus, 0: enable, 1: disable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: DCACHE_TAG_POWER_CTRL + description: "******* Description ***********" + addressOffset: 8 + size: 32 + resetValue: 5 + fields: + - name: DCACHE_TAG_MEM_FORCE_ON + description: "The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DCACHE_TAG_MEM_FORCE_PD + description: "The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: power down" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DCACHE_TAG_MEM_FORCE_PU + description: "The bit is used to power dcache tag memory up, 0: follow rtc_lslp_pd, 1: power up" + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: DCACHE_PRELOCK_CTRL + description: "******* Description ***********" + addressOffset: 12 + size: 32 + fields: + - name: DCACHE_PRELOCK_SCT0_EN + description: The bit is used to enable the first section of prelock function. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DCACHE_PRELOCK_SCT1_EN + description: The bit is used to enable the second section of prelock function. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: DCACHE_PRELOCK_SCT0_ADDR + description: "******* Description ***********" + addressOffset: 16 + size: 32 + fields: + - name: DCACHE_PRELOCK_SCT0_ADDR + description: "The bits are used to configure the first start virtual address of data prelock, which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DCACHE_PRELOCK_SCT1_ADDR + description: "******* Description ***********" + addressOffset: 20 + size: 32 + fields: + - name: DCACHE_PRELOCK_SCT1_ADDR + description: "The bits are used to configure the second start virtual address of data prelock, which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DCACHE_PRELOCK_SCT_SIZE + description: "******* Description ***********" + addressOffset: 24 + size: 32 + fields: + - name: DCACHE_PRELOCK_SCT1_SIZE + description: "The bits are used to configure the second length of data locking, which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG" + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: DCACHE_PRELOCK_SCT0_SIZE + description: "The bits are used to configure the first length of data locking, which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG" + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: DCACHE_LOCK_CTRL + description: "******* Description ***********" + addressOffset: 28 + size: 32 + resetValue: 4 + fields: + - name: DCACHE_LOCK_ENA + description: The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DCACHE_UNLOCK_ENA + description: The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DCACHE_LOCK_DONE + description: The bit is used to indicate unlock/lock operation is finished. + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: DCACHE_LOCK_ADDR + description: "******* Description ***********" + addressOffset: 32 + size: 32 + fields: + - name: DCACHE_LOCK_ADDR + description: The bits are used to configure the start virtual address for lock operations. It should be combined with DCACHE_LOCK_SIZE_REG. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DCACHE_LOCK_SIZE + description: "******* Description ***********" + addressOffset: 36 + size: 32 + fields: + - name: DCACHE_LOCK_SIZE + description: The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: DCACHE_SYNC_CTRL + description: "******* Description ***********" + addressOffset: 40 + size: 32 + resetValue: 1 + fields: + - name: DCACHE_INVALIDATE_ENA + description: The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DCACHE_WRITEBACK_ENA + description: The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DCACHE_CLEAN_ENA + description: The bit is used to enable clean operation. It will be cleared by hardware after clean operation done. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DCACHE_SYNC_DONE + description: The bit is used to indicate clean/writeback/invalidate operation is finished. + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: DCACHE_SYNC_ADDR + description: "******* Description ***********" + addressOffset: 44 + size: 32 + fields: + - name: DCACHE_SYNC_ADDR + description: The bits are used to configure the start virtual address for clean operations. It should be combined with DCACHE_SYNC_SIZE_REG. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DCACHE_SYNC_SIZE + description: "******* Description ***********" + addressOffset: 48 + size: 32 + fields: + - name: DCACHE_SYNC_SIZE + description: The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG. + bitOffset: 0 + bitWidth: 23 + access: read-write + - register: + name: DCACHE_OCCUPY_CTRL + description: "******* Description ***********" + addressOffset: 52 + size: 32 + resetValue: 2 + fields: + - name: DCACHE_OCCUPY_ENA + description: The bit is used to enable occupy operation. It will be cleared by hardware after issuing Auot-Invalidate Operation. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DCACHE_OCCUPY_DONE + description: The bit is used to indicate occupy operation is finished. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: DCACHE_OCCUPY_ADDR + description: "******* Description ***********" + addressOffset: 56 + size: 32 + fields: + - name: DCACHE_OCCUPY_ADDR + description: The bits are used to configure the start virtual address for occupy operation. It should be combined with DCACHE_OCCUPY_SIZE_REG. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DCACHE_OCCUPY_SIZE + description: "******* Description ***********" + addressOffset: 60 + size: 32 + fields: + - name: DCACHE_OCCUPY_SIZE + description: The bits are used to configure the length for occupy operation. The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: DCACHE_PRELOAD_CTRL + description: "******* Description ***********" + addressOffset: 64 + size: 32 + resetValue: 2 + fields: + - name: DCACHE_PRELOAD_ENA + description: The bit is used to enable preload operation. It will be cleared by hardware after preload operation done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DCACHE_PRELOAD_DONE + description: The bit is used to indicate preload operation is finished. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: DCACHE_PRELOAD_ORDER + description: "The bit is used to configure the direction of preload operation. 1: descending, 0: ascending." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: DCACHE_PRELOAD_ADDR + description: "******* Description ***********" + addressOffset: 68 + size: 32 + fields: + - name: DCACHE_PRELOAD_ADDR + description: The bits are used to configure the start virtual address for preload operation. It should be combined with DCACHE_PRELOAD_SIZE_REG. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DCACHE_PRELOAD_SIZE + description: "******* Description ***********" + addressOffset: 72 + size: 32 + fields: + - name: DCACHE_PRELOAD_SIZE + description: The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG.. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: DCACHE_AUTOLOAD_CTRL + description: "******* Description ***********" + addressOffset: 76 + size: 32 + resetValue: 8 + fields: + - name: DCACHE_AUTOLOAD_SCT0_ENA + description: The bits are used to enable the first section for autoload operation. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DCACHE_AUTOLOAD_SCT1_ENA + description: The bits are used to enable the second section for autoload operation. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DCACHE_AUTOLOAD_ENA + description: "The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable, 0: disable." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DCACHE_AUTOLOAD_DONE + description: The bit is used to indicate autoload operation is finished. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DCACHE_AUTOLOAD_ORDER + description: "The bits are used to configure the direction of autoload. 1: descending, 0: ascending." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DCACHE_AUTOLOAD_RQST + description: "The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit." + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: DCACHE_AUTOLOAD_SIZE + description: The bits are used to configure the numbers of the cache block for the issuing autoload operation. + bitOffset: 7 + bitWidth: 2 + access: read-write + - name: DCACHE_AUTOLOAD_BUFFER_CLEAR + description: The bit is used to clear autoload buffer in dcache. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: DCACHE_AUTOLOAD_SCT0_ADDR + description: "******* Description ***********" + addressOffset: 80 + size: 32 + fields: + - name: DCACHE_AUTOLOAD_SCT0_ADDR + description: The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DCACHE_AUTOLOAD_SCT0_SIZE + description: "******* Description ***********" + addressOffset: 84 + size: 32 + fields: + - name: DCACHE_AUTOLOAD_SCT0_SIZE + description: The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena. + bitOffset: 0 + bitWidth: 27 + access: read-write + - register: + name: DCACHE_AUTOLOAD_SCT1_ADDR + description: "******* Description ***********" + addressOffset: 88 + size: 32 + fields: + - name: DCACHE_AUTOLOAD_SCT1_ADDR + description: The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DCACHE_AUTOLOAD_SCT1_SIZE + description: "******* Description ***********" + addressOffset: 92 + size: 32 + fields: + - name: DCACHE_AUTOLOAD_SCT1_SIZE + description: The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena. + bitOffset: 0 + bitWidth: 27 + access: read-write + - register: + name: ICACHE_CTRL + description: "******* Description ***********" + addressOffset: 96 + size: 32 + fields: + - name: ICACHE_ENABLE + description: "The bit is used to activate the data cache. 0: disable, 1: enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ICACHE_WAY_MODE + description: "The bit is used to configure cache way mode.0: 4-way, 1: 8-way" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ICACHE_SIZE_MODE + description: "The bit is used to configure cache memory size.0: 16KB, 1: 32KB" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ICACHE_BLOCKSIZE_MODE + description: "The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes" + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: ICACHE_CTRL1 + description: "******* Description ***********" + addressOffset: 100 + size: 32 + resetValue: 3 + fields: + - name: ICACHE_SHUT_CORE0_BUS + description: "The bit is used to disable core0 ibus, 0: enable, 1: disable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ICACHE_SHUT_CORE1_BUS + description: "The bit is used to disable core1 ibus, 0: enable, 1: disable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: ICACHE_TAG_POWER_CTRL + description: "******* Description ***********" + addressOffset: 104 + size: 32 + resetValue: 5 + fields: + - name: ICACHE_TAG_MEM_FORCE_ON + description: "The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ICACHE_TAG_MEM_FORCE_PD + description: "The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ICACHE_TAG_MEM_FORCE_PU + description: "The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up" + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: ICACHE_PRELOCK_CTRL + description: "******* Description ***********" + addressOffset: 108 + size: 32 + fields: + - name: ICACHE_PRELOCK_SCT0_EN + description: The bit is used to enable the first section of prelock function. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ICACHE_PRELOCK_SCT1_EN + description: The bit is used to enable the second section of prelock function. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: ICACHE_PRELOCK_SCT0_ADDR + description: "******* Description ***********" + addressOffset: 112 + size: 32 + fields: + - name: ICACHE_PRELOCK_SCT0_ADDR + description: "The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ICACHE_PRELOCK_SCT1_ADDR + description: "******* Description ***********" + addressOffset: 116 + size: 32 + fields: + - name: ICACHE_PRELOCK_SCT1_ADDR + description: "The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ICACHE_PRELOCK_SCT_SIZE + description: "******* Description ***********" + addressOffset: 120 + size: 32 + fields: + - name: ICACHE_PRELOCK_SCT1_SIZE + description: "The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG" + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: ICACHE_PRELOCK_SCT0_SIZE + description: "The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG" + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: ICACHE_LOCK_CTRL + description: "******* Description ***********" + addressOffset: 124 + size: 32 + resetValue: 4 + fields: + - name: ICACHE_LOCK_ENA + description: The bit is used to enable lock operation. It will be cleared by hardware after lock operation done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ICACHE_UNLOCK_ENA + description: The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ICACHE_LOCK_DONE + description: The bit is used to indicate unlock/lock operation is finished. + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: ICACHE_LOCK_ADDR + description: "******* Description ***********" + addressOffset: 128 + size: 32 + fields: + - name: ICACHE_LOCK_ADDR + description: The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ICACHE_LOCK_SIZE + description: "******* Description ***********" + addressOffset: 132 + size: 32 + fields: + - name: ICACHE_LOCK_SIZE + description: The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: ICACHE_SYNC_CTRL + description: "******* Description ***********" + addressOffset: 136 + size: 32 + resetValue: 1 + fields: + - name: ICACHE_INVALIDATE_ENA + description: The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ICACHE_SYNC_DONE + description: The bit is used to indicate invalidate operation is finished. + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: ICACHE_SYNC_ADDR + description: "******* Description ***********" + addressOffset: 140 + size: 32 + fields: + - name: ICACHE_SYNC_ADDR + description: The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ICACHE_SYNC_SIZE + description: "******* Description ***********" + addressOffset: 144 + size: 32 + fields: + - name: ICACHE_SYNC_SIZE + description: The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG. + bitOffset: 0 + bitWidth: 23 + access: read-write + - register: + name: ICACHE_PRELOAD_CTRL + description: "******* Description ***********" + addressOffset: 148 + size: 32 + resetValue: 2 + fields: + - name: ICACHE_PRELOAD_ENA + description: The bit is used to enable preload operation. It will be cleared by hardware after preload operation done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ICACHE_PRELOAD_DONE + description: The bit is used to indicate preload operation is finished. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ICACHE_PRELOAD_ORDER + description: "The bit is used to configure the direction of preload operation. 1: descending, 0: ascending." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: ICACHE_PRELOAD_ADDR + description: "******* Description ***********" + addressOffset: 152 + size: 32 + fields: + - name: ICACHE_PRELOAD_ADDR + description: The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ICACHE_PRELOAD_SIZE + description: "******* Description ***********" + addressOffset: 156 + size: 32 + fields: + - name: ICACHE_PRELOAD_SIZE + description: The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG.. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: ICACHE_AUTOLOAD_CTRL + description: "******* Description ***********" + addressOffset: 160 + size: 32 + resetValue: 8 + fields: + - name: ICACHE_AUTOLOAD_SCT0_ENA + description: The bits are used to enable the first section for autoload operation. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ICACHE_AUTOLOAD_SCT1_ENA + description: The bits are used to enable the second section for autoload operation. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ICACHE_AUTOLOAD_ENA + description: "The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ICACHE_AUTOLOAD_DONE + description: The bit is used to indicate autoload operation is finished. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: ICACHE_AUTOLOAD_ORDER + description: "The bits are used to configure the direction of autoload. 1: descending, 0: ascending." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ICACHE_AUTOLOAD_RQST + description: "The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit." + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: ICACHE_AUTOLOAD_SIZE + description: The bits are used to configure the numbers of the cache block for the issuing autoload operation. + bitOffset: 7 + bitWidth: 2 + access: read-write + - name: ICACHE_AUTOLOAD_BUFFER_CLEAR + description: The bit is used to clear autoload buffer in icache. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: ICACHE_AUTOLOAD_SCT0_ADDR + description: "******* Description ***********" + addressOffset: 164 + size: 32 + fields: + - name: ICACHE_AUTOLOAD_SCT0_ADDR + description: The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ICACHE_AUTOLOAD_SCT0_SIZE + description: "******* Description ***********" + addressOffset: 168 + size: 32 + fields: + - name: ICACHE_AUTOLOAD_SCT0_SIZE + description: The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena. + bitOffset: 0 + bitWidth: 27 + access: read-write + - register: + name: ICACHE_AUTOLOAD_SCT1_ADDR + description: "******* Description ***********" + addressOffset: 172 + size: 32 + fields: + - name: ICACHE_AUTOLOAD_SCT1_ADDR + description: The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ICACHE_AUTOLOAD_SCT1_SIZE + description: "******* Description ***********" + addressOffset: 176 + size: 32 + fields: + - name: ICACHE_AUTOLOAD_SCT1_SIZE + description: The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena. + bitOffset: 0 + bitWidth: 27 + access: read-write + - register: + name: IBUS_TO_FLASH_START_VADDR + description: "******* Description ***********" + addressOffset: 180 + size: 32 + resetValue: 1140850688 + fields: + - name: IBUS_TO_FLASH_START_VADDR + description: The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: IBUS_TO_FLASH_END_VADDR + description: "******* Description ***********" + addressOffset: 184 + size: 32 + resetValue: 1207959551 + fields: + - name: IBUS_TO_FLASH_END_VADDR + description: The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DBUS_TO_FLASH_START_VADDR + description: "******* Description ***********" + addressOffset: 188 + size: 32 + fields: + - name: DBUS_TO_FLASH_START_VADDR + description: The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DBUS_TO_FLASH_END_VADDR + description: "******* Description ***********" + addressOffset: 192 + size: 32 + fields: + - name: DBUS_TO_FLASH_END_VADDR + description: The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CACHE_ACS_CNT_CLR + description: "******* Description ***********" + addressOffset: 196 + size: 32 + fields: + - name: DCACHE_ACS_CNT_CLR + description: The bit is used to clear dcache counter. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ICACHE_ACS_CNT_CLR + description: The bit is used to clear icache counter. + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: IBUS_ACS_MISS_CNT + description: "******* Description ***********" + addressOffset: 200 + size: 32 + fields: + - name: IBUS_ACS_MISS_CNT + description: The bits are used to count the number of the cache miss caused by ibus access flash/spiram. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: IBUS_ACS_CNT + description: "******* Description ***********" + addressOffset: 204 + size: 32 + fields: + - name: IBUS_ACS_CNT + description: The bits are used to count the number of ibus access flash/spiram through icache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DBUS_ACS_FLASH_MISS_CNT + description: "******* Description ***********" + addressOffset: 208 + size: 32 + fields: + - name: DBUS_ACS_FLASH_MISS_CNT + description: The bits are used to count the number of the cache miss caused by dbus access flash. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DBUS_ACS_SPIRAM_MISS_CNT + description: "******* Description ***********" + addressOffset: 212 + size: 32 + fields: + - name: DBUS_ACS_SPIRAM_MISS_CNT + description: The bits are used to count the number of the cache miss caused by dbus access spiram. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DBUS_ACS_CNT + description: "******* Description ***********" + addressOffset: 216 + size: 32 + fields: + - name: DBUS_ACS_CNT + description: The bits are used to count the number of dbus access flash/spiram through dcache. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CACHE_ILG_INT_ENA + description: "******* Description ***********" + addressOffset: 220 + size: 32 + fields: + - name: ICACHE_SYNC_OP_FAULT_INT_ENA + description: The bit is used to enable interrupt by sync configurations fault. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ICACHE_PRELOAD_OP_FAULT_INT_ENA + description: The bit is used to enable interrupt by preload configurations fault. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DCACHE_SYNC_OP_FAULT_INT_ENA + description: The bit is used to enable interrupt by sync configurations fault. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DCACHE_PRELOAD_OP_FAULT_INT_ENA + description: The bit is used to enable interrupt by preload configurations fault. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DCACHE_WRITE_FLASH_INT_ENA + description: The bit is used to enable interrupt by dcache trying to write flash. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: MMU_ENTRY_FAULT_INT_ENA + description: The bit is used to enable interrupt by mmu entry fault. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DCACHE_OCCUPY_EXC_INT_ENA + description: The bit is used to enable interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: IBUS_CNT_OVF_INT_ENA + description: The bit is used to enable interrupt by ibus counter overflow. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DBUS_CNT_OVF_INT_ENA + description: The bit is used to enable interrupt by dbus counter overflow. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: CACHE_ILG_INT_CLR + description: "******* Description ***********" + addressOffset: 224 + size: 32 + fields: + - name: ICACHE_SYNC_OP_FAULT_INT_CLR + description: The bit is used to clear interrupt by sync configurations fault. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ICACHE_PRELOAD_OP_FAULT_INT_CLR + description: The bit is used to clear interrupt by preload configurations fault. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: DCACHE_SYNC_OP_FAULT_INT_CLR + description: The bit is used to clear interrupt by sync configurations fault. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: DCACHE_PRELOAD_OP_FAULT_INT_CLR + description: The bit is used to clear interrupt by preload configurations fault. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: DCACHE_WRITE_FLASH_INT_CLR + description: The bit is used to clear interrupt by dcache trying to write flash. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: MMU_ENTRY_FAULT_INT_CLR + description: The bit is used to clear interrupt by mmu entry fault. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: DCACHE_OCCUPY_EXC_INT_CLR + description: The bit is used to clear interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: IBUS_CNT_OVF_INT_CLR + description: The bit is used to clear interrupt by ibus counter overflow. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: DBUS_CNT_OVF_INT_CLR + description: The bit is used to clear interrupt by dbus counter overflow. + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: CACHE_ILG_INT_ST + description: "******* Description ***********" + addressOffset: 228 + size: 32 + fields: + - name: ICACHE_SYNC_OP_FAULT_ST + description: The bit is used to indicate interrupt by sync configurations fault. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ICACHE_PRELOAD_OP_FAULT_ST + description: The bit is used to indicate interrupt by preload configurations fault. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: DCACHE_SYNC_OP_FAULT_ST + description: The bit is used to indicate interrupt by sync configurations fault. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: DCACHE_PRELOAD_OP_FAULT_ST + description: The bit is used to indicate interrupt by preload configurations fault. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DCACHE_WRITE_FLASH_ST + description: The bit is used to indicate interrupt by dcache trying to write flash. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: MMU_ENTRY_FAULT_ST + description: The bit is used to indicate interrupt by mmu entry fault. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: DCACHE_OCCUPY_EXC_ST + description: The bit is used to indicate interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: IBUS_ACS_CNT_OVF_ST + description: The bit is used to indicate interrupt by ibus access flash/spiram counter overflow. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IBUS_ACS_MISS_CNT_OVF_ST + description: The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DBUS_ACS_CNT_OVF_ST + description: The bit is used to indicate interrupt by dbus access flash/spiram counter overflow. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: DBUS_ACS_FLASH_MISS_CNT_OVF_ST + description: The bit is used to indicate interrupt by dbus access flash miss counter overflow. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST + description: The bit is used to indicate interrupt by dbus access spiram miss counter overflow. + bitOffset: 11 + bitWidth: 1 + access: read-only + - register: + name: CORE0_ACS_CACHE_INT_ENA + description: "******* Description ***********" + addressOffset: 232 + size: 32 + fields: + - name: CORE0_IBUS_ACS_MSK_IC_INT_ENA + description: The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE0_IBUS_WR_IC_INT_ENA + description: The bit is used to enable interrupt by ibus trying to write icache + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CORE0_IBUS_REJECT_INT_ENA + description: The bit is used to enable interrupt by authentication fail. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CORE0_DBUS_ACS_MSK_DC_INT_ENA + description: The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CORE0_DBUS_REJECT_INT_ENA + description: The bit is used to enable interrupt by authentication fail. + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: CORE0_ACS_CACHE_INT_CLR + description: "******* Description ***********" + addressOffset: 236 + size: 32 + fields: + - name: CORE0_IBUS_ACS_MSK_IC_INT_CLR + description: The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CORE0_IBUS_WR_IC_INT_CLR + description: The bit is used to clear interrupt by ibus trying to write icache + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CORE0_IBUS_REJECT_INT_CLR + description: The bit is used to clear interrupt by authentication fail. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CORE0_DBUS_ACS_MSK_DC_INT_CLR + description: The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: CORE0_DBUS_REJECT_INT_CLR + description: The bit is used to clear interrupt by authentication fail. + bitOffset: 4 + bitWidth: 1 + access: write-only + - register: + name: CORE0_ACS_CACHE_INT_ST + description: "******* Description ***********" + addressOffset: 240 + size: 32 + fields: + - name: CORE0_IBUS_ACS_MSK_ICACHE_ST + description: The bit is used to indicate interrupt by cpu access icache while the core0_ibus is disabled or icache is disabled which include speculative access. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE0_IBUS_WR_ICACHE_ST + description: The bit is used to indicate interrupt by ibus trying to write icache + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CORE0_IBUS_REJECT_ST + description: The bit is used to indicate interrupt by authentication fail. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CORE0_DBUS_ACS_MSK_DCACHE_ST + description: The bit is used to indicate interrupt by cpu access dcache while the core0_dbus is disabled or dcache is disabled which include speculative access. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: CORE0_DBUS_REJECT_ST + description: The bit is used to indicate interrupt by authentication fail. + bitOffset: 4 + bitWidth: 1 + access: read-only + - register: + name: CORE1_ACS_CACHE_INT_ENA + description: "******* Description ***********" + addressOffset: 244 + size: 32 + fields: + - name: CORE1_IBUS_ACS_MSK_IC_INT_ENA + description: The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE1_IBUS_WR_IC_INT_ENA + description: The bit is used to enable interrupt by ibus trying to write icache + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CORE1_IBUS_REJECT_INT_ENA + description: The bit is used to enable interrupt by authentication fail. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CORE1_DBUS_ACS_MSK_DC_INT_ENA + description: The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CORE1_DBUS_REJECT_INT_ENA + description: The bit is used to enable interrupt by authentication fail. + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: CORE1_ACS_CACHE_INT_CLR + description: "******* Description ***********" + addressOffset: 248 + size: 32 + fields: + - name: CORE1_IBUS_ACS_MSK_IC_INT_CLR + description: The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CORE1_IBUS_WR_IC_INT_CLR + description: The bit is used to clear interrupt by ibus trying to write icache + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CORE1_IBUS_REJECT_INT_CLR + description: The bit is used to clear interrupt by authentication fail. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CORE1_DBUS_ACS_MSK_DC_INT_CLR + description: The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: CORE1_DBUS_REJECT_INT_CLR + description: The bit is used to clear interrupt by authentication fail. + bitOffset: 4 + bitWidth: 1 + access: write-only + - register: + name: CORE1_ACS_CACHE_INT_ST + description: "******* Description ***********" + addressOffset: 252 + size: 32 + fields: + - name: CORE1_IBUS_ACS_MSK_ICACHE_ST + description: The bit is used to indicate interrupt by cpu access icache while the core1_ibus is disabled or icache is disabled which include speculative access. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE1_IBUS_WR_ICACHE_ST + description: The bit is used to indicate interrupt by ibus trying to write icache + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CORE1_IBUS_REJECT_ST + description: The bit is used to indicate interrupt by authentication fail. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CORE1_DBUS_ACS_MSK_DCACHE_ST + description: The bit is used to indicate interrupt by cpu access dcache while the core1_dbus is disabled or dcache is disabled which include speculative access. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: CORE1_DBUS_REJECT_ST + description: The bit is used to indicate interrupt by authentication fail. + bitOffset: 4 + bitWidth: 1 + access: read-only + - register: + name: CORE0_DBUS_REJECT_ST + description: "******* Description ***********" + addressOffset: 256 + size: 32 + fields: + - name: CORE0_DBUS_TAG_ATTR + description: "The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able." + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: CORE0_DBUS_ATTR + description: "The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able." + bitOffset: 3 + bitWidth: 3 + access: read-only + - name: CORE0_DBUS_WORLD + description: "The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1" + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: CORE0_DBUS_REJECT_VADDR + description: "******* Description ***********" + addressOffset: 260 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE0_DBUS_VADDR + description: The bits are used to indicate the virtual address of CPU access dbus when authentication fail. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE0_IBUS_REJECT_ST + description: "******* Description ***********" + addressOffset: 264 + size: 32 + fields: + - name: CORE0_IBUS_TAG_ATTR + description: "The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able." + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: CORE0_IBUS_ATTR + description: "The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able" + bitOffset: 3 + bitWidth: 3 + access: read-only + - name: CORE0_IBUS_WORLD + description: "The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1" + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: CORE0_IBUS_REJECT_VADDR + description: "******* Description ***********" + addressOffset: 268 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE0_IBUS_VADDR + description: The bits are used to indicate the virtual address of CPU access ibus when authentication fail. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE1_DBUS_REJECT_ST + description: "******* Description ***********" + addressOffset: 272 + size: 32 + fields: + - name: CORE1_DBUS_TAG_ATTR + description: "The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able." + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: CORE1_DBUS_ATTR + description: "The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able." + bitOffset: 3 + bitWidth: 3 + access: read-only + - name: CORE1_DBUS_WORLD + description: "The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1" + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: CORE1_DBUS_REJECT_VADDR + description: "******* Description ***********" + addressOffset: 276 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE1_DBUS_VADDR + description: The bits are used to indicate the virtual address of CPU access dbus when authentication fail. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE1_IBUS_REJECT_ST + description: "******* Description ***********" + addressOffset: 280 + size: 32 + fields: + - name: CORE1_IBUS_TAG_ATTR + description: "The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able." + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: CORE1_IBUS_ATTR + description: "The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able" + bitOffset: 3 + bitWidth: 3 + access: read-only + - name: CORE1_IBUS_WORLD + description: "The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1" + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: CORE1_IBUS_REJECT_VADDR + description: "******* Description ***********" + addressOffset: 284 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE1_IBUS_VADDR + description: The bits are used to indicate the virtual address of CPU access ibus when authentication fail. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CACHE_MMU_FAULT_CONTENT + description: "******* Description ***********" + addressOffset: 288 + size: 32 + fields: + - name: CACHE_MMU_FAULT_CONTENT + description: The bits are used to indicate the content of mmu entry which cause mmu fault.. + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: CACHE_MMU_FAULT_CODE + description: "The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache." + bitOffset: 16 + bitWidth: 4 + access: read-only + - register: + name: CACHE_MMU_FAULT_VADDR + description: "******* Description ***********" + addressOffset: 292 + size: 32 + fields: + - name: CACHE_MMU_FAULT_VADDR + description: The bits are used to indicate the virtual address which cause mmu fault.. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CACHE_WRAP_AROUND_CTRL + description: "******* Description ***********" + addressOffset: 296 + size: 32 + fields: + - name: CACHE_FLASH_WRAP_AROUND + description: The bit is used to enable wrap around mode when read data from flash. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CACHE_SRAM_RD_WRAP_AROUND + description: The bit is used to enable wrap around mode when read data from spiram. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CACHE_MMU_POWER_CTRL + description: "******* Description ***********" + addressOffset: 300 + size: 32 + resetValue: 5 + fields: + - name: CACHE_MMU_MEM_FORCE_ON + description: "The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CACHE_MMU_MEM_FORCE_PD + description: "The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CACHE_MMU_MEM_FORCE_PU + description: "The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up" + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: CACHE_STATE + description: "******* Description ***********" + addressOffset: 304 + size: 32 + fields: + - name: ICACHE_STATE + description: "The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state" + bitOffset: 0 + bitWidth: 12 + access: read-only + - name: DCACHE_STATE + description: "The bit is used to indicate whether dcache main fsm is in idle state or not. 1: in idle state, 0: not in idle state" + bitOffset: 12 + bitWidth: 12 + access: read-only + - register: + name: CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE + description: "******* Description ***********" + addressOffset: 308 + size: 32 + fields: + - name: RECORD_DISABLE_DB_ENCRYPT + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RECORD_DISABLE_G0CB_DECRYPT + description: Reserved + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON + description: "******* Description ***********" + addressOffset: 312 + size: 32 + resetValue: 7 + fields: + - name: CLK_FORCE_ON_MANUAL_CRYPT + description: "The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CLK_FORCE_ON_AUTO_CRYPT + description: "The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CLK_FORCE_ON_CRYPT + description: "The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: CACHE_BRIDGE_ARBITER_CTRL + description: "******* Description ***********" + addressOffset: 316 + size: 32 + fields: + - name: ALLOC_WB_HOLD_ARBITER + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CACHE_PRELOAD_INT_CTRL + description: "******* Description ***********" + addressOffset: 320 + size: 32 + fields: + - name: ICACHE_PRELOAD_INT_ST + description: The bit is used to indicate the interrupt by icache pre-load done. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ICACHE_PRELOAD_INT_ENA + description: The bit is used to enable the interrupt by icache pre-load done. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ICACHE_PRELOAD_INT_CLR + description: The bit is used to clear the interrupt by icache pre-load done. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: DCACHE_PRELOAD_INT_ST + description: The bit is used to indicate the interrupt by dcache pre-load done. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DCACHE_PRELOAD_INT_ENA + description: The bit is used to enable the interrupt by dcache pre-load done. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DCACHE_PRELOAD_INT_CLR + description: The bit is used to clear the interrupt by dcache pre-load done. + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: CACHE_SYNC_INT_CTRL + description: "******* Description ***********" + addressOffset: 324 + size: 32 + fields: + - name: ICACHE_SYNC_INT_ST + description: The bit is used to indicate the interrupt by icache sync done. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ICACHE_SYNC_INT_ENA + description: The bit is used to enable the interrupt by icache sync done. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ICACHE_SYNC_INT_CLR + description: The bit is used to clear the interrupt by icache sync done. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: DCACHE_SYNC_INT_ST + description: The bit is used to indicate the interrupt by dcache sync done. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DCACHE_SYNC_INT_ENA + description: The bit is used to enable the interrupt by dcache sync done. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DCACHE_SYNC_INT_CLR + description: The bit is used to clear the interrupt by dcache sync done. + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: CACHE_MMU_OWNER + description: "******* Description ***********" + addressOffset: 328 + size: 32 + fields: + - name: CACHE_MMU_OWNER + description: "The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved." + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: CACHE_CONF_MISC + description: "******* Description ***********" + addressOffset: 332 + size: 32 + resetValue: 7 + fields: + - name: CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT + description: The bit is used to disable checking mmu entry fault by preload operation. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT + description: The bit is used to disable checking mmu entry fault by sync operation. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CACHE_TRACE_ENA + description: The bit is used to enable cache trace function. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: DCACHE_FREEZE + description: "******* Description ***********" + addressOffset: 336 + size: 32 + resetValue: 4 + fields: + - name: ENA + description: The bit is used to enable dcache freeze mode + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MODE + description: "The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DONE + description: The bit is used to indicate dcache freeze success + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: ICACHE_FREEZE + description: "******* Description ***********" + addressOffset: 340 + size: 32 + resetValue: 4 + fields: + - name: ENA + description: The bit is used to enable icache freeze mode + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MODE + description: "The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DONE + description: The bit is used to indicate icache freeze success + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: ICACHE_ATOMIC_OPERATE_ENA + description: "******* Description ***********" + addressOffset: 344 + size: 32 + resetValue: 1 + fields: + - name: ICACHE_ATOMIC_OPERATE_ENA + description: "The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DCACHE_ATOMIC_OPERATE_ENA + description: "******* Description ***********" + addressOffset: 348 + size: 32 + resetValue: 1 + fields: + - name: DCACHE_ATOMIC_OPERATE_ENA + description: "The bit is used to activate dcache atomic operation protection. In this case, sync/lock/occupy operation can not interrupt miss-work. This feature does not work during invalidateAll operation." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CACHE_REQUEST + description: "******* Description ***********" + addressOffset: 352 + size: 32 + fields: + - name: BYPASS + description: The bit is used to disable request recording which could cause performance issue + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CLOCK_GATE + description: "******* Description ***********" + addressOffset: 356 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CACHE_TAG_OBJECT_CTRL + description: "******* Description ***********" + addressOffset: 384 + size: 32 + fields: + - name: ICACHE_TAG_OBJECT + description: Set this bit to set icache tag memory as object. This bit should be onehot with the others fields inside this register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DCACHE_TAG_OBJECT + description: Set this bit to set dcache tag memory as object. This bit should be onehot with the others fields inside this register. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CACHE_TAG_WAY_OBJECT + description: "******* Description ***********" + addressOffset: 388 + size: 32 + fields: + - name: CACHE_TAG_WAY_OBJECT + description: "Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, .., 7: way7." + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: CACHE_VADDR + description: "******* Description ***********" + addressOffset: 392 + size: 32 + fields: + - name: CACHE_VADDR + description: Those bits stores the virtual address which will decide where inside the specified tag memory object will be accessed. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CACHE_TAG_CONTENT + description: "******* Description ***********" + addressOffset: 396 + size: 32 + fields: + - name: CACHE_TAG_CONTENT + description: This is a constant place where we can write data to or read data from the tag memory on the specified cache. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DATE + description: "******* Description ***********" + addressOffset: 1020 + size: 32 + resetValue: 33628944 + fields: + - name: DATE + description: version information. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: GPIO + description: General Purpose Input/Output + groupName: GPIO + baseAddress: 1610629120 + addressBlock: + - offset: 0 + size: 1588 + usage: registers + interrupt: + - name: GPIO + value: 16 + - name: GPIO_NMI + value: 17 + - name: GPIO_INTR_2 + value: 18 + - name: GPIO_NMI_2 + value: 19 + registers: + - register: + name: BT_SELECT + description: GPIO bit select register + addressOffset: 0 + size: 32 + fields: + - name: BT_SEL + description: GPIO bit select register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: OUT + description: GPIO output register for GPIO0-31 + addressOffset: 4 + size: 32 + fields: + - name: DATA_ORIG + description: GPIO output register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: OUT_W1TS + description: GPIO output set register for GPIO0-31 + addressOffset: 8 + size: 32 + fields: + - name: OUT_W1TS + description: GPIO output set register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: OUT_W1TC + description: GPIO output clear register for GPIO0-31 + addressOffset: 12 + size: 32 + fields: + - name: OUT_W1TC + description: GPIO output clear register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: OUT1 + description: GPIO output register for GPIO32-53 + addressOffset: 16 + size: 32 + fields: + - name: DATA_ORIG + description: GPIO output register for GPIO32-53 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: OUT1_W1TS + description: GPIO output set register for GPIO32-53 + addressOffset: 20 + size: 32 + fields: + - name: OUT1_W1TS + description: GPIO output set register for GPIO32-53 + bitOffset: 0 + bitWidth: 22 + access: write-only + - register: + name: OUT1_W1TC + description: GPIO output clear register for GPIO32-53 + addressOffset: 24 + size: 32 + fields: + - name: OUT1_W1TC + description: GPIO output clear register for GPIO32-53 + bitOffset: 0 + bitWidth: 22 + access: write-only + - register: + name: SDIO_SELECT + description: GPIO sdio select register + addressOffset: 28 + size: 32 + fields: + - name: SDIO_SEL + description: GPIO sdio select register + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: ENABLE + description: GPIO output enable register for GPIO0-31 + addressOffset: 32 + size: 32 + fields: + - name: DATA + description: GPIO output enable register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ENABLE_W1TS + description: GPIO output enable set register for GPIO0-31 + addressOffset: 36 + size: 32 + fields: + - name: ENABLE_W1TS + description: GPIO output enable set register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: ENABLE_W1TC + description: GPIO output enable clear register for GPIO0-31 + addressOffset: 40 + size: 32 + fields: + - name: ENABLE_W1TC + description: GPIO output enable clear register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: ENABLE1 + description: GPIO output enable register for GPIO32-53 + addressOffset: 44 + size: 32 + fields: + - name: DATA + description: GPIO output enable register for GPIO32-53 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: ENABLE1_W1TS + description: GPIO output enable set register for GPIO32-53 + addressOffset: 48 + size: 32 + fields: + - name: ENABLE1_W1TS + description: GPIO output enable set register for GPIO32-53 + bitOffset: 0 + bitWidth: 22 + access: write-only + - register: + name: ENABLE1_W1TC + description: GPIO output enable clear register for GPIO32-53 + addressOffset: 52 + size: 32 + fields: + - name: ENABLE1_W1TC + description: GPIO output enable clear register for GPIO32-53 + bitOffset: 0 + bitWidth: 22 + access: write-only + - register: + name: STRAP + description: pad strapping register + addressOffset: 56 + size: 32 + fields: + - name: STRAPPING + description: pad strapping register + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: IN + description: GPIO input register for GPIO0-31 + addressOffset: 60 + size: 32 + fields: + - name: DATA_NEXT + description: GPIO input register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: IN1 + description: GPIO input register for GPIO32-53 + addressOffset: 64 + size: 32 + fields: + - name: DATA_NEXT + description: GPIO input register for GPIO32-53 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: STATUS + description: GPIO interrupt status register for GPIO0-31 + addressOffset: 68 + size: 32 + fields: + - name: INTERRUPT + description: GPIO interrupt status register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STATUS_W1TS + description: GPIO interrupt status set register for GPIO0-31 + addressOffset: 72 + size: 32 + fields: + - name: STATUS_W1TS + description: GPIO interrupt status set register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: STATUS_W1TC + description: GPIO interrupt status clear register for GPIO0-31 + addressOffset: 76 + size: 32 + fields: + - name: STATUS_W1TC + description: GPIO interrupt status clear register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: STATUS1 + description: GPIO interrupt status register for GPIO32-53 + addressOffset: 80 + size: 32 + fields: + - name: INTERRUPT + description: GPIO interrupt status register for GPIO32-53 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: STATUS1_W1TS + description: GPIO interrupt status set register for GPIO32-53 + addressOffset: 84 + size: 32 + fields: + - name: STATUS1_W1TS + description: GPIO interrupt status set register for GPIO32-53 + bitOffset: 0 + bitWidth: 22 + access: write-only + - register: + name: STATUS1_W1TC + description: GPIO interrupt status clear register for GPIO32-53 + addressOffset: 88 + size: 32 + fields: + - name: STATUS1_W1TC + description: GPIO interrupt status clear register for GPIO32-53 + bitOffset: 0 + bitWidth: 22 + access: write-only + - register: + name: PCPU_INT + description: GPIO PRO_CPU interrupt status register for GPIO0-31 + addressOffset: 92 + size: 32 + fields: + - name: PROCPU_INT + description: GPIO PRO_CPU interrupt status register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PCPU_NMI_INT + description: GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + addressOffset: 96 + size: 32 + fields: + - name: PROCPU_NMI_INT + description: GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CPUSDIO_INT + description: GPIO CPUSDIO interrupt status register for GPIO0-31 + addressOffset: 100 + size: 32 + fields: + - name: SDIO_INT + description: GPIO CPUSDIO interrupt status register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PCPU_INT1 + description: GPIO PRO_CPU interrupt status register for GPIO32-53 + addressOffset: 104 + size: 32 + fields: + - name: PROCPU_INT1 + description: GPIO PRO_CPU interrupt status register for GPIO32-53 + bitOffset: 0 + bitWidth: 22 + access: read-only + - register: + name: PCPU_NMI_INT1 + description: GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-53 + addressOffset: 108 + size: 32 + fields: + - name: PROCPU_NMI_INT1 + description: GPIO PRO_CPU(not shielded) interrupt status register for GPIO32-53 + bitOffset: 0 + bitWidth: 22 + access: read-only + - register: + name: CPUSDIO_INT1 + description: GPIO CPUSDIO interrupt status register for GPIO32-53 + addressOffset: 112 + size: 32 + fields: + - name: SDIO_INT1 + description: GPIO CPUSDIO interrupt status register for GPIO32-53 + bitOffset: 0 + bitWidth: 22 + access: read-only + - register: + dim: 54 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53" + name: PIN%s + description: GPIO pin configuration register + addressOffset: 116 + size: 32 + fields: + - name: SYNC2_BYPASS + description: "set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: PAD_DRIVER + description: "set this bit to select pad driver. 1:open-drain. 0:normal." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SYNC1_BYPASS + description: "set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge." + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: INT_TYPE + description: "set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CONFIG + description: reserved + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: INT_ENA + description: set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. + bitOffset: 13 + bitWidth: 5 + access: read-write + - register: + name: STATUS_NEXT + description: GPIO interrupt source register for GPIO0-31 + addressOffset: 332 + size: 32 + fields: + - name: STATUS_INTERRUPT_NEXT + description: GPIO interrupt source register for GPIO0-31 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: STATUS_NEXT1 + description: GPIO interrupt source register for GPIO32-53 + addressOffset: 336 + size: 32 + fields: + - name: STATUS_INTERRUPT_NEXT1 + description: GPIO interrupt source register for GPIO32-53 + bitOffset: 0 + bitWidth: 22 + access: read-only + - register: + dim: 256 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255" + name: FUNC%s_IN_SEL_CFG + description: GPIO input function configuration register + addressOffset: 340 + size: 32 + fields: + - name: IN_SEL + description: "set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level." + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: IN_INV_SEL + description: "set this bit to invert input signal. 1:invert. 0:not invert." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SEL + description: "set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO." + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + dim: 54 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53" + name: FUNC%s_OUT_SEL_CFG + description: GPIO output function select register + addressOffset: 1364 + size: 32 + resetValue: 256 + fields: + - name: OUT_SEL + description: "The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n]." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: INV_SEL + description: "set this bit to invert output signal.1:invert.0:not invert." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OEN_SEL + description: "set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OEN_INV_SEL + description: "set this bit to invert output enable signal.1:invert.0:not invert." + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: CLOCK_GATE + description: GPIO clock gate register + addressOffset: 1580 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: set this bit to enable GPIO clock gate + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: REG_DATE + description: GPIO version register + addressOffset: 1788 + size: 32 + resetValue: 26243136 + fields: + - name: REG_DATE + description: version register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: GPIO_SD + description: Sigma-Delta Modulation + groupName: GPIOSD + baseAddress: 1610632960 + addressBlock: + - offset: 0 + size: 44 + usage: registers + registers: + - register: + dim: 8 + dimIncrement: 4 + name: SIGMADELTA%s + description: Duty Cycle Configure Register of SDM%s + addressOffset: 0 + size: 32 + resetValue: 65280 + fields: + - name: SD_IN + description: This field is used to configure the duty cycle of sigma delta modulation output. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SD_PRESCALE + description: This field is used to set a divider value to divide APB clock. + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: SIGMADELTA_CG + description: Clock Gating Configure Register + addressOffset: 32 + size: 32 + fields: + - name: CLK_EN + description: Clock enable bit of configuration registers for sigma delta modulation. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SIGMADELTA_MISC + description: MISC Register + addressOffset: 36 + size: 32 + fields: + - name: FUNCTION_CLK_EN + description: Clock enable bit of sigma delta modulation. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI_SWAP + description: Reserved. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SIGMADELTA_VERSION + description: Version Control Register + addressOffset: 40 + size: 32 + resetValue: 25174624 + fields: + - name: GPIO_SD_DATE + description: Version control register. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: HMAC + description: HMAC (Hash-based Message Authentication Code) Accelerator + groupName: HMAC + baseAddress: 1610866688 + addressBlock: + - offset: 0 + size: 164 + usage: registers + registers: + - register: + name: SET_START + description: Process control register 0. + addressOffset: 64 + size: 32 + fields: + - name: SET_START + description: Start hmac operation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_PARA_PURPOSE + description: Configure purpose. + addressOffset: 68 + size: 32 + fields: + - name: PURPOSE_SET + description: Set hmac parameter purpose. + bitOffset: 0 + bitWidth: 4 + access: write-only + - register: + name: SET_PARA_KEY + description: Configure key. + addressOffset: 72 + size: 32 + fields: + - name: KEY_SET + description: Set hmac parameter key. + bitOffset: 0 + bitWidth: 3 + access: write-only + - register: + name: SET_PARA_FINISH + description: Finish initial configuration. + addressOffset: 76 + size: 32 + fields: + - name: SET_PARA_END + description: Finish hmac configuration. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_MESSAGE_ONE + description: Process control register 1. + addressOffset: 80 + size: 32 + fields: + - name: SET_TEXT_ONE + description: Call SHA to calculate one message block. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_MESSAGE_ING + description: Process control register 2. + addressOffset: 84 + size: 32 + fields: + - name: SET_TEXT_ING + description: Continue typical hmac. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_MESSAGE_END + description: Process control register 3. + addressOffset: 88 + size: 32 + fields: + - name: SET_TEXT_END + description: Start hardware padding. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_RESULT_FINISH + description: Process control register 4. + addressOffset: 92 + size: 32 + fields: + - name: SET_RESULT_END + description: "After read result from upstream, then let hmac back to idle." + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_INVALIDATE_JTAG + description: Invalidate register 0. + addressOffset: 96 + size: 32 + fields: + - name: SET_INVALIDATE_JTAG + description: Clear result from hmac downstream JTAG. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SET_INVALIDATE_DS + description: Invalidate register 1. + addressOffset: 100 + size: 32 + fields: + - name: SET_INVALIDATE_DS + description: Clear result from hmac downstream DS. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: QUERY_ERROR + description: Error register. + addressOffset: 104 + size: 32 + fields: + - name: QUERY_CHECK + description: "Hmac configuration state. 0: key are agree with purpose. 1: error" + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: QUERY_BUSY + description: Busy register. + addressOffset: 108 + size: 32 + fields: + - name: BUSY_STATE + description: "Hmac state. 1'b0: idle. 1'b1: busy" + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + dim: 16 + dimIncrement: 4 + name: "WR_MESSAGE_MEM[%s]" + description: Message block memory. + addressOffset: 128 + size: 32 + - register: + dim: 8 + dimIncrement: 4 + name: "RD_RESULT_MEM[%s]" + description: Result from upstream. + addressOffset: 192 + size: 32 + - register: + name: SET_MESSAGE_PAD + description: Process control register 5. + addressOffset: 240 + size: 32 + fields: + - name: SET_TEXT_PAD + description: Start software padding. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: ONE_BLOCK + description: Process control register 6. + addressOffset: 244 + size: 32 + fields: + - name: SET_ONE_BLOCK + description: "Don't have to do padding." + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: SOFT_JTAG_CTRL + description: Jtag register 0. + addressOffset: 248 + size: 32 + fields: + - name: SOFT_JTAG_CTRL + description: Turn on JTAG verification. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: WR_JTAG + description: Jtag register 1. + addressOffset: 252 + size: 32 + fields: + - name: WR_JTAG + description: 32-bit of key to be compared. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: DATE + description: Date register. + addressOffset: 508 + size: 32 + resetValue: 34607216 + fields: + - name: DATE + description: Hmac date information/ hmac version information. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: I2C0 + description: I2C (Inter-Integrated Circuit) Controller 0 + groupName: I2C + baseAddress: 1610690560 + addressBlock: + - offset: 0 + size: 144 + usage: registers + interrupt: + - name: I2C_MASTER + value: 11 + - name: I2C_EXT0 + value: 42 + registers: + - register: + name: SCL_LOW_PERIOD + description: "Configures the low level width of the SCL\nClock" + addressOffset: 0 + size: 32 + fields: + - name: SCL_LOW_PERIOD + description: "This register is used to configure for how long SCL remains low in master mode, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: CTR + description: Transmission setting + addressOffset: 4 + size: 32 + resetValue: 523 + fields: + - name: SDA_FORCE_OUT + description: "0: direct output; 1: open drain output." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_FORCE_OUT + description: "0: direct output; 1: open drain output." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SAMPLE_SCL_LEVEL + description: "This register is used to select the sample mode.\n1: sample SDA data on the SCL low level.\n0: sample SDA data on the SCL high level." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_FULL_ACK_LEVEL + description: This register is used to configure the ACK value that need to sent by master when the rx_fifo_cnt has reached the threshold. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MS_MODE + description: "Set this bit to configure the module as an I2C Master. Clear this bit to configure the\nmodule as an I2C Slave." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TRANS_START + description: Set this bit to start sending the data in txfifo. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TX_LSB_FIRST + description: "This bit is used to control the sending mode for data needing to be sent. \n1: send data from the least significant bit;\n0: send data from the most significant bit." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_LSB_FIRST + description: "This bit is used to control the storage mode for received data.\n1: receive data from the least significant bit;\n0: receive data from the most significant bit." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: Reserved + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: ARBITRATION_EN + description: This is the enable bit for arbitration_lost. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FSM_RST + description: This register is used to reset the scl FMS. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: CONF_UPGATE + description: synchronization bit + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: SLV_TX_AUTO_START_EN + description: This is the enable bit for slave to send data automatically + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: ADDR_10BIT_RW_CHECK_EN + description: This is the enable bit to check if the r/w bit of 10bit addressing consists with I2C protocol + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: ADDR_BROADCASTING_EN + description: This is the enable bit to support the 7bit general call function. + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: SR + description: Describe I2C work status. + addressOffset: 8 + size: 32 + resetValue: 49152 + fields: + - name: RESP_REC + description: "The received ACK value in master mode or slave mode. 0: ACK, 1: NACK." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SLAVE_RW + description: "When in slave mode, 1: master reads from slave; 0: master writes to slave." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ARB_LOST + description: "When the I2C controller loses control of SCL line, this register changes to 1." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BUS_BUSY + description: "1: the I2C bus is busy transferring data; 0: the I2C bus is in idle state." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SLAVE_ADDRESSED + description: "When configured as an I2C Slave, and the address sent by the master is\nequal to the address of the slave, then this bit will be of high level." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: RXFIFO_CNT + description: This field represents the amount of data needed to be sent. + bitOffset: 8 + bitWidth: 6 + access: read-only + - name: STRETCH_CAUSE + description: "The cause of stretching SCL low in slave mode. 0: stretching SCL low at the beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode." + bitOffset: 14 + bitWidth: 2 + access: read-only + - name: TXFIFO_CNT + description: This field stores the amount of received data in RAM. + bitOffset: 18 + bitWidth: 6 + access: read-only + - name: SCL_MAIN_STATE_LAST + description: "This field indicates the states of the I2C module state machine. \n0: Idle; 1: Address shift; 2: ACK address; 3: Rx data; 4: Tx data; 5: Send ACK; 6: Wait ACK" + bitOffset: 24 + bitWidth: 3 + access: read-only + - name: SCL_STATE_LAST + description: "This field indicates the states of the state machine used to produce SCL.\n0: Idle; 1: Start; 2: Negative edge; 3: Low; 4: Positive edge; 5: High; 6: Stop" + bitOffset: 28 + bitWidth: 3 + access: read-only + - register: + name: TO + description: Setting time out control for receiving data. + addressOffset: 12 + size: 32 + resetValue: 16 + fields: + - name: TIME_OUT_VALUE + description: "This register is used to configure the timeout for receiving a data bit in APB\nclock cycles." + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: TIME_OUT_EN + description: This is the enable bit for time out control. + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: SLAVE_ADDR + description: Local slave address setting + addressOffset: 16 + size: 32 + fields: + - name: SLAVE_ADDR + description: "When configured as an I2C Slave, this field is used to configure the slave address." + bitOffset: 0 + bitWidth: 15 + access: read-write + - name: ADDR_10BIT_EN + description: This field is used to enable the slave 10-bit addressing mode in master mode. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: FIFO_ST + description: FIFO status register. + addressOffset: 20 + size: 32 + fields: + - name: RXFIFO_RADDR + description: This is the offset address of the APB reading from rxfifo + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: RXFIFO_WADDR + description: This is the offset address of i2c module receiving data and writing to rxfifo. + bitOffset: 5 + bitWidth: 5 + access: read-only + - name: TXFIFO_RADDR + description: This is the offset address of i2c module reading from txfifo. + bitOffset: 10 + bitWidth: 5 + access: read-only + - name: TXFIFO_WADDR + description: This is the offset address of APB bus writing to txfifo. + bitOffset: 15 + bitWidth: 5 + access: read-only + - name: SLAVE_RW_POINT + description: The received data in I2C slave mode. + bitOffset: 22 + bitWidth: 8 + access: read-only + - register: + name: FIFO_CONF + description: FIFO configuration register. + addressOffset: 24 + size: 32 + resetValue: 16523 + fields: + - name: RXFIFO_WM_THRHD + description: "The water mark threshold of rx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid." + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: TXFIFO_WM_THRHD + description: "The water mark threshold of tx FIFO in nonfifo access mode. When reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid." + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: NONFIFO_EN + description: Set this bit to enable APB nonfifo access. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FIFO_ADDR_CFG_EN + description: "When this bit is set to 1, the byte received after the I2C address byte represents the offset address in the I2C Slave RAM." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RX_FIFO_RST + description: Set this bit to reset rx-fifo. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_FIFO_RST + description: Set this bit to reset tx-fifo. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FIFO_PRT_EN + description: "The control enable bit of FIFO pointer in non-fifo access mode. This bit controls the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty." + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DATA + description: Rx FIFO read data. + addressOffset: 28 + size: 32 + fields: + - name: FIFO_RDATA + description: The value of rx FIFO read data. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 32 + size: 32 + resetValue: 2 + fields: + - name: RXFIFO_WM_INT_RAW + description: The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_WM_INT_RAW + description: The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_RAW + description: The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: END_DETECT_INT_RAW + description: The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS_DONE_INT_RAW + description: The raw interrupt bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_RAW + description: The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: MST_TXFIFO_UDF_INT_RAW + description: The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_RAW + description: The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_RAW + description: The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TRANS_START_INT_RAW + description: The raw interrupt bit for the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: NACK_INT_RAW + description: The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: TXFIFO_OVF_INT_RAW + description: The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: RXFIFO_UDF_INT_RAW + description: The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SCL_ST_TO_INT_RAW + description: The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SCL_MAIN_ST_TO_INT_RAW + description: The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DET_START_INT_RAW + description: The raw interrupt bit for I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLAVE_STRETCH_INT_RAW + description: The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: GENERAL_CALL_INT_RAW + description: The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 36 + size: 32 + fields: + - name: RXFIFO_WM_INT_CLR + description: Set this bit to clear I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TXFIFO_WM_INT_CLR + description: Set this bit to clear I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RXFIFO_OVF_INT_CLR + description: Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: END_DETECT_INT_CLR + description: Set this bit to clear the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: BYTE_TRANS_DONE_INT_CLR + description: Set this bit to clear the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: ARBITRATION_LOST_INT_CLR + description: Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: MST_TXFIFO_UDF_INT_CLR + description: Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TRANS_COMPLETE_INT_CLR + description: Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: TIME_OUT_INT_CLR + description: Set this bit to clear the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: TRANS_START_INT_CLR + description: Set this bit to clear the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: NACK_INT_CLR + description: Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: TXFIFO_OVF_INT_CLR + description: Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: RXFIFO_UDF_INT_CLR + description: Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: SCL_ST_TO_INT_CLR + description: Set this bit to clear I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SCL_MAIN_ST_TO_INT_CLR + description: Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: DET_START_INT_CLR + description: Set this bit to clear I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: SLAVE_STRETCH_INT_CLR + description: Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: GENERAL_CALL_INT_CLR + description: Set this bit for I2C_GENARAL_CALL_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 40 + size: 32 + fields: + - name: RXFIFO_WM_INT_ENA + description: The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_WM_INT_ENA + description: The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_ENA + description: The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: END_DETECT_INT_ENA + description: The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: BYTE_TRANS_DONE_INT_ENA + description: The interrupt enable bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ARBITRATION_LOST_INT_ENA + description: The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: MST_TXFIFO_UDF_INT_ENA + description: The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TRANS_COMPLETE_INT_ENA + description: The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TIME_OUT_INT_ENA + description: The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TRANS_START_INT_ENA + description: The interrupt enable bit for the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: NACK_INT_ENA + description: The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TXFIFO_OVF_INT_ENA + description: The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RXFIFO_UDF_INT_ENA + description: The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SCL_ST_TO_INT_ENA + description: The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SCL_MAIN_ST_TO_INT_ENA + description: The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DET_START_INT_ENA + description: The interrupt enable bit for I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLAVE_STRETCH_INT_ENA + description: The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: GENERAL_CALL_INT_ENA + description: The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: INT_STATUS + description: Status of captured I2C communication events + addressOffset: 44 + size: 32 + fields: + - name: RXFIFO_WM_INT_ST + description: The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_WM_INT_ST + description: The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_ST + description: The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: END_DETECT_INT_ST + description: The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS_DONE_INT_ST + description: The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_ST + description: The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: MST_TXFIFO_UDF_INT_ST + description: The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_ST + description: The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_ST + description: The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TRANS_START_INT_ST + description: The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: NACK_INT_ST + description: The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: TXFIFO_OVF_INT_ST + description: The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: RXFIFO_UDF_INT_ST + description: The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: SCL_ST_TO_INT_ST + description: The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SCL_MAIN_ST_TO_INT_ST + description: The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: DET_START_INT_ST + description: The masked interrupt status bit for I2C_DET_START_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLAVE_STRETCH_INT_ST + description: The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: GENERAL_CALL_INT_ST + description: The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-only + - register: + name: SDA_HOLD + description: Configures the hold time after a negative SCL edge. + addressOffset: 48 + size: 32 + fields: + - name: TIME + description: "This register is used to configure the time to hold the data after the negative\nedge of SCL, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SDA_SAMPLE + description: Configures the sample time after a positive SCL edge. + addressOffset: 52 + size: 32 + fields: + - name: TIME + description: "This register is used to configure for how long SDA is sampled, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_HIGH_PERIOD + description: Configures the high level width of SCL + addressOffset: 56 + size: 32 + fields: + - name: SCL_HIGH_PERIOD + description: "This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: SCL_WAIT_HIGH_PERIOD + description: "This register is used to configure for the SCL_FSM's waiting period for SCL high level in master mode, in I2C module clock cycles." + bitOffset: 9 + bitWidth: 7 + access: read-write + - register: + name: SCL_START_HOLD + description: Configures the delay between the SDA and SCL negative edge for a start condition + addressOffset: 64 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the time between the negative edge\nof SDA and the negative edge of SCL for a START condition, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_RSTART_SETUP + description: "Configures the delay between the positive\nedge of SCL and the negative edge of SDA" + addressOffset: 68 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the time between the positive\nedge of SCL and the negative edge of SDA for a RESTART condition, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_STOP_HOLD + description: "Configures the delay after the SCL clock\nedge for a stop condition" + addressOffset: 72 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the delay after the STOP condition,\nin I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SCL_STOP_SETUP + description: "Configures the delay between the SDA and\nSCL positive edge for a stop condition" + addressOffset: 76 + size: 32 + resetValue: 8 + fields: + - name: TIME + description: "This register is used to configure the time between the positive edge\nof SCL and the positive edge of SDA, in I2C module clock cycles." + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: FILTER_CFG + description: SCL and SDA filter configuration register + addressOffset: 80 + size: 32 + resetValue: 768 + fields: + - name: SCL_FILTER_THRES + description: "When a pulse on the SCL input has smaller width than this register value\nin I2C module clock cycles, the I2C controller will ignore that pulse." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: SDA_FILTER_THRES + description: "When a pulse on the SDA input has smaller width than this register value\nin I2C module clock cycles, the I2C controller will ignore that pulse." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: SCL_FILTER_EN + description: This is the filter enable bit for SCL. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SDA_FILTER_EN + description: This is the filter enable bit for SDA. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: CLK_CONF + description: I2C CLK configuration register + addressOffset: 84 + size: 32 + resetValue: 2097152 + fields: + - name: SCLK_DIV_NUM + description: the integral part of the fractional divisor for i2c module + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SCLK_DIV_A + description: the numerator of the fractional part of the fractional divisor for i2c module + bitOffset: 8 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_B + description: the denominator of the fractional part of the fractional divisor for i2c module + bitOffset: 14 + bitWidth: 6 + access: read-write + - name: SCLK_SEL + description: "The clock selection for i2c module:0-XTAL;1-CLK_8MHz." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SCLK_ACTIVE + description: The clock switch for i2c module + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + dim: 8 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7" + name: COMD%s + description: I2C command register %s + addressOffset: 88 + size: 32 + fields: + - name: COMMAND + description: "This is the content of command 0. It consists of three parts: \nop_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.\nByte_num represents the number of bytes that need to be sent or received.\nack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd structure for more\nInformation." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND_DONE + description: "When command 0 is done in I2C Master mode, this bit changes to high\nlevel." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SCL_ST_TIME_OUT + description: SCL status time out register + addressOffset: 120 + size: 32 + resetValue: 16 + fields: + - name: SCL_ST_TO_I2C + description: The threshold value of SCL_FSM state unchanged period. It should be o more than 23 + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SCL_MAIN_ST_TIME_OUT + description: SCL main status time out register + addressOffset: 124 + size: 32 + resetValue: 16 + fields: + - name: SCL_MAIN_ST_TO_I2C + description: The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more than 23 + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SCL_SP_CONF + description: Power configuration register + addressOffset: 128 + size: 32 + fields: + - name: SCL_RST_SLV_EN + description: "When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses equals to reg_scl_rst_slv_num[4:0]." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_RST_SLV_NUM + description: Configure the pulses of SCL generated in I2C master mode. Valid when reg_scl_rst_slv_en is 1. + bitOffset: 1 + bitWidth: 5 + access: read-write + - name: SCL_PD_EN + description: "The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SDA_PD_EN + description: "The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low." + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: SCL_STRETCH_CONF + description: Set SCL stretch of I2C slave + addressOffset: 132 + size: 32 + fields: + - name: STRETCH_PROTECT_NUM + description: Configure the period of I2C slave stretching SCL line. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: SLAVE_SCL_STRETCH_EN + description: "The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch event happens. The stretch cause can be seen in reg_stretch_cause." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLAVE_SCL_STRETCH_CLR + description: Set this bit to clear the I2C slave SCL stretch function. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: SLAVE_BYTE_ACK_CTL_EN + description: The enable bit for slave to control ACK level function. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SLAVE_BYTE_ACK_LVL + description: Set the ACK level when slave controlling ACK level function enables. + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version register + addressOffset: 248 + size: 32 + resetValue: 537330177 + fields: + - name: DATE + description: This is the the version register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TXFIFO_START_ADDR + description: I2C TXFIFO base address register + addressOffset: 256 + size: 32 + fields: + - name: TXFIFO_START_ADDR + description: This is the I2C txfifo first address. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RXFIFO_START_ADDR + description: I2C RXFIFO base address register + addressOffset: 384 + size: 32 + fields: + - name: RXFIFO_START_ADDR + description: This is the I2C rxfifo first address. + bitOffset: 0 + bitWidth: 32 + access: read-only + - name: I2C1 + description: I2C (Inter-Integrated Circuit) Controller 1 + baseAddress: 1610772480 + interrupt: + - name: I2C_EXT1 + value: 43 + derivedFrom: I2C0 + - name: I2S0 + description: I2S (Inter-IC Sound) Controller 0 + groupName: I2S + baseAddress: 1610674176 + addressBlock: + - offset: 0 + size: 92 + usage: registers + interrupt: + - name: I2S0 + value: 25 + registers: + - register: + name: INT_RAW + description: "I2S interrupt raw register, valid in level." + addressOffset: 12 + size: 32 + fields: + - name: RX_DONE_INT_RAW + description: The raw interrupt status bit for the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_RAW + description: The raw interrupt status bit for the i2s_tx_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_RAW + description: The raw interrupt status bit for the i2s_rx_hung_int interrupt + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_RAW + description: The raw interrupt status bit for the i2s_tx_hung_int interrupt + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: I2S interrupt status register. + addressOffset: 16 + size: 32 + fields: + - name: RX_DONE_INT_ST + description: The masked interrupt status bit for the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_ST + description: The masked interrupt status bit for the i2s_tx_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_ST + description: The masked interrupt status bit for the i2s_rx_hung_int interrupt + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_ST + description: The masked interrupt status bit for the i2s_tx_hung_int interrupt + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: I2S interrupt enable register. + addressOffset: 20 + size: 32 + fields: + - name: RX_DONE_INT_ENA + description: The interrupt enable bit for the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_ENA + description: The interrupt enable bit for the i2s_tx_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_HUNG_INT_ENA + description: The interrupt enable bit for the i2s_rx_hung_int interrupt + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_HUNG_INT_ENA + description: The interrupt enable bit for the i2s_tx_hung_int interrupt + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: I2S interrupt clear register. + addressOffset: 24 + size: 32 + fields: + - name: RX_DONE_INT_CLR + description: Set this bit to clear the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TX_DONE_INT_CLR + description: Set this bit to clear the i2s_tx_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_HUNG_INT_CLR + description: Set this bit to clear the i2s_rx_hung_int interrupt + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TX_HUNG_INT_CLR + description: Set this bit to clear the i2s_tx_hung_int interrupt + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: RX_CONF + description: I2S RX configure register + addressOffset: 32 + size: 32 + resetValue: 38400 + fields: + - name: RX_RESET + description: Set this bit to reset receiver + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: RX_FIFO_RESET + description: Set this bit to reset Rx AFIFO + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_START + description: Set this bit to start receiving data + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_SLAVE_MOD + description: Set this bit to enable slave receiver mode + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_MONO + description: Set this bit to enable receiver in mono mode + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RX_BIG_ENDIAN + description: "I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RX_UPDATE + description: Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RX_MONO_FST_VLD + description: "1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RX_PCM_CONF + description: "I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: RX_PCM_BYPASS + description: Set this bit to bypass Compress/Decompress module for received data. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RX_STOP_MODE + description: "0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full." + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: RX_LEFT_ALIGN + description: "1: I2S RX left alignment mode. 0: I2S RX right alignment mode." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RX_24_FILL_EN + description: "1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RX_WS_IDLE_POL + description: "0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: RX_BIT_ORDER + description: "I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RX_TDM_EN + description: "1: Enable I2S TDM Rx mode . 0: Disable." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RX_PDM_EN + description: "1: Enable I2S PDM Rx mode . 0: Disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: RX_PDM2PCM_EN + description: "1: Enable PDM2PCM RX mode. 0: DIsable." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: RX_PDM_SINC_DSR_16_EN + description: "Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64." + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: TX_CONF + description: I2S TX configure register + addressOffset: 36 + size: 32 + resetValue: 45568 + fields: + - name: TX_RESET + description: Set this bit to reset transmitter + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TX_FIFO_RESET + description: Set this bit to reset Tx AFIFO + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TX_START + description: Set this bit to start transmitting data + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_SLAVE_MOD + description: Set this bit to enable slave transmitter mode + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_MONO + description: Set this bit to enable transmitter in mono mode + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TX_CHAN_EQUAL + description: "1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_BIG_ENDIAN + description: "I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TX_UPDATE + description: Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TX_MONO_FST_VLD + description: "1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TX_PCM_CONF + description: "I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: TX_PCM_BYPASS + description: Set this bit to bypass Compress/Decompress module for transmitted data. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_STOP_EN + description: Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_LEFT_ALIGN + description: "1: I2S TX left alignment mode. 0: I2S TX right alignment mode." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TX_24_FILL_EN + description: "1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: TX_WS_IDLE_POL + description: "0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: TX_BIT_ORDER + description: "I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TX_TDM_EN + description: "1: Enable I2S TDM Tx mode . 0: Disable." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: TX_PDM_EN + description: "1: Enable I2S PDM Tx mode . 0: Disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TX_CHAN_MOD + description: I2S transmitter channel mode configuration bits. + bitOffset: 24 + bitWidth: 3 + access: read-write + - name: SIG_LOOPBACK + description: Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: RX_CONF1 + description: I2S RX configure register 1 + addressOffset: 40 + size: 32 + resetValue: 792584960 + fields: + - name: RX_TDM_WS_WIDTH + description: "The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck" + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: RX_BCK_DIV_NUM + description: Bit clock configuration bits in receiver mode. + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: RX_BITS_MOD + description: "Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode." + bitOffset: 13 + bitWidth: 5 + access: read-write + - name: RX_HALF_SAMPLE_BITS + description: I2S Rx half sample bits -1. + bitOffset: 18 + bitWidth: 6 + access: read-write + - name: RX_TDM_CHAN_BITS + description: The Rx bit number for each channel minus 1in TDM mode. + bitOffset: 24 + bitWidth: 5 + access: read-write + - name: RX_MSB_SHIFT + description: Set this bit to enable receiver in Phillips standard mode + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: TX_CONF1 + description: I2S TX configure register 1 + addressOffset: 44 + size: 32 + resetValue: 1866326784 + fields: + - name: TX_TDM_WS_WIDTH + description: "The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck" + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: TX_BCK_DIV_NUM + description: Bit clock configuration bits in transmitter mode. + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: TX_BITS_MOD + description: "Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode." + bitOffset: 13 + bitWidth: 5 + access: read-write + - name: TX_HALF_SAMPLE_BITS + description: I2S Tx half sample bits -1. + bitOffset: 18 + bitWidth: 6 + access: read-write + - name: TX_TDM_CHAN_BITS + description: The Tx bit number for each channel minus 1in TDM mode. + bitOffset: 24 + bitWidth: 5 + access: read-write + - name: TX_MSB_SHIFT + description: Set this bit to enable transmitter in Phillips standard mode + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TX_BCK_NO_DLY + description: "1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode." + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: RX_CLKM_CONF + description: I2S RX clock configure register + addressOffset: 48 + size: 32 + resetValue: 2 + fields: + - name: RX_CLKM_DIV_NUM + description: Integral I2S clock divider value + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: RX_CLK_ACTIVE + description: I2S Rx module clock enable signal. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RX_CLK_SEL + description: "Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in." + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: MCLK_SEL + description: "0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT." + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: TX_CLKM_CONF + description: I2S TX clock configure register + addressOffset: 52 + size: 32 + resetValue: 2 + fields: + - name: TX_CLKM_DIV_NUM + description: "Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TX_CLK_ACTIVE + description: I2S Tx module clock enable signal. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TX_CLK_SEL + description: "Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in." + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: CLK_EN + description: Set this bit to enable clk gate + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: RX_CLKM_DIV_CONF + description: I2S RX module clock divider configure register + addressOffset: 56 + size: 32 + resetValue: 512 + fields: + - name: RX_CLKM_DIV_Z + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: RX_CLKM_DIV_Y + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))." + bitOffset: 9 + bitWidth: 9 + access: read-write + - name: RX_CLKM_DIV_X + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1." + bitOffset: 18 + bitWidth: 9 + access: read-write + - name: RX_CLKM_DIV_YN1 + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1." + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: TX_CLKM_DIV_CONF + description: I2S TX module clock divider configure register + addressOffset: 60 + size: 32 + resetValue: 512 + fields: + - name: TX_CLKM_DIV_Z + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: TX_CLKM_DIV_Y + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))." + bitOffset: 9 + bitWidth: 9 + access: read-write + - name: TX_CLKM_DIV_X + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1." + bitOffset: 18 + bitWidth: 9 + access: read-write + - name: TX_CLKM_DIV_YN1 + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1." + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: TX_PCM2PDM_CONF + description: I2S TX PCM2PDM configuration register + addressOffset: 64 + size: 32 + resetValue: 4890628 + fields: + - name: TX_PDM_HP_BYPASS + description: I2S TX PDM bypass hp filter or not. The option has been removed. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_PDM_SINC_OSR2 + description: I2S TX PDM OSR2 value + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: TX_PDM_PRESCALE + description: I2S TX PDM prescale for sigmadelta + bitOffset: 5 + bitWidth: 8 + access: read-write + - name: TX_PDM_HP_IN_SHIFT + description: "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4" + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: TX_PDM_LP_IN_SHIFT + description: "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4" + bitOffset: 15 + bitWidth: 2 + access: read-write + - name: TX_PDM_SINC_IN_SHIFT + description: "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4" + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: TX_PDM_SIGMADELTA_IN_SHIFT + description: "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4" + bitOffset: 19 + bitWidth: 2 + access: read-write + - name: TX_PDM_SIGMADELTA_DITHER2 + description: I2S TX PDM sigmadelta dither2 value + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: TX_PDM_SIGMADELTA_DITHER + description: I2S TX PDM sigmadelta dither value + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TX_PDM_DAC_2OUT_EN + description: I2S TX PDM dac mode enable + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TX_PDM_DAC_MODE_EN + description: I2S TX PDM dac 2channel enable + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PCM2PDM_CONV_EN + description: I2S TX PDM Converter enable + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: TX_PCM2PDM_CONF1 + description: I2S TX PCM2PDM configuration register + addressOffset: 68 + size: 32 + resetValue: 66552768 + fields: + - name: TX_PDM_FP + description: I2S TX PDM Fp + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: TX_PDM_FS + description: I2S TX PDM Fs + bitOffset: 10 + bitWidth: 10 + access: read-write + - name: TX_IIR_HP_MULT12_5 + description: "The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])" + bitOffset: 20 + bitWidth: 3 + access: read-write + - name: TX_IIR_HP_MULT12_0 + description: "The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])" + bitOffset: 23 + bitWidth: 3 + access: read-write + - register: + name: RX_TDM_CTRL + description: I2S TX TDM mode control register + addressOffset: 80 + size: 32 + resetValue: 65535 + fields: + - name: RX_TDM_PDM_CHAN0_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN1_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN2_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN3_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN4_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN5_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN6_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN7_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN8_EN + description: "1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN9_EN + description: "1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN10_EN + description: "1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN11_EN + description: "1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN12_EN + description: "1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN13_EN + description: "1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN14_EN + description: "1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN15_EN + description: "1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RX_TDM_TOT_CHAN_NUM + description: The total channel number of I2S TX TDM mode. + bitOffset: 16 + bitWidth: 4 + access: read-write + - register: + name: TX_TDM_CTRL + description: I2S TX TDM mode control register + addressOffset: 84 + size: 32 + resetValue: 65535 + fields: + - name: TX_TDM_CHAN0_EN + description: "1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN1_EN + description: "1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN2_EN + description: "1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN3_EN + description: "1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN4_EN + description: "1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN5_EN + description: "1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN6_EN + description: "1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN7_EN + description: "1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN8_EN + description: "1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN9_EN + description: "1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN10_EN + description: "1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN11_EN + description: "1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN12_EN + description: "1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN13_EN + description: "1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN14_EN + description: "1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN15_EN + description: "1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TX_TDM_TOT_CHAN_NUM + description: The total channel number of I2S TX TDM mode. + bitOffset: 16 + bitWidth: 4 + access: read-write + - name: TX_TDM_SKIP_MSK_EN + description: "When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels." + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: RX_TIMING + description: I2S RX timing control register + addressOffset: 88 + size: 32 + fields: + - name: RX_SD_IN_DM + description: "The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: RX_SD1_IN_DM + description: "The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: RX_SD2_IN_DM + description: "The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: RX_SD3_IN_DM + description: "The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: RX_WS_OUT_DM + description: "The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: RX_BCK_OUT_DM + description: "The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: RX_WS_IN_DM + description: "The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: RX_BCK_IN_DM + description: "The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 28 + bitWidth: 2 + access: read-write + - register: + name: TX_TIMING + description: I2S TX timing control register + addressOffset: 92 + size: 32 + fields: + - name: TX_SD_OUT_DM + description: "The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: TX_SD1_OUT_DM + description: "The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: TX_WS_OUT_DM + description: "The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: TX_BCK_OUT_DM + description: "The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TX_WS_IN_DM + description: "The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: TX_BCK_IN_DM + description: "The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 28 + bitWidth: 2 + access: read-write + - register: + name: LC_HUNG_CONF + description: I2S HUNG configure register. + addressOffset: 96 + size: 32 + resetValue: 2064 + fields: + - name: LC_FIFO_TIMEOUT + description: the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: LC_FIFO_TIMEOUT_SHIFT + description: The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + bitOffset: 8 + bitWidth: 3 + access: read-write + - name: LC_FIFO_TIMEOUT_ENA + description: The enable bit for FIFO timeout + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: RXEOF_NUM + description: I2S RX data number control register. + addressOffset: 100 + size: 32 + resetValue: 64 + fields: + - name: RX_EOF_NUM + description: "The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel." + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: CONF_SIGLE_DATA + description: I2S signal data register + addressOffset: 104 + size: 32 + fields: + - name: SINGLE_DATA + description: The configured constant channel data to be sent out. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STATE + description: I2S TX status register + addressOffset: 108 + size: 32 + resetValue: 1 + fields: + - name: TX_IDLE + description: "1: i2s_tx is idle state. 0: i2s_tx is working." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: Version control register + addressOffset: 128 + size: 32 + resetValue: 33591408 + fields: + - name: DATE + description: I2S version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: I2S1 + description: I2S (Inter-IC Sound) Controller 1 + groupName: I2S1 + baseAddress: 1610797056 + addressBlock: + - offset: 0 + size: 84 + usage: registers + interrupt: + - name: I2S1 + value: 26 + registers: + - register: + name: INT_RAW + description: "I2S interrupt raw register, valid in level." + addressOffset: 12 + size: 32 + fields: + - name: RX_DONE_INT_RAW + description: The raw interrupt status bit for the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_RAW + description: The raw interrupt status bit for the i2s_tx_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_RAW + description: The raw interrupt status bit for the i2s_rx_hung_int interrupt + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_RAW + description: The raw interrupt status bit for the i2s_tx_hung_int interrupt + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: I2S interrupt status register. + addressOffset: 16 + size: 32 + fields: + - name: RX_DONE_INT_ST + description: The masked interrupt status bit for the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_ST + description: The masked interrupt status bit for the i2s_tx_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_ST + description: The masked interrupt status bit for the i2s_rx_hung_int interrupt + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_ST + description: The masked interrupt status bit for the i2s_tx_hung_int interrupt + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: I2S interrupt enable register. + addressOffset: 20 + size: 32 + fields: + - name: RX_DONE_INT_ENA + description: The interrupt enable bit for the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_ENA + description: The interrupt enable bit for the i2s_tx_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_HUNG_INT_ENA + description: The interrupt enable bit for the i2s_rx_hung_int interrupt + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_HUNG_INT_ENA + description: The interrupt enable bit for the i2s_tx_hung_int interrupt + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: I2S interrupt clear register. + addressOffset: 24 + size: 32 + fields: + - name: RX_DONE_INT_CLR + description: Set this bit to clear the i2s_rx_done_int interrupt + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TX_DONE_INT_CLR + description: Set this bit to clear the i2s_tx_done_int interrupt + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_HUNG_INT_CLR + description: Set this bit to clear the i2s_rx_hung_int interrupt + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TX_HUNG_INT_CLR + description: Set this bit to clear the i2s_tx_hung_int interrupt + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: RX_CONF + description: I2S RX configure register + addressOffset: 32 + size: 32 + resetValue: 38400 + fields: + - name: RX_RESET + description: Set this bit to reset receiver + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: RX_FIFO_RESET + description: Set this bit to reset Rx AFIFO + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_START + description: Set this bit to start receiving data + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_SLAVE_MOD + description: Set this bit to enable slave receiver mode + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_MONO + description: Set this bit to enable receiver in mono mode + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RX_BIG_ENDIAN + description: "I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RX_UPDATE + description: Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RX_MONO_FST_VLD + description: "1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RX_PCM_CONF + description: "I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: RX_PCM_BYPASS + description: Set this bit to bypass Compress/Decompress module for received data. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RX_STOP_MODE + description: "0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full." + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: RX_LEFT_ALIGN + description: "1: I2S RX left alignment mode. 0: I2S RX right alignment mode." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RX_24_FILL_EN + description: "1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RX_WS_IDLE_POL + description: "0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: RX_BIT_ORDER + description: "I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RX_TDM_EN + description: "1: Enable I2S TDM Rx mode . 0: Disable." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RX_PDM_EN + description: "1: Enable I2S PDM Rx mode . 0: Disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: TX_CONF + description: I2S TX configure register + addressOffset: 36 + size: 32 + resetValue: 45568 + fields: + - name: TX_RESET + description: Set this bit to reset transmitter + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TX_FIFO_RESET + description: Set this bit to reset Tx AFIFO + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TX_START + description: Set this bit to start transmitting data + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_SLAVE_MOD + description: Set this bit to enable slave transmitter mode + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_MONO + description: Set this bit to enable transmitter in mono mode + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TX_CHAN_EQUAL + description: "1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_BIG_ENDIAN + description: "I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TX_UPDATE + description: Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TX_MONO_FST_VLD + description: "1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TX_PCM_CONF + description: "I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: TX_PCM_BYPASS + description: Set this bit to bypass Compress/Decompress module for transmitted data. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_STOP_EN + description: Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_LEFT_ALIGN + description: "1: I2S TX left alignment mode. 0: I2S TX right alignment mode." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TX_24_FILL_EN + description: "1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: TX_WS_IDLE_POL + description: "0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: TX_BIT_ORDER + description: "I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TX_TDM_EN + description: "1: Enable I2S TDM Tx mode . 0: Disable." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: TX_PDM_EN + description: "1: Enable I2S PDM Tx mode . 0: Disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TX_CHAN_MOD + description: I2S transmitter channel mode configuration bits. + bitOffset: 24 + bitWidth: 3 + access: read-write + - name: SIG_LOOPBACK + description: Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals. + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: RX_CONF1 + description: I2S RX configure register 1 + addressOffset: 40 + size: 32 + resetValue: 792584960 + fields: + - name: RX_TDM_WS_WIDTH + description: "The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck" + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: RX_BCK_DIV_NUM + description: Bit clock configuration bits in receiver mode. + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: RX_BITS_MOD + description: "Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode." + bitOffset: 13 + bitWidth: 5 + access: read-write + - name: RX_HALF_SAMPLE_BITS + description: I2S Rx half sample bits -1. + bitOffset: 18 + bitWidth: 6 + access: read-write + - name: RX_TDM_CHAN_BITS + description: The Rx bit number for each channel minus 1in TDM mode. + bitOffset: 24 + bitWidth: 5 + access: read-write + - name: RX_MSB_SHIFT + description: Set this bit to enable receiver in Phillips standard mode + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: TX_CONF1 + description: I2S TX configure register 1 + addressOffset: 44 + size: 32 + resetValue: 1866326784 + fields: + - name: TX_TDM_WS_WIDTH + description: "The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck" + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: TX_BCK_DIV_NUM + description: Bit clock configuration bits in transmitter mode. + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: TX_BITS_MOD + description: "Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode." + bitOffset: 13 + bitWidth: 5 + access: read-write + - name: TX_HALF_SAMPLE_BITS + description: I2S Tx half sample bits -1. + bitOffset: 18 + bitWidth: 6 + access: read-write + - name: TX_TDM_CHAN_BITS + description: The Tx bit number for each channel minus 1in TDM mode. + bitOffset: 24 + bitWidth: 5 + access: read-write + - name: TX_MSB_SHIFT + description: Set this bit to enable transmitter in Phillips standard mode + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TX_BCK_NO_DLY + description: "1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode." + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: RX_CLKM_CONF + description: I2S RX clock configure register + addressOffset: 48 + size: 32 + resetValue: 2 + fields: + - name: RX_CLKM_DIV_NUM + description: Integral I2S clock divider value + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: RX_CLK_ACTIVE + description: I2S Rx module clock enable signal. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RX_CLK_SEL + description: "Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in." + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: MCLK_SEL + description: "0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT." + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: TX_CLKM_CONF + description: I2S TX clock configure register + addressOffset: 52 + size: 32 + resetValue: 2 + fields: + - name: TX_CLKM_DIV_NUM + description: "Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TX_CLK_ACTIVE + description: I2S Tx module clock enable signal. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TX_CLK_SEL + description: "Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in." + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: CLK_EN + description: Set this bit to enable clk gate + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: RX_CLKM_DIV_CONF + description: I2S RX module clock divider configure register + addressOffset: 56 + size: 32 + resetValue: 512 + fields: + - name: RX_CLKM_DIV_Z + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b)." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: RX_CLKM_DIV_Y + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b))." + bitOffset: 9 + bitWidth: 9 + access: read-write + - name: RX_CLKM_DIV_X + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1." + bitOffset: 18 + bitWidth: 9 + access: read-write + - name: RX_CLKM_DIV_YN1 + description: "For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1." + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: TX_CLKM_DIV_CONF + description: I2S TX module clock divider configure register + addressOffset: 60 + size: 32 + resetValue: 512 + fields: + - name: TX_CLKM_DIV_Z + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b)." + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: TX_CLKM_DIV_Y + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b))." + bitOffset: 9 + bitWidth: 9 + access: read-write + - name: TX_CLKM_DIV_X + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1." + bitOffset: 18 + bitWidth: 9 + access: read-write + - name: TX_CLKM_DIV_YN1 + description: "For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1." + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: RX_TDM_CTRL + description: I2S TX TDM mode control register + addressOffset: 80 + size: 32 + resetValue: 65535 + fields: + - name: RX_TDM_PDM_CHAN0_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN1_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN2_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN3_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN4_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN5_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN6_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_TDM_PDM_CHAN7_EN + description: "1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN8_EN + description: "1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN9_EN + description: "1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN10_EN + description: "1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN11_EN + description: "1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN12_EN + description: "1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN13_EN + description: "1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN14_EN + description: "1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RX_TDM_CHAN15_EN + description: "1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RX_TDM_TOT_CHAN_NUM + description: The total channel number of I2S TX TDM mode. + bitOffset: 16 + bitWidth: 4 + access: read-write + - register: + name: TX_TDM_CTRL + description: I2S TX TDM mode control register + addressOffset: 84 + size: 32 + resetValue: 65535 + fields: + - name: TX_TDM_CHAN0_EN + description: "1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN1_EN + description: "1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN2_EN + description: "1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN3_EN + description: "1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN4_EN + description: "1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN5_EN + description: "1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN6_EN + description: "1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN7_EN + description: "1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN8_EN + description: "1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN9_EN + description: "1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN10_EN + description: "1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN11_EN + description: "1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN12_EN + description: "1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN13_EN + description: "1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN14_EN + description: "1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TX_TDM_CHAN15_EN + description: "1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TX_TDM_TOT_CHAN_NUM + description: The total channel number of I2S TX TDM mode. + bitOffset: 16 + bitWidth: 4 + access: read-write + - name: TX_TDM_SKIP_MSK_EN + description: "When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels." + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: RX_TIMING + description: I2S RX timing control register + addressOffset: 88 + size: 32 + fields: + - name: RX_SD_IN_DM + description: "The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: RX_WS_OUT_DM + description: "The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: RX_BCK_OUT_DM + description: "The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: RX_WS_IN_DM + description: "The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: RX_BCK_IN_DM + description: "The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 28 + bitWidth: 2 + access: read-write + - register: + name: TX_TIMING + description: I2S TX timing control register + addressOffset: 92 + size: 32 + fields: + - name: TX_SD_OUT_DM + description: "The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: TX_SD1_OUT_DM + description: "The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: TX_WS_OUT_DM + description: "The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: TX_BCK_OUT_DM + description: "The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TX_WS_IN_DM + description: "The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: TX_BCK_IN_DM + description: "The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used." + bitOffset: 28 + bitWidth: 2 + access: read-write + - register: + name: LC_HUNG_CONF + description: I2S HUNG configure register. + addressOffset: 96 + size: 32 + resetValue: 2064 + fields: + - name: LC_FIFO_TIMEOUT + description: the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: LC_FIFO_TIMEOUT_SHIFT + description: The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift + bitOffset: 8 + bitWidth: 3 + access: read-write + - name: LC_FIFO_TIMEOUT_ENA + description: The enable bit for FIFO timeout + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: RXEOF_NUM + description: I2S RX data number control register. + addressOffset: 100 + size: 32 + resetValue: 64 + fields: + - name: RX_EOF_NUM + description: "The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel." + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: CONF_SIGLE_DATA + description: I2S signal data register + addressOffset: 104 + size: 32 + fields: + - name: SINGLE_DATA + description: The configured constant channel data to be sent out. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STATE + description: I2S TX status register + addressOffset: 108 + size: 32 + resetValue: 1 + fields: + - name: TX_IDLE + description: "1: i2s_tx is idle state. 0: i2s_tx is working." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: Version control register + addressOffset: 128 + size: 32 + resetValue: 33591408 + fields: + - name: DATE + description: I2S version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: INTERRUPT_CORE0 + description: Interrupt Controller (Core 0) + groupName: INTERRUPT_CORE0 + baseAddress: 1611407360 + addressBlock: + - offset: 0 + size: 420 + usage: registers + interrupt: + - name: WIFI_MAC + value: 0 + - name: WIFI_NMI + value: 1 + - name: WIFI_PWR + value: 2 + - name: WIFI_BB + value: 3 + - name: BT_MAC + value: 4 + - name: BT_BB + value: 5 + - name: BT_BB_NMI + value: 6 + - name: RWBT + value: 7 + - name: RWBLE + value: 8 + - name: RWBT_NMI + value: 9 + - name: RWBLE_NMI + value: 10 + - name: SLC0 + value: 12 + - name: SLC1 + value: 13 + - name: SDIO_HOST + value: 30 + - name: WDT + value: 47 + - name: CACHE_IA + value: 56 + - name: DCACHE_PRELOAD0 + value: 61 + - name: ICACHE_PRELOAD0 + value: 62 + - name: DCACHE_SYNC0 + value: 63 + - name: ICACHE_SYNC0 + value: 64 + - name: FROM_CPU_INTR0 + value: 79 + - name: FROM_CPU_INTR1 + value: 80 + - name: FROM_CPU_INTR2 + value: 81 + - name: FROM_CPU_INTR3 + value: 82 + - name: CORE0_IRAM0_PMS + value: 85 + - name: CORE0_DRAM0_PMS + value: 86 + - name: CORE0_PIF_PMS + value: 87 + - name: CORE0_PIF_PMS_SIZE + value: 88 + - name: CACHE_CORE0_ACS + value: 94 + registers: + - register: + name: PRO_MAC_INTR_MAP + description: mac interrupt configuration register + addressOffset: 0 + size: 32 + resetValue: 16 + fields: + - name: MAC_INTR_MAP + description: "this register used to map mac interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: MAC_NMI_MAP + description: mac_nmi interrupt configuration register + addressOffset: 4 + size: 32 + resetValue: 16 + fields: + - name: MAC_NMI_MAP + description: "this register used to map_nmi interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PWR_INTR_MAP + description: pwr interrupt configuration register + addressOffset: 8 + size: 32 + resetValue: 16 + fields: + - name: PWR_INTR_MAP + description: "this register used to map pwr interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BB_INT_MAP + description: bb interrupt configuration register + addressOffset: 12 + size: 32 + resetValue: 16 + fields: + - name: BB_INT_MAP + description: "this register used to map bb interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BT_MAC_INT_MAP + description: bb_mac interrupt configuration register + addressOffset: 16 + size: 32 + resetValue: 16 + fields: + - name: BT_MAC_INT_MAP + description: "this register used to map bb_mac interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BT_BB_INT_MAP + description: bt_bb interrupt configuration register + addressOffset: 20 + size: 32 + resetValue: 16 + fields: + - name: BT_BB_INT_MAP + description: "this register used to map bt_bb interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BT_BB_NMI_MAP + description: bt_bb_nmi interrupt configuration register + addressOffset: 24 + size: 32 + resetValue: 16 + fields: + - name: BT_BB_NMI_MAP + description: "this register used to map bb_bt_nmi interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RWBT_IRQ_MAP + description: rwbt_irq interrupt configuration register + addressOffset: 28 + size: 32 + resetValue: 16 + fields: + - name: RWBT_IRQ_MAP + description: "this register used to map rwbt_irq interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RWBLE_IRQ_MAP + description: rwble_irq interrupt configuration register + addressOffset: 32 + size: 32 + resetValue: 16 + fields: + - name: RWBLE_IRQ_MAP + description: "this register used to map rwble_irq interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RWBT_NMI_MAP + description: rwbt_nmi interrupt configuration register + addressOffset: 36 + size: 32 + resetValue: 16 + fields: + - name: RWBT_NMI_MAP + description: "this register used to map mac rwbt_nmi to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RWBLE_NMI_MAP + description: rwble_nmi interrupt configuration register + addressOffset: 40 + size: 32 + resetValue: 16 + fields: + - name: RWBLE_NMI_MAP + description: "this register used to map rwble_nmi interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: I2C_MST_INT_MAP + description: i2c_mst interrupt configuration register + addressOffset: 44 + size: 32 + resetValue: 16 + fields: + - name: I2C_MST_INT_MAP + description: "this register used to map i2c_mst interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SLC0_INTR_MAP + description: slc0 interrupt configuration register + addressOffset: 48 + size: 32 + resetValue: 16 + fields: + - name: SLC0_INTR_MAP + description: "this register used to map slc0 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SLC1_INTR_MAP + description: slc1 interrupt configuration register + addressOffset: 52 + size: 32 + resetValue: 16 + fields: + - name: SLC1_INTR_MAP + description: "this register used to map slc1 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: UHCI0_INTR_MAP + description: uhci0 interrupt configuration register + addressOffset: 56 + size: 32 + resetValue: 16 + fields: + - name: UHCI0_INTR_MAP + description: "this register used to map uhci0 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: UHCI1_INTR_MAP + description: uhci1 interrupt configuration register + addressOffset: 60 + size: 32 + resetValue: 16 + fields: + - name: UHCI1_INTR_MAP + description: "this register used to map uhci1 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: GPIO_INTERRUPT_PRO_MAP + description: gpio_interrupt_pro interrupt configuration register + addressOffset: 64 + size: 32 + resetValue: 16 + fields: + - name: GPIO_INTERRUPT_PRO_MAP + description: "this register used to map gpio_interrupt_pro interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: GPIO_INTERRUPT_PRO_NMI_MAP + description: gpio_interrupt_pro_nmi interrupt configuration register + addressOffset: 68 + size: 32 + resetValue: 16 + fields: + - name: GPIO_INTERRUPT_PRO_NMI_MAP + description: "this register used to map gpio_interrupt_pro_nmi interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: GPIO_INTERRUPT_APP_MAP + description: gpio_interrupt_app interrupt configuration register + addressOffset: 72 + size: 32 + resetValue: 16 + fields: + - name: GPIO_INTERRUPT_APP_MAP + description: "this register used to map gpio_interrupt_app interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: GPIO_INTERRUPT_APP_NMI_MAP + description: gpio_interrupt_app_nmi interrupt configuration register + addressOffset: 76 + size: 32 + resetValue: 16 + fields: + - name: GPIO_INTERRUPT_APP_NMI_MAP + description: "this register used to map gpio_interrupt_app_nmi interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SPI_INTR_1_MAP + description: spi_intr_1 interrupt configuration register + addressOffset: 80 + size: 32 + resetValue: 16 + fields: + - name: SPI_INTR_1_MAP + description: "this register used to map spi_intr_1 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SPI_INTR_2_MAP + description: spi_intr_2 interrupt configuration register + addressOffset: 84 + size: 32 + resetValue: 16 + fields: + - name: SPI_INTR_2_MAP + description: "this register used to map spi_intr_2 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SPI_INTR_3_MAP + description: spi_intr_3 interrupt configuration register + addressOffset: 88 + size: 32 + resetValue: 16 + fields: + - name: SPI_INTR_3_MAP + description: "this register used to map spi_intr_3 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SPI_INTR_4_MAP + description: spi_intr_4 interrupt configuration register + addressOffset: 92 + size: 32 + resetValue: 16 + fields: + - name: SPI_INTR_4_MAP + description: "this register used to map spi_intr_4 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: LCD_CAM_INT_MAP + description: lcd_cam interrupt configuration register + addressOffset: 96 + size: 32 + resetValue: 16 + fields: + - name: LCD_CAM_INT_MAP + description: "this register used to map lcd_cam interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: I2S0_INT_MAP + description: i2s0 interrupt configuration register + addressOffset: 100 + size: 32 + resetValue: 16 + fields: + - name: I2S0_INT_MAP + description: "this register used to map i2s0 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: I2S1_INT_MAP + description: i2s1 interrupt configuration register + addressOffset: 104 + size: 32 + resetValue: 16 + fields: + - name: I2S1_INT_MAP + description: "this register used to map i2s1 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: UART_INTR_MAP + description: uart interrupt configuration register + addressOffset: 108 + size: 32 + resetValue: 16 + fields: + - name: UART_INTR_MAP + description: "this register used to map uart interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: UART1_INTR_MAP + description: uart1 interrupt configuration register + addressOffset: 112 + size: 32 + resetValue: 16 + fields: + - name: UART1_INTR_MAP + description: "this register used to map uart1 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: UART2_INTR_MAP + description: uart2 interrupt configuration register + addressOffset: 116 + size: 32 + resetValue: 16 + fields: + - name: UART2_INTR_MAP + description: "this register used to map uart2 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SDIO_HOST_INTERRUPT_MAP + description: sdio_host interrupt configuration register + addressOffset: 120 + size: 32 + resetValue: 16 + fields: + - name: SDIO_HOST_INTERRUPT_MAP + description: "this register used to map sdio_host interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PWM0_INTR_MAP + description: pwm0 interrupt configuration register + addressOffset: 124 + size: 32 + resetValue: 16 + fields: + - name: PWM0_INTR_MAP + description: "this register used to map pwm0 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PWM1_INTR_MAP + description: pwm1 interrupt configuration register + addressOffset: 128 + size: 32 + resetValue: 16 + fields: + - name: PWM1_INTR_MAP + description: "this register used to map pwm1 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PWM2_INTR_MAP + description: pwm2 interrupt configuration register + addressOffset: 132 + size: 32 + resetValue: 16 + fields: + - name: PWM2_INTR_MAP + description: "this register used to map pwm2 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PWM3_INTR_MAP + description: pwm3 interrupt configuration register + addressOffset: 136 + size: 32 + resetValue: 16 + fields: + - name: PWM3_INTR_MAP + description: "this register used to map pwm3 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: LEDC_INT_MAP + description: ledc interrupt configuration register + addressOffset: 140 + size: 32 + resetValue: 16 + fields: + - name: LEDC_INT_MAP + description: "this register used to map ledc interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: EFUSE_INT_MAP + description: efuse interrupt configuration register + addressOffset: 144 + size: 32 + resetValue: 16 + fields: + - name: EFUSE_INT_MAP + description: "this register used to map efuse interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CAN_INT_MAP + description: can interrupt configuration register + addressOffset: 148 + size: 32 + resetValue: 16 + fields: + - name: CAN_INT_MAP + description: "this register used to map can interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: USB_INTR_MAP + description: usb interrupt configuration register + addressOffset: 152 + size: 32 + resetValue: 16 + fields: + - name: USB_INTR_MAP + description: "this register used to map usb interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RTC_CORE_INTR_MAP + description: rtc_core interrupt configuration register + addressOffset: 156 + size: 32 + resetValue: 16 + fields: + - name: RTC_CORE_INTR_MAP + description: "this register used to map rtc_core interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RMT_INTR_MAP + description: rmt interrupt configuration register + addressOffset: 160 + size: 32 + resetValue: 16 + fields: + - name: RMT_INTR_MAP + description: "this register used to map rmt interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PCNT_INTR_MAP + description: pcnt interrupt configuration register + addressOffset: 164 + size: 32 + resetValue: 16 + fields: + - name: PCNT_INTR_MAP + description: "this register used to map pcnt interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: I2C_EXT0_INTR_MAP + description: i2c_ext0 interrupt configuration register + addressOffset: 168 + size: 32 + resetValue: 16 + fields: + - name: I2C_EXT0_INTR_MAP + description: "this register used to map i2c_ext0 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: I2C_EXT1_INTR_MAP + description: i2c_ext1 interrupt configuration register + addressOffset: 172 + size: 32 + resetValue: 16 + fields: + - name: I2C_EXT1_INTR_MAP + description: "this register used to map i2c_ext1 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SPI2_DMA_INT_MAP + description: spi2_dma interrupt configuration register + addressOffset: 176 + size: 32 + resetValue: 16 + fields: + - name: SPI2_DMA_INT_MAP + description: "this register used to map spi2_dma interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SPI3_DMA_INT_MAP + description: spi3_dma interrupt configuration register + addressOffset: 180 + size: 32 + resetValue: 16 + fields: + - name: SPI3_DMA_INT_MAP + description: "this register used to map spi3_dma interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SPI4_DMA_INT_MAP + description: spi4_dma interrupt configuration register + addressOffset: 184 + size: 32 + resetValue: 16 + fields: + - name: SPI4_DMA_INT_MAP + description: "this register used to map spi4_dma interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: WDG_INT_MAP + description: wdg interrupt configuration register + addressOffset: 188 + size: 32 + resetValue: 16 + fields: + - name: WDG_INT_MAP + description: "this register used to map wdg interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TIMER_INT1_MAP + description: timer_int1 interrupt configuration register + addressOffset: 192 + size: 32 + resetValue: 16 + fields: + - name: TIMER_INT1_MAP + description: "this register used to map timer_int1 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TIMER_INT2_MAP + description: timer_int2 interrupt configuration register + addressOffset: 196 + size: 32 + resetValue: 16 + fields: + - name: TIMER_INT2_MAP + description: "this register used to map timer_int2 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG_T0_INT_MAP + description: tg_t0 interrupt configuration register + addressOffset: 200 + size: 32 + resetValue: 16 + fields: + - name: TG_T0_INT_MAP + description: "this register used to map tg_t0 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG_T1_INT_MAP + description: tg_t1 interrupt configuration register + addressOffset: 204 + size: 32 + resetValue: 16 + fields: + - name: TG_T1_INT_MAP + description: "this register used to map tg_t1 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG_WDT_INT_MAP + description: tg_wdt interrupt configuration register + addressOffset: 208 + size: 32 + resetValue: 16 + fields: + - name: TG_WDT_INT_MAP + description: "this register used to map rg_wdt interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG1_T0_INT_MAP + description: tg1_t0 interrupt configuration register + addressOffset: 212 + size: 32 + resetValue: 16 + fields: + - name: TG1_T0_INT_MAP + description: "this register used to map tg1_t0 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG1_T1_INT_MAP + description: tg1_t1 interrupt configuration register + addressOffset: 216 + size: 32 + resetValue: 16 + fields: + - name: TG1_T1_INT_MAP + description: "this register used to map tg1_t1 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG1_WDT_INT_MAP + description: tg1_wdt interrupt configuration register + addressOffset: 220 + size: 32 + resetValue: 16 + fields: + - name: TG1_WDT_INT_MAP + description: "this register used to map tg1_wdt interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CACHE_IA_INT_MAP + description: cache_ia interrupt configuration register + addressOffset: 224 + size: 32 + resetValue: 16 + fields: + - name: CACHE_IA_INT_MAP + description: "this register used to map cache_ia interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SYSTIMER_TARGET0_INT_MAP + description: systimer_target0 interrupt configuration register + addressOffset: 228 + size: 32 + resetValue: 16 + fields: + - name: SYSTIMER_TARGET0_INT_MAP + description: "this register used to map systimer_target0 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SYSTIMER_TARGET1_INT_MAP + description: systimer_target1 interrupt configuration register + addressOffset: 232 + size: 32 + resetValue: 16 + fields: + - name: SYSTIMER_TARGET1_INT_MAP + description: "this register used to map systimer_target1 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SYSTIMER_TARGET2_INT_MAP + description: systimer_target2 interrupt configuration register + addressOffset: 236 + size: 32 + resetValue: 16 + fields: + - name: SYSTIMER_TARGET2_INT_MAP + description: "this register used to map systimer_target2 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SPI_MEM_REJECT_INTR_MAP + description: spi_mem_reject interrupt configuration register + addressOffset: 240 + size: 32 + resetValue: 16 + fields: + - name: SPI_MEM_REJECT_INTR_MAP + description: "this register used to map spi_mem_reject interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DCACHE_PRELOAD_INT_MAP + description: dcache_prelaod interrupt configuration register + addressOffset: 244 + size: 32 + resetValue: 16 + fields: + - name: DCACHE_PRELOAD_INT_MAP + description: "this register used to map dcache_prelaod interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: ICACHE_PRELOAD_INT_MAP + description: icache_preload interrupt configuration register + addressOffset: 248 + size: 32 + resetValue: 16 + fields: + - name: ICACHE_PRELOAD_INT_MAP + description: "this register used to map icache_preload interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DCACHE_SYNC_INT_MAP + description: dcache_sync interrupt configuration register + addressOffset: 252 + size: 32 + resetValue: 16 + fields: + - name: DCACHE_SYNC_INT_MAP + description: "this register used to map dcache_sync interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: ICACHE_SYNC_INT_MAP + description: icache_sync interrupt configuration register + addressOffset: 256 + size: 32 + resetValue: 16 + fields: + - name: ICACHE_SYNC_INT_MAP + description: "this register used to map icache_sync interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APB_ADC_INT_MAP + description: apb_adc interrupt configuration register + addressOffset: 260 + size: 32 + resetValue: 16 + fields: + - name: APB_ADC_INT_MAP + description: "this register used to map apb_adc interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_IN_CH0_INT_MAP + description: dma_in_ch0 interrupt configuration register + addressOffset: 264 + size: 32 + resetValue: 16 + fields: + - name: DMA_IN_CH0_INT_MAP + description: "this register used to map dma_in_ch0 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_IN_CH1_INT_MAP + description: dma_in_ch1 interrupt configuration register + addressOffset: 268 + size: 32 + resetValue: 16 + fields: + - name: DMA_IN_CH1_INT_MAP + description: "this register used to map dma_in_ch1 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_IN_CH2_INT_MAP + description: dma_in_ch2 interrupt configuration register + addressOffset: 272 + size: 32 + resetValue: 16 + fields: + - name: DMA_IN_CH2_INT_MAP + description: "this register used to map dma_in_ch2 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_IN_CH3_INT_MAP + description: dma_in_ch3 interrupt configuration register + addressOffset: 276 + size: 32 + resetValue: 16 + fields: + - name: DMA_IN_CH3_INT_MAP + description: "this register used to map dma_in_ch3 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_IN_CH4_INT_MAP + description: dma_in_ch4 interrupt configuration register + addressOffset: 280 + size: 32 + resetValue: 16 + fields: + - name: DMA_IN_CH4_INT_MAP + description: "this register used to map dma_in_ch4 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_OUT_CH0_INT_MAP + description: dma_out_ch0 interrupt configuration register + addressOffset: 284 + size: 32 + resetValue: 16 + fields: + - name: DMA_OUT_CH0_INT_MAP + description: "this register used to map dma_out_ch0 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_OUT_CH1_INT_MAP + description: dma_out_ch1 interrupt configuration register + addressOffset: 288 + size: 32 + resetValue: 16 + fields: + - name: DMA_OUT_CH1_INT_MAP + description: "this register used to map dma_out_ch1 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_OUT_CH2_INT_MAP + description: dma_out_ch2 interrupt configuration register + addressOffset: 292 + size: 32 + resetValue: 16 + fields: + - name: DMA_OUT_CH2_INT_MAP + description: "this register used to map dma_out_ch2 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_OUT_CH3_INT_MAP + description: dma_out_ch3 interrupt configuration register + addressOffset: 296 + size: 32 + resetValue: 16 + fields: + - name: DMA_OUT_CH3_INT_MAP + description: "this register used to map dma_out_ch3 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_OUT_CH4_INT_MAP + description: dma_out_ch4 interrupt configuration register + addressOffset: 300 + size: 32 + resetValue: 16 + fields: + - name: DMA_OUT_CH4_INT_MAP + description: "this register used to map dma_out_ch4 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RSA_INT_MAP + description: rsa interrupt configuration register + addressOffset: 304 + size: 32 + resetValue: 16 + fields: + - name: RSA_INT_MAP + description: "this register used to map rsa interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: AES_INT_MAP + description: aes interrupt configuration register + addressOffset: 308 + size: 32 + resetValue: 16 + fields: + - name: AES_INT_MAP + description: "this register used to map aes interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SHA_INT_MAP + description: sha interrupt configuration register + addressOffset: 312 + size: 32 + resetValue: 16 + fields: + - name: SHA_INT_MAP + description: "this register used to map sha interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_0_MAP + description: cpu_intr_from_cpu_0 interrupt configuration register + addressOffset: 316 + size: 32 + resetValue: 16 + fields: + - name: CPU_INTR_FROM_CPU_0_MAP + description: "this register used to map cpu_intr_from_cpu_0 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_1_MAP + description: cpu_intr_from_cpu_1 interrupt configuration register + addressOffset: 320 + size: 32 + resetValue: 16 + fields: + - name: CPU_INTR_FROM_CPU_1_MAP + description: "this register used to map cpu_intr_from_cpu_1 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_2_MAP + description: cpu_intr_from_cpu_2 interrupt configuration register + addressOffset: 324 + size: 32 + resetValue: 16 + fields: + - name: CPU_INTR_FROM_CPU_2_MAP + description: "this register used to map cpu_intr_from_cpu_2 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_3_MAP + description: cpu_intr_from_cpu_3 interrupt configuration register + addressOffset: 328 + size: 32 + resetValue: 16 + fields: + - name: CPU_INTR_FROM_CPU_3_MAP + description: "this register used to map cpu_intr_from_cpu_3 interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: ASSIST_DEBUG_INTR_MAP + description: assist_debug interrupt configuration register + addressOffset: 332 + size: 32 + resetValue: 16 + fields: + - name: ASSIST_DEBUG_INTR_MAP + description: "this register used to map assist_debug interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP + description: dma_pms_monitor_violatile interrupt configuration register + addressOffset: 336 + size: 32 + resetValue: 16 + fields: + - name: DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP + description: "this register used to map dma_pms_monitor_violatile interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + description: core0_IRam0_pms_monitor_violatile interrupt configuration register + addressOffset: 340 + size: 32 + resetValue: 16 + fields: + - name: CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + description: "this register used to map core0_IRam0_pms_monitor_violatile interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + description: core0_DRam0_pms_monitor_violatile interrupt configuration register + addressOffset: 344 + size: 32 + resetValue: 16 + fields: + - name: CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + description: "this register used to map core0_DRam0_pms_monitor_violatile interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + description: core0_PIF_pms_monitor_violatile interrupt configuration register + addressOffset: 348 + size: 32 + resetValue: 16 + fields: + - name: CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + description: "this register used to map core0_PIF_pms_monitor_violatile interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + description: core0_PIF_pms_monitor_violatile_size interrupt configuration register + addressOffset: 352 + size: 32 + resetValue: 16 + fields: + - name: CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + description: "this register used to map core0_PIF_pms_monitor_violatile_size interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + description: core1_IRam0_pms_monitor_violatile interrupt configuration register + addressOffset: 356 + size: 32 + resetValue: 16 + fields: + - name: CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + description: "this register used to map core1_IRam0_pms_monitor_violatile interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + description: core1_DRam0_pms_monitor_violatile interrupt configuration register + addressOffset: 360 + size: 32 + resetValue: 16 + fields: + - name: CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + description: "this register used to map core1_DRam0_pms_monitor_violatile interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + description: core1_PIF_pms_monitor_violatile interrupt configuration register + addressOffset: 364 + size: 32 + resetValue: 16 + fields: + - name: CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + description: "this register used to map core1_PIF_pms_monitor_violatile interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + description: core1_PIF_pms_monitor_violatile_size interrupt configuration register + addressOffset: 368 + size: 32 + resetValue: 16 + fields: + - name: CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + description: "this register used to map core1_PIF_pms_monitor_violatile_size interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BACKUP_PMS_VIOLATE_INTR_MAP + description: backup_pms_monitor_violatile interrupt configuration register + addressOffset: 372 + size: 32 + resetValue: 16 + fields: + - name: BACKUP_PMS_VIOLATE_INTR_MAP + description: "this register used to map backup_pms_monitor_violatile interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CACHE_CORE0_ACS_INT_MAP + description: cache_core0_acs interrupt configuration register + addressOffset: 376 + size: 32 + resetValue: 16 + fields: + - name: CACHE_CORE0_ACS_INT_MAP + description: "this register used to map cache_core0_acs interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CACHE_CORE1_ACS_INT_MAP + description: cache_core1_acs interrupt configuration register + addressOffset: 380 + size: 32 + resetValue: 16 + fields: + - name: CACHE_CORE1_ACS_INT_MAP + description: "this register used to map cache_core1_acs interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: USB_DEVICE_INT_MAP + description: usb_device interrupt configuration register + addressOffset: 384 + size: 32 + resetValue: 16 + fields: + - name: USB_DEVICE_INT_MAP + description: "this register used to map usb_device interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PERI_BACKUP_INT_MAP + description: peri_backup interrupt configuration register + addressOffset: 388 + size: 32 + resetValue: 16 + fields: + - name: PERI_BACKUP_INT_MAP + description: "this register used to map peri_backup interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_EXTMEM_REJECT_INT_MAP + description: dma_extmem_reject interrupt configuration register + addressOffset: 392 + size: 32 + resetValue: 16 + fields: + - name: DMA_EXTMEM_REJECT_INT_MAP + description: "this register used to map dma_extmem_reject interrupt to one of core0's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PRO_INTR_STATUS_0 + description: interrupt status register + addressOffset: 396 + size: 32 + fields: + - name: INTR_STATUS_0 + description: this register store the status of the first 32 interrupt source + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PRO_INTR_STATUS_1 + description: interrupt status register + addressOffset: 400 + size: 32 + fields: + - name: INTR_STATUS_1 + description: this register store the status of the first 32 interrupt source + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PRO_INTR_STATUS_2 + description: interrupt status register + addressOffset: 404 + size: 32 + fields: + - name: INTR_STATUS_2 + description: this register store the status of the first 32 interrupt source + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PRO_INTR_STATUS_3 + description: interrupt status register + addressOffset: 408 + size: 32 + fields: + - name: INTR_STATUS_3 + description: this register store the status of the first 32 interrupt source + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CLOCK_GATE + description: clock gate register + addressOffset: 412 + size: 32 + resetValue: 1 + fields: + - name: REG_CLK_EN + description: this register uesd to control clock-gating interupt martrix + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: version register + addressOffset: 2044 + size: 32 + resetValue: 33628928 + fields: + - name: INTERRUPT_REG_DATE + description: version register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: INTERRUPT_CORE1 + description: Interrupt Controller (Core 1) + groupName: INTERRUPT_CORE1 + baseAddress: 1611407360 + addressBlock: + - offset: 0 + size: 420 + usage: registers + interrupt: + - name: CORE1_IRAM0_PMS + value: 89 + - name: CORE1_DRAM0_PMS + value: 90 + - name: CORE1_PIF_PMS + value: 91 + - name: CORE1_PIF_PMS_SIZE + value: 92 + - name: CACHE_CORE1_ACS + value: 95 + registers: + - register: + name: APP_MAC_INTR_MAP + description: mac interrupt configuration register + addressOffset: 2048 + size: 32 + resetValue: 16 + fields: + - name: MAC_INTR_MAP + description: "this register used to map mac interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: MAC_NMI_MAP + description: mac_nmi interrupt configuration register + addressOffset: 2052 + size: 32 + resetValue: 16 + fields: + - name: MAC_NMI_MAP + description: "this register used to map_nmi interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PWR_INTR_MAP + description: pwr interrupt configuration register + addressOffset: 2056 + size: 32 + resetValue: 16 + fields: + - name: PWR_INTR_MAP + description: "this register used to map pwr interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BB_INT_MAP + description: bb interrupt configuration register + addressOffset: 2060 + size: 32 + resetValue: 16 + fields: + - name: BB_INT_MAP + description: "this register used to map bb interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BT_MAC_INT_MAP + description: bb_mac interrupt configuration register + addressOffset: 2064 + size: 32 + resetValue: 16 + fields: + - name: BT_MAC_INT_MAP + description: "this register used to map bb_mac interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BT_BB_INT_MAP + description: bt_bb interrupt configuration register + addressOffset: 2068 + size: 32 + resetValue: 16 + fields: + - name: BT_BB_INT_MAP + description: "this register used to map bt_bb interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BT_BB_NMI_MAP + description: bt_bb_nmi interrupt configuration register + addressOffset: 2072 + size: 32 + resetValue: 16 + fields: + - name: BT_BB_NMI_MAP + description: "this register used to map bb_bt_nmi interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RWBT_IRQ_MAP + description: rwbt_irq interrupt configuration register + addressOffset: 2076 + size: 32 + resetValue: 16 + fields: + - name: RWBT_IRQ_MAP + description: "this register used to map rwbt_irq interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RWBLE_IRQ_MAP + description: rwble_irq interrupt configuration register + addressOffset: 2080 + size: 32 + resetValue: 16 + fields: + - name: RWBLE_IRQ_MAP + description: "this register used to map rwble_irq interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RWBT_NMI_MAP + description: rwbt_nmi interrupt configuration register + addressOffset: 2084 + size: 32 + resetValue: 16 + fields: + - name: RWBT_NMI_MAP + description: "this register used to map rwbt_nmi interupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RWBLE_NMI_MAP + description: rwble_nmi interrupt configuration register + addressOffset: 2088 + size: 32 + resetValue: 16 + fields: + - name: RWBLE_NMI_MAP + description: "this register used to map rwble_nmi interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: I2C_MST_INT_MAP + description: i2c_mst interrupt configuration register + addressOffset: 2092 + size: 32 + resetValue: 16 + fields: + - name: I2C_MST_INT_MAP + description: "this register used to map i2c_mst interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SLC0_INTR_MAP + description: slc0 interrupt configuration register + addressOffset: 2096 + size: 32 + resetValue: 16 + fields: + - name: SLC0_INTR_MAP + description: "this register used to map slc0 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SLC1_INTR_MAP + description: slc1 interrupt configuration register + addressOffset: 2100 + size: 32 + resetValue: 16 + fields: + - name: SLC1_INTR_MAP + description: "this register used to map slc1 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: UHCI0_INTR_MAP + description: uhci0 interrupt configuration register + addressOffset: 2104 + size: 32 + resetValue: 16 + fields: + - name: UHCI0_INTR_MAP + description: "this register used to map uhci0 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: UHCI1_INTR_MAP + description: uhci1 interrupt configuration register + addressOffset: 2108 + size: 32 + resetValue: 16 + fields: + - name: UHCI1_INTR_MAP + description: "this register used to map uhci1 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: GPIO_INTERRUPT_PRO_MAP + description: gpio_interrupt_pro interrupt configuration register + addressOffset: 2112 + size: 32 + resetValue: 16 + fields: + - name: GPIO_INTERRUPT_PRO_MAP + description: "this register used to map gpio_interrupt_pro interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: GPIO_INTERRUPT_PRO_NMI_MAP + description: gpio_interrupt_pro_nmi interrupt configuration register + addressOffset: 2116 + size: 32 + resetValue: 16 + fields: + - name: GPIO_INTERRUPT_PRO_NMI_MAP + description: "this register used to map gpio_interrupt_pro_nmi interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: GPIO_INTERRUPT_APP_MAP + description: gpio_interrupt_app interrupt configuration register + addressOffset: 2120 + size: 32 + resetValue: 16 + fields: + - name: GPIO_INTERRUPT_APP_MAP + description: "this register used to map gpio_interrupt_app interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: GPIO_INTERRUPT_APP_NMI_MAP + description: gpio_interrupt_app_nmi interrupt configuration register + addressOffset: 2124 + size: 32 + resetValue: 16 + fields: + - name: GPIO_INTERRUPT_APP_NMI_MAP + description: "this register used to map gpio_interrupt_app_nmi interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SPI_INTR_1_MAP + description: spi_intr_1 interrupt configuration register + addressOffset: 2128 + size: 32 + resetValue: 16 + fields: + - name: SPI_INTR_1_MAP + description: "this register used to map spi_intr_1 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SPI_INTR_2_MAP + description: spi_intr_2 interrupt configuration register + addressOffset: 2132 + size: 32 + resetValue: 16 + fields: + - name: SPI_INTR_2_MAP + description: "this register used to map spi_intr_2 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SPI_INTR_3_MAP + description: spi_intr_3 interrupt configuration register + addressOffset: 2136 + size: 32 + resetValue: 16 + fields: + - name: SPI_INTR_3_MAP + description: "this register used to map spi_intr_3 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SPI_INTR_4_MAP + description: spi_intr_4 interrupt configuration register + addressOffset: 2140 + size: 32 + resetValue: 16 + fields: + - name: SPI_INTR_4_MAP + description: "this register used to map spi_intr_4 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: LCD_CAM_INT_MAP + description: lcd_cam interrupt configuration register + addressOffset: 2144 + size: 32 + resetValue: 16 + fields: + - name: LCD_CAM_INT_MAP + description: "this register used to map lcd_cam interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: I2S0_INT_MAP + description: i2s0 interrupt configuration register + addressOffset: 2148 + size: 32 + resetValue: 16 + fields: + - name: I2S0_INT_MAP + description: "this register used to map i2s0 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: I2S1_INT_MAP + description: i2s1 interrupt configuration register + addressOffset: 2152 + size: 32 + resetValue: 16 + fields: + - name: I2S1_INT_MAP + description: "this register used to map i2s1 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: UART_INTR_MAP + description: uart interrupt configuration register + addressOffset: 2156 + size: 32 + resetValue: 16 + fields: + - name: UART_INTR_MAP + description: "this register used to map uart interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: UART1_INTR_MAP + description: uart1 interrupt configuration register + addressOffset: 2160 + size: 32 + resetValue: 16 + fields: + - name: UART1_INTR_MAP + description: "this register used to map uart1 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: UART2_INTR_MAP + description: uart2 interrupt configuration register + addressOffset: 2164 + size: 32 + resetValue: 16 + fields: + - name: UART2_INTR_MAP + description: "this register used to map uart2 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SDIO_HOST_INTERRUPT_MAP + description: sdio_host interrupt configuration register + addressOffset: 2168 + size: 32 + resetValue: 16 + fields: + - name: SDIO_HOST_INTERRUPT_MAP + description: "this register used to map sdio_host interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PWM0_INTR_MAP + description: pwm0 interrupt configuration register + addressOffset: 2172 + size: 32 + resetValue: 16 + fields: + - name: PWM0_INTR_MAP + description: "this register used to map pwm0 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PWM1_INTR_MAP + description: pwm1 interrupt configuration register + addressOffset: 2176 + size: 32 + resetValue: 16 + fields: + - name: PWM1_INTR_MAP + description: "this register used to map pwm1 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PWM2_INTR_MAP + description: pwm2 interrupt configuration register + addressOffset: 2180 + size: 32 + resetValue: 16 + fields: + - name: PWM2_INTR_MAP + description: "this register used to map pwm2 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PWM3_INTR_MAP + description: pwm3 interrupt configuration register + addressOffset: 2184 + size: 32 + resetValue: 16 + fields: + - name: PWM3_INTR_MAP + description: "this register used to map pwm3 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: LEDC_INT_MAP + description: ledc interrupt configuration register + addressOffset: 2188 + size: 32 + resetValue: 16 + fields: + - name: LEDC_INT_MAP + description: "this register used to map ledc interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: EFUSE_INT_MAP + description: efuse interrupt configuration register + addressOffset: 2192 + size: 32 + resetValue: 16 + fields: + - name: EFUSE_INT_MAP + description: "this register used to map efuse interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CAN_INT_MAP + description: can interrupt configuration register + addressOffset: 2196 + size: 32 + resetValue: 16 + fields: + - name: CAN_INT_MAP + description: "this register used to map can interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: USB_INTR_MAP + description: usb interrupt configuration register + addressOffset: 2200 + size: 32 + resetValue: 16 + fields: + - name: USB_INTR_MAP + description: "this register used to map usb interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RTC_CORE_INTR_MAP + description: rtc_core interrupt configuration register + addressOffset: 2204 + size: 32 + resetValue: 16 + fields: + - name: RTC_CORE_INTR_MAP + description: "this register used to map rtc_core interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RMT_INTR_MAP + description: rmt interrupt configuration register + addressOffset: 2208 + size: 32 + resetValue: 16 + fields: + - name: RMT_INTR_MAP + description: "this register used to map rmt interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PCNT_INTR_MAP + description: pcnt interrupt configuration register + addressOffset: 2212 + size: 32 + resetValue: 16 + fields: + - name: PCNT_INTR_MAP + description: "this register used to map pcnt interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: I2C_EXT0_INTR_MAP + description: i2c_ext0 interrupt configuration register + addressOffset: 2216 + size: 32 + resetValue: 16 + fields: + - name: I2C_EXT0_INTR_MAP + description: "this register used to map i2c_ext0 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: I2C_EXT1_INTR_MAP + description: i2c_ext1 interrupt configuration register + addressOffset: 2220 + size: 32 + resetValue: 16 + fields: + - name: I2C_EXT1_INTR_MAP + description: "this register used to map i2c_ext1 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SPI2_DMA_INT_MAP + description: spi2_dma interrupt configuration register + addressOffset: 2224 + size: 32 + resetValue: 16 + fields: + - name: SPI2_DMA_INT_MAP + description: "this register used to map spi2_dma interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SPI3_DMA_INT_MAP + description: spi3_dma interrupt configuration register + addressOffset: 2228 + size: 32 + resetValue: 16 + fields: + - name: SPI3_DMA_INT_MAP + description: "this register used to map spi3_dma interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SPI4_DMA_INT_MAP + description: spi4_dma interrupt configuration register + addressOffset: 2232 + size: 32 + resetValue: 16 + fields: + - name: SPI4_DMA_INT_MAP + description: "this register used to map spi4_dma interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: WDG_INT_MAP + description: wdg interrupt configuration register + addressOffset: 2236 + size: 32 + resetValue: 16 + fields: + - name: WDG_INT_MAP + description: "this register used to map wdg interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TIMER_INT1_MAP + description: timer_int1 interrupt configuration register + addressOffset: 2240 + size: 32 + resetValue: 16 + fields: + - name: TIMER_INT1_MAP + description: "this register used to map timer_int1 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TIMER_INT2_MAP + description: timer_int2 interrupt configuration register + addressOffset: 2244 + size: 32 + resetValue: 16 + fields: + - name: TIMER_INT2_MAP + description: "this register used to map timer_int2 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG_T0_INT_MAP + description: tg_t0 interrupt configuration register + addressOffset: 2248 + size: 32 + resetValue: 16 + fields: + - name: TG_T0_INT_MAP + description: "this register used to map tg_t0 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG_T1_INT_MAP + description: tg_t1 interrupt configuration register + addressOffset: 2252 + size: 32 + resetValue: 16 + fields: + - name: TG_T1_INT_MAP + description: "this register used to map tg_t1 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG_WDT_INT_MAP + description: tg_wdt interrupt configuration register + addressOffset: 2256 + size: 32 + resetValue: 16 + fields: + - name: TG_WDT_INT_MAP + description: "this register used to map rg_wdt interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG1_T0_INT_MAP + description: tg1_t0 interrupt configuration register + addressOffset: 2260 + size: 32 + resetValue: 16 + fields: + - name: TG1_T0_INT_MAP + description: "this register used to map tg1_t0 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG1_T1_INT_MAP + description: tg1_t1 interrupt configuration register + addressOffset: 2264 + size: 32 + resetValue: 16 + fields: + - name: TG1_T1_INT_MAP + description: "this register used to map tg1_t1 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: TG1_WDT_INT_MAP + description: tg1_wdt interrupt configuration register + addressOffset: 2268 + size: 32 + resetValue: 16 + fields: + - name: TG1_WDT_INT_MAP + description: "this register used to map tg1_wdt interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CACHE_IA_INT_MAP + description: cache_ia interrupt configuration register + addressOffset: 2272 + size: 32 + resetValue: 16 + fields: + - name: CACHE_IA_INT_MAP + description: "this register used to map cache_ia interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SYSTIMER_TARGET0_INT_MAP + description: systimer_target0 interrupt configuration register + addressOffset: 2276 + size: 32 + resetValue: 16 + fields: + - name: SYSTIMER_TARGET0_INT_MAP + description: "this register used to map systimer_target0 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SYSTIMER_TARGET1_INT_MAP + description: systimer_target1 interrupt configuration register + addressOffset: 2280 + size: 32 + resetValue: 16 + fields: + - name: SYSTIMER_TARGET1_INT_MAP + description: "this register used to map systimer_target1 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SYSTIMER_TARGET2_INT_MAP + description: systimer_target2 interrupt configuration register + addressOffset: 2284 + size: 32 + resetValue: 16 + fields: + - name: SYSTIMER_TARGET2_INT_MAP + description: "this register used to map systimer_target2 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SPI_MEM_REJECT_INTR_MAP + description: spi_mem_reject interrupt configuration register + addressOffset: 2288 + size: 32 + resetValue: 16 + fields: + - name: SPI_MEM_REJECT_INTR_MAP + description: "this register used to map spi_mem_reject interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DCACHE_PRELOAD_INT_MAP + description: dcache_prelaod interrupt configuration register + addressOffset: 2292 + size: 32 + resetValue: 16 + fields: + - name: DCACHE_PRELOAD_INT_MAP + description: "this register used to map dcache_prelaod interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: ICACHE_PRELOAD_INT_MAP + description: icache_preload interrupt configuration register + addressOffset: 2296 + size: 32 + resetValue: 16 + fields: + - name: ICACHE_PRELOAD_INT_MAP + description: "this register used to map icache_preload interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DCACHE_SYNC_INT_MAP + description: dcache_sync interrupt configuration register + addressOffset: 2300 + size: 32 + resetValue: 16 + fields: + - name: DCACHE_SYNC_INT_MAP + description: "this register used to map dcache_sync interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: ICACHE_SYNC_INT_MAP + description: icache_sync interrupt configuration register + addressOffset: 2304 + size: 32 + resetValue: 16 + fields: + - name: ICACHE_SYNC_INT_MAP + description: "this register used to map icache_sync interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APB_ADC_INT_MAP + description: apb_adc interrupt configuration register + addressOffset: 2308 + size: 32 + resetValue: 16 + fields: + - name: APB_ADC_INT_MAP + description: "this register used to map apb_adc interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_IN_CH0_INT_MAP + description: dma_in_ch0 interrupt configuration register + addressOffset: 2312 + size: 32 + resetValue: 16 + fields: + - name: DMA_IN_CH0_INT_MAP + description: "this register used to map dma_in_ch0 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_IN_CH1_INT_MAP + description: dma_in_ch1 interrupt configuration register + addressOffset: 2316 + size: 32 + resetValue: 16 + fields: + - name: DMA_IN_CH1_INT_MAP + description: "this register used to map dma_in_ch1 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_IN_CH2_INT_MAP + description: dma_in_ch2 interrupt configuration register + addressOffset: 2320 + size: 32 + resetValue: 16 + fields: + - name: DMA_IN_CH2_INT_MAP + description: "this register used to map dma_in_ch2 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_IN_CH3_INT_MAP + description: dma_in_ch3 interrupt configuration register + addressOffset: 2324 + size: 32 + resetValue: 16 + fields: + - name: DMA_IN_CH3_INT_MAP + description: "this register used to map dma_in_ch3 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_IN_CH4_INT_MAP + description: dma_in_ch4 interrupt configuration register + addressOffset: 2328 + size: 32 + resetValue: 16 + fields: + - name: DMA_IN_CH4_INT_MAP + description: "this register used to map dma_in_ch4 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_OUT_CH0_INT_MAP + description: dma_out_ch0 interrupt configuration register + addressOffset: 2332 + size: 32 + resetValue: 16 + fields: + - name: DMA_OUT_CH0_INT_MAP + description: "this register used to map dma_out_ch0 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_OUT_CH1_INT_MAP + description: dma_out_ch1 interrupt configuration register + addressOffset: 2336 + size: 32 + resetValue: 16 + fields: + - name: DMA_OUT_CH1_INT_MAP + description: "this register used to map dma_out_ch1 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_OUT_CH2_INT_MAP + description: dma_out_ch2 interrupt configuration register + addressOffset: 2340 + size: 32 + resetValue: 16 + fields: + - name: DMA_OUT_CH2_INT_MAP + description: "this register used to map dma_out_ch2 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_OUT_CH3_INT_MAP + description: dma_out_ch3 interrupt configuration register + addressOffset: 2344 + size: 32 + resetValue: 16 + fields: + - name: DMA_OUT_CH3_INT_MAP + description: "this register used to map dma_out_ch3 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_OUT_CH4_INT_MAP + description: dma_out_ch4 interrupt configuration register + addressOffset: 2348 + size: 32 + resetValue: 16 + fields: + - name: DMA_OUT_CH4_INT_MAP + description: "this register used to map dma_out_ch4 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: RSA_INT_MAP + description: rsa interrupt configuration register + addressOffset: 2352 + size: 32 + resetValue: 16 + fields: + - name: RSA_INT_MAP + description: "this register used to map rsa interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: AES_INT_MAP + description: aes interrupt configuration register + addressOffset: 2356 + size: 32 + resetValue: 16 + fields: + - name: AES_INT_MAP + description: "this register used to map aes interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SHA_INT_MAP + description: sha interrupt configuration register + addressOffset: 2360 + size: 32 + resetValue: 16 + fields: + - name: SHA_INT_MAP + description: "this register used to map sha interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_0_MAP + description: cpu_intr_from_cpu_0 interrupt configuration register + addressOffset: 2364 + size: 32 + resetValue: 16 + fields: + - name: CPU_INTR_FROM_CPU_0_MAP + description: "this register used to map cpu_intr_from_cpu_0 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_1_MAP + description: cpu_intr_from_cpu_1 interrupt configuration register + addressOffset: 2368 + size: 32 + resetValue: 16 + fields: + - name: CPU_INTR_FROM_CPU_1_MAP + description: "this register used to map cpu_intr_from_cpu_1 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_2_MAP + description: cpu_intr_from_cpu_2 interrupt configuration register + addressOffset: 2372 + size: 32 + resetValue: 16 + fields: + - name: CPU_INTR_FROM_CPU_2_MAP + description: "this register used to map cpu_intr_from_cpu_2 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_3_MAP + description: cpu_intr_from_cpu_3 interrupt configuration register + addressOffset: 2376 + size: 32 + resetValue: 16 + fields: + - name: CPU_INTR_FROM_CPU_3_MAP + description: "this register used to map cpu_intr_from_cpu_3 interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: ASSIST_DEBUG_INTR_MAP + description: assist_debug interrupt configuration register + addressOffset: 2380 + size: 32 + resetValue: 16 + fields: + - name: ASSIST_DEBUG_INTR_MAP + description: "this register used to map assist_debug interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP + description: dma_pms_monitor_violatile interrupt configuration register + addressOffset: 2384 + size: 32 + resetValue: 16 + fields: + - name: DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP + description: "this register used to map dma_pms_monitor_violatile interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + description: core0_IRam0_pms_monitor_violatile interrupt configuration register + addressOffset: 2388 + size: 32 + resetValue: 16 + fields: + - name: CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + description: "this register used to map core0_IRam0_pms_monitor_violatile interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + description: core0_DRam0_pms_monitor_violatile interrupt configuration register + addressOffset: 2392 + size: 32 + resetValue: 16 + fields: + - name: CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + description: "this register used to map core0_DRam0_pms_monitor_violatile interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + description: core0_PIF_pms_monitor_violatile interrupt configuration register + addressOffset: 2396 + size: 32 + resetValue: 16 + fields: + - name: CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + description: "this register used to map core0_PIF_pms_monitor_violatile interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + description: core0_PIF_pms_monitor_violatile_size interrupt configuration register + addressOffset: 2400 + size: 32 + resetValue: 16 + fields: + - name: CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + description: "this register used to map core0_PIF_pms_monitor_violatile_size interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + description: core1_IRam0_pms_monitor_violatile interrupt configuration register + addressOffset: 2404 + size: 32 + resetValue: 16 + fields: + - name: CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + description: "this register used to map core1_IRam0_pms_monitor_violatile interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + description: core1_DRam0_pms_monitor_violatile interrupt configuration register + addressOffset: 2408 + size: 32 + resetValue: 16 + fields: + - name: CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP + description: "this register used to map core1_DRam0_pms_monitor_violatile interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + description: core1_PIF_pms_monitor_violatile interrupt configuration register + addressOffset: 2412 + size: 32 + resetValue: 16 + fields: + - name: CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP + description: "this register used to map core1_PIF_pms_monitor_violatile interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + description: core1_PIF_pms_monitor_violatile_size interrupt configuration register + addressOffset: 2416 + size: 32 + resetValue: 16 + fields: + - name: CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP + description: "this register used to map core1_PIF_pms_monitor_violatile_size interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: BACKUP_PMS_VIOLATE_INTR_MAP + description: backup_pms_monitor_violatile interrupt configuration register + addressOffset: 2420 + size: 32 + resetValue: 16 + fields: + - name: BACKUP_PMS_VIOLATE_INTR_MAP + description: "this register used to map backup_pms_monitor_violatile interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CACHE_CORE0_ACS_INT_MAP + description: cache_core0_acs interrupt configuration register + addressOffset: 2424 + size: 32 + resetValue: 16 + fields: + - name: CACHE_CORE0_ACS_INT_MAP + description: "this register used to map cache_core0_acs interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: CACHE_CORE1_ACS_INT_MAP + description: cache_core1_acs interrupt configuration register + addressOffset: 2428 + size: 32 + resetValue: 16 + fields: + - name: CACHE_CORE1_ACS_INT_MAP + description: "this register used to map cache_core1_acs interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: USB_DEVICE_INT_MAP + description: usb_device interrupt configuration register + addressOffset: 2432 + size: 32 + resetValue: 16 + fields: + - name: USB_DEVICE_INT_MAP + description: "this register used to map usb_device interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: PERI_BACKUP_INT_MAP + description: peri_backup interrupt configuration register + addressOffset: 2436 + size: 32 + resetValue: 16 + fields: + - name: PERI_BACKUP_INT_MAP + description: "this register used to map peri_backup interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: DMA_EXTMEM_REJECT_INT_MAP + description: dma_extmem_reject interrupt configuration register + addressOffset: 2440 + size: 32 + resetValue: 16 + fields: + - name: DMA_EXTMEM_REJECT_INT_MAP + description: "this register used to map dma_extmem_reject interrupt to one of core1's external interrupt" + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: APP_INTR_STATUS_0 + description: interrupt status register + addressOffset: 2444 + size: 32 + fields: + - name: INTR_STATUS_0 + description: this register store the status of the first 32 interrupt source + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APP_INTR_STATUS_1 + description: interrupt status register + addressOffset: 2448 + size: 32 + fields: + - name: INTR_STATUS_1 + description: this register store the status of the first 32 interrupt source + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APP_INTR_STATUS_2 + description: interrupt status register + addressOffset: 2452 + size: 32 + fields: + - name: INTR_STATUS_2 + description: this register store the status of the first 32 interrupt source + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: APP_INTR_STATUS_3 + description: interrupt status register + addressOffset: 2456 + size: 32 + fields: + - name: INTR_STATUS_3 + description: this register store the status of the first 32 interrupt source + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CLOCK_GATE + description: clock gate register + addressOffset: 2460 + size: 32 + resetValue: 1 + fields: + - name: REG_CLK_EN + description: this register uesd to control clock-gating interupt martrix + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: version register + addressOffset: 4092 + size: 32 + resetValue: 33628928 + fields: + - name: INTERRUPT_DATE + description: version register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: IO_MUX + description: Input/Output Multiplexer + groupName: IO_MUX + baseAddress: 1610649600 + addressBlock: + - offset: 0 + size: 204 + usage: registers + registers: + - register: + name: PIN_CTRL + description: Clock Output Configuration Register + addressOffset: 0 + size: 32 + resetValue: 2047 + fields: + - name: CLK_OUT1 + description: "If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: CLK_OUT2 + description: "If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: CLK_OUT3 + description: "If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals." + bitOffset: 8 + bitWidth: 4 + access: read-write + - register: + dim: 49 + dimIncrement: 4 + name: GPIO%s + description: IO MUX Configure Register for pad GPIO0 + addressOffset: 4 + size: 32 + resetValue: 2816 + fields: + - name: MCU_OE + description: "Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MCU_WPD + description: "Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MCU_WPU + description: "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MCU_IE + description: "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FUN_WPD + description: "Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FUN_WPU + description: "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FUN_IE + description: "Input enable of the pad. 1: input enabled; 0: input disabled." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FUN_DRV + description: "Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: MCU_SEL + description: "Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: FILTER_EN + description: "Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled." + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: IO MUX Version Control Register + addressOffset: 252 + size: 32 + resetValue: 26243424 + fields: + - name: REG_DATE + description: Version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: LCD_CAM + description: Camera/LCD Controller + groupName: LCD_CAM + baseAddress: 1610878976 + addressBlock: + - offset: 0 + size: 72 + usage: registers + interrupt: + - name: LCD_CAM + value: 24 + registers: + - register: + name: LCD_CLOCK + description: LCD clock configuration register + addressOffset: 0 + size: 32 + fields: + - name: LCD_CLKCNT_N + description: "fLCD_PCLK\n = fLCD_CLK/(LCD_CAM_LCD_CLKCNT_N + 1) when LCD_CAM_LCD_CLK_EQU_SYSCLK is 0. Note: this field must not be configured to 0." + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: LCD_CLK_EQU_SYSCLK + description: "1: fLCD_PCLK\n= fLCD_CLK. 0: fLCD_PCLK\n = fLCD_CLK/(LCD_CAM_LCD_CLKCNT_N + 1)." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: LCD_CK_IDLE_EDGE + description: "1: LCD_PCLK line is high in idle. 0: LCD_PCLK line is low in idle." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: LCD_CK_OUT_EDGE + description: "1: LCD_PCLK is high in the first half clock cycle. 0: LCD_PCLK is low in the first half clock cycle." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: LCD_CLKM_DIV_NUM + description: Integral LCD clock divider value. + bitOffset: 9 + bitWidth: 8 + access: read-write + - name: LCD_CLKM_DIV_B + description: Fractional clock divider numerator value. + bitOffset: 17 + bitWidth: 6 + access: read-write + - name: LCD_CLKM_DIV_A + description: Fractional clock divider denominator value. + bitOffset: 23 + bitWidth: 6 + access: read-write + - name: LCD_CLK_SEL + description: "Select LCD module source clock. 0: clock source is disabled. 1: XTAL_CLK. 2: PLL_D2_CLK. 3: PLL_F160M_CLK." + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: CLK_EN + description: Set this bit to force enable the clock for all configuration registers. Clock gate is not used. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CAM_CTRL + description: Camera clock configuration register + addressOffset: 4 + size: 32 + fields: + - name: CAM_STOP_EN + description: "Camera stop enable signal, 1: camera stops when GDMA Rx FIFO is full. 0: Do not stop." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CAM_VSYNC_FILTER_THRES + description: Filter threshold value for CAM_VSYNC signal. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: CAM_UPDATE + description: "1: Update camera registers. This bit is cleared by hardware. 0: Do not care." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CAM_BYTE_ORDER + description: "1: Invert data byte order, only valid in 16-bit mode. 0: Do not change." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CAM_BIT_ORDER + description: "1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in 8-bit mode, and bits[15:0] to bits[0:15] in 16-bit mode. 0: Do not change." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CAM_LINE_INT_EN + description: "1: Enable to generate LCD_CAM_CAM_HS_INT. 0: Disable." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CAM_VS_EOF_EN + description: "1: Enable CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by LCD_CAM_CAM_REC_DATA_BYTELEN." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CAM_CLKM_DIV_NUM + description: Integral camera clock divider value. + bitOffset: 9 + bitWidth: 8 + access: read-write + - name: CAM_CLKM_DIV_B + description: Fractional clock divider numerator value. + bitOffset: 17 + bitWidth: 6 + access: read-write + - name: CAM_CLKM_DIV_A + description: Fractional clock divider denominator value. + bitOffset: 23 + bitWidth: 6 + access: read-write + - name: CAM_CLK_SEL + description: "Select camera module source clock. 0: Clock source is disabled. 1: XTAL_CLK. 2: PLL_D2_CLK. 3: PLL_F160M_CLK." + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: CAM_CTRL1 + description: Camera control register + addressOffset: 8 + size: 32 + fields: + - name: CAM_REC_DATA_BYTELEN + description: "Configure camera received data byte length. When the length of received data reaches this value + 1, GDMA in_suc_eof_int is triggered." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CAM_LINE_INT_NUM + description: "Configure line number. When the number of received lines reaches this value + 1, LCD_CAM_CAM_HS_INT is triggered." + bitOffset: 16 + bitWidth: 6 + access: read-write + - name: CAM_CLK_INV + description: "1: Invert the input signal CAM_PCLK. 0: Do not invert." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: CAM_VSYNC_FILTER_EN + description: "1: Enable CAM_VSYNC filter function. 0: Bypass." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: CAM_2BYTE_EN + description: "1: The width of input data is 16 bits. 0: The width of input data is 8 bits." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: CAM_DE_INV + description: "CAM_DE invert enable signal, valid in high level." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: CAM_HSYNC_INV + description: "CAM_HSYNC invert enable signal, valid in high level." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CAM_VSYNC_INV + description: "CAM_VSYNC invert enable signal, valid in high level." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: CAM_VH_DE_MODE_EN + description: "1: Input control signals are CAM_DE and CAM_HSYNC. CAM_VSYNC is 1. 0: Input control signals are CAM_DE and CAM_VSYNC. CAM_HSYNC and CAM_DE are all 1 at the the same time." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CAM_START + description: Camera module start signal. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CAM_RESET + description: Camera module reset signal. + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: CAM_AFIFO_RESET + description: Camera Async Rx FIFO reset signal. + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: CAM_RGB_YUV + description: Camera data format conversion register + addressOffset: 12 + size: 32 + fields: + - name: CAM_CONV_8BITS_DATA_INV + description: "Swap every two 8-bit input data. 1: Enabled. 0: Disabled." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CAM_CONV_YUV2YUV_MODE + description: "In YUV-to-YUV mode, 0: data is converted to YUV422 format. 1: data is converted to YUV420 format. 2: data is converted to YUV411 format. 3: disabled. To enable YUV-to-YUV mode, LCD_CAM_CAM_CONV_TRANS_MODE must be set to 1." + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CAM_CONV_YUV_MODE + description: "In YUV-to-YUV mode and YUV-to-RGB mode, LCD_CAM_CAM_CONV_YUV_MODE decides the YUV mode of input data. 0: input data is in YUV422 format. 1: input data is in YUV420 format. 2: input data is in YUV411 format. In RGB-to-YUV mode, 0: data is converted to YUV422 format. 1: data is converted to YUV420 format. 2: data is converted to YUV411 format." + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CAM_CONV_PROTOCOL_MODE + description: "0: BT601. 1: BT709." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CAM_CONV_DATA_OUT_MODE + description: "Configure color range for output data. 0: limited color range. 1: full color range." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: CAM_CONV_DATA_IN_MODE + description: "Configure color range for input data. 0: limited color range. 1: full color range." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CAM_CONV_MODE_8BITS_ON + description: "0: 16-bit mode. 1: 8-bit mode." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CAM_CONV_TRANS_MODE + description: "0: converted to RGB format. 1: converted to YUV format." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CAM_CONV_BYPASS + description: "0: Bypass converter. 1: Enable converter." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LCD_RGB_YUV + description: LCD data format conversion register + addressOffset: 16 + size: 32 + fields: + - name: LCD_CONV_8BITS_DATA_INV + description: "Swap every two 8-bit input data. 1: Enabled. 0: Disabled." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: LCD_CONV_YUV2YUV_MODE + description: "In YUV-to-YUV mode, 0: data is converted to YUV422 format. 1: data is converted to YUV420 format. 2: data is converted to YUV411 format. 3: disabled. To enable YUV-to-YUV mode, LCD_CAM_LCD_CONV_TRANS_MODE must be set to 1." + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: LCD_CONV_YUV_MODE + description: "In YUV-to-YUV mode and YUV-to-RGB mode, LCD_CAM_LCD_CONV_YUV_MODE decides the YUV mode of input data. 0: input data is in YUV422 format. 1: input data is in YUV420 format. 2: input data is in YUV411 format. In RGB-to-YUV mode, 0: data is converted to YUV422 format. 1: data is converted to YUV420 format. 2: data is converted to YUV411 format." + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: LCD_CONV_PROTOCOL_MODE + description: "0: BT601. 1: BT709." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LCD_CONV_DATA_OUT_MODE + description: "Configure color range for output data. 0: limited color range. 1: full color range." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LCD_CONV_DATA_IN_MODE + description: "Configure color range for input data. 0: limited color range. 1: full color range." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LCD_CONV_MODE_8BITS_ON + description: "0: 16-bit mode. 1: 8-bit mode." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LCD_CONV_TRANS_MODE + description: "0: converted to RGB format. 1: converted to YUV format." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LCD_CONV_BYPASS + description: "0: Bypass converter. 1: Enable converter." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LCD_USER + description: LCD user configuration register + addressOffset: 20 + size: 32 + fields: + - name: LCD_DOUT_CYCLELEN + description: Configure the cycles for DOUT phase of LCD module. The cycles = this value + 1. + bitOffset: 0 + bitWidth: 13 + access: read-write + - name: LCD_ALWAYS_OUT_EN + description: "LCD continues outputting data when LCD is in DOUT phase, till LCD_CAM_LCD_START is cleared or LCD_CAM_LCD_RESET is set." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: LCD_8BITS_ORDER + description: "1: Swap every two data bytes, valid in 8-bit mode. 0: Do not swap." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: LCD_UPDATE + description: "1: Update LCD registers. This bit is cleared by hardware. 0: Do not care." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: LCD_BIT_ORDER + description: "1: Change data bit order. Change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in 8-bit mode, and bits[15:0] to bits[0:15] in 16-bit mode. 0: Do not change." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: LCD_BYTE_ORDER + description: "1: Invert data byte order, only valid in 16-bit mode. 0: Do not invert." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: LCD_2BYTE_EN + description: "1: The width of output LCD data is 16 bits. 0: The width of output LCD data is 8 bits." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: LCD_DOUT + description: "1: Be able to send data out in LCD sequence when LCD starts. 0: Disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: LCD_DUMMY + description: "1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LCD_CMD + description: "1: Be able to send command in LCD sequence when LCD starts. 0: Disable." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LCD_START + description: "LCD starts sending data enable signal, valid in high level." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LCD_RESET + description: Reset LCD module. + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: LCD_DUMMY_CYCLELEN + description: Configure DUMMY cycles. DUMMY cycles = this value + 1. + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: LCD_CMD_2_CYCLE_EN + description: "The cycle length of command phase. 1: 2 cycles. 0: 1 cycle." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LCD_MISC + description: LCD MISC configuration register + addressOffset: 24 + size: 32 + resetValue: 34 + fields: + - name: LCD_AFIFO_THRESHOLD_NUM + description: Set the threshold for Async Tx FIFO full event. + bitOffset: 1 + bitWidth: 5 + access: read-write + - name: LCD_VFK_CYCLELEN + description: Configure the setup cycles in LCD non-RGB mode. Setup cycles expected = this value + 1. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: LCD_VBK_CYCLELEN + description: "Configure the hold time cycles in LCD non-RGB mode. Hold cycles expected = this value + 1. %Configure the cycles for vertical back blank region in LCD RGB mode, the cycles = this value + 1. Or configure the hold time cycles in LCD non-RGB mode, the cycles = this value + 1." + bitOffset: 12 + bitWidth: 13 + access: read-write + - name: LCD_NEXT_FRAME_EN + description: "1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LCD_BK_EN + description: "1: Enable blank region when LCD sends data out. 0: No blank region." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LCD_AFIFO_RESET + description: Async Tx FIFO reset signal. + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: LCD_CD_DATA_SET + description: "1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in DOUT phase. 0: LCD_CD = LCD_CAM_LCD_CD_IDLE_EDGE." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: LCD_CD_DUMMY_SET + description: "1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in DUMMY phase. 0: LCD_CD = LCD_CAM_LCD_CD_IDLE_EDGE." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: LCD_CD_CMD_SET + description: "1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in CMD phase. 0: LCD_CD = LCD_CAM_LCD_CD_IDLE_EDGE." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: LCD_CD_IDLE_EDGE + description: The default value of LCD_CD. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LCD_CTRL + description: LCD signal configuration register + addressOffset: 28 + size: 32 + fields: + - name: LCD_HB_FRONT + description: It is the horizontal blank front porch of a frame. + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: LCD_VA_HEIGHT + description: It is the vertical active height of a frame. + bitOffset: 11 + bitWidth: 10 + access: read-write + - name: LCD_VT_HEIGHT + description: It is the vertical total height of a frame. + bitOffset: 21 + bitWidth: 10 + access: read-write + - name: LCD_RGB_MODE_EN + description: "1: Enable RGB mode, and input VSYNC, HSYNC, and DE signals. 0: Disable." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: LCD_CTRL1 + description: LCD signal configuration register 1 + addressOffset: 32 + size: 32 + fields: + - name: LCD_VB_FRONT + description: It is the vertical blank front porch of a frame. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: LCD_HA_WIDTH + description: It is the horizontal active width of a frame. + bitOffset: 8 + bitWidth: 12 + access: read-write + - name: LCD_HT_WIDTH + description: It is the horizontal total width of a frame. + bitOffset: 20 + bitWidth: 12 + access: read-write + - register: + name: LCD_CTRL2 + description: LCD signal configuration register 2 + addressOffset: 36 + size: 32 + fields: + - name: LCD_VSYNC_WIDTH + description: It is the width of LCD_VSYNC active pulse in a line. + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: LCD_VSYNC_IDLE_POL + description: It is the idle value of LCD_VSYNC. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: LCD_DE_IDLE_POL + description: It is the idle value of LCD_DE. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: LCD_HS_BLANK_EN + description: "1: The pulse of LCD_HSYNC is out in vertical blanking lines in RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: LCD_HSYNC_WIDTH + description: It is the width of LCD_HSYNC active pulse in a line. + bitOffset: 16 + bitWidth: 7 + access: read-write + - name: LCD_HSYNC_IDLE_POL + description: It is the idle value of LCD_HSYNC. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: LCD_HSYNC_POSITION + description: It is the position of LCD_HSYNC active pulse in a line. + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: LCD_CMD_VAL + description: LCD command value configuration register + addressOffset: 40 + size: 32 + fields: + - name: LCD_CMD_VALUE + description: The LCD write command value. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LCD_DLY_MODE + description: LCD signal delay configuration register + addressOffset: 48 + size: 32 + fields: + - name: LCD_CD_MODE + description: "The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: LCD_DE_MODE + description: "The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: LCD_HSYNC_MODE + description: "The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: LCD_VSYNC_MODE + description: "The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delay by the falling edge of LCD_CLK." + bitOffset: 6 + bitWidth: 2 + access: read-write + - register: + name: LCD_DATA_DOUT_MODE + description: LCD data delay configuration register + addressOffset: 56 + size: 32 + fields: + - name: DOUT0_MODE + description: "The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DOUT1_MODE + description: "The output data bit 1 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DOUT2_MODE + description: "The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DOUT3_MODE + description: "The output data bit 3 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DOUT4_MODE + description: "The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK." + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: DOUT5_MODE + description: "The output data bit 5 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DOUT6_MODE + description: "The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK." + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DOUT7_MODE + description: "The output data bit 7 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK." + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DOUT8_MODE + description: "The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DOUT9_MODE + description: "The output data bit 9 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK." + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DOUT10_MODE + description: "The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DOUT11_MODE + description: "The output data bit 11 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK." + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: DOUT12_MODE + description: "The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK." + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: DOUT13_MODE + description: "The output data bit 13 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK." + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: DOUT14_MODE + description: "The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK." + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: DOUT15_MODE + description: "The output data bit 15 is delayed by module clock LCD_CLK. 0: output without delay. 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK." + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: LC_DMA_INT_ENA + description: LCD_CAM GDMA interrupt enable register + addressOffset: 100 + size: 32 + fields: + - name: LCD_VSYNC_INT_ENA + description: The enable bit for LCD_CAM_LCD_VSYNC_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LCD_TRANS_DONE_INT_ENA + description: The enable bit for LCD_CAM_LCD_TRANS_DONE_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CAM_VSYNC_INT_ENA + description: The enable bit for LCD_CAM_CAM_VSYNC_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CAM_HS_INT_ENA + description: The enable bit for LCD_CAM_CAM_HS_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: LC_DMA_INT_RAW + description: LCD_CAM GDMA raw interrupt status register + addressOffset: 104 + size: 32 + fields: + - name: LCD_VSYNC_INT_RAW + description: The raw bit for LCD_CAM_LCD_VSYNC_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: LCD_TRANS_DONE_INT_RAW + description: The raw bit for LCD_CAM_LCD_TRANS_DONE_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CAM_VSYNC_INT_RAW + description: The raw bit for LCD_CAM_CAM_VSYNC_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CAM_HS_INT_RAW + description: The raw bit for LCD_CAM_CAM_HS_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: LC_DMA_INT_ST + description: LCD_CAM GDMA masked interrupt status register + addressOffset: 108 + size: 32 + fields: + - name: LCD_VSYNC_INT_ST + description: The status bit for LCD_CAM_LCD_VSYNC_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: LCD_TRANS_DONE_INT_ST + description: The status bit for LCD_CAM_LCD_TRANS_DONE_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CAM_VSYNC_INT_ST + description: The status bit for LCD_CAM_CAM_VSYNC_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CAM_HS_INT_ST + description: The status bit for LCD_CAM_CAM_HS_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: LC_DMA_INT_CLR + description: LCD_CAM GDMA interrupt clear register + addressOffset: 112 + size: 32 + fields: + - name: LCD_VSYNC_INT_CLR + description: The clear bit for LCD_CAM_LCD_VSYNC_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: LCD_TRANS_DONE_INT_CLR + description: The clear bit for LCD_CAM_LCD_TRANS_DONE_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CAM_VSYNC_INT_CLR + description: The clear bit for LCD_CAM_CAM_VSYNC_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CAM_HS_INT_CLR + description: The clear bit for LCD_CAM_CAM_HS_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: LC_REG_DATE + description: Version control register + addressOffset: 252 + size: 32 + resetValue: 33566752 + fields: + - name: LC_DATE + description: Version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: LEDC + description: LED Control PWM (Pulse Width Modulation) + groupName: LEDC + baseAddress: 1610715136 + addressBlock: + - offset: 0 + size: 216 + usage: registers + interrupt: + - name: LEDC + value: 35 + - name: TIMER1 + value: 48 + - name: TIMER2 + value: 49 + registers: + - register: + dim: 8 + dimIncrement: 20 + name: CH%s_CONF0 + description: Configuration register 0 for channel %s + addressOffset: 0 + size: 32 + fields: + - name: TIMER_SEL + description: "This field is used to select one of timers for channel %s.\n\n0: select timer0\n\n1: select timer1\n\n2: select timer2\n\n3: select timer3" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SIG_OUT_EN + description: Set this bit to enable signal output on channel %s. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: IDLE_LV + description: This bit is used to control the output value when channel %s is inactive (when LEDC_SIG_OUT_EN_CH%s is 0). + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PARA_UP + description: "This bit is used to update LEDC_HPOINT_CH%s, LEDC_DUTY_START_CH%s, LEDC_SIG_OUT_EN_CH%s, LEDC_TIMER_SEL_CH%s, LEDC_DUTY_NUM_CH%s, LEDC_DUTY_CYCLE_CH%s, LEDC_DUTY_SCALE_CH%s, LEDC_DUTY_INC_CH%s, and LEDC_OVF_CNT_EN_CH%s fields for channel %s, and will be automatically cleared by hardware." + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: OVF_NUM + description: "This register is used to configure the maximum times of overflow minus 1.\n\nThe LEDC_OVF_CNT_CH%s_INT interrupt will be triggered when channel %s overflows for (LEDC_OVF_NUM_CH%s + 1) times." + bitOffset: 5 + bitWidth: 10 + access: read-write + - name: OVF_CNT_EN + description: This bit is used to enable the ovf_cnt of channel %s. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: OVF_CNT_RESET + description: Set this bit to reset the ovf_cnt of channel %s. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: OVF_CNT_RESET_ST + description: This is the status bit of LEDC_OVF_CNT_RESET_CH%s. + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + dim: 8 + dimIncrement: 20 + name: CH%s_HPOINT + description: High point register for channel %s + addressOffset: 4 + size: 32 + fields: + - name: HPOINT + description: The output value changes to high when the selected timers has reached the value specified by this register. + bitOffset: 0 + bitWidth: 14 + access: read-write + - register: + dim: 8 + dimIncrement: 20 + name: CH%s_DUTY + description: Initial duty cycle for channel %s + addressOffset: 8 + size: 32 + fields: + - name: DUTY + description: "This register is used to change the output duty by controlling the Lpoint.\n\nThe output value turns to low when the selected timers has reached the Lpoint." + bitOffset: 0 + bitWidth: 19 + access: read-write + - register: + dim: 8 + dimIncrement: 20 + name: CH%s_CONF1 + description: Configuration register 1 for channel %s + addressOffset: 12 + size: 32 + resetValue: 1073741824 + fields: + - name: DUTY_SCALE + description: This register is used to configure the changing step scale of duty on channel %s. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: DUTY_CYCLE + description: The duty will change every LEDC_DUTY_CYCLE_CH%s on channel %s. + bitOffset: 10 + bitWidth: 10 + access: read-write + - name: DUTY_NUM + description: This register is used to control the number of times the duty cycle will be changed. + bitOffset: 20 + bitWidth: 10 + access: read-write + - name: DUTY_INC + description: "This register is used to increase or decrease the duty of output signal on channel %s. 1: Increase; 0: Decrease." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DUTY_START + description: Other configured fields in LEDC_CH%s_CONF1_REG will start to take effect when this bit is set to 1. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + dim: 8 + dimIncrement: 20 + name: CH%s_DUTY_R + description: Current duty cycle for channel %s + addressOffset: 16 + size: 32 + fields: + - name: DUTY_R + description: This register stores the current duty of output signal on channel %s. + bitOffset: 0 + bitWidth: 19 + access: read-only + - register: + dim: 4 + dimIncrement: 8 + name: TIMER%s_CONF + description: Timer %s configuration + addressOffset: 160 + size: 32 + resetValue: 8388608 + fields: + - name: DUTY_RES + description: This register is used to control the range of the counter in timer %s. + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: CLK_DIV + description: "This register is used to configure the divisor for the divider in timer %s.\n\nThe least significant eight bits represent the fractional part." + bitOffset: 4 + bitWidth: 18 + access: read-write + - name: PAUSE + description: This bit is used to suspend the counter in timer %s. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RST + description: This bit is used to reset timer %s. The counter will show 0 after reset. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TICK_SEL + description: "This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate.\n\n1'h0: SLOW_CLK 1'h1: REF_TICK" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PARA_UP + description: Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES. + bitOffset: 25 + bitWidth: 1 + access: write-only + - register: + dim: 4 + dimIncrement: 8 + name: TIMER%s_VALUE + description: Timer %s current counter value + addressOffset: 164 + size: 32 + fields: + - name: CNT + description: This register stores the current counter value of timer %s. + bitOffset: 0 + bitWidth: 14 + access: read-only + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 192 + size: 32 + fields: + - name: TIMER0_OVF_INT_RAW + description: Triggered when the timer0 has reached its maximum counter value. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMER1_OVF_INT_RAW + description: Triggered when the timer1 has reached its maximum counter value. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER2_OVF_INT_RAW + description: Triggered when the timer2 has reached its maximum counter value. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TIMER3_OVF_INT_RAW + description: Triggered when the timer3 has reached its maximum counter value. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH0_INT_RAW + description: Interrupt raw bit for channel 0. Triggered when the gradual change of duty has finished. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH1_INT_RAW + description: Interrupt raw bit for channel 1. Triggered when the gradual change of duty has finished. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH2_INT_RAW + description: Interrupt raw bit for channel 2. Triggered when the gradual change of duty has finished. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH3_INT_RAW + description: Interrupt raw bit for channel 3. Triggered when the gradual change of duty has finished. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH4_INT_RAW + description: Interrupt raw bit for channel 4. Triggered when the gradual change of duty has finished. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH5_INT_RAW + description: Interrupt raw bit for channel 5. Triggered when the gradual change of duty has finished. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH6_INT_RAW + description: Interrupt raw bit for channel 6. Triggered when the gradual change of duty has finished. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH7_INT_RAW + description: Interrupt raw bit for channel 7. Triggered when the gradual change of duty has finished. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH0_INT_RAW + description: Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH0. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH1_INT_RAW + description: Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH1. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH2_INT_RAW + description: Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH2. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH3_INT_RAW + description: Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH3. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH4_INT_RAW + description: Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH4. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH5_INT_RAW + description: Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH5. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH6_INT_RAW + description: Interrupt raw bit for channel 6. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH6. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH7_INT_RAW + description: Interrupt raw bit for channel 7. Triggered when the ovf_cnt has reached the value specified by LEDC_OVF_NUM_CH7. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 196 + size: 32 + fields: + - name: TIMER0_OVF_INT_ST + description: This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TIMER1_OVF_INT_ST + description: This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TIMER2_OVF_INT_ST + description: This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TIMER3_OVF_INT_ST + description: This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH0_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt when LEDC_DUTY_CHNG_END_CH0_INT_ENAIS set to 1. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH1_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt when LEDC_DUTY_CHNG_END_CH1_INT_ENAIS set to 1. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH2_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt when LEDC_DUTY_CHNG_END_CH2_INT_ENAIS set to 1. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH3_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt when LEDC_DUTY_CHNG_END_CH3_INT_ENAIS set to 1. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH4_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt when LEDC_DUTY_CHNG_END_CH4_INT_ENAIS set to 1. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH5_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt when LEDC_DUTY_CHNG_END_CH5_INT_ENAIS set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH6_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH6_INT interrupt when LEDC_DUTY_CHNG_END_CH6_INT_ENAIS set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: DUTY_CHNG_END_CH7_INT_ST + description: This is the masked interrupt status bit for the LEDC_DUTY_CHNG_END_CH7_INT interrupt when LEDC_DUTY_CHNG_END_CH7_INT_ENAIS set to 1. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH0_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH1_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH2_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH3_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH4_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH5_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH6_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH6_INT interrupt when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: OVF_CNT_CH7_INT_ST + description: This is the masked interrupt status bit for the LEDC_OVF_CNT_CH7_INT interrupt when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. + bitOffset: 19 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 200 + size: 32 + fields: + - name: TIMER0_OVF_INT_ENA + description: The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMER1_OVF_INT_ENA + description: The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER2_OVF_INT_ENA + description: The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TIMER3_OVF_INT_ENA + description: The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH0_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH1_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH2_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH3_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH4_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH5_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH6_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH6_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DUTY_CHNG_END_CH7_INT_ENA + description: The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH7_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH0_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH1_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH2_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH3_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH4_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH5_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH6_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH6_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: OVF_CNT_CH7_INT_ENA + description: The interrupt enable bit for the LEDC_OVF_CNT_CH7_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 204 + size: 32 + fields: + - name: TIMER0_OVF_INT_CLR + description: Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TIMER1_OVF_INT_CLR + description: Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TIMER2_OVF_INT_CLR + description: Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TIMER3_OVF_INT_CLR + description: Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH0_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH1_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH2_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH3_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH4_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH5_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH6_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH6_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: DUTY_CHNG_END_CH7_INT_CLR + description: Set this bit to clear the LEDC_DUTY_CHNG_END_CH7_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH0_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH1_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH2_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH3_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH4_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH5_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH6_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH6_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: OVF_CNT_CH7_INT_CLR + description: Set this bit to clear the LEDC_OVF_CNT_CH7_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - register: + name: CONF + description: Global ledc configuration register + addressOffset: 208 + size: 32 + fields: + - name: APB_CLK_SEL + description: "This bit is used to select clock source for the 4 timers .\n\n2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CLK_EN + description: "This bit is used to control clock.\n\n1'b1: Force clock on for register. 1'h0: Support clock only when application writes registers." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 252 + size: 32 + resetValue: 419693056 + fields: + - name: DATE + description: This is the version control register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: PCNT + description: Pulse Count Controller + groupName: PCNT + baseAddress: 1610706944 + addressBlock: + - offset: 0 + size: 104 + usage: registers + interrupt: + - name: PCNT + value: 41 + registers: + - register: + dim: 4 + dimIncrement: 12 + name: U%s_CONF0 + description: Configuration register 0 for unit %s + addressOffset: 0 + size: 32 + resetValue: 15376 + fields: + - name: FILTER_THRES + description: "This sets the maximum threshold, in APB_CLK cycles, for the filter.\n\nAny pulses with width less than this will be ignored when the filter is enabled." + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: FILTER_EN + description: "This is the enable bit for unit %s's input filter." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: THR_ZERO_EN + description: "This is the enable bit for unit %s's zero comparator." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: THR_H_LIM_EN + description: "This is the enable bit for unit %s's thr_h_lim comparator." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: THR_L_LIM_EN + description: "This is the enable bit for unit %s's thr_l_lim comparator." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: THR_THRES0_EN + description: "This is the enable bit for unit %s's thres0 comparator." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: THR_THRES1_EN + description: "This is the enable bit for unit %s's thres1 comparator." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CH0_NEG_MODE + description: "This register sets the behavior when the signal input of channel 0 detects a negative edge.\n\n1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter" + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CH0_POS_MODE + description: "This register sets the behavior when the signal input of channel 0 detects a positive edge.\n\n1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter" + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: CH0_HCTRL_MODE + description: "This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high.\n\n0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification" + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: CH0_LCTRL_MODE + description: "This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low.\n\n0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification" + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CH1_NEG_MODE + description: "This register sets the behavior when the signal input of channel 1 detects a negative edge.\n\n1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter" + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CH1_POS_MODE + description: "This register sets the behavior when the signal input of channel 1 detects a positive edge.\n\n1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter" + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CH1_HCTRL_MODE + description: "This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is high.\n\n0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification" + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: CH1_LCTRL_MODE + description: "This register configures how the CH%s_POS_MODE/CH%s_NEG_MODE settings will be modified when the control signal is low.\n\n0: No modification;1: Invert behavior (increase -> decrease, decrease -> increase);2, 3: Inhibit counter modification" + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + dim: 4 + dimIncrement: 12 + name: U%s_CONF1 + description: Configuration register 1 for unit %s + addressOffset: 4 + size: 32 + fields: + - name: CNT_THRES0 + description: This register is used to configure the thres0 value for unit %s. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CNT_THRES1 + description: This register is used to configure the thres1 value for unit %s. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + dim: 4 + dimIncrement: 12 + name: U%s_CONF2 + description: Configuration register 2 for unit %s + addressOffset: 8 + size: 32 + fields: + - name: CNT_H_LIM + description: This register is used to configure the thr_h_lim value for unit %s. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CNT_L_LIM + description: This register is used to configure the thr_l_lim value for unit %s. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: U%s_CNT + description: Counter value for unit %s + addressOffset: 48 + size: 32 + fields: + - name: CNT + description: This register stores the current pulse count value for unit %s. + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: INT_RAW + description: Interrupt raw status register + addressOffset: 64 + size: 32 + fields: + - name: CNT_THR_EVENT_U0 + description: The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U1 + description: The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U2 + description: The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U3 + description: The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: Interrupt status register + addressOffset: 68 + size: 32 + fields: + - name: CNT_THR_EVENT_U0 + description: The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U1 + description: The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U2 + description: The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CNT_THR_EVENT_U3 + description: The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable register + addressOffset: 72 + size: 32 + fields: + - name: CNT_THR_EVENT_U0 + description: The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U1 + description: The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U2 + description: The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CNT_THR_EVENT_U3 + description: The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear register + addressOffset: 76 + size: 32 + fields: + - name: CNT_THR_EVENT_U0 + description: Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: CNT_THR_EVENT_U1 + description: Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: CNT_THR_EVENT_U2 + description: Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CNT_THR_EVENT_U3 + description: Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + dim: 4 + dimIncrement: 4 + name: U%s_STATUS + description: PNCT UNIT%s status register + addressOffset: 80 + size: 32 + fields: + - name: ZERO_MODE + description: "The pulse counter status of PCNT_U%s corresponding to 0. 0: pulse counter decreases from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter is negative. 3: pulse counter is positive." + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: THRES1 + description: "The latched value of thres1 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0: others" + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: THRES0 + description: "The latched value of thres0 event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0: others" + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: L_LIM + description: "The latched value of low limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_l_lim and low limit event is valid. 0: others" + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: H_LIM + description: "The latched value of high limit event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to thr_h_lim and high limit event is valid. 0: others" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ZERO + description: "The latched value of zero threshold event of PCNT_U%s when threshold event interrupt is valid. 1: the current pulse counter equals to 0 and zero threshold event is valid. 0: others" + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: CTRL + description: Control register for all counters + addressOffset: 96 + size: 32 + resetValue: 1 + fields: + - name: CNT_RST_U0 + description: "Set this bit to clear unit 0's counter." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U0 + description: "Set this bit to freeze unit 0's counter." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CNT_RST_U1 + description: "Set this bit to clear unit 1's counter." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U1 + description: "Set this bit to freeze unit 1's counter." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CNT_RST_U2 + description: "Set this bit to clear unit 2's counter." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U2 + description: "Set this bit to freeze unit 2's counter." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CNT_RST_U3 + description: "Set this bit to clear unit 3's counter." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CNT_PAUSE_U3 + description: "Set this bit to freeze unit 3's counter." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "The registers clock gate enable signal of PCNT module. 1: the registers can be read and written by application. 0: the registers can not be read or written by application" + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: PCNT version control register + addressOffset: 252 + size: 32 + resetValue: 419898881 + fields: + - name: DATE + description: This is the PCNT version control register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: PERI_BACKUP + description: PERI_BACKUP Peripheral + groupName: PERI_BACKUP + baseAddress: 1610784768 + addressBlock: + - offset: 0 + size: 48 + usage: registers + interrupt: + - name: PERI_BACKUP + value: 97 + registers: + - register: + name: CONFIG + description: x + addressOffset: 0 + size: 32 + resetValue: 25728 + fields: + - name: FLOW_ERR + description: x + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: ADDR_MAP_MODE + description: x + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: BURST_LIMIT + description: x + bitOffset: 4 + bitWidth: 5 + access: read-write + - name: TOUT_THRES + description: x + bitOffset: 9 + bitWidth: 10 + access: read-write + - name: SIZE + description: x + bitOffset: 19 + bitWidth: 10 + access: read-write + - name: START + description: x + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: TO_MEM + description: x + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: ENA + description: x + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: APB_ADDR + description: x + addressOffset: 4 + size: 32 + fields: + - name: APB_START_ADDR + description: x + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: MEM_ADDR + description: x + addressOffset: 8 + size: 32 + fields: + - name: MEM_START_ADDR + description: x + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_MAP0 + description: x + addressOffset: 12 + size: 32 + fields: + - name: MAP0 + description: x + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_MAP1 + description: x + addressOffset: 16 + size: 32 + fields: + - name: MAP1 + description: x + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_MAP2 + description: x + addressOffset: 20 + size: 32 + fields: + - name: MAP2 + description: x + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_MAP3 + description: x + addressOffset: 24 + size: 32 + fields: + - name: MAP3 + description: x + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: INT_RAW + description: x + addressOffset: 28 + size: 32 + fields: + - name: DONE_INT_RAW + description: x + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ERR_INT_RAW + description: x + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: x + addressOffset: 32 + size: 32 + fields: + - name: DONE_INT_ST + description: x + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ERR_INT_ST + description: x + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: x + addressOffset: 36 + size: 32 + fields: + - name: DONE_INT_ENA + description: x + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ERR_INT_ENA + description: x + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: x + addressOffset: 40 + size: 32 + fields: + - name: DONE_INT_CLR + description: x + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ERR_INT_CLR + description: x + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: DATE + description: x + addressOffset: 252 + size: 32 + resetValue: 33628928 + fields: + - name: DATE + description: x + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: CLK_EN + description: register file clk gating + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: MCPWM0 + description: Motor Control Pulse-Width Modulation 0 + groupName: PWM + baseAddress: 1610735616 + addressBlock: + - offset: 0 + size: 296 + usage: registers + interrupt: + - name: MCPWM0 + value: 31 + registers: + - register: + name: CLK_CFG + description: PWM clock prescaler register. + addressOffset: 0 + size: 32 + fields: + - name: CLK_PRESCALE + description: Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1) + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: TIMER0_CFG0 + description: PWM timer0 period and update method configuration register. + addressOffset: 4 + size: 32 + resetValue: 65280 + fields: + - name: TIMER0_PRESCALE + description: period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1) + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TIMER0_PERIOD + description: period shadow register of PWM timer0 + bitOffset: 8 + bitWidth: 16 + access: read-write + - name: TIMER0_PERIOD_UPMETHOD + description: "Update method for active register of PWM timer0 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event" + bitOffset: 24 + bitWidth: 2 + access: read-write + - register: + name: TIMER0_CFG1 + description: PWM timer0 working mode and start/stop control configuration register. + addressOffset: 8 + size: 32 + fields: + - name: TIMER0_START + description: "PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at TEZ, 1: if timer0 starts, then stops at TEP, 2: PWM timer0 starts and runs on, 3: timer0 starts and stops at the next TEZ, 4: timer0 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: TIMER0_MOD + description: "PWM timer0 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode" + bitOffset: 3 + bitWidth: 2 + access: read-write + - register: + name: TIMER0_SYNC + description: PWM timer0 sync function configuration register. + addressOffset: 12 + size: 32 + fields: + - name: TIMER0_SYNCI_EN + description: "When set, timer reloading with phase on sync input event is enabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SW + description: Toggling this bit will trigger a software sync. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER0_SYNCO_SEL + description: "PWM timer0 sync_out selection, 0: synci, 1: TEZ, 2: TEP, otherwise:sync out is software sync" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: TIMER0_PHASE + description: phase for timer reload on sync event + bitOffset: 4 + bitWidth: 16 + access: read-write + - name: TIMER0_PHASE_DIRECTION + description: "Configure the PWM timer0's direction when timer0 mode is up-down mode. 0: increase; 1: decrease." + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: TIMER0_STATUS + description: PWM timer0 status register. + addressOffset: 16 + size: 32 + fields: + - name: TIMER0_VALUE + description: current PWM timer0 counter value + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: TIMER0_DIRECTION + description: "current PWM timer0 counter direction, 0: increment 1: decrement" + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: TIMER1_CFG0 + description: PWM timer1 period and update method configuration register. + addressOffset: 20 + size: 32 + resetValue: 65280 + fields: + - name: TIMER1_PRESCALE + description: period of PT0_clk = Period of PWM_clk * (PWM_timer1_PRESCALE + 1) + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TIMER1_PERIOD + description: period shadow register of PWM timer1 + bitOffset: 8 + bitWidth: 16 + access: read-write + - name: TIMER1_PERIOD_UPMETHOD + description: "Update method for active register of PWM timer1 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event" + bitOffset: 24 + bitWidth: 2 + access: read-write + - register: + name: TIMER1_CFG1 + description: PWM timer1 working mode and start/stop control configuration register. + addressOffset: 24 + size: 32 + fields: + - name: TIMER1_START + description: "PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at TEZ, 1: if timer1 starts, then stops at TEP, 2: PWM timer1 starts and runs on, 3: timer1 starts and stops at the next TEZ, 4: timer1 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: TIMER1_MOD + description: "PWM timer1 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode" + bitOffset: 3 + bitWidth: 2 + access: read-write + - register: + name: TIMER1_SYNC + description: PWM timer1 sync function configuration register. + addressOffset: 28 + size: 32 + fields: + - name: TIMER1_SYNCI_EN + description: "When set, timer reloading with phase on sync input event is enabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SW + description: Toggling this bit will trigger a software sync. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER1_SYNCO_SEL + description: "PWM timer1 sync_out selection, 0: synci, 1: TEZ, 2: TEP, otherwise:sync out is software sync" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: TIMER1_PHASE + description: phase for timer reload on sync event + bitOffset: 4 + bitWidth: 16 + access: read-write + - name: TIMER1_PHASE_DIRECTION + description: "Configure the PWM timer1's direction when timer1 mode is up-down mode. 0: increase; 1: decrease." + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: TIMER1_STATUS + description: PWM timer1 status register. + addressOffset: 32 + size: 32 + fields: + - name: TIMER1_VALUE + description: current PWM timer1 counter value + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: TIMER1_DIRECTION + description: "current PWM timer1 counter direction, 0: increment 1: decrement" + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: TIMER2_CFG0 + description: PWM timer2 period and update method configuration register. + addressOffset: 36 + size: 32 + resetValue: 65280 + fields: + - name: TIMER2_PRESCALE + description: period of PT0_clk = Period of PWM_clk * (PWM_timer2_PRESCALE + 1) + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TIMER2_PERIOD + description: period shadow register of PWM timer2 + bitOffset: 8 + bitWidth: 16 + access: read-write + - name: TIMER2_PERIOD_UPMETHOD + description: "Update method for active register of PWM timer2 period, 0: immediate, 1: TEZ, 2: sync, 3: TEZ | sync. TEZ here and below means timer equal zero event" + bitOffset: 24 + bitWidth: 2 + access: read-write + - register: + name: TIMER2_CFG1 + description: PWM timer2 working mode and start/stop control configuration register. + addressOffset: 40 + size: 32 + fields: + - name: TIMER2_START + description: "PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at TEZ, 1: if timer2 starts, then stops at TEP, 2: PWM timer2 starts and runs on, 3: timer2 starts and stops at the next TEZ, 4: timer2 starts and stops at the next TEP. TEP here and below means the event that happens when the timer equals to period" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: TIMER2_MOD + description: "PWM timer2 working mode, 0: freeze, 1: increase mode, 2: decrease mode, 3: up-down mode" + bitOffset: 3 + bitWidth: 2 + access: read-write + - register: + name: TIMER2_SYNC + description: PWM timer2 sync function configuration register. + addressOffset: 44 + size: 32 + fields: + - name: TIMER2_SYNCI_EN + description: "When set, timer reloading with phase on sync input event is enabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SW + description: Toggling this bit will trigger a software sync. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER2_SYNCO_SEL + description: "PWM timer2 sync_out selection, 0: synci, 1: TEZ, 2: TEP, otherwise:sync out is software sync" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: TIMER2_PHASE + description: phase for timer reload on sync event + bitOffset: 4 + bitWidth: 16 + access: read-write + - name: TIMER2_PHASE_DIRECTION + description: "Configure the PWM timer2's direction when timer2 mode is up-down mode. 0: increase; 1: decrease." + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: TIMER2_STATUS + description: PWM timer2 status register. + addressOffset: 48 + size: 32 + fields: + - name: TIMER2_VALUE + description: current PWM timer2 counter value + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: TIMER2_DIRECTION + description: "current PWM timer2 counter direction, 0: increment 1: decrement" + bitOffset: 16 + bitWidth: 1 + access: read-only + - register: + name: TIMER_SYNCI_CFG + description: Synchronization input selection for three PWM timers. + addressOffset: 52 + size: 32 + fields: + - name: TIMER0_SYNCISEL + description: "select sync input for PWM timer0, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: TIMER1_SYNCISEL + description: "select sync input for PWM timer1, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected" + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: TIMER2_SYNCISEL + description: "select sync input for PWM timer2, 1: PWM timer0 sync_out, 2: PWM timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: EXTERNAL_SYNCI0_INVERT + description: invert SYNC0 from GPIO matrix + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: EXTERNAL_SYNCI1_INVERT + description: invert SYNC1 from GPIO matrix + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: EXTERNAL_SYNCI2_INVERT + description: invert SYNC2 from GPIO matrix + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: OPERATOR_TIMERSEL + description: Select specific timer for PWM operators. + addressOffset: 56 + size: 32 + fields: + - name: OPERATOR0_TIMERSEL + description: "Select which PWM timer's is the timing reference for PWM operator0, 0: timer0, 1: timer1, 2: timer2" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: OPERATOR1_TIMERSEL + description: "Select which PWM timer's is the timing reference for PWM operator1, 0: timer0, 1: timer1, 2: timer2" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: OPERATOR2_TIMERSEL + description: "Select which PWM timer's is the timing reference for PWM operator2, 0: timer0, 1: timer1, 2: timer2" + bitOffset: 4 + bitWidth: 2 + access: read-write + - register: + name: CMPR0_CFG + description: Transfer status and update method for time stamp registers A and B + addressOffset: 60 + size: 32 + fields: + - name: CMPR0_A_UPMETHOD + description: "Update method for PWM generator 0 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: CMPR0_B_UPMETHOD + description: "Update method for PWM generator 0 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: CMPR0_A_SHDW_FULL + description: "Set and reset by hardware. If set, PWM generator 0 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CMPR0_B_SHDW_FULL + description: "Set and reset by hardware. If set, PWM generator 0 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value" + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: CMPR0_VALUE0 + description: Shadow register for register A. + addressOffset: 64 + size: 32 + fields: + - name: CMPR0_A + description: "PWM generator 0 time stamp A's shadow register" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: CMPR0_VALUE1 + description: Shadow register for register B. + addressOffset: 68 + size: 32 + fields: + - name: CMPR0_B + description: "PWM generator 0 time stamp B's shadow register" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: GEN0_CFG0 + description: Fault event T0 and T1 handling + addressOffset: 72 + size: 32 + fields: + - name: GEN0_CFG_UPMETHOD + description: "Update method for PWM generator 0's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:" + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: GEN0_T0_SEL + description: "Source selection for PWM generator 0 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none" + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: GEN0_T1_SEL + description: "Source selection for PWM generator 0 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none" + bitOffset: 7 + bitWidth: 3 + access: read-write + - register: + name: GEN0_FORCE + description: Permissives to force PWM0A and PWM0B outputs by software + addressOffset: 76 + size: 32 + resetValue: 32 + fields: + - name: GEN0_CNTUFORCE_UPMETHOD + description: "Updating method for continuous software force of PWM generator0. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.)" + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: GEN0_A_CNTUFORCE_MODE + description: "Continuous software force mode for PWM0A. 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: GEN0_B_CNTUFORCE_MODE + description: "Continuous software force mode for PWM0B. 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: GEN0_A_NCIFORCE + description: "Trigger of non-continuous immediate software-force event for PWM0A, a toggle will trigger a force event." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GEN0_A_NCIFORCE_MODE + description: "non-continuous immediate software force mode for PWM0A, 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: GEN0_B_NCIFORCE + description: "Trigger of non-continuous immediate software-force event for PWM0B, a toggle will trigger a force event." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: GEN0_B_NCIFORCE_MODE + description: "non-continuous immediate software force mode for PWM0B, 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: GEN0_A + description: Actions triggered by events on PWM0A + addressOffset: 80 + size: 32 + fields: + - name: UTEZ + description: Action on PWM0A triggered by event TEZ when timer increasing + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + description: Action on PWM0A triggered by event TEP when timer increasing + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + description: Action on PWM0A triggered by event TEA when timer increasing + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + description: Action on PWM0A triggered by event TEB when timer increasing + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + description: Action on PWM0A triggered by event_t0 when timer increasing + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + description: Action on PWM0A triggered by event_t1 when timer increasing + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + description: Action on PWM0A triggered by event TEZ when timer decreasing + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + description: Action on PWM0A triggered by event TEP when timer decreasing + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + description: Action on PWM0A triggered by event TEA when timer decreasing + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + description: Action on PWM0A triggered by event TEB when timer decreasing + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + description: Action on PWM0A triggered by event_t0 when timer decreasing + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + description: "Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: GEN0_B + description: Actions triggered by events on PWM0B + addressOffset: 84 + size: 32 + fields: + - name: UTEZ + description: Action on PWM0B triggered by event TEZ when timer increasing + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + description: Action on PWM0B triggered by event TEP when timer increasing + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + description: Action on PWM0B triggered by event TEA when timer increasing + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + description: Action on PWM0B triggered by event TEB when timer increasing + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + description: Action on PWM0B triggered by event_t0 when timer increasing + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + description: Action on PWM0B triggered by event_t1 when timer increasing + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + description: Action on PWM0B triggered by event TEZ when timer decreasing + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + description: Action on PWM0B triggered by event TEP when timer decreasing + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + description: Action on PWM0B triggered by event TEA when timer decreasing + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + description: Action on PWM0B triggered by event TEB when timer decreasing + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + description: Action on PWM0B triggered by event_t0 when timer decreasing + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + description: "Action on PWM0B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: DB0_CFG + description: dead time type selection and configuration + addressOffset: 88 + size: 32 + resetValue: 98304 + fields: + - name: DB0_FED_UPMETHOD + description: "Update method for FED (falling edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze" + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: DB0_RED_UPMETHOD + description: "Update method for RED (rising edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze" + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: DB0_DEB_MODE + description: "S8 in documentation, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DB0_A_OUTSWAP + description: S6 in documentation + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DB0_B_OUTSWAP + description: S7 in documentation + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DB0_RED_INSEL + description: S4 in documentation + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DB0_FED_INSEL + description: S5 in documentation + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DB0_RED_OUTINVERT + description: S2 in documentation + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DB0_FED_OUTINVERT + description: S3 in documentation + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DB0_A_OUTBYPASS + description: S1 in documentation + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DB0_B_OUTBYPASS + description: S0 in documentation + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DB0_CLK_SEL + description: "Dead time generator 0 clock selection. 0: PWM_clk, 1: PT_clk" + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: DB0_FED_CFG + description: Shadow register for falling edge delay (FED). + addressOffset: 92 + size: 32 + fields: + - name: DB0_FED + description: Shadow register for FED + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: DB0_RED_CFG + description: Shadow register for rising edge delay (RED). + addressOffset: 96 + size: 32 + fields: + - name: DB0_RED + description: Shadow register for RED + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: CHOPPER0_CFG + description: Carrier enable and configuratoin + addressOffset: 100 + size: 32 + fields: + - name: CHOPPER0_EN + description: "When set, carrier0 function is enabled. When cleared, carrier0 is bypassed" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CHOPPER0_PRESCALE + description: PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CHOPPER0_DUTY + description: carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + bitOffset: 5 + bitWidth: 3 + access: read-write + - name: CHOPPER0_OSHTWTH + description: width of the fist pulse in number of periods of the carrier + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: CHOPPER0_OUT_INVERT + description: "when set, invert the output of PWM0A and PWM0B for this submodule" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CHOPPER0_IN_INVERT + description: "when set, invert the input of PWM0A and PWM0B for this submodule" + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: TZ0_CFG0 + description: Actions on PWM0A and PWM0B trip events + addressOffset: 104 + size: 32 + fields: + - name: TZ0_SW_CBC + description: "Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TZ0_F2_CBC + description: "event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TZ0_F1_CBC + description: "event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TZ0_F0_CBC + description: "event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TZ0_SW_OST + description: "Enable register for software force one-shot mode action. 0: disable, 1: enable" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TZ0_F2_OST + description: "event_f2 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TZ0_F1_OST + description: "event_f1 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TZ0_F0_OST + description: "event_f0 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TZ0_A_CBC_D + description: "Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: TZ0_A_CBC_U + description: "Cycle-by-cycle mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: TZ0_A_OST_D + description: "One-shot mode action on PWM0A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle" + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: TZ0_A_OST_U + description: "One-shot mode action on PWM0A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle" + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: TZ0_B_CBC_D + description: "Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle" + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: TZ0_B_CBC_U + description: "Cycle-by-cycle mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle" + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: TZ0_B_OST_D + description: "One-shot mode action on PWM0B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle" + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TZ0_B_OST_U + description: "One-shot mode action on PWM0B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: TZ0_CFG1 + description: Software triggers for fault handler actions + addressOffset: 108 + size: 32 + fields: + - name: TZ0_CLR_OST + description: a rising edge will clear on going one-shot mode action + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TZ0_CBCPULSE + description: "cycle-by-cycle mode action refresh moment selection. Bit0: TEZ, bit1:TEP" + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: TZ0_FORCE_CBC + description: a toggle trigger a cycle-by-cycle mode action + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TZ0_FORCE_OST + description: a toggle (software negate its value) triggers a one-shot mode action + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: TZ0_STATUS + description: Status of fault events. + addressOffset: 112 + size: 32 + fields: + - name: TZ0_CBC_ON + description: "Set and reset by hardware. If set, a cycle-by-cycle mode action is on going" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TZ0_OST_ON + description: "Set and reset by hardware. If set, an one-shot mode action is on going" + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: CMPR1_CFG + description: Transfer status and update method for time stamp registers A and B + addressOffset: 116 + size: 32 + fields: + - name: CMPR1_A_UPMETHOD + description: "Update method for PWM generator 1 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: CMPR1_B_UPMETHOD + description: "Update method for PWM generator 1 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: CMPR1_A_SHDW_FULL + description: "Set and reset by hardware. If set, PWM generator 1 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CMPR1_B_SHDW_FULL + description: "Set and reset by hardware. If set, PWM generator 1 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value" + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: CMPR1_VALUE0 + description: Shadow register for register A. + addressOffset: 120 + size: 32 + fields: + - name: CMPR1_A + description: "PWM generator 1 time stamp A's shadow register" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: CMPR1_VALUE1 + description: Shadow register for register B. + addressOffset: 124 + size: 32 + fields: + - name: CMPR1_B + description: "PWM generator 1 time stamp B's shadow register" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: GEN1_CFG0 + description: Fault event T0 and T1 handling + addressOffset: 128 + size: 32 + fields: + - name: GEN1_CFG_UPMETHOD + description: "Update method for PWM generator 1's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:" + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: GEN1_T0_SEL + description: "Source selection for PWM generator 1 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none" + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: GEN1_T1_SEL + description: "Source selection for PWM generator 1 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none" + bitOffset: 7 + bitWidth: 3 + access: read-write + - register: + name: GEN1_FORCE + description: Permissives to force PWM1A and PWM1B outputs by software + addressOffset: 132 + size: 32 + resetValue: 32 + fields: + - name: GEN1_CNTUFORCE_UPMETHOD + description: "Updating method for continuous software force of PWM generator 1. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.)" + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: GEN1_A_CNTUFORCE_MODE + description: "Continuous software force mode for PWM1A. 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: GEN1_B_CNTUFORCE_MODE + description: "Continuous software force mode for PWM1B. 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: GEN1_A_NCIFORCE + description: "Trigger of non-continuous immediate software-force event for PWM1A, a toggle will trigger a force event." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GEN1_A_NCIFORCE_MODE + description: "non-continuous immediate software force mode for PWM1A, 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: GEN1_B_NCIFORCE + description: "Trigger of non-continuous immediate software-force event for PWM1B, a toggle will trigger a force event." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: GEN1_B_NCIFORCE_MODE + description: "non-continuous immediate software force mode for PWM1B, 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: GEN1_A + description: Actions triggered by events on PWM1A + addressOffset: 136 + size: 32 + fields: + - name: UTEZ + description: Action on PWM1A triggered by event TEZ when timer increasing + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + description: Action on PWM1A triggered by event TEP when timer increasing + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + description: Action on PWM1A triggered by event TEA when timer increasing + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + description: Action on PWM1A triggered by event TEB when timer increasing + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + description: Action on PWM1A triggered by event_t0 when timer increasing + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + description: Action on PWM1A triggered by event_t1 when timer increasing + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + description: Action on PWM1A triggered by event TEZ when timer decreasing + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + description: Action on PWM1A triggered by event TEP when timer decreasing + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + description: Action on PWM1A triggered by event TEA when timer decreasing + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + description: Action on PWM1A triggered by event TEB when timer decreasing + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + description: Action on PWM1A triggered by event_t0 when timer decreasing + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + description: "Action on PWM1A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: GEN1_B + description: Actions triggered by events on PWM1B + addressOffset: 140 + size: 32 + fields: + - name: UTEZ + description: Action on PWM1B triggered by event TEZ when timer increasing + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + description: Action on PWM1B triggered by event TEP when timer increasing + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + description: Action on PWM1B triggered by event TEA when timer increasing + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + description: Action on PWM1B triggered by event TEB when timer increasing + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + description: Action on PWM1B triggered by event_t0 when timer increasing + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + description: Action on PWM1B triggered by event_t1 when timer increasing + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + description: Action on PWM1B triggered by event TEZ when timer decreasing + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + description: Action on PWM1B triggered by event TEP when timer decreasing + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + description: Action on PWM1B triggered by event TEA when timer decreasing + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + description: Action on PWM1B triggered by event TEB when timer decreasing + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + description: Action on PWM1B triggered by event_t0 when timer decreasing + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + description: "Action on PWM1B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: DB1_CFG + description: dead time type selection and configuration + addressOffset: 144 + size: 32 + resetValue: 98304 + fields: + - name: DB1_FED_UPMETHOD + description: "Update method for FED (falling edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze" + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: DB1_RED_UPMETHOD + description: "Update method for RED (rising edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze" + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: DB1_DEB_MODE + description: "S8 in documentation, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DB1_A_OUTSWAP + description: S6 in documentation + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DB1_B_OUTSWAP + description: S7 in documentation + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DB1_RED_INSEL + description: S4 in documentation + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DB1_FED_INSEL + description: S5 in documentation + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DB1_RED_OUTINVERT + description: S2 in documentation + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DB1_FED_OUTINVERT + description: S3 in documentation + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DB1_A_OUTBYPASS + description: S1 in documentation + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DB1_B_OUTBYPASS + description: S0 in documentation + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DB1_CLK_SEL + description: "Dead time generator 1 clock selection. 0: PWM_clk, 1: PT_clk" + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: DB1_FED_CFG + description: Shadow register for falling edge delay (FED). + addressOffset: 148 + size: 32 + fields: + - name: DB1_FED + description: Shadow register for FED + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: DB1_RED_CFG + description: Shadow register for rising edge delay (RED). + addressOffset: 152 + size: 32 + fields: + - name: DB1_RED + description: Shadow register for RED + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: CHOPPER1_CFG + description: Carrier enable and configuratoin + addressOffset: 156 + size: 32 + fields: + - name: CHOPPER1_EN + description: "When set, carrier0 function is enabled. When cleared, carrier0 is bypassed" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CHOPPER1_PRESCALE + description: PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CHOPPER1_DUTY + description: carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + bitOffset: 5 + bitWidth: 3 + access: read-write + - name: CHOPPER1_OSHTWTH + description: width of the fist pulse in number of periods of the carrier + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: CHOPPER1_OUT_INVERT + description: "when set, invert the output of PWM1A and PWM1B for this submodule" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CHOPPER1_IN_INVERT + description: "when set, invert the input of PWM1A and PWM1B for this submodule" + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: TZ1_CFG0 + description: Actions on PWM1A and PWM1B trip events + addressOffset: 160 + size: 32 + fields: + - name: TZ1_SW_CBC + description: "Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TZ1_F2_CBC + description: "event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TZ1_F1_CBC + description: "event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TZ1_F0_CBC + description: "event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TZ1_SW_OST + description: "Enable register for software force one-shot mode action. 0: disable, 1: enable" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TZ1_F2_OST + description: "event_f2 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TZ1_F1_OST + description: "event_f1 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TZ1_F0_OST + description: "event_f0 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TZ1_A_CBC_D + description: "Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: TZ1_A_CBC_U + description: "Cycle-by-cycle mode action on PWM1A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: TZ1_A_OST_D + description: "One-shot mode action on PWM1A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle" + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: TZ1_A_OST_U + description: "One-shot mode action on PWM1A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle" + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: TZ1_B_CBC_D + description: "Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle" + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: TZ1_B_CBC_U + description: "Cycle-by-cycle mode action on PWM1B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle" + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: TZ1_B_OST_D + description: "One-shot mode action on PWM1B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle" + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TZ1_B_OST_U + description: "One-shot mode action on PWM1B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: TZ1_CFG1 + description: Software triggers for fault handler actions + addressOffset: 164 + size: 32 + fields: + - name: TZ1_CLR_OST + description: a rising edge will clear on going one-shot mode action + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TZ1_CBCPULSE + description: "cycle-by-cycle mode action refresh moment selection. Bit0: TEZ, bit1:TEP" + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: TZ1_FORCE_CBC + description: a toggle trigger a cycle-by-cycle mode action + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TZ1_FORCE_OST + description: a toggle (software negate its value) triggers a one-shot mode action + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: TZ1_STATUS + description: Status of fault events. + addressOffset: 168 + size: 32 + fields: + - name: TZ1_CBC_ON + description: "Set and reset by hardware. If set, a cycle-by-cycle mode action is on going" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TZ1_OST_ON + description: "Set and reset by hardware. If set, an one-shot mode action is on going" + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: CMPR2_CFG + description: Transfer status and update method for time stamp registers A and B + addressOffset: 172 + size: 32 + fields: + - name: CMPR2_A_UPMETHOD + description: "Update method for PWM generator 2 time stamp A's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update." + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: CMPR2_B_UPMETHOD + description: "Update method for PWM generator 2 time stamp B's active register. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1: TEP,when bit2 is set to 1: sync, when bit3 is set to 1: disable the update." + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: CMPR2_A_SHDW_FULL + description: "Set and reset by hardware. If set, PWM generator 2 time stamp A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared, A's active reg has been updated with shadow register latest value" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CMPR2_B_SHDW_FULL + description: "Set and reset by hardware. If set, PWM generator 2 time stamp B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared, B's active reg has been updated with shadow register latest value" + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: CMPR2_VALUE0 + description: Shadow register for register A. + addressOffset: 176 + size: 32 + fields: + - name: CMPR2_A + description: "PWM generator 2 time stamp A's shadow register" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: CMPR2_VALUE1 + description: Shadow register for register B. + addressOffset: 180 + size: 32 + fields: + - name: CMPR2_B + description: "PWM generator 2 time stamp B's shadow register" + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: GEN2_CFG0 + description: Fault event T0 and T1 handling + addressOffset: 184 + size: 32 + fields: + - name: GEN2_CFG_UPMETHOD + description: "Update method for PWM generator 2's active register of configuration. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ, when bit1 is set to 1:" + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: GEN2_T0_SEL + description: "Source selection for PWM generator 2 event_t0, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none" + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: GEN2_T1_SEL + description: "Source selection for PWM generator 2 event_t1, take effect immediately, 0: fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none" + bitOffset: 7 + bitWidth: 3 + access: read-write + - register: + name: GEN2_FORCE + description: Permissives to force PWM2A and PWM2B outputs by software + addressOffset: 188 + size: 32 + resetValue: 32 + fields: + - name: GEN2_CNTUFORCE_UPMETHOD + description: "Updating method for continuous software force of PWM generator 2. When all bits are set to 0: immediately, when bit0 is set to 1: TEZ,,when bit1 is set to 1: TEP, when bit2 is set to 1: TEA, when bit3 is set to 1: TEB, when bit4 is set to 1: sync, when bit5 is set to 1: disable update. (TEA/B here and below means an event generated when the timer's value equals to that of register A/B.)" + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: GEN2_A_CNTUFORCE_MODE + description: "Continuous software force mode for PWM2A. 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: GEN2_B_CNTUFORCE_MODE + description: "Continuous software force mode for PWM2B. 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: GEN2_A_NCIFORCE + description: "Trigger of non-continuous immediate software-force event for PWM2A, a toggle will trigger a force event." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GEN2_A_NCIFORCE_MODE + description: "non-continuous immediate software force mode for PWM2A, 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: GEN2_B_NCIFORCE + description: "Trigger of non-continuous immediate software-force event for PWM2B, a toggle will trigger a force event." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: GEN2_B_NCIFORCE_MODE + description: "non-continuous immediate software force mode for PWM2B, 0: disabled, 1: low, 2: high, 3: disabled" + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: GEN2_A + description: Actions triggered by events on PWM2A + addressOffset: 192 + size: 32 + fields: + - name: UTEZ + description: Action on PWM2A triggered by event TEZ when timer increasing + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + description: Action on PWM2A triggered by event TEP when timer increasing + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + description: Action on PWM2A triggered by event TEA when timer increasing + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + description: Action on PWM2A triggered by event TEB when timer increasing + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + description: Action on PWM2A triggered by event_t0 when timer increasing + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + description: Action on PWM2A triggered by event_t1 when timer increasing + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + description: Action on PWM2A triggered by event TEZ when timer decreasing + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + description: Action on PWM2A triggered by event TEP when timer decreasing + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + description: Action on PWM2A triggered by event TEA when timer decreasing + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + description: Action on PWM2A triggered by event TEB when timer decreasing + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + description: Action on PWM2A triggered by event_t0 when timer decreasing + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + description: "Action on PWM2A triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: GEN2_B + description: Actions triggered by events on PWM2B + addressOffset: 196 + size: 32 + fields: + - name: UTEZ + description: Action on PWM2B triggered by event TEZ when timer increasing + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: UTEP + description: Action on PWM2B triggered by event TEP when timer increasing + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: UTEA + description: Action on PWM2B triggered by event TEA when timer increasing + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: UTEB + description: Action on PWM2B triggered by event TEB when timer increasing + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: UT0 + description: Action on PWM2B triggered by event_t0 when timer increasing + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: UT1 + description: Action on PWM2B triggered by event_t1 when timer increasing + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DTEZ + description: Action on PWM2B triggered by event TEZ when timer decreasing + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DTEP + description: Action on PWM2B triggered by event TEP when timer decreasing + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DTEA + description: Action on PWM2B triggered by event TEA when timer decreasing + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: DTEB + description: Action on PWM2B triggered by event TEB when timer decreasing + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: DT0 + description: Action on PWM2B triggered by event_t0 when timer decreasing + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: DT1 + description: "Action on PWM2B triggered by event_t1 when timer decreasing. 0: no change, 1: low, 2: high, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: DB2_CFG + description: dead time type selection and configuration + addressOffset: 200 + size: 32 + resetValue: 98304 + fields: + - name: DB2_FED_UPMETHOD + description: "Update method for FED (falling edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze" + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: DB2_RED_UPMETHOD + description: "Update method for RED (rising edge delay) active register. 0: immediate, bit0: tez, bit1: tep, bit2: sync, bit3: freeze" + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: DB2_DEB_MODE + description: "S8 in documentation, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DB2_A_OUTSWAP + description: S6 in documentation + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DB2_B_OUTSWAP + description: S7 in documentation + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DB2_RED_INSEL + description: S4 in documentation + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DB2_FED_INSEL + description: S5 in documentation + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DB2_RED_OUTINVERT + description: S2 in documentation + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DB2_FED_OUTINVERT + description: S3 in documentation + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DB2_A_OUTBYPASS + description: S1 in documentation + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DB2_B_OUTBYPASS + description: S0 in documentation + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DB2_CLK_SEL + description: "Dead time generator 2 clock selection. 0: PWM_clk, 1: PT_clk" + bitOffset: 17 + bitWidth: 1 + access: read-write + - register: + name: DB2_FED_CFG + description: Shadow register for falling edge delay (FED). + addressOffset: 204 + size: 32 + fields: + - name: DB2_FED + description: Shadow register for FED + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: DB2_RED_CFG + description: Shadow register for rising edge delay (RED). + addressOffset: 208 + size: 32 + fields: + - name: DB2_RED + description: Shadow register for RED + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: CHOPPER2_CFG + description: Carrier enable and configuratoin + addressOffset: 212 + size: 32 + fields: + - name: CHOPPER2_EN + description: "When set, carrier0 function is enabled. When cleared, carrier0 is bypassed" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CHOPPER2_PRESCALE + description: PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1) + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CHOPPER2_DUTY + description: carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8 + bitOffset: 5 + bitWidth: 3 + access: read-write + - name: CHOPPER2_OSHTWTH + description: width of the fist pulse in number of periods of the carrier + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: CHOPPER2_OUT_INVERT + description: "when set, invert the output of PWM2A and PWM2B for this submodule" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: CHOPPER2_IN_INVERT + description: "when set, invert the input of PWM2A and PWM2B for this submodule" + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: TZ2_CFG0 + description: Actions on PWM2A and PWM2B trip events + addressOffset: 216 + size: 32 + fields: + - name: TZ2_SW_CBC + description: "Enable register for software force cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TZ2_F2_CBC + description: "event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TZ2_F1_CBC + description: "event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TZ2_F0_CBC + description: "event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TZ2_SW_OST + description: "Enable register for software force one-shot mode action. 0: disable, 1: enable" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TZ2_F2_OST + description: "event_f2 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TZ2_F1_OST + description: "event_f1 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TZ2_F0_OST + description: "event_f0 will trigger one-shot mode action. 0: disable, 1: enable" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TZ2_A_CBC_D + description: "Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: TZ2_A_CBC_U + description: "Cycle-by-cycle mode action on PWM2A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: TZ2_A_OST_D + description: "One-shot mode action on PWM2A when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle" + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: TZ2_A_OST_U + description: "One-shot mode action on PWM2A when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle" + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: TZ2_B_CBC_D + description: "Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle" + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: TZ2_B_CBC_U + description: "Cycle-by-cycle mode action on PWM2B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle" + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: TZ2_B_OST_D + description: "One-shot mode action on PWM2B when fault event occurs and timer is decreasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle" + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: TZ2_B_OST_U + description: "One-shot mode action on PWM2B when fault event occurs and timer is increasing. 0: do nothing, 1: force lo, 2: force hi, 3: toggle" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: TZ2_CFG1 + description: Software triggers for fault handler actions + addressOffset: 220 + size: 32 + fields: + - name: TZ2_CLR_OST + description: a rising edge will clear on going one-shot mode action + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TZ2_CBCPULSE + description: "cycle-by-cycle mode action refresh moment selection. Bit0: TEZ, bit1:TEP" + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: TZ2_FORCE_CBC + description: a toggle trigger a cycle-by-cycle mode action + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TZ2_FORCE_OST + description: a toggle (software negate its value) triggers a one-shot mode action + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: TZ2_STATUS + description: Status of fault events. + addressOffset: 224 + size: 32 + fields: + - name: TZ2_CBC_ON + description: "Set and reset by hardware. If set, a cycle-by-cycle mode action is on going" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TZ2_OST_ON + description: "Set and reset by hardware. If set, an one-shot mode action is on going" + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: FAULT_DETECT + description: Fault detection configuration and status + addressOffset: 228 + size: 32 + fields: + - name: F0_EN + description: "When set, event_f0 generation is enabled" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: F1_EN + description: "When set, event_f1 generation is enabled" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: F2_EN + description: "When set, event_f2 generation is enabled" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: F0_POLE + description: "Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: F1_POLE + description: "Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: F2_POLE + description: "Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1: level high" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: EVENT_F0 + description: "Set and reset by hardware. If set, event_f0 is on going" + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: EVENT_F1 + description: "Set and reset by hardware. If set, event_f1 is on going" + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: EVENT_F2 + description: "Set and reset by hardware. If set, event_f2 is on going" + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: CAP_TIMER_CFG + description: Configure capture timer + addressOffset: 232 + size: 32 + fields: + - name: CAP_TIMER_EN + description: "When set, capture timer incrementing under APB_clk is enabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CAP_SYNCI_EN + description: "When set, capture timer sync is enabled." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CAP_SYNCI_SEL + description: "capture module sync input selection. 0: none, 1: timer0 sync_out, 2: timer1 sync_out, 3: timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO matrix, 6: SYNC2 from GPIO matrix" + bitOffset: 2 + bitWidth: 3 + access: read-write + - name: CAP_SYNC_SW + description: "Write 1 will force a capture timer sync, capture timer is loaded with value in phase register." + bitOffset: 5 + bitWidth: 1 + access: write-only + - register: + name: CAP_TIMER_PHASE + description: Phase for capture timer sync + addressOffset: 236 + size: 32 + fields: + - name: CAP_PHASE + description: Phase value for capture timer sync operation. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CAP_CH0_CFG + description: Capture channel 0 configuration and enable + addressOffset: 240 + size: 32 + fields: + - name: CAP0_EN + description: "When set, capture on channel 0 is enabled" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CAP0_MODE + description: "Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge." + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: CAP0_PRESCALE + description: Value of prescaling on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1 + bitOffset: 3 + bitWidth: 8 + access: read-write + - name: CAP0_IN_INVERT + description: "when set, CAP0 form GPIO matrix is inverted before prescale" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CAP0_SW + description: Write 1 will trigger a software forced capture on channel 0 + bitOffset: 12 + bitWidth: 1 + access: write-only + - register: + name: CAP_CH1_CFG + description: Capture channel 1 configuration and enable + addressOffset: 244 + size: 32 + fields: + - name: CAP1_EN + description: "When set, capture on channel 2 is enabled" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CAP1_MODE + description: "Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge." + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: CAP1_PRESCALE + description: Value of prescaling on possitive edge of CAP1. Prescale value = PWM_CAP1_PRESCALE + 1 + bitOffset: 3 + bitWidth: 8 + access: read-write + - name: CAP1_IN_INVERT + description: "when set, CAP1 form GPIO matrix is inverted before prescale" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CAP1_SW + description: Write 1 will trigger a software forced capture on channel 1 + bitOffset: 12 + bitWidth: 1 + access: write-only + - register: + name: CAP_CH2_CFG + description: Capture channel 2 configuration and enable + addressOffset: 248 + size: 32 + fields: + - name: CAP2_EN + description: "When set, capture on channel 2 is enabled" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CAP2_MODE + description: "Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable capture on the negative edge, When bit1 is set to 1: enable capture on the positive edge." + bitOffset: 1 + bitWidth: 2 + access: read-write + - name: CAP2_PRESCALE + description: Value of prescaling on possitive edge of CAP2. Prescale value = PWM_CAP2_PRESCALE + 1 + bitOffset: 3 + bitWidth: 8 + access: read-write + - name: CAP2_IN_INVERT + description: "when set, CAP2 form GPIO matrix is inverted before prescale" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: CAP2_SW + description: Write 1 will trigger a software forced capture on channel 2 + bitOffset: 12 + bitWidth: 1 + access: write-only + - register: + name: CAP_CH0 + description: Value of last capture on channel 0 + addressOffset: 252 + size: 32 + fields: + - name: CAP0_VALUE + description: Value of last capture on channel 0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CAP_CH1 + description: Value of last capture on channel 1 + addressOffset: 256 + size: 32 + fields: + - name: CAP1_VALUE + description: Value of last capture on channel 1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CAP_CH2 + description: Value of last capture on channel 2 + addressOffset: 260 + size: 32 + fields: + - name: CAP2_VALUE + description: Value of last capture on channel 2 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CAP_STATUS + description: Edge of last capture trigger + addressOffset: 264 + size: 32 + fields: + - name: CAP0_EDGE + description: "Edge of last capture trigger on channel 0, 0: posedge, 1: negedge" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CAP1_EDGE + description: "Edge of last capture trigger on channel 1, 0: posedge, 1: negedge" + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CAP2_EDGE + description: "Edge of last capture trigger on channel 2, 0: posedge, 1: negedge" + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: UPDATE_CFG + description: Enable update. + addressOffset: 268 + size: 32 + resetValue: 85 + fields: + - name: GLOBAL_UP_EN + description: The global enable of update of all active registers in MCPWM module + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: GLOBAL_FORCE_UP + description: a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OP0_UP_EN + description: "When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 0 are enabled" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OP0_FORCE_UP + description: a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OP1_UP_EN + description: "When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 1 are enabled" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: OP1_FORCE_UP + description: a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OP2_UP_EN + description: "When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM operator 2 are enabled" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OP2_FORCE_UP + description: a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2 + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 272 + size: 32 + fields: + - name: TIMER0_STOP_INT_ENA + description: The enable bit for the interrupt triggered when the timer 0 stops. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMER1_STOP_INT_ENA + description: The enable bit for the interrupt triggered when the timer 1 stops. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER2_STOP_INT_ENA + description: The enable bit for the interrupt triggered when the timer 2 stops. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TIMER0_TEZ_INT_ENA + description: The enable bit for the interrupt triggered by a PWM timer 0 TEZ event. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TIMER1_TEZ_INT_ENA + description: The enable bit for the interrupt triggered by a PWM timer 1 TEZ event. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TIMER2_TEZ_INT_ENA + description: The enable bit for the interrupt triggered by a PWM timer 2 TEZ event. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TIMER0_TEP_INT_ENA + description: The enable bit for the interrupt triggered by a PWM timer 0 TEP event. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TIMER1_TEP_INT_ENA + description: The enable bit for the interrupt triggered by a PWM timer 1 TEP event. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TIMER2_TEP_INT_ENA + description: The enable bit for the interrupt triggered by a PWM timer 2 TEP event. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FAULT0_INT_ENA + description: The enable bit for the interrupt triggered when event_f0 starts. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FAULT1_INT_ENA + description: The enable bit for the interrupt triggered when event_f1 starts. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FAULT2_INT_ENA + description: The enable bit for the interrupt triggered when event_f2 starts. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FAULT0_CLR_INT_ENA + description: The enable bit for the interrupt triggered when event_f0 ends. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FAULT1_CLR_INT_ENA + description: The enable bit for the interrupt triggered when event_f1 ends. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FAULT2_CLR_INT_ENA + description: The enable bit for the interrupt triggered when event_f2 ends. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CMPR0_TEA_INT_ENA + description: The enable bit for the interrupt triggered by a PWM operator 0 TEA event + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CMPR1_TEA_INT_ENA + description: The enable bit for the interrupt triggered by a PWM operator 1 TEA event + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CMPR2_TEA_INT_ENA + description: The enable bit for the interrupt triggered by a PWM operator 2 TEA event + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: CMPR0_TEB_INT_ENA + description: The enable bit for the interrupt triggered by a PWM operator 0 TEB event + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: CMPR1_TEB_INT_ENA + description: The enable bit for the interrupt triggered by a PWM operator 1 TEB event + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: CMPR2_TEB_INT_ENA + description: The enable bit for the interrupt triggered by a PWM operator 2 TEB event + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TZ0_CBC_INT_ENA + description: The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: TZ1_CBC_INT_ENA + description: The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TZ2_CBC_INT_ENA + description: The enable bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TZ0_OST_INT_ENA + description: The enable bit for the interrupt triggered by a one-shot mode action on PWM0. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TZ1_OST_INT_ENA + description: The enable bit for the interrupt triggered by a one-shot mode action on PWM1. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TZ2_OST_INT_ENA + description: The enable bit for the interrupt triggered by a one-shot mode action on PWM2. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CAP0_INT_ENA + description: The enable bit for the interrupt triggered by capture on channel 0. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: CAP1_INT_ENA + description: The enable bit for the interrupt triggered by capture on channel 1. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CAP2_INT_ENA + description: The enable bit for the interrupt triggered by capture on channel 2. + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 276 + size: 32 + fields: + - name: TIMER0_STOP_INT_RAW + description: The raw status bit for the interrupt triggered when the timer 0 stops. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMER1_STOP_INT_RAW + description: The raw status bit for the interrupt triggered when the timer 1 stops. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TIMER2_STOP_INT_RAW + description: The raw status bit for the interrupt triggered when the timer 2 stops. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TIMER0_TEZ_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM timer 0 TEZ event. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TIMER1_TEZ_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM timer 1 TEZ event. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TIMER2_TEZ_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM timer 2 TEZ event. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TIMER0_TEP_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM timer 0 TEP event. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TIMER1_TEP_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM timer 1 TEP event. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TIMER2_TEP_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM timer 2 TEP event. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FAULT0_INT_RAW + description: The raw status bit for the interrupt triggered when event_f0 starts. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FAULT1_INT_RAW + description: The raw status bit for the interrupt triggered when event_f1 starts. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FAULT2_INT_RAW + description: The raw status bit for the interrupt triggered when event_f2 starts. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FAULT0_CLR_INT_RAW + description: The raw status bit for the interrupt triggered when event_f0 ends. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FAULT1_CLR_INT_RAW + description: The raw status bit for the interrupt triggered when event_f1 ends. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FAULT2_CLR_INT_RAW + description: The raw status bit for the interrupt triggered when event_f2 ends. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CMPR0_TEA_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM operator 0 TEA event + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CMPR1_TEA_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM operator 1 TEA event + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CMPR2_TEA_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM operator 2 TEA event + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: CMPR0_TEB_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM operator 0 TEB event + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: CMPR1_TEB_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM operator 1 TEB event + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: CMPR2_TEB_INT_RAW + description: The raw status bit for the interrupt triggered by a PWM operator 2 TEB event + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TZ0_CBC_INT_RAW + description: The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: TZ1_CBC_INT_RAW + description: The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TZ2_CBC_INT_RAW + description: The raw status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TZ0_OST_INT_RAW + description: The raw status bit for the interrupt triggered by a one-shot mode action on PWM0. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TZ1_OST_INT_RAW + description: The raw status bit for the interrupt triggered by a one-shot mode action on PWM1. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TZ2_OST_INT_RAW + description: The raw status bit for the interrupt triggered by a one-shot mode action on PWM2. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CAP0_INT_RAW + description: The raw status bit for the interrupt triggered by capture on channel 0. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: CAP1_INT_RAW + description: The raw status bit for the interrupt triggered by capture on channel 1. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CAP2_INT_RAW + description: The raw status bit for the interrupt triggered by capture on channel 2. + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 280 + size: 32 + fields: + - name: TIMER0_STOP_INT_ST + description: The masked status bit for the interrupt triggered when the timer 0 stops. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TIMER1_STOP_INT_ST + description: The masked status bit for the interrupt triggered when the timer 1 stops. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TIMER2_STOP_INT_ST + description: The masked status bit for the interrupt triggered when the timer 2 stops. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TIMER0_TEZ_INT_ST + description: The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TIMER1_TEZ_INT_ST + description: The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TIMER2_TEZ_INT_ST + description: The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: TIMER0_TEP_INT_ST + description: The masked status bit for the interrupt triggered by a PWM timer 0 TEP event. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TIMER1_TEP_INT_ST + description: The masked status bit for the interrupt triggered by a PWM timer 1 TEP event. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TIMER2_TEP_INT_ST + description: The masked status bit for the interrupt triggered by a PWM timer 2 TEP event. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: FAULT0_INT_ST + description: The masked status bit for the interrupt triggered when event_f0 starts. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: FAULT1_INT_ST + description: The masked status bit for the interrupt triggered when event_f1 starts. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: FAULT2_INT_ST + description: The masked status bit for the interrupt triggered when event_f2 starts. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: FAULT0_CLR_INT_ST + description: The masked status bit for the interrupt triggered when event_f0 ends. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: FAULT1_CLR_INT_ST + description: The masked status bit for the interrupt triggered when event_f1 ends. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: FAULT2_CLR_INT_ST + description: The masked status bit for the interrupt triggered when event_f2 ends. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: CMPR0_TEA_INT_ST + description: The masked status bit for the interrupt triggered by a PWM operator 0 TEA event + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: CMPR1_TEA_INT_ST + description: The masked status bit for the interrupt triggered by a PWM operator 1 TEA event + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: CMPR2_TEA_INT_ST + description: The masked status bit for the interrupt triggered by a PWM operator 2 TEA event + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: CMPR0_TEB_INT_ST + description: The masked status bit for the interrupt triggered by a PWM operator 0 TEB event + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: CMPR1_TEB_INT_ST + description: The masked status bit for the interrupt triggered by a PWM operator 1 TEB event + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: CMPR2_TEB_INT_ST + description: The masked status bit for the interrupt triggered by a PWM operator 2 TEB event + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: TZ0_CBC_INT_ST + description: The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: TZ1_CBC_INT_ST + description: The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1. + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: TZ2_CBC_INT_ST + description: The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2. + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: TZ0_OST_INT_ST + description: The masked status bit for the interrupt triggered by a one-shot mode action on PWM0. + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: TZ1_OST_INT_ST + description: The masked status bit for the interrupt triggered by a one-shot mode action on PWM1. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: TZ2_OST_INT_ST + description: The masked status bit for the interrupt triggered by a one-shot mode action on PWM2. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: CAP0_INT_ST + description: The masked status bit for the interrupt triggered by capture on channel 0. + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: CAP1_INT_ST + description: The masked status bit for the interrupt triggered by capture on channel 1. + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: CAP2_INT_ST + description: The masked status bit for the interrupt triggered by capture on channel 2. + bitOffset: 29 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 284 + size: 32 + fields: + - name: TIMER0_STOP_INT_CLR + description: Set this bit to clear the interrupt triggered when the timer 0 stops. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TIMER1_STOP_INT_CLR + description: Set this bit to clear the interrupt triggered when the timer 1 stops. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TIMER2_STOP_INT_CLR + description: Set this bit to clear the interrupt triggered when the timer 2 stops. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TIMER0_TEZ_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TIMER1_TEZ_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: TIMER2_TEZ_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TIMER0_TEP_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TIMER1_TEP_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: TIMER2_TEP_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: FAULT0_INT_CLR + description: Set this bit to clear the interrupt triggered when event_f0 starts. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: FAULT1_INT_CLR + description: Set this bit to clear the interrupt triggered when event_f1 starts. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: FAULT2_INT_CLR + description: Set this bit to clear the interrupt triggered when event_f2 starts. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: FAULT0_CLR_INT_CLR + description: Set this bit to clear the interrupt triggered when event_f0 ends. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: FAULT1_CLR_INT_CLR + description: Set this bit to clear the interrupt triggered when event_f1 ends. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: FAULT2_CLR_INT_CLR + description: Set this bit to clear the interrupt triggered when event_f2 ends. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: CMPR0_TEA_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: CMPR1_TEA_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: CMPR2_TEA_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: CMPR0_TEB_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: CMPR1_TEB_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: CMPR2_TEB_INT_CLR + description: Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: TZ0_CBC_INT_CLR + description: Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0. + bitOffset: 21 + bitWidth: 1 + access: write-only + - name: TZ1_CBC_INT_CLR + description: Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1. + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: TZ2_CBC_INT_CLR + description: Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2. + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: TZ0_OST_INT_CLR + description: Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0. + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: TZ1_OST_INT_CLR + description: Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1. + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: TZ2_OST_INT_CLR + description: Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2. + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: CAP0_INT_CLR + description: Set this bit to clear the interrupt triggered by capture on channel 0. + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: CAP1_INT_CLR + description: Set this bit to clear the interrupt triggered by capture on channel 1. + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: CAP2_INT_CLR + description: Set this bit to clear the interrupt triggered by capture on channel 2. + bitOffset: 29 + bitWidth: 1 + access: write-only + - register: + name: CLK + description: MCPWM APB configuration register + addressOffset: 288 + size: 32 + fields: + - name: EN + description: Force clock on for this register file + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: VERSION + description: Version register. + addressOffset: 292 + size: 32 + resetValue: 22057232 + fields: + - name: DATE + description: Version of this register file + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: MCPWM1 + description: Motor Control Pulse-Width Modulation 1 + baseAddress: 1610792960 + interrupt: + - name: MCPWM1 + value: 32 + derivedFrom: MCPWM0 + - name: RMT + description: Remote Control + groupName: RMT + baseAddress: 1610702848 + addressBlock: + - offset: 0 + size: 208 + usage: registers + interrupt: + - name: RMT + value: 40 + registers: + - register: + dim: 8 + dimIncrement: 4 + name: CH%sDATA + description: The read and write data register for CHANNEL%s by apb fifo access. + addressOffset: 0 + size: 32 + fields: + - name: DATA + description: Read and write data for channel %s via APB FIFO. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: CH%s_TX_CONF0 + description: Channel %s configure register 0 + addressOffset: 32 + size: 32 + resetValue: 7406080 + fields: + - name: TX_START + description: Set this bit to start sending data on CHANNEL%s. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: MEM_RD_RST + description: Set this bit to reset read ram address for CHANNEL%s by accessing transmitter. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: APB_MEM_RST + description: Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TX_CONTI_MODE + description: Set this bit to restart transmission from the first data to the last data in CHANNEL%s. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: MEM_TX_WRAP_EN + description: "This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: IDLE_OUT_LV + description: This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: IDLE_OUT_EN + description: This is the output enable-control bit for CHANNEL%s in IDLE state. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_STOP + description: Set this bit to stop the transmitter of CHANNEL%s sending data out. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DIV_CNT + description: This register is used to configure the divider for clock of CHANNEL%s. + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: MEM_SIZE + description: This register is used to configure the maximum size of memory allocated to CHANNEL%s. + bitOffset: 16 + bitWidth: 4 + access: read-write + - name: CARRIER_EFF_EN + description: "1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CARRIER_EN + description: "This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CARRIER_OUT_LV + description: "This bit is used to configure the position of carrier wave for CHANNEL%s.\n\n1'h0: add carrier wave on low level.\n\n1'h1: add carrier wave on high level." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: AFIFO_RST + description: Reserved + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: CONF_UPDATE + description: synchronization bit for CHANNEL%s + bitOffset: 24 + bitWidth: 1 + access: write-only + - register: + dim: 4 + dimIncrement: 8 + dimIndex: "4,5,6,7" + name: CH%s_RX_CONF0 + description: Channel %s configure register 0 + addressOffset: 48 + size: 32 + resetValue: 830471938 + fields: + - name: DIV_CNT + description: This register is used to configure the divider for clock of CHANNEL%s. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: IDLE_THRES + description: "When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished." + bitOffset: 8 + bitWidth: 15 + access: read-write + - name: MEM_SIZE + description: This register is used to configure the maximum size of memory allocated to CHANNEL%s. + bitOffset: 24 + bitWidth: 4 + access: read-write + - name: CARRIER_EN + description: "This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CARRIER_OUT_LV + description: "This bit is used to configure the position of carrier wave for CHANNEL%s.\n\n1'h0: add carrier wave on low level.\n\n1'h1: add carrier wave on high level." + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + dim: 4 + dimIncrement: 8 + dimIndex: "4,5,6,7" + name: CH%s_RX_CONF1 + description: Channel %s configure register 1 + addressOffset: 52 + size: 32 + resetValue: 488 + fields: + - name: RX_EN + description: Set this bit to enable receiver to receive data on CHANNEL%s. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_WR_RST + description: Set this bit to reset write ram address for CHANNEL%s by accessing receiver. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: APB_MEM_RST + description: Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: MEM_OWNER + description: "This register marks the ownership of CHANNEL%s's ram block.\n\n1'h1: Receiver is using the ram. \n\n1'h0: APB bus is using the ram." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_FILTER_EN + description: "This is the receive filter's enable bit for CHANNEL%s." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_FILTER_THRES + description: Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode). + bitOffset: 5 + bitWidth: 8 + access: read-write + - name: MEM_RX_WRAP_EN + description: "This is the channel %s enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: AFIFO_RST + description: Reserved + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: CONF_UPDATE + description: synchronization bit for CHANNEL%s + bitOffset: 15 + bitWidth: 1 + access: write-only + - register: + dim: 4 + dimIncrement: 4 + name: CH%s_TX_STATUS + description: Channel %s status register + addressOffset: 80 + size: 32 + fields: + - name: MEM_RADDR_EX + description: This register records the memory address offset when transmitter of CHANNEL%s is using the RAM. + bitOffset: 0 + bitWidth: 10 + access: read-only + - name: APB_MEM_WADDR + description: This register records the memory address offset when writes RAM over APB bus. + bitOffset: 11 + bitWidth: 10 + access: read-only + - name: STATE + description: This register records the FSM status of CHANNEL%s. + bitOffset: 22 + bitWidth: 3 + access: read-only + - name: MEM_EMPTY + description: This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: APB_MEM_WR_ERR + description: This status bit will be set if the offset address out of memory size when writes via APB bus. + bitOffset: 26 + bitWidth: 1 + access: read-only + - register: + dim: 4 + dimIncrement: 4 + name: CH%s_RX_STATUS + description: Channel %s status register + addressOffset: 96 + size: 32 + resetValue: 393408 + fields: + - name: MEM_WADDR_EX + description: This register records the memory address offset when receiver of CHANNEL%s is using the RAM. + bitOffset: 0 + bitWidth: 10 + access: read-only + - name: APB_MEM_RADDR + description: This register records the memory address offset when reads RAM over APB bus. + bitOffset: 11 + bitWidth: 10 + access: read-only + - name: STATE + description: This register records the FSM status of CHANNEL%s. + bitOffset: 22 + bitWidth: 3 + access: read-only + - name: MEM_OWNER_ERR + description: This status bit will be set when the ownership of memory block is wrong. + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: MEM_FULL + description: This status bit will be set if the receiver receives more data than the memory size. + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: APB_MEM_RD_ERR + description: This status bit will be set if the offset address out of memory size when reads via APB bus. + bitOffset: 27 + bitWidth: 1 + access: read-only + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 112 + size: 32 + fields: + - dim: 4 + dimIncrement: 1 + dimIndex: "0,1,2,3" + name: CH%s_TX_END + description: The interrupt raw bit for CHANNEL%s. Triggered when transmission done. + bitOffset: 0 + bitWidth: 1 + access: read-write + - dim: 4 + dimIncrement: 1 + dimIndex: "0,1,2,3" + name: CH%s_TX_ERR + description: The interrupt raw bit for CHANNEL%s. Triggered when error occurs. + bitOffset: 4 + bitWidth: 1 + access: read-write + - dim: 4 + dimIncrement: 1 + dimIndex: "0,1,2,3" + name: CH%s_TX_THR_EVENT + description: The interrupt raw bit for CHANNEL%s. Triggered when transmitter sent more data than configured value. + bitOffset: 8 + bitWidth: 1 + access: read-write + - dim: 4 + dimIncrement: 1 + dimIndex: "0,1,2,3" + name: CH%s_TX_LOOP + description: The interrupt raw bit for CHANNEL%s. Triggered when the loop count reaches the configured threshold value. + bitOffset: 12 + bitWidth: 1 + access: read-write + - dim: 4 + dimIncrement: 1 + dimIndex: "4,5,6,7" + name: CH%s_RX_END + description: The interrupt raw bit for CHANNEL4. Triggered when reception done. + bitOffset: 16 + bitWidth: 1 + access: read-write + - dim: 4 + dimIncrement: 1 + dimIndex: "4,5,6,7" + name: CH%s_RX_ERR + description: The interrupt raw bit for CHANNEL4. Triggered when error occurs. + bitOffset: 20 + bitWidth: 1 + access: read-write + - dim: 4 + dimIncrement: 1 + dimIndex: "4,5,6,7" + name: CH%s_RX_THR_EVENT + description: The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than configured value. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TX_CH3_DMA_ACCESS_FAIL + description: The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: RX_CH7_DMA_ACCESS_FAIL + description: The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails. + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 116 + size: 32 + fields: + - dim: 4 + dimIncrement: 1 + dimIndex: "0,1,2,3" + name: CH%s_TX_END + description: The masked interrupt status bit for CH%s_TX_END_INT. + bitOffset: 0 + bitWidth: 1 + access: read-only + - dim: 4 + dimIncrement: 1 + dimIndex: "0,1,2,3" + name: CH%s_TX_ERR + description: The masked interrupt status bit for CH%s_ERR_INT. + bitOffset: 4 + bitWidth: 1 + access: read-only + - dim: 4 + dimIncrement: 1 + dimIndex: "0,1,2,3" + name: CH%s_TX_THR_EVENT + description: The masked interrupt status bit for CH%s_TX_THR_EVENT_INT. + bitOffset: 8 + bitWidth: 1 + access: read-only + - dim: 4 + dimIncrement: 1 + dimIndex: "0,1,2,3" + name: CH%s_TX_LOOP + description: The masked interrupt status bit for CH%s_TX_LOOP_INT. + bitOffset: 12 + bitWidth: 1 + access: read-only + - dim: 4 + dimIncrement: 1 + dimIndex: "4,5,6,7" + name: CH%s_RX_END + description: The masked interrupt status bit for CH4_RX_END_INT. + bitOffset: 16 + bitWidth: 1 + access: read-only + - dim: 4 + dimIncrement: 1 + dimIndex: "4,5,6,7" + name: CH%s_RX_ERR + description: The masked interrupt status bit for CH4_ERR_INT. + bitOffset: 20 + bitWidth: 1 + access: read-only + - dim: 4 + dimIncrement: 1 + dimIndex: "4,5,6,7" + name: CH%s_RX_THR_EVENT + description: The masked interrupt status bit for CH4_RX_THR_EVENT_INT. + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: TX_CH3_DMA_ACCESS_FAIL + description: The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT. + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: RX_CH7_DMA_ACCESS_FAIL + description: The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT. + bitOffset: 29 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 120 + size: 32 + fields: + - dim: 4 + dimIncrement: 1 + dimIndex: "0,1,2,3" + name: CH%s_TX_END + description: The interrupt enable bit for CH%s_TX_END_INT. + bitOffset: 0 + bitWidth: 1 + access: read-write + - dim: 4 + dimIncrement: 1 + dimIndex: "0,1,2,3" + name: CH%s_TX_ERR + description: The interrupt enable bit for CH%s_ERR_INT. + bitOffset: 4 + bitWidth: 1 + access: read-write + - dim: 4 + dimIncrement: 1 + dimIndex: "0,1,2,3" + name: CH%s_TX_THR_EVENT + description: The interrupt enable bit for CH%s_TX_THR_EVENT_INT. + bitOffset: 8 + bitWidth: 1 + access: read-write + - dim: 4 + dimIncrement: 1 + dimIndex: "0,1,2,3" + name: CH%s_TX_LOOP + description: The interrupt enable bit for CH%s_TX_LOOP_INT. + bitOffset: 12 + bitWidth: 1 + access: read-write + - dim: 4 + dimIncrement: 1 + dimIndex: "4,5,6,7" + name: CH%s_RX_END + description: The interrupt enable bit for CH4_RX_END_INT. + bitOffset: 16 + bitWidth: 1 + access: read-write + - dim: 4 + dimIncrement: 1 + dimIndex: "4,5,6,7" + name: CH%s_RX_ERR + description: The interrupt enable bit for CH4_ERR_INT. + bitOffset: 20 + bitWidth: 1 + access: read-write + - dim: 4 + dimIncrement: 1 + dimIndex: "4,5,6,7" + name: CH%s_RX_THR_EVENT + description: The interrupt enable bit for CH4_RX_THR_EVENT_INT. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TX_CH3_DMA_ACCESS_FAIL + description: The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: RX_CH7_DMA_ACCESS_FAIL + description: The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT. + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 124 + size: 32 + fields: + - dim: 4 + dimIncrement: 1 + dimIndex: "0,1,2,3" + name: CH%s_TX_END + description: Set this bit to clear theCH%s_TX_END_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - dim: 4 + dimIncrement: 1 + dimIndex: "0,1,2,3" + name: CH%s_TX_ERR + description: Set this bit to clear theCH%s_ERR_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - dim: 4 + dimIncrement: 1 + dimIndex: "0,1,2,3" + name: CH%s_TX_THR_EVENT + description: Set this bit to clear theCH%s_TX_THR_EVENT_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - dim: 4 + dimIncrement: 1 + dimIndex: "0,1,2,3" + name: CH%s_TX_LOOP + description: Set this bit to clear theCH%s_TX_LOOP_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - dim: 4 + dimIncrement: 1 + dimIndex: "4,5,6,7" + name: CH%s_RX_END + description: Set this bit to clear theCH4_RX_END_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - dim: 4 + dimIncrement: 1 + dimIndex: "4,5,6,7" + name: CH%s_RX_ERR + description: Set this bit to clear theCH4_ERR_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: write-only + - dim: 4 + dimIncrement: 1 + dimIndex: "4,5,6,7" + name: CH%s_RX_THR_EVENT + description: Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt. + bitOffset: 24 + bitWidth: 1 + access: write-only + - name: TX_CH3_DMA_ACCESS_FAIL + description: Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt. + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: RX_CH7_DMA_ACCESS_FAIL + description: Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt. + bitOffset: 29 + bitWidth: 1 + access: write-only + - register: + dim: 4 + dimIncrement: 4 + name: CH%sCARRIER_DUTY + description: Channel %s duty cycle configuration register + addressOffset: 128 + size: 32 + resetValue: 4194368 + fields: + - name: CARRIER_LOW + description: "This register is used to configure carrier wave 's low level clock period for CHANNEL%s." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CARRIER_HIGH + description: "This register is used to configure carrier wave 's high level clock period for CHANNEL%s." + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: CH%s_RX_CARRIER_RM + description: Channel %s carrier remove register + addressOffset: 144 + size: 32 + fields: + - name: CARRIER_LOW_THRES + description: The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH%s + 1) for channel %s. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CARRIER_HIGH_THRES + description: The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH%s + 1) for channel %s. + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: CH%s_TX_LIM + description: Channel %s Tx event configuration register + addressOffset: 160 + size: 32 + resetValue: 128 + fields: + - name: TX_LIM + description: This register is used to configure the maximum entries that CHANNEL%s can send out. + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: TX_LOOP_NUM + description: This register is used to configure the maximum loop count when tx_conti_mode is valid. + bitOffset: 9 + bitWidth: 10 + access: read-write + - name: TX_LOOP_CNT_EN + description: This register is the enabled bit for loop count. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: LOOP_COUNT_RESET + description: This register is used to reset the loop count when tx_conti_mode is valid. + bitOffset: 20 + bitWidth: 1 + access: write-only + - name: LOOP_STOP_EN + description: This bit is used to enable the loop send stop function after the loop counter counts to loop number for CHANNEL%s. + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + dim: 4 + dimIncrement: 4 + name: CH%s_RX_LIM + description: Channel %s Rx event configuration register + addressOffset: 176 + size: 32 + resetValue: 128 + fields: + - name: RX_LIM + description: This register is used to configure the maximum entries that CHANNEL%s can receive. + bitOffset: 0 + bitWidth: 9 + access: read-write + - register: + name: SYS_CONF + description: RMT apb configuration register + addressOffset: 192 + size: 32 + resetValue: 83886096 + fields: + - name: APB_FIFO_MASK + description: "1'h1: access memory directly. 1'h0: access memory by FIFO." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MEM_CLK_FORCE_ON + description: Set this bit to enable the clock for RMT memory. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PD + description: Set this bit to power down RMT memory. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PU + description: "1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SCLK_DIV_NUM + description: the integral part of the fractional divisor + bitOffset: 4 + bitWidth: 8 + access: read-write + - name: SCLK_DIV_A + description: the numerator of the fractional part of the fractional divisor + bitOffset: 12 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_B + description: the denominator of the fractional part of the fractional divisor + bitOffset: 18 + bitWidth: 6 + access: read-write + - name: SCLK_SEL + description: "choose the clock source of rmt_sclk. 1:CLK_80Mhz;2:CLK_8MHz; 2:XTAL" + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: SCLK_ACTIVE + description: rmt_sclk switch + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TX_SIM + description: RMT TX synchronous register + addressOffset: 196 + size: 32 + fields: + - name: CH0 + description: Set this bit to enable CHANNEL0 to start sending data synchronously with other enabled channels. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CH1 + description: Set this bit to enable CHANNEL1 to start sending data synchronously with other enabled channels. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CH2 + description: Set this bit to enable CHANNEL2 to start sending data synchronously with other enabled channels. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CH3 + description: Set this bit to enable CHANNEL3 to start sending data synchronously with other enabled channels. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: EN + description: This register is used to enable multiple of channels to start sending data synchronously. + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: REF_CNT_RST + description: RMT clock divider reset register + addressOffset: 200 + size: 32 + fields: + - dim: 8 + dimIncrement: 1 + dimIndex: "0,1,2,3,4,5,6,7" + name: CH%s + description: This register is used to reset the clock divider of CHANNEL%s. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: DATE + description: RMT version register + addressOffset: 204 + size: 32 + resetValue: 34607489 + fields: + - name: DATE + description: This is the version register. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: RNG + description: Hardware Random Number Generator + groupName: RNG + baseAddress: 1610829676 + addressBlock: + - offset: 0 + size: 4 + usage: registers + registers: + - register: + name: DATA + description: Random number data + addressOffset: 272 + size: 32 + access: read-only + - name: RSA + description: RSA (Rivest Shamir Adleman) Accelerator + groupName: RSA + baseAddress: 1610858496 + addressBlock: + - offset: 0 + size: 2100 + usage: registers + interrupt: + - name: RSA + value: 76 + registers: + - register: + dim: 128 + dimIncrement: 4 + name: "M_MEM[%s]" + description: Memory M + addressOffset: 0 + size: 32 + access: write-only + - register: + dim: 128 + dimIncrement: 4 + name: "Z_MEM[%s]" + description: Memory Z + addressOffset: 512 + size: 32 + access: read-write + - register: + dim: 128 + dimIncrement: 4 + name: "Y_MEM[%s]" + description: Memory Y + addressOffset: 1024 + size: 32 + access: write-only + - register: + dim: 128 + dimIncrement: 4 + name: "X_MEM[%s]" + description: Memory X + addressOffset: 1536 + size: 32 + access: write-only + - register: + name: M_PRIME + description: "RSA M' register" + addressOffset: 2048 + size: 32 + fields: + - name: M_PRIME + description: "Stores M'" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: MODE + description: RSA length mode register + addressOffset: 2052 + size: 32 + fields: + - name: MODE + description: Stores the RSA length mode + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: CLEAN + description: RSA clean register + addressOffset: 2056 + size: 32 + fields: + - name: CLEAN + description: The content of this bit is 1 when memories complete initialization. + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: MODEXP_START + description: Modular exponentiation trigger register. + addressOffset: 2060 + size: 32 + fields: + - name: MODEXP_START + description: Set this bit to 1 to start the modular exponentiation. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: MODMULT_START + description: Modular multiplication trigger register. + addressOffset: 2064 + size: 32 + fields: + - name: MODMULT_START + description: Set this bit to 1 to start the modular multiplication + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: MULT_START + description: Normal multiplication trigger register. + addressOffset: 2068 + size: 32 + fields: + - name: MULT_START + description: Set this bit to 1 to start the multiplicaiton. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: IDLE + description: RSA idle register + addressOffset: 2072 + size: 32 + fields: + - name: IDLE + description: The content of this bit is 1 when the RSA accelerator is idle. + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: CLEAR_INTERRUPT + description: RSA interrupt clear register + addressOffset: 2076 + size: 32 + fields: + - name: CLEAR_INTERRUPT + description: set this bit to 1 to clear the RSA interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: CONSTANT_TIME + description: CONSTANT_TIME option control register + addressOffset: 2080 + size: 32 + resetValue: 1 + fields: + - name: CONSTANT_TIME + description: "Controls the CONSTANT_TIME option. 0: acceleration. 1: no acceleration(by default)." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SEARCH_ENABLE + description: SEARCH option enable register + addressOffset: 2084 + size: 32 + fields: + - name: SEARCH_ENABLE + description: "Controls the SEARCH option. 0: no acceleration(by default). 1: acceleration." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SEARCH_POS + description: RSA search position configure register + addressOffset: 2088 + size: 32 + fields: + - name: SEARCH_POS + description: This field is used to configure the starting search position when the acceleration option of SEARCH is used. + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: INTERRUPT_ENA + description: RSA interrupt enable register + addressOffset: 2092 + size: 32 + fields: + - name: INTERRUPT_ENA + description: Set this bit to 1 to enable the RSA interrupt. This option is enabled by default. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: RSA version control register + addressOffset: 2096 + size: 32 + resetValue: 538513969 + fields: + - name: DATE + description: rsa version information + bitOffset: 0 + bitWidth: 30 + access: read-write + - name: RTC_CNTL + description: Real-Time Clock Control + groupName: RTC_CNTL + baseAddress: 1610645504 + addressBlock: + - offset: 0 + size: 348 + usage: registers + interrupt: + - name: RTC_CORE + value: 39 + registers: + - register: + name: OPTIONS0 + description: RTC common configure register + addressOffset: 0 + size: 32 + resetValue: 469803008 + fields: + - name: SW_STALL_APPCPU_C0 + description: "{reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SW_STALL_PROCPU_C0 + description: "{reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: SW_APPCPU_RST + description: APP CPU SW reset + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SW_PROCPU_RST + description: PRO CPU SW reset + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: BB_I2C_FORCE_PD + description: BB_I2C force power down + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BB_I2C_FORCE_PU + description: BB_I2C force power up + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: BBPLL_I2C_FORCE_PD + description: BB_PLL _I2C force power down + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BBPLL_I2C_FORCE_PU + description: BB_PLL_I2C force power up + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: BBPLL_FORCE_PD + description: BB_PLL force power down + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: BBPLL_FORCE_PU + description: BB_PLL force power up + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: XTL_FORCE_PD + description: crystall force power down + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: XTL_FORCE_PU + description: crystall force power up + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: XTL_EN_WAIT + description: wait bias_sleep and current source wakeup + bitOffset: 14 + bitWidth: 4 + access: read-write + - name: XTL_FORCE_ISO + description: No public + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: PLL_FORCE_ISO + description: No public + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: ANALOG_FORCE_ISO + description: No public + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: XTL_FORCE_NOISO + description: No public + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: PLL_FORCE_NOISO + description: No public + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: ANALOG_FORCE_NOISO + description: No public + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_RST + description: digital wrap force reset in deep sleep + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_NORST + description: digital core force no reset in deep sleep + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SW_SYS_RST + description: SW system reset + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: SLP_TIMER0 + description: configure min sleep time + addressOffset: 4 + size: 32 + fields: + - name: SLP_VAL_LO + description: RTC sleep timer low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SLP_TIMER1 + description: configure sleep time hi + addressOffset: 8 + size: 32 + fields: + - name: SLP_VAL_HI + description: RTC sleep timer high 16 bits + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MAIN_TIMER_ALARM_EN + description: timer alarm enable bit + bitOffset: 16 + bitWidth: 1 + access: write-only + - register: + name: TIME_UPDATE + description: update rtc main timer + addressOffset: 12 + size: 32 + fields: + - name: TIMER_SYS_STALL + description: Enable to record system stall time + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: TIMER_XTL_OFF + description: Enable to record 40M XTAL OFF time + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: TIMER_SYS_RST + description: enable to record system reset time + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TIME_UPDATE + description: "Set 1: to update register with RTC timer" + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: TIME_LOW0 + description: read rtc_main timer low bits + addressOffset: 16 + size: 32 + fields: + - name: TIMER_VALUE0_LOW + description: RTC timer low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: TIME_HIGH0 + description: read rtc_main timer high bits + addressOffset: 20 + size: 32 + fields: + - name: TIMER_VALUE0_HIGH + description: RTC timer high 16 bits + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: STATE0 + description: configure chip sleep + addressOffset: 24 + size: 32 + fields: + - name: SW_CPU_INT + description: rtc software interrupt to main cpu + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SLP_REJECT_CAUSE_CLR + description: clear rtc sleep reject cause + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: APB2RTC_BRIDGE_SEL + description: "1: APB to RTC using bridge, 0: APB to RTC using sync" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SDIO_ACTIVE_IND + description: SDIO active indication + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SLP_WAKEUP + description: leep wakeup bit + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SLP_REJECT + description: leep reject bit + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SLEEP_EN + description: sleep enable bit + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TIMER1 + description: rtc state wait time + addressOffset: 28 + size: 32 + resetValue: 672400387 + fields: + - name: CPU_STALL_EN + description: CPU stall enable bit + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CPU_STALL_WAIT + description: CPU stall wait cycles in fast_clk_rtc + bitOffset: 1 + bitWidth: 5 + access: read-write + - name: CK8M_WAIT + description: CK8M wait cycles in slow_clk_rtc + bitOffset: 6 + bitWidth: 8 + access: read-write + - name: XTL_BUF_WAIT + description: XTAL wait cycles in slow_clk_rtc + bitOffset: 14 + bitWidth: 10 + access: read-write + - name: PLL_BUF_WAIT + description: PLL wait cycles in slow_clk_rtc + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: TIMER2 + description: rtc monitor state delay time + addressOffset: 32 + size: 32 + resetValue: 17301504 + fields: + - name: ULPCP_TOUCH_START_WAIT + description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work + bitOffset: 15 + bitWidth: 9 + access: read-write + - name: MIN_TIME_CK8M_OFF + description: minimal cycles in slow_clk_rtc for CK8M in power down state + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: TIMER3 + description: No public + addressOffset: 36 + size: 32 + resetValue: 336988680 + fields: + - name: WIFI_WAIT_TIMER + description: No public + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: WIFI_POWERUP_TIMER + description: No public + bitOffset: 9 + bitWidth: 7 + access: read-write + - name: BT_WAIT_TIMER + description: No public + bitOffset: 16 + bitWidth: 9 + access: read-write + - name: BT_POWERUP_TIMER + description: No public + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: TIMER4 + description: No public + addressOffset: 40 + size: 32 + resetValue: 270535176 + fields: + - name: WAIT_TIMER + description: No public + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: POWERUP_TIMER + description: No public + bitOffset: 9 + bitWidth: 7 + access: read-write + - name: DG_WRAP_WAIT_TIMER + description: No public + bitOffset: 16 + bitWidth: 9 + access: read-write + - name: DG_WRAP_POWERUP_TIMER + description: No public + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: TIMER5 + description: configure min sleep time + addressOffset: 44 + size: 32 + resetValue: 32768 + fields: + - name: MIN_SLP_VAL + description: minimal sleep cycles in slow_clk_rtc + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: TIMER6 + description: No public + addressOffset: 48 + size: 32 + resetValue: 270535176 + fields: + - name: CPU_TOP_WAIT_TIMER + description: No public + bitOffset: 0 + bitWidth: 9 + access: read-write + - name: CPU_TOP_POWERUP_TIMER + description: No public + bitOffset: 9 + bitWidth: 7 + access: read-write + - name: DG_PERI_WAIT_TIMER + description: No public + bitOffset: 16 + bitWidth: 9 + access: read-write + - name: DG_PERI_POWERUP_TIMER + description: No public + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: ANA_CONF + description: analog configure register + addressOffset: 52 + size: 32 + resetValue: 4456448 + fields: + - name: I2C_RESET_POR_FORCE_PD + description: force down I2C_RESET_POR + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: I2C_RESET_POR_FORCE_PU + description: force on I2C_RESET_POR + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: GLITCH_RST_EN + description: enable clk glitch + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SAR_I2C_PU + description: PLLA force power up + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: ANALOG_TOP_ISO_SLEEP + description: PLLA force power down + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: ANALOG_TOP_ISO_MONITOR + description: PLLA force power up + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: BBPLL_CAL_SLP_START + description: start BBPLL calibration during sleep + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PVTMON_PU + description: "1: PVTMON power up, otherwise power down" + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TXRF_I2C_PU + description: "1: TXRF_I2C power up, otherwise power down" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RFRX_PBUS_PU + description: "1: RFRX_PBUS power up, otherwise power down" + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CKGEN_I2C_PU + description: "1: CKGEN_I2C power up, otherwise power down" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: PLL_I2C_PU + description: power on pll i2c + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RESET_STATE + description: get reset state + addressOffset: 56 + size: 32 + resetValue: 12288 + fields: + - name: RESET_CAUSE_PROCPU + description: reset cause of PRO CPU + bitOffset: 0 + bitWidth: 6 + access: read-only + - name: RESET_CAUSE_APPCPU + description: reset cause of APP CPU + bitOffset: 6 + bitWidth: 6 + access: read-only + - name: APPCPU_STAT_VECTOR_SEL + description: APP CPU state vector sel + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PROCPU_STAT_VECTOR_SEL + description: PRO CPU state vector sel + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: RESET_FLAG_PROCPU + description: PRO CPU reset_flag + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: RESET_FLAG_APPCPU + description: APP CPU reset flag + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: RESET_FLAG_PROCPU_CLR + description: clear PRO CPU reset_flag + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: RESET_FLAG_APPCPU_CLR + description: clear APP CPU reset flag + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: APPCPU_OCD_HALT_ON_RESET + description: APPCPU OcdHaltOnReset + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: PROCPU_OCD_HALT_ON_RESET + description: PROCPU OcdHaltOnReset + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RESET_FLAG_JTAG_PROCPU + description: jtag reset flag + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: RESET_FLAG_JTAG_APPCPU + description: jtag reset flag + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: RESET_FLAG_JTAG_PROCPU_CLR + description: clear jtag reset flag + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: RESET_FLAG_JTAG_APPCPU_CLR + description: clear jtag reset flag + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: APP_DRESET_MASK + description: bypass cpu1 dreset + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PRO_DRESET_MASK + description: bypass cpu0 dreset + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: WAKEUP_STATE + description: configure wakeup state + addressOffset: 60 + size: 32 + resetValue: 393216 + fields: + - name: WAKEUP_ENA + description: wakeup enable bitmap + bitOffset: 15 + bitWidth: 17 + access: read-write + - register: + name: INT_ENA_RTC + description: configure rtc interrupt register + addressOffset: 64 + size: 32 + fields: + - name: SLP_WAKEUP_INT_ENA + description: enable sleep wakeup interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SLP_REJECT_INT_ENA + description: enable sleep reject interrupt + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SDIO_IDLE_INT_ENA + description: enable SDIO idle interrupt + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: WDT_INT_ENA + description: enable RTC WDT interrupt + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TOUCH_SCAN_DONE_INT_ENA + description: enable touch scan done interrupt + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ULP_CP_INT_ENA + description: enable ULP-coprocessor interrupt + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TOUCH_DONE_INT_ENA + description: enable touch done interrupt + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TOUCH_ACTIVE_INT_ENA + description: enable touch active interrupt + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TOUCH_INACTIVE_INT_ENA + description: enable touch inactive interrupt + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_INT_ENA + description: enable brown out interrupt + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: MAIN_TIMER_INT_ENA + description: enable RTC main timer interrupt + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SARADC1_INT_ENA + description: enable saradc1 interrupt + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TSENS_INT_ENA + description: enable tsens interrupt + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: COCPU_INT_ENA + description: enable riscV cocpu interrupt + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SARADC2_INT_ENA + description: enable saradc2 interrupt + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SWD_INT_ENA + description: enable super watch dog interrupt + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: XTAL32K_DEAD_INT_ENA + description: enable xtal32k_dead interrupt + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: COCPU_TRAP_INT_ENA + description: enable cocpu trap interrupt + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: TOUCH_TIMEOUT_INT_ENA + description: enable touch timeout interrupt + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: GLITCH_DET_INT_ENA + description: enbale gitch det interrupt + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: TOUCH_APPROACH_LOOP_DONE_INT_ENA + description: touch approach mode loop interrupt + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW_RTC + description: rtc interrupt register + addressOffset: 68 + size: 32 + fields: + - name: SLP_WAKEUP_INT_RAW + description: sleep wakeup interrupt raw + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SLP_REJECT_INT_RAW + description: sleep reject interrupt raw + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SDIO_IDLE_INT_RAW + description: SDIO idle interrupt raw + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: WDT_INT_RAW + description: RTC WDT interrupt raw + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TOUCH_SCAN_DONE_INT_RAW + description: enable touch scan done interrupt raw + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ULP_CP_INT_RAW + description: ULP-coprocessor interrupt raw + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: TOUCH_DONE_INT_RAW + description: touch interrupt raw + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TOUCH_ACTIVE_INT_RAW + description: touch active interrupt raw + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TOUCH_INACTIVE_INT_RAW + description: touch inactive interrupt raw + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: BROWN_OUT_INT_RAW + description: brown out interrupt raw + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: MAIN_TIMER_INT_RAW + description: RTC main timer interrupt raw + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SARADC1_INT_RAW + description: saradc1 interrupt raw + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TSENS_INT_RAW + description: tsens interrupt raw + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: COCPU_INT_RAW + description: riscV cocpu interrupt raw + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SARADC2_INT_RAW + description: saradc2 interrupt raw + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SWD_INT_RAW + description: super watch dog interrupt raw + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: XTAL32K_DEAD_INT_RAW + description: xtal32k dead detection interrupt raw + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: COCPU_TRAP_INT_RAW + description: cocpu trap interrupt raw + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: TOUCH_TIMEOUT_INT_RAW + description: touch timeout interrupt raw + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: GLITCH_DET_INT_RAW + description: glitch_det_interrupt_raw + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: TOUCH_APPROACH_LOOP_DONE_INT_RAW + description: touch approach mode loop interrupt raw + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: INT_ST_RTC + description: rtc interrupt register + addressOffset: 72 + size: 32 + fields: + - name: SLP_WAKEUP_INT_ST + description: sleep wakeup interrupt state + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SLP_REJECT_INT_ST + description: sleep reject interrupt state + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SDIO_IDLE_INT_ST + description: SDIO idle interrupt state + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: WDT_INT_ST + description: RTC WDT interrupt state + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TOUCH_SCAN_DONE_INT_ST + description: enable touch scan done interrupt raw + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ULP_CP_INT_ST + description: ULP-coprocessor interrupt state + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: TOUCH_DONE_INT_ST + description: touch done interrupt state + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TOUCH_ACTIVE_INT_ST + description: touch active interrupt state + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: TOUCH_INACTIVE_INT_ST + description: touch inactive interrupt state + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: BROWN_OUT_INT_ST + description: brown out interrupt state + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: MAIN_TIMER_INT_ST + description: RTC main timer interrupt state + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SARADC1_INT_ST + description: saradc1 interrupt state + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TSENS_INT_ST + description: tsens interrupt state + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: COCPU_INT_ST + description: riscV cocpu interrupt state + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SARADC2_INT_ST + description: saradc2 interrupt state + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SWD_INT_ST + description: super watch dog interrupt state + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: XTAL32K_DEAD_INT_ST + description: xtal32k dead detection interrupt state + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: COCPU_TRAP_INT_ST + description: cocpu trap interrupt state + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: TOUCH_TIMEOUT_INT_ST + description: Touch timeout interrupt state + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: GLITCH_DET_INT_ST + description: glitch_det_interrupt state + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: TOUCH_APPROACH_LOOP_DONE_INT_ST + description: touch approach mode loop interrupt state + bitOffset: 20 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR_RTC + description: rtc interrupt register + addressOffset: 76 + size: 32 + fields: + - name: SLP_WAKEUP_INT_CLR + description: Clear sleep wakeup interrupt state + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SLP_REJECT_INT_CLR + description: Clear sleep reject interrupt state + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SDIO_IDLE_INT_CLR + description: Clear SDIO idle interrupt state + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: WDT_INT_CLR + description: Clear RTC WDT interrupt state + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TOUCH_SCAN_DONE_INT_CLR + description: clear touch scan done interrupt raw + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: ULP_CP_INT_CLR + description: Clear ULP-coprocessor interrupt state + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TOUCH_DONE_INT_CLR + description: Clear touch done interrupt state + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TOUCH_ACTIVE_INT_CLR + description: Clear touch active interrupt state + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: TOUCH_INACTIVE_INT_CLR + description: Clear touch inactive interrupt state + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: BROWN_OUT_INT_CLR + description: Clear brown out interrupt state + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: MAIN_TIMER_INT_CLR + description: Clear RTC main timer interrupt state + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SARADC1_INT_CLR + description: Clear saradc1 interrupt state + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TSENS_INT_CLR + description: Clear tsens interrupt state + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: COCPU_INT_CLR + description: Clear riscV cocpu interrupt state + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SARADC2_INT_CLR + description: Clear saradc2 interrupt state + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SWD_INT_CLR + description: Clear super watch dog interrupt state + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: XTAL32K_DEAD_INT_CLR + description: Clear RTC WDT interrupt state + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: COCPU_TRAP_INT_CLR + description: Clear cocpu trap interrupt state + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: TOUCH_TIMEOUT_INT_CLR + description: Clear touch timeout interrupt state + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: GLITCH_DET_INT_CLR + description: Clear glitch det interrupt state + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: TOUCH_APPROACH_LOOP_DONE_INT_CLR + description: cleartouch approach mode loop interrupt state + bitOffset: 20 + bitWidth: 1 + access: write-only + - register: + name: STORE0 + description: Reserved register + addressOffset: 80 + size: 32 + fields: + - name: SCRATCH0 + description: Reserved register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE1 + description: Reserved register + addressOffset: 84 + size: 32 + fields: + - name: SCRATCH1 + description: Reserved register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE2 + description: Reserved register + addressOffset: 88 + size: 32 + fields: + - name: SCRATCH2 + description: Reserved register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE3 + description: Reserved register + addressOffset: 92 + size: 32 + fields: + - name: SCRATCH3 + description: Reserved register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: EXT_XTL_CONF + description: Reserved register + addressOffset: 96 + size: 32 + resetValue: 420992 + fields: + - name: XTAL32K_WDT_EN + description: xtal 32k watch dog enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: XTAL32K_WDT_CLK_FO + description: xtal 32k watch dog clock force on + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: XTAL32K_WDT_RESET + description: xtal 32k watch dog sw reset + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: XTAL32K_EXT_CLK_FO + description: xtal 32k external xtal clock force on + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: XTAL32K_AUTO_BACKUP + description: xtal 32k switch to back up clock when xtal is dead + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: XTAL32K_AUTO_RESTART + description: xtal 32k restart xtal when xtal is dead + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: XTAL32K_AUTO_RETURN + description: xtal 32k switch back xtal when xtal is restarted + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: XTAL32K_XPD_FORCE + description: Xtal 32k xpd control by sw or fsm + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: ENCKINIT_XTAL_32K + description: apply an internal clock to help xtal 32k to start + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DBUF_XTAL_32K + description: "0: single-end buffer 1: differential buffer" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DGM_XTAL_32K + description: xtal_32k gm control + bitOffset: 10 + bitWidth: 3 + access: read-write + - name: DRES_XTAL_32K + description: DRES_XTAL_32K + bitOffset: 13 + bitWidth: 3 + access: read-write + - name: XPD_XTAL_32K + description: XPD_XTAL_32K + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DAC_XTAL_32K + description: DAC_XTAL_32K + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: WDT_STATE + description: state of 32k_wdt + bitOffset: 20 + bitWidth: 3 + access: read-only + - name: XTAL32K_GPIO_SEL + description: "XTAL_32K sel. 0: external XTAL_32K, 1: CLK from RTC pad X32P_C" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: XTL_EXT_CTR_LV + description: "0: power down XTAL at high level, 1: power down XTAL at low level" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: XTL_EXT_CTR_EN + description: Reserved register + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: EXT_WAKEUP_CONF + description: ext wakeup configure + addressOffset: 100 + size: 32 + fields: + - name: GPIO_WAKEUP_FILTER + description: enable filter for gpio wakeup event + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: EXT_WAKEUP0_LV + description: "0: external wakeup at low level, 1: external wakeup at high level" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: EXT_WAKEUP1_LV + description: "0: external wakeup at low level, 1: external wakeup at high level" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SLP_REJECT_CONF + description: reject sleep register + addressOffset: 104 + size: 32 + fields: + - name: SLEEP_REJECT_ENA + description: sleep reject enable + bitOffset: 12 + bitWidth: 18 + access: read-write + - name: LIGHT_SLP_REJECT_EN + description: enable reject for light sleep + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DEEP_SLP_REJECT_EN + description: enable reject for deep sleep + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CPU_PERIOD_CONF + description: conigure cpu freq + addressOffset: 108 + size: 32 + fields: + - name: CPUSEL_CONF + description: CPU sel option + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CPUPERIOD_SEL + description: conigure cpu freq + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: SDIO_ACT_CONF + description: No public + addressOffset: 112 + size: 32 + fields: + - name: SDIO_ACT_DNUM + description: No public + bitOffset: 22 + bitWidth: 10 + access: read-write + - register: + name: CLK_CONF + description: configure clock register + addressOffset: 116 + size: 32 + resetValue: 290992668 + fields: + - name: EFUSE_CLK_FORCE_GATING + description: force efuse clk gating + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EFUSE_CLK_FORCE_NOGATING + description: force efuse clk nogating + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CK8M_DIV_SEL_VLD + description: "used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel, then set vld to actually switch the clk" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CK8M_DIV + description: "CK8M_D256_OUT divider. 00: div128, 01: div256, 10: div512, 11: div1024." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: ENB_CK8M + description: disable CK8M and CK8M_D256_OUT + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: ENB_CK8M_DIV + description: "1: CK8M_D256_OUT is actually CK8M, 0: CK8M_D256_OUT is CK8M divided by 256" + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DIG_XTAL32K_EN + description: enable CK_XTAL_32K for digital core (no relationship with RTC core) + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DIG_CLK8M_D256_EN + description: enable CK8M_D256_OUT for digital core (no relationship with RTC core) + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DIG_CLK8M_EN + description: enable CK8M for digital core (no relationship with RTC core) + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CK8M_DIV_SEL + description: divider = reg_ck8m_div_sel + 1 + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: XTAL_FORCE_NOGATING + description: XTAL force no gating during sleep + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CK8M_FORCE_NOGATING + description: CK8M force no gating during sleep + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CK8M_DFREQ + description: CK8M_DFREQ + bitOffset: 17 + bitWidth: 8 + access: read-write + - name: CK8M_FORCE_PD + description: CK8M force power down + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: CK8M_FORCE_PU + description: CK8M force power up + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: XTAL_GLOBAL_FORCE_GATING + description: force global xtal gating + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: XTAL_GLOBAL_FORCE_NOGATING + description: force global xtal no gating + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: FAST_CLK_RTC_SEL + description: "fast_clk_rtc sel. 0: XTAL div 4, 1: CK8M" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ANA_CLK_RTC_SEL + description: select slow clock + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: SLOW_CLK_CONF + description: configure slow clk + addressOffset: 120 + size: 32 + resetValue: 4194304 + fields: + - name: ANA_CLK_DIV_VLD + description: "used to sync div bus. clear vld before set reg_rtc_ana_clk_div, then set vld to actually switch the clk" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: ANA_CLK_DIV + description: rtc clk div + bitOffset: 23 + bitWidth: 8 + access: read-write + - name: SLOW_CLK_NEXT_EDGE + description: No public + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SDIO_CONF + description: configure flash power + addressOffset: 124 + size: 32 + resetValue: 179355146 + fields: + - name: SDIO_TIMER_TARGET + description: timer count to apply reg_sdio_dcap after sdio power on + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SDIO_DTHDRV + description: "Tieh = 1 mode drive ability. Initially set to 0 to limit charge current, set to 3 after several us." + bitOffset: 9 + bitWidth: 2 + access: read-write + - name: SDIO_DCAP + description: ability to prevent LDO from overshoot + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: SDIO_INITI + description: "add resistor from ldo output to ground. 0: no res, 1: 6k,2:4k,3:2k" + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: SDIO_EN_INITI + description: "0 to set init[1:0]=0" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SDIO_DCURLIM + description: tune current limit threshold when tieh = 0. About 800mA/(8+d) + bitOffset: 16 + bitWidth: 3 + access: read-write + - name: SDIO_MODECURLIM + description: select current limit mode + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SDIO_ENCURLIM + description: enable current limit + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SDIO_REG_PD_EN + description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SDIO_FORCE + description: "1: use SW option to control SDIO_REG, 0: use state machine" + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SDIO_TIEH + description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1 + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: REG1P8_READY + description: read only register for REG1P8_READY + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: DREFL_SDIO + description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1 + bitOffset: 25 + bitWidth: 2 + access: read-write + - name: DREFM_SDIO + description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1 + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: DREFH_SDIO + description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1 + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: XPD_SDIO + description: power on flash regulator + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: BIAS_CONF + description: No public + addressOffset: 128 + size: 32 + resetValue: 67584 + fields: + - name: BIAS_BUF_IDLE + description: No public + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: BIAS_BUF_WAKE + description: No public + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: BIAS_BUF_DEEP_SLP + description: No public + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: BIAS_BUF_MONITOR + description: No public + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: PD_CUR_DEEP_SLP + description: xpd cur when rtc in sleep_state + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PD_CUR_MONITOR + description: xpd cur when rtc in monitor state + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: BIAS_SLEEP_DEEP_SLP + description: bias_sleep when rtc in sleep_state + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: BIAS_SLEEP_MONITOR + description: bias_sleep when rtc in monitor state + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: DBG_ATTEN_DEEP_SLP + description: DBG_ATTEN when rtc in sleep state + bitOffset: 18 + bitWidth: 4 + access: read-write + - name: DBG_ATTEN_MONITOR + description: DBG_ATTEN when rtc in monitor state + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: DBG_ATTEN_WAKEUP + description: No public + bitOffset: 26 + bitWidth: 4 + access: read-write + - register: + name: RTC + description: configure rtc regulator + addressOffset: 132 + size: 32 + resetValue: 2684354560 + fields: + - name: DIG_REG_CAL_EN + description: enable dig regulator cali + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SCK_DCAP + description: SCK_DCAP + bitOffset: 14 + bitWidth: 8 + access: read-write + - name: DBOOST_FORCE_PD + description: RTC_DBOOST force power down + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DBOOST_FORCE_PU + description: RTC_DBOOST force power up + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: REGULATOR_FORCE_PD + description: RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower ) + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: REGULATOR_FORCE_PU + description: RTC_REG force power on (for RTC_REG power down means decrease the voltage to 0.8v or lower ) + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: PWC + description: configure rtc power + addressOffset: 136 + size: 32 + resetValue: 2341 + fields: + - name: FASTMEM_FORCE_NOISO + description: Fast RTC memory force no ISO + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FASTMEM_FORCE_ISO + description: Fast RTC memory force ISO + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SLOWMEM_FORCE_NOISO + description: RTC memory force no ISO + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLOWMEM_FORCE_ISO + description: RTC memory force ISO + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FORCE_ISO + description: rtc_peri force ISO + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FORCE_NOISO + description: rtc_peri force no ISO + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FASTMEM_FOLW_CPU + description: "1: Fast RTC memory PD following CPU, 0: fast RTC memory PD following RTC state machine" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FASTMEM_FORCE_LPD + description: Fast RTC memory force PD + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FASTMEM_FORCE_LPU + description: Fast RTC memory force no PD + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLOWMEM_FOLW_CPU + description: "1: RTC memory PD following CPU, 0: RTC memory PD following RTC state machine" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLOWMEM_FORCE_LPD + description: RTC memory force PD + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLOWMEM_FORCE_LPU + description: RTC memory force no PD + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FORCE_PD + description: rtc_peri force power down + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: FORCE_PU + description: rtc_peri force power up + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PD_EN + description: enable power down rtc_peri in sleep + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: PAD_FORCE_HOLD + description: rtc pad force hold + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + name: REGULATOR_DRV_CTRL + description: No public + addressOffset: 140 + size: 32 + fields: + - name: REGULATOR_DRV_B_MONITOR + description: No public + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: REGULATOR_DRV_B_SLP + description: No public + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: DG_VDD_DRV_B_SLP + description: No public + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: DG_VDD_DRV_B_MONITOR + description: No public + bitOffset: 20 + bitWidth: 8 + access: read-write + - register: + name: DIG_PWC + description: configure digital power + addressOffset: 144 + size: 32 + resetValue: 5525520 + fields: + - name: LSLP_MEM_FORCE_PD + description: memories in digital core force PD in sleep + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: LSLP_MEM_FORCE_PU + description: memories in digital core force no PD in sleep + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: BT_FORCE_PD + description: internal SRAM 2 force power down + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: BT_FORCE_PU + description: internal SRAM 2 force power up + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DG_PERI_FORCE_PD + description: internal SRAM 3 force power down + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DG_PERI_FORCE_PU + description: internal SRAM 3 force power up + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: WIFI_FORCE_PD + description: wifi force power down + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: WIFI_FORCE_PU + description: wifi force power up + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_PD + description: digital core force power down + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_PU + description: digital core force power up + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CPU_TOP_FORCE_PD + description: digital dcdc force power down + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CPU_TOP_FORCE_PU + description: digital dcdc force power up + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: BT_PD_EN + description: enable power down internal SRAM 2 in sleep + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: DG_PERI_PD_EN + description: enable power down internal SRAM 3 in sleep + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: CPU_TOP_PD_EN + description: enable power down internal SRAM 4 in sleep + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: WIFI_PD_EN + description: enable power down wifi in sleep + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DG_WRAP_PD_EN + description: enable power down all digital logic + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DIG_ISO + description: congigure digital power isolation + addressOffset: 148 + size: 32 + resetValue: 2860535936 + fields: + - name: FORCE_OFF + description: No public + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FORCE_ON + description: No public + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DG_PAD_AUTOHOLD + description: read only register to indicate digital pad auto-hold status + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: CLR_DG_PAD_AUTOHOLD + description: wtite only register to clear digital pad auto-hold + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: DG_PAD_AUTOHOLD_EN + description: digital pad enable auto-hold + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DG_PAD_FORCE_NOISO + description: digital pad force no ISO + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DG_PAD_FORCE_ISO + description: digital pad force ISO + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DG_PAD_FORCE_UNHOLD + description: digital pad force un-hold + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DG_PAD_FORCE_HOLD + description: digital pad force hold + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: BT_FORCE_ISO + description: internal SRAM 2 force ISO + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: BT_FORCE_NOISO + description: internal SRAM 2 force no ISO + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: DG_PERI_FORCE_ISO + description: internal SRAM 3 force ISO + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: DG_PERI_FORCE_NOISO + description: internal SRAM 3 force no ISO + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: CPU_TOP_FORCE_ISO + description: internal SRAM 4 force ISO + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CPU_TOP_FORCE_NOISO + description: internal SRAM 4 force no ISO + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: WIFI_FORCE_ISO + description: wifi force ISO + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: WIFI_FORCE_NOISO + description: wifi force no ISO + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_ISO + description: digital core force ISO + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DG_WRAP_FORCE_NOISO + description: digita core force no ISO + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: WDTCONFIG0 + description: configure rtc watch dog + addressOffset: 152 + size: 32 + resetValue: 78356 + fields: + - name: WDT_CHIP_RESET_WIDTH + description: chip reset siginal pulse width + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: WDT_CHIP_RESET_EN + description: wdt reset whole chip enable + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: WDT_PAUSE_IN_SLP + description: pause WDT in sleep + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: WDT_APPCPU_RESET_EN + description: enable WDT reset APP CPU + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: WDT_PROCPU_RESET_EN + description: enable WDT reset PRO CPU + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: WDT_FLASHBOOT_MOD_EN + description: enable WDT in flash boot + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: WDT_SYS_RESET_LENGTH + description: system reset counter length + bitOffset: 13 + bitWidth: 3 + access: read-write + - name: WDT_CPU_RESET_LENGTH + description: CPU reset counter length + bitOffset: 16 + bitWidth: 3 + access: read-write + - name: WDT_STG3 + description: "1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en" + bitOffset: 19 + bitWidth: 3 + access: read-write + - name: WDT_STG2 + description: "1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en" + bitOffset: 22 + bitWidth: 3 + access: read-write + - name: WDT_STG1 + description: "1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en" + bitOffset: 25 + bitWidth: 3 + access: read-write + - name: WDT_STG0 + description: "1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: RTC reset stage en" + bitOffset: 28 + bitWidth: 3 + access: read-write + - name: WDT_EN + description: enable rtc watch dog + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: WDTCONFIG1 + description: stage0 hold time + addressOffset: 156 + size: 32 + resetValue: 200000 + fields: + - name: WDT_STG0_HOLD + description: stage0 hold time + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG2 + description: stage1 hold time + addressOffset: 160 + size: 32 + resetValue: 80000 + fields: + - name: WDT_STG1_HOLD + description: stage1 hold time + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG3 + description: stage2 hold time + addressOffset: 164 + size: 32 + resetValue: 4095 + fields: + - name: WDT_STG2_HOLD + description: stage2 hold time + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG4 + description: stage3 hold time + addressOffset: 168 + size: 32 + resetValue: 4095 + fields: + - name: WDT_STG3_HOLD + description: stage3 hold time + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTFEED + description: rtc wdt feed + addressOffset: 172 + size: 32 + fields: + - name: WDT_FEED + description: rtc wdt feed + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: WDTWPROTECT + description: configure rtc watch dog + addressOffset: 176 + size: 32 + resetValue: 1356348065 + fields: + - name: WDT_WKEY + description: rtc watch dog key + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SWD_CONF + description: congfigure super watch dog + addressOffset: 180 + size: 32 + resetValue: 78643200 + fields: + - name: SWD_RESET_FLAG + description: swd reset flag + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SWD_FEED_INT + description: swd interrupt for feeding + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SWD_BYPASS_RST + description: bypass super watch dog reset + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SWD_SIGNAL_WIDTH + description: adjust signal width send to swd + bitOffset: 18 + bitWidth: 10 + access: read-write + - name: SWD_RST_FLAG_CLR + description: reset swd reset flag + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: SWD_FEED + description: Sw feed swd + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: SWD_DISABLE + description: disabel SWD + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SWD_AUTO_FEED_EN + description: automatically feed swd when int comes + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SWD_WPROTECT + description: super watch dog key + addressOffset: 184 + size: 32 + resetValue: 2401055018 + fields: + - name: SWD_WKEY + description: super watch dog key + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SW_CPU_STALL + description: configure cpu stall by sw + addressOffset: 188 + size: 32 + fields: + - name: SW_STALL_APPCPU_C1 + description: "{reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU" + bitOffset: 20 + bitWidth: 6 + access: read-write + - name: SW_STALL_PROCPU_C1 + description: "{reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU" + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: STORE4 + description: reserved register + addressOffset: 192 + size: 32 + fields: + - name: SCRATCH4 + description: reserved register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE5 + description: reserved register + addressOffset: 196 + size: 32 + fields: + - name: SCRATCH5 + description: reserved register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE6 + description: reserved register + addressOffset: 200 + size: 32 + fields: + - name: SCRATCH6 + description: reserved register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: STORE7 + description: reserved register + addressOffset: 204 + size: 32 + fields: + - name: SCRATCH7 + description: reserved register + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LOW_POWER_ST + description: reserved register + addressOffset: 208 + size: 32 + fields: + - name: XPD_ROM0 + description: rom0 power down + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: XPD_DIG_DCDC + description: External DCDC power down + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: PERI_ISO + description: rtc peripheral iso + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: XPD_RTC_PERI + description: rtc peripheral power down + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: WIFI_ISO + description: wifi iso + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: XPD_WIFI + description: wifi wrap power down + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: DIG_ISO + description: digital wrap iso + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: XPD_DIG + description: digital wrap power down + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: TOUCH_STATE_START + description: touch should start to work + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: TOUCH_STATE_SWITCH + description: touch is about to working. Switch rtc main state + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: TOUCH_STATE_SLP + description: touch is in sleep state + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TOUCH_STATE_DONE + description: touch is done + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: COCPU_STATE_START + description: ulp/cocpu should start to work + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: COCPU_STATE_SWITCH + description: ulp/cocpu is about to working. Switch rtc main state + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: COCPU_STATE_SLP + description: ulp/cocpu is in sleep state + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: COCPU_STATE_DONE + description: ulp/cocpu is done + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: MAIN_STATE_XTAL_ISO + description: no use any more + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: MAIN_STATE_PLL_ON + description: rtc main state machine is in states that pll should be running + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: RDY_FOR_WAKEUP + description: rtc is ready to receive wake up trigger from wake up source + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: MAIN_STATE_WAIT_END + description: rtc main state machine has been waited for some cycles + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: IN_WAKEUP_STATE + description: rtc main state machine is in the states of wakeup process + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: IN_LOW_POWER_STATE + description: rtc main state machine is in the states of low power + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: MAIN_STATE_IN_WAIT_8M + description: rtc main state machine is in wait 8m state + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: MAIN_STATE_IN_WAIT_PLL + description: rtc main state machine is in wait pll state + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: MAIN_STATE_IN_WAIT_XTL + description: rtc main state machine is in wait xtal state + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: MAIN_STATE_IN_SLP + description: rtc main state machine is in sleep state + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: MAIN_STATE_IN_IDLE + description: rtc main state machine is in idle state + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: MAIN_STATE + description: rtc main state machine status + bitOffset: 28 + bitWidth: 4 + access: read-only + - register: + name: DIAG0 + description: No public + addressOffset: 212 + size: 32 + fields: + - name: LOW_POWER_DIAG1 + description: No public + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: PAD_HOLD + description: rtc pad hold configure + addressOffset: 216 + size: 32 + fields: + - name: TOUCH_PAD0_HOLD + description: hold rtc pad0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD1_HOLD + description: hold rtc pad-1 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD2_HOLD + description: hold rtc pad-2 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD3_HOLD + description: hold rtc pad-3 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD4_HOLD + description: hold rtc pad-4 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD5_HOLD + description: hold rtc pad-5 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD6_HOLD + description: hold rtc pad-6 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD7_HOLD + description: hold rtc pad-7 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD8_HOLD + description: hold rtc pad-8 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD9_HOLD + description: hold rtc pad-9 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD10_HOLD + description: hold rtc pad-10 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD11_HOLD + description: hold rtc pad-11 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD12_HOLD + description: hold rtc pad-12 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD13_HOLD + description: hold rtc pad-13 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TOUCH_PAD14_HOLD + description: hold rtc pad-14 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: X32P_HOLD + description: hold rtc pad-15 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: X32N_HOLD + description: hold rtc pad-16 + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PDAC1_HOLD + description: hold rtc pad-17 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: PDAC2_HOLD + description: hold rtc pad-18 + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: PAD19_HOLD + description: hold rtc pad-19 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PAD20_HOLD + description: hold rtc pad-20 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: PAD21_HOLD + description: hold rtc pad-21 + bitOffset: 21 + bitWidth: 1 + access: read-write + - register: + name: DIG_PAD_HOLD + description: configure digtal pad hold + addressOffset: 220 + size: 32 + fields: + - name: DIG_PAD_HOLD + description: configure digtal pad hold + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: EXT_WAKEUP1 + description: configure ext1 wakeup + addressOffset: 224 + size: 32 + fields: + - name: EXT_WAKEUP1_SEL + description: Bitmap to select RTC pads for ext wakeup1 + bitOffset: 0 + bitWidth: 22 + access: read-write + - name: EXT_WAKEUP1_STATUS_CLR + description: clear ext wakeup1 status + bitOffset: 22 + bitWidth: 1 + access: write-only + - register: + name: EXT_WAKEUP1_STATUS + description: check ext wakeup1 status + addressOffset: 228 + size: 32 + fields: + - name: EXT_WAKEUP1_STATUS + description: ext wakeup1 status + bitOffset: 0 + bitWidth: 22 + access: read-only + - register: + name: BROWN_OUT + description: congfigure brownout + addressOffset: 232 + size: 32 + resetValue: 1140785168 + fields: + - name: BROWN_OUT_INT_WAIT + description: brown out interrupt wait cycles + bitOffset: 4 + bitWidth: 10 + access: read-write + - name: BROWN_OUT_CLOSE_FLASH_ENA + description: enable close flash when brown out happens + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_PD_RF_ENA + description: enable power down RF when brown out happens + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_RST_WAIT + description: brown out reset wait cycles + bitOffset: 16 + bitWidth: 10 + access: read-write + - name: BROWN_OUT_RST_ENA + description: enable brown out reset + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_RST_SEL + description: "1: 4-pos reset, 0: sys_reset" + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_ANA_RST_EN + description: enable brown out reset en + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_CNT_CLR + description: clear brown out counter + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: BROWN_OUT_ENA + description: enable brown out + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DET + description: get brown out detect + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: TIME_LOW1 + description: RTC timer low 32 bits + addressOffset: 236 + size: 32 + fields: + - name: TIMER_VALUE1_LOW + description: RTC timer low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: TIME_HIGH1 + description: RTC timer high 16 bits + addressOffset: 240 + size: 32 + fields: + - name: TIMER_VALUE1_HIGH + description: RTC timer high 16 bits + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: XTAL32K_CLK_FACTOR + description: xtal 32k watch dog backup clock factor + addressOffset: 244 + size: 32 + fields: + - name: XTAL32K_CLK_FACTOR + description: xtal 32k watch dog backup clock factor + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: XTAL32K_CONF + description: configure xtal32k + addressOffset: 248 + size: 32 + resetValue: 267386880 + fields: + - name: XTAL32K_RETURN_WAIT + description: cycles to wait to return noral xtal 32k + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: XTAL32K_RESTART_WAIT + description: cycles to wait to repower on xtal 32k + bitOffset: 4 + bitWidth: 16 + access: read-write + - name: XTAL32K_WDT_TIMEOUT + description: If no clock detected for this amount of time 32k is regarded as dead + bitOffset: 20 + bitWidth: 8 + access: read-write + - name: XTAL32K_STABLE_THRES + description: "if restarted xtal32k period is smaller than this, it is regarded as stable" + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: ULP_CP_TIMER + description: configure ulp + addressOffset: 252 + size: 32 + fields: + - name: ULP_CP_PC_INIT + description: ULP-coprocessor PC initial address + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: ULP_CP_GPIO_WAKEUP_ENA + description: ULP-coprocessor wakeup by GPIO enable + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ULP_CP_GPIO_WAKEUP_CLR + description: ULP-coprocessor wakeup by GPIO state clear + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: ULP_CP_SLP_TIMER_EN + description: ULP-coprocessor timer enable bit + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: ULP_CP_CTRL + description: configure ulp + addressOffset: 256 + size: 32 + resetValue: 1049088 + fields: + - name: ULP_CP_MEM_ADDR_INIT + description: No public + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: ULP_CP_MEM_ADDR_SIZE + description: No public + bitOffset: 11 + bitWidth: 11 + access: read-write + - name: ULP_CP_MEM_OFFST_CLR + description: No public + bitOffset: 22 + bitWidth: 1 + access: write-only + - name: ULP_CP_CLK_FO + description: ulp coprocessor clk force on + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: ULP_CP_RESET + description: ulp coprocessor clk software reset + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ULP_CP_FORCE_START_TOP + description: "1: ULP-coprocessor is started by SW" + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: ULP_CP_START_TOP + description: Write 1 to start ULP-coprocessor + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: COCPU_CTRL + description: configure ulp-riscv + addressOffset: 260 + size: 32 + resetValue: 9046032 + fields: + - name: COCPU_CLK_FO + description: cocpu clk force on + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: COCPU_START_2_RESET_DIS + description: time from start cocpu to pull down reset + bitOffset: 1 + bitWidth: 6 + access: read-write + - name: COCPU_START_2_INTR_EN + description: time from start cocpu to give start interrupt + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: COCPU_SHUT + description: to shut cocpu + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: COCPU_SHUT_2_CLK_DIS + description: time from shut cocpu to disable clk + bitOffset: 14 + bitWidth: 8 + access: read-write + - name: COCPU_SHUT_RESET_EN + description: to reset cocpu + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: COCPU_SEL + description: "1: old ULP 0: new riscV" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: COCPU_DONE_FORCE + description: "1: select riscv done 0: select ulp done" + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: COCPU_DONE + description: done signal used by riscv to control timer. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: COCPU_SW_INT_TRIGGER + description: trigger cocpu register interrupt + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: COCPU_CLKGATE_EN + description: open ulp-riscv clk gate + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: TOUCH_CTRL1 + description: configure touch controller + addressOffset: 264 + size: 32 + resetValue: 268435712 + fields: + - name: TOUCH_SLEEP_CYCLES + description: sleep cycles for timer + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: TOUCH_MEAS_NUM + description: the meas length (in 8MHz) + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: TOUCH_CTRL2 + description: configure touch controller + addressOffset: 268 + size: 32 + resetValue: 540876 + fields: + - name: TOUCH_DRANGE + description: TOUCH_DRANGE + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: TOUCH_DREFL + description: TOUCH_DREFL + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: TOUCH_DREFH + description: TOUCH_DREFH + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: TOUCH_XPD_BIAS + description: TOUCH_XPD_BIAS + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TOUCH_REFC + description: TOUCH pad0 reference cap + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: TOUCH_DBIAS + description: "1:use self bias 0:use bandgap bias" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TOUCH_SLP_TIMER_EN + description: touch timer enable bit + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TOUCH_START_FSM_EN + description: "1: TOUCH_START & TOUCH_XPD is controlled by touch fsm" + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TOUCH_START_EN + description: "1: start touch fsm" + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: TOUCH_START_FORCE + description: "1: to start touch fsm by SW" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: TOUCH_XPD_WAIT + description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD + bitOffset: 17 + bitWidth: 8 + access: read-write + - name: TOUCH_SLP_CYC_DIV + description: when a touch pad is active sleep cycle could be divided by this number + bitOffset: 25 + bitWidth: 2 + access: read-write + - name: TOUCH_TIMER_FORCE_DONE + description: force touch timer done + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: TOUCH_RESET + description: reset upgrade touch + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TOUCH_CLK_FO + description: touch clock force on + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TOUCH_CLKGATE_EN + description: touch clock enable + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TOUCH_SCAN_CTRL + description: configure touch controller + addressOffset: 272 + size: 32 + resetValue: 4026532098 + fields: + - name: TOUCH_DENOISE_RES + description: "De-noise resolution: 12/10/8/4 bit" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: TOUCH_DENOISE_EN + description: touch pad0 will be used to de-noise + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TOUCH_INACTIVE_CONNECTION + description: "inactive touch pads connect to 1: gnd 0: HighZ" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TOUCH_SHIELD_PAD_EN + description: touch pad14 will be used as shield + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: TOUCH_SCAN_PAD_MAP + description: touch scan mode pad enable map + bitOffset: 10 + bitWidth: 15 + access: read-write + - name: TOUCH_BUFDRV + description: touch7 buffer driver strength + bitOffset: 25 + bitWidth: 3 + access: read-write + - name: TOUCH_OUT_RING + description: select out ring pad + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: TOUCH_SLP_THRES + description: configure touch controller + addressOffset: 276 + size: 32 + resetValue: 2013265920 + fields: + - name: TOUCH_SLP_TH + description: the threshold for sleep touch pad + bitOffset: 0 + bitWidth: 22 + access: read-write + - name: TOUCH_SLP_APPROACH_EN + description: sleep pad approach function enable + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TOUCH_SLP_PAD + description: configure which pad as slp pad + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: TOUCH_APPROACH + description: configure touch controller + addressOffset: 280 + size: 32 + resetValue: 1342177280 + fields: + - name: TOUCH_SLP_CHANNEL_CLR + description: clear touch slp channel + bitOffset: 23 + bitWidth: 1 + access: write-only + - name: TOUCH_APPROACH_MEAS_TIME + description: approach pads total meas times + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: TOUCH_FILTER_CTRL + description: configure touch controller + addressOffset: 284 + size: 32 + resetValue: 2527758336 + fields: + - name: TOUCH_BYPASS_NEG_NOISE_THRES + description: bypass neg noise thres + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TOUCH_BYPASS_NOISE_THRES + description: bypaas noise thres + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: TOUCH_SMOOTH_LVL + description: smooth filter factor + bitOffset: 9 + bitWidth: 2 + access: read-write + - name: TOUCH_JITTER_STEP + description: touch jitter step + bitOffset: 11 + bitWidth: 4 + access: read-write + - name: TOUCH_NEG_NOISE_LIMIT + description: negative threshold counter limit + bitOffset: 15 + bitWidth: 4 + access: read-write + - name: TOUCH_NEG_NOISE_THRES + description: neg noise thres + bitOffset: 19 + bitWidth: 2 + access: read-write + - name: TOUCH_NOISE_THRES + description: noise thres + bitOffset: 21 + bitWidth: 2 + access: read-write + - name: TOUCH_HYSTERESIS + description: hysteresis + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: TOUCH_DEBOUNCE + description: debounce counter + bitOffset: 25 + bitWidth: 3 + access: read-write + - name: TOUCH_FILTER_MODE + description: "0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter" + bitOffset: 28 + bitWidth: 3 + access: read-write + - name: TOUCH_FILTER_EN + description: touch filter enable + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USB_CONF + description: usb configure + addressOffset: 288 + size: 32 + fields: + - name: USB_VREFH + description: reg_usb_vrefh + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: USB_VREFL + description: reg_usb_vrefl + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: USB_VREF_OVERRIDE + description: reg_usb_vref_override + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: USB_PAD_PULL_OVERRIDE + description: reg_usb_pad_pull_override + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: USB_DP_PULLUP + description: reg_usb_dp_pullup + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: USB_DP_PULLDOWN + description: reg_usb_dp_pulldown + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: USB_DM_PULLUP + description: reg_usb_dm_pullup + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: USB_DM_PULLDOWN + description: reg_usb_dm_pulldown + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: USB_PULLUP_VALUE + description: reg_usb_pullup_value + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: USB_PAD_ENABLE_OVERRIDE + description: reg_usb_pad_enable_override + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: USB_PAD_ENABLE + description: reg_usb_pad_enable + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: USB_TXM + description: reg_usb_txm + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: USB_TXP + description: reg_usb_txp + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: USB_TX_EN + description: reg_usb_tx_en + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: USB_TX_EN_OVERRIDE + description: reg_usb_tx_en_override + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: USB_RESET_DISABLE + description: reg_usb_reset_disable + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: IO_MUX_RESET_DISABLE + description: reg_io_mux_reset_disable + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SW_USB_PHY_SEL + description: reg_sw_usb_phy_sel + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SW_HW_USB_PHY_SEL + description: reg_sw_hw_usb_phy_sel + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: TOUCH_TIMEOUT_CTRL + description: configure touch controller + addressOffset: 292 + size: 32 + resetValue: 8388607 + fields: + - name: TOUCH_TIMEOUT_NUM + description: configure touch timerout time + bitOffset: 0 + bitWidth: 22 + access: read-write + - name: TOUCH_TIMEOUT_EN + description: enable touch timerout + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: SLP_REJECT_CAUSE + description: get reject casue + addressOffset: 296 + size: 32 + fields: + - name: REJECT_CAUSE + description: sleep reject cause + bitOffset: 0 + bitWidth: 18 + access: read-only + - register: + name: OPTION1 + description: rtc common configure + addressOffset: 300 + size: 32 + fields: + - name: FORCE_DOWNLOAD_BOOT + description: force chip entry download boot by sw + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SLP_WAKEUP_CAUSE + description: get wakeup cause + addressOffset: 304 + size: 32 + fields: + - name: WAKEUP_CAUSE + description: sleep wakeup cause + bitOffset: 0 + bitWidth: 17 + access: read-only + - register: + name: ULP_CP_TIMER_1 + description: configure ulp sleep time + addressOffset: 308 + size: 32 + resetValue: 51200 + fields: + - name: ULP_CP_TIMER_SLP_CYCLE + description: sleep cycles for ULP-coprocessor timer + bitOffset: 8 + bitWidth: 24 + access: read-write + - register: + name: INT_ENA_RTC_W1TS + description: oneset rtc interrupt + addressOffset: 312 + size: 32 + fields: + - name: SLP_WAKEUP_INT_ENA_W1TS + description: enable sleep wakeup interrupt + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SLP_REJECT_INT_ENA_W1TS + description: enable sleep reject interrupt + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SDIO_IDLE_INT_ENA_W1TS + description: enable SDIO idle interrupt + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: WDT_INT_ENA_W1TS + description: enable RTC WDT interrupt + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TOUCH_SCAN_DONE_INT_ENA_W1TS + description: enable touch scan done interrupt + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: ULP_CP_INT_ENA_W1TS + description: enable ULP-coprocessor interrupt + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TOUCH_DONE_INT_ENA_W1TS + description: enable touch done interrupt + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TOUCH_ACTIVE_INT_ENA_W1TS + description: enable touch active interrupt + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: TOUCH_INACTIVE_INT_ENA_W1TS + description: enable touch inactive interrupt + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: BROWN_OUT_INT_ENA_W1TS + description: enable brown out interrupt + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: MAIN_TIMER_INT_ENA_W1TS + description: enable RTC main timer interrupt + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SARADC1_INT_ENA_W1TS + description: enable saradc1 interrupt + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TSENS_INT_ENA_W1TS + description: enable tsens interrupt + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: COCPU_INT_ENA_W1TS + description: enable riscV cocpu interrupt + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SARADC2_INT_ENA_W1TS + description: enable saradc2 interrupt + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SWD_INT_ENA_W1TS + description: enable super watch dog interrupt + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: XTAL32K_DEAD_INT_ENA_W1TS + description: enable xtal32k_dead interrupt + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: COCPU_TRAP_INT_ENA_W1TS + description: enable cocpu trap interrupt + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: TOUCH_TIMEOUT_INT_ENA_W1TS + description: enable touch timeout interrupt + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: GLITCH_DET_INT_ENA_W1TS + description: enbale gitch det interrupt + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS + description: enbale touch approach_loop done interrupt + bitOffset: 20 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA_RTC_W1TC + description: oneset clr rtc interrupt enable + addressOffset: 316 + size: 32 + fields: + - name: SLP_WAKEUP_INT_ENA_W1TC + description: enable sleep wakeup interrupt + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SLP_REJECT_INT_ENA_W1TC + description: enable sleep reject interrupt + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SDIO_IDLE_INT_ENA_W1TC + description: enable SDIO idle interrupt + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: WDT_INT_ENA_W1TC + description: enable RTC WDT interrupt + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TOUCH_SCAN_DONE_INT_ENA_W1TC + description: enable touch scan done interrupt + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: ULP_CP_INT_ENA_W1TC + description: enable ULP-coprocessor interrupt + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: TOUCH_DONE_INT_ENA_W1TC + description: enable touch done interrupt + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TOUCH_ACTIVE_INT_ENA_W1TC + description: enable touch active interrupt + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: TOUCH_INACTIVE_INT_ENA_W1TC + description: enable touch inactive interrupt + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: BROWN_OUT_INT_ENA_W1TC + description: enable brown out interrupt + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: MAIN_TIMER_INT_ENA_W1TC + description: enable RTC main timer interrupt + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SARADC1_INT_ENA_W1TC + description: enable saradc1 interrupt + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TSENS_INT_ENA_W1TC + description: enable tsens interrupt + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: COCPU_INT_ENA_W1TC + description: enable riscV cocpu interrupt + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SARADC2_INT_ENA_W1TC + description: enable saradc2 interrupt + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SWD_INT_ENA_W1TC + description: enable super watch dog interrupt + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: XTAL32K_DEAD_INT_ENA_W1TC + description: enable xtal32k_dead interrupt + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: COCPU_TRAP_INT_ENA_W1TC + description: enable cocpu trap interrupt + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: TOUCH_TIMEOUT_INT_ENA_W1TC + description: enable touch timeout interrupt + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: GLITCH_DET_INT_ENA_W1TC + description: enbale gitch det interrupt + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC + description: enbale touch approach_loop done interrupt + bitOffset: 20 + bitWidth: 1 + access: write-only + - register: + name: RETENTION_CTRL + description: configure retention + addressOffset: 320 + size: 32 + resetValue: 674496512 + fields: + - name: RETENTION_TAG_MODE + description: No public + bitOffset: 10 + bitWidth: 4 + access: read-write + - name: RETENTION_TARGET + description: congfigure retention target cpu and/or tag + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: RETENTION_CLK_SEL + description: No public + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RETENTION_DONE_WAIT + description: wait retention done cycle + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: RETENTION_CLKOFF_WAIT + description: wait clk off cycle + bitOffset: 20 + bitWidth: 4 + access: read-write + - name: RETENTION_EN + description: enable retention + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: RETENTION_WAIT + description: wait cycles for rention operation + bitOffset: 25 + bitWidth: 7 + access: read-write + - register: + name: PG_CTRL + description: configure power glitch + addressOffset: 324 + size: 32 + fields: + - name: POWER_GLITCH_DSENSE + description: GLITCH_DSENSE + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: POWER_GLITCH_FORCE_PD + description: force power glitch disable + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: POWER_GLITCH_FORCE_PU + description: force power glitch enable + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: POWER_GLITCH_EFUSE_SEL + description: select use analog fib signal + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: POWER_GLITCH_EN + description: enable power glitch + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: FIB_SEL + description: No public + addressOffset: 328 + size: 32 + resetValue: 7 + fields: + - name: FIB_SEL + description: No public + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: TOUCH_DAC + description: configure touch dac + addressOffset: 332 + size: 32 + fields: + - name: TOUCH_PAD9_DAC + description: configure touch pad dac9 + bitOffset: 2 + bitWidth: 3 + access: read-write + - name: TOUCH_PAD8_DAC + description: configure touch pad dac8 + bitOffset: 5 + bitWidth: 3 + access: read-write + - name: TOUCH_PAD7_DAC + description: configure touch pad dac7 + bitOffset: 8 + bitWidth: 3 + access: read-write + - name: TOUCH_PAD6_DAC + description: configure touch pad dac6 + bitOffset: 11 + bitWidth: 3 + access: read-write + - name: TOUCH_PAD5_DAC + description: configure touch pad dac5 + bitOffset: 14 + bitWidth: 3 + access: read-write + - name: TOUCH_PAD4_DAC + description: configure touch pad dac4 + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: TOUCH_PAD3_DAC + description: configure touch pad dac3 + bitOffset: 20 + bitWidth: 3 + access: read-write + - name: TOUCH_PAD2_DAC + description: configure touch pad dac2 + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: TOUCH_PAD1_DAC + description: configure touch pad dac1 + bitOffset: 26 + bitWidth: 3 + access: read-write + - name: TOUCH_PAD0_DAC + description: configure touch pad dac0 + bitOffset: 29 + bitWidth: 3 + access: read-write + - register: + name: TOUCH_DAC1 + description: configure touch dac + addressOffset: 336 + size: 32 + fields: + - name: TOUCH_PAD14_DAC + description: configure touch pad dac14 + bitOffset: 17 + bitWidth: 3 + access: read-write + - name: TOUCH_PAD13_DAC + description: configure touch pad dac13 + bitOffset: 20 + bitWidth: 3 + access: read-write + - name: TOUCH_PAD12_DAC + description: configure touch pad dac12 + bitOffset: 23 + bitWidth: 3 + access: read-write + - name: TOUCH_PAD11_DAC + description: configure touch pad dac11 + bitOffset: 26 + bitWidth: 3 + access: read-write + - name: TOUCH_PAD10_DAC + description: configure touch pad dac10 + bitOffset: 29 + bitWidth: 3 + access: read-write + - register: + name: COCPU_DISABLE + description: configure ulp diable + addressOffset: 340 + size: 32 + fields: + - name: DISABLE_RTC_CPU + description: configure ulp diable + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: version register + addressOffset: 508 + size: 32 + resetValue: 34607729 + fields: + - name: DATE + description: version register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: RTC_I2C + description: Low-power I2C (Inter-Integrated Circuit) Controller + groupName: RTC_I2C + baseAddress: 1610648576 + addressBlock: + - offset: 0 + size: 124 + usage: registers + registers: + - register: + name: SCL_LOW + description: configure low scl period + addressOffset: 0 + size: 32 + resetValue: 256 + fields: + - name: PERIOD + description: time period that scl =0 + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: CTRL + description: configure i2c ctrl + addressOffset: 4 + size: 32 + fields: + - name: SDA_FORCE_OUT + description: "1=push pull,0=open drain" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SCL_FORCE_OUT + description: "1=push pull,0=open drain" + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MS_MODE + description: "1=master,0=slave" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TRANS_START + description: force start + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_LSB_FIRST + description: transit lsb first + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_LSB_FIRST + description: receive lsb first + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: I2C_CTRL_CLK_GATE_EN + description: configure i2c ctrl clk enable + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: I2C_RESET + description: rtc i2c sw reset + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: I2CCLK_EN + description: rtc i2c reg clk gating + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: STATUS + description: get i2c status + addressOffset: 8 + size: 32 + fields: + - name: ACK_REC + description: ack response + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SLAVE_RW + description: slave read or write + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ARB_LOST + description: arbitration is lost + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: BUS_BUSY + description: bus is busy + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SLAVE_ADDRESSED + description: slave reg sub address + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: BYTE_TRANS + description: One byte transit done + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OP_CNT + description: which operation is working + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: SHIFT + description: shifter content + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: SCL_MAIN_STATE_LAST + description: i2c last main status + bitOffset: 24 + bitWidth: 3 + access: read-only + - name: SCL_STATE_LAST + description: scl last status + bitOffset: 28 + bitWidth: 3 + access: read-only + - register: + name: TO + description: configure time out + addressOffset: 12 + size: 32 + resetValue: 65536 + fields: + - name: TIME_OUT + description: time out threshold + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: SLAVE_ADDR + description: configure slave id + addressOffset: 16 + size: 32 + fields: + - name: SLAVE_ADDR + description: slave address + bitOffset: 0 + bitWidth: 15 + access: read-write + - name: ADDR_10BIT_EN + description: i2c 10bit mode enable + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SCL_HIGH + description: configure high scl period + addressOffset: 20 + size: 32 + resetValue: 256 + fields: + - name: PERIOD + description: time period that scl = 1 + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: SDA_DUTY + description: configure sda duty + addressOffset: 24 + size: 32 + resetValue: 16 + fields: + - name: NUM + description: time period for SDA to toggle after SCL goes low + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: SCL_START_PERIOD + description: configure scl start period + addressOffset: 28 + size: 32 + resetValue: 8 + fields: + - name: SCL_START_PERIOD + description: time period for SCL to toggle after I2C start is triggered + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: SCL_STOP_PERIOD + description: configure scl stop period + addressOffset: 32 + size: 32 + resetValue: 8 + fields: + - name: SCL_STOP_PERIOD + description: time period for SCL to stop after I2C end is triggered + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: INT_CLR + description: interrupt clear register + addressOffset: 36 + size: 32 + fields: + - name: SLAVE_TRAN_COMP_INT_CLR + description: clear slave transit complete interrupt + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ARBITRATION_LOST_INT_CLR + description: clear arbitration lost interrupt + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: MASTER_TRAN_COMP_INT_CLR + description: clear master transit complete interrupt + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TRANS_COMPLETE_INT_CLR + description: clear transit complete interrupt + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: TIME_OUT_INT_CLR + description: clear time out interrupt + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: ACK_ERR_INT_CLR + description: clear ack error interrupt + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: RX_DATA_INT_CLR + description: clear receive data interrupt + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: TX_DATA_INT_CLR + description: clear transit load data complete interrupt + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: DETECT_START_INT_CLR + description: clear detect start interrupt + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: INT_RAW + description: interrupt raw register + addressOffset: 40 + size: 32 + fields: + - name: SLAVE_TRAN_COMP_INT_RAW + description: slave transit complete interrupt raw + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_RAW + description: arbitration lost interrupt raw + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: MASTER_TRAN_COMP_INT_RAW + description: master transit complete interrupt raw + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_RAW + description: transit complete interrupt raw + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_RAW + description: time out interrupt raw + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ACK_ERR_INT_RAW + description: ack error interrupt raw + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: RX_DATA_INT_RAW + description: receive data interrupt raw + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TX_DATA_INT_RAW + description: transit data interrupt raw + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DETECT_START_INT_RAW + description: detect start interrupt raw + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INT_ST + description: interrupt state register + addressOffset: 44 + size: 32 + fields: + - name: SLAVE_TRAN_COMP_INT_ST + description: slave transit complete interrupt state + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ARBITRATION_LOST_INT_ST + description: arbitration lost interrupt state + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: MASTER_TRAN_COMP_INT_ST + description: master transit complete interrupt state + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TRANS_COMPLETE_INT_ST + description: transit complete interrupt state + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TIME_OUT_INT_ST + description: time out interrupt state + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: ACK_ERR_INT_ST + description: ack error interrupt state + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: RX_DATA_INT_ST + description: receive data interrupt state + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: TX_DATA_INT_ST + description: transit data interrupt state + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: DETECT_START_INT_ST + description: detect start interrupt state + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: interrupt enable register + addressOffset: 48 + size: 32 + fields: + - name: SLAVE_TRAN_COMP_INT_ENA + description: enable slave transit complete interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ARBITRATION_LOST_INT_ENA + description: enable arbitration lost interrupt + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MASTER_TRAN_COMP_INT_ENA + description: enable master transit complete interrupt + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TRANS_COMPLETE_INT_ENA + description: enable transit complete interrupt + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TIME_OUT_INT_ENA + description: enable time out interrupt + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: ACK_ERR_INT_ENA + description: enable eack error interrupt + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RX_DATA_INT_ENA + description: enable receive data interrupt + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TX_DATA_INT_ENA + description: enable transit data interrupt + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DETECT_START_INT_ENA + description: enable detect start interrupt + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: DATA + description: get i2c data status + addressOffset: 52 + size: 32 + fields: + - name: I2C_RDATA + description: data received + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: SLAVE_TX_DATA + description: data sent by slave + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: I2C_DONE + description: i2c done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD0 + description: i2c commond0 register + addressOffset: 56 + size: 32 + resetValue: 2307 + fields: + - name: COMMAND0 + description: command0 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND0_DONE + description: command0_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD1 + description: i2c commond1 register + addressOffset: 60 + size: 32 + resetValue: 6401 + fields: + - name: COMMAND1 + description: command1 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND1_DONE + description: command1_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD2 + description: i2c commond2 register + addressOffset: 64 + size: 32 + resetValue: 2306 + fields: + - name: COMMAND2 + description: command2 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND2_DONE + description: command2_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD3 + description: i2c commond3 register + addressOffset: 68 + size: 32 + resetValue: 257 + fields: + - name: COMMAND3 + description: command3 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND3_DONE + description: command3_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD4 + description: i2c commond4 register + addressOffset: 72 + size: 32 + resetValue: 2305 + fields: + - name: COMMAND4 + description: command4 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND4_DONE + description: command4_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD5 + description: i2c commond5_register + addressOffset: 76 + size: 32 + resetValue: 5889 + fields: + - name: COMMAND5 + description: command5 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND5_DONE + description: command5_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD6 + description: i2c commond6 register + addressOffset: 80 + size: 32 + resetValue: 6401 + fields: + - name: COMMAND6 + description: command6 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND6_DONE + description: command6_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD7 + description: i2c commond7 register + addressOffset: 84 + size: 32 + resetValue: 2308 + fields: + - name: COMMAND7 + description: command7 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND7_DONE + description: command7_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD8 + description: i2c commond8 register + addressOffset: 88 + size: 32 + resetValue: 6401 + fields: + - name: COMMAND8 + description: command8 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND8_DONE + description: command8_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD9 + description: i2c commond9 register + addressOffset: 92 + size: 32 + resetValue: 2307 + fields: + - name: COMMAND9 + description: command9 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND9_DONE + description: command9_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD10 + description: i2c commond10 register + addressOffset: 96 + size: 32 + resetValue: 257 + fields: + - name: COMMAND10 + description: command10 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND10_DONE + description: command10_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD11 + description: i2c commond11 register + addressOffset: 100 + size: 32 + resetValue: 2305 + fields: + - name: COMMAND11 + description: command11 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND11_DONE + description: command11_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD12 + description: i2c commond12 register + addressOffset: 104 + size: 32 + resetValue: 5889 + fields: + - name: COMMAND12 + description: command12 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND12_DONE + description: command12_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD13 + description: i2c commond13 register + addressOffset: 108 + size: 32 + resetValue: 6401 + fields: + - name: COMMAND13 + description: command13 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND13_DONE + description: command13_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD14 + description: i2c commond14 register + addressOffset: 112 + size: 32 + fields: + - name: COMMAND14 + description: command14 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND14_DONE + description: command14_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CMD15 + description: i2c commond15 register + addressOffset: 116 + size: 32 + fields: + - name: COMMAND15 + description: command15 + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: COMMAND15_DONE + description: command15_done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: version register + addressOffset: 252 + size: 32 + resetValue: 26235664 + fields: + - name: I2C_DATE + description: version + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: RTC_IO + description: Low-power Input/Output + groupName: RTC_IO + baseAddress: 1610646528 + addressBlock: + - offset: 0 + size: 240 + usage: registers + registers: + - register: + name: RTC_GPIO_OUT + description: RTC GPIO 0 ~ 21 output data register + addressOffset: 0 + size: 32 + fields: + - name: DATA + description: RTC GPIO 0 ~ 21 output data + bitOffset: 10 + bitWidth: 22 + access: read-write + - register: + name: RTC_GPIO_OUT_W1TS + description: one set RTC GPIO output data + addressOffset: 4 + size: 32 + fields: + - name: RTC_GPIO_OUT_DATA_W1TS + description: RTC GPIO 0 ~ 21 output data write 1 to set + bitOffset: 10 + bitWidth: 22 + access: write-only + - register: + name: RTC_GPIO_OUT_W1TC + description: one clear RTC GPIO output data + addressOffset: 8 + size: 32 + fields: + - name: RTC_GPIO_OUT_DATA_W1TC + description: RTC GPIO 0 ~ 21 output data write 1 to clear + bitOffset: 10 + bitWidth: 22 + access: write-only + - register: + name: RTC_GPIO_ENABLE + description: Configure RTC GPIO output enable + addressOffset: 12 + size: 32 + fields: + - name: RTC_GPIO_ENABLE + description: RTC GPIO 0 ~ 21 enable + bitOffset: 10 + bitWidth: 22 + access: read-write + - register: + name: RTC_GPIO_ENABLE_W1TS + description: one set RTC GPIO output enable + addressOffset: 16 + size: 32 + fields: + - name: RTC_GPIO_ENABLE_W1TS + description: RTC GPIO 0 ~ 21 enable write 1 to set + bitOffset: 10 + bitWidth: 22 + access: write-only + - register: + name: ENABLE_W1TC + description: one clear RTC GPIO output enable + addressOffset: 20 + size: 32 + fields: + - name: ENABLE_W1TC + description: RTC GPIO 0 ~ 21 enable write 1 to clear + bitOffset: 10 + bitWidth: 22 + access: write-only + - register: + name: RTC_GPIO_STATUS + description: RTC GPIO 0 ~ 21 interrupt status + addressOffset: 24 + size: 32 + fields: + - name: INT + description: RTC GPIO 0 ~ 21 interrupt status + bitOffset: 10 + bitWidth: 22 + access: read-write + - register: + name: RTC_GPIO_STATUS_W1TS + description: One set RTC GPIO 0 ~ 21 interrupt status + addressOffset: 28 + size: 32 + fields: + - name: RTC_GPIO_STATUS_INT_W1TS + description: RTC GPIO 0 ~ 21 interrupt status write 1 to set + bitOffset: 10 + bitWidth: 22 + access: write-only + - register: + name: RTC_GPIO_STATUS_W1TC + description: One clear RTC GPIO 0 ~ 21 interrupt status + addressOffset: 32 + size: 32 + fields: + - name: RTC_GPIO_STATUS_INT_W1TC + description: RTC GPIO 0 ~ 21 interrupt status write 1 to clear + bitOffset: 10 + bitWidth: 22 + access: write-only + - register: + name: RTC_GPIO_IN + description: RTC GPIO input data + addressOffset: 36 + size: 32 + fields: + - name: NEXT + description: RTC GPIO input data + bitOffset: 10 + bitWidth: 22 + access: read-only + - register: + dim: 22 + dimIncrement: 4 + dimIndex: "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21" + name: PIN%s + description: configure RTC GPIO%s + addressOffset: 40 + size: 32 + fields: + - name: PAD_DRIVER + description: "if set to 0: normal output, if set to 1: open drain" + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_TYPE + description: "if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger" + bitOffset: 7 + bitWidth: 3 + access: read-write + - name: WAKEUP_ENABLE + description: RTC GPIO wakeup enable bit + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: RTC_DEBUG_SEL + description: configure rtc debug + addressOffset: 128 + size: 32 + fields: + - name: RTC_DEBUG_SEL0 + description: configure rtc debug + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: RTC_DEBUG_SEL1 + description: configure rtc debug + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: RTC_DEBUG_SEL2 + description: configure rtc debug + bitOffset: 10 + bitWidth: 5 + access: read-write + - name: RTC_DEBUG_SEL3 + description: configure rtc debug + bitOffset: 15 + bitWidth: 5 + access: read-write + - name: RTC_DEBUG_SEL4 + description: configure rtc debug + bitOffset: 20 + bitWidth: 5 + access: read-write + - name: RTC_DEBUG_12M_NO_GATING + description: configure rtc debug + bitOffset: 25 + bitWidth: 1 + access: read-write + - register: + name: TOUCH_PAD0 + description: configure RTC PAD0 + addressOffset: 132 + size: 32 + resetValue: 1342177280 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD1 + description: configure RTC PAD1 + addressOffset: 136 + size: 32 + resetValue: 1207959552 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD2 + description: configure RTC PAD2 + addressOffset: 140 + size: 32 + resetValue: 1342177280 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD3 + description: configure RTC PAD3 + addressOffset: 144 + size: 32 + resetValue: 1207959552 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD4 + description: configure RTC PAD4 + addressOffset: 148 + size: 32 + resetValue: 1342177280 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD5 + description: configure RTC PAD5 + addressOffset: 152 + size: 32 + resetValue: 1342177280 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD6 + description: configure RTC PAD6 + addressOffset: 156 + size: 32 + resetValue: 1207959552 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD7 + description: configure RTC PAD7 + addressOffset: 160 + size: 32 + resetValue: 1073741824 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD8 + description: configure RTC PAD8 + addressOffset: 164 + size: 32 + resetValue: 1073741824 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD9 + description: configure RTC PAD9 + addressOffset: 168 + size: 32 + resetValue: 1073741824 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD10 + description: configure RTC PAD10 + addressOffset: 172 + size: 32 + resetValue: 1073741824 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD11 + description: configure RTC PAD11 + addressOffset: 176 + size: 32 + resetValue: 1073741824 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD12 + description: configure RTC PAD12 + addressOffset: 180 + size: 32 + resetValue: 1073741824 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD13 + description: configure RTC PAD13 + addressOffset: 184 + size: 32 + resetValue: 1073741824 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_PAD14 + description: configure RTC PAD14 + addressOffset: 188 + size: 32 + resetValue: 1073741824 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: XPD + description: TOUCH_XPD + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: TIE_OPT + description: TOUCH_TIE_OPT + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: START + description: TOUCH_START + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: XTAL_32P_PAD + description: configure RTC PAD15 + addressOffset: 192 + size: 32 + resetValue: 1073741824 + fields: + - name: X32P_FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: X32P_SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: X32P_SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: X32P_SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: X32P_FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: X32P_MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: X32P_RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: X32P_RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: X32P_DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: XTAL_32N_PAD + description: configure RTC PAD16 + addressOffset: 196 + size: 32 + resetValue: 1073741824 + fields: + - name: X32N_FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: X32N_SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: X32N_SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: X32N_SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: X32N_FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: X32N_MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: X32N_RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: X32N_RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: X32N_DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: PAD_DAC1 + description: configure RTC PAD17 + addressOffset: 200 + size: 32 + resetValue: 1073741824 + fields: + - name: PDAC1_DAC + description: PDAC1_DAC + bitOffset: 3 + bitWidth: 8 + access: read-write + - name: PDAC1_XPD_DAC + description: PDAC1_XPD_DAC + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: PDAC1_DAC_XPD_FORCE + description: "1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC,0: use SAR ADC FSM to control PDAC1_XPD_DAC" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PDAC1_FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: PDAC1_SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PDAC1_SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: PDAC1_SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PDAC1_FUN_SEL + description: PDAC1 function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: PDAC1_MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PDAC1_RUE + description: PDAC1_RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: PDAC1_RDE + description: PDAC1_RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: PDAC1_DRV + description: PDAC1_DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: PAD_DAC2 + description: configure RTC PAD18 + addressOffset: 204 + size: 32 + resetValue: 1073741824 + fields: + - name: PDAC2_DAC + description: PDAC2_DAC + bitOffset: 3 + bitWidth: 8 + access: read-write + - name: PDAC2_XPD_DAC + description: PDAC2_XPD_DAC + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: PDAC2_DAC_XPD_FORCE + description: "1: use reg_pdac2_xpd_dac to control PDAC2_XPD_DAC,0: use SAR ADC FSM to control PDAC2_XPD_DAC" + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PDAC2_FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: PDAC2_SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PDAC2_SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: PDAC2_SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PDAC2_FUN_SEL + description: PDAC1 function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: PDAC2_MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PDAC2_RUE + description: PDAC2_RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: PDAC2_RDE + description: PDAC2_RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: PDAC2_DRV + description: PDAC2_DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: RTC_PAD19 + description: configure RTC PAD19 + addressOffset: 208 + size: 32 + resetValue: 1342177280 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: RTC_PAD20 + description: configure RTC PAD20 + addressOffset: 212 + size: 32 + resetValue: 1342177280 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: RTC_PAD21 + description: configure RTC PAD21 + addressOffset: 216 + size: 32 + resetValue: 1342177280 + fields: + - name: FUN_IE + description: input enable in work mode + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SLP_OE + description: output enable in sleep mode + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLP_IE + description: input enable in sleep mode + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLP_SEL + description: "1: enable sleep mode during sleep,0: no sleep mode" + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: FUN_SEL + description: function sel + bitOffset: 17 + bitWidth: 2 + access: read-write + - name: MUX_SEL + description: "1: use RTC GPIO,0: use digital GPIO" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: RUE + description: RUE + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: RDE + description: RDE + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DRV + description: DRV + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: EXT_WAKEUP0 + description: configure EXT0 wakeup + addressOffset: 220 + size: 32 + fields: + - name: SEL + description: "******* Description configure***" + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: XTL_EXT_CTR + description: configure gpio pd XTAL + addressOffset: 224 + size: 32 + fields: + - name: SEL + description: select RTC GPIO 0 ~ 17 to control XTAL + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: SAR_I2C_IO + description: configure rtc i2c mux + addressOffset: 228 + size: 32 + fields: + - name: SAR_DEBUG_BIT_SEL + description: "******* Description configure***" + bitOffset: 23 + bitWidth: 5 + access: read-write + - name: SAR_I2C_SCL_SEL + description: "******* Description configure***" + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: SAR_I2C_SDA_SEL + description: "******* Description configure***" + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: TOUCH_CTRL + description: configure touch pad bufmode + addressOffset: 232 + size: 32 + fields: + - name: IO_TOUCH_BUFSEL + description: BUF_SEL when touch work without fsm + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: IO_TOUCH_BUFMODE + description: BUF_MODE when touch work without fsm + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: version + addressOffset: 508 + size: 32 + resetValue: 34607488 + fields: + - name: DATE + description: version + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SDHOST + description: SD/MMC Host Controller + groupName: SDHOST + baseAddress: 1610776576 + addressBlock: + - offset: 0 + size: 164 + usage: registers + registers: + - register: + name: CTRL + description: Control register + addressOffset: 0 + size: 32 + fields: + - name: CONTROLLER_RESET + description: "To reset controller, firmware should set this bit. This bit is auto-cleared after two AHB and two sdhost_cclk_in clock cycles." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FIFO_RESET + description: "To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation.\nNote: FIFO pointers will be out of reset after 2 cycles of system clocks in addition to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DMA_RESET + description: "To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INT_ENABLE + description: "Global interrupt enable/disable bit. 0: Disable; 1: Enable." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: READ_WAIT + description: For sending read-wait to SDIO cards. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SEND_IRQ_RESPONSE + description: "Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: ABORT_READ_DATA + description: "After a suspend-command is issued during a read-operation, software polls the card to find when the suspend-event occurred. Once the suspend-event has occurred, software sets the bit which will reset the data state machine that is waiting for the next block of data. This bit is automatically cleared once the data state machine is reset to idle." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SEND_CCSD + description: "When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the SDHOST_SEND_CCSD bit. It also sets the Command Done (CD) bit in the SDHOST_RINTSTS_REG register, and generates an interrupt for the host, in case the Command Done interrupt is not masked. \nNOTE: Once the SDHOST_SEND_CCSD bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device has signalled CCS." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SEND_AUTO_STOP_CCSD + description: "Always Set SDHOST_SEND_AUTO_STOP_CCSD and SDHOST_SEND_CCSD bits together; SDHOST_SEND_AUTO_STOP_CCSD should not be set independently of send_ccsd. When set, SD/MMC automatically sends an internally-generated STOP command (CMD12) to the CE-ATA device. After sending this internally-generated STOP command, the Auto Command Done (ACD) bit in SDHOST_RINTSTS_REG is set and an interrupt is generated for the host, in case the ACD interrupt is not masked. After sending the Command Completion Signal Disable (CCSD), SD/MMC automatically clears the SDHOST_SEND_AUTO_STOP_CCSD bit." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CEATA_DEVICE_INTERRUPT_STATUS + description: "Software should appropriately write to this bit after the power-on reset or any other reset to the CE-ATA device. After reset, the CE-ATA device's interrupt is usually disabled (nIEN = 1). If the host enables the CE-ATA device's interrupt, then software should set this bit." + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: CLKDIV + description: Clock divider configuration register + addressOffset: 8 + size: 32 + fields: + - name: CLK_DIVIDER0 + description: "Clock divider0 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CLK_DIVIDER1 + description: "Clock divider1 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on." + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: CLK_DIVIDER2 + description: "Clock divider2 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on." + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: CLK_DIVIDER3 + description: "Clock divider3 value. Clock divisor is 2*n, where n = 0 bypasses the divider (divisor of 1). For example, a value of 1 means divided by 2*1 = 2, a value of 0xFF means divided by 2*255 = 510, and so on." + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: CLKSRC + description: Clock source selection register + addressOffset: 12 + size: 32 + fields: + - name: CLKSRC + description: "Clock divider source for two SD cards is supported. Each card has two bits assigned to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for card 1. Card 0 maps and internally routes clock divider[0:3] outputs to cclk_out[1:0] pins, depending on bit value.\n00 : Clock divider 0;\n01 : Clock divider 1;\n10 : Clock divider 2;\n11 : Clock divider 3." + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: CLKENA + description: Clock enable register + addressOffset: 16 + size: 32 + fields: + - name: CCLK_ENABLE + description: "Clock-enable control for two SD card clocks and one MMC card clock is supported. One bit per card.\n0: Clock disabled;\n1: Clock enabled." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: LP_ENABLE + description: "Disable clock when the card is in IDLE state. One bit per card.\n0: clock disabled;\n1: clock enabled." + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: TMOUT + description: Data and response timeout configuration register + addressOffset: 20 + size: 32 + resetValue: 4294967104 + fields: + - name: RESPONSE_TIMEOUT + description: "Response timeout value. Value is specified in terms of number of card output clocks, i.e., sdhost_cclk_out." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: DATA_TIMEOUT + description: "Value for card data read timeout. This value is also used for data starvation by host timeout. The timeout counter is started only after the card clock is stopped. This value is specified in number of card output clocks, i.e. sdhost_cclk_out of the selected card.\nNOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this case, read data timeout interrupt needs to be disabled." + bitOffset: 8 + bitWidth: 24 + access: read-write + - register: + name: CTYPE + description: Card bus width configuration register + addressOffset: 24 + size: 32 + fields: + - name: CARD_WIDTH4 + description: "One bit per card indicates if card is 1-bit or 4-bit mode.\n0: 1-bit mode;\n1: 4-bit mode.\nBit[1:0] correspond to card[1:0] respectively." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CARD_WIDTH8 + description: "One bit per card indicates if card is in 8-bit mode.\n0: Non 8-bit mode;\n1: 8-bit mode.\nBit[17:16] correspond to card[1:0] respectively." + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: BLKSIZ + description: Card data block size configuration register + addressOffset: 28 + size: 32 + resetValue: 512 + fields: + - name: BLOCK_SIZE + description: Block size. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: BYTCNT + description: Data transfer length configuration register + addressOffset: 32 + size: 32 + resetValue: 512 + fields: + - name: BYTE_COUNT + description: "Number of bytes to be transferred, should be an integral multiple of Block Size for block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to terminate data transfer." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: INTMASK + description: SDIO interrupt mask register + addressOffset: 36 + size: 32 + fields: + - name: INT_MASK + description: "These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value of 1 enables the interrupt.\nBit 15 (EBE): End-bit error/no CRC error;\nBit 14 (ACD): Auto command done;\nBit 13 (SBE/BCI): Rx Start Bit Error;\nBit 12 (HLE): Hardware locked write error;\nBit 11 (FRUN): FIFO underrun/overrun error;\nBit 10 (HTO): Data starvation-by-host timeout;\nBit 9 (DRTO): Data read timeout;\nBit 8 (RTO): Response timeout; \nBit 7 (DCRC): Data CRC error; \nBit 6 (RCRC): Response CRC error; \nBit 5 (RXDR): Receive FIFO data request; \nBit 4 (TXDR): Transmit FIFO data request; \nBit 3 (DTO): Data transfer over; \nBit 2 (CD): Command done; \nBit 1 (RE): Response error;\nBit 0 (CD): Card detect." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SDIO_INT_MASK + description: "SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0] respectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt, and 1 enables an interrupt." + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: CMDARG + description: Command argument data register + addressOffset: 40 + size: 32 + fields: + - name: CMDARG + description: Value indicates command argument to be passed to the card. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CMD + description: Command and boot configuration register + addressOffset: 44 + size: 32 + resetValue: 536870912 + fields: + - name: INDEX + description: Command index. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: RESPONSE_EXPECT + description: "0: No response expected from card; 1: Response expected from card." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RESPONSE_LENGTH + description: "0: Short response expected from card; 1: Long response expected from card." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CHECK_RESPONSE_CRC + description: "0: Do not check; 1: Check response CRC.\nSome of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DATA_EXPECTED + description: "0: No data transfer expected; 1: Data transfer expected." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: READ_WRITE + description: "0: Read from card; 1: Write to card.\nDon't care if no data is expected from card." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TRANSFER_MODE + description: "0: Block data transfer command; 1: Stream data transfer command.\nDon't care if no data expected." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SEND_AUTO_STOP + description: "0: No stop command is sent at the end of data transfer; 1: Send stop command at the end of data transfer." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: WAIT_PRVDATA_COMPLETE + description: "0: Send command at once, even if previous data transfer has not completed; 1: Wait for previous data transfer to complete before sending Command.\nThe SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr should be same as in previous command." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: STOP_ABORT_CMD + description: "0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-number currently selected or not in data-transfer mode, then bit should be set to 0; 1: Stop or abort command intended to stop current data transfer in progress.\nWhen open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SEND_INITIALIZATION + description: "0: Do not send initialization sequence (80 clocks of 1) before sending this command; 1: Send initialization sequence before sending this command.\nAfter powered on, 80 clocks must be sent to card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CARD_NUMBER + description: "Card number in use. Represents physical slot number of card being accessed. In SD-only mode, up to two cards are supported." + bitOffset: 16 + bitWidth: 5 + access: read-write + - name: UPDATE_CLOCK_REGISTERS_ONLY + description: "0: Normal command sequence; 1: Do not send commands, just update clock register value into card clock domain.\nFollowing register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA.\nChanges card clocks (change frequency, truncate off or on, and set low-frequency mode). This is provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when sdhost_update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: READ_CEATA_DEVICE + description: "Read access flag.\n0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device;\n1: Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device.\nSoftware should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: CCS_EXPECTED + description: "Expected Command Completion Signal (CCS) configuration.\n0: Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device;\n1: Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device. \nIf the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: USE_HOLE + description: "Use Hold Register.\n0: CMD and DATA sent to card bypassing HOLD Register;\n1: CMD and DATA sent to card through the HOLD Register." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: START_CMD + description: "Start command. Once command is served by the CIU, this bit is automatically cleared. When this bit is set, host should not attempt to write to any command registers. If a write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and a response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt Register." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RESP0 + description: Response data register + addressOffset: 48 + size: 32 + fields: + - name: RESPONSE0 + description: "Bit[31:0] of response." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RESP1 + description: Long response data register + addressOffset: 52 + size: 32 + fields: + - name: RESPONSE1 + description: "Bit[63:32] of long response." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RESP2 + description: Long response data register + addressOffset: 56 + size: 32 + fields: + - name: RESPONSE2 + description: "Bit[95:64] of long response." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: RESP3 + description: Long response data register + addressOffset: 60 + size: 32 + fields: + - name: RESPONSE3 + description: "Bit[127:96] of long response." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: MINTSTS + description: Masked interrupt status register + addressOffset: 64 + size: 32 + fields: + - name: INT_STATUS_MSK + description: "Interrupt enabled only if corresponding bit in interrupt mask register is set.\nBit 15 (EBE): End-bit error/no CRC error;\nBit 14 (ACD): Auto command done;\nBit 13 (SBE/BCI): RX Start Bit Error;\nBit 12 (HLE): Hardware locked write error; \nBit 11 (FRUN): FIFO underrun/overrun error;\nBit 10 (HTO): Data starvation by host timeout (HTO);\nBit 9 (DTRO): Data read timeout; \nBit 8 (RTO): Response timeout; \nBit 7 (DCRC): Data CRC error; \nBit 6 (RCRC): Response CRC error; \nBit 5 (RXDR): Receive FIFO data request; \nBit 4 (TXDR): Transmit FIFO data request;\nBit 3 (DTO): Data transfer over; \nBit 2 (CD): Command done; \nBit 1 (RE): Response error;\nBit 0 (CD): Card detect." + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: SDIO_INTERRUPT_MSK + description: "Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. SDIO interrupt for card is enabled only if corresponding sdhost_sdio_int_mask bit is set in Interrupt mask register (Setting mask bit enables interrupt)." + bitOffset: 16 + bitWidth: 2 + access: read-only + - register: + name: RINTSTS + description: Raw interrupt status register + addressOffset: 68 + size: 32 + fields: + - name: INT_STATUS_RAW + description: "Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits are logged regardless of interrupt mask status.\nBit 15 (EBE): End-bit error/no CRC error;\nBit 14 (ACD): Auto command done;\nBit 13 (SBE/BCI): RX Start Bit Error;\nBit 12 (HLE): Hardware locked write error; \nBit 11 (FRUN): FIFO underrun/overrun error;\nBit 10 (HTO): Data starvation by host timeout (HTO);\nBit 9 (DTRO): Data read timeout; \nBit 8 (RTO): Response timeout; \nBit 7 (DCRC): Data CRC error; \nBit 6 (RCRC): Response CRC error; \nBit 5 (RXDR): Receive FIFO data request; \nBit 4 (TXDR): Transmit FIFO data request;\nBit 3 (DTO): Data transfer over; \nBit 2 (CD): Command done; \nBit 1 (RE): Response error;\nBit 0 (CD): Card detect." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SDIO_INTERRUPT_RAW + description: "Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has no effect.\n0: No SDIO interrupt from card;\n1: SDIO interrupt from card." + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: STATUS + description: SD/MMC status register + addressOffset: 72 + size: 32 + resetValue: 1814 + fields: + - name: FIFO_RX_WATERMARK + description: "FIFO reached Receive watermark level, not qualified with data transfer." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: FIFO_TX_WATERMARK + description: "FIFO reached Transmit watermark level, not qualified with data transfer." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: FIFO_EMPTY + description: FIFO is empty status. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FIFO_FULL + description: FIFO is full status. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: COMMAND_FSM_STATES + description: "Command FSM states.\n0: Idle;\n1: Send init sequence; \n2: Send cmd start bit; \n3: Send cmd tx bit;\n4: Send cmd index + arg;\n5: Send cmd crc7;\n6: Send cmd end bit;\n7: Receive resp start bit;\n8: Receive resp IRQ response;\n9: Receive resp tx bit;\n10: Receive resp cmd idx;\n11: Receive resp data;\n12: Receive resp crc7;\n13: Receive resp end bit;\n14: Cmd path wait NCC;\n15: Wait, cmd-to-response turnaround." + bitOffset: 4 + bitWidth: 4 + access: read-only + - name: DATA_3_STATUS + description: "Raw selected sdhost_card_data[3], checks whether card is present.\n0: card not present;\n1: card present." + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: DATA_BUSY + description: "Inverted version of raw selected sdhost_card_data[0].\n0: Card data not busy;\n1: Card data busy." + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: DATA_STATE_MC_BUSY + description: Data transmit or receive state-machine is busy. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: RESPONSE_INDEX + description: "Index of previous response, including any auto-stop sent by core." + bitOffset: 11 + bitWidth: 6 + access: read-only + - name: FIFO_COUNT + description: "FIFO count, number of filled locations in FIFO." + bitOffset: 17 + bitWidth: 13 + access: read-only + - register: + name: FIFOTH + description: FIFO configuration register + addressOffset: 76 + size: 32 + fields: + - name: TX_WMARK + description: "FIFO threshold watermark level when transmitting data to card. When FIFO data count is less than or equal to this number, DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated, regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred." + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: RX_WMARK + description: "FIFO threshold watermark level when receiving data to card.When FIFO data count reaches greater than this number , DMA/FIFO request is raised. During end of packet, request is generated regardless of threshold programming in order to complete any remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set." + bitOffset: 16 + bitWidth: 11 + access: read-write + - name: DMA_MULTIPLE_TRANSACTION_SIZE + description: "Burst size of multiple transaction, should be programmed same as DMA controller multiple-transaction-size SDHOST_SRC/DEST_MSIZE.\n000: 1-byte transfer; \n001: 4-byte transfer; \n010: 8-byte transfer; \n011: 16-byte transfer; \n100: 32-byte transfer; \n101: 64-byte transfer; \n110: 128-byte transfer; \n111: 256-byte transfer." + bitOffset: 28 + bitWidth: 3 + access: read-write + - register: + name: CDETECT + description: Card detect register + addressOffset: 80 + size: 32 + fields: + - name: CARD_DETECT_N + description: "Value on sdhost_card_detect_n input ports (1 bit per card), read-only bits. 0 represents presence of card. Only NUM_CARDS number of bits are implemented." + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: WRTPRT + description: Card write protection (WP) status register + addressOffset: 84 + size: 32 + fields: + - name: WRITE_PROTECT + description: Value on sdhost_card_write_prt input ports (1 bit per card). 1 represents write protection. Only NUM_CARDS number of bits are implemented. + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: TCBCNT + description: Transferred byte count register + addressOffset: 92 + size: 32 + fields: + - name: TCBCNT + description: Number of bytes transferred by CIU unit to card. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: TBBCNT + description: Transferred byte count register + addressOffset: 96 + size: 32 + fields: + - name: TBBCNT + description: Number of bytes transferred between Host/DMA memory and BIU FIFO. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DEBNCE + description: Debounce filter time configuration register + addressOffset: 100 + size: 32 + fields: + - name: DEBOUNCE_COUNT + description: "Number of host clocks (clk) used by debounce filter logic. The typical debounce time is 5 \\verb+~+ 25 ms to prevent the card instability when the card is inserted or removed." + bitOffset: 0 + bitWidth: 24 + access: read-write + - register: + name: USRID + description: User ID (scratchpad) register + addressOffset: 104 + size: 32 + fields: + - name: USRID + description: "User identification register, value set by user. Can also be used as a scratchpad register by user." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: VERID + description: Version ID (scratchpad) register + addressOffset: 108 + size: 32 + resetValue: 1412572938 + fields: + - name: VERSIONID + description: Hardware version register. Can also be read by fireware. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HCON + description: Hardware feature register + addressOffset: 112 + size: 32 + resetValue: 54807747 + fields: + - name: CARD_TYPE + description: Hardware support SDIO and MMC. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CARD_NUM + description: Support card number is 2. + bitOffset: 1 + bitWidth: 5 + access: read-only + - name: BUS_TYPE + description: Register config is APB bus. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: DATA_WIDTH + description: Regisger data widht is 32. + bitOffset: 7 + bitWidth: 3 + access: read-only + - name: ADDR_WIDTH + description: Register address width is 32. + bitOffset: 10 + bitWidth: 6 + access: read-only + - name: DMA_WIDTH + description: DMA data witdth is 32. + bitOffset: 18 + bitWidth: 3 + access: read-only + - name: RAM_INDISE + description: Inside RAM in SDMMC module. + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: HOLD + description: Have a hold regiser in data path . + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: NUM_CLK_DIV + description: Have 4 clk divider in design . + bitOffset: 24 + bitWidth: 2 + access: read-only + - register: + name: UHS + description: UHS-1 register + addressOffset: 116 + size: 32 + fields: + - name: DDR + description: "DDR mode selecton,1 bit for each card.\n0-Non-DDR mdoe.\n1-DDR mdoe." + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: RST_N + description: Card reset register + addressOffset: 120 + size: 32 + resetValue: 1 + fields: + - name: CARD_RESET + description: "Hardware reset.\n1: Active mode; \n0: Reset. \nThese bits cause the cards to enter pre-idle state, which requires them to be re-initialized. SDHOST_RST_CARD_RESET[0] should be set to 1'b0 to reset card0, SDHOST_RST_CARD_RESET[1] should be set to 1'b0 to reset card1." + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: BMOD + description: Burst mode transfer configuration register + addressOffset: 128 + size: 32 + fields: + - name: SWR + description: "Software Reset. When set, the DMA Controller resets all its internal registers. It is automatically cleared after one clock cycle." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FB + description: "Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DE + description: "IDMAC Enable. When set, the IDMAC is enabled." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: PBL + description: "Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC???Internal DMA Control???transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows:\n000: 1-byte transfer; \n001: 4-byte transfer; \n010: 8-byte transfer; \n011: 16-byte transfer; \n100: 32-byte transfer; \n101: 64-byte transfer; \n110: 128-byte transfer; \n111: 256-byte transfer.\nPBL is a read-only value and is applicable only for data access, it does not apply to descriptor access." + bitOffset: 8 + bitWidth: 3 + access: read-write + - register: + name: PLDMND + description: Poll demand configuration register + addressOffset: 132 + size: 32 + fields: + - name: PD + description: "Poll Demand. If the OWNER bit of a descriptor is not set, the FSM goes to the Suspend state. The host needs to write any value into this register for the IDMAC FSM to resume normal descriptor fetch operation. This is a write only ." + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: DBADDR + description: Descriptor base address register + addressOffset: 136 + size: 32 + fields: + - name: DBADDR + description: "Start of Descriptor List. Contains the base address of the First Descriptor. The LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be treated as read-only." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: IDSTS + description: IDMAC status register + addressOffset: 140 + size: 32 + fields: + - name: TI + description: Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RI + description: Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FBE + description: "Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DU + description: "Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0[31] = 0). Writing 1 clears this bit." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CES + description: "Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits:\nEBE : End Bit Error; \nRTO : Response Timeout/Boot Ack Timeout; \nRCRC : Response CRC; \nSBE : Start Bit Error; \nDRTO : Data Read Timeout/BDS timeout; \nDCRC : Data CRC for Receive; \nRE : Response Error.\nWriting 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: NIS + description: "Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit Interrupt, IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: AIS + description: "Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus Interrupt, IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FBE_CODE + description: "Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an interrupt.\n001: Host Abort received during transmission;\n010: Host Abort received during reception;\nOthers: Reserved." + bitOffset: 10 + bitWidth: 3 + access: read-write + - name: FSM + description: "DMAC FSM present state.\n0: DMA_IDLE (idle state); \n1: DMA_SUSPEND (suspend state); \n2: DESC_RD (descriptor reading state); \n3: DESC_CHK (descriptor checking state); \n4: DMA_RD_REQ_WAIT (read-data request waiting state);\n5: DMA_WR_REQ_WAIT (write-data request waiting state); \n6: DMA_RD (data-read state); \n7: DMA_WR (data-write state); \n8: DESC_CLOSE (descriptor close state)." + bitOffset: 13 + bitWidth: 4 + access: read-write + - register: + name: IDINTEN + description: IDMAC interrupt enable register + addressOffset: 144 + size: 32 + fields: + - name: TI + description: "Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RI + description: "Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FBE + description: "Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DU + description: "Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CES + description: "Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: NI + description: "Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits:\nIDINTEN[0]: Transmit Interrupt;\nIDINTEN[1]: Receive Interrupt." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: AI + description: "Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits:\nIDINTEN[2]: Fatal Bus Error Interrupt;\nIDINTEN[4]: DU Interrupt." + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: DSCADDR + description: Host descriptor address pointer + addressOffset: 148 + size: 32 + fields: + - name: DSCADDR + description: "Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the start address of the current descriptor read by the IDMAC." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: BUFADDR + description: Host buffer address pointer register + addressOffset: 152 + size: 32 + fields: + - name: BUFADDR + description: "Host Buffer Address Pointer, updated by IDMAC during operation and cleared on reset. This register points to the current Data Buffer Address being accessed by the IDMAC." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CARDTHRCTL + description: Card Threshold Control register + addressOffset: 256 + size: 32 + fields: + - name: CARDRDTHREN + description: "Card read threshold enable.\n1'b0-Card read threshold disabled.\n1'b1-Card read threshold enabled." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CARDCLRINTEN + description: "Busy clear interrupt generation:\n1'b0-Busy clear interrypt disabled.\n1'b1-Busy clear interrypt enabled." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CARDWRTHREN + description: "Applicable when HS400 mode is enabled.\n1'b0-Card write Threshold disabled.\n1'b1-Card write Threshold enabled." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CARDTHRESHOLD + description: "The inside FIFO size is 512,This register is applicable when SDHOST_CARDERTHREN_REG is set to 1 or SDHOST_CARDRDTHREN_REG set to 1." + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: EMMCDDR + description: eMMC DDR register + addressOffset: 268 + size: 32 + fields: + - name: HALFSTARTBIT + description: "Control for start bit detection mechanism duration of start bit.Each bit refers to one slot.Set this bit to 1 for eMMC4.5 and above,set to 0 for SD applications.For eMMC4.5,start bit can be:\n1'b0-Full cycle.\n1'b1-less than one full cycle." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: HS400_MODE + description: Set 1 to enable HS400 mode. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: ENSHIFT + description: Enable Phase Shift register + addressOffset: 272 + size: 32 + fields: + - name: ENABLE_SHIFT + description: "Control for the amount of phase shift provided on the default enables in the design.Two bits assigned for each card.\n2'b00-Default phase shift.\n2'b01-Enables shifted to next immediate positive edge.\n2'b10-Enables shifted to next immediate negative edge.\n2'b11-Reserved." + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: BUFFIFO + description: CPU write and read transmit data by FIFO + addressOffset: 512 + size: 32 + fields: + - name: BUFFIFO + description: CPU write and read transmit data by FIFO. This register points to the current Data FIFO . + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CLK_EDGE_SEL + description: SDIO control register. + addressOffset: 2048 + size: 32 + resetValue: 8520192 + fields: + - name: CCLKIN_EDGE_DRV_SEL + description: "It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270." + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: CCLKIN_EDGE_SAM_SEL + description: "It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270." + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: CCLKIN_EDGE_SLF_SEL + description: "It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270." + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: CCLLKIN_EDGE_H + description: The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L. + bitOffset: 9 + bitWidth: 4 + access: read-write + - name: CCLLKIN_EDGE_L + description: The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H. + bitOffset: 13 + bitWidth: 4 + access: read-write + - name: CCLLKIN_EDGE_N + description: The clock division of cclk_in. + bitOffset: 17 + bitWidth: 4 + access: read-write + - name: ESDIO_MODE + description: Enable esdio mode. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: ESD_MODE + description: Enable esd mode. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: CCLK_EN + description: Sdio clock enable. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SENS + description: SENS Peripheral + groupName: SENS + baseAddress: 1610647552 + addressBlock: + - offset: 0 + size: 284 + usage: registers + registers: + - register: + name: SAR_READER1_CTRL + description: configure saradc1 reader + addressOffset: 0 + size: 32 + resetValue: 537133058 + fields: + - name: SAR_SAR1_CLK_DIV + description: clock divider + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SAR_SAR1_CLK_GATED + description: no public + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SAR_SAR1_SAMPLE_NUM + description: no public + bitOffset: 19 + bitWidth: 8 + access: read-write + - name: SAR_SAR1_DATA_INV + description: Invert SAR ADC1 data + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SAR_SAR1_INT_EN + description: enable saradc1 to send out interrupt + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: SAR_READER1_STATUS + description: get saradc1 reader controller status + addressOffset: 4 + size: 32 + fields: + - name: SAR_SAR1_READER_STATUS + description: get saradc1 reader controller status + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SAR_MEAS1_CTRL1 + description: no public + addressOffset: 8 + size: 32 + fields: + - name: FORCE_XPD_AMP + description: no public + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: AMP_RST_FB_FORCE + description: no public + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: AMP_SHORT_REF_FORCE + description: no public + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: AMP_SHORT_REF_GND_FORCE + description: no public + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: SAR_MEAS1_CTRL2 + description: configure saradc1 controller + addressOffset: 12 + size: 32 + fields: + - name: MEAS1_DATA_SAR + description: SAR ADC1 data + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: MEAS1_DONE_SAR + description: SAR ADC1 conversion done indication + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: MEAS1_START_SAR + description: SAR ADC1 controller (in RTC) starts conversion + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MEAS1_START_FORCE + description: "1: SAR ADC1 controller (in RTC) is started by SW" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SAR1_EN_PAD + description: SAR ADC1 pad enable bitmap + bitOffset: 19 + bitWidth: 12 + access: read-write + - name: SAR1_EN_PAD_FORCE + description: "1: SAR ADC1 pad enable bitmap is controlled by SW" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAR_MEAS1_MUX + description: configure saradc1 controller + addressOffset: 16 + size: 32 + fields: + - name: SAR1_DIG_FORCE + description: "1: SAR ADC1 controlled by DIG ADC1 CTRL" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAR_ATTEN1 + description: configure saradc1 controller + addressOffset: 20 + size: 32 + resetValue: 4294967295 + fields: + - name: SAR1_ATTEN + description: 2-bit attenuation for each pad + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SAR_AMP_CTRL1 + description: no public + addressOffset: 24 + size: 32 + resetValue: 655370 + fields: + - name: SAR_AMP_WAIT1 + description: no public + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: SAR_AMP_WAIT2 + description: no public + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SAR_AMP_CTRL2 + description: no public + addressOffset: 28 + size: 32 + resetValue: 655360 + fields: + - name: SAR_SAR1_DAC_XPD_FSM_IDLE + description: no public + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SAR_XPD_SAR_AMP_FSM_IDLE + description: no public + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SAR_AMP_RST_FB_FSM_IDLE + description: no public + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SAR_AMP_SHORT_REF_FSM_IDLE + description: no public + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SAR_AMP_SHORT_REF_GND_FSM_IDLE + description: no public + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SAR_XPD_SAR_FSM_IDLE + description: no public + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SAR_RSTB_FSM_IDLE + description: no public + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SAR_AMP_WAIT3 + description: no public + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: SAR_AMP_CTRL3 + description: no public + addressOffset: 32 + size: 32 + resetValue: 7551219 + fields: + - name: SAR1_DAC_XPD_FSM + description: no public + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: XPD_SAR_AMP_FSM + description: no public + bitOffset: 4 + bitWidth: 4 + access: read-write + - name: AMP_RST_FB_FSM + description: no public + bitOffset: 8 + bitWidth: 4 + access: read-write + - name: AMP_SHORT_REF_FSM + description: no public + bitOffset: 12 + bitWidth: 4 + access: read-write + - name: AMP_SHORT_REF_GND_FSM + description: no public + bitOffset: 16 + bitWidth: 4 + access: read-write + - name: XPD_SAR_FSM + description: no public + bitOffset: 20 + bitWidth: 4 + access: read-write + - name: RSTB_FSM + description: no public + bitOffset: 24 + bitWidth: 4 + access: read-write + - register: + name: SAR_READER2_CTRL + description: configure saradc2 reader + addressOffset: 36 + size: 32 + resetValue: 1074069506 + fields: + - name: SAR_SAR2_CLK_DIV + description: clock divider + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SAR_SAR2_WAIT_ARB_CYCLE + description: wait arbit stable after sar_done + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: SAR_SAR2_CLK_GATED + description: "******* Description ***********" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SAR_SAR2_SAMPLE_NUM + description: "******* Description ***********" + bitOffset: 19 + bitWidth: 8 + access: read-write + - name: SAR_SAR2_DATA_INV + description: Invert SAR ADC2 data + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SAR_SAR2_INT_EN + description: enable saradc2 to send out interrupt + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: SAR_READER2_STATUS + description: get saradc1 reader controller status + addressOffset: 40 + size: 32 + fields: + - name: SAR_SAR2_READER_STATUS + description: get saradc1 reader controller status + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: SAR_MEAS2_CTRL1 + description: configure saradc2 controller + addressOffset: 44 + size: 32 + resetValue: 117572096 + fields: + - name: SAR_SAR2_CNTL_STATE + description: saradc2_cntl_fsm + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: SAR_SAR2_PWDET_CAL_EN + description: rtc control pwdet enable + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SAR_SAR2_PKDET_CAL_EN + description: rtc control pkdet enable + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SAR_SAR2_EN_TEST + description: SAR2_EN_TEST + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SAR_SAR2_RSTB_FORCE + description: no public + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: SAR_SAR2_STANDBY_WAIT + description: no public + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SAR_SAR2_RSTB_WAIT + description: no public + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SAR_SAR2_XPD_WAIT + description: no public + bitOffset: 24 + bitWidth: 8 + access: read-write + - register: + name: SAR_MEAS2_CTRL2 + description: configure saradc2 controller + addressOffset: 48 + size: 32 + fields: + - name: MEAS2_DATA_SAR + description: SAR ADC2 data + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: MEAS2_DONE_SAR + description: SAR ADC2 conversion done indication + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: MEAS2_START_SAR + description: SAR ADC2 controller (in RTC) starts conversion + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MEAS2_START_FORCE + description: "1: SAR ADC2 controller (in RTC) is started by SW" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SAR2_EN_PAD + description: SAR ADC2 pad enable bitmap + bitOffset: 19 + bitWidth: 12 + access: read-write + - name: SAR2_EN_PAD_FORCE + description: "1: SAR ADC2 pad enable bitmap is controlled by SW" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAR_MEAS2_MUX + description: configure saradc2 controller + addressOffset: 52 + size: 32 + fields: + - name: SAR2_PWDET_CCT + description: SAR2_PWDET_CCT + bitOffset: 28 + bitWidth: 3 + access: read-write + - name: SAR2_RTC_FORCE + description: "in sleep, force to use rtc to control ADC" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAR_ATTEN2 + description: configure saradc2 controller + addressOffset: 56 + size: 32 + resetValue: 4294967295 + fields: + - name: SAR2_ATTEN + description: 2-bit attenuation for each pad + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SAR_POWER_XPD_SAR + description: configure power of saradc + addressOffset: 60 + size: 32 + fields: + - name: FORCE_XPD_SAR + description: force power on/off saradc + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: SARCLK_EN + description: no public + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAR_SLAVE_ADDR1 + description: configure i2c slave address + addressOffset: 64 + size: 32 + fields: + - name: SAR_I2C_SLAVE_ADDR1 + description: configure i2c slave address1 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: SAR_I2C_SLAVE_ADDR0 + description: configure i2c slave address0 + bitOffset: 11 + bitWidth: 11 + access: read-write + - name: SAR_SARADC_MEAS_STATUS + description: no public + bitOffset: 22 + bitWidth: 8 + access: read-only + - register: + name: SAR_SLAVE_ADDR2 + description: configure i2c slave address + addressOffset: 68 + size: 32 + fields: + - name: SAR_I2C_SLAVE_ADDR3 + description: configure i2c slave address3 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: SAR_I2C_SLAVE_ADDR2 + description: configure i2c slave address2 + bitOffset: 11 + bitWidth: 11 + access: read-write + - register: + name: SAR_SLAVE_ADDR3 + description: configure i2c slave address + addressOffset: 72 + size: 32 + fields: + - name: SAR_I2C_SLAVE_ADDR5 + description: configure i2c slave address5 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: SAR_I2C_SLAVE_ADDR4 + description: configure i2c slave address4 + bitOffset: 11 + bitWidth: 11 + access: read-write + - register: + name: SAR_SLAVE_ADDR4 + description: configure i2c slave address + addressOffset: 76 + size: 32 + fields: + - name: SAR_I2C_SLAVE_ADDR7 + description: configure i2c slave address7 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: SAR_I2C_SLAVE_ADDR6 + description: configure i2c slave address6 + bitOffset: 11 + bitWidth: 11 + access: read-write + - register: + name: SAR_TSENS_CTRL + description: configure tsens controller + addressOffset: 80 + size: 32 + resetValue: 102400 + fields: + - name: SAR_TSENS_OUT + description: temperature sensor data out + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: SAR_TSENS_READY + description: indicate temperature sensor out ready + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SAR_TSENS_INT_EN + description: enable temperature sensor to send out interrupt + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SAR_TSENS_IN_INV + description: invert temperature sensor data + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SAR_TSENS_CLK_DIV + description: temperature sensor clock divider + bitOffset: 14 + bitWidth: 8 + access: read-write + - name: SAR_TSENS_POWER_UP + description: temperature sensor power up + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SAR_TSENS_POWER_UP_FORCE + description: "1: dump out & power up controlled by SW 0: by FSM" + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: SAR_TSENS_DUMP_OUT + description: temperature sensor dump out only active when reg_tsens_power_up_force = 1 + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: SAR_TSENS_CTRL2 + description: configure tsens controller + addressOffset: 84 + size: 32 + resetValue: 16386 + fields: + - name: SAR_TSENS_XPD_WAIT + description: no public + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: SAR_TSENS_XPD_FORCE + description: no public + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: SAR_TSENS_CLK_INV + description: no public + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: SAR_I2C_CTRL + description: configure rtc i2c controller by sw + addressOffset: 88 + size: 32 + fields: + - name: SAR_I2C_CTRL + description: I2C control data only active when reg_sar_i2c_start_force = 1 + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SAR_I2C_START + description: start I2C only active when reg_sar_i2c_start_force = 1 + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SAR_I2C_START_FORCE + description: "1: I2C started by SW 0: I2C started by FSM" + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: SAR_TOUCH_CONF + description: configure touch controller + addressOffset: 92 + size: 32 + resetValue: 4293951487 + fields: + - name: SAR_TOUCH_OUTEN + description: touch controller output enable + bitOffset: 0 + bitWidth: 15 + access: read-write + - name: SAR_TOUCH_STATUS_CLR + description: clear all touch active status + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: SAR_TOUCH_DATA_SEL + description: "3: smooth data 2: baseline 1,0: raw_data" + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: SAR_TOUCH_DENOISE_END + description: touch_denoise_done + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: SAR_TOUCH_UNIT_END + description: touch_unit_done + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: SAR_TOUCH_APPROACH_PAD2 + description: indicate which pad is approach pad2 + bitOffset: 20 + bitWidth: 4 + access: read-write + - name: SAR_TOUCH_APPROACH_PAD1 + description: indicate which pad is approach pad1 + bitOffset: 24 + bitWidth: 4 + access: read-write + - name: SAR_TOUCH_APPROACH_PAD0 + description: indicate which pad is approach pad0 + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: SAR_TOUCH_DENOISE + description: configure touch controller + addressOffset: 96 + size: 32 + fields: + - name: DATA + description: configure touch controller + bitOffset: 0 + bitWidth: 22 + access: read-only + - register: + name: SAR_TOUCH_THRES1 + description: configure touch thres of touch pad + addressOffset: 100 + size: 32 + fields: + - name: SAR_TOUCH_OUT_TH1 + description: Finger threshold for touch pad 1 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES2 + description: configure touch thres of touch pad + addressOffset: 104 + size: 32 + fields: + - name: SAR_TOUCH_OUT_TH2 + description: Finger threshold for touch pad 2 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES3 + description: configure touch thres of touch pad + addressOffset: 108 + size: 32 + fields: + - name: SAR_TOUCH_OUT_TH3 + description: Finger threshold for touch pad 3 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES4 + description: configure touch thres of touch pad + addressOffset: 112 + size: 32 + fields: + - name: SAR_TOUCH_OUT_TH4 + description: Finger threshold for touch pad 4 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES5 + description: configure touch thres of touch pad + addressOffset: 116 + size: 32 + fields: + - name: SAR_TOUCH_OUT_TH5 + description: Finger threshold for touch pad 5 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES6 + description: configure touch thres of touch pad + addressOffset: 120 + size: 32 + fields: + - name: SAR_TOUCH_OUT_TH6 + description: Finger threshold for touch pad 6 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES7 + description: configure touch thres of touch pad + addressOffset: 124 + size: 32 + fields: + - name: SAR_TOUCH_OUT_TH7 + description: Finger threshold for touch pad 7 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES8 + description: configure touch thres of touch pad + addressOffset: 128 + size: 32 + fields: + - name: SAR_TOUCH_OUT_TH8 + description: Finger threshold for touch pad 8 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES9 + description: configure touch thres of touch pad + addressOffset: 132 + size: 32 + fields: + - name: SAR_TOUCH_OUT_TH9 + description: Finger threshold for touch pad 9 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES10 + description: configure touch thres of touch pad + addressOffset: 136 + size: 32 + fields: + - name: SAR_TOUCH_OUT_TH10 + description: Finger threshold for touch pad 10 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES11 + description: configure touch thres of touch pad + addressOffset: 140 + size: 32 + fields: + - name: SAR_TOUCH_OUT_TH11 + description: Finger threshold for touch pad 11 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES12 + description: configure touch thres of touch pad + addressOffset: 144 + size: 32 + fields: + - name: SAR_TOUCH_OUT_TH12 + description: Finger threshold for touch pad 12 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES13 + description: configure touch thres of touch pad + addressOffset: 148 + size: 32 + fields: + - name: SAR_TOUCH_OUT_TH13 + description: Finger threshold for touch pad 13 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_THRES14 + description: configure touch thres of touch pad + addressOffset: 152 + size: 32 + fields: + - name: SAR_TOUCH_OUT_TH14 + description: Finger threshold for touch pad 14 + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: SAR_TOUCH_CHN_ST + description: Get touch channel status + addressOffset: 156 + size: 32 + fields: + - name: SAR_TOUCH_PAD_ACTIVE + description: touch active status + bitOffset: 0 + bitWidth: 15 + access: read-only + - name: SAR_TOUCH_CHANNEL_CLR + description: Clear touch channel + bitOffset: 15 + bitWidth: 15 + access: write-only + - name: SAR_TOUCH_MEAS_DONE + description: get touch meas done + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: SAR_TOUCH_STATUS0 + description: get touch scan status + addressOffset: 160 + size: 32 + fields: + - name: SAR_TOUCH_SCAN_CURR + description: current sample channel + bitOffset: 22 + bitWidth: 4 + access: read-only + - register: + name: SAR_TOUCH_STATUS1 + description: touch channel status of touch pad 1 + addressOffset: 164 + size: 32 + fields: + - name: SAR_TOUCH_PAD1_DATA + description: touch data debounce of touch pad 1 + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: SAR_TOUCH_PAD1_DEBOUNCE + description: touch current debounce of touch pad 1 + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS2 + description: touch channel status of touch pad 2 + addressOffset: 168 + size: 32 + fields: + - name: SAR_TOUCH_PAD2_DATA + description: touch data debounce of touch pad 2 + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: SAR_TOUCH_PAD2_DEBOUNCE + description: touch current debounce of touch pad 2 + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS3 + description: touch channel status of touch pad 3 + addressOffset: 172 + size: 32 + fields: + - name: SAR_TOUCH_PAD3_DATA + description: touch data debounce of touch pad 3 + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: SAR_TOUCH_PAD3_DEBOUNCE + description: touch current debounce of touch pad 3 + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS4 + description: touch channel status of touch pad 4 + addressOffset: 176 + size: 32 + fields: + - name: SAR_TOUCH_PAD4_DATA + description: touch data debounce of touch pad 4 + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: SAR_TOUCH_PAD4_DEBOUNCE + description: touch current debounce of touch pad 4 + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS5 + description: touch channel status of touch pad 5 + addressOffset: 180 + size: 32 + fields: + - name: SAR_TOUCH_PAD5_DATA + description: touch data debounce of touch pad 5 + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: SAR_TOUCH_PAD5_DEBOUNCE + description: touch current debounce of touch pad 5 + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS6 + description: touch channel status of touch pad 6 + addressOffset: 184 + size: 32 + fields: + - name: SAR_TOUCH_PAD6_DATA + description: touch data debounce of touch pad 6 + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: SAR_TOUCH_PAD6_DEBOUNCE + description: touch current debounce of touch pad 6 + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS7 + description: touch channel status of touch pad 7 + addressOffset: 188 + size: 32 + fields: + - name: SAR_TOUCH_PAD7_DATA + description: touch data debounce of touch pad 7 + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: SAR_TOUCH_PAD7_DEBOUNCE + description: touch current debounce of touch pad 7 + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS8 + description: touch channel status of touch pad 8 + addressOffset: 192 + size: 32 + fields: + - name: SAR_TOUCH_PAD8_DATA + description: touch data debounce of touch pad 8 + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: SAR_TOUCH_PAD8_DEBOUNCE + description: touch current debounce of touch pad 8 + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS9 + description: touch channel status of touch pad 9 + addressOffset: 196 + size: 32 + fields: + - name: SAR_TOUCH_PAD9_DATA + description: touch data debounce of touch pad 9 + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: SAR_TOUCH_PAD9_DEBOUNCE + description: touch current debounce of touch pad 9 + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS10 + description: touch channel status of touch pad 10 + addressOffset: 200 + size: 32 + fields: + - name: SAR_TOUCH_PAD10_DATA + description: touch data debounce of touch pad 10 + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: SAR_TOUCH_PAD10_DEBOUNCE + description: touch current debounce of touch pad 10 + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS11 + description: touch channel status of touch pad 11 + addressOffset: 204 + size: 32 + fields: + - name: SAR_TOUCH_PAD11_DATA + description: touch data debounce of touch pad 11 + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: SAR_TOUCH_PAD11_DEBOUNCE + description: touch current debounce of touch pad 11 + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS12 + description: touch channel status of touch pad 12 + addressOffset: 208 + size: 32 + fields: + - name: SAR_TOUCH_PAD12_DATA + description: touch data debounce of touch pad 12 + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: SAR_TOUCH_PAD12_DEBOUNCE + description: touch current debounce of touch pad 12 + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS13 + description: touch channel status of touch pad 13 + addressOffset: 212 + size: 32 + fields: + - name: SAR_TOUCH_PAD13_DATA + description: touch data debounce of touch pad 13 + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: SAR_TOUCH_PAD13_DEBOUNCE + description: touch current debounce of touch pad 13 + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS14 + description: touch channel status of touch pad 14 + addressOffset: 216 + size: 32 + fields: + - name: SAR_TOUCH_PAD14_DATA + description: touch data debounce of touch pad 14 + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: SAR_TOUCH_PAD14_DEBOUNCE + description: touch current debounce of touch pad 14 + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS15 + description: touch channel status of sleep pad + addressOffset: 220 + size: 32 + fields: + - name: SAR_TOUCH_SLP_DATA + description: touch data debounce of sleep pad + bitOffset: 0 + bitWidth: 22 + access: read-only + - name: SAR_TOUCH_SLP_DEBOUNCE + description: touch current debounce of sleep pad + bitOffset: 29 + bitWidth: 3 + access: read-only + - register: + name: SAR_TOUCH_STATUS16 + description: touch channel status of approach mode + addressOffset: 224 + size: 32 + fields: + - name: SAR_TOUCH_APPROACH_PAD2_CNT + description: touch current approach count of approach pad2 + bitOffset: 0 + bitWidth: 8 + access: read-only + - name: SAR_TOUCH_APPROACH_PAD1_CNT + description: touch current approach count of approach pad1 + bitOffset: 8 + bitWidth: 8 + access: read-only + - name: SAR_TOUCH_APPROACH_PAD0_CNT + description: touch current approach count of approach pad0 + bitOffset: 16 + bitWidth: 8 + access: read-only + - name: SAR_TOUCH_SLP_APPROACH_CNT + description: touch current approach count of slp pad + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: SAR_COCPU_STATE + description: get cocpu status + addressOffset: 228 + size: 32 + fields: + - name: SAR_COCPU_DBG_TRIGGER + description: trigger cocpu debug registers + bitOffset: 25 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_CLK_EN_ST + description: check cocpu whether clk on + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_RESET_N + description: check cocpu whether in reset state + bitOffset: 27 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_EOI + description: check cocpu whether in interrupt state + bitOffset: 28 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TRAP + description: check cocpu whether in trap state + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_EBREAK + description: check cocpu whether in ebreak + bitOffset: 30 + bitWidth: 1 + access: read-only + - register: + name: SAR_COCPU_INT_RAW + description: the interrupt raw of ulp + addressOffset: 232 + size: 32 + fields: + - name: SAR_COCPU_TOUCH_DONE_INT_RAW + description: int from touch done + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TOUCH_INACTIVE_INT_RAW + description: int from touch inactive + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TOUCH_ACTIVE_INT_RAW + description: int from touch active + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_SARADC1_INT_RAW + description: int from saradc1 + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_SARADC2_INT_RAW + description: int from saradc2 + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TSENS_INT_RAW + description: int from tsens + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_START_INT_RAW + description: int from start + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_SW_INT_RAW + description: int from software + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_SWD_INT_RAW + description: int from super watch dog + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TOUCH_TIMEOUT_INT_RAW + description: int from timeout done + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW + description: int from approach loop done + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TOUCH_SCAN_DONE_INT_RAW + description: int from touch scan done + bitOffset: 11 + bitWidth: 1 + access: read-only + - register: + name: SAR_COCPU_INT_ENA + description: the interrupt enable of ulp + addressOffset: 236 + size: 32 + fields: + - name: SAR_COCPU_TOUCH_DONE_INT_ENA + description: int enable of touch done + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SAR_COCPU_TOUCH_INACTIVE_INT_ENA + description: int enable of from touch inactive + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SAR_COCPU_TOUCH_ACTIVE_INT_ENA + description: int enable of touch active + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SAR_COCPU_SARADC1_INT_ENA + description: int enable of from saradc1 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SAR_COCPU_SARADC2_INT_ENA + description: int enable of from saradc2 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SAR_COCPU_TSENS_INT_ENA + description: int enable of tsens + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SAR_COCPU_START_INT_ENA + description: int enable of start + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SAR_COCPU_SW_INT_ENA + description: int enable of software + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SAR_COCPU_SWD_INT_ENA + description: int enable of super watch dog + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SAR_COCPU_TOUCH_TIMEOUT_INT_ENA + description: int enable of timeout done + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA + description: int enable of approach loop done + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA + description: int enable of touch scan done + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: SAR_COCPU_INT_ST + description: the interrupt state of ulp + addressOffset: 240 + size: 32 + fields: + - name: SAR_COCPU_TOUCH_DONE_INT_ST + description: int state of touch done + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TOUCH_INACTIVE_INT_ST + description: int state of from touch inactive + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TOUCH_ACTIVE_INT_ST + description: int state of touch active + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_SARADC1_INT_ST + description: int state of from saradc1 + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_SARADC2_INT_ST + description: int state of from saradc2 + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TSENS_INT_ST + description: int state of tsens + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_START_INT_ST + description: int state of start + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_SW_INT_ST + description: int state of software + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_SWD_INT_ST + description: int state of super watch dog + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TOUCH_TIMEOUT_INT_ST + description: int state of timeout done + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST + description: int state of approach loop done + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_TOUCH_SCAN_DONE_INT_ST + description: int state of touch scan done + bitOffset: 11 + bitWidth: 1 + access: read-only + - register: + name: SAR_COCPU_INT_CLR + description: the interrupt clear of ulp + addressOffset: 244 + size: 32 + fields: + - name: SAR_COCPU_TOUCH_DONE_INT_CLR + description: int clear of touch done + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_TOUCH_INACTIVE_INT_CLR + description: int clear of from touch inactive + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_TOUCH_ACTIVE_INT_CLR + description: int clear of touch active + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_SARADC1_INT_CLR + description: int clear of from saradc1 + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_SARADC2_INT_CLR + description: int clear of from saradc2 + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_TSENS_INT_CLR + description: int clear of tsens + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_START_INT_CLR + description: int clear of start + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_SW_INT_CLR + description: int clear of software + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_SWD_INT_CLR + description: int clear of super watch dog + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_TOUCH_TIMEOUT_INT_CLR + description: int clear of timeout done + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR + description: int clear of approach loop done + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_TOUCH_SCAN_DONE_INT_CLR + description: int clear of touch scan done + bitOffset: 11 + bitWidth: 1 + access: write-only + - register: + name: SAR_COCPU_DEBUG + description: Ulp-riscv debug signal + addressOffset: 248 + size: 32 + fields: + - name: SAR_COCPU_PC + description: cocpu Program counter + bitOffset: 0 + bitWidth: 13 + access: read-only + - name: SAR_COCPU_MEM_VLD + description: cocpu mem valid output + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_MEM_RDY + description: cocpu mem ready input + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SAR_COCPU_MEM_WEN + description: cocpu mem write enable output + bitOffset: 15 + bitWidth: 4 + access: read-only + - name: SAR_COCPU_MEM_ADDR + description: cocpu mem address output + bitOffset: 19 + bitWidth: 13 + access: read-only + - register: + name: SAR_HALL_CTRL + description: no public + addressOffset: 252 + size: 32 + resetValue: 2684354560 + fields: + - name: XPD_HALL + description: Power on hall sensor and connect to VP and VN + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: XPD_HALL_FORCE + description: "1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor" + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: HALL_PHASE + description: Reverse phase of hall sensor + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: HALL_PHASE_FORCE + description: "1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor" + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAR_NOUSE + description: no public + addressOffset: 256 + size: 32 + fields: + - name: SAR_NOUSE + description: no public + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SAR_PERI_CLK_GATE_CONF + description: the peri clock gate of rtc peri + addressOffset: 260 + size: 32 + fields: + - name: RTC_I2C_CLK_EN + description: enable rtc i2c clock + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: TSENS_CLK_EN + description: enable tsens clock + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SARADC_CLK_EN + description: enbale saradc clock + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: IOMUX_CLK_EN + description: enable io_mux clock + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: SAR_PERI_RESET_CONF + description: the peri reset of rtc peri + addressOffset: 264 + size: 32 + fields: + - name: SAR_COCPU_RESET + description: enable ulp-riscv reset + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: SAR_RTC_I2C_RESET + description: Reserved. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SAR_TSENS_RESET + description: enbale saradc reset + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SAR_SARADC_RESET + description: enable io_mux reset + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: SAR_COCPU_INT_ENA_W1TS + description: the interrupt enable of ulp + addressOffset: 268 + size: 32 + fields: + - name: SAR_COCPU_TOUCH_DONE_INT_ENA_W1TS + description: int enable of touch done + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS + description: int enable of from touch inactive + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS + description: int enable of touch active + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_SARADC1_INT_ENA_W1TS + description: int enable of from saradc1 + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_SARADC2_INT_ENA_W1TS + description: int enable of from saradc2 + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_TSENS_INT_ENA_W1TS + description: int enable of tsens + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_START_INT_ENA_W1TS + description: int enable of start + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_SW_INT_ENA_W1TS + description: int enable of software + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_SWD_INT_ENA_W1TS + description: int enable of super watch dog + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS + description: int enable of timeout done + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS + description: int enable of approach loop done + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS + description: int enable of touch scan done + bitOffset: 11 + bitWidth: 1 + access: write-only + - register: + name: SAR_COCPU_INT_ENA_W1TC + description: the interrupt enable clear of ulp + addressOffset: 272 + size: 32 + fields: + - name: SAR_COCPU_TOUCH_DONE_INT_ENA_W1TC + description: Clear int enable of touch done + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC + description: Clear int enable of from touch inactive + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC + description: Clear int enable of touch active + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_SARADC1_INT_ENA_W1TC + description: Clear int enable of from saradc1 + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_SARADC2_INT_ENA_W1TC + description: Clear int enable of from saradc2 + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_TSENS_INT_ENA_W1TC + description: Clear int enable of tsens + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_START_INT_ENA_W1TC + description: Clear int enable of start + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_SW_INT_ENA_W1TC + description: Clear int enable of software + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_SWD_INT_ENA_W1TC + description: Clear int enable of super watch dog + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC + description: Clear int enable of timeout done + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC + description: Clear int enable of approach loop done + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SAR_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC + description: Clear int enable of touch scan done + bitOffset: 11 + bitWidth: 1 + access: write-only + - register: + name: SAR_DEBUG_CONF + description: rtc peri debug configure + addressOffset: 276 + size: 32 + fields: + - name: SAR_DEBUG_BIT_SEL + description: no public + bitOffset: 0 + bitWidth: 5 + access: read-write + - register: + name: SAR_SARDATE + description: version + addressOffset: 508 + size: 32 + resetValue: 34607488 + fields: + - name: SAR_DATE + description: version + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SENSITIVE + description: SENSITIVE Peripheral + groupName: SENSITIVE + baseAddress: 1611403264 + addressBlock: + - offset: 0 + size: 788 + usage: registers + registers: + - register: + name: CACHE_DATAARRAY_CONNECT_0 + description: Cache data array configuration register 0. + addressOffset: 0 + size: 32 + fields: + - name: CACHE_DATAARRAY_CONNECT_LOCK + description: Set 1 to lock cache data array registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CACHE_DATAARRAY_CONNECT_1 + description: Cache data array configuration register 1. + addressOffset: 4 + size: 32 + resetValue: 255 + fields: + - name: CACHE_DATAARRAY_CONNECT_FLATTEN + description: Cache data array connection configuration. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: APB_PERIPHERAL_ACCESS_0 + description: APB peripheral configuration register 0. + addressOffset: 8 + size: 32 + fields: + - name: APB_PERIPHERAL_ACCESS_LOCK + description: Set 1 to lock APB peripheral Configuration Register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: APB_PERIPHERAL_ACCESS_1 + description: APB peripheral configuration register 1. + addressOffset: 12 + size: 32 + resetValue: 1 + fields: + - name: APB_PERIPHERAL_ACCESS_SPLIT_BURST + description: Set 1 to support split function for AHB access to APB peripherals. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: INTERNAL_SRAM_USAGE_0 + description: Internal SRAM configuration register 0. + addressOffset: 16 + size: 32 + fields: + - name: INTERNAL_SRAM_USAGE_LOCK + description: Set 1 to lock internal SRAM Configuration Register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: INTERNAL_SRAM_USAGE_1 + description: Internal SRAM configuration register 1. + addressOffset: 20 + size: 32 + resetValue: 2047 + fields: + - name: INTERNAL_SRAM_ICACHE_USAGE + description: Set 1 to someone bit means corresponding internal SRAM level can be accessed by icache. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: INTERNAL_SRAM_DCACHE_USAGE + description: Set 1 to someone bit means corresponding internal SRAM level can be accessed by dcache. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: INTERNAL_SRAM_CPU_USAGE + description: Set 1 to someone bit means corresponding internal SRAM level can be accessed by cpu. + bitOffset: 4 + bitWidth: 7 + access: read-write + - register: + name: INTERNAL_SRAM_USAGE_2 + description: Internal SRAM configuration register 2. + addressOffset: 24 + size: 32 + fields: + - name: INTERNAL_SRAM_CORE0_TRACE_USAGE + description: Set 1 to someone bit means corresponding internal SRAM level can be accessed by core0 trace bus. + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: INTERNAL_SRAM_CORE1_TRACE_USAGE + description: Set 1 to someone bit means corresponding internal SRAM level can be accessed by core1 trace bus. + bitOffset: 7 + bitWidth: 7 + access: read-write + - name: INTERNAL_SRAM_CORE0_TRACE_ALLOC + description: Which internal SRAM bank (16KB) of 64KB can be accessed by core0 trace bus. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: INTERNAL_SRAM_CORE1_TRACE_ALLOC + description: Which internal SRAM bank (16KB) of 64KB can be accessed by core1 trace bus. + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: INTERNAL_SRAM_USAGE_3 + description: Internal SRAM configuration register 3. + addressOffset: 28 + size: 32 + fields: + - name: INTERNAL_SRAM_MAC_DUMP_USAGE + description: Set 1 to someone bit means corresponding internal SRAM level can be accessed by mac dump. + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: INTERNAL_SRAM_USAGE_4 + description: Internal SRAM configuration register 4. + addressOffset: 32 + size: 32 + fields: + - name: INTERNAL_SRAM_LOG_USAGE + description: Set 1 to someone bit means corresponding internal SRAM level can be accessed by log bus. + bitOffset: 0 + bitWidth: 7 + access: read-write + - register: + name: RETENTION_DISABLE + description: Retention configuration register. + addressOffset: 36 + size: 32 + fields: + - name: RETENTION_DISABLE + description: Set 1 to disable retention function and lock disable state. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CACHE_TAG_ACCESS_0 + description: Cache tag configuration register 0. + addressOffset: 40 + size: 32 + fields: + - name: CACHE_TAG_ACCESS_LOCK + description: Set 1 to lock cache tag Configuration Register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CACHE_TAG_ACCESS_1 + description: Cache tag configuration register 1. + addressOffset: 44 + size: 32 + resetValue: 15 + fields: + - name: PRO_I_TAG_RD_ACS + description: Set 1 to enable Icache read access tag memory. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_I_TAG_WR_ACS + description: Set 1 to enable Icache wrtie access tag memory. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PRO_D_TAG_RD_ACS + description: Set 1 to enable Dcache read access tag memory. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PRO_D_TAG_WR_ACS + description: Set 1 to enable Dcache wrtie access tag memory. + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: CACHE_MMU_ACCESS_0 + description: Cache MMU configuration register 0. + addressOffset: 48 + size: 32 + fields: + - name: CACHE_MMU_ACCESS_LOCK + description: Set 1 to lock cache MMU registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CACHE_MMU_ACCESS_1 + description: Cache MMU configuration register 1. + addressOffset: 52 + size: 32 + resetValue: 3 + fields: + - name: PRO_MMU_RD_ACS + description: Set 1 to enable read access MMU memory. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PRO_MMU_WR_ACS + description: Set 1 to enable write access MMU memory. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_SPI2_PMS_CONSTRAIN_0 + description: spi2 dma permission configuration register 0. + addressOffset: 56 + size: 32 + fields: + - name: DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK + description: Set 1 to lock spi2 dma permission Configuration Register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_SPI2_PMS_CONSTRAIN_1 + description: spi2 dma permission configuration register 1. + addressOffset: 60 + size: 32 + resetValue: 4095 + fields: + - name: DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0 + description: "spi2's permission(store,load) in data region0 of SRAM" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1 + description: "spi2's permission(store,load) in data region1 of SRAM" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2 + description: "spi2's permission(store,load) in data region2 of SRAM" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3 + description: "spi2's permission(store,load) in data region3 of SRAM" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + description: "spi2's permission(store,load) in dcache data sram block0" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + description: "spi2's permission(store,load) in dcache data sram block1" + bitOffset: 10 + bitWidth: 2 + access: read-write + - register: + name: DMA_APBPERI_SPI3_PMS_CONSTRAIN_0 + description: spi3 dma permission configuration register 0. + addressOffset: 64 + size: 32 + fields: + - name: DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK + description: Set 1 to lock spi3 dma permission Configuration Register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_SPI3_PMS_CONSTRAIN_1 + description: spi3 dma permission configuration register 1. + addressOffset: 68 + size: 32 + resetValue: 4095 + fields: + - name: DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0 + description: "spi3's permission(store,load) in data region0 of SRAM" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1 + description: "spi3's permission(store,load) in data region1 of SRAM" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2 + description: "spi3's permission(store,load) in data region2 of SRAM" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3 + description: "spi3's permission(store,load) in data region3 of SRAM" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + description: "spi3's permission(store,load) in dcache data sram block0" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + description: "spi3's permission(store,load) in dcache data sram block1" + bitOffset: 10 + bitWidth: 2 + access: read-write + - register: + name: DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0 + description: uhci0 dma permission configuration register 0. + addressOffset: 72 + size: 32 + fields: + - name: DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK + description: Set 1 to lock uhci0 dma permission Configuration Register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1 + description: uhci0 dma permission configuration register 1. + addressOffset: 76 + size: 32 + resetValue: 4095 + fields: + - name: DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0 + description: "uhci0's permission(store,load) in data region0 of SRAM" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1 + description: "uhci0's permission(store,load) in data region1 of SRAM" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2 + description: "uhci0's permission(store,load) in data region2 of SRAM" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3 + description: "uhci0's permission(store,load) in data region3 of SRAM" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + description: "uhci0's permission(store,load) in dcache data sram block0" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + description: "uhci0's permission(store,load) in dcache data sram block1" + bitOffset: 10 + bitWidth: 2 + access: read-write + - register: + name: DMA_APBPERI_I2S0_PMS_CONSTRAIN_0 + description: i2s0 dma permission configuration register 0. + addressOffset: 80 + size: 32 + fields: + - name: DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK + description: Set 1 to lock i2s0 dma permission Configuration Register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_I2S0_PMS_CONSTRAIN_1 + description: i2s0 dma permission configuration register 1. + addressOffset: 84 + size: 32 + resetValue: 4095 + fields: + - name: DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0 + description: "i2s0's permission(store,load) in data region0 of SRAM" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1 + description: "i2s0's permission(store,load) in data region1 of SRAM" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2 + description: "i2s0's permission(store,load) in data region2 of SRAM" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3 + description: "i2s0's permission(store,load) in data region3 of SRAM" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + description: "i2s0's permission(store,load) in dcache data sram block0" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + description: "i2s0's permission(store,load) in dcache data sram block1" + bitOffset: 10 + bitWidth: 2 + access: read-write + - register: + name: DMA_APBPERI_I2S1_PMS_CONSTRAIN_0 + description: i2s1 dma permission configuration register 0. + addressOffset: 88 + size: 32 + fields: + - name: DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK + description: Set 1 to lock i2s1 dma permission Configuration Register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_I2S1_PMS_CONSTRAIN_1 + description: i2s1 dma permission configuration register 1. + addressOffset: 92 + size: 32 + resetValue: 4095 + fields: + - name: DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0 + description: "i2s1's permission(store,load) in data region0 of SRAM" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1 + description: "i2s1's permission(store,load) in data region1 of SRAM" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2 + description: "i2s1's permission(store,load) in data region2 of SRAM" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3 + description: "i2s1's permission(store,load) in data region3 of SRAM" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + description: "i2s1's permission(store,load) in dcache data sram block0" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + description: "i2s1's permission(store,load) in dcache data sram block1" + bitOffset: 10 + bitWidth: 2 + access: read-write + - register: + name: DMA_APBPERI_MAC_PMS_CONSTRAIN_0 + description: mac dma permission configuration register 0. + addressOffset: 96 + size: 32 + fields: + - name: DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK + description: Set 1 to lock mac dma permission Configuration Register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_MAC_PMS_CONSTRAIN_1 + description: mac dma permission configuration register 1. + addressOffset: 100 + size: 32 + resetValue: 4095 + fields: + - name: DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0 + description: "mac's permission(store,load) in data region0 of SRAM" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1 + description: "mac's permission(store,load) in data region1 of SRAM" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2 + description: "mac's permission(store,load) in data region2 of SRAM" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3 + description: "mac's permission(store,load) in data region3 of SRAM" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + description: "mac's permission(store,load) in dcache data sram block0" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + description: "mac's permission(store,load) in dcache data sram block1" + bitOffset: 10 + bitWidth: 2 + access: read-write + - register: + name: DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0 + description: backup dma permission configuration register 0. + addressOffset: 104 + size: 32 + fields: + - name: DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK + description: Set 1 to lock backup dma permission Configuration Register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1 + description: backup dma permission configuration register 1. + addressOffset: 108 + size: 32 + resetValue: 4095 + fields: + - name: DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0 + description: "backup's permission(store,load) in data region0 of SRAM" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1 + description: "backup's permission(store,load) in data region1 of SRAM" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2 + description: "backup's permission(store,load) in data region2 of SRAM" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3 + description: "backup's permission(store,load) in data region3 of SRAM" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + description: "backup's permission(store,load) in dcache data sram block0" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + description: "backup's permission(store,load) in dcache data sram block1" + bitOffset: 10 + bitWidth: 2 + access: read-write + - register: + name: DMA_APBPERI_AES_PMS_CONSTRAIN_0 + description: aes dma permission configuration register 0. + addressOffset: 112 + size: 32 + fields: + - name: DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK + description: Set 1 to lock aes dma permission Configuration Register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_AES_PMS_CONSTRAIN_1 + description: aes dma permission configuration register 1. + addressOffset: 116 + size: 32 + resetValue: 4095 + fields: + - name: DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0 + description: "aes's permission(store,load) in data region0 of SRAM" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1 + description: "aes's permission(store,load) in data region1 of SRAM" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2 + description: "aes's permission(store,load) in data region2 of SRAM" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3 + description: "aes's permission(store,load) in data region3 of SRAM" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + description: "aes's permission(store,load) in dcache data sram block0" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + description: "aes's permission(store,load) in dcache data sram block1" + bitOffset: 10 + bitWidth: 2 + access: read-write + - register: + name: DMA_APBPERI_SHA_PMS_CONSTRAIN_0 + description: sha dma permission configuration register 0. + addressOffset: 120 + size: 32 + fields: + - name: DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK + description: Set 1 to lock sha dma permission Configuration Register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_SHA_PMS_CONSTRAIN_1 + description: sha dma permission configuration register 1. + addressOffset: 124 + size: 32 + resetValue: 4095 + fields: + - name: DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0 + description: "sha's permission(store,load) in data region0 of SRAM" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1 + description: "sha's permission(store,load) in data region1 of SRAM" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2 + description: "sha's permission(store,load) in data region2 of SRAM" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3 + description: "sha's permission(store,load) in data region3 of SRAM" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + description: "sha's permission(store,load) in dcache data sram block0" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + description: "sha's permission(store,load) in dcache data sram block1" + bitOffset: 10 + bitWidth: 2 + access: read-write + - register: + name: DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0 + description: adc_dac dma permission configuration register 0. + addressOffset: 128 + size: 32 + fields: + - name: DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK + description: Set 1 to lock adc_dac dma permission Configuration Register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1 + description: adc_dac dma permission configuration register 1. + addressOffset: 132 + size: 32 + resetValue: 4095 + fields: + - name: DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0 + description: "adc_dac's permission(store,load) in data region0 of SRAM" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1 + description: "adc_dac's permission(store,load) in data region1 of SRAM" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2 + description: "adc_dac's permission(store,load) in data region2 of SRAM" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3 + description: "adc_dac's permission(store,load) in data region3 of SRAM" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + description: "adc_dac's permission(store,load) in dcache data sram block0" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + description: "adc_dac's permission(store,load) in dcache data sram block1" + bitOffset: 10 + bitWidth: 2 + access: read-write + - register: + name: DMA_APBPERI_RMT_PMS_CONSTRAIN_0 + description: rmt dma permission configuration register 0. + addressOffset: 136 + size: 32 + fields: + - name: DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK + description: Set 1 to lock rmt dma permission Configuration Register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_RMT_PMS_CONSTRAIN_1 + description: rmt dma permission configuration register 1. + addressOffset: 140 + size: 32 + resetValue: 4095 + fields: + - name: DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0 + description: "rmt's permission(store,load) in data region0 of SRAM" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1 + description: "rmt's permission(store,load) in data region1 of SRAM" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2 + description: "rmt's permission(store,load) in data region2 of SRAM" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3 + description: "rmt's permission(store,load) in data region3 of SRAM" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + description: "rmt's permission(store,load) in dcache data sram block0" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + description: "rmt's permission(store,load) in dcache data sram block1" + bitOffset: 10 + bitWidth: 2 + access: read-write + - register: + name: DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0 + description: lcd_cam dma permission configuration register 0. + addressOffset: 144 + size: 32 + fields: + - name: DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK + description: Set 1 to lock lcd_cam dma permission Configuration Register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1 + description: lcd_cam dma permission configuration register 1. + addressOffset: 148 + size: 32 + resetValue: 4095 + fields: + - name: DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0 + description: "lcd_cam's permission(store,load) in data region0 of SRAM" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1 + description: "lcd_cam's permission(store,load) in data region1 of SRAM" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2 + description: "lcd_cam's permission(store,load) in data region2 of SRAM" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3 + description: "lcd_cam's permission(store,load) in data region3 of SRAM" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + description: "lcd_cam's permission(store,load) in dcache data sram block0" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + description: "lcd_cam's permission(store,load) in dcache data sram block1" + bitOffset: 10 + bitWidth: 2 + access: read-write + - register: + name: DMA_APBPERI_USB_PMS_CONSTRAIN_0 + description: usb dma permission configuration register 0. + addressOffset: 152 + size: 32 + fields: + - name: DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK + description: Set 1 to lock usb dma permission Configuration Register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_USB_PMS_CONSTRAIN_1 + description: usb dma permission configuration register 1. + addressOffset: 156 + size: 32 + resetValue: 4095 + fields: + - name: DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0 + description: "usb's permission(store,load) in data region0 of SRAM" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1 + description: "usb's permission(store,load) in data region1 of SRAM" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2 + description: "usb's permission(store,load) in data region2 of SRAM" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3 + description: "usb's permission(store,load) in data region3 of SRAM" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + description: "usb's permission(store,load) in dcache data sram block0" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + description: "usb's permission(store,load) in dcache data sram block1" + bitOffset: 10 + bitWidth: 2 + access: read-write + - register: + name: DMA_APBPERI_LC_PMS_CONSTRAIN_0 + description: lc dma permission configuration register 0. + addressOffset: 160 + size: 32 + fields: + - name: DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK + description: Set 1 to lock lc dma permission Configuration Register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_LC_PMS_CONSTRAIN_1 + description: lc dma permission configuration register 1. + addressOffset: 164 + size: 32 + resetValue: 4095 + fields: + - name: DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0 + description: "lc's permission(store,load) in data region0 of SRAM" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1 + description: "lc's permission(store,load) in data region1 of SRAM" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2 + description: "lc's permission(store,load) in data region2 of SRAM" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3 + description: "lc's permission(store,load) in data region3 of SRAM" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + description: "lc's permission(store,load) in dcache data sram block0" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + description: "lc's permission(store,load) in dcache data sram block1" + bitOffset: 10 + bitWidth: 2 + access: read-write + - register: + name: DMA_APBPERI_SDIO_PMS_CONSTRAIN_0 + description: sdio dma permission configuration register 0. + addressOffset: 168 + size: 32 + fields: + - name: DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK + description: Set 1 to lock sdio dma permission Configuration Register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_SDIO_PMS_CONSTRAIN_1 + description: sdio dma permission configuration register 1. + addressOffset: 172 + size: 32 + resetValue: 4095 + fields: + - name: DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0 + description: "sdio's permission(store,load) in data region0 of SRAM" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1 + description: "sdio's permission(store,load) in data region1 of SRAM" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2 + description: "sdio's permission(store,load) in data region2 of SRAM" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3 + description: "sdio's permission(store,load) in data region3 of SRAM" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 + description: "sdio's permission(store,load) in dcache data sram block0" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 + description: "sdio's permission(store,load) in dcache data sram block1" + bitOffset: 10 + bitWidth: 2 + access: read-write + - register: + name: DMA_APBPERI_PMS_MONITOR_0 + description: dma permission monitor configuration register 0. + addressOffset: 176 + size: 32 + fields: + - name: DMA_APBPERI_PMS_MONITOR_LOCK + description: Set 1 to lock dma permission monitor Configuration Register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_PMS_MONITOR_1 + description: dma permission monitor configuration register 1. + addressOffset: 180 + size: 32 + resetValue: 3 + fields: + - name: DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR + description: Set 1 to clear dma_pms_monitor_violate interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DMA_APBPERI_PMS_MONITOR_VIOLATE_EN + description: "Set 1 to enable dma pms monitor, if dma access violated permission, will trigger interrupt." + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: DMA_APBPERI_PMS_MONITOR_2 + description: dma permission monitor configuration register 2. + addressOffset: 184 + size: 32 + fields: + - name: DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR + description: "recorded dma's interrupt status when dma access violated permission" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD + description: "recorded dma's world status when dma access violated permission" + bitOffset: 1 + bitWidth: 2 + access: read-only + - name: DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR + description: "recorded dma's address bit[25:4] status when dma access violated permission, real address is 0x3c00_0000+addr*16" + bitOffset: 3 + bitWidth: 22 + access: read-only + - register: + name: DMA_APBPERI_PMS_MONITOR_3 + description: dma permission monitor configuration register 3. + addressOffset: 188 + size: 32 + fields: + - name: DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR + description: "recorded dma's write status when dma access violated permission, 1(write), 0(read)" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN + description: "recorded dma's byte enable status when dma access violated permission" + bitOffset: 1 + bitWidth: 16 + access: read-only + - register: + name: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0 + description: sram split line configuration register 0 + addressOffset: 192 + size: 32 + fields: + - name: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK + description: Set 1 to lock sram split configuration register + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1 + description: sram split line configuration register 1 + addressOffset: 196 + size: 32 + fields: + - name: CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 + description: "category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 + description: "category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 + description: "category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3 + description: "category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4 + description: "category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5 + description: "category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6 + description: "category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00" + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR + description: "splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address" + bitOffset: 14 + bitWidth: 8 + access: read-write + - register: + name: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2 + description: sram split line configuration register 1 + addressOffset: 200 + size: 32 + fields: + - name: CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 + description: "category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 + description: "category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 + description: "category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3 + description: "category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4 + description: "category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5 + description: "category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6 + description: "category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00" + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR + description: "splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address" + bitOffset: 14 + bitWidth: 8 + access: read-write + - register: + name: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3 + description: sram split line configuration register 1 + addressOffset: 204 + size: 32 + fields: + - name: CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 + description: "category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 + description: "category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 + description: "category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3 + description: "category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4 + description: "category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5 + description: "category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6 + description: "category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00" + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR + description: "splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address" + bitOffset: 14 + bitWidth: 8 + access: read-write + - register: + name: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4 + description: sram split line configuration register 1 + addressOffset: 208 + size: 32 + fields: + - name: CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 + description: "category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 + description: "category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 + description: "category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3 + description: "category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4 + description: "category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5 + description: "category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6 + description: "category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00" + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR + description: "splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address" + bitOffset: 14 + bitWidth: 8 + access: read-write + - register: + name: CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5 + description: sram split line configuration register 1 + addressOffset: 212 + size: 32 + fields: + - name: CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 + description: "category0 of core_x_iram0_dram_dma_line, if the splitaddress in block0 of SRAM, configured as 0x10, else if the splitaddress below block0 of SRAM, configured as 0x11, else if splitaddress higher than block0 of SRAM, configured as 0x00" + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 + description: "category1 of core_x_iram0_dram_dma_line, if the splitaddress in block1 of SRAM, configured as 0x10, else if the splitaddress below block1 of SRAM, configured as 0x11, else if splitaddress higher than block1 of SRAM, configured as 0x00" + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 + description: "category2 of core_x_iram0_dram_dma_line, if the splitaddress in block2 of SRAM, configured as 0x10, else if the splitaddress below block2 of SRAM, configured as 0x11, else if splitaddress higher than block2 of SRAM, configured as 0x00" + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3 + description: "category3 of core_x_iram0_dram_dma_line, if the splitaddress in block3 of SRAM, configured as 0x10, else if the splitaddress below block3 of SRAM, configured as 0x11, else if splitaddress higher than block3 of SRAM, configured as 0x00" + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4 + description: "category4 of core_x_iram0_dram_dma_line, if the splitaddress in block4 of SRAM, configured as 0x10, else if the splitaddress below block4 of SRAM, configured as 0x11, else if splitaddress higher than block4 of SRAM, configured as 0x00" + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5 + description: "category5 of core_x_iram0_dram_dma_line, if the splitaddress in block5 of SRAM, configured as 0x10, else if the splitaddress below block5 of SRAM, configured as 0x11, else if splitaddress higher than block5 of SRAM, configured as 0x00" + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6 + description: "category6 of core_x_iram0_dram_dma_line, if the splitaddress in block6 of SRAM, configured as 0x10, else if the splitaddress below block6 of SRAM, configured as 0x11, else if splitaddress higher than block6 of SRAM, configured as 0x00" + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR + description: "splitaddr of core_x_iram0_dram_dma_line, configured as [15:8]bit of actual address" + bitOffset: 14 + bitWidth: 8 + access: read-write + - register: + name: CORE_X_IRAM0_PMS_CONSTRAIN_0 + description: corex iram0 permission configuration register 0 + addressOffset: 216 + size: 32 + fields: + - name: CORE_X_IRAM0_PMS_CONSTRAIN_LOCK + description: Set 1 to lock corex iram0 permission configuration register + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_X_IRAM0_PMS_CONSTRAIN_1 + description: corex iram0 permission configuration register 0 + addressOffset: 220 + size: 32 + resetValue: 2097151 + fields: + - name: CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + description: "core0/core1's permission of instruction region0 of SRAM in world1" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + description: "core0/core1's permission of instruction region1 of SRAM in world1" + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + description: "core0/core1's permission of instruction region2 of SRAM in world1" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + description: "core0/core1's permission of instruction region3 of SRAM in world1" + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 + description: "core0/core1's permission of icache data sram block0 in world1" + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 + description: "core0/core1's permission of icache data sram block1 in world1" + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS + description: "core0/core1's permission of rom in world1" + bitOffset: 18 + bitWidth: 3 + access: read-write + - register: + name: CORE_X_IRAM0_PMS_CONSTRAIN_2 + description: corex iram0 permission configuration register 1 + addressOffset: 224 + size: 32 + resetValue: 2097151 + fields: + - name: CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + description: "core0/core1's permission of instruction region0 of SRAM in world1" + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + description: "core0/core1's permission of instruction region1 of SRAM in world1" + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + description: "core0/core1's permission of instruction region2 of SRAM in world1" + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + description: "core0/core1's permission of instruction region3 of SRAM in world1" + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 + description: "core0/core1's permission of icache data sram block0 in world1" + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 + description: "core0/core1's permission of icache data sram block1 in world1" + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS + description: "core0/core1's permission of rom in world1" + bitOffset: 18 + bitWidth: 3 + access: read-write + - register: + name: CORE_0_IRAM0_PMS_MONITOR_0 + description: core0 iram0 permission monitor configuration register 0 + addressOffset: 228 + size: 32 + fields: + - name: CORE_0_IRAM0_PMS_MONITOR_LOCK + description: Set 1 to lock core0 iram0 permission monitor register + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_IRAM0_PMS_MONITOR_1 + description: core0 iram0 permission monitor configuration register 1 + addressOffset: 232 + size: 32 + resetValue: 3 + fields: + - name: CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR + description: Set 1 to clear core0 iram0 permission violated interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN + description: "Set 1 to enable core0 iram0 permission monitor, when core0_iram violated permission, will trigger interrupt" + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_IRAM0_PMS_MONITOR_2 + description: core0 iram0 permission monitor configuration register 2 + addressOffset: 236 + size: 32 + fields: + - name: CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR + description: recorded core0 iram0 pms monitor interrupt status. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR + description: "recorded core0 iram0 wr status, only if loadstore is 1 have meaning, 1(store), 0(load)." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE + description: "recorded core0 iram0 loadstore status, indicated the type of operation, 0(fetch), 1(load/store)." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD + description: "recorded core0 iram0 world status, 0x01 means world0, 0x10 means world1." + bitOffset: 3 + bitWidth: 2 + access: read-only + - name: CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR + description: "recorded core0 iram0 address [25:2] status when core0 iram0 violated permission, the real address is 0x40000000+addr*4" + bitOffset: 5 + bitWidth: 24 + access: read-only + - register: + name: CORE_1_IRAM0_PMS_MONITOR_0 + description: core1 iram0 permission monitor configuration register 0 + addressOffset: 240 + size: 32 + fields: + - name: CORE_1_IRAM0_PMS_MONITOR_LOCK + description: Set 1 to lock core1 iram0 permission monitor register + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_1_IRAM0_PMS_MONITOR_1 + description: core1 iram0 permission monitor configuration register 1 + addressOffset: 244 + size: 32 + resetValue: 3 + fields: + - name: CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR + description: Set 1 to clear core1 iram0 permission violated interrupt + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN + description: "Set 1 to enable core1 iram0 permission monitor, when core1_iram violated permission, will trigger interrupt" + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CORE_1_IRAM0_PMS_MONITOR_2 + description: core1 iram0 permission monitor configuration register 2 + addressOffset: 248 + size: 32 + fields: + - name: CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR + description: recorded core1 iram0 pms monitor interrupt status. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR + description: "recorded core1 iram0 wr status, only if loadstore is 1 have meaning, 1(store), 0(load)." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE + description: "recorded core1 iram0 loadstore status, indicated the type of operation, 0(fetch), 1(load/store)." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD + description: "recorded core1 iram0 world status, 0x01 means world0, 0x10 means world1." + bitOffset: 3 + bitWidth: 2 + access: read-only + - name: CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR + description: "recorded core1 iram0 address [25:2] status when core1 iram0 violated permission, the real address is 0x40000000+addr*4" + bitOffset: 5 + bitWidth: 24 + access: read-only + - register: + name: CORE_X_DRAM0_PMS_CONSTRAIN_0 + description: corex dram0 permission configuration register 0 + addressOffset: 252 + size: 32 + fields: + - name: CORE_X_DRAM0_PMS_CONSTRAIN_LOCK + description: Set 1 to lock corex dram0 permission configuration register + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_X_DRAM0_PMS_CONSTRAIN_1 + description: corex dram0 permission configuration register 1 + addressOffset: 256 + size: 32 + resetValue: 268435455 + fields: + - name: CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 + description: "core0/core1's permission of data region0 of SRAM in world0." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 + description: "core0/core1's permission of data region1 of SRAM in world0." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 + description: "core0/core1's permission of data region2 of SRAM in world0." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 + description: "core0/core1's permission of data region3 of SRAM in world0." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 + description: "core0/core1's permission of dcache data sram block0 in world0." + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 + description: "core0/core1's permission of dcache data sram block1 in world0." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 + description: "core0/core1's permission of data region0 of SRAM in world1." + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 + description: "core0/core1's permission of data region1 of SRAM in world1." + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 + description: "core0/core1's permission of data region2 of SRAM in world1." + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 + description: "core0/core1's permission of data region3 of SRAM in world1." + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 + description: "core0/core1's permission of dcache data sram block0 in world1." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 + description: "core0/core1's permission of dcache data sram block1 in world1." + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS + description: "core0/core1's permission(sotre,load) of rom in world0." + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS + description: "core0/core1's permission(sotre,load) of rom in world1." + bitOffset: 26 + bitWidth: 2 + access: read-write + - register: + name: CORE_0_DRAM0_PMS_MONITOR_0 + description: core0 dram0 permission monitor configuration register 0 + addressOffset: 260 + size: 32 + fields: + - name: CORE_0_DRAM0_PMS_MONITOR_LOCK + description: Set 1 to lock core0 dram0 permission monitor configuration register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_DRAM0_PMS_MONITOR_1 + description: core0 dram0 permission monitor configuration register 1 + addressOffset: 264 + size: 32 + resetValue: 3 + fields: + - name: CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR + description: Set 1 to clear core0 dram0 permission monior interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN + description: Set 1 to enable core0 dram0 permission monitor interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_DRAM0_PMS_MONITOR_2 + description: core0 dram0 permission monitor configuration register 2. + addressOffset: 268 + size: 32 + fields: + - name: CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR + description: recorded core0 dram0 permission monitor interrupt status. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK + description: "recorded core0 dram0 lock status, 1 means s32c1i access." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD + description: "recorded core0 dram0 world status, 0x1 means world0, 0x2 means world1." + bitOffset: 2 + bitWidth: 2 + access: read-only + - name: CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR + description: "recorded core0 dram0 address[25:4] status when core0 dram0 violated permission,the real address is 0x3c000000+addr*16" + bitOffset: 4 + bitWidth: 22 + access: read-only + - register: + name: CORE_0_DRAM0_PMS_MONITOR_3 + description: core0 dram0 permission monitor configuration register 3. + addressOffset: 272 + size: 32 + fields: + - name: CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR + description: "recorded core0 dram0 wr status, 1 means store, 0 means load." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN + description: recorded core0 dram0 byteen status. + bitOffset: 1 + bitWidth: 16 + access: read-only + - register: + name: CORE_1_DRAM0_PMS_MONITOR_0 + description: core1 dram0 permission monitor configuration register 0 + addressOffset: 276 + size: 32 + fields: + - name: CORE_1_DRAM0_PMS_MONITOR_LOCK + description: Set 1 to lock core1 dram0 permission monitor configuration register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_1_DRAM0_PMS_MONITOR_1 + description: core1 dram0 permission monitor configuration register 1 + addressOffset: 280 + size: 32 + resetValue: 3 + fields: + - name: CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR + description: Set 1 to clear core1 dram0 permission monior interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN + description: Set 1 to enable core1 dram0 permission monitor interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CORE_1_DRAM0_PMS_MONITOR_2 + description: core1 dram0 permission monitor configuration register 2. + addressOffset: 284 + size: 32 + fields: + - name: CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR + description: recorded core1 dram0 permission monitor interrupt status. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK + description: "recorded core1 dram0 lock status, 1 means s32c1i access." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD + description: "recorded core1 dram0 world status, 0x1 means world0, 0x2 means world1." + bitOffset: 2 + bitWidth: 2 + access: read-only + - name: CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR + description: "recorded core1 dram0 address[25:4] status when core1 dram0 violated permission,the real address is 0x3c000000+addr*16" + bitOffset: 4 + bitWidth: 22 + access: read-only + - register: + name: CORE_1_DRAM0_PMS_MONITOR_3 + description: core1 dram0 permission monitor configuration register 3. + addressOffset: 288 + size: 32 + fields: + - name: CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR + description: "recorded core1 dram0 wr status, 1 means store, 0 means load." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN + description: recorded core1 dram0 byteen status. + bitOffset: 1 + bitWidth: 16 + access: read-only + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_0 + description: Core0 access peripherals permission configuration register 0. + addressOffset: 292 + size: 32 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_LOCK + description: Set 1 to lock core0 access peripherals permission Configuration Register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_1 + description: Core0 access peripherals permission configuration register 1. + addressOffset: 296 + size: 32 + resetValue: 4281585663 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART + description: Core0 access uart permission in world0. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 + description: Core0 access g0spi_1 permission in world0. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 + description: Core0 access g0spi_0 permission in world0. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO + description: Core0 access gpio permission in world0. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 + description: Core0 access fe2 permission in world0. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE + description: Core0 access fe permission in world0. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC + description: Core0 access rtc permission in world0. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX + description: Core0 access io_mux permission in world0. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF + description: Core0 access hinf permission in world0. + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC + description: Core0 access misc permission in world0. + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C + description: Core0 access i2c permission in world0. + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 + description: Core0 access i2s0 permission in world0. + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 + description: Core0 access uart1 permission in world0. + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_2 + description: Core0 access peripherals permission configuration register 2. + addressOffset: 300 + size: 32 + resetValue: 4291821555 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT + description: Core0 access bt permission in world0. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 + description: Core0 access i2c_ext0 permission in world0. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 + description: Core0 access uhci0 permission in world0. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST + description: Core0 access slchost permission in world0. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT + description: Core0 access rmt permission in world0. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT + description: Core0 access pcnt permission in world0. + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC + description: Core0 access slc permission in world0. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC + description: Core0 access ledc permission in world0. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP + description: Core0 access backup permission in world0. + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB + description: Core0 access bb permission in world0. + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 + description: Core0 access pwm0 permission in world0. + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP + description: Core0 access timergroup permission in world0. + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 + description: Core0 access timergroup1 permission in world0. + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER + description: Core0 access systimer permission in world0. + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_3 + description: Core0 access peripherals permission configuration register 3. + addressOffset: 304 + size: 32 + resetValue: 1019478015 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 + description: Core0 access spi_2 permission in world0. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 + description: Core0 access spi_3 permission in world0. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL + description: Core0 access apb_ctrl permission in world0. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 + description: Core0 access i2c_ext1 permission in world0. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST + description: Core0 access sdio_host permission in world0. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN + description: Core0 access can permission in world0. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 + description: Core0 access pwm1 permission in world0. + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 + description: Core0 access i2s1 permission in world0. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2 + description: Core0 access uart2 permission in world0. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT + description: Core0 access rwbt permission in world0. + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC + description: Core0 access wifimac permission in world0. + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR + description: Core0 access pwr permission in world0. + bitOffset: 28 + bitWidth: 2 + access: read-write + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_4 + description: Core0 access peripherals permission configuration register 4. + addressOffset: 308 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE + description: Core0 access usb_device permission in world0. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP + description: Core0 access usb_wrap permission in world0. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI + description: Core0 access crypto_peri permission in world0. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA + description: Core0 access crypto_dma permission in world0. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC + description: Core0 access apb_adc permission in world0. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM + description: Core0 access lcd_cam permission in world0. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR + description: Core0 access bt_pwr permission in world0. + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB + description: Core0 access usb permission in world0. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM + description: Core0 access system permission in world0. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE + description: Core0 access sensitive permission in world0. + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT + description: Core0 access interrupt permission in world0. + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY + description: Core0 access dma_copy permission in world0. + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG + description: Core0 access cache_config permission in world0. + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD + description: Core0 access ad permission in world0. + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO + description: Core0 access dio permission in world0. + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER + description: Core0 access world_controller permission in world0. + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_5 + description: Core0 access peripherals permission configuration register 5. + addressOffset: 312 + size: 32 + resetValue: 4281585663 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART + description: Core0 access uart permission in world1. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 + description: Core0 access g0spi_1 permission in world1. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 + description: Core0 access g0spi_0 permission in world1. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO + description: Core0 access gpio permission in world1. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 + description: Core0 access fe2 permission in world1. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE + description: Core0 access fe permission in world1. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC + description: Core0 access rtc permission in world1. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX + description: Core0 access io_mux permission in world1. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF + description: Core0 access hinf permission in world1. + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC + description: Core0 access misc permission in world1. + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C + description: Core0 access i2c permission in world1. + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 + description: Core0 access i2s0 permission in world1. + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 + description: Core0 access uart1 permission in world1. + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_6 + description: Core0 access peripherals permission configuration register 6. + addressOffset: 316 + size: 32 + resetValue: 4291821555 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT + description: Core0 access bt permission in world1. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 + description: Core0 access i2c_ext0 permission in world1. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 + description: Core0 access uhci0 permission in world1. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST + description: Core0 access slchost permission in world1. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT + description: Core0 access rmt permission in world1. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT + description: Core0 access pcnt permission in world1. + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC + description: Core0 access slc permission in world1. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC + description: Core0 access ledc permission in world1. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP + description: Core0 access backup permission in world1. + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB + description: Core0 access bb permission in world1. + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 + description: Core0 access pwm0 permission in world1. + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP + description: Core0 access timergroup permission in world1. + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 + description: Core0 access timergroup1 permission in world1. + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER + description: Core0 access systimer permission in world1. + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_7 + description: Core0 access peripherals permission configuration register 7. + addressOffset: 320 + size: 32 + resetValue: 1019478015 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 + description: Core0 access spi_2 permission in world1. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 + description: Core0 access spi_3 permission in world1. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL + description: Core0 access apb_ctrl permission in world1. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 + description: Core0 access i2c_ext1 permission in world1. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST + description: Core0 access sdio_host permission in world1. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN + description: Core0 access can permission in world1. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 + description: Core0 access pwm1 permission in world1. + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 + description: Core0 access i2s1 permission in world1. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2 + description: Core0 access uart2 permission in world1. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT + description: Core0 access rwbt permission in world1. + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC + description: Core0 access wifimac permission in world1. + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR + description: Core0 access pwr permission in world1. + bitOffset: 28 + bitWidth: 2 + access: read-write + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_8 + description: Core0 access peripherals permission configuration register 8. + addressOffset: 324 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE + description: Core0 access usb_device permission in world1. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP + description: Core0 access usb_wrap permission in world1. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI + description: Core0 access crypto_peri permission in world1. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA + description: Core0 access crypto_dma permission in world1. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC + description: Core0 access apb_adc permission in world1. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM + description: Core0 access lcd_cam permission in world1. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR + description: Core0 access bt_pwr permission in world1. + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB + description: Core0 access usb permission in world1. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM + description: Core0 access system permission in world1. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE + description: Core0 access sensitive permission in world1. + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT + description: Core0 access interrupt permission in world1. + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY + description: Core0 access dma_copy permission in world1. + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG + description: Core0 access cache_config permission in world1. + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD + description: Core0 access ad permission in world1. + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO + description: Core0 access dio permission in world1. + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER + description: Core0 access world_controller permission in world1. + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_9 + description: Core0 access peripherals permission configuration register 9. + addressOffset: 328 + size: 32 + resetValue: 4194303 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 + description: RTCFast memory split address in world 0 for core0. + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 + description: RTCFast memory split address in world 1 for core0. + bitOffset: 11 + bitWidth: 11 + access: read-write + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_10 + description: Core0 access peripherals permission configuration register 10. + addressOffset: 332 + size: 32 + resetValue: 4095 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L + description: RTCFast memory low region permission in world 0 for core0. + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H + description: RTCFast memory high region permission in world 0 for core0. + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L + description: RTCFast memory low region permission in world 1 for core0. + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H + description: RTCFast memory high region permission in world 1 for core0. + bitOffset: 9 + bitWidth: 3 + access: read-write + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_11 + description: Core0 access peripherals permission configuration register 11. + addressOffset: 336 + size: 32 + resetValue: 4194303 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 + description: RTCSlow_0 memory split address in world 0 for core0. + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 + description: RTCSlow_0 memory split address in world 1 for core0. + bitOffset: 11 + bitWidth: 11 + access: read-write + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_12 + description: Core0 access peripherals permission configuration register 12. + addressOffset: 340 + size: 32 + resetValue: 4095 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L + description: RTCSlow_0 memory low region permission in world 0 for core0. + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H + description: RTCSlow_0 memory high region permission in world 0 for core0. + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L + description: RTCSlow_0 memory low region permission in world 1 for core0. + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H + description: RTCSlow_0 memory high region permission in world 1 for core0. + bitOffset: 9 + bitWidth: 3 + access: read-write + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_13 + description: Core0 access peripherals permission configuration register 13. + addressOffset: 344 + size: 32 + resetValue: 4194303 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 + description: RTCSlow_1 memory split address in world 0 for core0. + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 + description: RTCSlow_1 memory split address in world 1 for core0. + bitOffset: 11 + bitWidth: 11 + access: read-write + - register: + name: CORE_0_PIF_PMS_CONSTRAIN_14 + description: Core0 access peripherals permission configuration register 14. + addressOffset: 348 + size: 32 + resetValue: 4095 + fields: + - name: CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L + description: RTCSlow_1 memory low region permission in world 0 for core0. + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H + description: RTCSlow_1 memory high region permission in world 0 for core0. + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L + description: RTCSlow_1 memory low region permission in world 1 for core0. + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H + description: RTCSlow_1 memory high region permission in world 1 for core0. + bitOffset: 9 + bitWidth: 3 + access: read-write + - register: + name: CORE_0_REGION_PMS_CONSTRAIN_0 + description: Core0 region permission register 0. + addressOffset: 352 + size: 32 + fields: + - name: CORE_0_REGION_PMS_CONSTRAIN_LOCK + description: Set 1 to lock core0 region permission registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_REGION_PMS_CONSTRAIN_1 + description: Core0 region permission register 1. + addressOffset: 356 + size: 32 + resetValue: 4194303 + fields: + - name: CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 + description: Region 0 permission in world 0 for core0. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 + description: Region 1 permission in world 0 for core0. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 + description: Region 2 permission in world 0 for core0. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 + description: Region 3 permission in world 0 for core0. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 + description: Region 4 permission in world 0 for core0. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 + description: Region 5 permission in world 0 for core0. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 + description: Region 6 permission in world 0 for core0. + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 + description: Region 7 permission in world 0 for core0. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 + description: Region 8 permission in world 0 for core0. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 + description: Region 9 permission in world 0 for core0. + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 + description: Region 10 permission in world 0 for core0. + bitOffset: 20 + bitWidth: 2 + access: read-write + - register: + name: CORE_0_REGION_PMS_CONSTRAIN_2 + description: Core0 region permission register 2. + addressOffset: 360 + size: 32 + resetValue: 4194303 + fields: + - name: CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 + description: Region 0 permission in world 1 for core0. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 + description: Region 1 permission in world 1 for core0. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 + description: Region 2 permission in world 1 for core0. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 + description: Region 3 permission in world 1 for core0. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 + description: Region 4 permission in world 1 for core0. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 + description: Region 5 permission in world 1 for core0. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 + description: Region 6 permission in world 1 for core0. + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 + description: Region 7 permission in world 1 for core0. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 + description: Region 8 permission in world 1 for core0. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 + description: Region 9 permission in world 1 for core0. + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 + description: Region 10 permission in world 1 for core0. + bitOffset: 20 + bitWidth: 2 + access: read-write + - register: + name: CORE_0_REGION_PMS_CONSTRAIN_3 + description: Core0 region permission register 3. + addressOffset: 364 + size: 32 + fields: + - name: CORE_0_REGION_PMS_CONSTRAIN_ADDR_0 + description: Region 0 start address for core0. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_0_REGION_PMS_CONSTRAIN_4 + description: Core0 region permission register 4. + addressOffset: 368 + size: 32 + fields: + - name: CORE_0_REGION_PMS_CONSTRAIN_ADDR_1 + description: Region 0 end address and Region 1 start address for core0. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_0_REGION_PMS_CONSTRAIN_5 + description: Core0 region permission register 5. + addressOffset: 372 + size: 32 + fields: + - name: CORE_0_REGION_PMS_CONSTRAIN_ADDR_2 + description: Region 1 end address and Region 2 start address for core0. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_0_REGION_PMS_CONSTRAIN_6 + description: Core0 region permission register 6. + addressOffset: 376 + size: 32 + fields: + - name: CORE_0_REGION_PMS_CONSTRAIN_ADDR_3 + description: Region 2 end address and Region 3 start address for core0. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_0_REGION_PMS_CONSTRAIN_7 + description: Core0 region permission register 7. + addressOffset: 380 + size: 32 + fields: + - name: CORE_0_REGION_PMS_CONSTRAIN_ADDR_4 + description: Region 3 end address and Region 4 start address for core0. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_0_REGION_PMS_CONSTRAIN_8 + description: Core0 region permission register 8. + addressOffset: 384 + size: 32 + fields: + - name: CORE_0_REGION_PMS_CONSTRAIN_ADDR_5 + description: Region 4 end address and Region 5 start address for core0. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_0_REGION_PMS_CONSTRAIN_9 + description: Core0 region permission register 9. + addressOffset: 388 + size: 32 + fields: + - name: CORE_0_REGION_PMS_CONSTRAIN_ADDR_6 + description: Region 5 end address and Region 6 start address for core0. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_0_REGION_PMS_CONSTRAIN_10 + description: Core0 region permission register 10. + addressOffset: 392 + size: 32 + fields: + - name: CORE_0_REGION_PMS_CONSTRAIN_ADDR_7 + description: Region 6 end address and Region 7 start address for core0. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_0_REGION_PMS_CONSTRAIN_11 + description: Core0 region permission register 11. + addressOffset: 396 + size: 32 + fields: + - name: CORE_0_REGION_PMS_CONSTRAIN_ADDR_8 + description: Region 7 end address and Region 8 start address for core0. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_0_REGION_PMS_CONSTRAIN_12 + description: Core0 region permission register 12. + addressOffset: 400 + size: 32 + fields: + - name: CORE_0_REGION_PMS_CONSTRAIN_ADDR_9 + description: Region 8 end address and Region 9 start address for core0. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_0_REGION_PMS_CONSTRAIN_13 + description: Core0 region permission register 13. + addressOffset: 404 + size: 32 + fields: + - name: CORE_0_REGION_PMS_CONSTRAIN_ADDR_10 + description: Region 9 end address and Region 10 start address for core0. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_0_REGION_PMS_CONSTRAIN_14 + description: Core0 region permission register 14. + addressOffset: 408 + size: 32 + fields: + - name: CORE_0_REGION_PMS_CONSTRAIN_ADDR_11 + description: Region 10 end address for core0. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_0_PIF_PMS_MONITOR_0 + description: Core0 permission report register 0. + addressOffset: 412 + size: 32 + fields: + - name: CORE_0_PIF_PMS_MONITOR_LOCK + description: Set 1 to lock core0 permission report registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_PIF_PMS_MONITOR_1 + description: Core0 permission report register 1. + addressOffset: 416 + size: 32 + resetValue: 3 + fields: + - name: CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR + description: Set 1 to clear interrupt that core0 initiate illegal PIF bus access. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_PIF_PMS_MONITOR_VIOLATE_EN + description: Set 1 to enable interrupt that core0 initiate illegal PIF bus access. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_PIF_PMS_MONITOR_2 + description: Core0 permission report register 2. + addressOffset: 420 + size: 32 + fields: + - name: CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR + description: Record core0 illegal access interrupt state. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 + description: Record hport information when core0 initiate illegal access. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE + description: Record access type when core0 initate illegal access. + bitOffset: 2 + bitWidth: 3 + access: read-only + - name: CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE + description: Record access direction when core0 initiate illegal access. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD + description: Record world information when core0 initiate illegal access. + bitOffset: 6 + bitWidth: 2 + access: read-only + - register: + name: CORE_0_PIF_PMS_MONITOR_3 + description: Core0 permission report register 3. + addressOffset: 424 + size: 32 + fields: + - name: CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR + description: Record address information when core0 initiate illegal access. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_PIF_PMS_MONITOR_4 + description: Core0 permission report register 4. + addressOffset: 428 + size: 32 + resetValue: 3 + fields: + - name: CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR + description: Set 1 to clear interrupt that core0 initiate unsupported access type. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN + description: Set 1 to enable interrupt that core0 initiate unsupported access type. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_PIF_PMS_MONITOR_5 + description: Core0 permission report register 5. + addressOffset: 432 + size: 32 + fields: + - name: CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR + description: Record core0 unsupported access type interrupt state. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE + description: Record access type when core0 initiate unsupported access type. + bitOffset: 1 + bitWidth: 2 + access: read-only + - name: CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD + description: Record world information when core0 initiate unsupported access type. + bitOffset: 3 + bitWidth: 2 + access: read-only + - register: + name: CORE_0_PIF_PMS_MONITOR_6 + description: Core0 permission report register 6. + addressOffset: 436 + size: 32 + fields: + - name: CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR + description: Record address information when core0 initiate unsupported access type. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_0_VECBASE_OVERRIDE_LOCK + description: core0 vecbase override configuration register 0 + addressOffset: 440 + size: 32 + fields: + - name: CORE_0_VECBASE_OVERRIDE_LOCK + description: Set 1 to lock core0 vecbase configuration register + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_VECBASE_OVERRIDE_0 + description: core0 vecbase override configuration register 0 + addressOffset: 444 + size: 32 + resetValue: 1 + fields: + - name: CORE_0_VECBASE_WORLD_MASK + description: "Set 1 to mask world, then only world0_value will work." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_VECBASE_OVERRIDE_1 + description: core0 vecbase override configuration register 1 + addressOffset: 448 + size: 32 + fields: + - name: CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE + description: "world0 vecbase_override register, when core0 in world0 use this register to override vecbase register." + bitOffset: 0 + bitWidth: 22 + access: read-write + - name: CORE_0_VECBASE_OVERRIDE_SEL + description: Set 0x3 to sel vecbase_override to override vecbase register. + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: CORE_0_VECBASE_OVERRIDE_2 + description: core0 vecbase override configuration register 1 + addressOffset: 452 + size: 32 + fields: + - name: CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE + description: "world1 vecbase_override register, when core0 in world1 use this register to override vecbase register." + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0 + description: core0 toomanyexception override configuration register 0. + addressOffset: 456 + size: 32 + fields: + - name: CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK + description: Set 1 to lock core0 toomanyexception override configuration register + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1 + description: core0 toomanyexception override configuration register 1. + addressOffset: 460 + size: 32 + resetValue: 1 + fields: + - name: CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE + description: Set 1 to mask toomanyexception. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_1_PIF_PMS_CONSTRAIN_0 + description: Core1 access peripherals permission configuration register 0. + addressOffset: 464 + size: 32 + fields: + - name: CORE_1_PIF_PMS_CONSTRAIN_LOCK + description: Set 1 to lock core1 pif permission configuration register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_1_PIF_PMS_CONSTRAIN_1 + description: Core1 access peripherals permission configuration register 1. + addressOffset: 468 + size: 32 + resetValue: 4281585663 + fields: + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART + description: Core1 access uart permission in world0. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 + description: Core1 access g0spi_1 permission in world0. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 + description: Core1 access g0spi_0 permission in world0. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO + description: Core1 access gpio permission in world0. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2 + description: Core1 access fe2 permission in world0. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE + description: Core1 access fe permission in world0. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC + description: Core1 access rtc permission in world0. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX + description: Core1 access io_mux permission in world0. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF + description: Core1 access hinf permission in world0. + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC + description: Core1 access misc permission in world0. + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C + description: Core1 access i2c permission in world0. + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 + description: Core1 access i2s0 permission in world0. + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1 + description: Core1 access uart1 permission in world0. + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CORE_1_PIF_PMS_CONSTRAIN_2 + description: Core1 access peripherals permission configuration register 2. + addressOffset: 472 + size: 32 + resetValue: 4291821555 + fields: + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT + description: Core1 access bt permission in world0. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 + description: Core1 access i2c_ext0 permission in world0. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 + description: Core1 access uhci0 permission in world0. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST + description: Core1 access slchost permission in world0. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT + description: Core1 access rmt permission in world0. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT + description: Core1 access pcnt permission in world0. + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC + description: Core1 access slc permission in world0. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC + description: Core1 access ledc permission in world0. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP + description: Core1 access backup permission in world0. + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB + description: Core1 access bb permission in world0. + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 + description: Core1 access pwm0 permission in world0. + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP + description: Core1 access timergroup permission in world0. + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 + description: Core1 access timergroup1 permission in world0. + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER + description: Core1 access systimer permission in world0. + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CORE_1_PIF_PMS_CONSTRAIN_3 + description: Core1 access peripherals permission configuration register 3. + addressOffset: 476 + size: 32 + resetValue: 1019478015 + fields: + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 + description: Core1 access spi_2 permission in world0. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 + description: Core1 access spi_3 permission in world0. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL + description: Core1 access apb_ctrl permission in world0. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 + description: Core1 access i2c_ext1 permission in world0. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST + description: Core1 access sdio_host permission in world0. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN + description: Core1 access can permission in world0. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 + description: Core1 access pwm1 permission in world0. + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 + description: Core1 access i2s1 permission in world0. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2 + description: Core1 access uart2 permission in world0. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT + description: Core1 access rwbt permission in world0. + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC + description: Core1 access wifimac permission in world0. + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR + description: Core1 access pwr permission in world0. + bitOffset: 28 + bitWidth: 2 + access: read-write + - register: + name: CORE_1_PIF_PMS_CONSTRAIN_4 + description: Core1 access peripherals permission configuration register 4. + addressOffset: 480 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE + description: Core1 access usb_device permission in world0. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP + description: Core1 access usb_wrap permission in world0. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI + description: Core1 access crypto_peri permission in world0. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA + description: Core1 access crypto_dma permission in world0. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC + description: Core1 access apb_adc permission in world0. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM + description: Core1 access lcd_cam permission in world0. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR + description: Core1 access bt_pwr permission in world0. + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB + description: Core1 access usb permission in world0. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM + description: Core1 access system permission in world0. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE + description: Core1 access sensitive permission in world0. + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT + description: Core1 access interrupt permission in world0. + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY + description: Core1 access dma_copy permission in world0. + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG + description: Core1 access cache_config permission in world0. + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD + description: Core1 access ad permission in world0. + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO + description: Core1 access dio permission in world0. + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER + description: Core1 access world_controller permission in world0. + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CORE_1_PIF_PMS_CONSTRAIN_5 + description: Core1 access peripherals permission configuration register 5. + addressOffset: 484 + size: 32 + resetValue: 4281585663 + fields: + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART + description: Core1 access uart permission in world1. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 + description: Core1 access g0spi_1 permission in world1. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 + description: Core1 access g0spi_0 permission in world1. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO + description: Core1 access gpio permission in world1. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2 + description: Core1 access fe2 permission in world1. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE + description: Core1 access fe permission in world1. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC + description: Core1 access rtc permission in world1. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX + description: Core1 access io_mux permission in world1. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF + description: Core1 access hinf permission in world1. + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC + description: Core1 access misc permission in world1. + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C + description: Core1 access i2c permission in world1. + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 + description: Core1 access i2s0 permission in world1. + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1 + description: Core1 access uart1 permission in world1. + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CORE_1_PIF_PMS_CONSTRAIN_6 + description: Core1 access peripherals permission configuration register 6. + addressOffset: 488 + size: 32 + resetValue: 4291821555 + fields: + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT + description: Core1 access bt permission in world1. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 + description: Core1 access i2c_ext0 permission in world1. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 + description: Core1 access uhci0 permission in world1. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST + description: Core1 access slchost permission in world1. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT + description: Core1 access rmt permission in world1. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT + description: Core1 access pcnt permission in world1. + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC + description: Core1 access slc permission in world1. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC + description: Core1 access ledc permission in world1. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP + description: Core1 access backup permission in world1. + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB + description: Core1 access bb permission in world1. + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 + description: Core1 access pwm0 permission in world1. + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP + description: Core1 access timergroup permission in world1. + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 + description: Core1 access timergroup1 permission in world1. + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER + description: Core1 access systimer permission in world1. + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CORE_1_PIF_PMS_CONSTRAIN_7 + description: Core1 access peripherals permission configuration register 7. + addressOffset: 492 + size: 32 + resetValue: 1019478015 + fields: + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 + description: Core1 access spi_2 permission in world1. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 + description: Core1 access spi_3 permission in world1. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL + description: Core1 access apb_ctrl permission in world1. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 + description: Core1 access i2c_ext1 permission in world1. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST + description: Core1 access sdio_host permission in world1. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN + description: Core1 access can permission in world1. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 + description: Core1 access pwm1 permission in world1. + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 + description: Core1 access i2s1 permission in world1. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2 + description: Core1 access uart2 permission in world1. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT + description: Core1 access rwbt permission in world1. + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC + description: Core1 access wifimac permission in world1. + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR + description: Core1 access pwr permission in world1. + bitOffset: 28 + bitWidth: 2 + access: read-write + - register: + name: CORE_1_PIF_PMS_CONSTRAIN_8 + description: Core1 access peripherals permission configuration register 8. + addressOffset: 496 + size: 32 + resetValue: 4294967295 + fields: + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE + description: Core1 access usb_device permission in world1. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP + description: Core1 access usb_wrap permission in world1. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI + description: Core1 access crypto_peri permission in world1. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA + description: Core1 access crypto_dma permission in world1. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC + description: Core1 access apb_adc permission in world1. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM + description: Core1 access lcd_cam permission in world1. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR + description: Core1 access bt_pwr permission in world1. + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB + description: Core1 access usb permission in world1. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM + description: Core1 access system permission in world1. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE + description: Core1 access sensitive permission in world1. + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT + description: Core1 access interrupt permission in world1. + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY + description: Core1 access dma_copy permission in world1. + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG + description: Core1 access cache_config permission in world1. + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD + description: Core1 access ad permission in world1. + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO + description: Core1 access dio permission in world1. + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER + description: Core1 access world_controller permission in world1. + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: CORE_1_PIF_PMS_CONSTRAIN_9 + description: Core1 access peripherals permission configuration register 9. + addressOffset: 500 + size: 32 + resetValue: 4194303 + fields: + - name: CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 + description: RTCFast memory split address in world 0 for core1. + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 + description: RTCFast memory split address in world 1 for core1. + bitOffset: 11 + bitWidth: 11 + access: read-write + - register: + name: CORE_1_PIF_PMS_CONSTRAIN_10 + description: core1 access peripherals permission configuration register 10. + addressOffset: 504 + size: 32 + resetValue: 4095 + fields: + - name: CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L + description: RTCFast memory low region permission in world 0 for core1. + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H + description: RTCFast memory high region permission in world 0 for core1. + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L + description: RTCFast memory low region permission in world 1 for core1. + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H + description: RTCFast memory high region permission in world 1 for core1. + bitOffset: 9 + bitWidth: 3 + access: read-write + - register: + name: CORE_1_PIF_PMS_CONSTRAIN_11 + description: core1 access peripherals permission configuration register 11. + addressOffset: 508 + size: 32 + resetValue: 4194303 + fields: + - name: CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 + description: RTCSlow_0 memory split address in world 0 for core1. + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 + description: RTCSlow_0 memory split address in world 1 for core1. + bitOffset: 11 + bitWidth: 11 + access: read-write + - register: + name: CORE_1_PIF_PMS_CONSTRAIN_12 + description: core1 access peripherals permission configuration register 12. + addressOffset: 512 + size: 32 + resetValue: 4095 + fields: + - name: CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L + description: RTCSlow_0 memory low region permission in world 0 for core1. + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H + description: RTCSlow_0 memory high region permission in world 0 for core1. + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L + description: RTCSlow_0 memory low region permission in world 1 for core1. + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H + description: RTCSlow_0 memory high region permission in world 1 for core1. + bitOffset: 9 + bitWidth: 3 + access: read-write + - register: + name: CORE_1_PIF_PMS_CONSTRAIN_13 + description: core1 access peripherals permission configuration register 13. + addressOffset: 516 + size: 32 + resetValue: 4194303 + fields: + - name: CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 + description: RTCSlow_1 memory split address in world 0 for core1. + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 + description: RTCSlow_1 memory split address in world 1 for core1. + bitOffset: 11 + bitWidth: 11 + access: read-write + - register: + name: CORE_1_PIF_PMS_CONSTRAIN_14 + description: core1 access peripherals permission configuration register 14. + addressOffset: 520 + size: 32 + resetValue: 4095 + fields: + - name: CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L + description: RTCSlow_1 memory low region permission in world 0 for core1. + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H + description: RTCSlow_1 memory high region permission in world 0 for core1. + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L + description: RTCSlow_1 memory low region permission in world 1 for core1. + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H + description: RTCSlow_1 memory high region permission in world 1 for core1. + bitOffset: 9 + bitWidth: 3 + access: read-write + - register: + name: CORE_1_REGION_PMS_CONSTRAIN_0 + description: core1 region permission register 0. + addressOffset: 524 + size: 32 + fields: + - name: CORE_1_REGION_PMS_CONSTRAIN_LOCK + description: Set 1 to lock core1 region permission registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_1_REGION_PMS_CONSTRAIN_1 + description: core1 region permission register 1. + addressOffset: 528 + size: 32 + resetValue: 4194303 + fields: + - name: CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 + description: Region 0 permission in world 0 for core1. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 + description: Region 1 permission in world 0 for core1. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 + description: Region 2 permission in world 0 for core1. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 + description: Region 3 permission in world 0 for core1. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 + description: Region 4 permission in world 0 for core1. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 + description: Region 5 permission in world 0 for core1. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 + description: Region 6 permission in world 0 for core1. + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 + description: Region 7 permission in world 0 for core1. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 + description: Region 8 permission in world 0 for core1. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 + description: Region 9 permission in world 0 for core1. + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 + description: Region 10 permission in world 0 for core1. + bitOffset: 20 + bitWidth: 2 + access: read-write + - register: + name: CORE_1_REGION_PMS_CONSTRAIN_2 + description: core1 region permission register 2. + addressOffset: 532 + size: 32 + resetValue: 4194303 + fields: + - name: CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 + description: Region 0 permission in world 1 for core1. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 + description: Region 1 permission in world 1 for core1. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 + description: Region 2 permission in world 1 for core1. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 + description: Region 3 permission in world 1 for core1. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 + description: Region 4 permission in world 1 for core1. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 + description: Region 5 permission in world 1 for core1. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 + description: Region 6 permission in world 1 for core1. + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 + description: Region 7 permission in world 1 for core1. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 + description: Region 8 permission in world 1 for core1. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 + description: Region 9 permission in world 1 for core1. + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 + description: Region 10 permission in world 1 for core1. + bitOffset: 20 + bitWidth: 2 + access: read-write + - register: + name: CORE_1_REGION_PMS_CONSTRAIN_3 + description: core1 region permission register 3. + addressOffset: 536 + size: 32 + fields: + - name: CORE_1_REGION_PMS_CONSTRAIN_ADDR_0 + description: Region 0 start address for core1. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_1_REGION_PMS_CONSTRAIN_4 + description: core1 region permission register 4. + addressOffset: 540 + size: 32 + fields: + - name: CORE_1_REGION_PMS_CONSTRAIN_ADDR_1 + description: Region 0 end address and Region 1 start address for core1. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_1_REGION_PMS_CONSTRAIN_5 + description: core1 region permission register 5. + addressOffset: 544 + size: 32 + fields: + - name: CORE_1_REGION_PMS_CONSTRAIN_ADDR_2 + description: Region 1 end address and Region 2 start address for core1. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_1_REGION_PMS_CONSTRAIN_6 + description: core1 region permission register 6. + addressOffset: 548 + size: 32 + fields: + - name: CORE_1_REGION_PMS_CONSTRAIN_ADDR_3 + description: Region 2 end address and Region 3 start address for core1. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_1_REGION_PMS_CONSTRAIN_7 + description: core1 region permission register 7. + addressOffset: 552 + size: 32 + fields: + - name: CORE_1_REGION_PMS_CONSTRAIN_ADDR_4 + description: Region 3 end address and Region 4 start address for core1. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_1_REGION_PMS_CONSTRAIN_8 + description: core1 region permission register 8. + addressOffset: 556 + size: 32 + fields: + - name: CORE_1_REGION_PMS_CONSTRAIN_ADDR_5 + description: Region 4 end address and Region 5 start address for core1. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_1_REGION_PMS_CONSTRAIN_9 + description: core1 region permission register 9. + addressOffset: 560 + size: 32 + fields: + - name: CORE_1_REGION_PMS_CONSTRAIN_ADDR_6 + description: Region 5 end address and Region 6 start address for core1. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_1_REGION_PMS_CONSTRAIN_10 + description: core1 region permission register 10. + addressOffset: 564 + size: 32 + fields: + - name: CORE_1_REGION_PMS_CONSTRAIN_ADDR_7 + description: Region 6 end address and Region 7 start address for core1. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_1_REGION_PMS_CONSTRAIN_11 + description: core1 region permission register 11. + addressOffset: 568 + size: 32 + fields: + - name: CORE_1_REGION_PMS_CONSTRAIN_ADDR_8 + description: Region 7 end address and Region 8 start address for core1. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_1_REGION_PMS_CONSTRAIN_12 + description: core1 region permission register 12. + addressOffset: 572 + size: 32 + fields: + - name: CORE_1_REGION_PMS_CONSTRAIN_ADDR_9 + description: Region 8 end address and Region 9 start address for core1. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_1_REGION_PMS_CONSTRAIN_13 + description: core1 region permission register 13. + addressOffset: 576 + size: 32 + fields: + - name: CORE_1_REGION_PMS_CONSTRAIN_ADDR_10 + description: Region 9 end address and Region 10 start address for core1. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_1_REGION_PMS_CONSTRAIN_14 + description: core1 region permission register 14. + addressOffset: 580 + size: 32 + fields: + - name: CORE_1_REGION_PMS_CONSTRAIN_ADDR_11 + description: Region 10 end address for core1. + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: CORE_1_PIF_PMS_MONITOR_0 + description: core1 permission report register 0. + addressOffset: 584 + size: 32 + fields: + - name: CORE_1_PIF_PMS_MONITOR_LOCK + description: Set 1 to lock core1 permission report registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_1_PIF_PMS_MONITOR_1 + description: core1 permission report register 1. + addressOffset: 588 + size: 32 + resetValue: 3 + fields: + - name: CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR + description: Set 1 to clear interrupt that core1 initiate illegal PIF bus access. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_1_PIF_PMS_MONITOR_VIOLATE_EN + description: Set 1 to enable interrupt that core1 initiate illegal PIF bus access. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CORE_1_PIF_PMS_MONITOR_2 + description: core1 permission report register 2. + addressOffset: 592 + size: 32 + fields: + - name: CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR + description: Record core1 illegal access interrupt state. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 + description: Record hport information when core1 initiate illegal access. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE + description: Record access type when core1 initate illegal access. + bitOffset: 2 + bitWidth: 3 + access: read-only + - name: CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE + description: Record access direction when core1 initiate illegal access. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD + description: Record world information when core1 initiate illegal access. + bitOffset: 6 + bitWidth: 2 + access: read-only + - register: + name: CORE_1_PIF_PMS_MONITOR_3 + description: core1 permission report register 3. + addressOffset: 596 + size: 32 + fields: + - name: CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR + description: Record address information when core1 initiate illegal access. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_1_PIF_PMS_MONITOR_4 + description: core1 permission report register 4. + addressOffset: 600 + size: 32 + resetValue: 3 + fields: + - name: CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR + description: Set 1 to clear interrupt that core1 initiate unsupported access type. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN + description: Set 1 to enable interrupt that core1 initiate unsupported access type. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CORE_1_PIF_PMS_MONITOR_5 + description: core1 permission report register 5. + addressOffset: 604 + size: 32 + fields: + - name: CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR + description: Record core1 unsupported access type interrupt state. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE + description: Record access type when core1 initiate unsupported access type. + bitOffset: 1 + bitWidth: 2 + access: read-only + - name: CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD + description: Record world information when core1 initiate unsupported access type. + bitOffset: 3 + bitWidth: 2 + access: read-only + - register: + name: CORE_1_PIF_PMS_MONITOR_6 + description: core1 permission report register 6. + addressOffset: 608 + size: 32 + fields: + - name: CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR + description: Record address information when core1 initiate unsupported access type. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CORE_1_VECBASE_OVERRIDE_LOCK + description: core1 vecbase override configuration register 0 + addressOffset: 612 + size: 32 + fields: + - name: CORE_1_VECBASE_OVERRIDE_LOCK + description: Set 1 to lock core1 vecbase configuration register + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_1_VECBASE_OVERRIDE_0 + description: core1 vecbase override configuration register 0 + addressOffset: 616 + size: 32 + resetValue: 1 + fields: + - name: CORE_1_VECBASE_WORLD_MASK + description: "Set 1 to mask world, then only world0_value will work." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_1_VECBASE_OVERRIDE_1 + description: core1 vecbase override configuration register 1 + addressOffset: 620 + size: 32 + fields: + - name: CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE + description: "world0 vecbase_override register, when core1 in world0 use this register to override vecbase register." + bitOffset: 0 + bitWidth: 22 + access: read-write + - name: CORE_1_VECBASE_OVERRIDE_SEL + description: Set 0x3 to sel vecbase_override to override vecbase register. + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: CORE_1_VECBASE_OVERRIDE_2 + description: core1 vecbase override configuration register 1 + addressOffset: 624 + size: 32 + fields: + - name: CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE + description: "world1 vecbase_override register, when core1 in world1 use this register to override vecbase register." + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + name: CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0 + description: core1 toomanyexception override configuration register 0. + addressOffset: 628 + size: 32 + fields: + - name: CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK + description: Set 1 to lock core1 toomanyexception override configuration register + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1 + description: core1 toomanyexception override configuration register 1. + addressOffset: 632 + size: 32 + resetValue: 1 + fields: + - name: CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE + description: Set 1 to mask toomanyexception. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: BACKUP_BUS_PMS_CONSTRAIN_0 + description: BackUp access peripherals permission configuration register 0. + addressOffset: 636 + size: 32 + fields: + - name: BACKUP_BUS_PMS_CONSTRAIN_LOCK + description: Set 1 to lock BackUp permission configuration registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: BACKUP_BUS_PMS_CONSTRAIN_1 + description: BackUp access peripherals permission configuration register 1. + addressOffset: 640 + size: 32 + resetValue: 4281585663 + fields: + - name: BACKUP_BUS_PMS_CONSTRAIN_UART + description: BackUp access uart permission. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 + description: BackUp access g0spi_1 permission. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 + description: BackUp access g0spi_0 permission. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_GPIO + description: BackUp access gpio permission. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_FE2 + description: BackUp access fe2 permission. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_FE + description: BackUp access fe permission. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_RTC + description: BackUp access rtc permission. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_IO_MUX + description: BackUp access io_mux permission. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_HINF + description: BackUp access hinf permission. + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_MISC + description: BackUp access misc permission. + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_I2C + description: BackUp access i2c permission. + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_I2S0 + description: BackUp access i2s0 permission. + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_UART1 + description: BackUp access uart1 permission. + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: BACKUP_BUS_PMS_CONSTRAIN_2 + description: BackUp access peripherals permission configuration register 2. + addressOffset: 644 + size: 32 + resetValue: 4291821555 + fields: + - name: BACKUP_BUS_PMS_CONSTRAIN_BT + description: BackUp access bt permission. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 + description: BackUp access i2c_ext0 permission. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_UHCI0 + description: BackUp access uhci0 permission. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_SLCHOST + description: BackUp access slchost permission. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_RMT + description: BackUp access rmt permission. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_PCNT + description: BackUp access pcnt permission. + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_SLC + description: BackUp access slc permission. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_LEDC + description: BackUp access ledc permission. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_BACKUP + description: BackUp access backup permission. + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_BB + description: BackUp access bb permission. + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_PWM0 + description: BackUp access pwm0 permission. + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP + description: BackUp access timergroup permission. + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 + description: BackUp access timergroup1 permission. + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER + description: BackUp access systimer permission. + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: BACKUP_BUS_PMS_CONSTRAIN_3 + description: BackUp access peripherals permission configuration register 3. + addressOffset: 648 + size: 32 + resetValue: 1019478015 + fields: + - name: BACKUP_BUS_PMS_CONSTRAIN_SPI_2 + description: BackUp access spi_2 permission. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_SPI_3 + description: BackUp access spi_3 permission. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL + description: BackUp access apb_ctrl permission. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1 + description: BackUp access i2c_ext1 permission. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST + description: BackUp access sdio_host permission. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_CAN + description: BackUp access can permission. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_PWM1 + description: BackUp access pwm1 permission. + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_I2S1 + description: BackUp access i2s1 permission. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_UART2 + description: BackUp access uart2 permission. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_RWBT + description: BackUp access rwbt permission. + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC + description: BackUp access wifimac permission. + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_PWR + description: BackUp access pwr permission. + bitOffset: 28 + bitWidth: 2 + access: read-write + - register: + name: BACKUP_BUS_PMS_CONSTRAIN_4 + description: BackUp access peripherals permission configuration register 4. + addressOffset: 652 + size: 32 + resetValue: 4294967295 + fields: + - name: BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE + description: BackUp access usb_device permission. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP + description: BackUp access usb_wrap permission. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI + description: BackUp access crypto_peri permission. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA + description: BackUp access crypto_dma permission. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_APB_ADC + description: BackUp access apb_adc permission. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM + description: BackUp access lcd_cam permission. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_BT_PWR + description: BackUp access bt_pwr permission. + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_USB + description: BackUp access usb permission. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_SYSTEM + description: BackUp access system permission. + bitOffset: 16 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE + description: BackUp access sensitive permission. + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT + description: BackUp access interrupt permission. + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY + description: BackUp access dma_copy permission. + bitOffset: 22 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG + description: BackUp access cache_config permission. + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_AD + description: BackUp access ad permission. + bitOffset: 26 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_DIO + description: BackUp access dio permission. + bitOffset: 28 + bitWidth: 2 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER + description: BackUp access world_controller permission. + bitOffset: 30 + bitWidth: 2 + access: read-write + - register: + name: BACKUP_BUS_PMS_CONSTRAIN_5 + description: BackUp access peripherals permission configuration register 5. + addressOffset: 656 + size: 32 + resetValue: 2047 + fields: + - name: BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR + description: BackUp access rtcfast_spltaddr permission. + bitOffset: 0 + bitWidth: 11 + access: read-write + - register: + name: BACKUP_BUS_PMS_CONSTRAIN_6 + description: BackUp access peripherals permission configuration register 6. + addressOffset: 660 + size: 32 + resetValue: 63 + fields: + - name: BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L + description: BackUp access rtcfast_l permission. + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H + description: BackUp access rtcfast_h permission. + bitOffset: 3 + bitWidth: 3 + access: read-write + - register: + name: BACKUP_BUS_PMS_MONITOR_0 + description: BackUp permission report register 0. + addressOffset: 664 + size: 32 + fields: + - name: BACKUP_BUS_PMS_MONITOR_LOCK + description: Set 1 to lock BackUp permission report registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: BACKUP_BUS_PMS_MONITOR_1 + description: BackUp permission report register 1. + addressOffset: 668 + size: 32 + resetValue: 3 + fields: + - name: BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR + description: Set 1 to clear interrupt that BackUp initiate illegal access. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: BACKUP_BUS_PMS_MONITOR_VIOLATE_EN + description: Set 1 to enable interrupt that BackUp initiate illegal access. + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: BACKUP_BUS_PMS_MONITOR_2 + description: BackUp permission report register 2. + addressOffset: 672 + size: 32 + fields: + - name: BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR + description: Record BackUp illegal access interrupt state. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS + description: Record htrans when BackUp initate illegal access. + bitOffset: 1 + bitWidth: 2 + access: read-only + - name: BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE + description: Record access type when BackUp initate illegal access. + bitOffset: 3 + bitWidth: 3 + access: read-only + - name: BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE + description: Record access direction when BackUp initiate illegal access. + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: BACKUP_BUS_PMS_MONITOR_3 + description: BackUp permission report register 3. + addressOffset: 676 + size: 32 + fields: + - name: BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR + description: Record address information when BackUp initiate illegal access. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: EDMA_BOUNDARY_LOCK + description: EDMA boundary lock register. + addressOffset: 680 + size: 32 + fields: + - name: EDMA_BOUNDARY_LOCK + description: Set 1 to lock EDMA boundary registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: EDMA_BOUNDARY_0 + description: EDMA boundary 0 configuration + addressOffset: 684 + size: 32 + fields: + - name: EDMA_BOUNDARY_0 + description: "This field is used to configure the boundary 0 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K)." + bitOffset: 0 + bitWidth: 14 + access: read-write + - register: + name: EDMA_BOUNDARY_1 + description: EDMA boundary 1 configuration + addressOffset: 688 + size: 32 + resetValue: 8192 + fields: + - name: EDMA_BOUNDARY_1 + description: "This field is used to configure the boundary 1 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K)." + bitOffset: 0 + bitWidth: 14 + access: read-write + - register: + name: EDMA_BOUNDARY_2 + description: EDMA boundary 2 configuration + addressOffset: 692 + size: 32 + resetValue: 8192 + fields: + - name: EDMA_BOUNDARY_2 + description: "This field is used to configure the boundary 2 of external RAM. The unit is 4K. For example, set this field to 0x80, then the address boundary 0 would be 0x3C080000 (0x3C000000 + 0x80 * 4K)." + bitOffset: 0 + bitWidth: 14 + access: read-write + - register: + name: EDMA_PMS_SPI2_LOCK + description: EDMA-SPI2 permission lock register. + addressOffset: 696 + size: 32 + fields: + - name: EDMA_PMS_SPI2_LOCK + description: Set 1 to lock EDMA-SPI2 permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: EDMA_PMS_SPI2 + description: EDMA-SPI2 permission control register. + addressOffset: 700 + size: 32 + resetValue: 15 + fields: + - name: ATTR1 + description: "This field is used to configure the permission of SPI2 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: ATTR2 + description: "This field is used to configure the permission of SPI2 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission." + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: EDMA_PMS_SPI3_LOCK + description: EDMA-SPI3 permission lock register. + addressOffset: 704 + size: 32 + fields: + - name: EDMA_PMS_SPI3_LOCK + description: Set 1 to lock EDMA-SPI3 permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: EDMA_PMS_SPI3 + description: EDMA-SPI3 permission control register. + addressOffset: 708 + size: 32 + resetValue: 15 + fields: + - name: ATTR1 + description: "This field is used to configure the permission of SPI3 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: ATTR2 + description: "This field is used to configure the permission of SPI3 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission." + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: EDMA_PMS_UHCI0_LOCK + description: EDMA-UHCI0 permission lock register. + addressOffset: 712 + size: 32 + fields: + - name: EDMA_PMS_UHCI0_LOCK + description: Set 1 to lock EDMA-UHCI0 permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: EDMA_PMS_UHCI0 + description: EDMA-UHCI0 permission control register. + addressOffset: 716 + size: 32 + resetValue: 15 + fields: + - name: ATTR1 + description: "This field is used to configure the permission of UHCI0 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: ATTR2 + description: "This field is used to configure the permission of UHCI0 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission." + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: EDMA_PMS_I2S0_LOCK + description: EDMA-I2S0 permission lock register. + addressOffset: 720 + size: 32 + fields: + - name: EDMA_PMS_I2S0_LOCK + description: Set 1 to lock EDMA-I2S0 permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: EDMA_PMS_I2S0 + description: EDMA-I2S0 permission control register. + addressOffset: 724 + size: 32 + resetValue: 15 + fields: + - name: ATTR1 + description: "This field is used to configure the permission of I2S0 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: ATTR2 + description: "This field is used to configure the permission of I2S0 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission." + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: EDMA_PMS_I2S1_LOCK + description: EDMA-I2S1 permission lock register. + addressOffset: 728 + size: 32 + fields: + - name: EDMA_PMS_I2S1_LOCK + description: Set 1 to lock EDMA-I2S1 permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: EDMA_PMS_I2S1 + description: EDMA-I2S1 permission control register. + addressOffset: 732 + size: 32 + resetValue: 15 + fields: + - name: ATTR1 + description: "This field is used to configure the permission of I2S1 accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: ATTR2 + description: "This field is used to configure the permission of I2S1 accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission." + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: EDMA_PMS_LCD_CAM_LOCK + description: EDMA-LCD/CAM permission lock register. + addressOffset: 736 + size: 32 + fields: + - name: EDMA_PMS_LCD_CAM_LOCK + description: Set 1 to lock EDMA-LCD/CAM permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: EDMA_PMS_LCD_CAM + description: EDMA-LCD/CAM permission control register. + addressOffset: 740 + size: 32 + resetValue: 15 + fields: + - name: ATTR1 + description: "This field is used to configure the permission of LCD/CAM accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: ATTR2 + description: "This field is used to configure the permission of LCD/CAM accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission." + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: EDMA_PMS_AES_LOCK + description: EDMA-AES permission lock register. + addressOffset: 744 + size: 32 + fields: + - name: EDMA_PMS_AES_LOCK + description: Set 1 to lock EDMA-AES permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: EDMA_PMS_AES + description: EDMA-AES permission control register. + addressOffset: 748 + size: 32 + resetValue: 15 + fields: + - name: ATTR1 + description: "This field is used to configure the permission of AES accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: ATTR2 + description: "This field is used to configure the permission of AES accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission." + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: EDMA_PMS_SHA_LOCK + description: EDMA-SHA permission lock register. + addressOffset: 752 + size: 32 + fields: + - name: EDMA_PMS_SHA_LOCK + description: Set 1 to lock EDMA-SHA permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: EDMA_PMS_SHA + description: EDMA-SHA permission control register. + addressOffset: 756 + size: 32 + resetValue: 15 + fields: + - name: ATTR1 + description: "This field is used to configure the permission of SHA accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: ATTR2 + description: "This field is used to configure the permission of SHA accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission." + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: EDMA_PMS_ADC_DAC_LOCK + description: EDMA-ADC/DAC permission lock register. + addressOffset: 760 + size: 32 + fields: + - name: EDMA_PMS_ADC_DAC_LOCK + description: Set 1 to lock EDMA-ADC/DAC permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: EDMA_PMS_ADC_DAC + description: EDMA-ADC/DAC permission control register. + addressOffset: 764 + size: 32 + resetValue: 15 + fields: + - name: ATTR1 + description: "This field is used to configure the permission of ADC/DAC accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: ATTR2 + description: "This field is used to configure the permission of ADC/DAC accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission." + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: EDMA_PMS_RMT_LOCK + description: EDMA-RMT permission lock register. + addressOffset: 768 + size: 32 + fields: + - name: EDMA_PMS_RMT_LOCK + description: Set 1 to lock EDMA-RMT permission control registers. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: EDMA_PMS_RMT + description: EDMA-RMT permission control register. + addressOffset: 772 + size: 32 + resetValue: 15 + fields: + - name: ATTR1 + description: "This field is used to configure the permission of RMT accessing address, which is larger than boundary 0 and less than boundary 1, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: ATTR2 + description: "This field is used to configure the permission of RMT accessing address, which is larger than boundary 1 and less than boundary 2, through EDMA. Bit 0: set this bit to enable read permission. Bit 1: set this bit to enable write permission." + bitOffset: 2 + bitWidth: 2 + access: read-write + - register: + name: CLOCK_GATE + description: Sensitive module clock gate configuration register. + addressOffset: 776 + size: 32 + resetValue: 1 + fields: + - name: REG_CLK_EN + description: Set 1 to enable clock gate function. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: RTC_PMS + description: RTC coprocessor permission register. + addressOffset: 780 + size: 32 + fields: + - name: DIS_RTC_CPU + description: Set 1 to disable rtc coprocessor. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Sensitive version register. + addressOffset: 4092 + size: 32 + resetValue: 34607744 + fields: + - name: DATE + description: Sensitive Date register. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SHA + description: SHA (Secure Hash Algorithm) Accelerator + groupName: SHA + baseAddress: 1610854400 + addressBlock: + - offset: 0 + size: 176 + usage: registers + interrupt: + - name: SHA + value: 77 + registers: + - register: + name: MODE + description: Initial configuration register. + addressOffset: 0 + size: 32 + fields: + - name: MODE + description: sha mode + bitOffset: 0 + bitWidth: 3 + access: read-write + - register: + name: T_STRING + description: SHA 512/t configuration register 0. + addressOffset: 4 + size: 32 + fields: + - name: T_STRING + description: sha t_string(used if and only if mode == sha_256/t) + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: T_LENGTH + description: SHA 512/t configuration register 1. + addressOffset: 8 + size: 32 + fields: + - name: T_LENGTH + description: sha t_length(used if and only if mode == sha_256/t) + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: DMA_BLOCK_NUM + description: DMA configuration register 0. + addressOffset: 12 + size: 32 + fields: + - name: DMA_BLOCK_NUM + description: dma-sha block number + bitOffset: 0 + bitWidth: 6 + access: read-write + - register: + name: START + description: Typical SHA configuration register 0. + addressOffset: 16 + size: 32 + fields: + - name: START + description: reserved. + bitOffset: 1 + bitWidth: 31 + access: write-only + - register: + name: CONTINUE + description: Typical SHA configuration register 1. + addressOffset: 20 + size: 32 + fields: + - name: CONTINUE + description: reserved. + bitOffset: 1 + bitWidth: 31 + access: write-only + - register: + name: BUSY + description: Busy register. + addressOffset: 24 + size: 32 + fields: + - name: STATE + description: "sha busy state. 1'b0: idle 1'b1: busy" + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: DMA_START + description: DMA configuration register 1. + addressOffset: 28 + size: 32 + fields: + - name: DMA_START + description: start dma-sha + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: DMA_CONTINUE + description: DMA configuration register 2. + addressOffset: 32 + size: 32 + fields: + - name: DMA_CONTINUE + description: continue dma-sha + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: CLEAR_IRQ + description: Interrupt clear register. + addressOffset: 36 + size: 32 + fields: + - name: CLEAR_INTERRUPT + description: clear sha interrupt + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: IRQ_ENA + description: Interrupt enable register. + addressOffset: 40 + size: 32 + fields: + - name: INTERRUPT_ENA + description: "sha interrupt enable register. 1'b0: disable(default) 1'b1: enable" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Date register. + addressOffset: 44 + size: 32 + resetValue: 538510338 + fields: + - name: DATE + description: sha date information/ sha version information + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + dim: 16 + dimIncrement: 4 + name: "H_MEM[%s]" + description: Sha H memory which contains intermediate hash or finial hash. + addressOffset: 64 + size: 32 + - register: + dim: 16 + dimIncrement: 4 + name: "M_MEM[%s]" + description: Sha M memory which contains message. + addressOffset: 128 + size: 32 + - name: SPI0 + description: SPI (Serial Peripheral Interface) Controller 0 + groupName: SPI0 + baseAddress: 1610625024 + addressBlock: + - offset: 0 + size: 152 + usage: registers + interrupt: + - name: SPI_MEM_REJECT_CACHE + value: 60 + registers: + - register: + name: CTRL + description: SPI0 control register. + addressOffset: 8 + size: 32 + resetValue: 2891776 + fields: + - name: FDUMMY_OUT + description: In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FDOUT_OCT + description: Set this bit to enable 8-bit-mode(8-bm) in DOUT phase. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FDIN_OCT + description: Set this bit to enable 8-bit-mode(8-bm) in DIN phase. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FADDR_OCT + description: Set this bit to enable 8-bit-mode(8-bm) in ADDR phase. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FCMD_DUAL + description: Set this bit to enable 2-bit-mode(2-bm) in CMD phase. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FCMD_QUAD + description: Set this bit to enable 4-bit-mode(4-bm) in CMD phase. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FCMD_OCT + description: Set this bit to enable 8-bit-mode(8-bm) in CMD phase. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FASTRD_MODE + description: "This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FREAD_DUAL + description: "In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: Q_POL + description: "The bit is used to set MISO line polarity, 1: high 0, low" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: D_POL + description: "The bit is used to set MOSI line polarity, 1: high 0, low" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: FREAD_QUAD + description: "In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: WP + description: "Write protect signal output when SPI is idle. 1: output high, 0: output low." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: FREAD_DIO + description: "In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: FREAD_QIO + description: "In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: CTRL1 + description: SPI0 control 1 register. + addressOffset: 12 + size: 32 + fields: + - name: CLK_MODE + description: "SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: RXFIFO_RST + description: SPI0 RX FIFO reset signal. Set this bit and clear it before SPI0 transfer starts. + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: CTRL2 + description: SPI0 control 2 register. + addressOffset: 16 + size: 32 + resetValue: 11297 + fields: + - name: CS_SETUP_TIME + description: "(cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit." + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: CS_HOLD_TIME + description: "SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit." + bitOffset: 5 + bitWidth: 5 + access: read-write + - name: ECC_CS_HOLD_TIME + description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC mode when accessed flash. + bitOffset: 10 + bitWidth: 3 + access: read-write + - name: ECC_SKIP_PAGE_CORNER + description: "1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: ECC_16TO18_BYTE_EN + description: Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: CS_HOLD_DELAY + description: "These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles." + bitOffset: 25 + bitWidth: 6 + access: read-write + - name: SYNC_RESET + description: The FSM will be reset. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CLOCK + description: SPI_CLK clock division register when SPI0 accesses to flash. + addressOffset: 20 + size: 32 + resetValue: 196867 + fields: + - name: CLKCNT_L + description: It must equal to the value of SPI_MEM_CLKCNT_N. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CLKCNT_H + description: It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1). + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: CLKCNT_N + description: "When SPI0 accesses flash, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1)" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: CLK_EQU_SYSCLK + description: "When SPI0 accesses flash, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USER + description: SPI0 user register. + addressOffset: 24 + size: 32 + fields: + - name: CS_HOLD + description: Set this bit to keep SPI_CS low when MSPI is in DONE state. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CS_SETUP + description: Set this bit to keep SPI_CS low when MSPI is in PREP state. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: CK_OUT_EDGE + description: "This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: USR_DUMMY_IDLE + description: SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: USR_DUMMY + description: This bit enable the DUMMY phase of an SPI transfer. + bitOffset: 29 + bitWidth: 1 + access: read-write + - register: + name: USER1 + description: SPI0 user1 register. + addressOffset: 28 + size: 32 + resetValue: 1543503879 + fields: + - name: USR_DUMMY_CYCLELEN + description: The SPI_CLK cycle length minus 1 of DUMMY phase. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: USR_ADDR_BITLEN + description: The length in bits of ADDR phase. The register value shall be (bit_num-1). + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: USER2 + description: SPI0 user2 register. + addressOffset: 32 + size: 32 + resetValue: 1879048192 + fields: + - name: USR_COMMAND_VALUE + description: The value of user defined(USR) command. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: USR_COMMAND_BITLEN + description: The length in bits of CMD phase. The register value shall be (bit_num-1) + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: RD_STATUS + description: SPI0 read control register. + addressOffset: 44 + size: 32 + fields: + - name: WB_MODE + description: Mode bits in the flash fast read mode it is combined with SPI_MEM_FASTRD_MODE bit. + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: EXT_ADDR + description: SPI0 extended address register. + addressOffset: 48 + size: 32 + fields: + - name: EXT_ADDR + description: The register are the higher 32bits in the 64 bits address mode. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: MISC + description: SPI0 misc register + addressOffset: 52 + size: 32 + fields: + - name: FSUB_PIN + description: Flash is connected to SPI SUBPIN bus. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SSUB_PIN + description: Ext_RAM is connected to SPI SUBPIN bus. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CK_IDLE_EDGE + description: "1: SPI_CLK line is high when idle. 0: SPI_CLK line is low when idle" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CS_KEEP_ACTIVE + description: SPI_CS line keep low when the bit is set. + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: CACHE_FCTRL + description: SPI0 external RAM bit mode control register. + addressOffset: 60 + size: 32 + fields: + - name: CACHE_REQ_EN + description: "Set this bit to enable Cache's access and SPI0's transfer." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CACHE_USR_CMD_4BYTE + description: Set this bit to enable SPI0 read flash with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CACHE_FLASH_USR_CMD + description: "1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FDIN_DUAL + description: "When SPI0 accesses to flash, set this bit to enable 2-bm in DIN phase." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FDOUT_DUAL + description: "When SPI0 accesses to flash, set this bit to enable 2-bm in DOUT phase." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FADDR_DUAL + description: "When SPI0 accesses to flash, set this bit to enable 2-bm in ADDR phase." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FDIN_QUAD + description: "When SPI0 accesses to flash, set this bit to enable 4-bm in DIN phase." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FDOUT_QUAD + description: "When SPI0 accesses to flash, set this bit to enable 4-bm in DOUT phase." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FADDR_QUAD + description: "When SPI0 accesses to flash, set this bit to enable 4-bm in ADDR phase." + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: CACHE_SCTRL + description: SPI0 external RAM control register + addressOffset: 64 + size: 32 + resetValue: 5619824 + fields: + - name: CACHE_USR_SCMD_4BYTE + description: Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: USR_SRAM_DIO + description: Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: USR_SRAM_QIO + description: Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: USR_WR_SRAM_DUMMY + description: "When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: USR_RD_SRAM_DUMMY + description: "When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CACHE_SRAM_USR_RCMD + description: "1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SRAM_RDUMMY_CYCLELEN + description: "When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer." + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: SRAM_ADDR_BITLEN + description: "When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1)." + bitOffset: 14 + bitWidth: 6 + access: read-write + - name: CACHE_SRAM_USR_WCMD + description: "1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SRAM_OCT + description: Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SRAM_WDUMMY_CYCLELEN + description: "When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer." + bitOffset: 22 + bitWidth: 6 + access: read-write + - register: + name: SRAM_CMD + description: SPI0 external RAM mode control register + addressOffset: 68 + size: 32 + fields: + - name: SCLK_MODE + description: "SPI_CLK mode bits when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inactive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two cycles after CS inactive 3: SPI_CLK is always on." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SWB_MODE + description: Mode bits when SPI0 accesses to Ext_RAM. + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: SDIN_DUAL + description: "When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SDOUT_DUAL + description: "When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: SADDR_DUAL + description: "When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in ADDR phase." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SCMD_DUAL + description: "When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SDIN_QUAD + description: "When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DIN phase." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SDOUT_QUAD + description: "When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DOUT phase." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SADDR_QUAD + description: "When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in ADDR phase." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SCMD_QUAD + description: "When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: SDIN_OCT + description: "When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SDOUT_OCT + description: "When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SADDR_OCT + description: "When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in ADDR phase." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: SCMD_OCT + description: "When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SDUMMY_OUT + description: "When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal level of SPI bus is output by the SPI0 controller." + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: SRAM_DRD_CMD + description: SPI0 external RAM DDR read command control register + addressOffset: 72 + size: 32 + fields: + - name: CACHE_SRAM_USR_RD_CMD_VALUE + description: "When SPI0 reads Ext_RAM, it is the command value of CMD phase." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CACHE_SRAM_USR_RD_CMD_BITLEN + description: "When SPI0 reads Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1)." + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: SRAM_DWR_CMD + description: SPI0 external RAM DDR write command control register + addressOffset: 76 + size: 32 + fields: + - name: CACHE_SRAM_USR_WR_CMD_VALUE + description: "When SPI0 writes Ext_RAM, it is the command value of CMD phase." + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: CACHE_SRAM_USR_WR_CMD_BITLEN + description: "When SPI0 writes Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1)." + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: SRAM_CLK + description: SPI_CLK clock division register when SPI0 accesses to Ext_RAM. + addressOffset: 80 + size: 32 + resetValue: 196867 + fields: + - name: SCLKCNT_L + description: It must equal to the value of SPI_MEM_SCLKCNT_N. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SCLKCNT_H + description: It must be a floor value of ((SPI_MEM_SCLKCNT_N+1)/2-1). + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SCLKCNT_N + description: "When SPI0 accesses to Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_SCLKCNT_N+1)" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: SCLK_EQU_SYSCLK + description: "When SPI0 accesses to Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: FSM + description: SPI0 state machine(FSM) status register. + addressOffset: 84 + size: 32 + fields: + - name: ST + description: "The status of SPI0 state machine. 0: idle state(IDLE), 1: preparation state(PREP), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DIN), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE)." + bitOffset: 0 + bitWidth: 3 + access: read-only + - register: + name: TIMING_CALI + description: SPI0 timing compensation register when accesses to flash. + addressOffset: 168 + size: 32 + fields: + - name: TIMING_CLK_ENA + description: "Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TIMING_CALI + description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EXTRA_DUMMY_CYCLELEN + description: "Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to flash. Active when SPI_MEM_TIMING_CALI bit is set." + bitOffset: 2 + bitWidth: 3 + access: read-write + - register: + name: DIN_MODE + description: MSPI input timing delay mode control register when accesses to flash. + addressOffset: 172 + size: 32 + fields: + - name: DIN0_MODE + description: "SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN0_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: DIN1_MODE + description: "SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN3_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: DIN2_MODE + description: "SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN6_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: DIN3_MODE + description: "SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN9_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: DIN4_MODE + description: "SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN12_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: DIN5_MODE + description: "SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN15_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: DIN6_MODE + description: "SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN18_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: DIN7_MODE + description: "SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN21_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 21 + bitWidth: 3 + access: read-write + - name: DINS_MODE + description: "SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 24 + bitWidth: 3 + access: read-write + - register: + name: DIN_NUM + description: MSPI input timing delay number control register when accesses to flash. + addressOffset: 176 + size: 32 + fields: + - name: DIN0_NUM + description: SPI_D input delay number. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DIN1_NUM + description: SPI_Q input delay number. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DIN2_NUM + description: SPI_WP input delay number. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DIN3_NUM + description: SPI_HD input delay number. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DIN4_NUM + description: SPI_IO4 input delay number. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: DIN5_NUM + description: SPI_IO5 input delay number. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DIN6_NUM + description: SPI_IO6 input delay number. + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DIN7_NUM + description: SPI_IO7 input delay number. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: DINS_NUM + description: SPI_DQS input delay number. + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: DOUT_MODE + description: MSPI output timing delay mode control register when accesses to flash. + addressOffset: 180 + size: 32 + fields: + - name: DOUT0_MODE + description: "SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DOUT1_MODE + description: "SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DOUT2_MODE + description: "SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DOUT3_MODE + description: "SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DOUT4_MODE + description: "SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DOUT5_MODE + description: "SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DOUT6_MODE + description: "SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: DOUT7_MODE + description: "SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: DOUTS_MODE + description: "SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: SPI_SMEM_TIMING_CALI + description: SPI0 Ext_RAM timing compensation register. + addressOffset: 188 + size: 32 + fields: + - name: SPI_SMEM_TIMING_CLK_ENA + description: "Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_TIMING_CALI + description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_EXTRA_DUMMY_CYCLELEN + description: "Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set." + bitOffset: 2 + bitWidth: 3 + access: read-write + - register: + name: SPI_SMEM_DIN_MODE + description: MSPI input timing delay mode control register when accesses to Ext_RAM. + addressOffset: 192 + size: 32 + fields: + - name: SPI_SMEM_DIN0_MODE + description: "SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN0_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DIN1_MODE + description: "SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN3_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 3 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DIN2_MODE + description: "SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN6_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 6 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DIN3_MODE + description: "SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN9_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 9 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DIN4_MODE + description: "SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN12_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DIN5_MODE + description: "SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN15_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DIN6_MODE + description: "SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN18_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DIN7_MODE + description: "SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN21_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 21 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_DINS_MODE + description: "SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 24 + bitWidth: 3 + access: read-write + - register: + name: SPI_SMEM_DIN_NUM + description: MSPI input timing delay number control register when accesses to Ext_RAM. + addressOffset: 196 + size: 32 + fields: + - name: SPI_SMEM_DIN0_NUM + description: SPI_D input delay number. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_DIN1_NUM + description: SPI_Q input delay number. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_DIN2_NUM + description: SPI_WP input delay number. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_DIN3_NUM + description: SPI_HD input delay number. + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_DIN4_NUM + description: SPI_IO4 input delay number. + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_DIN5_NUM + description: SPI_IO5 input delay number. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_DIN6_NUM + description: SPI_IO6 input delay number. + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_DIN7_NUM + description: SPI_IO7 input delay number. + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: SPI_SMEM_DINS_NUM + description: SPI_DQS input delay number. + bitOffset: 16 + bitWidth: 2 + access: read-write + - register: + name: SPI_SMEM_DOUT_MODE + description: MSPI output timing delay mode control register when accesses to Ext_RAM. + addressOffset: 200 + size: 32 + fields: + - name: SPI_SMEM_DOUT0_MODE + description: "SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DOUT1_MODE + description: "SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DOUT2_MODE + description: "SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DOUT3_MODE + description: "SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DOUT4_MODE + description: "SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DOUT5_MODE + description: "SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DOUT6_MODE + description: "SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DOUT7_MODE + description: "SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DOUTS_MODE + description: "SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge." + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: ECC_CTRL + description: MSPI ECC control register + addressOffset: 204 + size: 32 + resetValue: 10 + fields: + - name: ECC_ERR_INT_NUM + description: Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SPI_FMEM_ECC_ERR_INT_EN + description: Set this bit to calculate the error times of MSPI ECC read when accesses to flash. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: ECC_ERR_ADDR + description: MSPI ECC error address register + addressOffset: 208 + size: 32 + fields: + - name: ECC_ERR_ADDR + description: "These bits show the first MSPI ECC error address when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM, including ECC byte error and data error. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: ECC_ERR_BIT + description: MSPI ECC error bits register + addressOffset: 212 + size: 32 + fields: + - name: ECC_DATA_ERR_BIT + description: "It records the first ECC data error bit number when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. The value ranges from 0~127, corresponding to the bit number in 16 data bytes. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit." + bitOffset: 6 + bitWidth: 7 + access: read-only + - name: ECC_CHK_ERR_BIT + description: "When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error bit number of ECC byte." + bitOffset: 13 + bitWidth: 3 + access: read-only + - name: ECC_BYTE_ERR + description: It records the first ECC byte error when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: ECC_ERR_CNT + description: "This bits show the error times of MSPI ECC read, including ECC byte error and data byte error. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set." + bitOffset: 17 + bitWidth: 8 + access: read-only + - register: + name: SPI_SMEM_AC + description: MSPI external RAM ECC and SPI CS timing control register + addressOffset: 220 + size: 32 + resetValue: 45188 + fields: + - name: SPI_SMEM_CS_SETUP + description: Set this bit to keep SPI_CS low when MSPI is in PREP state. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_CS_HOLD + description: Set this bit to keep SPI_CS low when MSPI is in DONE state. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_CS_SETUP_TIME + description: "(cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit." + bitOffset: 2 + bitWidth: 5 + access: read-write + - name: SPI_SMEM_CS_HOLD_TIME + description: "SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit." + bitOffset: 7 + bitWidth: 5 + access: read-write + - name: SPI_SMEM_ECC_CS_HOLD_TIME + description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accesses to external RAM. + bitOffset: 12 + bitWidth: 3 + access: read-write + - name: SPI_SMEM_ECC_SKIP_PAGE_CORNER + description: "1: MSPI skips page corner when accesses to external RAM. 0: Not skip page corner when accesses to external RAM." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_ECC_16TO18_BYTE_EN + description: Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses to external RAM. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_ECC_ERR_INT_EN + description: Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_CS_HOLD_DELAY + description: "These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles." + bitOffset: 25 + bitWidth: 6 + access: read-write + - register: + name: DDR + description: SPI0 flash DDR mode control register + addressOffset: 224 + size: 32 + resetValue: 12320 + fields: + - name: SPI_FMEM_DDR_EN + description: "1: in ddr mode, 0 in sdr mode" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_VAR_DUMMY + description: Set the bit to enable variable dummy cycle in DDR mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_DDR_RDAT_SWP + description: Set the bit to reorder RX data of the word in DDR mode. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_DDR_WDAT_SWP + description: Set the bit to swap TX data of a word in DDR mode. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_DDR_CMD_DIS + description: the bit is used to disable dual edge in CMD phase when ddr mode. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_OUTMINBYTELEN + description: It is the minimum output data length in the panda device. + bitOffset: 5 + bitWidth: 7 + access: read-write + - name: SPI_FMEM_TX_DDR_MSK_EN + description: "Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to flash." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_RX_DDR_MSK_EN + description: "Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to flash." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_USR_DDR_DQS_THD + description: The delay number of data strobe which from memory based on SPI_CLK. + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: SPI_FMEM_DDR_DQS_LOOP + description: "1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_DDR_DQS_LOOP_MODE + description: "When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_CLK_DIFF_EN + description: "Set this bit to enable the differential SPI_CLK#." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_HYPERBUS_MODE + description: Set this bit to enable the SPI HyperBus mode. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_DQS_CA_IN + description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_HYPERBUS_DUMMY_2X + description: "Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_CLK_DIFF_INV + description: Set this bit to invert SPI_DIFF when accesses to flash. . + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_OCTA_RAM_ADDR + description: "Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_HYPERBUS_CA + description: "Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}." + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: SPI_SMEM_DDR + description: SPI0 external RAM DDR mode control register + addressOffset: 228 + size: 32 + resetValue: 12320 + fields: + - name: EN + description: "1: in ddr mode, 0 in sdr mode" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_VAR_DUMMY + description: Set the bit to enable variable dummy cycle in spi ddr mode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RDAT_SWP + description: Set the bit to reorder rx data of the word in spi ddr mode. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: WDAT_SWP + description: Set the bit to reorder tx data of the word in spi ddr mode. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CMD_DIS + description: the bit is used to disable dual edge in CMD phase when ddr mode. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_OUTMINBYTELEN + description: It is the minimum output data length in the ddr psram. + bitOffset: 5 + bitWidth: 7 + access: read-write + - name: SPI_SMEM_TX_DDR_MSK_EN + description: "Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to external RAM." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_RX_DDR_MSK_EN + description: "Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to external RAM." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_USR_DDR_DQS_THD + description: The delay number of data strobe which from memory based on SPI_CLK. + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: DQS_LOOP + description: "1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: DQS_LOOP_MODE + description: "When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_CLK_DIFF_EN + description: "Set this bit to enable the differential SPI_CLK#." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_HYPERBUS_MODE + description: Set this bit to enable the SPI HyperBus mode. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_DQS_CA_IN + description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_HYPERBUS_DUMMY_2X + description: "Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_CLK_DIFF_INV + description: Set this bit to invert SPI_DIFF when accesses to external RAM. . + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_OCTA_RAM_ADDR + description: "Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SPI_SMEM_HYPERBUS_CA + description: "Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}." + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: CLOCK_GATE + description: SPI0 clk_gate register + addressOffset: 232 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: "Register clock gate enable signal. 1: Enable. 0: Disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CORE_CLK_SEL + description: SPI0 module clock select register + addressOffset: 236 + size: 32 + fields: + - name: CORE_CLK_SEL + description: "When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of SPI_MEM_CORE_CLK_SEL: 0: SPI0/1 module clock (MSPI_CORE_CLK) is 80MHz. 1: MSPI_CORE_CLK is 120MHz. 2: MSPI_CORE_CLK is 160MHz. 3: MSPI_CORE_CLK is 240MHz. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of SPI_MEM_CORE_CLK_SEL: 0: MSPI_CORE_CLK is 80MHz. 1: MSPI_CORE_CLK is 80MHz. 2: MSPI_CORE_CLK 160MHz. 3: Not used." + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: INT_ENA + description: SPI1 interrupt enable register + addressOffset: 240 + size: 32 + fields: + - name: TOTAL_TRANS_END_INT_ENA + description: The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ECC_ERR_INT_ENA + description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: SPI1 interrupt clear register + addressOffset: 244 + size: 32 + fields: + - name: TOTAL_TRANS_END_INT_CLR + description: The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: ECC_ERR_INT_CLR + description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt. SPI_MEM_ECC_ERR_ADDR and SPI_MEM_ECC_ERR_CNT will be cleared by the pulse of this bit. + bitOffset: 4 + bitWidth: 1 + access: write-only + - register: + name: INT_RAW + description: SPI1 interrupt raw register + addressOffset: 248 + size: 32 + fields: + - name: TOTAL_TRANS_END_INT_RAW + description: "The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Others." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ECC_ERR_INT_RAW + description: "The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When APB_CTRL_FECC_ERR_INT_EN is set and APB_CTRL_SECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN is cleared and APB_CTRL_SECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are cleared, this bit will not be triggered." + bitOffset: 4 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: SPI1 interrupt status register + addressOffset: 252 + size: 32 + fields: + - name: TOTAL_TRANS_END_INT_ST + description: The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: ECC_ERR_INT_ST + description: The status bit for SPI_MEM_ECC_ERR_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: SPI0 version control register + addressOffset: 1020 + size: 32 + resetValue: 34607168 + fields: + - name: SPI_SMEM_SPICLK_FUN_DRV + description: "The driver of SPI_CLK PAD is controlled by the bits SPI_SMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to external RAM." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: SPI_FMEM_SPICLK_FUN_DRV + description: "The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to flash." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: SPI_SPICLK_PAD_DRV_CTL_EN + description: "SPI_CLK PAD driver control signal. 1: The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] and SPI_SMEM_SPICLK_FUN_DRV[1:0]. 0: The driver of SPI_CLK PAD is controlled by the bits IO_MUX_FUNC_DRV[1:0] of SPICLK PAD." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DATE + description: SPI register version. + bitOffset: 5 + bitWidth: 23 + access: read-write + - name: SPI1 + description: SPI (Serial Peripheral Interface) Controller 1 + groupName: SPI1 + baseAddress: 1610620928 + addressBlock: + - offset: 0 + size: 180 + usage: registers + interrupt: + - name: SPI1 + value: 20 + registers: + - register: + name: CMD + description: SPI1 memory command register + addressOffset: 0 + size: 32 + fields: + - name: FLASH_PE + description: "In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: USR + description: "User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: FLASH_HPM + description: "Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: FLASH_RES + description: "This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: FLASH_DP + description: "Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: FLASH_CE + description: "Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: FLASH_BE + description: "Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: FLASH_SE + description: "Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: FLASH_PP + description: "Page program enable(1 byte ~64 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: FLASH_WRSR + description: "Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: FLASH_RDSR + description: "Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: FLASH_RDID + description: "Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: FLASH_WRDI + description: "Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: FLASH_WREN + description: "Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: FLASH_READ + description: "Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: ADDR + description: SPI1 address register + addressOffset: 4 + size: 32 + fields: + - name: USR_ADDR_VALUE + description: "In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CTRL + description: SPI1 control register + addressOffset: 8 + size: 32 + resetValue: 2924544 + fields: + - name: FDUMMY_OUT + description: In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FDOUT_OCT + description: Set this bit to enable 8-bit-mode(8-bm) in DOUT phase. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FDIN_OCT + description: Set this bit to enable 8-bit-mode(8-bm) in DIN phase. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FADDR_OCT + description: Set this bit to enable 8-bit-mode(8-bm) in ADDR phase. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FCMD_DUAL + description: Set this bit to enable 2-bit-mode(2-bm) in CMD phase. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FCMD_QUAD + description: Set this bit to enable 4-bit-mode(4-bm) in CMD phase. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FCMD_OCT + description: Set this bit to enable 8-bit-mode(8-bm) in CMD phase. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FCS_CRC_EN + description: "For SPI1, initialize crc32 module before writing encrypted data to flash. Active low." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: TX_CRC_EN + description: "For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: FASTRD_MODE + description: "This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FREAD_DUAL + description: "In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RESANDRES + description: "The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: Q_POL + description: "The bit is used to set MISO line polarity, 1: high 0, low" + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: D_POL + description: "The bit is used to set MOSI line polarity, 1: high 0, low" + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: FREAD_QUAD + description: "In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: WP + description: "Write protect signal output when SPI is idle. 1: output high, 0: output low." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: WRSR_2B + description: "Two bytes data will be written to status register when it is set. 1: enable 0: disable." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: FREAD_DIO + description: "In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: FREAD_QIO + description: "In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: CTRL1 + description: SPI1 control1 register + addressOffset: 12 + size: 32 + resetValue: 4092 + fields: + - name: CLK_MODE + description: "SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CS_HOLD_DLY_RES + description: "After RES/DP/HPM/PES/PER command is sent, SPI1 may waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or * 256) SPI_CLK cycles." + bitOffset: 2 + bitWidth: 10 + access: read-write + - register: + name: CTRL2 + description: SPI1 control2 register + addressOffset: 16 + size: 32 + fields: + - name: SYNC_RESET + description: The FSM will be reset. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: CLOCK + description: SPI_CLK clock division register when SPI1 accesses to flash or Ext_RAM. + addressOffset: 20 + size: 32 + resetValue: 196867 + fields: + - name: CLKCNT_L + description: It must equal to the value of SPI_MEM_CLKCNT_N. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CLKCNT_H + description: It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1). + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: CLKCNT_N + description: "When SPI1 accesses to flash or Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1)" + bitOffset: 16 + bitWidth: 8 + access: read-write + - name: CLK_EQU_SYSCLK + description: "When SPI1 access to flash or Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USER + description: SPI1 user register. + addressOffset: 24 + size: 32 + resetValue: 2147483648 + fields: + - name: CK_OUT_EDGE + description: "This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FWRITE_DUAL + description: Set this bit to enable 2-bm in DOUT phase in SPI1 write operation. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FWRITE_QUAD + description: Set this bit to enable 4-bm in DOUT phase in SPI1 write operation. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FWRITE_DIO + description: Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: FWRITE_QIO + description: Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write operation. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: USR_MISO_HIGHPART + description: "DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: USR_MOSI_HIGHPART + description: "DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: USR_DUMMY_IDLE + description: SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: USR_MOSI + description: Set this bit to enable the DOUT phase of an write-data operation. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: USR_MISO + description: Set this bit to enable enable the DIN phase of a read-data operation. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: USR_DUMMY + description: Set this bit to enable enable the DUMMY phase of an operation. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: USR_ADDR + description: Set this bit to enable enable the ADDR phase of an operation. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: USR_COMMAND + description: Set this bit to enable enable the CMD phase of an operation. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USER1 + description: SPI1 user1 register. + addressOffset: 28 + size: 32 + resetValue: 1543503879 + fields: + - name: USR_DUMMY_CYCLELEN + description: The SPI_CLK cycle length minus 1 of DUMMY phase. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: USR_ADDR_BITLEN + description: The length in bits of ADDR phase. The register value shall be (bit_num-1). + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: USER2 + description: SPI1 user2 register. + addressOffset: 32 + size: 32 + resetValue: 1879048192 + fields: + - name: USR_COMMAND_VALUE + description: The value of user defined(USR) command. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: USR_COMMAND_BITLEN + description: The length in bits of CMD phase. The register value shall be (bit_num-1) + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: MOSI_DLEN + description: SPI1 write-data bit length register. + addressOffset: 36 + size: 32 + fields: + - name: USR_MOSI_DBITLEN + description: The length in bits of DOUT phase. The register value shall be (bit_num-1). + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: MISO_DLEN + description: SPI1 read-data bit length register. + addressOffset: 40 + size: 32 + fields: + - name: USR_MISO_DBITLEN + description: The length in bits of DIN phase. The register value shall be (bit_num-1). + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: RD_STATUS + description: SPI1 read control register. + addressOffset: 44 + size: 32 + fields: + - name: STATUS + description: The value is stored when set SPI_MEM_FLASH_RDSR bit and SPI_MEM_FLASH_RES bit. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: WB_MODE + description: Mode bits in the flash fast read mode it is combined with SPI_MEM_FASTRD_MODE bit. + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: EXT_ADDR + description: SPI1 extended address register. + addressOffset: 48 + size: 32 + fields: + - name: EXT_ADDR + description: The register are the higher 32bits in the 64 bits address mode. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: MISC + description: SPI1 misc register. + addressOffset: 52 + size: 32 + resetValue: 2 + fields: + - name: CS0_DIS + description: "Set this bit to raise high SPI_CS pin, which means that the SPI device(flash) connected to SPI_CS is in low level when SPI1 transfer starts." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CS1_DIS + description: "Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM) connected to SPI_CS1 is in low level when SPI1 transfer starts." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CK_IDLE_EDGE + description: "1: SPI_CLK line is high when MSPI is idle. 0: SPI_CLK line is low when MSPI is idle." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: CS_KEEP_ACTIVE + description: SPI_CS line keep low when the bit is set. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: AUTO_PER + description: Set this bit to enable auto PER function. Hardware will sent out PER command if PES command is sent. + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: TX_CRC + description: SPI1 CRC data register. + addressOffset: 56 + size: 32 + resetValue: 4294967295 + fields: + - name: DATA + description: "For SPI1, the value of crc32." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: CACHE_FCTRL + description: SPI1 bit mode control register. + addressOffset: 60 + size: 32 + fields: + - name: CACHE_USR_CMD_4BYTE + description: Set this bit to enable SPI1 transfer with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FDIN_DUAL + description: "When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DIN phase." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FDOUT_DUAL + description: "When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DOUT phase." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FADDR_DUAL + description: "When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in ADDR phase." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FDIN_QUAD + description: "When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DIN phase." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FDOUT_QUAD + description: "When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DOUT phase." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FADDR_QUAD + description: "When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in ADDR phase." + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: FSM + description: SPI1 state machine(FSM) status register. + addressOffset: 84 + size: 32 + fields: + - name: ST + description: "The status of SPI1 state machine. 0: idle state(IDLE), 1: preparation state(PREP), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DIN), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE)." + bitOffset: 0 + bitWidth: 3 + access: read-only + - register: + name: W0 + description: SPI1 memory data buffer0 + addressOffset: 88 + size: 32 + fields: + - name: BUF0 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W1 + description: SPI1 memory data buffer1 + addressOffset: 92 + size: 32 + fields: + - name: BUF1 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W2 + description: SPI1 memory data buffer2 + addressOffset: 96 + size: 32 + fields: + - name: BUF2 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W3 + description: SPI1 memory data buffer3 + addressOffset: 100 + size: 32 + fields: + - name: BUF3 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W4 + description: SPI1 memory data buffer4 + addressOffset: 104 + size: 32 + fields: + - name: BUF4 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W5 + description: SPI1 memory data buffer5 + addressOffset: 108 + size: 32 + fields: + - name: BUF5 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W6 + description: SPI1 memory data buffer6 + addressOffset: 112 + size: 32 + fields: + - name: BUF6 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W7 + description: SPI1 memory data buffer7 + addressOffset: 116 + size: 32 + fields: + - name: BUF7 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W8 + description: SPI1 memory data buffer8 + addressOffset: 120 + size: 32 + fields: + - name: BUF8 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W9 + description: SPI1 memory data buffer9 + addressOffset: 124 + size: 32 + fields: + - name: BUF9 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W10 + description: SPI1 memory data buffer10 + addressOffset: 128 + size: 32 + fields: + - name: BUF10 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W11 + description: SPI1 memory data buffer11 + addressOffset: 132 + size: 32 + fields: + - name: BUF11 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W12 + description: SPI1 memory data buffer12 + addressOffset: 136 + size: 32 + fields: + - name: BUF12 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W13 + description: SPI1 memory data buffer13 + addressOffset: 140 + size: 32 + fields: + - name: BUF13 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W14 + description: SPI1 memory data buffer14 + addressOffset: 144 + size: 32 + fields: + - name: BUF14 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W15 + description: SPI1 memory data buffer15 + addressOffset: 148 + size: 32 + fields: + - name: BUF15 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: FLASH_WAITI_CTRL + description: SPI1 wait idle control register + addressOffset: 152 + size: 32 + resetValue: 20 + fields: + - name: WAITI_EN + description: Set this bit to enable auto-waiting flash idle operation when PP/SE/BE/CE/WRSR/PES command is sent. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: WAITI_DUMMY + description: Set this bit to enable DUMMY phase in auto wait flash idle transfer(RDSR). + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: WAITI_CMD + description: The command value of auto wait flash idle transfer(RDSR). + bitOffset: 2 + bitWidth: 8 + access: read-write + - name: WAITI_DUMMY_CYCLELEN + description: The dummy cycle length when wait flash idle(RDSR). + bitOffset: 10 + bitWidth: 6 + access: read-write + - register: + name: FLASH_SUS_CMD + description: SPI1 flash suspend control register + addressOffset: 156 + size: 32 + fields: + - name: FLASH_PER + description: "program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FLASH_PES + description: "program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FLASH_PER_WAIT_EN + description: Set this bit to add delay time after program erase resume(PER) is sent. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FLASH_PES_WAIT_EN + description: Set this bit to add delay time after program erase suspend(PES) command is sent. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PES_PER_EN + description: Set this bit to enable PES transfer trigger PES transfer option. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: PESR_IDLE_EN + description: "1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate." + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: FLASH_SUS_CTRL + description: SPI1 flash suspend command register + addressOffset: 160 + size: 32 + resetValue: 60148 + fields: + - name: FLASH_PES_EN + description: Set this bit to enable auto-suspend function. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FLASH_PER_COMMAND + description: Program/Erase resume command value. + bitOffset: 1 + bitWidth: 8 + access: read-write + - name: FLASH_PES_COMMAND + description: Program/Erase suspend command value. + bitOffset: 9 + bitWidth: 8 + access: read-write + - register: + name: SUS_STATUS + description: SPI1 flash suspend status register + addressOffset: 164 + size: 32 + fields: + - name: FLASH_SUS + description: "The status of flash suspend. This bit is set when PES command is sent, and cleared when PER is sent. Only used in SPI1." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: FLASH_HPM_DLY_256 + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FLASH_RES_DLY_256 + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FLASH_DP_DLY_256 + description: "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: FLASH_PER_DLY_256 + description: "Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FLASH_PES_DLY_256 + description: "Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent." + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: TIMING_CALI + description: SPI1 timing compensation register when accesses to flash or Ext_RAM. + addressOffset: 168 + size: 32 + fields: + - name: TIMING_CALI + description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EXTRA_DUMMY_CYCLELEN + description: Extra SPI_CLK cycles added in DUMMY phase for timing compensation. Active when SPI_MEM_TIMING_CALI bit is set. + bitOffset: 2 + bitWidth: 3 + access: read-write + - register: + name: DDR + description: SPI1 DDR control register + addressOffset: 224 + size: 32 + resetValue: 32 + fields: + - name: SPI_FMEM_DDR_EN + description: "1: in DDR mode, 0: in SDR mode." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_VAR_DUMMY + description: Set the bit to enable variable dummy cycle in DDRmode. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_DDR_RDAT_SWP + description: Set the bit to reorder RX data of the word in DDR mode. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_DDR_WDAT_SWP + description: Set the bit to reorder TX data of the word in DDR mode. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_DDR_CMD_DIS + description: the bit is used to disable dual edge in command phase when DDR mode. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_OUTMINBYTELEN + description: It is the minimum output data length in the panda device. + bitOffset: 5 + bitWidth: 7 + access: read-write + - name: SPI_FMEM_USR_DDR_DQS_THD + description: The delay number of data strobe which from memory based on SPI_CLK. + bitOffset: 14 + bitWidth: 7 + access: read-write + - name: SPI_FMEM_DDR_DQS_LOOP + description: "1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module" + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_DDR_DQS_LOOP_MODE + description: "When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active." + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_CLK_DIFF_EN + description: "Set this bit to enable the differential SPI_CLK#." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_HYPERBUS_MODE + description: Set this bit to enable the SPI HyperBus mode. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_DQS_CA_IN + description: Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_HYPERBUS_DUMMY_2X + description: "Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_CLK_DIFF_INV + description: Set this bit to invert SPI_DIFF when accesses to flash. . + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_OCTA_RAM_ADDR + description: "Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SPI_FMEM_HYPERBUS_CA + description: "Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}." + bitOffset: 30 + bitWidth: 1 + access: read-write + - register: + name: CLOCK_GATE + description: SPI1 clk_gate register + addressOffset: 232 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: "Register clock gate enable signal. 1: Enable. 0: Disable." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: INT_ENA + description: SPI1 interrupt enable register + addressOffset: 240 + size: 32 + fields: + - name: PER_END_INT_ENA + description: The enable bit for SPI_MEM_PER_END_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PES_END_INT_ENA + description: The enable bit for SPI_MEM_PES_END_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TOTAL_TRANS_END_INT_ENA + description: The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_INT_ENA + description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: SPI1 interrupt clear register + addressOffset: 244 + size: 32 + fields: + - name: PER_END_INT_CLR + description: The clear bit for SPI_MEM_PER_END_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: PES_END_INT_CLR + description: The clear bit for SPI_MEM_PES_END_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TOTAL_TRANS_END_INT_CLR + description: The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: BROWN_OUT_INT_CLR + description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: INT_RAW + description: SPI1 interrupt raw register + addressOffset: 248 + size: 32 + fields: + - name: PER_END_INT_RAW + description: "The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PES_END_INT_RAW + description: "The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TOTAL_TRANS_END_INT_RAW + description: "The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Others." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: BROWN_OUT_INT_RAW + description: "The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others." + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: SPI1 interrupt status register + addressOffset: 252 + size: 32 + fields: + - name: PER_END_INT_ST + description: The status bit for SPI_MEM_PER_END_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PES_END_INT_ST + description: The status bit for SPI_MEM_PES_END_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TOTAL_TRANS_END_INT_ST + description: The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: BROWN_OUT_INT_ST + description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: SPI0 version control register + addressOffset: 1020 + size: 32 + resetValue: 34607168 + fields: + - name: DATE + description: SPI register version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SPI2 + description: SPI (Serial Peripheral Interface) Controller 2 + groupName: SPI2 + baseAddress: 1610760192 + addressBlock: + - offset: 0 + size: 152 + usage: registers + interrupt: + - name: SPI2 + value: 21 + - name: SPI2_DMA + value: 44 + registers: + - register: + name: CMD + description: Command control register + addressOffset: 0 + size: 32 + fields: + - name: CONF_BITLEN + description: Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 18 + access: read-write + - name: UPDATE + description: "Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: USR + description: "User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf." + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: ADDR + description: Address value register + addressOffset: 4 + size: 32 + fields: + - name: USR_ADDR_VALUE + description: Address to slave. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CTRL + description: SPI control register + addressOffset: 8 + size: 32 + resetValue: 3932160 + fields: + - name: DUMMY_OUT + description: "0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: FADDR_DUAL + description: "Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: FADDR_QUAD + description: "Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: FADDR_OCT + description: "Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: FCMD_DUAL + description: "Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: FCMD_QUAD + description: "Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FCMD_OCT + description: "Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: FREAD_DUAL + description: "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: FREAD_QUAD + description: "In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: FREAD_OCT + description: "In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: Q_POL + description: "The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: D_POL + description: "The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: HOLD_POL + description: "SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: WP_POL + description: "Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: RD_BIT_ORDER + description: "In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state." + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: WR_BIT_ORDER + description: "In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state." + bitOffset: 25 + bitWidth: 2 + access: read-write + - register: + name: CLOCK + description: SPI clock control register + addressOffset: 12 + size: 32 + resetValue: 2147496003 + fields: + - name: CLKCNT_L + description: In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: CLKCNT_H + description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: CLKCNT_N + description: In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state. + bitOffset: 12 + bitWidth: 6 + access: read-write + - name: CLKDIV_PRE + description: In the master mode it is pre-divider of spi_clk. Can be configured in CONF state. + bitOffset: 18 + bitWidth: 4 + access: read-write + - name: CLK_EQU_SYSCLK + description: "In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USER + description: SPI USER control register + addressOffset: 16 + size: 32 + resetValue: 2147483840 + fields: + - name: DOUTDIN + description: "Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: QPI_MODE + description: "Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OPI_MODE + description: "Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TSCK_I_EDGE + description: "In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CS_HOLD + description: "spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CS_SETUP + description: "spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RSCK_I_EDGE + description: "In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: CK_OUT_EDGE + description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: FWRITE_DUAL + description: In the write operations read-data phase apply 2 signals. Can be configured in CONF state. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: FWRITE_QUAD + description: In the write operations read-data phase apply 4 signals. Can be configured in CONF state. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: FWRITE_OCT + description: In the write operations read-data phase apply 8 signals. Can be configured in CONF state. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: USR_CONF_NXT + description: "1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SIO + description: "Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: USR_MISO_HIGHPART + description: "read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: USR_MOSI_HIGHPART + description: "write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: USR_DUMMY_IDLE + description: spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state. + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: USR_MOSI + description: This bit enable the write-data phase of an operation. Can be configured in CONF state. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: USR_MISO + description: This bit enable the read-data phase of an operation. Can be configured in CONF state. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: USR_DUMMY + description: This bit enable the dummy phase of an operation. Can be configured in CONF state. + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: USR_ADDR + description: This bit enable the address phase of an operation. Can be configured in CONF state. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: USR_COMMAND + description: This bit enable the command phase of an operation. Can be configured in CONF state. + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: USER1 + description: SPI USER control register 1 + addressOffset: 20 + size: 32 + resetValue: 3091267591 + fields: + - name: USR_DUMMY_CYCLELEN + description: The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: MST_WFULL_ERR_END_EN + description: "1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: CS_SETUP_TIME + description: (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state. + bitOffset: 17 + bitWidth: 5 + access: read-write + - name: CS_HOLD_TIME + description: delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state. + bitOffset: 22 + bitWidth: 5 + access: read-write + - name: USR_ADDR_BITLEN + description: The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 27 + bitWidth: 5 + access: read-write + - register: + name: USER2 + description: SPI USER control register 2 + addressOffset: 24 + size: 32 + resetValue: 2013265920 + fields: + - name: USR_COMMAND_VALUE + description: The value of command. Can be configured in CONF state. + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: MST_REMPTY_ERR_END_EN + description: "1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode." + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: USR_COMMAND_BITLEN + description: The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 28 + bitWidth: 4 + access: read-write + - register: + name: MS_DLEN + description: SPI data bit length control register + addressOffset: 28 + size: 32 + fields: + - name: MS_DATA_BITLEN + description: The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state. + bitOffset: 0 + bitWidth: 18 + access: read-write + - register: + name: MISC + description: SPI misc register + addressOffset: 32 + size: 32 + resetValue: 62 + fields: + - name: CS0_DIS + description: "SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CS1_DIS + description: "SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CS2_DIS + description: "SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CS3_DIS + description: "SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CS4_DIS + description: "SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CS5_DIS + description: "SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CK_DIS + description: "1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: MASTER_CS_POL + description: "In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 6 + access: read-write + - name: CLK_DATA_DTR_EN + description: "1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: DATA_DTR_EN + description: "1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: ADDR_DTR_EN + description: "1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: CMD_DTR_EN + description: "1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SLAVE_CS_POL + description: "spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: DQS_IDLE_EDGE + description: The default value of spi_dqs. Can be configured in CONF state. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: CK_IDLE_EDGE + description: "1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: CS_KEEP_ACTIVE + description: spi cs line keep low when the bit is set. Can be configured in CONF state. + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: QUAD_DIN_PIN_SWAP + description: "1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DIN_MODE + description: SPI input delay mode configuration + addressOffset: 36 + size: 32 + fields: + - name: DIN0_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DIN1_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DIN2_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DIN3_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DIN4_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: DIN5_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DIN6_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DIN7_MODE + description: "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state." + bitOffset: 14 + bitWidth: 2 + access: read-write + - name: TIMING_HCLK_ACTIVE + description: "1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state." + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: DIN_NUM + description: SPI input delay number configuration + addressOffset: 40 + size: 32 + fields: + - name: DIN0_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DIN1_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: DIN2_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: DIN3_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 6 + bitWidth: 2 + access: read-write + - name: DIN4_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 8 + bitWidth: 2 + access: read-write + - name: DIN5_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: DIN6_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 12 + bitWidth: 2 + access: read-write + - name: DIN7_NUM + description: "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state." + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: DOUT_MODE + description: SPI output delay mode configuration + addressOffset: 44 + size: 32 + fields: + - name: DOUT0_MODE + description: "The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DOUT1_MODE + description: "The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DOUT2_MODE + description: "The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DOUT3_MODE + description: "The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DOUT4_MODE + description: "The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DOUT5_MODE + description: "The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DOUT6_MODE + description: "The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: DOUT7_MODE + description: "The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: D_DQS_MODE + description: "The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state." + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: DMA_CONF + description: SPI DMA control register + addressOffset: 48 + size: 32 + resetValue: 3 + fields: + - name: DMA_OUTFIFO_EMPTY + description: "Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DMA_INFIFO_FULL + description: "Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: DMA_SLV_SEG_TRANS_EN + description: "Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: SLV_RX_SEG_TRANS_CLR_EN + description: "1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done." + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SLV_TX_SEG_TRANS_CLR_EN + description: "1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done." + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: RX_EOF_EN + description: "1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: DMA_RX_ENA + description: Set this bit to enable SPI DMA controlled receive data mode. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: DMA_TX_ENA + description: Set this bit to enable SPI DMA controlled send data mode. + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: RX_AFIFO_RST + description: "Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer." + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: BUF_AFIFO_RST + description: "Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer." + bitOffset: 30 + bitWidth: 1 + access: write-only + - name: DMA_AFIFO_RST + description: "Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer." + bitOffset: 31 + bitWidth: 1 + access: write-only + - register: + name: DMA_INT_ENA + description: SPI interrupt enable register + addressOffset: 52 + size: 32 + fields: + - name: DMA_INFIFO_FULL_ERR_INT_ENA + description: The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DMA_OUTFIFO_EMPTY_ERR_INT_ENA + description: The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SLV_EX_QPI_INT_ENA + description: The enable bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLV_EN_QPI_INT_ENA + description: The enable bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLV_CMD7_INT_ENA + description: The enable bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SLV_CMD8_INT_ENA + description: The enable bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SLV_CMD9_INT_ENA + description: The enable bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SLV_CMDA_INT_ENA + description: The enable bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SLV_RD_DMA_DONE_INT_ENA + description: The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLV_WR_DMA_DONE_INT_ENA + description: The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLV_RD_BUF_DONE_INT_ENA + description: The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLV_WR_BUF_DONE_INT_ENA + description: The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TRANS_DONE_INT_ENA + description: The enable bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DMA_SEG_TRANS_DONE_INT_ENA + description: The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SEG_MAGIC_ERR_INT_ENA + description: The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLV_BUF_ADDR_ERR_INT_ENA + description: The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLV_CMD_ERR_INT_ENA + description: The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: MST_RX_AFIFO_WFULL_ERR_INT_ENA + description: The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MST_TX_AFIFO_REMPTY_ERR_INT_ENA + description: The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: APP2_INT_ENA + description: The enable bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: APP1_INT_ENA + description: The enable bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: DMA_INT_CLR + description: SPI interrupt clear register + addressOffset: 56 + size: 32 + fields: + - name: DMA_INFIFO_FULL_ERR_INT_CLR + description: The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: DMA_OUTFIFO_EMPTY_ERR_INT_CLR + description: The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SLV_EX_QPI_INT_CLR + description: The clear bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SLV_EN_QPI_INT_CLR + description: The clear bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SLV_CMD7_INT_CLR + description: The clear bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SLV_CMD8_INT_CLR + description: The clear bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: SLV_CMD9_INT_CLR + description: The clear bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: SLV_CMDA_INT_CLR + description: The clear bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SLV_RD_DMA_DONE_INT_CLR + description: The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SLV_WR_DMA_DONE_INT_CLR + description: The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SLV_RD_BUF_DONE_INT_CLR + description: The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SLV_WR_BUF_DONE_INT_CLR + description: The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TRANS_DONE_INT_CLR + description: The clear bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: DMA_SEG_TRANS_DONE_INT_CLR + description: The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SEG_MAGIC_ERR_INT_CLR + description: The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SLV_BUF_ADDR_ERR_INT_CLR + description: The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: SLV_CMD_ERR_INT_CLR + description: The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: MST_RX_AFIFO_WFULL_ERR_INT_CLR + description: The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: MST_TX_AFIFO_REMPTY_ERR_INT_CLR + description: The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: APP2_INT_CLR + description: The clear bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: APP1_INT_CLR + description: The clear bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: write-only + - register: + name: DMA_INT_RAW + description: SPI interrupt raw register + addressOffset: 60 + size: 32 + fields: + - name: DMA_INFIFO_FULL_ERR_INT_RAW + description: "1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DMA_OUTFIFO_EMPTY_ERR_INT_RAW + description: "1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SLV_EX_QPI_INT_RAW + description: "The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SLV_EN_QPI_INT_RAW + description: "The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others." + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLV_CMD7_INT_RAW + description: "The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SLV_CMD8_INT_RAW + description: "The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SLV_CMD9_INT_RAW + description: "The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others." + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SLV_CMDA_INT_RAW + description: "The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others." + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SLV_RD_DMA_DONE_INT_RAW + description: "The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLV_WR_DMA_DONE_INT_RAW + description: "The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLV_RD_BUF_DONE_INT_RAW + description: "The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLV_WR_BUF_DONE_INT_RAW + description: "The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TRANS_DONE_INT_RAW + description: "The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DMA_SEG_TRANS_DONE_INT_RAW + description: "The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred." + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: SEG_MAGIC_ERR_INT_RAW + description: "The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: SLV_BUF_ADDR_ERR_INT_RAW + description: "The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SLV_CMD_ERR_INT_RAW + description: "The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others." + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: MST_RX_AFIFO_WFULL_ERR_INT_RAW + description: "The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: MST_TX_AFIFO_REMPTY_ERR_INT_RAW + description: "The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others." + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: APP2_INT_RAW + description: The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: APP1_INT_RAW + description: The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software. + bitOffset: 20 + bitWidth: 1 + access: read-write + - register: + name: DMA_INT_ST + description: SPI interrupt status register + addressOffset: 64 + size: 32 + fields: + - name: DMA_INFIFO_FULL_ERR_INT_ST + description: The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: DMA_OUTFIFO_EMPTY_ERR_INT_ST + description: The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SLV_EX_QPI_INT_ST + description: The status bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SLV_EN_QPI_INT_ST + description: The status bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SLV_CMD7_INT_ST + description: The status bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SLV_CMD8_INT_ST + description: The status bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: SLV_CMD9_INT_ST + description: The status bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SLV_CMDA_INT_ST + description: The status bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: SLV_RD_DMA_DONE_INT_ST + description: The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SLV_WR_DMA_DONE_INT_ST + description: The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SLV_RD_BUF_DONE_INT_ST + description: The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: SLV_WR_BUF_DONE_INT_ST + description: The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TRANS_DONE_INT_ST + description: The status bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: DMA_SEG_TRANS_DONE_INT_ST + description: The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: SEG_MAGIC_ERR_INT_ST + description: The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: SLV_BUF_ADDR_ERR_INT_ST + description: The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: SLV_CMD_ERR_INT_ST + description: The status bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: MST_RX_AFIFO_WFULL_ERR_INT_ST + description: The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: MST_TX_AFIFO_REMPTY_ERR_INT_ST + description: The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: APP2_INT_ST + description: The status bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: APP1_INT_ST + description: The status bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: read-only + - register: + name: DMA_INT_SET + description: SPI interrupt software set register + addressOffset: 68 + size: 32 + fields: + - name: DMA_INFIFO_FULL_ERR_INT_SET + description: The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: DMA_OUTFIFO_EMPTY_ERR_INT_SET + description: The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SLV_EX_QPI_INT_SET + description: The software set bit for SPI slave Ex_QPI interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SLV_EN_QPI_INT_SET + description: The software set bit for SPI slave En_QPI interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SLV_CMD7_INT_SET + description: The software set bit for SPI slave CMD7 interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SLV_CMD8_INT_SET + description: The software set bit for SPI slave CMD8 interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: SLV_CMD9_INT_SET + description: The software set bit for SPI slave CMD9 interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: SLV_CMDA_INT_SET + description: The software set bit for SPI slave CMDA interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: SLV_RD_DMA_DONE_INT_SET + description: The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SLV_WR_DMA_DONE_INT_SET + description: The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SLV_RD_BUF_DONE_INT_SET + description: The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: SLV_WR_BUF_DONE_INT_SET + description: The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TRANS_DONE_INT_SET + description: The software set bit for SPI_TRANS_DONE_INT interrupt. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: DMA_SEG_TRANS_DONE_INT_SET + description: The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: SEG_MAGIC_ERR_INT_SET + description: The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: SLV_BUF_ADDR_ERR_INT_SET + description: The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: SLV_CMD_ERR_INT_SET + description: The software set bit for SPI_SLV_CMD_ERR_INT interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: MST_RX_AFIFO_WFULL_ERR_INT_SET + description: The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: MST_TX_AFIFO_REMPTY_ERR_INT_SET + description: The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: APP2_INT_SET + description: The software set bit for SPI_APP2_INT interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - name: APP1_INT_SET + description: The software set bit for SPI_APP1_INT interrupt. + bitOffset: 20 + bitWidth: 1 + access: write-only + - register: + name: W0 + description: SPI CPU-controlled buffer0 + addressOffset: 152 + size: 32 + fields: + - name: BUF0 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W1 + description: SPI CPU-controlled buffer1 + addressOffset: 156 + size: 32 + fields: + - name: BUF1 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W2 + description: SPI CPU-controlled buffer2 + addressOffset: 160 + size: 32 + fields: + - name: BUF2 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W3 + description: SPI CPU-controlled buffer3 + addressOffset: 164 + size: 32 + fields: + - name: BUF3 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W4 + description: SPI CPU-controlled buffer4 + addressOffset: 168 + size: 32 + fields: + - name: BUF4 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W5 + description: SPI CPU-controlled buffer5 + addressOffset: 172 + size: 32 + fields: + - name: BUF5 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W6 + description: SPI CPU-controlled buffer6 + addressOffset: 176 + size: 32 + fields: + - name: BUF6 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W7 + description: SPI CPU-controlled buffer7 + addressOffset: 180 + size: 32 + fields: + - name: BUF7 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W8 + description: SPI CPU-controlled buffer8 + addressOffset: 184 + size: 32 + fields: + - name: BUF8 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W9 + description: SPI CPU-controlled buffer9 + addressOffset: 188 + size: 32 + fields: + - name: BUF9 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W10 + description: SPI CPU-controlled buffer10 + addressOffset: 192 + size: 32 + fields: + - name: BUF10 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W11 + description: SPI CPU-controlled buffer11 + addressOffset: 196 + size: 32 + fields: + - name: BUF11 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W12 + description: SPI CPU-controlled buffer12 + addressOffset: 200 + size: 32 + fields: + - name: BUF12 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W13 + description: SPI CPU-controlled buffer13 + addressOffset: 204 + size: 32 + fields: + - name: BUF13 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W14 + description: SPI CPU-controlled buffer14 + addressOffset: 208 + size: 32 + fields: + - name: BUF14 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: W15 + description: SPI CPU-controlled buffer15 + addressOffset: 212 + size: 32 + fields: + - name: BUF15 + description: data buffer + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: SLAVE + description: SPI slave control register + addressOffset: 224 + size: 32 + resetValue: 41943040 + fields: + - name: CLK_MODE + description: "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state." + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: CLK_MODE_13 + description: "{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6]." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RSCK_DATA_OUT + description: "It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge" + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SLV_RDDMA_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SLV_WRDMA_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others" + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SLV_RDBUF_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others" + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: SLV_WRBUF_BITLEN_EN + description: "1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others" + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DMA_SEG_MAGIC_VALUE + description: The magic value of BM table in master DMA seg-trans. + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: MODE + description: "Set SPI work mode. 1: slave mode 0: master mode." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SOFT_RESET + description: "Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state." + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: USR_CONF + description: "1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode." + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: SLAVE1 + description: SPI slave control register 1 + addressOffset: 228 + size: 32 + fields: + - name: SLV_DATA_BITLEN + description: The transferred data bit length in SPI slave FD and HD mode. + bitOffset: 0 + bitWidth: 18 + access: read-write + - name: SLV_LAST_COMMAND + description: In the slave mode it is the value of command. + bitOffset: 18 + bitWidth: 8 + access: read-write + - name: SLV_LAST_ADDR + description: In the slave mode it is the value of address. + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: CLK_GATE + description: SPI module clock and register clock control + addressOffset: 232 + size: 32 + fields: + - name: CLK_EN + description: Set this bit to enable clk gate + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: MST_CLK_ACTIVE + description: Set this bit to power on the SPI module clock. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: MST_CLK_SEL + description: "This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control + addressOffset: 240 + size: 32 + resetValue: 34607504 + fields: + - name: DATE + description: SPI register version. + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SPI3 + description: SPI (Serial Peripheral Interface) Controller 3 + baseAddress: 1610764288 + interrupt: + - name: SPI3 + value: 22 + - name: SPI3_DMA + value: 45 + derivedFrom: SPI2 + - name: SYSTEM + description: System Configuration Registers + groupName: SYSTEM + baseAddress: 1611399168 + addressBlock: + - offset: 0 + size: 168 + usage: registers + registers: + - register: + name: CORE_1_CONTROL_0 + description: Core0 control regiter 0 + addressOffset: 0 + size: 32 + resetValue: 4 + fields: + - name: CONTROL_CORE_1_RUNSTALL + description: Set 1 to stall core1 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CONTROL_CORE_1_CLKGATE_EN + description: Set 1 to open core1 clock + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CONTROL_CORE_1_RESETING + description: Set 1 to let core1 reset + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: CORE_1_CONTROL_1 + description: Core0 control regiter 1 + addressOffset: 4 + size: 32 + fields: + - name: CONTROL_CORE_1_MESSAGE + description: "it's only a R/W register, no function, software can write any value" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: CPU_PERI_CLK_EN + description: cpu_peripheral clock configuration register + addressOffset: 8 + size: 32 + fields: + - name: CLK_EN_ASSIST_DEBUG + description: Set 1 to open assist_debug module clock + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CLK_EN_DEDICATED_GPIO + description: Set 1 to open dedicated_gpio module clk + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: CPU_PERI_RST_EN + description: cpu_peripheral reset configuration regsiter + addressOffset: 12 + size: 32 + resetValue: 192 + fields: + - name: RST_EN_ASSIST_DEBUG + description: Set 1 to let assist_debug module reset + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RST_EN_DEDICATED_GPIO + description: Set 1 to let dedicated_gpio module reset + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: CPU_PER_CONF + description: cpu peripheral clock configuration register + addressOffset: 16 + size: 32 + resetValue: 12 + fields: + - name: CPUPERIOD_SEL + description: This field used to sel cpu clock frequent. + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: PLL_FREQ_SEL + description: This field used to sel pll frequent. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CPU_WAIT_MODE_FORCE_ON + description: Set 1 to force cpu_waiti_clk enable. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CPU_WAITI_DELAY_NUM + description: "This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close" + bitOffset: 4 + bitWidth: 4 + access: read-write + - register: + name: MEM_PD_MASK + description: memory power down mask configuration register + addressOffset: 20 + size: 32 + resetValue: 1 + fields: + - name: LSLP_MEM_PD_MASK + description: Set 1 to mask memory power down. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: PERIP_CLK_EN0 + description: peripheral clock configuration regsiter 0 + addressOffset: 24 + size: 32 + resetValue: 4190232687 + fields: + - name: TIMERS_CLK_EN + description: Set 1 to enable TIMERS clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI01_CLK_EN + description: Set 1 to enable SPI01 clock + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UART_CLK_EN + description: Set 1 to enable UART clock + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: WDG_CLK_EN + description: Set 1 to enable WDG clock + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: I2S0_CLK_EN + description: Set 1 to enable I2S0 clock + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: UART1_CLK_EN + description: Set 1 to enable UART1 clock + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI2_CLK_EN + description: Set 1 to enable SPI2 clock + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: I2C_EXT0_CLK_EN + description: Set 1 to enable I2C_EXT0 clock + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: UHCI0_CLK_EN + description: Set 1 to enable UHCI0 clock + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RMT_CLK_EN + description: Set 1 to enable RMT clock + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PCNT_CLK_EN + description: Set 1 to enable PCNT clock + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: LEDC_CLK_EN + description: Set 1 to enable LEDC clock + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: UHCI1_CLK_EN + description: Set 1 to enable UHCI1 clock + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TIMERGROUP_CLK_EN + description: Set 1 to enable TIMERGROUP clock + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: EFUSE_CLK_EN + description: Set 1 to enable EFUSE clock + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TIMERGROUP1_CLK_EN + description: Set 1 to enable TIMERGROUP1 clock + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI3_CLK_EN + description: Set 1 to enable SPI3 clock + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PWM0_CLK_EN + description: Set 1 to enable PWM0 clock + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: I2C_EXT1_CLK_EN + description: Set 1 to enable I2C_EXT1 clock + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TWAI_CLK_EN + description: Set 1 to enable CAN clock + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PWM1_CLK_EN + description: Set 1 to enable PWM1 clock + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: I2S1_CLK_EN + description: Set 1 to enable I2S1 clock + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI2_DMA_CLK_EN + description: Set 1 to enable SPI2_DMA clock + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: USB_CLK_EN + description: Set 1 to enable USB clock + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: UART_MEM_CLK_EN + description: Set 1 to enable UART_MEM clock + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PWM2_CLK_EN + description: Set 1 to enable PWM2 clock + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PWM3_CLK_EN + description: Set 1 to enable PWM3 clock + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI3_DMA_CLK_EN + description: Set 1 to enable SPI4 clock + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: APB_SARADC_CLK_EN + description: Set 1 to enable APB_SARADC clock + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SYSTIMER_CLK_EN + description: Set 1 to enable SYSTEMTIMER clock + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ADC2_ARB_CLK_EN + description: Set 1 to enable ADC2_ARB clock + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI4_CLK_EN + description: Set 1 to enable SPI4 clock + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: PERIP_CLK_EN1 + description: peripheral clock configuration regsiter 1 + addressOffset: 28 + size: 32 + resetValue: 1536 + fields: + - name: PERI_BACKUP_CLK_EN + description: Set 1 to enable BACKUP clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CRYPTO_AES_CLK_EN + description: Set 1 to enable AES clock + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CRYPTO_SHA_CLK_EN + description: Set 1 to enable SHA clock + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CRYPTO_RSA_CLK_EN + description: Set 1 to enable RSA clock + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CRYPTO_DS_CLK_EN + description: Set 1 to enable DS clock + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CRYPTO_HMAC_CLK_EN + description: Set 1 to enable HMAC clock + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DMA_CLK_EN + description: Set 1 to enable DMA clock + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SDIO_HOST_CLK_EN + description: Set 1 to enable SDIO_HOST clock + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: LCD_CAM_CLK_EN + description: Set 1 to enable LCD_CAM clock + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: UART2_CLK_EN + description: Set 1 to enable UART2 clock + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: USB_DEVICE_CLK_EN + description: Set 1 to enable USB_DEVICE clock + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: PERIP_RST_EN0 + description: peripheral reset configuration register0 + addressOffset: 32 + size: 32 + fields: + - name: TIMERS_RST + description: Set 1 to let TIMERS reset + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SPI01_RST + description: Set 1 to let SPI01 reset + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UART_RST + description: Set 1 to let UART reset + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: WDG_RST + description: Set 1 to let WDG reset + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: I2S0_RST + description: Set 1 to let I2S0 reset + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: UART1_RST + description: Set 1 to let UART1 reset + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: SPI2_RST + description: Set 1 to let SPI2 reset + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: I2C_EXT0_RST + description: Set 1 to let I2C_EXT0 reset + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: UHCI0_RST + description: Set 1 to let UHCI0 reset + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RMT_RST + description: Set 1 to let RMT reset + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PCNT_RST + description: Set 1 to let PCNT reset + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: LEDC_RST + description: Set 1 to let LEDC reset + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: UHCI1_RST + description: Set 1 to let UHCI1 reset + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TIMERGROUP_RST + description: Set 1 to let TIMERGROUP reset + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: EFUSE_RST + description: Set 1 to let EFUSE reset + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TIMERGROUP1_RST + description: Set 1 to let TIMERGROUP1 reset + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: SPI3_RST + description: Set 1 to let SPI3 reset + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PWM0_RST + description: Set 1 to let PWM0 reset + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: I2C_EXT1_RST + description: Set 1 to let I2C_EXT1 reset + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: TWAI_RST + description: Set 1 to let CAN reset + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PWM1_RST + description: Set 1 to let PWM1 reset + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: I2S1_RST + description: Set 1 to let I2S1 reset + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: SPI2_DMA_RST + description: Set 1 to let SPI2 reset + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: USB_RST + description: Set 1 to let USB reset + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: UART_MEM_RST + description: Set 1 to let UART_MEM reset + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: PWM2_RST + description: Set 1 to let PWM2 reset + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PWM3_RST + description: Set 1 to let PWM3 reset + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: SPI3_DMA_RST + description: Set 1 to let SPI3 reset + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: APB_SARADC_RST + description: Set 1 to let APB_SARADC reset + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: SYSTIMER_RST + description: Set 1 to let SYSTIMER reset + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: ADC2_ARB_RST + description: Set 1 to let ADC2_ARB reset + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: SPI4_RST + description: Set 1 to let SPI4 reset + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: PERIP_RST_EN1 + description: peripheral reset configuration regsiter 1 + addressOffset: 36 + size: 32 + resetValue: 510 + fields: + - name: PERI_BACKUP_RST + description: Set 1 to let BACKUP reset + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CRYPTO_AES_RST + description: Set 1 to let CRYPTO_AES reset + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CRYPTO_SHA_RST + description: Set 1 to let CRYPTO_SHA reset + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: CRYPTO_RSA_RST + description: Set 1 to let CRYPTO_RSA reset + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: CRYPTO_DS_RST + description: Set 1 to let CRYPTO_DS reset + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CRYPTO_HMAC_RST + description: Set 1 to let CRYPTO_HMAC reset + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: DMA_RST + description: Set 1 to let DMA reset + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SDIO_HOST_RST + description: Set 1 to let SDIO_HOST reset + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: LCD_CAM_RST + description: Set 1 to let LCD_CAM reset + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: UART2_RST + description: Set 1 to let UART2 reset + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: USB_DEVICE_RST + description: Set 1 to let USB_DEVICE reset + bitOffset: 10 + bitWidth: 1 + access: read-write + - register: + name: BT_LPCK_DIV_INT + description: low power clock frequent division factor configuration regsiter + addressOffset: 40 + size: 32 + resetValue: 255 + fields: + - name: BT_LPCK_DIV_NUM + description: This field is lower power clock frequent division factor + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: BT_LPCK_DIV_FRAC + description: low power clock configuration register + addressOffset: 44 + size: 32 + resetValue: 33558529 + fields: + - name: BT_LPCK_DIV_B + description: This field is lower power clock frequent division factor b + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: BT_LPCK_DIV_A + description: This field is lower power clock frequent division factor a + bitOffset: 12 + bitWidth: 12 + access: read-write + - name: LPCLK_SEL_RTC_SLOW + description: Set 1 to select rtc-slow clock as rtc low power clock + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: LPCLK_SEL_8M + description: Set 1 to select 8m clock as rtc low power clock + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: LPCLK_SEL_XTAL + description: Set 1 to select xtal clock as rtc low power clock + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: LPCLK_SEL_XTAL32K + description: Set 1 to select xtal32k clock as low power clock + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: LPCLK_RTC_EN + description: Set 1 to enable RTC low power clock + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_0 + description: interrupt source register 0 + addressOffset: 48 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_0 + description: Set 1 to generate cpu interrupt 0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_1 + description: interrupt source register 1 + addressOffset: 52 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_1 + description: Set 1 to generate cpu interrupt 1 + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_2 + description: interrupt source register 2 + addressOffset: 56 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_2 + description: Set 1 to generate cpu interrupt 2 + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: CPU_INTR_FROM_CPU_3 + description: interrupt source register 3 + addressOffset: 60 + size: 32 + fields: + - name: CPU_INTR_FROM_CPU_3 + description: Set 1 to generate cpu interrupt 3 + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: RSA_PD_CTRL + description: rsa memory power control register + addressOffset: 64 + size: 32 + resetValue: 1 + fields: + - name: RSA_MEM_PD + description: "Set 1 to power down RSA memory. This bit has the lowest priority.When Digital Signature occupies the RSA, this bit is invalid." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RSA_MEM_FORCE_PU + description: "Set 1 to force power up RSA memory, this bit has the second highest priority." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RSA_MEM_FORCE_PD + description: "Set 1 to force power down RSA memory,this bit has the highest priority." + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: EDMA_CTRL + description: EDMA control register + addressOffset: 68 + size: 32 + resetValue: 1 + fields: + - name: EDMA_CLK_ON + description: Set 1 to enable EDMA clock. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EDMA_RESET + description: Set 1 to let EDMA reset + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: CACHE_CONTROL + description: Cache control register + addressOffset: 72 + size: 32 + resetValue: 5 + fields: + - name: ICACHE_CLK_ON + description: Set 1 to enable icache clock + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ICACHE_RESET + description: Set 1 to let icache reset + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DCACHE_CLK_ON + description: Set 1 to enable dcache clock + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DCACHE_RESET + description: Set 1 to let dcache reset + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL + description: External memory encrypt and decrypt control register + addressOffset: 76 + size: 32 + fields: + - name: ENABLE_SPI_MANUAL_ENCRYPT + description: Set 1 to enable the SPI manual encrypt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ENABLE_DOWNLOAD_DB_ENCRYPT + description: Set 1 to enable download DB encrypt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ENABLE_DOWNLOAD_G0CB_DECRYPT + description: Set 1 to enable download G0CB decrypt + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ENABLE_DOWNLOAD_MANUAL_ENCRYPT + description: Set 1 to enable download manual encrypt + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: RTC_FASTMEM_CONFIG + description: RTC fast memory configuration register + addressOffset: 80 + size: 32 + resetValue: 2146435072 + fields: + - name: RTC_MEM_CRC_START + description: Set 1 to start the CRC of RTC memory + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: RTC_MEM_CRC_ADDR + description: This field is used to set address of RTC memory for CRC. + bitOffset: 9 + bitWidth: 11 + access: read-write + - name: RTC_MEM_CRC_LEN + description: This field is used to set length of RTC memory for CRC based on start address. + bitOffset: 20 + bitWidth: 11 + access: read-write + - name: RTC_MEM_CRC_FINISH + description: This bit stores the status of RTC memory CRC.1 means finished. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: RTC_FASTMEM_CRC + description: RTC fast memory CRC control register + addressOffset: 84 + size: 32 + fields: + - name: RTC_MEM_CRC_RES + description: This field stores the CRC result of RTC memory. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: REDUNDANT_ECO_CTRL + description: "******* Description ***********" + addressOffset: 88 + size: 32 + fields: + - name: REDUNDANT_ECO_DRIVE + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: REDUNDANT_ECO_RESULT + description: "******* Description ***********" + bitOffset: 1 + bitWidth: 1 + access: read-only + - register: + name: CLOCK_GATE + description: "******* Description ***********" + addressOffset: 92 + size: 32 + resetValue: 1 + fields: + - name: CLK_EN + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: SYSCLK_CONF + description: System clock configuration register. + addressOffset: 96 + size: 32 + resetValue: 1 + fields: + - name: PRE_DIV_CNT + description: This field is used to set the count of prescaler of XTAL_CLK. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: SOC_CLK_SEL + description: This field is used to select soc clock. + bitOffset: 10 + bitWidth: 2 + access: read-write + - name: CLK_XTAL_FREQ + description: This field is used to read xtal frequency in MHz. + bitOffset: 12 + bitWidth: 7 + access: read-only + - name: CLK_DIV_EN + description: Reserved. + bitOffset: 19 + bitWidth: 1 + access: read-only + - register: + name: MEM_PVT + description: "******* Description ***********" + addressOffset: 100 + size: 32 + resetValue: 3 + fields: + - name: MEM_PATH_LEN + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: MEM_ERR_CNT_CLR + description: "******* Description ***********" + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: MONITOR_EN + description: "******* Description ***********" + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: MEM_TIMING_ERR_CNT + description: "******* Description ***********" + bitOffset: 6 + bitWidth: 16 + access: read-only + - name: MEM_VT_SEL + description: "******* Description ***********" + bitOffset: 22 + bitWidth: 2 + access: read-write + - register: + name: COMB_PVT_LVT_CONF + description: "******* Description ***********" + addressOffset: 104 + size: 32 + resetValue: 3 + fields: + - name: COMB_PATH_LEN_LVT + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: COMB_ERR_CNT_CLR_LVT + description: "******* Description ***********" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: COMB_PVT_MONITOR_EN_LVT + description: "******* Description ***********" + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: COMB_PVT_NVT_CONF + description: "******* Description ***********" + addressOffset: 108 + size: 32 + resetValue: 3 + fields: + - name: COMB_PATH_LEN_NVT + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: COMB_ERR_CNT_CLR_NVT + description: "******* Description ***********" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: COMB_PVT_MONITOR_EN_NVT + description: "******* Description ***********" + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: COMB_PVT_HVT_CONF + description: "******* Description ***********" + addressOffset: 112 + size: 32 + resetValue: 3 + fields: + - name: COMB_PATH_LEN_HVT + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 5 + access: read-write + - name: COMB_ERR_CNT_CLR_HVT + description: "******* Description ***********" + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: COMB_PVT_MONITOR_EN_HVT + description: "******* Description ***********" + bitOffset: 6 + bitWidth: 1 + access: read-write + - register: + name: COMB_PVT_ERR_LVT_SITE0 + description: "******* Description ***********" + addressOffset: 116 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_LVT_SITE0 + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_NVT_SITE0 + description: "******* Description ***********" + addressOffset: 120 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_NVT_SITE0 + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_HVT_SITE0 + description: "******* Description ***********" + addressOffset: 124 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_HVT_SITE0 + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_LVT_SITE1 + description: "******* Description ***********" + addressOffset: 128 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_LVT_SITE1 + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_NVT_SITE1 + description: "******* Description ***********" + addressOffset: 132 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_NVT_SITE1 + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_HVT_SITE1 + description: "******* Description ***********" + addressOffset: 136 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_HVT_SITE1 + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_LVT_SITE2 + description: "******* Description ***********" + addressOffset: 140 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_LVT_SITE2 + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_NVT_SITE2 + description: "******* Description ***********" + addressOffset: 144 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_NVT_SITE2 + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_HVT_SITE2 + description: "******* Description ***********" + addressOffset: 148 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_HVT_SITE2 + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_LVT_SITE3 + description: "******* Description ***********" + addressOffset: 152 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_LVT_SITE3 + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_NVT_SITE3 + description: "******* Description ***********" + addressOffset: 156 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_NVT_SITE3 + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: COMB_PVT_ERR_HVT_SITE3 + description: "******* Description ***********" + addressOffset: 160 + size: 32 + fields: + - name: COMB_TIMING_ERR_CNT_HVT_SITE3 + description: "******* Description ***********" + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: DATE + description: version register + addressOffset: 4092 + size: 32 + resetValue: 34607648 + fields: + - name: DATE + description: version register + bitOffset: 0 + bitWidth: 28 + access: read-write + - name: SYSTIMER + description: System Timer + groupName: SYSTIMER + baseAddress: 1610756096 + addressBlock: + - offset: 0 + size: 144 + usage: registers + interrupt: + - name: SYSTIMER_TARGET0 + value: 57 + - name: SYSTIMER_TARGET1 + value: 58 + - name: SYSTIMER_TARGET2 + value: 59 + registers: + - register: + name: CONF + description: Configure system timer clock + addressOffset: 0 + size: 32 + resetValue: 1174405120 + fields: + - name: SYSTIMER_CLK_FO + description: systimer clock force on + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TARGET2_WORK_EN + description: target2 work enable + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TARGET1_WORK_EN + description: target1 work enable + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TARGET0_WORK_EN + description: target0 work enable + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT1_CORE1_STALL_EN + description: If timer unit1 is stalled when core1 stalled + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT1_CORE0_STALL_EN + description: If timer unit1 is stalled when core0 stalled + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT0_CORE1_STALL_EN + description: If timer unit0 is stalled when core1 stalled + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT0_CORE0_STALL_EN + description: If timer unit0 is stalled when core0 stalled + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT1_WORK_EN + description: timer unit1 work enable + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: TIMER_UNIT0_WORK_EN + description: timer unit0 work enable + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: register file clk gating + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: UNIT0_OP + description: system timer unit0 value update register + addressOffset: 4 + size: 32 + fields: + - name: TIMER_UNIT0_VALUE_VALID + description: timer value is sync and valid + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: TIMER_UNIT0_UPDATE + description: update timer_unit0 + bitOffset: 30 + bitWidth: 1 + access: write-only + - register: + name: UNIT1_OP + description: system timer unit1 value update register + addressOffset: 8 + size: 32 + fields: + - name: TIMER_UNIT1_VALUE_VALID + description: timer value is sync and valid + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: TIMER_UNIT1_UPDATE + description: update timer unit1 + bitOffset: 30 + bitWidth: 1 + access: write-only + - register: + name: UNIT0_LOAD_HI + description: system timer unit0 value high load register + addressOffset: 12 + size: 32 + fields: + - name: TIMER_UNIT0_LOAD_HI + description: timer unit0 load high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: UNIT0_LOAD_LO + description: system timer unit0 value low load register + addressOffset: 16 + size: 32 + fields: + - name: TIMER_UNIT0_LOAD_LO + description: timer unit0 load low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: UNIT1_LOAD_HI + description: system timer unit1 value high load register + addressOffset: 20 + size: 32 + fields: + - name: TIMER_UNIT1_LOAD_HI + description: timer unit1 load high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: UNIT1_LOAD_LO + description: system timer unit1 value low load register + addressOffset: 24 + size: 32 + fields: + - name: TIMER_UNIT1_LOAD_LO + description: timer unit1 load low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET0_HI + description: system timer comp0 value high register + addressOffset: 28 + size: 32 + fields: + - name: TIMER_TARGET0_HI + description: timer taget0 high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: TARGET0_LO + description: system timer comp0 value low register + addressOffset: 32 + size: 32 + fields: + - name: TIMER_TARGET0_LO + description: timer taget0 low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET1_HI + description: system timer comp1 value high register + addressOffset: 36 + size: 32 + fields: + - name: TIMER_TARGET1_HI + description: timer taget1 high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: TARGET1_LO + description: system timer comp1 value low register + addressOffset: 40 + size: 32 + fields: + - name: TIMER_TARGET1_LO + description: timer taget1 low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET2_HI + description: system timer comp2 value high register + addressOffset: 44 + size: 32 + fields: + - name: TIMER_TARGET2_HI + description: timer taget2 high 20 bits + bitOffset: 0 + bitWidth: 20 + access: read-write + - register: + name: TARGET2_LO + description: system timer comp2 value low register + addressOffset: 48 + size: 32 + fields: + - name: TIMER_TARGET2_LO + description: timer taget2 low 32 bits + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: TARGET0_CONF + description: system timer comp0 target mode register + addressOffset: 52 + size: 32 + fields: + - name: TARGET0_PERIOD + description: target0 period + bitOffset: 0 + bitWidth: 26 + access: read-write + - name: TARGET0_PERIOD_MODE + description: Set target0 to period mode + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TARGET0_TIMER_UNIT_SEL + description: select which unit to compare + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TARGET1_CONF + description: system timer comp1 target mode register + addressOffset: 56 + size: 32 + fields: + - name: TARGET1_PERIOD + description: target1 period + bitOffset: 0 + bitWidth: 26 + access: read-write + - name: TARGET1_PERIOD_MODE + description: Set target1 to period mode + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TARGET1_TIMER_UNIT_SEL + description: select which unit to compare + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TARGET2_CONF + description: system timer comp2 target mode register + addressOffset: 60 + size: 32 + fields: + - name: TARGET2_PERIOD + description: target2 period + bitOffset: 0 + bitWidth: 26 + access: read-write + - name: TARGET2_PERIOD_MODE + description: Set target2 to period mode + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: TARGET2_TIMER_UNIT_SEL + description: select which unit to compare + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: UNIT0_VALUE_HI + description: system timer unit0 value high register + addressOffset: 64 + size: 32 + fields: + - name: TIMER_UNIT0_VALUE_HI + description: timer read value high 20bits + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: UNIT0_VALUE_LO + description: system timer unit0 value low register + addressOffset: 68 + size: 32 + fields: + - name: TIMER_UNIT0_VALUE_LO + description: timer read value low 32bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: UNIT1_VALUE_HI + description: system timer unit1 value high register + addressOffset: 72 + size: 32 + fields: + - name: TIMER_UNIT1_VALUE_HI + description: timer read value high 20bits + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: UNIT1_VALUE_LO + description: system timer unit1 value low register + addressOffset: 76 + size: 32 + fields: + - name: TIMER_UNIT1_VALUE_LO + description: timer read value low 32bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: COMP0_LOAD + description: system timer comp0 conf sync register + addressOffset: 80 + size: 32 + fields: + - name: TIMER_COMP0_LOAD + description: timer comp0 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: COMP1_LOAD + description: system timer comp1 conf sync register + addressOffset: 84 + size: 32 + fields: + - name: TIMER_COMP1_LOAD + description: timer comp1 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: COMP2_LOAD + description: system timer comp2 conf sync register + addressOffset: 88 + size: 32 + fields: + - name: TIMER_COMP2_LOAD + description: timer comp2 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: UNIT0_LOAD + description: system timer unit0 conf sync register + addressOffset: 92 + size: 32 + fields: + - name: TIMER_UNIT0_LOAD + description: timer unit0 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: UNIT1_LOAD + description: system timer unit1 conf sync register + addressOffset: 96 + size: 32 + fields: + - name: TIMER_UNIT1_LOAD + description: timer unit1 sync enable signal + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: INT_ENA + description: systimer interrupt enable register + addressOffset: 100 + size: 32 + fields: + - name: TARGET0_INT_ENA + description: interupt0 enable + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TARGET1_INT_ENA + description: interupt1 enable + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TARGET2_INT_ENA + description: interupt2 enable + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: systimer interrupt raw register + addressOffset: 104 + size: 32 + fields: + - name: TARGET0_INT_RAW + description: interupt0 raw + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TARGET1_INT_RAW + description: interupt1 raw + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TARGET2_INT_RAW + description: interupt2 raw + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: systimer interrupt clear register + addressOffset: 108 + size: 32 + fields: + - name: TARGET0_INT_CLR + description: interupt0 clear + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TARGET1_INT_CLR + description: interupt1 clear + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: TARGET2_INT_CLR + description: interupt2 clear + bitOffset: 2 + bitWidth: 1 + access: write-only + - register: + name: INT_ST + description: systimer interrupt status register + addressOffset: 112 + size: 32 + fields: + - name: TARGET0_INT_ST + description: interupt0 status + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TARGET1_INT_ST + description: interupt1 status + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TARGET2_INT_ST + description: interupt2 status + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: REAL_TARGET0_LO + description: system timer comp0 actual target value low register + addressOffset: 116 + size: 32 + fields: + - name: TARGET0_LO_RO + description: actual target value value low 32bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: REAL_TARGET0_HI + description: system timer comp0 actual target value high register + addressOffset: 120 + size: 32 + fields: + - name: TARGET0_HI_RO + description: actual target value value high 20bits + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: REAL_TARGET1_LO + description: system timer comp1 actual target value low register + addressOffset: 124 + size: 32 + fields: + - name: TARGET1_LO_RO + description: actual target value value low 32bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: REAL_TARGET1_HI + description: system timer comp1 actual target value high register + addressOffset: 128 + size: 32 + fields: + - name: TARGET1_HI_RO + description: actual target value value high 20bits + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: REAL_TARGET2_LO + description: system timer comp2 actual target value low register + addressOffset: 132 + size: 32 + fields: + - name: TARGET2_LO_RO + description: actual target value value low 32bits + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: REAL_TARGET2_HI + description: system timer comp2 actual target value high register + addressOffset: 136 + size: 32 + fields: + - name: TARGET2_HI_RO + description: actual target value value high 20bits + bitOffset: 0 + bitWidth: 20 + access: read-only + - register: + name: DATE + description: system timer version control register + addressOffset: 252 + size: 32 + resetValue: 33628753 + fields: + - name: DATE + description: systimer register version + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: TIMG0 + description: Timer Group 0 + groupName: TIMG + baseAddress: 1610739712 + addressBlock: + - offset: 0 + size: 140 + usage: registers + interrupt: + - name: TG0_T0_LEVEL + value: 50 + - name: TG0_T1_LEVEL + value: 51 + - name: TG0_WDT_LEVEL + value: 52 + registers: + - register: + dim: 2 + dimIncrement: 36 + name: T%sCONFIG + description: Timer %s configuration register + addressOffset: 0 + size: 32 + resetValue: 1610620928 + fields: + - name: USE_XTAL + description: "1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: ALARM_EN + description: "When set, the alarm is enabled. This bit is automatically cleared once an\nalarm occurs." + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DIVIDER + description: Timer %s clock (T%s_clk) prescaler value. + bitOffset: 13 + bitWidth: 16 + access: read-write + - name: AUTORELOAD + description: "When set, timer %s auto-reload at alarm is enabled." + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: INCREASE + description: "When set, the timer %s time-base counter will increment every clock tick. When\ncleared, the timer %s time-base counter will decrement." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: EN + description: "When set, the timer %s time-base counter is enabled." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + dim: 2 + dimIncrement: 36 + name: T%sLO + description: "Timer %s current value, low 32 bits" + addressOffset: 4 + size: 32 + fields: + - name: LO + description: "After writing to TIMG_T%sUPDATE_REG, the low 32 bits of the time-base counter\nof timer %s can be read here." + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + dim: 2 + dimIncrement: 36 + name: T%sHI + description: "Timer %s current value, high 22 bits" + addressOffset: 8 + size: 32 + fields: + - name: HI + description: "After writing to TIMG_T%sUPDATE_REG, the high 22 bits of the time-base counter\nof timer %s can be read here." + bitOffset: 0 + bitWidth: 22 + access: read-only + - register: + dim: 2 + dimIncrement: 36 + name: T%sUPDATE + description: Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG + addressOffset: 12 + size: 32 + fields: + - name: UPDATE + description: "After writing 0 or 1 to TIMG_T%sUPDATE_REG, the counter value is latched." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + dim: 2 + dimIncrement: 36 + name: T%sALARMLO + description: "Timer %s alarm value, low 32 bits" + addressOffset: 16 + size: 32 + fields: + - name: ALARM_LO + description: "Timer %s alarm trigger time-base counter value, low 32 bits." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 2 + dimIncrement: 36 + name: T%sALARMHI + description: "Timer %s alarm value, high bits" + addressOffset: 20 + size: 32 + fields: + - name: ALARM_HI + description: "Timer %s alarm trigger time-base counter value, high 22 bits." + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + dim: 2 + dimIncrement: 36 + name: T%sLOADLO + description: "Timer %s reload value, low 32 bits" + addressOffset: 24 + size: 32 + fields: + - name: LOAD_LO + description: "Low 32 bits of the value that a reload will load onto timer %s time-base\nCounter." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + dim: 2 + dimIncrement: 36 + name: T%sLOADHI + description: "Timer %s reload value, high 22 bits" + addressOffset: 28 + size: 32 + fields: + - name: LOAD_HI + description: "High 22 bits of the value that a reload will load onto timer %s time-base\ncounter." + bitOffset: 0 + bitWidth: 22 + access: read-write + - register: + dim: 2 + dimIncrement: 36 + name: T%sLOAD + description: Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG + addressOffset: 32 + size: 32 + fields: + - name: LOAD + description: Write any value to trigger a timer %s time-base counter reload. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: WDTCONFIG0 + description: Watchdog timer configuration register + addressOffset: 72 + size: 32 + resetValue: 311296 + fields: + - name: WDT_APPCPU_RESET_EN + description: Reserved + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: WDT_PROCPU_RESET_EN + description: WDT reset CPU enable. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: WDT_FLASHBOOT_MOD_EN + description: "When set, Flash boot protection is enabled." + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: WDT_SYS_RESET_LENGTH + description: "System reset signal length selection. 0: 100 ns, 1: 200 ns,\n2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us." + bitOffset: 15 + bitWidth: 3 + access: read-write + - name: WDT_CPU_RESET_LENGTH + description: "CPU reset signal length selection. 0: 100 ns, 1: 200 ns,\n2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us." + bitOffset: 18 + bitWidth: 3 + access: read-write + - name: WDT_STG3 + description: "Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system." + bitOffset: 23 + bitWidth: 2 + access: read-write + - name: WDT_STG2 + description: "Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system." + bitOffset: 25 + bitWidth: 2 + access: read-write + - name: WDT_STG1 + description: "Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system." + bitOffset: 27 + bitWidth: 2 + access: read-write + - name: WDT_STG0 + description: "Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system." + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: WDT_EN + description: "When set, MWDT is enabled." + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: WDTCONFIG1 + description: Watchdog timer prescaler register + addressOffset: 76 + size: 32 + resetValue: 65536 + fields: + - name: WDT_CLK_PRESCALE + description: "MWDT clock prescaler value. MWDT clock period = 12.5 ns *\nTIMG_WDT_CLK_PRESCALE." + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: WDTCONFIG2 + description: Watchdog timer stage 0 timeout value + addressOffset: 80 + size: 32 + resetValue: 26000000 + fields: + - name: WDT_STG0_HOLD + description: "Stage 0 timeout value, in MWDT clock cycles." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG3 + description: Watchdog timer stage 1 timeout value + addressOffset: 84 + size: 32 + resetValue: 134217727 + fields: + - name: WDT_STG1_HOLD + description: "Stage 1 timeout value, in MWDT clock cycles." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG4 + description: Watchdog timer stage 2 timeout value + addressOffset: 88 + size: 32 + resetValue: 1048575 + fields: + - name: WDT_STG2_HOLD + description: "Stage 2 timeout value, in MWDT clock cycles." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTCONFIG5 + description: Watchdog timer stage 3 timeout value + addressOffset: 92 + size: 32 + resetValue: 1048575 + fields: + - name: WDT_STG3_HOLD + description: "Stage 3 timeout value, in MWDT clock cycles." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: WDTFEED + description: Write to feed the watchdog timer + addressOffset: 96 + size: 32 + fields: + - name: WDT_FEED + description: Write any value to feed the MWDT. (WO) + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: WDTWPROTECT + description: Watchdog write protect register + addressOffset: 100 + size: 32 + resetValue: 1356348065 + fields: + - name: WDT_WKEY + description: "If the register contains a different value than its reset value, write\nprotection is enabled." + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: RTCCALICFG + description: RTC calibration configure register + addressOffset: 104 + size: 32 + resetValue: 77824 + fields: + - name: RTC_CALI_START_CYCLING + description: Reserved + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: RTC_CALI_CLK_SEL + description: "0:rtc slow clock. 1:clk_80m. 2:xtal_32k." + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: RTC_CALI_RDY + description: Reserved + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: RTC_CALI_MAX + description: Reserved + bitOffset: 16 + bitWidth: 15 + access: read-write + - name: RTC_CALI_START + description: Reserved + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: RTCCALICFG1 + description: RTC calibration configure1 register + addressOffset: 108 + size: 32 + fields: + - name: RTC_CALI_CYCLING_DATA_VLD + description: Reserved + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RTC_CALI_VALUE + description: Reserved + bitOffset: 7 + bitWidth: 25 + access: read-only + - register: + name: INT_ENA_TIMERS + description: Interrupt enable bits + addressOffset: 112 + size: 32 + fields: + - name: T0_INT_ENA + description: The interrupt enable bit for the TIMG_T0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: T1_INT_ENA + description: The interrupt enable bit for the TIMG_T1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: WDT_INT_ENA + description: The interrupt enable bit for the TIMG_WDT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW_TIMERS + description: Raw interrupt status + addressOffset: 116 + size: 32 + fields: + - name: T0_INT_RAW + description: The raw interrupt status bit for the TIMG_T0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: T1_INT_RAW + description: The raw interrupt status bit for the TIMG_T1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: WDT_INT_RAW + description: The raw interrupt status bit for the TIMG_WDT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - register: + name: INT_ST_TIMERS + description: Masked interrupt status + addressOffset: 120 + size: 32 + fields: + - name: T0_INT_ST + description: The masked interrupt status bit for the TIMG_T0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: T1_INT_ST + description: The masked interrupt status bit for the TIMG_T1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: WDT_INT_ST + description: The masked interrupt status bit for the TIMG_WDT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: INT_CLR_TIMERS + description: Interrupt clear bits + addressOffset: 124 + size: 32 + fields: + - name: T0_INT_CLR + description: Set this bit to clear the TIMG_T0_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: T1_INT_CLR + description: Set this bit to clear the TIMG_T1_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: WDT_INT_CLR + description: Set this bit to clear the TIMG_WDT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - register: + name: RTCCALICFG2 + description: Timer group calibration register + addressOffset: 128 + size: 32 + resetValue: 4294967192 + fields: + - name: RTC_CALI_TIMEOUT + description: RTC calibration timeout indicator + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: RTC_CALI_TIMEOUT_RST_CNT + description: Cycles that release calibration timeout reset + bitOffset: 3 + bitWidth: 4 + access: read-write + - name: RTC_CALI_TIMEOUT_THRES + description: "Threshold value for the RTC calibration timer. If the calibration timer's value exceeds this threshold, a timeout is triggered." + bitOffset: 7 + bitWidth: 25 + access: read-write + - register: + name: NTIMERS_DATE + description: Timer version control register + addressOffset: 248 + size: 32 + resetValue: 33566833 + fields: + - name: NTIMERS_DATE + description: Timer version control register + bitOffset: 0 + bitWidth: 28 + access: read-write + - register: + name: REGCLK + description: Timer group clock gate register + addressOffset: 252 + size: 32 + fields: + - name: CLK_EN + description: "Register clock gate signal. 1: The clock for software to read and write registers is always on. 0: The clock for software to read and write registers only exits when the operation happens." + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: TIMG1 + description: Timer Group 1 + baseAddress: 1610743808 + interrupt: + - name: TG1_T0_LEVEL + value: 53 + - name: TG1_T1_LEVEL + value: 54 + - name: TG1_WDT_LEVEL + value: 55 + derivedFrom: TIMG0 + - name: TWAI0 + description: Two-Wire Automotive Interface + groupName: TWAI + baseAddress: 1610788864 + addressBlock: + - offset: 0 + size: 108 + usage: registers + interrupt: + - name: TWAI0 + value: 37 + registers: + - register: + name: MODE + description: Mode Register + addressOffset: 0 + size: 32 + resetValue: 1 + fields: + - name: RESET_MODE + description: "This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: LISTEN_ONLY_MODE + description: "1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SELF_TEST_MODE + description: "1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RX_FILTER_MODE + description: "This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode." + bitOffset: 3 + bitWidth: 1 + access: read-write + - register: + name: CMD + description: Command Register + addressOffset: 4 + size: 32 + fields: + - name: TX_REQ + description: Set the bit to 1 to allow the driving nodes start transmission. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: ABORT_TX + description: Set the bit to 1 to cancel a pending transmission request. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RELEASE_BUF + description: Set the bit to 1 to release the RX buffer. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: CLR_OVERRUN + description: Set the bit to 1 to clear the data overrun status bit. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SELF_RX_REQ + description: Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously. + bitOffset: 4 + bitWidth: 1 + access: write-only + - register: + name: STATUS + description: Status register + addressOffset: 8 + size: 32 + fields: + - name: RX_BUF_ST + description: "1: The data in the RX buffer is not empty, with at least one received data packet." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: OVERRUN_ST + description: "1: The RX FIFO is full and data overrun has occurred." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: TX_BUF_ST + description: "1: The TX buffer is empty, the CPU may write a message into it." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_COMPLETE + description: "1: The TWAI controller has successfully received a packet from the bus." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: RX_ST + description: "1: The TWAI Controller is receiving a message from the bus." + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TX_ST + description: "1: The TWAI Controller is transmitting a message to the bus." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ERR_ST + description: "1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG." + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BUS_OFF_ST + description: "1: In bus-off status, the TWAI Controller is no longer involved in bus activities." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: MISS_ST + description: "This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete" + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INT_RAW + description: Interrupt Register + addressOffset: 12 + size: 32 + fields: + - name: RX_INT_ST + description: "Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO." + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_INT_ST + description: "Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: ERR_WARN_INT_ST + description: "Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0)." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: OVERRUN_INT_ST + description: "Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: ERR_PASSIVE_INT_ST + description: "Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters." + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ARB_LOST_INT_ST + description: "Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated." + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BUS_ERR_INT_ST + description: "Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus." + bitOffset: 7 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt Enable Register + addressOffset: 16 + size: 32 + fields: + - name: RX_INT_ENA + description: Set this bit to 1 to enable receive interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_INT_ENA + description: Set this bit to 1 to enable transmit interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: ERR_WARN_INT_ENA + description: Set this bit to 1 to enable error warning interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: OVERRUN_INT_ENA + description: Set this bit to 1 to enable data overrun interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ERR_PASSIVE_INT_ENA + description: Set this bit to 1 to enable error passive interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: ARB_LOST_INT_ENA + description: Set this bit to 1 to enable arbitration lost interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BUS_ERR_INT_ENA + description: Set this bit to 1 to enable error interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: BUS_TIMING_0 + description: Bus Timing Register 0 + addressOffset: 24 + size: 32 + fields: + - name: BAUD_PRESC + description: "Baud Rate Prescaler, determines the frequency dividing ratio." + bitOffset: 0 + bitWidth: 14 + access: read-write + - name: SYNC_JUMP_WIDTH + description: "Synchronization Jump Width (SJW), 1 \\verb+~+ 14 Tq wide." + bitOffset: 14 + bitWidth: 2 + access: read-write + - register: + name: BUS_TIMING_1 + description: Bus Timing Register 1 + addressOffset: 28 + size: 32 + fields: + - name: TIME_SEG1 + description: The width of PBS1. + bitOffset: 0 + bitWidth: 4 + access: read-write + - name: TIME_SEG2 + description: The width of PBS2. + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: TIME_SAMP + description: "The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times" + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: ARB_LOST_CAP + description: Arbitration Lost Capture Register + addressOffset: 44 + size: 32 + fields: + - name: ARB_LOST_CAP + description: This register contains information about the bit position of lost arbitration. + bitOffset: 0 + bitWidth: 5 + access: read-only + - register: + name: ERR_CODE_CAP + description: Error Code Capture Register + addressOffset: 48 + size: 32 + fields: + - name: ECC_SEGMENT + description: "This register contains information about the location of errors, see Table 181 for details." + bitOffset: 0 + bitWidth: 5 + access: read-only + - name: ECC_DIRECTION + description: "This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: ECC_TYPE + description: "This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error" + bitOffset: 6 + bitWidth: 2 + access: read-only + - register: + name: ERR_WARNING_LIMIT + description: Error Warning Limit Register + addressOffset: 52 + size: 32 + resetValue: 96 + fields: + - name: ERR_WARNING_LIMIT + description: "Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid)." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: RX_ERR_CNT + description: Receive Error Counter Register + addressOffset: 56 + size: 32 + fields: + - name: RX_ERR_CNT + description: "The RX error counter register, reflects value changes under reception status." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: TX_ERR_CNT + description: Transmit Error Counter Register + addressOffset: 60 + size: 32 + fields: + - name: TX_ERR_CNT + description: "The TX error counter register, reflects value changes under transmission status." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_0 + description: Data register 0 + addressOffset: 64 + size: 32 + fields: + - name: TX_BYTE_0 + description: "In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_1 + description: Data register 1 + addressOffset: 68 + size: 32 + fields: + - name: TX_BYTE_1 + description: "In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_2 + description: Data register 2 + addressOffset: 72 + size: 32 + fields: + - name: TX_BYTE_2 + description: "In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_3 + description: Data register 3 + addressOffset: 76 + size: 32 + fields: + - name: TX_BYTE_3 + description: "In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_4 + description: Data register 4 + addressOffset: 80 + size: 32 + fields: + - name: TX_BYTE_4 + description: "In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_5 + description: Data register 5 + addressOffset: 84 + size: 32 + fields: + - name: TX_BYTE_5 + description: "In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_6 + description: Data register 6 + addressOffset: 88 + size: 32 + fields: + - name: TX_BYTE_6 + description: "In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_7 + description: Data register 7 + addressOffset: 92 + size: 32 + fields: + - name: TX_BYTE_7 + description: "In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_8 + description: Data register 8 + addressOffset: 96 + size: 32 + fields: + - name: TX_BYTE_8 + description: Stored the 8th byte information of the data to be transmitted under operating mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_9 + description: Data register 9 + addressOffset: 100 + size: 32 + fields: + - name: TX_BYTE_9 + description: Stored the 9th byte information of the data to be transmitted under operating mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_10 + description: Data register 10 + addressOffset: 104 + size: 32 + fields: + - name: TX_BYTE_10 + description: Stored the 10th byte information of the data to be transmitted under operating mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_11 + description: Data register 11 + addressOffset: 108 + size: 32 + fields: + - name: TX_BYTE_11 + description: Stored the 11th byte information of the data to be transmitted under operating mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: DATA_12 + description: Data register 12 + addressOffset: 112 + size: 32 + fields: + - name: TX_BYTE_12 + description: Stored the 12th byte information of the data to be transmitted under operating mode. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: RX_MESSAGE_CNT + description: Receive Message Counter Register + addressOffset: 116 + size: 32 + fields: + - name: RX_MESSAGE_COUNTER + description: This register reflects the number of messages available within the RX FIFO. + bitOffset: 0 + bitWidth: 7 + access: read-only + - register: + name: CLOCK_DIVIDER + description: Clock Divider register + addressOffset: 124 + size: 32 + fields: + - name: CD + description: These bits are used to configure frequency dividing coefficients of the external CLKOUT pin. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CLOCK_OFF + description: "This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin" + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: UART0 + description: UART (Universal Asynchronous Receiver-Transmitter) Controller 0 + groupName: UART + baseAddress: 1610612736 + addressBlock: + - offset: 0 + size: 132 + usage: registers + interrupt: + - name: UART0 + value: 27 + registers: + - register: + name: FIFO + description: FIFO data register + addressOffset: 0 + size: 32 + fields: + - name: RXFIFO_RD_BYTE + description: UART 0 accesses FIFO via this register. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 4 + size: 32 + resetValue: 2 + fields: + - name: RXFIFO_FULL_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_EMPTY_INT_RAW + description: This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PARITY_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a parity error in the data. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FRM_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a data frame error . + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DSR_CHG_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CTS_CHG_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BRK_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RXFIFO_TOUT_INT_RAW + description: This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SW_XON_INT_RAW + description: This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SW_XOFF_INT_RAW + description: This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GLITCH_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_BRK_DONE_INT_RAW + description: "This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent." + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_BRK_IDLE_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_RAW + description: This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RS485_PARITY_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RS485_FRM_ERR_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RS485_CLASH_INT_RAW + description: This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: AT_CMD_CHAR_DET_INT_RAW + description: This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: WAKEUP_INT_RAW + description: This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 8 + size: 32 + fields: + - name: RXFIFO_FULL_INT_ST + description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TXFIFO_EMPTY_INT_ST + description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: PARITY_ERR_INT_ST + description: This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: FRM_ERR_INT_ST + description: This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: RXFIFO_OVF_INT_ST + description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: DSR_CHG_INT_ST + description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CTS_CHG_INT_ST + description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: BRK_DET_INT_ST + description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: RXFIFO_TOUT_INT_ST + description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: SW_XON_INT_ST + description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: SW_XOFF_INT_ST + description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: GLITCH_DET_INT_ST + description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1. + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: TX_BRK_DONE_INT_ST + description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1. + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: TX_BRK_IDLE_DONE_INT_ST + description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: TX_DONE_INT_ST + description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: RS485_PARITY_ERR_INT_ST + description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: RS485_FRM_ERR_INT_ST + description: This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1. + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: RS485_CLASH_INT_ST + description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1. + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: AT_CMD_CHAR_DET_INT_ST + description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1. + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: WAKEUP_INT_ST + description: This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1. + bitOffset: 19 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 12 + size: 32 + fields: + - name: RXFIFO_FULL_INT_ENA + description: This is the enable bit for rxfifo_full_int_st register. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TXFIFO_EMPTY_INT_ENA + description: This is the enable bit for txfifo_empty_int_st register. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PARITY_ERR_INT_ENA + description: This is the enable bit for parity_err_int_st register. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FRM_ERR_INT_ENA + description: This is the enable bit for frm_err_int_st register. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RXFIFO_OVF_INT_ENA + description: This is the enable bit for rxfifo_ovf_int_st register. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: DSR_CHG_INT_ENA + description: This is the enable bit for dsr_chg_int_st register. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CTS_CHG_INT_ENA + description: This is the enable bit for cts_chg_int_st register. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BRK_DET_INT_ENA + description: This is the enable bit for brk_det_int_st register. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: RXFIFO_TOUT_INT_ENA + description: This is the enable bit for rxfifo_tout_int_st register. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: SW_XON_INT_ENA + description: This is the enable bit for sw_xon_int_st register. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: SW_XOFF_INT_ENA + description: This is the enable bit for sw_xoff_int_st register. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: GLITCH_DET_INT_ENA + description: This is the enable bit for glitch_det_int_st register. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: TX_BRK_DONE_INT_ENA + description: This is the enable bit for tx_brk_done_int_st register. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: TX_BRK_IDLE_DONE_INT_ENA + description: This is the enable bit for tx_brk_idle_done_int_st register. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: TX_DONE_INT_ENA + description: This is the enable bit for tx_done_int_st register. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: RS485_PARITY_ERR_INT_ENA + description: This is the enable bit for rs485_parity_err_int_st register. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: RS485_FRM_ERR_INT_ENA + description: This is the enable bit for rs485_parity_err_int_st register. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RS485_CLASH_INT_ENA + description: This is the enable bit for rs485_clash_int_st register. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: AT_CMD_CHAR_DET_INT_ENA + description: This is the enable bit for at_cmd_char_det_int_st register. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: WAKEUP_INT_ENA + description: This is the enable bit for uart_wakeup_int_st register. + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 16 + size: 32 + fields: + - name: RXFIFO_FULL_INT_CLR + description: Set this bit to clear the rxfifo_full_int_raw interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TXFIFO_EMPTY_INT_CLR + description: Set this bit to clear txfifo_empty_int_raw interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: PARITY_ERR_INT_CLR + description: Set this bit to clear parity_err_int_raw interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: FRM_ERR_INT_CLR + description: Set this bit to clear frm_err_int_raw interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: RXFIFO_OVF_INT_CLR + description: Set this bit to clear rxfifo_ovf_int_raw interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: DSR_CHG_INT_CLR + description: Set this bit to clear the dsr_chg_int_raw interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CTS_CHG_INT_CLR + description: Set this bit to clear the cts_chg_int_raw interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: BRK_DET_INT_CLR + description: Set this bit to clear the brk_det_int_raw interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: RXFIFO_TOUT_INT_CLR + description: Set this bit to clear the rxfifo_tout_int_raw interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SW_XON_INT_CLR + description: Set this bit to clear the sw_xon_int_raw interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: SW_XOFF_INT_CLR + description: Set this bit to clear the sw_xoff_int_raw interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: GLITCH_DET_INT_CLR + description: Set this bit to clear the glitch_det_int_raw interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - name: TX_BRK_DONE_INT_CLR + description: Set this bit to clear the tx_brk_done_int_raw interrupt.. + bitOffset: 12 + bitWidth: 1 + access: write-only + - name: TX_BRK_IDLE_DONE_INT_CLR + description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt. + bitOffset: 13 + bitWidth: 1 + access: write-only + - name: TX_DONE_INT_CLR + description: Set this bit to clear the tx_done_int_raw interrupt. + bitOffset: 14 + bitWidth: 1 + access: write-only + - name: RS485_PARITY_ERR_INT_CLR + description: Set this bit to clear the rs485_parity_err_int_raw interrupt. + bitOffset: 15 + bitWidth: 1 + access: write-only + - name: RS485_FRM_ERR_INT_CLR + description: Set this bit to clear the rs485_frm_err_int_raw interrupt. + bitOffset: 16 + bitWidth: 1 + access: write-only + - name: RS485_CLASH_INT_CLR + description: Set this bit to clear the rs485_clash_int_raw interrupt. + bitOffset: 17 + bitWidth: 1 + access: write-only + - name: AT_CMD_CHAR_DET_INT_CLR + description: Set this bit to clear the at_cmd_char_det_int_raw interrupt. + bitOffset: 18 + bitWidth: 1 + access: write-only + - name: WAKEUP_INT_CLR + description: Set this bit to clear the uart_wakeup_int_raw interrupt. + bitOffset: 19 + bitWidth: 1 + access: write-only + - register: + name: CLKDIV + description: Clock divider configuration + addressOffset: 20 + size: 32 + resetValue: 694 + fields: + - name: CLKDIV + description: The integral part of the frequency divider factor. + bitOffset: 0 + bitWidth: 12 + access: read-write + - name: FRAG + description: The decimal part of the frequency divider factor. + bitOffset: 20 + bitWidth: 4 + access: read-write + - register: + name: RX_FILT + description: Rx Filter configuration + addressOffset: 24 + size: 32 + resetValue: 8 + fields: + - name: GLITCH_FILT + description: "when input pulse width is lower than this value, the pulse is ignored." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: GLITCH_FILT_EN + description: Set this bit to enable Rx signal filter. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: STATUS + description: UART status register + addressOffset: 28 + size: 32 + resetValue: 3758145536 + fields: + - name: RXFIFO_CNT + description: Stores the byte number of valid data in Rx-FIFO. + bitOffset: 0 + bitWidth: 10 + access: read-only + - name: DSRN + description: The register represent the level value of the internal uart dsr signal. + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: CTSN + description: This register represent the level value of the internal uart cts signal. + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: RXD + description: This register represent the level value of the internal uart rxd signal. + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: TXFIFO_CNT + description: Stores the byte number of data in Tx-FIFO. + bitOffset: 16 + bitWidth: 10 + access: read-only + - name: DTRN + description: This bit represents the level of the internal uart dtr signal. + bitOffset: 29 + bitWidth: 1 + access: read-only + - name: RTSN + description: This bit represents the level of the internal uart rts signal. + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: TXD + description: This bit represents the level of the internal uart txd signal. + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: CONF0 + description: a + addressOffset: 32 + size: 32 + resetValue: 268435484 + fields: + - name: PARITY + description: This register is used to configure the parity check mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PARITY_EN + description: Set this bit to enable uart parity check. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: BIT_NUM + description: This register is used to set the length of data. + bitOffset: 2 + bitWidth: 2 + access: read-write + - name: STOP_BIT_NUM + description: This register is used to set the length of stop bit. + bitOffset: 4 + bitWidth: 2 + access: read-write + - name: SW_RTS + description: This register is used to configure the software rts signal which is used in software flow control. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: SW_DTR + description: This register is used to configure the software dtr signal which is used in software flow control. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: TXD_BRK + description: Set this bit to enbale transmitter to send NULL when the process of sending data is done. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: IRDA_DPLX + description: Set this bit to enable IrDA loopback mode. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: IRDA_TX_EN + description: This is the start enable bit for IrDA transmitter. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: IRDA_WCTL + description: "1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: IRDA_TX_INV + description: Set this bit to invert the level of IrDA transmitter. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: IRDA_RX_INV + description: Set this bit to invert the level of IrDA receiver. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: LOOPBACK + description: Set this bit to enable uart loopback test mode. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: TX_FLOW_EN + description: Set this bit to enable flow control function for transmitter. + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: IRDA_EN + description: Set this bit to enable IrDA protocol. + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RXFIFO_RST + description: Set this bit to reset the uart receive-FIFO. + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: TXFIFO_RST + description: Set this bit to reset the uart transmit-FIFO. + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: RXD_INV + description: Set this bit to inverse the level value of uart rxd signal. + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: CTS_INV + description: Set this bit to inverse the level value of uart cts signal. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: DSR_INV + description: Set this bit to inverse the level value of uart dsr signal. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: TXD_INV + description: Set this bit to inverse the level value of uart txd signal. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RTS_INV + description: Set this bit to inverse the level value of uart rts signal. + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: DTR_INV + description: Set this bit to inverse the level value of uart dtr signal. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers." + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: ERR_WR_MASK + description: "1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: AUTOBAUD_EN + description: This is the enable bit for detecting baudrate. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: MEM_CLK_EN + description: UART memory clock gate enable signal. + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: CONF1 + description: Configuration register 1 + addressOffset: 36 + size: 32 + resetValue: 98400 + fields: + - name: RXFIFO_FULL_THRHD + description: It will produce rxfifo_full_int interrupt when receiver receives more data than this register value. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: TXFIFO_EMPTY_THRHD + description: It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value. + bitOffset: 10 + bitWidth: 10 + access: read-write + - name: DIS_RX_DAT_OVF + description: Disable UART Rx data overflow detect. + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: RX_TOUT_FLOW_DIS + description: Set this bit to stop accumulating idle_cnt when hardware flow control works. + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: RX_FLOW_EN + description: This is the flow enable bit for UART receiver. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RX_TOUT_EN + description: "This is the enble bit for uart receiver's timeout function." + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: LOWPULSE + description: Autobaud minimum low pulse duration register + addressOffset: 40 + size: 32 + resetValue: 4095 + fields: + - name: MIN_CNT + description: This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process. + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: HIGHPULSE + description: Autobaud minimum high pulse duration register + addressOffset: 44 + size: 32 + resetValue: 4095 + fields: + - name: MIN_CNT + description: This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process. + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: RXD_CNT + description: Autobaud edge change count register + addressOffset: 48 + size: 32 + fields: + - name: RXD_EDGE_CNT + description: This register stores the count of rxd edge change. It is used in baud rate-detect process. + bitOffset: 0 + bitWidth: 10 + access: read-only + - register: + name: FLOW_CONF + description: Software flow-control configuration + addressOffset: 52 + size: 32 + fields: + - name: SW_FLOW_CON_EN + description: Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: XONOFF_DEL + description: Set this bit to remove flow control char from the received data. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FORCE_XON + description: Set this bit to enable the transmitter to go on sending data. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: FORCE_XOFF + description: Set this bit to stop the transmitter from sending data. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SEND_XON + description: Set this bit to send Xon char. It is cleared by hardware automatically. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SEND_XOFF + description: Set this bit to send Xoff char. It is cleared by hardware automatically. + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: SLEEP_CONF + description: Sleep-mode configuration + addressOffset: 56 + size: 32 + resetValue: 240 + fields: + - name: ACTIVE_THRESHOLD + description: The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value. + bitOffset: 0 + bitWidth: 10 + access: read-write + - register: + name: SWFC_CONF0 + description: Software flow-control character configuration + addressOffset: 60 + size: 32 + resetValue: 19680 + fields: + - name: XOFF_THRESHOLD + description: "When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char." + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: XOFF_CHAR + description: This register stores the Xoff flow control char. + bitOffset: 10 + bitWidth: 8 + access: read-write + - register: + name: SWFC_CONF1 + description: Software flow-control character configuration + addressOffset: 64 + size: 32 + resetValue: 17408 + fields: + - name: XON_THRESHOLD + description: "When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char." + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: XON_CHAR + description: This register stores the Xon flow control char. + bitOffset: 10 + bitWidth: 8 + access: read-write + - register: + name: TXBRK_CONF + description: Tx Break character configuration + addressOffset: 68 + size: 32 + resetValue: 10 + fields: + - name: TX_BRK_NUM + description: This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1. + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: IDLE_CONF + description: Frame-end idle configuration + addressOffset: 72 + size: 32 + resetValue: 262400 + fields: + - name: RX_IDLE_THRHD + description: It will produce frame end signal when receiver takes more time to receive one byte data than this register value. + bitOffset: 0 + bitWidth: 10 + access: read-write + - name: TX_IDLE_NUM + description: This register is used to configure the duration time between transfers. + bitOffset: 10 + bitWidth: 10 + access: read-write + - register: + name: RS485_CONF + description: RS485 mode configuration + addressOffset: 76 + size: 32 + fields: + - name: RS485_EN + description: Set this bit to choose the rs485 mode. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DL0_EN + description: Set this bit to delay the stop bit by 1 bit. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DL1_EN + description: Set this bit to delay the stop bit by 1 bit. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RS485TX_RX_EN + description: Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RS485RXBY_TX_EN + description: "1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy." + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RS485_RX_DLY_NUM + description: "This register is used to delay the receiver's internal data signal." + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RS485_TX_DLY_NUM + description: "This register is used to delay the transmitter's internal data signal." + bitOffset: 6 + bitWidth: 4 + access: read-write + - register: + name: AT_CMD_PRECNT + description: Pre-sequence timing configuration + addressOffset: 80 + size: 32 + resetValue: 2305 + fields: + - name: PRE_IDLE_NUM + description: This register is used to configure the idle duration time before the first at_cmd is received by receiver. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_POSTCNT + description: Post-sequence timing configuration + addressOffset: 84 + size: 32 + resetValue: 2305 + fields: + - name: POST_IDLE_NUM + description: This register is used to configure the duration time between the last at_cmd and the next data. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_GAPTOUT + description: Timeout configuration + addressOffset: 88 + size: 32 + resetValue: 11 + fields: + - name: RX_GAP_TOUT + description: This register is used to configure the duration time between the at_cmd chars. + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: AT_CMD_CHAR + description: AT escape sequence detection configuration + addressOffset: 92 + size: 32 + resetValue: 811 + fields: + - name: AT_CMD_CHAR + description: This register is used to configure the content of at_cmd char. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: CHAR_NUM + description: This register is used to configure the num of continuous at_cmd chars received by receiver. + bitOffset: 8 + bitWidth: 8 + access: read-write + - register: + name: MEM_CONF + description: UART threshold and allocation configuration + addressOffset: 96 + size: 32 + resetValue: 1310738 + fields: + - name: RX_SIZE + description: This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes. + bitOffset: 1 + bitWidth: 3 + access: read-write + - name: TX_SIZE + description: This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes. + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: RX_FLOW_THRHD + description: This register is used to configure the maximum amount of data that can be received when hardware flow control works. + bitOffset: 7 + bitWidth: 10 + access: read-write + - name: RX_TOUT_THRHD + description: This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1. + bitOffset: 17 + bitWidth: 10 + access: read-write + - name: MEM_FORCE_PD + description: Set this bit to force power down UART memory. + bitOffset: 27 + bitWidth: 1 + access: read-write + - name: MEM_FORCE_PU + description: Set this bit to force power up UART memory. + bitOffset: 28 + bitWidth: 1 + access: read-write + - register: + name: MEM_TX_STATUS + description: Tx-FIFO write and read offset address. + addressOffset: 100 + size: 32 + fields: + - name: APB_TX_WADDR + description: This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB. + bitOffset: 0 + bitWidth: 10 + access: read-only + - name: TX_RADDR + description: This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl. + bitOffset: 11 + bitWidth: 10 + access: read-only + - register: + name: MEM_RX_STATUS + description: Rx-FIFO write and read offset address. + addressOffset: 104 + size: 32 + resetValue: 1049088 + fields: + - name: APB_RX_RADDR + description: "This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300." + bitOffset: 0 + bitWidth: 10 + access: read-only + - name: RX_WADDR + description: "This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h200. UART1 is 10'h280. UART2 is 10'h300." + bitOffset: 11 + bitWidth: 10 + access: read-only + - register: + name: FSM_STATUS + description: UART transmit and receive status. + addressOffset: 108 + size: 32 + fields: + - name: ST_URX_OUT + description: This is the status register of receiver. + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: ST_UTX_OUT + description: This is the status register of transmitter. + bitOffset: 4 + bitWidth: 4 + access: read-only + - register: + name: POSPULSE + description: Autobaud high pulse register + addressOffset: 112 + size: 32 + resetValue: 4095 + fields: + - name: POSEDGE_MIN_CNT + description: This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process. + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: NEGPULSE + description: Autobaud low pulse register + addressOffset: 116 + size: 32 + resetValue: 4095 + fields: + - name: NEGEDGE_MIN_CNT + description: This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process. + bitOffset: 0 + bitWidth: 12 + access: read-only + - register: + name: CLK_CONF + description: UART core clock configuration + addressOffset: 120 + size: 32 + resetValue: 57675776 + fields: + - name: SCLK_DIV_B + description: The denominator of the frequency divider factor. + bitOffset: 0 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_A + description: The numerator of the frequency divider factor. + bitOffset: 6 + bitWidth: 6 + access: read-write + - name: SCLK_DIV_NUM + description: The integral part of the frequency divider factor. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: SCLK_SEL + description: "UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL." + bitOffset: 20 + bitWidth: 2 + access: read-write + - name: SCLK_EN + description: Set this bit to enable UART Tx/Rx clock. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RST_CORE + description: "Write 1 then write 0 to this bit, reset UART Tx/Rx." + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: TX_SCLK_EN + description: Set this bit to enable UART Tx clock. + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: RX_SCLK_EN + description: Set this bit to enable UART Rx clock. + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: TX_RST_CORE + description: "Write 1 then write 0 to this bit, reset UART Tx." + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: RX_RST_CORE + description: "Write 1 then write 0 to this bit, reset UART Rx." + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: UART Version register + addressOffset: 124 + size: 32 + resetValue: 33587824 + fields: + - name: DATE + description: This is the version register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ID + description: UART ID register + addressOffset: 128 + size: 32 + resetValue: 1073743104 + fields: + - name: ID + description: This register is used to configure the uart_id. + bitOffset: 0 + bitWidth: 30 + access: read-write + - name: HIGH_SPEED + description: "This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers." + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: REG_UPDATE + description: Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done. + bitOffset: 31 + bitWidth: 1 + access: read-write + - name: UART1 + description: UART (Universal Asynchronous Receiver-Transmitter) Controller 1 + baseAddress: 1610678272 + interrupt: + - name: UART1 + value: 28 + derivedFrom: UART0 + - name: UART2 + description: UART (Universal Asynchronous Receiver-Transmitter) Controller 2 + baseAddress: 1610801152 + interrupt: + - name: UART2 + value: 29 + derivedFrom: UART0 + - name: UHCI0 + description: Universal Host Controller Interface 0 + groupName: UHCI + baseAddress: 1610694656 + addressBlock: + - offset: 0 + size: 136 + usage: registers + interrupt: + - name: UHCI0 + value: 14 + registers: + - register: + name: CONF0 + description: UHCI configuration register + addressOffset: 0 + size: 32 + resetValue: 1760 + fields: + - name: TX_RST + description: "Write 1, then write 0 to this bit to reset decode state machine." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: RX_RST + description: "Write 1, then write 0 to this bit to reset encode state machine." + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: UART0_CE + description: Set this bit to link up HCI and UART0. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: UART1_CE + description: Set this bit to link up HCI and UART1. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: UART2_CE + description: Set this bit to link up HCI and UART2. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SEPER_EN + description: Set this bit to separate the data frame using a special char. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: HEAD_EN + description: Set this bit to encode the data packet with a formatting header. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: CRC_REC_EN + description: Set this bit to enable UHCI to receive the 16 bit CRC. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: UART_IDLE_EOF_EN + description: "If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state." + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: LEN_EOF_EN + description: "If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received." + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: ENCODE_CRC_EN + description: Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: "1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers." + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: UART_RX_BRK_EOF_EN + description: "If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART." + bitOffset: 12 + bitWidth: 1 + access: read-write + - register: + name: INT_RAW + description: Raw interrupt status + addressOffset: 4 + size: 32 + fields: + - name: RX_START_INT_RAW + description: This is the interrupt raw bit. Triggered when a separator char has been sent. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_START_INT_RAW + description: This is the interrupt raw bit. Triggered when UHCI detects a separator char. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_HUNG_INT_RAW + description: This is the interrupt raw bit. Triggered when UHCI takes more time to receive data than configure value. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_HUNG_INT_RAW + description: This is the interrupt raw bit. Triggered when UHCI takes more time to read data from RAM than the configured value. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SEND_S_REG_Q_INT_RAW + description: This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using single_send registers. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SEND_A_REG_Q_INT_RAW + description: This is the interrupt raw bit. Triggered when UHCI has sent out a short packet using always_send registers. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUT_EOF_INT_RAW + description: This is the interrupt raw bit. Triggered when there are some errors in EOF in the transmit data. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: APP_CTRL0_INT_RAW + description: This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL0_IN_SET. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: APP_CTRL1_INT_RAW + description: This is the interrupt raw bit. Triggered when set UHCI_APP_CTRL1_IN_SET. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Masked interrupt status + addressOffset: 8 + size: 32 + fields: + - name: RX_START_INT_ST + description: This is the masked interrupt bit for UHCI_RX_START_INT interrupt when UHCI_RX_START_INT_ENA is set to 1. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: TX_START_INT_ST + description: This is the masked interrupt bit for UHCI_TX_START_INT interrupt when UHCI_TX_START_INT_ENA is set to 1. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: RX_HUNG_INT_ST + description: This is the masked interrupt bit for UHCI_RX_HUNG_INT interrupt when UHCI_RX_HUNG_INT_ENA is set to 1. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: TX_HUNG_INT_ST + description: This is the masked interrupt bit for UHCI_TX_HUNG_INT interrupt when UHCI_TX_HUNG_INT_ENA is set to 1. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SEND_S_REG_Q_INT_ST + description: This is the masked interrupt bit for UHCI_SEND_S_REQ_Q_INT interrupt when UHCI_SEND_S_REQ_Q_INT_ENA is set to 1. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: SEND_A_REG_Q_INT_ST + description: This is the masked interrupt bit for UHCI_SEND_A_REQ_Q_INT interrupt when UHCI_SEND_A_REQ_Q_INT_ENA is set to 1. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: OUTLINK_EOF_ERR_INT_ST + description: This is the masked interrupt bit for UHCI_OUTLINK_EOF_ERR_INT interrupt when UHCI_OUTLINK_EOF_ERR_INT_ENA is set to 1. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: APP_CTRL0_INT_ST + description: This is the masked interrupt bit for UHCI_APP_CTRL0_INT interrupt when UHCI_APP_CTRL0_INT_ENA is set to 1. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: APP_CTRL1_INT_ST + description: This is the masked interrupt bit for UHCI_APP_CTRL1_INT interrupt when UHCI_APP_CTRL1_INT_ENA is set to 1. + bitOffset: 8 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 12 + size: 32 + fields: + - name: RX_START_INT_ENA + description: This is the interrupt enable bit for UHCI_RX_START_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_START_INT_ENA + description: This is the interrupt enable bit for UHCI_TX_START_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: RX_HUNG_INT_ENA + description: This is the interrupt enable bit for UHCI_RX_HUNG_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_HUNG_INT_ENA + description: This is the interrupt enable bit for UHCI_TX_HUNG_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: SEND_S_REG_Q_INT_ENA + description: This is the interrupt enable bit for UHCI_SEND_S_REQ_Q_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: SEND_A_REG_Q_INT_ENA + description: This is the interrupt enable bit for UHCI_SEND_A_REQ_Q_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: OUTLINK_EOF_ERR_INT_ENA + description: This is the interrupt enable bit for UHCI_OUTLINK_EOF_ERR_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: APP_CTRL0_INT_ENA + description: This is the interrupt enable bit for UHCI_APP_CTRL0_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: APP_CTRL1_INT_ENA + description: This is the interrupt enable bit for UHCI_APP_CTRL1_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 16 + size: 32 + fields: + - name: RX_START_INT_CLR + description: Set this bit to clear UHCI_RX_START_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: TX_START_INT_CLR + description: Set this bit to clear UHCI_TX_START_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: RX_HUNG_INT_CLR + description: Set this bit to clear UHCI_RX_HUNG_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: TX_HUNG_INT_CLR + description: Set this bit to clear UHCI_TX_HUNG_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: SEND_S_REG_Q_INT_CLR + description: Set this bit to clear UHCI_SEND_S_REQ_Q_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: SEND_A_REG_Q_INT_CLR + description: Set this bit to clear UHCI_SEND_A_REQ_Q_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: OUTLINK_EOF_ERR_INT_CLR + description: Set this bit to clear UHCI_OUTLINK_EOF_ERR_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: APP_CTRL0_INT_CLR + description: Set this bit to clear UHCI_APP_CTRL0_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: APP_CTRL1_INT_CLR + description: Set this bit to clear UHCI_APP_CTRL1_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - register: + name: APP_INT_SET + description: Software interrupt trigger source + addressOffset: 20 + size: 32 + fields: + - name: APP_CTRL0_INT_SET + description: This bit is software interrupt trigger source of UHCI_APP_CTRL0_INT. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: APP_CTRL1_INT_SET + description: This bit is software interrupt trigger source of UHCI_APP_CTRL1_INT. + bitOffset: 1 + bitWidth: 1 + access: write-only + - register: + name: CONF1 + description: UHCI configuration register + addressOffset: 24 + size: 32 + resetValue: 51 + fields: + - name: CHECK_SUM_EN + description: This is the enable bit to check header checksum when UHCI receives a data packet. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CHECK_SEQ_EN + description: This is the enable bit to check sequence number when UHCI receives a data packet. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: CRC_DISABLE + description: Set this bit to support CRC calculation. Data Integrity Check Present bit in UHCI packet frame should be 1. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SAVE_HEAD + description: Set this bit to save the packet header when HCI receives a data packet. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TX_CHECK_SUM_RE + description: Set this bit to encode the data packet with a checksum. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TX_ACK_NUM_RE + description: Set this bit to encode the data packet with an acknowledgment when a reliable packet is to be transmit. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: WAIT_SW_START + description: The uhci-encoder will jump to ST_SW_WAIT status if this register is set to 1. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: SW_START + description: "If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1." + bitOffset: 8 + bitWidth: 1 + access: read-write + - register: + name: STATE0 + description: UHCI receive status + addressOffset: 28 + size: 32 + fields: + - name: RX_ERR_CAUSE + description: "This register indicates the error type when DMA has received a packet with error. 3'b001: Checksum error in HCI packet. 3'b010: Sequence number error in HCI packet. 3'b011: CRC bit error in HCI packet. 3'b100: 0xc0 is found but received HCI packet is not end. 3'b101: 0xc0 is not found when receiving HCI packet is end. 3'b110: CRC check error." + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: DECODE_STATE + description: UHCI decoder status. + bitOffset: 3 + bitWidth: 3 + access: read-only + - register: + name: STATE1 + description: UHCI transmit status + addressOffset: 32 + size: 32 + fields: + - name: ENCODE_STATE + description: UHCI encoder status. + bitOffset: 0 + bitWidth: 3 + access: read-only + - register: + name: ESCAPE_CONF + description: Escape character configuration + addressOffset: 36 + size: 32 + resetValue: 51 + fields: + - name: TX_C0_ESC_EN + description: Set this bit to enable decoding char 0xc0 when DMA receives data. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TX_DB_ESC_EN + description: Set this bit to enable decoding char 0xdb when DMA receives data. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TX_11_ESC_EN + description: Set this bit to enable decoding flow control char 0x11 when DMA receives data. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_13_ESC_EN + description: Set this bit to enable decoding flow control char 0x13 when DMA receives data. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_C0_ESC_EN + description: Set this bit to enable replacing 0xc0 by special char when DMA sends data. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: RX_DB_ESC_EN + description: Set this bit to enable replacing 0xdb by special char when DMA sends data. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: RX_11_ESC_EN + description: Set this bit to enable replacing flow control char 0x11 by special char when DMA sends data. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: RX_13_ESC_EN + description: Set this bit to enable replacing flow control char 0x13 by special char when DMA sends data. + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: HUNG_CONF + description: Timeout configuration + addressOffset: 40 + size: 32 + resetValue: 8456208 + fields: + - name: TXFIFO_TIMEOUT + description: This register stores the timeout value. It will produce the UHCI_TX_HUNG_INT interrupt when DMA takes more time to receive data. + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: TXFIFO_TIMEOUT_SHIFT + description: This register is used to configure the tick count maximum value. + bitOffset: 8 + bitWidth: 3 + access: read-write + - name: TXFIFO_TIMEOUT_ENA + description: This is the enable bit for Tx-FIFO receive-data timeout. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: RXFIFO_TIMEOUT + description: This register stores the timeout value. It will produce the UHCI_RX_HUNG_INT interrupt when DMA takes more time to read data from RAM. + bitOffset: 12 + bitWidth: 8 + access: read-write + - name: RXFIFO_TIMEOUT_SHIFT + description: This register is used to configure the tick count maximum value. + bitOffset: 20 + bitWidth: 3 + access: read-write + - name: RXFIFO_TIMEOUT_ENA + description: This is the enable bit for DMA send-data timeout. + bitOffset: 23 + bitWidth: 1 + access: read-write + - register: + name: ACK_NUM + description: UHCI ACK number configuration + addressOffset: 44 + size: 32 + resetValue: 8 + fields: + - name: ACK_NUM + description: This ACK number used in software flow control. + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: LOAD + description: "Set this bit to 1, the value configured by UHCI_ACK_NUM would be loaded." + bitOffset: 3 + bitWidth: 1 + access: write-only + - register: + name: RX_HEAD + description: UHCI packet header register + addressOffset: 48 + size: 32 + fields: + - name: RX_HEAD + description: This register stores the header of the current received packet. + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: QUICK_SENT + description: UHCI quick send configuration register + addressOffset: 52 + size: 32 + fields: + - name: SINGLE_SEND_NUM + description: This register is used to specify the single_send register. + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: SINGLE_SEND_EN + description: Set this bit to enable single_send mode to send short packet. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ALWAYS_SEND_NUM + description: This register is used to specify the always_send register. + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: ALWAYS_SEND_EN + description: Set this bit to enable always_send mode to send short packet. + bitOffset: 7 + bitWidth: 1 + access: read-write + - register: + name: REG_Q0_WORD0 + description: Q0_WORD0 quick_sent register + addressOffset: 56 + size: 32 + fields: + - name: SEND_Q0_WORD0 + description: This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q0_WORD1 + description: Q0_WORD1 quick_sent register + addressOffset: 60 + size: 32 + fields: + - name: SEND_Q0_WORD1 + description: This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q1_WORD0 + description: Q1_WORD0 quick_sent register + addressOffset: 64 + size: 32 + fields: + - name: SEND_Q1_WORD0 + description: This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q1_WORD1 + description: Q1_WORD1 quick_sent register + addressOffset: 68 + size: 32 + fields: + - name: SEND_Q1_WORD1 + description: This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q2_WORD0 + description: Q2_WORD0 quick_sent register + addressOffset: 72 + size: 32 + fields: + - name: SEND_Q2_WORD0 + description: This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q2_WORD1 + description: Q2_WORD1 quick_sent register + addressOffset: 76 + size: 32 + fields: + - name: SEND_Q2_WORD1 + description: This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q3_WORD0 + description: Q3_WORD0 quick_sent register + addressOffset: 80 + size: 32 + fields: + - name: SEND_Q3_WORD0 + description: This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q3_WORD1 + description: Q3_WORD1 quick_sent register + addressOffset: 84 + size: 32 + fields: + - name: SEND_Q3_WORD1 + description: This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q4_WORD0 + description: Q4_WORD0 quick_sent register + addressOffset: 88 + size: 32 + fields: + - name: SEND_Q4_WORD0 + description: This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q4_WORD1 + description: Q4_WORD1 quick_sent register + addressOffset: 92 + size: 32 + fields: + - name: SEND_Q4_WORD1 + description: This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q5_WORD0 + description: Q5_WORD0 quick_sent register + addressOffset: 96 + size: 32 + fields: + - name: SEND_Q5_WORD0 + description: This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q5_WORD1 + description: Q5_WORD1 quick_sent register + addressOffset: 100 + size: 32 + fields: + - name: SEND_Q5_WORD1 + description: This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q6_WORD0 + description: Q6_WORD0 quick_sent register + addressOffset: 104 + size: 32 + fields: + - name: SEND_Q6_WORD0 + description: This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: REG_Q6_WORD1 + description: Q6_WORD1 quick_sent register + addressOffset: 108 + size: 32 + fields: + - name: SEND_Q6_WORD1 + description: This register is used as a quick_sent register when specified by UHCI_ALWAYS_SEND_NUM or UHCI_SINGLE_SEND_NUM. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: ESC_CONF0 + description: Escape sequence configuration register 0 + addressOffset: 112 + size: 32 + resetValue: 14474176 + fields: + - name: SEPER_CHAR + description: "This register is used to define the separate char that need to be encoded, default is 0xc0." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: SEPER_ESC_CHAR0 + description: "This register is used to define the first char of slip escape sequence when encoding the separate char, default is 0xdb." + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: SEPER_ESC_CHAR1 + description: "This register is used to define the second char of slip escape sequence when encoding the separate char, default is 0xdc." + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: ESC_CONF1 + description: Escape sequence configuration register 1 + addressOffset: 116 + size: 32 + resetValue: 14539739 + fields: + - name: ESC_SEQ0 + description: "This register is used to define a char that need to be encoded, default is 0xdb that used as the first char of slip escape sequence." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: ESC_SEQ0_CHAR0 + description: "This register is used to define the first char of slip escape sequence when encoding the UHCI_ESC_SEQ0, default is 0xdb." + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: ESC_SEQ0_CHAR1 + description: "This register is used to define the second char of slip escape sequence when encoding the UHCI_ESC_SEQ0, default is 0xdd." + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: ESC_CONF2 + description: Escape sequence configuration register 2 + addressOffset: 120 + size: 32 + resetValue: 14605073 + fields: + - name: ESC_SEQ1 + description: "This register is used to define a char that need to be encoded, default is 0x11 that used as flow control char." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: ESC_SEQ1_CHAR0 + description: "This register is used to define the first char of slip escape sequence when encoding the UHCI_ESC_SEQ1, default is 0xdb." + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: ESC_SEQ1_CHAR1 + description: "This register is used to define the second char of slip escape sequence when encoding the UHCI_ESC_SEQ1, default is 0xde." + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: ESC_CONF3 + description: Escape sequence configuration register 3 + addressOffset: 124 + size: 32 + resetValue: 14670611 + fields: + - name: ESC_SEQ2 + description: "This register is used to define a char that need to be decoded, default is 0x13 that used as flow control char." + bitOffset: 0 + bitWidth: 8 + access: read-write + - name: ESC_SEQ2_CHAR0 + description: "This register is used to define the first char of slip escape sequence when encoding the UHCI_ESC_SEQ2, default is 0xdb." + bitOffset: 8 + bitWidth: 8 + access: read-write + - name: ESC_SEQ2_CHAR1 + description: "This register is used to define the second char of slip escape sequence when encoding the UHCI_ESC_SEQ2, default is 0xdf." + bitOffset: 16 + bitWidth: 8 + access: read-write + - register: + name: PKT_THRES + description: Configure register for packet length + addressOffset: 128 + size: 32 + resetValue: 128 + fields: + - name: PKT_THRS + description: This register is used to configure the maximum value of the packet length when UHCI_HEAD_EN is 0. + bitOffset: 0 + bitWidth: 13 + access: read-write + - register: + name: DATE + description: UHCI version control register + addressOffset: 132 + size: 32 + resetValue: 33620112 + fields: + - name: DATE + description: This is the version control register. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: UHCI1 + description: Universal Host Controller Interface 1 + baseAddress: 1610661888 + interrupt: + - name: UHCI1 + value: 15 + derivedFrom: UHCI0 + - name: USB0 + description: USB OTG (On-The-Go) + groupName: USB + baseAddress: 1611137024 + addressBlock: + - offset: 0 + size: 672 + usage: registers + interrupt: + - name: USB + value: 38 + registers: + - register: + name: GOTGCTL + addressOffset: 0 + size: 32 + fields: + - name: SESREQSCS + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SESREQ + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: VBVALIDOVEN + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: VBVALIDOVVAL + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: AVALIDOVEN + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: AVALIDOVVAL + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BVALIDOVEN + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: BVALIDOVVAL + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: HSTNEGSCS + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: HNPREQ + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: HSTSETHNPEN + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DEVHNPEN + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: EHEN + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DBNCEFLTRBYPASS + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: CONIDSTS + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: DBNCTIME + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: ASESVLD + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: BSESVLD + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: OTGVER + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: CURMOD + bitOffset: 21 + bitWidth: 1 + access: read-only + - register: + name: GOTGINT + addressOffset: 4 + size: 32 + fields: + - name: SESENDDET + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SESREQSUCSTSCHNG + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: HSTNEGSUCSTSCHNG + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: HSTNEGDET + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: ADEVTOUTCHG + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: DBNCEDONE + bitOffset: 19 + bitWidth: 1 + access: read-write + - register: + name: GAHBCFG + addressOffset: 8 + size: 32 + fields: + - name: GLBLLNTRMSK + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: HBSTLEN + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: DMAEN + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: NPTXFEMPLVL + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: PTXFEMPLVL + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: REMMEMSUPP + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: NOTIALLDMAWRIT + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: AHBSINGLE + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: INVDESCENDIANESS + bitOffset: 24 + bitWidth: 1 + access: read-write + - register: + name: GUSBCFG + addressOffset: 12 + size: 32 + resetValue: 5184 + fields: + - name: TOUTCAL + bitOffset: 0 + bitWidth: 3 + access: read-write + - name: PHYIF + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: ULPI_UTMI_SEL + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: FSINTF + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: PHYSEL + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: SRPCAP + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: HNPCAP + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: USBTRDTIM + bitOffset: 10 + bitWidth: 4 + access: read-write + - name: TERMSELDLPULSE + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: TXENDDELAY + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: FORCEHSTMODE + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: FORCEDEVMODE + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: CORRUPTTXPKT + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: GRSTCTL + addressOffset: 16 + size: 32 + fields: + - name: CSFTRST + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: PIUFSSFTRST + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: FRMCNTRRST + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RXFFLSH + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: TXFFLSH + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: TXFNUM + bitOffset: 6 + bitWidth: 5 + access: read-write + - name: DMAREQ + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: AHBIDLE + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: GINTSTS + addressOffset: 20 + size: 32 + fields: + - name: CURMOD_INT + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: MODEMIS + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OTGINT + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SOF + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RXFLVI + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: NPTXFEMP + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: GINNAKEFF + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: GOUTNAKEFF + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: ERLYSUSP + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: USBSUSP + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: USBRST + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: ENUMDONE + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: ISOOUTDROP + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: EOPF + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: EPMIS + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: IEPINT + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: OEPINT + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: INCOMPISOIN + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: INCOMPIP + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: FETSUSP + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RESETDET + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: PRTLNT + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: HCHLNT + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: PTXFEMP + bitOffset: 26 + bitWidth: 1 + access: read-only + - name: CONIDSTSCHNG + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DISCONNINT + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SESSREQINT + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: WKUPINT + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: GINTMSK + addressOffset: 24 + size: 32 + fields: + - name: MODEMISMSK + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: OTGINTMSK + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SOFMSK + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RXFLVIMSK + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: NPTXFEMPMSK + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: GINNAKEFFMSK + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: GOUTNACKEFFMSK + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: ERLYSUSPMSK + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: USBSUSPMSK + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: USBRSTMSK + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: ENUMDONEMSK + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: ISOOUTDROPMSK + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: EOPFMSK + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: EPMISMSK + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: IEPINTMSK + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: OEPINTMSK + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: INCOMPISOINMSK + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: INCOMPIPMSK + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: FETSUSPMSK + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: RESETDETMSK + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: PRTLNTMSK + bitOffset: 24 + bitWidth: 1 + access: read-write + - name: HCHINTMSK + bitOffset: 25 + bitWidth: 1 + access: read-write + - name: PTXFEMPMSK + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: CONIDSTSCHNGMSK + bitOffset: 28 + bitWidth: 1 + access: read-write + - name: DISCONNINTMSK + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: SESSREQINTMSK + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: WKUPINTMSK + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: GRXSTSR + addressOffset: 28 + size: 32 + fields: + - name: G_CHNUM + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: G_BCNT + bitOffset: 4 + bitWidth: 11 + access: read-only + - name: G_DPID + bitOffset: 15 + bitWidth: 2 + access: read-only + - name: G_PKTSTS + bitOffset: 17 + bitWidth: 4 + access: read-only + - name: G_FN + bitOffset: 21 + bitWidth: 4 + access: read-only + - register: + name: GRXSTSP + addressOffset: 32 + size: 32 + fields: + - name: CHNUM + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: BCNT + bitOffset: 4 + bitWidth: 11 + access: read-only + - name: DPID + bitOffset: 15 + bitWidth: 2 + access: read-only + - name: PKTSTS + bitOffset: 17 + bitWidth: 4 + access: read-only + - name: FN + bitOffset: 21 + bitWidth: 4 + access: read-only + - register: + name: GRXFSIZ + addressOffset: 36 + size: 32 + resetValue: 256 + fields: + - name: RXFDEP + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: GNPTXFSIZ + addressOffset: 40 + size: 32 + resetValue: 16777472 + fields: + - name: NPTXFSTADDR + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: NPTXFDEP + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: GNPTXSTS + addressOffset: 44 + size: 32 + resetValue: 262400 + fields: + - name: NPTXFSPCAVAIL + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: NPTXQSPCAVAIL + bitOffset: 16 + bitWidth: 4 + access: read-only + - name: NPTXQTOP + bitOffset: 24 + bitWidth: 7 + access: read-only + - register: + name: GSNPSID + addressOffset: 64 + size: 32 + resetValue: 1330921482 + fields: + - name: SYNOPSYSID + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: GHWCFG1 + addressOffset: 68 + size: 32 + fields: + - name: EPDIR + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: GHWCFG2 + addressOffset: 72 + size: 32 + resetValue: 575527216 + fields: + - name: OTGMODE + bitOffset: 0 + bitWidth: 3 + access: read-only + - name: OTGARCH + bitOffset: 3 + bitWidth: 2 + access: read-only + - name: SINGPNT + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: HSPHYTYPE + bitOffset: 6 + bitWidth: 2 + access: read-only + - name: FSPHYTYPE + bitOffset: 8 + bitWidth: 2 + access: read-only + - name: NUMDEVEPS + bitOffset: 10 + bitWidth: 4 + access: read-only + - name: NUMHSTCHNL + bitOffset: 14 + bitWidth: 4 + access: read-only + - name: PERIOSUPPORT + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: DYNFIFOSIZING + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: MULTIPROCINTRPT + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: NPTXQDEPTH + bitOffset: 22 + bitWidth: 2 + access: read-only + - name: PTXQDEPTH + bitOffset: 24 + bitWidth: 2 + access: read-only + - name: TKNQDEPTH + bitOffset: 26 + bitWidth: 5 + access: read-only + - name: OTG_ENABLE_IC_USB + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: GHWCFG3 + addressOffset: 76 + size: 32 + resetValue: 16778421 + fields: + - name: XFERSIZEWIDTH + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: PKTSIZEWIDTH + bitOffset: 4 + bitWidth: 3 + access: read-only + - name: OTGEN + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: I2CINTSEL + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: VNDCTLSUPT + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: OPTFEATURE + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: RSTTYPE + bitOffset: 11 + bitWidth: 1 + access: read-only + - name: ADPSUPPORT + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: HSICMODE + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: BCSUPPORT + bitOffset: 14 + bitWidth: 1 + access: read-only + - name: LPMMODE + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: DFIFODEPTH + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: GHWCFG4 + addressOffset: 80 + size: 32 + resetValue: 3555762224 + fields: + - name: G_NUMDEVPERIOEPS + bitOffset: 0 + bitWidth: 4 + access: read-only + - name: G_PARTIALPWRDN + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: G_AHBFREQ + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: G_HIBERNATION + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: G_EXTENDEDHIBERNATION + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: G_ACGSUPT + bitOffset: 12 + bitWidth: 1 + access: read-only + - name: G_ENHANCEDLPMSUPT + bitOffset: 13 + bitWidth: 1 + access: read-only + - name: G_PHYDATAWIDTH + bitOffset: 14 + bitWidth: 2 + access: read-only + - name: G_NUMCTLEPS + bitOffset: 16 + bitWidth: 4 + access: read-only + - name: G_IDDQFLTR + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: G_VBUSVALIDFLTR + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: G_AVALIDFLTR + bitOffset: 22 + bitWidth: 1 + access: read-only + - name: G_BVALIDFLTR + bitOffset: 23 + bitWidth: 1 + access: read-only + - name: G_SESSENDFLTR + bitOffset: 24 + bitWidth: 1 + access: read-only + - name: G_DEDFIFOMODE + bitOffset: 25 + bitWidth: 1 + access: read-only + - name: G_INEPS + bitOffset: 26 + bitWidth: 4 + access: read-only + - name: G_DESCDMAENABLED + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: G_DESCDMA + bitOffset: 31 + bitWidth: 1 + access: read-only + - register: + name: GDFIFOCFG + addressOffset: 92 + size: 32 + fields: + - name: GDFIFOCFG + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: EPINFOBASEADDR + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: HPTXFSIZ + addressOffset: 256 + size: 32 + resetValue: 268435968 + fields: + - name: PTXFSTADDR + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: PTXFSIZE + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: DIEPTXF1 + addressOffset: 260 + size: 32 + resetValue: 268435968 + fields: + - name: INEP1TXFSTADDR + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: INEP1TXFDEP + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: DIEPTXF2 + addressOffset: 264 + size: 32 + resetValue: 268435968 + fields: + - name: INEP2TXFSTADDR + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: INEP2TXFDEP + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: DIEPTXF3 + addressOffset: 268 + size: 32 + resetValue: 268435968 + fields: + - name: INEP3TXFSTADDR + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: INEP3TXFDEP + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: DIEPTXF4 + addressOffset: 272 + size: 32 + resetValue: 268435968 + fields: + - name: INEP4TXFSTADDR + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: INEP4TXFDEP + bitOffset: 16 + bitWidth: 16 + access: read-write + - register: + name: HCFG + addressOffset: 1024 + size: 32 + fields: + - name: H_FSLSPCLKSEL + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: H_FSLSSUPP + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_ENA32KHZS + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_DESCDMA + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: H_FRLISTEN + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: H_PERSCHEDENA + bitOffset: 26 + bitWidth: 1 + access: read-write + - name: H_MODECHTIMEN + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HFIR + addressOffset: 1028 + size: 32 + resetValue: 6103 + fields: + - name: FRINT + bitOffset: 0 + bitWidth: 16 + access: read-write + - name: HFIRRLDCTRL + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: HFNUM + addressOffset: 1032 + size: 32 + resetValue: 16383 + fields: + - name: FRNUM + bitOffset: 0 + bitWidth: 14 + access: read-only + - name: FRREM + bitOffset: 16 + bitWidth: 16 + access: read-only + - register: + name: HPTXSTS + addressOffset: 1040 + size: 32 + resetValue: 524544 + fields: + - name: PTXFSPCAVAIL + bitOffset: 0 + bitWidth: 16 + access: read-only + - name: PTXQSPCAVAIL + bitOffset: 16 + bitWidth: 5 + access: read-only + - name: PTXQTOP + bitOffset: 24 + bitWidth: 8 + access: read-only + - register: + name: HAINT + addressOffset: 1044 + size: 32 + fields: + - name: HAINT + bitOffset: 0 + bitWidth: 8 + access: read-only + - register: + name: HAINTMSK + addressOffset: 1048 + size: 32 + fields: + - name: HAINTMSK + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: HFLBADDR + addressOffset: 1052 + size: 32 + fields: + - name: HFLBADDR + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HPRT + addressOffset: 1088 + size: 32 + fields: + - name: PRTCONNSTS + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: PRTCONNDET + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PRTENA + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: PRTENCHNG + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PRTOVRCURRACT + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: PRTOVRCURRCHNG + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: PRTRES + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: PRTSUSP + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: PRTRST + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: PRTLNSTS + bitOffset: 10 + bitWidth: 2 + access: read-only + - name: PRTPWR + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PRTTSTCTL + bitOffset: 13 + bitWidth: 4 + access: read-write + - name: PRTSPD + bitOffset: 17 + bitWidth: 2 + access: read-only + - register: + name: HCCHAR0 + addressOffset: 1280 + size: 32 + fields: + - name: H_MPS0 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: H_EPNUM0 + bitOffset: 11 + bitWidth: 4 + access: read-write + - name: H_EPDIR0 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: H_LSPDDEV0 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: H_EPTYPE0 + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: H_EC0 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: H_DEVADDR0 + bitOffset: 22 + bitWidth: 7 + access: read-write + - name: H_ODDFRM0 + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: H_CHDIS0 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: H_CHENA0 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCINT0 + addressOffset: 1288 + size: 32 + fields: + - name: H_XFERCOMPL0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTD0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERR0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALL0 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NACK0 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACK0 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYET0 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERR0 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERR0 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUN0 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERR0 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTR0 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_XCS_XACT_ERR0 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTR0 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCINTMSK0 + addressOffset: 1292 + size: 32 + fields: + - name: H_XFERCOMPLMSK0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTDMSK0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERRMSK0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALLMSK0 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NAKMSK0 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACKMSK0 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYETMSK0 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERRMSK0 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERRMSK0 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUNMSK0 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERRMSK0 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTRMSK0 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTRMSK0 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCTSIZ0 + addressOffset: 1296 + size: 32 + fields: + - name: H_XFERSIZE0 + bitOffset: 0 + bitWidth: 19 + access: read-write + - name: H_PKTCNT0 + bitOffset: 19 + bitWidth: 10 + access: read-write + - name: H_PID0 + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: H_DOPNG0 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCDMA0 + addressOffset: 1300 + size: 32 + fields: + - name: H_DMAADDR0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HCDMAB0 + addressOffset: 1308 + size: 32 + fields: + - name: H_HCDMAB0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HCCHAR1 + addressOffset: 1312 + size: 32 + fields: + - name: H_MPS1 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: H_EPNUM1 + bitOffset: 11 + bitWidth: 4 + access: read-write + - name: H_EPDIR1 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: H_LSPDDEV1 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: H_EPTYPE1 + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: H_EC1 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: H_DEVADDR1 + bitOffset: 22 + bitWidth: 7 + access: read-write + - name: H_ODDFRM1 + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: H_CHDIS1 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: H_CHENA1 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCINT1 + addressOffset: 1320 + size: 32 + fields: + - name: H_XFERCOMPL1 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTD1 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERR1 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALL1 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NACK1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACK1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYET1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERR1 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERR1 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUN1 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERR1 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTR1 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_XCS_XACT_ERR1 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTR1 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCINTMSK1 + addressOffset: 1324 + size: 32 + fields: + - name: H_XFERCOMPLMSK1 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTDMSK1 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERRMSK1 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALLMSK1 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NAKMSK1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACKMSK1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYETMSK1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERRMSK1 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERRMSK1 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUNMSK1 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERRMSK1 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTRMSK1 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTRMSK1 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCTSIZ1 + addressOffset: 1328 + size: 32 + fields: + - name: H_XFERSIZE1 + bitOffset: 0 + bitWidth: 19 + access: read-write + - name: H_PKTCNT1 + bitOffset: 19 + bitWidth: 10 + access: read-write + - name: H_PID1 + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: H_DOPNG1 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCDMA1 + addressOffset: 1332 + size: 32 + fields: + - name: H_DMAADDR1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HCDMAB1 + addressOffset: 1340 + size: 32 + fields: + - name: H_HCDMAB1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HCCHAR2 + addressOffset: 1344 + size: 32 + fields: + - name: H_MPS2 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: H_EPNUM2 + bitOffset: 11 + bitWidth: 4 + access: read-write + - name: H_EPDIR2 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: H_LSPDDEV2 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: H_EPTYPE2 + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: H_EC2 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: H_DEVADDR2 + bitOffset: 22 + bitWidth: 7 + access: read-write + - name: H_ODDFRM2 + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: H_CHDIS2 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: H_CHENA2 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCINT2 + addressOffset: 1352 + size: 32 + fields: + - name: H_XFERCOMPL2 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTD2 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERR2 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALL2 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NACK2 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACK2 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYET2 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERR2 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERR2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUN2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERR2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTR2 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_XCS_XACT_ERR2 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTR2 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCINTMSK2 + addressOffset: 1356 + size: 32 + fields: + - name: H_XFERCOMPLMSK2 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTDMSK2 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERRMSK2 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALLMSK2 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NAKMSK2 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACKMSK2 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYETMSK2 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERRMSK2 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERRMSK2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUNMSK2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERRMSK2 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTRMSK2 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTRMSK2 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCTSIZ2 + addressOffset: 1360 + size: 32 + fields: + - name: H_XFERSIZE2 + bitOffset: 0 + bitWidth: 19 + access: read-write + - name: H_PKTCNT2 + bitOffset: 19 + bitWidth: 10 + access: read-write + - name: H_PID2 + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: H_DOPNG2 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCDMA2 + addressOffset: 1364 + size: 32 + fields: + - name: H_DMAADDR2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HCDMAB2 + addressOffset: 1372 + size: 32 + fields: + - name: H_HCDMAB2 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HCCHAR3 + addressOffset: 1376 + size: 32 + fields: + - name: H_MPS3 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: H_EPNUM3 + bitOffset: 11 + bitWidth: 4 + access: read-write + - name: H_EPDIR3 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: H_LSPDDEV3 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: H_EPTYPE3 + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: H_EC3 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: H_DEVADDR3 + bitOffset: 22 + bitWidth: 7 + access: read-write + - name: H_ODDFRM3 + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: H_CHDIS3 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: H_CHENA3 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCINT3 + addressOffset: 1384 + size: 32 + fields: + - name: H_XFERCOMPL3 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTD3 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERR3 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALL3 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NACK3 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACK3 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYET3 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERR3 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERR3 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUN3 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERR3 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTR3 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_XCS_XACT_ERR3 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTR3 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCINTMSK3 + addressOffset: 1388 + size: 32 + fields: + - name: H_XFERCOMPLMSK3 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTDMSK3 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERRMSK3 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALLMSK3 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NAKMSK3 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACKMSK3 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYETMSK3 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERRMSK3 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERRMSK3 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUNMSK3 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERRMSK3 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTRMSK3 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTRMSK3 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCTSIZ3 + addressOffset: 1392 + size: 32 + fields: + - name: H_XFERSIZE3 + bitOffset: 0 + bitWidth: 19 + access: read-write + - name: H_PKTCNT3 + bitOffset: 19 + bitWidth: 10 + access: read-write + - name: H_PID3 + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: H_DOPNG3 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCDMA3 + addressOffset: 1396 + size: 32 + fields: + - name: H_DMAADDR3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HCDMAB3 + addressOffset: 1404 + size: 32 + fields: + - name: H_HCDMAB3 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HCCHAR4 + addressOffset: 1408 + size: 32 + fields: + - name: H_MPS4 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: H_EPNUM4 + bitOffset: 11 + bitWidth: 4 + access: read-write + - name: H_EPDIR4 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: H_LSPDDEV4 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: H_EPTYPE4 + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: H_EC4 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: H_DEVADDR4 + bitOffset: 22 + bitWidth: 7 + access: read-write + - name: H_ODDFRM4 + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: H_CHDIS4 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: H_CHENA4 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCINT4 + addressOffset: 1416 + size: 32 + fields: + - name: H_XFERCOMPL4 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTD4 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERR4 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALL4 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NACK4 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACK4 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYET4 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERR4 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERR4 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUN4 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERR4 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTR4 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_XCS_XACT_ERR4 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTR4 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCINTMSK4 + addressOffset: 1420 + size: 32 + fields: + - name: H_XFERCOMPLMSK4 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTDMSK4 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERRMSK4 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALLMSK4 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NAKMSK4 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACKMSK4 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYETMSK4 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERRMSK4 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERRMSK4 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUNMSK4 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERRMSK4 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTRMSK4 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTRMSK4 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCTSIZ4 + addressOffset: 1424 + size: 32 + fields: + - name: H_XFERSIZE4 + bitOffset: 0 + bitWidth: 19 + access: read-write + - name: H_PKTCNT4 + bitOffset: 19 + bitWidth: 10 + access: read-write + - name: H_PID4 + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: H_DOPNG4 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCDMA4 + addressOffset: 1428 + size: 32 + fields: + - name: H_DMAADDR4 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HCDMAB4 + addressOffset: 1436 + size: 32 + fields: + - name: H_HCDMAB4 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HCCHAR5 + addressOffset: 1440 + size: 32 + fields: + - name: H_MPS5 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: H_EPNUM5 + bitOffset: 11 + bitWidth: 4 + access: read-write + - name: H_EPDIR5 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: H_LSPDDEV5 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: H_EPTYPE5 + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: H_EC5 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: H_DEVADDR5 + bitOffset: 22 + bitWidth: 7 + access: read-write + - name: H_ODDFRM5 + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: H_CHDIS5 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: H_CHENA5 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCINT5 + addressOffset: 1448 + size: 32 + fields: + - name: H_XFERCOMPL5 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTD5 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERR5 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALL5 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NACK5 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACK5 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYET5 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERR5 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERR5 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUN5 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERR5 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTR5 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_XCS_XACT_ERR5 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTR5 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCINTMSK5 + addressOffset: 1452 + size: 32 + fields: + - name: H_XFERCOMPLMSK5 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTDMSK5 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERRMSK5 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALLMSK5 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NAKMSK5 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACKMSK5 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYETMSK5 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERRMSK5 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERRMSK5 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUNMSK5 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERRMSK5 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTRMSK5 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTRMSK5 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCTSIZ5 + addressOffset: 1456 + size: 32 + fields: + - name: H_XFERSIZE5 + bitOffset: 0 + bitWidth: 19 + access: read-write + - name: H_PKTCNT5 + bitOffset: 19 + bitWidth: 10 + access: read-write + - name: H_PID5 + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: H_DOPNG5 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCDMA5 + addressOffset: 1460 + size: 32 + fields: + - name: H_DMAADDR5 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HCDMAB5 + addressOffset: 1468 + size: 32 + fields: + - name: H_HCDMAB5 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HCCHAR6 + addressOffset: 1472 + size: 32 + fields: + - name: H_MPS6 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: H_EPNUM6 + bitOffset: 11 + bitWidth: 4 + access: read-write + - name: H_EPDIR6 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: H_LSPDDEV6 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: H_EPTYPE6 + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: H_EC6 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: H_DEVADDR6 + bitOffset: 22 + bitWidth: 7 + access: read-write + - name: H_ODDFRM6 + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: H_CHDIS6 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: H_CHENA6 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCINT6 + addressOffset: 1480 + size: 32 + fields: + - name: H_XFERCOMPL6 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTD6 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERR6 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALL6 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NACK6 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACK6 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYET6 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERR6 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERR6 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUN6 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERR6 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTR6 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_XCS_XACT_ERR6 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTR6 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCINTMSK6 + addressOffset: 1484 + size: 32 + fields: + - name: H_XFERCOMPLMSK6 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTDMSK6 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERRMSK6 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALLMSK6 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NAKMSK6 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACKMSK6 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYETMSK6 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERRMSK6 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERRMSK6 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUNMSK6 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERRMSK6 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTRMSK6 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTRMSK6 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCTSIZ6 + addressOffset: 1488 + size: 32 + fields: + - name: H_XFERSIZE6 + bitOffset: 0 + bitWidth: 19 + access: read-write + - name: H_PKTCNT6 + bitOffset: 19 + bitWidth: 10 + access: read-write + - name: H_PID6 + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: H_DOPNG6 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCDMA6 + addressOffset: 1492 + size: 32 + fields: + - name: H_DMAADDR6 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HCDMAB6 + addressOffset: 1500 + size: 32 + fields: + - name: H_HCDMAB6 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: HCCHAR7 + addressOffset: 1504 + size: 32 + fields: + - name: H_MPS7 + bitOffset: 0 + bitWidth: 11 + access: read-write + - name: H_EPNUM7 + bitOffset: 11 + bitWidth: 4 + access: read-write + - name: H_EPDIR7 + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: H_LSPDDEV7 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: H_EPTYPE7 + bitOffset: 18 + bitWidth: 2 + access: read-write + - name: H_EC7 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: H_DEVADDR7 + bitOffset: 22 + bitWidth: 7 + access: read-write + - name: H_ODDFRM7 + bitOffset: 29 + bitWidth: 1 + access: read-write + - name: H_CHDIS7 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: H_CHENA7 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCINT7 + addressOffset: 1512 + size: 32 + fields: + - name: H_XFERCOMPL7 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTD7 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERR7 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALL7 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NACK7 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACK7 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYET7 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERR7 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERR7 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUN7 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERR7 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTR7 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_XCS_XACT_ERR7 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTR7 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCINTMSK7 + addressOffset: 1516 + size: 32 + fields: + - name: H_XFERCOMPLMSK7 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: H_CHHLTDMSK7 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: H_AHBERRMSK7 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: H_STALLMSK7 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: H_NAKMSK7 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: H_ACKMSK7 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: H_NYETMSK7 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: H_XACTERRMSK7 + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: H_BBLERRMSK7 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: H_FRMOVRUNMSK7 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: H_DATATGLERRMSK7 + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: H_BNAINTRMSK7 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: H_DESC_LST_ROLLINTRMSK7 + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: HCTSIZ7 + addressOffset: 1520 + size: 32 + fields: + - name: H_XFERSIZE7 + bitOffset: 0 + bitWidth: 19 + access: read-write + - name: H_PKTCNT7 + bitOffset: 19 + bitWidth: 10 + access: read-write + - name: H_PID7 + bitOffset: 29 + bitWidth: 2 + access: read-write + - name: H_DOPNG7 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: HCDMA7 + addressOffset: 1524 + size: 32 + fields: + - name: H_DMAADDR7 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: HCDMAB7 + addressOffset: 1532 + size: 32 + fields: + - name: H_HCDMAB7 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DCFG + addressOffset: 2048 + size: 32 + resetValue: 135266304 + fields: + - name: NZSTSOUTHSHK + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: ENA32KHZSUSP + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DEVADDR + bitOffset: 4 + bitWidth: 7 + access: read-write + - name: PERFRLINT + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: ENDEVOUTNAK + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: XCVRDLY + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: ERRATICINTMSK + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: EPMISCNT + bitOffset: 18 + bitWidth: 5 + access: read-write + - name: DESCDMA + bitOffset: 23 + bitWidth: 1 + access: read-write + - name: PERSCHINTVL + bitOffset: 24 + bitWidth: 2 + access: read-write + - name: RESVALID + bitOffset: 26 + bitWidth: 6 + access: read-write + - register: + name: DCTL + addressOffset: 2052 + size: 32 + resetValue: 8192 + fields: + - name: RMTWKUPSIG + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SFTDISCON + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: GNPINNAKSTS + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: GOUTNAKSTS + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: TSTCTL + bitOffset: 4 + bitWidth: 3 + access: read-write + - name: SGNPINNAK + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: CGNPINNAK + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: SGOUTNAK + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: CGOUTNAK + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: PWRONPRGDONE + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: GMC + bitOffset: 13 + bitWidth: 2 + access: read-write + - name: IGNRFRMNUM + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: NAKONBBLE + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: ENCOUNTONBNA + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: DEEPSLEEPBESLREJECT + bitOffset: 18 + bitWidth: 1 + access: read-write + - register: + name: DSTS + addressOffset: 2056 + size: 32 + resetValue: 2 + fields: + - name: SUSPSTS + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: ENUMSPD + bitOffset: 1 + bitWidth: 2 + access: read-only + - name: ERRTICERR + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: SOFFN + bitOffset: 8 + bitWidth: 14 + access: read-only + - name: DEVLNSTS + bitOffset: 22 + bitWidth: 2 + access: read-only + - register: + name: DIEPMSK + addressOffset: 2064 + size: 32 + fields: + - name: DI_XFERCOMPLMSK + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: DI_EPDISBLDMSK + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: DI_AHBERMSK + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TIMEOUTMSK + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: INTKNTXFEMPMSK + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: INTKNEPMISMSK + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: INEPNAKEFFMSK + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: TXFIFOUNDRNMSK + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BNAININTRMSK + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DI_NAKMSK + bitOffset: 13 + bitWidth: 1 + access: read-write + - register: + name: DOEPMSK + addressOffset: 2068 + size: 32 + fields: + - name: XFERCOMPLMSK + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EPDISBLDMSK + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AHBERMSK + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SETUPMSK + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTTKNEPDISMSK + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: STSPHSERCVDMSK + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BACK2BACKSETUP + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTPKTERRMSK + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BNAOUTINTRMSK + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: BBLEERRMSK + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: NAKMSK + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: NYETMSK + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DAINT + addressOffset: 2072 + size: 32 + fields: + - name: INEPINT0 + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: INEPINT1 + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: INEPINT2 + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: INEPINT3 + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: INEPINT4 + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: INEPINT5 + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: INEPINT6 + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUTEPINT0 + bitOffset: 16 + bitWidth: 1 + access: read-only + - name: OUTEPINT1 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: OUTEPINT2 + bitOffset: 18 + bitWidth: 1 + access: read-only + - name: OUTEPINT3 + bitOffset: 19 + bitWidth: 1 + access: read-only + - name: OUTEPINT4 + bitOffset: 20 + bitWidth: 1 + access: read-only + - name: OUTEPINT5 + bitOffset: 21 + bitWidth: 1 + access: read-only + - name: OUTEPINT6 + bitOffset: 22 + bitWidth: 1 + access: read-only + - register: + name: DAINTMSK + addressOffset: 2076 + size: 32 + fields: + - name: INEPMSK0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: INEPMSK1 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: INEPMSK2 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: INEPMSK3 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: INEPMSK4 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: INEPMSK5 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: INEPMSK6 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTEPMSK0 + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: OUTEPMSK1 + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: OUTEPMSK2 + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: OUTEPMSK3 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: OUTEPMSK4 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: OUTEPMSK5 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: OUTEPMSK6 + bitOffset: 22 + bitWidth: 1 + access: read-write + - register: + name: DVBUSDIS + addressOffset: 2088 + size: 32 + resetValue: 6103 + fields: + - name: DVBUSDIS + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: DVBUSPULSE + addressOffset: 2092 + size: 32 + resetValue: 1464 + fields: + - name: DVBUSPULSE + bitOffset: 0 + bitWidth: 12 + access: read-write + - register: + name: DTHRCTL + addressOffset: 2096 + size: 32 + resetValue: 134348832 + fields: + - name: NONISOTHREN + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: ISOTHREN + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TXTHRLEN + bitOffset: 2 + bitWidth: 9 + access: read-write + - name: AHBTHRRATIO + bitOffset: 11 + bitWidth: 2 + access: read-write + - name: RXTHREN + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: RXTHRLEN + bitOffset: 17 + bitWidth: 9 + access: read-write + - name: ARBPRKEN + bitOffset: 27 + bitWidth: 1 + access: read-write + - register: + name: DIEPEMPMSK + addressOffset: 2100 + size: 32 + fields: + - name: D_INEPTXFEMPMSK + bitOffset: 0 + bitWidth: 16 + access: read-write + - register: + name: DIEPCTL0 + addressOffset: 2304 + size: 32 + resetValue: 32768 + fields: + - name: D_MPS0 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: D_USBACTEP0 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: D_NAKSTS0 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: D_EPTYPE0 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: D_STALL0 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: D_TXFNUM0 + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: D_CNAK0 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DI_SNAK0 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: D_EPDIS0 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: D_EPENA0 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DIEPINT0 + addressOffset: 2312 + size: 32 + fields: + - name: D_XFERCOMPL0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: D_EPDISBLD0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: D_AHBERR0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: D_TIMEOUT0 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: D_INTKNTXFEMP0 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: D_INTKNEPMIS0 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: D_INEPNAKEFF0 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: D_TXFEMP0 + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: D_TXFIFOUNDRN0 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: D_BNAINTR0 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: D_PKTDRPSTS0 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: D_BBLEERR0 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: D_NAKINTRPT0 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: D_NYETINTRPT0 + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DIEPTSIZ0 + addressOffset: 2320 + size: 32 + fields: + - name: D_XFERSIZE0 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: D_PKTCNT0 + bitOffset: 19 + bitWidth: 2 + access: read-write + - register: + name: DIEPDMA0 + addressOffset: 2324 + size: 32 + fields: + - name: D_DMAADDR0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DTXFSTS0 + addressOffset: 2328 + size: 32 + fields: + - name: D_INEPTXFSPCAVAIL0 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: DIEPDMAB0 + addressOffset: 2332 + size: 32 + fields: + - name: D_DMABUFFERADDR0 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DIEPCTL1 + addressOffset: 2336 + size: 32 + resetValue: 32768 + fields: + - name: D_MPS1 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: D_USBACTEP1 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: D_NAKSTS1 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: D_EPTYPE1 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: D_STALL1 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: D_TXFNUM1 + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: D_CNAK1 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DI_SNAK1 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: DI_SETD0PID1 + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DI_SETD1PID1 + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: D_EPDIS1 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: D_EPENA1 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DIEPINT1 + addressOffset: 2344 + size: 32 + fields: + - name: D_XFERCOMPL1 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: D_EPDISBLD1 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: D_AHBERR1 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: D_TIMEOUT1 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: D_INTKNTXFEMP1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: D_INTKNEPMIS1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: D_INEPNAKEFF1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: D_TXFEMP1 + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: D_TXFIFOUNDRN1 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: D_BNAINTR1 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: D_PKTDRPSTS1 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: D_BBLEERR1 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: D_NAKINTRPT1 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: D_NYETINTRPT1 + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DIEPTSIZ1 + addressOffset: 2352 + size: 32 + fields: + - name: D_XFERSIZE1 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: D_PKTCNT1 + bitOffset: 19 + bitWidth: 2 + access: read-write + - register: + name: DIEPDMA1 + addressOffset: 2356 + size: 32 + fields: + - name: D_DMAADDR1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DTXFSTS1 + addressOffset: 2360 + size: 32 + fields: + - name: D_INEPTXFSPCAVAIL1 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: DIEPDMAB1 + addressOffset: 2364 + size: 32 + fields: + - name: D_DMABUFFERADDR1 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DIEPCTL2 + addressOffset: 2368 + size: 32 + resetValue: 32768 + fields: + - name: D_MPS2 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: D_USBACTEP2 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: D_NAKSTS2 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: D_EPTYPE2 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: D_STALL2 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: D_TXFNUM2 + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: D_CNAK2 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DI_SNAK2 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: DI_SETD0PID2 + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DI_SETD1PID2 + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: D_EPDIS2 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: D_EPENA2 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DIEPINT2 + addressOffset: 2376 + size: 32 + fields: + - name: D_XFERCOMPL2 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: D_EPDISBLD2 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: D_AHBERR2 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: D_TIMEOUT2 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: D_INTKNTXFEMP2 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: D_INTKNEPMIS2 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: D_INEPNAKEFF2 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: D_TXFEMP2 + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: D_TXFIFOUNDRN2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: D_BNAINTR2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: D_PKTDRPSTS2 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: D_BBLEERR2 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: D_NAKINTRPT2 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: D_NYETINTRPT2 + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DIEPTSIZ2 + addressOffset: 2384 + size: 32 + fields: + - name: D_XFERSIZE2 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: D_PKTCNT2 + bitOffset: 19 + bitWidth: 2 + access: read-write + - register: + name: DIEPDMA2 + addressOffset: 2388 + size: 32 + fields: + - name: D_DMAADDR2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DTXFSTS2 + addressOffset: 2392 + size: 32 + fields: + - name: D_INEPTXFSPCAVAIL2 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: DIEPDMAB2 + addressOffset: 2396 + size: 32 + fields: + - name: D_DMABUFFERADDR2 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DIEPCTL3 + addressOffset: 2400 + size: 32 + resetValue: 32768 + fields: + - name: DI_MPS3 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DI_USBACTEP3 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: DI_NAKSTS3 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: DI_EPTYPE3 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: DI_STALL3 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: DI_TXFNUM3 + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: DI_CNAK3 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DI_SNAK3 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: DI_SETD0PID3 + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DI_SETD1PID3 + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: DI_EPDIS3 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DI_EPENA3 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DIEPINT3 + addressOffset: 2408 + size: 32 + fields: + - name: D_XFERCOMPL3 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: D_EPDISBLD3 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: D_AHBERR3 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: D_TIMEOUT3 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: D_INTKNTXFEMP3 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: D_INTKNEPMIS3 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: D_INEPNAKEFF3 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: D_TXFEMP3 + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: D_TXFIFOUNDRN3 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: D_BNAINTR3 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: D_PKTDRPSTS3 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: D_BBLEERR3 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: D_NAKINTRPT3 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: D_NYETINTRPT3 + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DIEPTSIZ3 + addressOffset: 2416 + size: 32 + fields: + - name: D_XFERSIZE3 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: D_PKTCNT3 + bitOffset: 19 + bitWidth: 2 + access: read-write + - register: + name: DIEPDMA3 + addressOffset: 2420 + size: 32 + fields: + - name: D_DMAADDR3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DTXFSTS3 + addressOffset: 2424 + size: 32 + fields: + - name: D_INEPTXFSPCAVAIL3 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: DIEPDMAB3 + addressOffset: 2428 + size: 32 + fields: + - name: D_DMABUFFERADDR3 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DIEPCTL4 + addressOffset: 2432 + size: 32 + resetValue: 32768 + fields: + - name: D_MPS4 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: D_USBACTEP4 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: D_NAKSTS4 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: D_EPTYPE4 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: D_STALL4 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: D_TXFNUM4 + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: D_CNAK4 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DI_SNAK4 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: DI_SETD0PID4 + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DI_SETD1PID4 + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: D_EPDIS4 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: D_EPENA4 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DIEPINT4 + addressOffset: 2440 + size: 32 + fields: + - name: D_XFERCOMPL4 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: D_EPDISBLD4 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: D_AHBERR4 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: D_TIMEOUT4 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: D_INTKNTXFEMP4 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: D_INTKNEPMIS4 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: D_INEPNAKEFF4 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: D_TXFEMP4 + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: D_TXFIFOUNDRN4 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: D_BNAINTR4 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: D_PKTDRPSTS4 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: D_BBLEERR4 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: D_NAKINTRPT4 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: D_NYETINTRPT4 + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DIEPTSIZ4 + addressOffset: 2448 + size: 32 + fields: + - name: D_XFERSIZE4 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: D_PKTCNT4 + bitOffset: 19 + bitWidth: 2 + access: read-write + - register: + name: DIEPDMA4 + addressOffset: 2452 + size: 32 + fields: + - name: D_DMAADDR4 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DTXFSTS4 + addressOffset: 2456 + size: 32 + fields: + - name: D_INEPTXFSPCAVAIL4 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: DIEPDMAB4 + addressOffset: 2460 + size: 32 + fields: + - name: D_DMABUFFERADDR4 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DIEPCTL5 + addressOffset: 2464 + size: 32 + resetValue: 32768 + fields: + - name: DI_MPS5 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: DI_USBACTEP5 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: DI_NAKSTS5 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: DI_EPTYPE5 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: DI_STALL5 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: DI_TXFNUM5 + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: DI_CNAK5 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DI_SNAK5 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: DI_SETD0PID5 + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DI_SETD1PID5 + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: DI_EPDIS5 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: DI_EPENA5 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DIEPINT5 + addressOffset: 2472 + size: 32 + fields: + - name: D_XFERCOMPL5 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: D_EPDISBLD5 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: D_AHBERR5 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: D_TIMEOUT5 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: D_INTKNTXFEMP5 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: D_INTKNEPMIS5 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: D_INEPNAKEFF5 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: D_TXFEMP5 + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: D_TXFIFOUNDRN5 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: D_BNAINTR5 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: D_PKTDRPSTS5 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: D_BBLEERR5 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: D_NAKINTRPT5 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: D_NYETINTRPT5 + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DIEPTSIZ5 + addressOffset: 2480 + size: 32 + fields: + - name: D_XFERSIZE5 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: D_PKTCNT5 + bitOffset: 19 + bitWidth: 2 + access: read-write + - register: + name: DIEPDMA5 + addressOffset: 2484 + size: 32 + fields: + - name: D_DMAADDR5 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DTXFSTS5 + addressOffset: 2488 + size: 32 + fields: + - name: D_INEPTXFSPCAVAIL5 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: DIEPDMAB5 + addressOffset: 2492 + size: 32 + fields: + - name: D_DMABUFFERADDR5 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DIEPCTL6 + addressOffset: 2496 + size: 32 + resetValue: 32768 + fields: + - name: D_MPS6 + bitOffset: 0 + bitWidth: 2 + access: read-write + - name: D_USBACTEP6 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: D_NAKSTS6 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: D_EPTYPE6 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: D_STALL6 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: D_TXFNUM6 + bitOffset: 22 + bitWidth: 4 + access: read-write + - name: D_CNAK6 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DI_SNAK6 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: DI_SETD0PID6 + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DI_SETD1PID6 + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: D_EPDIS6 + bitOffset: 30 + bitWidth: 1 + access: read-write + - name: D_EPENA6 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DIEPINT6 + addressOffset: 2504 + size: 32 + fields: + - name: D_XFERCOMPL6 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: D_EPDISBLD6 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: D_AHBERR6 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: D_TIMEOUT6 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: D_INTKNTXFEMP6 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: D_INTKNEPMIS6 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: D_INEPNAKEFF6 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: D_TXFEMP6 + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: D_TXFIFOUNDRN6 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: D_BNAINTR6 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: D_PKTDRPSTS6 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: D_BBLEERR6 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: D_NAKINTRPT6 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: D_NYETINTRPT6 + bitOffset: 14 + bitWidth: 1 + access: read-write + - register: + name: DIEPTSIZ6 + addressOffset: 2512 + size: 32 + fields: + - name: D_XFERSIZE6 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: D_PKTCNT6 + bitOffset: 19 + bitWidth: 2 + access: read-write + - register: + name: DIEPDMA6 + addressOffset: 2516 + size: 32 + fields: + - name: D_DMAADDR6 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DTXFSTS6 + addressOffset: 2520 + size: 32 + fields: + - name: D_INEPTXFSPCAVAIL6 + bitOffset: 0 + bitWidth: 16 + access: read-only + - register: + name: DIEPDMAB6 + addressOffset: 2524 + size: 32 + fields: + - name: D_DMABUFFERADDR6 + bitOffset: 0 + bitWidth: 32 + access: read-only + - register: + name: DOEPCTL0 + addressOffset: 2816 + size: 32 + resetValue: 32768 + fields: + - name: MPS0 + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: USBACTEP0 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: NAKSTS0 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: EPTYPE0 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: SNP0 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: STALL0 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CNAK0 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DO_SNAK0 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: EPDIS0 + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: EPENA0 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DOEPINT0 + addressOffset: 2824 + size: 32 + fields: + - name: XFERCOMPL0 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EPDISBLD0 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AHBERR0 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SETUP0 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTTKNEPDIS0 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: STSPHSERCVD0 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BACK2BACKSETUP0 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTPKTERR0 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BNAINTR0 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PKTDRPSTS0 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: BBLEERR0 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: NAKINTRPT0 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: NYEPINTRPT0 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: STUPPKTRCVD0 + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: DOEPTSIZ0 + addressOffset: 2832 + size: 32 + fields: + - name: XFERSIZE0 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: PKTCNT0 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SUPCNT0 + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: DOEPDMA0 + addressOffset: 2836 + size: 32 + fields: + - name: DMAADDR0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPDMAB0 + addressOffset: 2844 + size: 32 + fields: + - name: DMABUFFERADDR0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPCTL1 + addressOffset: 2848 + size: 32 + resetValue: 32768 + fields: + - name: MPS1 + bitOffset: 0 + bitWidth: 11 + access: read-only + - name: USBACTEP1 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: NAKSTS1 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: EPTYPE1 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: SNP1 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: STALL1 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CNAK1 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DO_SNAK1 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: DO_SETD0PID1 + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DO_SETD1PID1 + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: EPDIS1 + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: EPENA1 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DOEPINT1 + addressOffset: 2856 + size: 32 + fields: + - name: XFERCOMPL1 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EPDISBLD1 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AHBERR1 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SETUP1 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTTKNEPDIS1 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: STSPHSERCVD1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BACK2BACKSETUP1 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTPKTERR1 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BNAINTR1 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PKTDRPSTS1 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: BBLEERR1 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: NAKINTRPT1 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: NYEPINTRPT1 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: STUPPKTRCVD1 + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: DOEPTSIZ1 + addressOffset: 2864 + size: 32 + fields: + - name: XFERSIZE1 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: PKTCNT1 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SUPCNT1 + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: DOEPDMA1 + addressOffset: 2868 + size: 32 + fields: + - name: DMAADDR1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPDMAB1 + addressOffset: 2876 + size: 32 + fields: + - name: DMABUFFERADDR1 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPCTL2 + addressOffset: 2880 + size: 32 + resetValue: 32768 + fields: + - name: MPS2 + bitOffset: 0 + bitWidth: 11 + access: read-only + - name: USBACTEP2 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: NAKSTS2 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: EPTYPE2 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: SNP2 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: STALL2 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CNAK2 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DO_SNAK2 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: DO_SETD0PID2 + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DO_SETD1PID2 + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: EPDIS2 + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: EPENA2 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DOEPINT2 + addressOffset: 2888 + size: 32 + fields: + - name: XFERCOMPL2 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EPDISBLD2 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AHBERR2 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SETUP2 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTTKNEPDIS2 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: STSPHSERCVD2 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BACK2BACKSETUP2 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTPKTERR2 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BNAINTR2 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PKTDRPSTS2 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: BBLEERR2 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: NAKINTRPT2 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: NYEPINTRPT2 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: STUPPKTRCVD2 + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: DOEPTSIZ2 + addressOffset: 2896 + size: 32 + fields: + - name: XFERSIZE2 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: PKTCNT2 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SUPCNT2 + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: DOEPDMA2 + addressOffset: 2900 + size: 32 + fields: + - name: DMAADDR2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPDMAB2 + addressOffset: 2908 + size: 32 + fields: + - name: DMABUFFERADDR2 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPCTL3 + addressOffset: 2912 + size: 32 + resetValue: 32768 + fields: + - name: MPS3 + bitOffset: 0 + bitWidth: 11 + access: read-only + - name: USBACTEP3 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: NAKSTS3 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: EPTYPE3 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: SNP3 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: STALL3 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CNAK3 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DO_SNAK3 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: DO_SETD0PID3 + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DO_SETD1PID3 + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: EPDIS3 + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: EPENA3 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DOEPINT3 + addressOffset: 2920 + size: 32 + fields: + - name: XFERCOMPL3 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EPDISBLD3 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AHBERR3 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SETUP3 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTTKNEPDIS3 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: STSPHSERCVD3 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BACK2BACKSETUP3 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTPKTERR3 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BNAINTR3 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PKTDRPSTS3 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: BBLEERR3 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: NAKINTRPT3 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: NYEPINTRPT3 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: STUPPKTRCVD3 + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: DOEPTSIZ3 + addressOffset: 2928 + size: 32 + fields: + - name: XFERSIZE3 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: PKTCNT3 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SUPCNT3 + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: DOEPDMA3 + addressOffset: 2932 + size: 32 + fields: + - name: DMAADDR3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPDMAB3 + addressOffset: 2940 + size: 32 + fields: + - name: DMABUFFERADDR3 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPCTL4 + addressOffset: 2944 + size: 32 + resetValue: 32768 + fields: + - name: MPS4 + bitOffset: 0 + bitWidth: 11 + access: read-only + - name: USBACTEP4 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: NAKSTS4 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: EPTYPE4 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: SNP4 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: STALL4 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CNAK4 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DO_SNAK4 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: DO_SETD0PID4 + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DO_SETD1PID4 + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: EPDIS4 + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: EPENA4 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DOEPINT4 + addressOffset: 2952 + size: 32 + fields: + - name: XFERCOMPL4 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EPDISBLD4 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AHBERR4 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SETUP4 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTTKNEPDIS4 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: STSPHSERCVD4 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BACK2BACKSETUP4 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTPKTERR4 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BNAINTR4 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PKTDRPSTS4 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: BBLEERR4 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: NAKINTRPT4 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: NYEPINTRPT4 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: STUPPKTRCVD4 + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: DOEPTSIZ4 + addressOffset: 2960 + size: 32 + fields: + - name: XFERSIZE4 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: PKTCNT4 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SUPCNT4 + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: DOEPDMA4 + addressOffset: 2964 + size: 32 + fields: + - name: DMAADDR4 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPDMAB4 + addressOffset: 2972 + size: 32 + fields: + - name: DMABUFFERADDR4 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPCTL5 + addressOffset: 2976 + size: 32 + resetValue: 32768 + fields: + - name: MPS5 + bitOffset: 0 + bitWidth: 11 + access: read-only + - name: USBACTEP5 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: NAKSTS5 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: EPTYPE5 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: SNP5 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: STALL5 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CNAK5 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DO_SNAK5 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: DO_SETD0PID5 + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DO_SETD1PID5 + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: EPDIS5 + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: EPENA5 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DOEPINT5 + addressOffset: 2984 + size: 32 + fields: + - name: XFERCOMPL5 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EPDISBLD5 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AHBERR5 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SETUP5 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTTKNEPDIS5 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: STSPHSERCVD5 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BACK2BACKSETUP5 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTPKTERR5 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BNAINTR5 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PKTDRPSTS5 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: BBLEERR5 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: NAKINTRPT5 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: NYEPINTRPT5 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: STUPPKTRCVD5 + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: DOEPTSIZ5 + addressOffset: 2992 + size: 32 + fields: + - name: XFERSIZE5 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: PKTCNT5 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SUPCNT5 + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: DOEPDMA5 + addressOffset: 2996 + size: 32 + fields: + - name: DMAADDR5 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPDMAB5 + addressOffset: 3004 + size: 32 + fields: + - name: DMABUFFERADDR5 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPCTL6 + addressOffset: 3008 + size: 32 + resetValue: 32768 + fields: + - name: MPS6 + bitOffset: 0 + bitWidth: 11 + access: read-only + - name: USBACTEP6 + bitOffset: 15 + bitWidth: 1 + access: read-only + - name: NAKSTS6 + bitOffset: 17 + bitWidth: 1 + access: read-only + - name: EPTYPE6 + bitOffset: 18 + bitWidth: 2 + access: read-only + - name: SNP6 + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: STALL6 + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: CNAK6 + bitOffset: 26 + bitWidth: 1 + access: write-only + - name: DO_SNAK6 + bitOffset: 27 + bitWidth: 1 + access: write-only + - name: DO_SETD0PID6 + bitOffset: 28 + bitWidth: 1 + access: write-only + - name: DO_SETD1PID6 + bitOffset: 29 + bitWidth: 1 + access: write-only + - name: EPDIS6 + bitOffset: 30 + bitWidth: 1 + access: read-only + - name: EPENA6 + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: DOEPINT6 + addressOffset: 3016 + size: 32 + fields: + - name: XFERCOMPL6 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EPDISBLD6 + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: AHBERR6 + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SETUP6 + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: OUTTKNEPDIS6 + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: STSPHSERCVD6 + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: BACK2BACKSETUP6 + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: OUTPKTERR6 + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: BNAINTR6 + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: PKTDRPSTS6 + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: BBLEERR6 + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: NAKINTRPT6 + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: NYEPINTRPT6 + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: STUPPKTRCVD6 + bitOffset: 15 + bitWidth: 1 + access: read-write + - register: + name: DOEPTSIZ6 + addressOffset: 3024 + size: 32 + fields: + - name: XFERSIZE6 + bitOffset: 0 + bitWidth: 7 + access: read-write + - name: PKTCNT6 + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: SUPCNT6 + bitOffset: 29 + bitWidth: 2 + access: read-write + - register: + name: DOEPDMA6 + addressOffset: 3028 + size: 32 + fields: + - name: DMAADDR6 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: DOEPDMAB6 + addressOffset: 3036 + size: 32 + fields: + - name: DMABUFFERADDR6 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: PCGCCTL + addressOffset: 3584 + size: 32 + fields: + - name: STOPPCLK + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: GATEHCLK + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PWRCLMP + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: RSTPDWNMODULE + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PHYSLEEP + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: L1SUSPENDED + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: RESETAFTERSUSP + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: USB_DEVICE + description: Full-speed USB Serial/JTAG Controller + groupName: USB_DEVICE + baseAddress: 1610842112 + addressBlock: + - offset: 0 + size: 80 + usage: registers + interrupt: + - name: USB_DEVICE + value: 96 + registers: + - register: + name: EP1 + description: Endpoint 1 FIFO register + addressOffset: 0 + size: 32 + fields: + - name: RDWR_BYTE + description: "Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO." + bitOffset: 0 + bitWidth: 8 + access: read-write + - register: + name: EP1_CONF + description: Endpoint 1 configure and status register + addressOffset: 4 + size: 32 + resetValue: 2 + fields: + - name: WR_DONE + description: Set this bit to indicate writing byte data to UART Tx FIFO is done. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SERIAL_IN_EP_DATA_FREE + description: "1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host." + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SERIAL_OUT_EP_DATA_AVAIL + description: "1'b1: Indicate there is data in UART Rx FIFO." + bitOffset: 2 + bitWidth: 1 + access: read-only + - register: + name: INT_RAW + description: Raw status interrupt + addressOffset: 8 + size: 32 + resetValue: 8 + fields: + - name: JTAG_IN_FLUSH_INT_RAW + description: The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SOF_INT_RAW + description: The raw interrupt bit turns to high level when SOF frame is received. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SERIAL_OUT_RECV_PKT_INT_RAW + description: The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SERIAL_IN_EMPTY_INT_RAW + description: The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PID_ERR_INT_RAW + description: The raw interrupt bit turns to high level when pid error is detected. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CRC5_ERR_INT_RAW + description: The raw interrupt bit turns to high level when CRC5 error is detected. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CRC16_ERR_INT_RAW + description: The raw interrupt bit turns to high level when CRC16 error is detected. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: STUFF_ERR_INT_RAW + description: The raw interrupt bit turns to high level when stuff error is detected. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IN_TOKEN_REC_IN_EP1_INT_RAW + description: The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: USB_BUS_RESET_INT_RAW + description: The raw interrupt bit turns to high level when usb bus reset is detected. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OUT_EP1_ZERO_PAYLOAD_INT_RAW + description: The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OUT_EP2_ZERO_PAYLOAD_INT_RAW + description: The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload. + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: INT_ST + description: Masked interrupt + addressOffset: 12 + size: 32 + fields: + - name: JTAG_IN_FLUSH_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: SOF_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-only + - name: SERIAL_OUT_RECV_PKT_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: SERIAL_IN_EMPTY_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: PID_ERR_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: CRC5_ERR_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CRC16_ERR_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: STUFF_ERR_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IN_TOKEN_REC_IN_EP1_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-only + - name: USB_BUS_RESET_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-only + - name: OUT_EP1_ZERO_PAYLOAD_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-only + - name: OUT_EP2_ZERO_PAYLOAD_INT_ST + description: The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-only + - register: + name: INT_ENA + description: Interrupt enable bits + addressOffset: 16 + size: 32 + fields: + - name: JTAG_IN_FLUSH_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SOF_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: SERIAL_OUT_RECV_PKT_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: SERIAL_IN_EMPTY_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: PID_ERR_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: CRC5_ERR_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: CRC16_ERR_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: STUFF_ERR_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: IN_TOKEN_REC_IN_EP1_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: USB_BUS_RESET_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: OUT_EP1_ZERO_PAYLOAD_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: OUT_EP2_ZERO_PAYLOAD_INT_ENA + description: The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: read-write + - register: + name: INT_CLR + description: Interrupt clear bits + addressOffset: 20 + size: 32 + fields: + - name: JTAG_IN_FLUSH_INT_CLR + description: Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. + bitOffset: 0 + bitWidth: 1 + access: write-only + - name: SOF_INT_CLR + description: Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. + bitOffset: 1 + bitWidth: 1 + access: write-only + - name: SERIAL_OUT_RECV_PKT_INT_CLR + description: Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. + bitOffset: 2 + bitWidth: 1 + access: write-only + - name: SERIAL_IN_EMPTY_INT_CLR + description: Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. + bitOffset: 3 + bitWidth: 1 + access: write-only + - name: PID_ERR_INT_CLR + description: Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. + bitOffset: 4 + bitWidth: 1 + access: write-only + - name: CRC5_ERR_INT_CLR + description: Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. + bitOffset: 5 + bitWidth: 1 + access: write-only + - name: CRC16_ERR_INT_CLR + description: Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. + bitOffset: 6 + bitWidth: 1 + access: write-only + - name: STUFF_ERR_INT_CLR + description: Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. + bitOffset: 7 + bitWidth: 1 + access: write-only + - name: IN_TOKEN_REC_IN_EP1_INT_CLR + description: Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. + bitOffset: 8 + bitWidth: 1 + access: write-only + - name: USB_BUS_RESET_INT_CLR + description: Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. + bitOffset: 9 + bitWidth: 1 + access: write-only + - name: OUT_EP1_ZERO_PAYLOAD_INT_CLR + description: Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. + bitOffset: 10 + bitWidth: 1 + access: write-only + - name: OUT_EP2_ZERO_PAYLOAD_INT_CLR + description: Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. + bitOffset: 11 + bitWidth: 1 + access: write-only + - register: + name: CONF0 + description: Configure 0 register + addressOffset: 24 + size: 32 + resetValue: 16896 + fields: + - name: PHY_SEL + description: Select internal/external PHY + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: EXCHG_PINS_OVERRIDE + description: Enable software control USB D+ D- exchange + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: EXCHG_PINS + description: USB D+ D- exchange + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: VREFH + description: "Control single-end input high threshold,1.76V to 2V, step 80mV" + bitOffset: 3 + bitWidth: 2 + access: read-write + - name: VREFL + description: "Control single-end input low threshold,0.8V to 1.04V, step 80mV" + bitOffset: 5 + bitWidth: 2 + access: read-write + - name: VREF_OVERRIDE + description: Enable software control input threshold + bitOffset: 7 + bitWidth: 1 + access: read-write + - name: PAD_PULL_OVERRIDE + description: Enable software control USB D+ D- pullup pulldown + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: DP_PULLUP + description: Control USB D+ pull up. + bitOffset: 9 + bitWidth: 1 + access: read-write + - name: DP_PULLDOWN + description: Control USB D+ pull down. + bitOffset: 10 + bitWidth: 1 + access: read-write + - name: DM_PULLUP + description: Control USB D- pull up. + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: DM_PULLDOWN + description: Control USB D- pull down. + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: PULLUP_VALUE + description: Control pull up value. + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: USB_PAD_ENABLE + description: Enable USB pad function. + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: PHY_TX_EDGE_SEL + description: "0: TX output at clock negedge. 1: Tx output at clock posedge." + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: USB_JTAG_BRIDGE_EN + description: "Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix." + bitOffset: 16 + bitWidth: 1 + access: read-write + - register: + name: TEST + description: USB Internal PHY test register + addressOffset: 28 + size: 32 + fields: + - name: ENABLE + description: Enable test of the USB pad + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: USB_OE + description: USB pad oen in test + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TX_DP + description: USB D+ tx value in test + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TX_DM + description: USB D- tx value in test + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: RX_RCV + description: USB differential rx value in test + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: RX_DP + description: USB D+ rx value in test + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: RX_DM + description: USB D- rx value in test + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: JFIFO_ST + description: USB-JTAG FIFO status + addressOffset: 32 + size: 32 + resetValue: 68 + fields: + - name: IN_FIFO_CNT + description: JTAT in fifo counter. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_FIFO_EMPTY + description: "1: JTAG in fifo is empty." + bitOffset: 2 + bitWidth: 1 + access: read-only + - name: IN_FIFO_FULL + description: "1: JTAG in fifo is full." + bitOffset: 3 + bitWidth: 1 + access: read-only + - name: OUT_FIFO_CNT + description: JTAT out fifo counter. + bitOffset: 4 + bitWidth: 2 + access: read-only + - name: OUT_FIFO_EMPTY + description: "1: JTAG out fifo is empty." + bitOffset: 6 + bitWidth: 1 + access: read-only + - name: OUT_FIFO_FULL + description: "1: JTAG out fifo is full." + bitOffset: 7 + bitWidth: 1 + access: read-only + - name: IN_FIFO_RESET + description: Write 1 to reset JTAG in fifo. + bitOffset: 8 + bitWidth: 1 + access: read-write + - name: OUT_FIFO_RESET + description: Write 1 to reset JTAG out fifo. + bitOffset: 9 + bitWidth: 1 + access: read-write + - register: + name: FRAM_NUM + description: SOF frame number + addressOffset: 36 + size: 32 + fields: + - name: SOF_FRAME_INDEX + description: Frame index of received SOF frame. + bitOffset: 0 + bitWidth: 11 + access: read-only + - register: + name: IN_EP0_ST + description: IN Endpoint 0 status + addressOffset: 40 + size: 32 + resetValue: 1 + fields: + - name: IN_EP0_STATE + description: State of IN Endpoint 0. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_EP0_WR_ADDR + description: Write data address of IN endpoint 0. + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: IN_EP0_RD_ADDR + description: Read data address of IN endpoint 0. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: IN_EP1_ST + description: IN Endpoint 1 status + addressOffset: 44 + size: 32 + resetValue: 1 + fields: + - name: IN_EP1_STATE + description: State of IN Endpoint 1. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_EP1_WR_ADDR + description: Write data address of IN endpoint 1. + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: IN_EP1_RD_ADDR + description: Read data address of IN endpoint 1. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: IN_EP2_ST + description: IN Endpoint 2 status + addressOffset: 48 + size: 32 + resetValue: 1 + fields: + - name: IN_EP2_STATE + description: State of IN Endpoint 2. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_EP2_WR_ADDR + description: Write data address of IN endpoint 2. + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: IN_EP2_RD_ADDR + description: Read data address of IN endpoint 2. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: IN_EP3_ST + description: IN Endpoint 3 status + addressOffset: 52 + size: 32 + resetValue: 1 + fields: + - name: IN_EP3_STATE + description: State of IN Endpoint 3. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: IN_EP3_WR_ADDR + description: Write data address of IN endpoint 3. + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: IN_EP3_RD_ADDR + description: Read data address of IN endpoint 3. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: OUT_EP0_ST + description: OUT Endpoint 0 status + addressOffset: 56 + size: 32 + fields: + - name: OUT_EP0_STATE + description: State of OUT Endpoint 0. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: OUT_EP0_WR_ADDR + description: "Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0." + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: OUT_EP0_RD_ADDR + description: Read data address of OUT endpoint 0. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: OUT_EP1_ST + description: OUT Endpoint 1 status + addressOffset: 60 + size: 32 + fields: + - name: OUT_EP1_STATE + description: State of OUT Endpoint 1. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: OUT_EP1_WR_ADDR + description: "Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1." + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: OUT_EP1_RD_ADDR + description: Read data address of OUT endpoint 1. + bitOffset: 9 + bitWidth: 7 + access: read-only + - name: OUT_EP1_REC_DATA_CNT + description: Data count in OUT endpoint 1 when one packet is received. + bitOffset: 16 + bitWidth: 7 + access: read-only + - register: + name: OUT_EP2_ST + description: OUT Endpoint 2 status + addressOffset: 64 + size: 32 + fields: + - name: OUT_EP2_STATE + description: State of OUT Endpoint 2. + bitOffset: 0 + bitWidth: 2 + access: read-only + - name: OUT_EP2_WR_ADDR + description: "Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2." + bitOffset: 2 + bitWidth: 7 + access: read-only + - name: OUT_EP2_RD_ADDR + description: Read data address of OUT endpoint 2. + bitOffset: 9 + bitWidth: 7 + access: read-only + - register: + name: MISC_CONF + description: MISC register + addressOffset: 68 + size: 32 + fields: + - name: CLK_EN + description: "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: MEM_CONF + description: Power control + addressOffset: 72 + size: 32 + resetValue: 2 + fields: + - name: USB_MEM_PD + description: "1: power down usb memory." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: USB_MEM_CLK_EN + description: "1: Force clock on for usb memory." + bitOffset: 1 + bitWidth: 1 + access: read-write + - register: + name: DATE + description: Version control register + addressOffset: 128 + size: 32 + resetValue: 34607616 + fields: + - name: DATE + description: register version. + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: USB_WRAP + description: USB_WRAP Peripheral + groupName: USB_WRAP + baseAddress: 1610846208 + addressBlock: + - offset: 0 + size: 12 + usage: registers + registers: + - register: + name: OTG_CONF + description: USB OTG Wrapper Configure Register + addressOffset: 0 + size: 32 + resetValue: 1835008 + fields: + - name: SRP_SESSEND_OVERRIDE + description: "This bit is used to enable the software over-ride of srp session end signal. 1'b0: the signal is controlled by the chip input. 1'b1: the signal is controlled by the software." + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: SRP_SESSEND_VALUE + description: Software over-ride value of srp session end signal. + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: PHY_SEL + description: "Select internal external PHY. 1'b0: Select internal PHY. 1'b1: Select external PHY." + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: DFIFO_FORCE_PD + description: Force the dfifo to go into low power mode. The data in dfifo will not lost. + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: DBNCE_FLTR_BYPASS + description: "Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals" + bitOffset: 4 + bitWidth: 1 + access: read-write + - name: EXCHG_PINS_OVERRIDE + description: Enable software controlle USB D+ D- exchange + bitOffset: 5 + bitWidth: 1 + access: read-write + - name: EXCHG_PINS + description: "USB D+ D- exchange. 1'b0: don't change. 1'b1: exchange D+ D-" + bitOffset: 6 + bitWidth: 1 + access: read-write + - name: VREFH + description: "Control single-end input high threshold,1.76V to 2V, step 80mV" + bitOffset: 7 + bitWidth: 2 + access: read-write + - name: VREFL + description: "Control single-end input low threshold,0.8V to 1.04V, step 80mV" + bitOffset: 9 + bitWidth: 2 + access: read-write + - name: VREF_OVERRIDE + description: Enable software controlle input threshold + bitOffset: 11 + bitWidth: 1 + access: read-write + - name: PAD_PULL_OVERRIDE + description: Enable software controlle USB D+ D- pullup pulldown + bitOffset: 12 + bitWidth: 1 + access: read-write + - name: DP_PULLUP + description: Controlle USB D+ pullup + bitOffset: 13 + bitWidth: 1 + access: read-write + - name: DP_PULLDOWN + description: Controlle USB D+ pulldown + bitOffset: 14 + bitWidth: 1 + access: read-write + - name: DM_PULLUP + description: Controlle USB D+ pullup + bitOffset: 15 + bitWidth: 1 + access: read-write + - name: DM_PULLDOWN + description: Controlle USB D+ pulldown + bitOffset: 16 + bitWidth: 1 + access: read-write + - name: PULLUP_VALUE + description: "Controlle pullup value. 1'b0: typical value is 2.4K. 1'b1: typical value is 1.2K." + bitOffset: 17 + bitWidth: 1 + access: read-write + - name: USB_PAD_ENABLE + description: Enable USB pad function + bitOffset: 18 + bitWidth: 1 + access: read-write + - name: AHB_CLK_FORCE_ON + description: Force ahb clock always on + bitOffset: 19 + bitWidth: 1 + access: read-write + - name: PHY_CLK_FORCE_ON + description: Force phy clock always on + bitOffset: 20 + bitWidth: 1 + access: read-write + - name: PHY_TX_EDGE_SEL + description: "Select phy tx signal output clock edge. 1'b0: negedge. 1'b1: posedge." + bitOffset: 21 + bitWidth: 1 + access: read-write + - name: DFIFO_FORCE_PU + description: Disable the dfifo to go into low power mode. The data in dfifo will not lost. + bitOffset: 22 + bitWidth: 1 + access: read-write + - name: CLK_EN + description: Disable auto clock gating of CSR registers + bitOffset: 31 + bitWidth: 1 + access: read-write + - register: + name: TEST_CONF + description: USB Internal PHY Testing Register + addressOffset: 4 + size: 32 + fields: + - name: TEST_ENABLE + description: Enable test of the USB pad + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: TEST_USB_OE + description: USB pad oen in test + bitOffset: 1 + bitWidth: 1 + access: read-write + - name: TEST_TX_DP + description: USB D+ tx value in test + bitOffset: 2 + bitWidth: 1 + access: read-write + - name: TEST_TX_DM + description: USB D- tx value in test + bitOffset: 3 + bitWidth: 1 + access: read-write + - name: TEST_RX_RCV + description: USB differential rx value in test + bitOffset: 4 + bitWidth: 1 + access: read-only + - name: TEST_RX_DP + description: USB D+ rx value in test + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: TEST_RX_DM + description: USB D- rx value in test + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: DATE + description: Version Control Register + addressOffset: 1020 + size: 32 + resetValue: 34611216 + fields: + - name: USB_WRAP_DATE + description: Date register + bitOffset: 0 + bitWidth: 32 + access: read-write + - name: WCL + description: WCL Peripheral + groupName: WCL + baseAddress: 1611464704 + addressBlock: + - offset: 0 + size: 352 + usage: registers + registers: + - register: + name: Core_0_ENTRY_1_ADDR + description: Core_0 Entry 1 address configuration Register + addressOffset: 0 + size: 32 + fields: + - name: CORE_0_ENTRY_1_ADDR + description: Core_0 Entry 1 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_0_ENTRY_2_ADDR + description: Core_0 Entry 2 address configuration Register + addressOffset: 4 + size: 32 + fields: + - name: CORE_0_ENTRY_2_ADDR + description: Core_0 Entry 2 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_0_ENTRY_3_ADDR + description: Core_0 Entry 3 address configuration Register + addressOffset: 8 + size: 32 + fields: + - name: CORE_0_ENTRY_3_ADDR + description: Core_0 Entry 3 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_0_ENTRY_4_ADDR + description: Core_0 Entry 4 address configuration Register + addressOffset: 12 + size: 32 + fields: + - name: CORE_0_ENTRY_4_ADDR + description: Core_0 Entry 4 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_0_ENTRY_5_ADDR + description: Core_0 Entry 5 address configuration Register + addressOffset: 16 + size: 32 + fields: + - name: CORE_0_ENTRY_5_ADDR + description: Core_0 Entry 5 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_0_ENTRY_6_ADDR + description: Core_0 Entry 6 address configuration Register + addressOffset: 20 + size: 32 + fields: + - name: CORE_0_ENTRY_6_ADDR + description: Core_0 Entry 6 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_0_ENTRY_7_ADDR + description: Core_0 Entry 7 address configuration Register + addressOffset: 24 + size: 32 + fields: + - name: CORE_0_ENTRY_7_ADDR + description: Core_0 Entry 7 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_0_ENTRY_8_ADDR + description: Core_0 Entry 8 address configuration Register + addressOffset: 28 + size: 32 + fields: + - name: CORE_0_ENTRY_8_ADDR + description: Core_0 Entry 8 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_0_ENTRY_9_ADDR + description: Core_0 Entry 9 address configuration Register + addressOffset: 32 + size: 32 + fields: + - name: CORE_0_ENTRY_9_ADDR + description: Core_0 Entry 9 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_0_ENTRY_10_ADDR + description: Core_0 Entry 10 address configuration Register + addressOffset: 36 + size: 32 + fields: + - name: CORE_0_ENTRY_10_ADDR + description: Core_0 Entry 10 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_0_ENTRY_11_ADDR + description: Core_0 Entry 11 address configuration Register + addressOffset: 40 + size: 32 + fields: + - name: CORE_0_ENTRY_11_ADDR + description: Core_0 Entry 11 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_0_ENTRY_12_ADDR + description: Core_0 Entry 12 address configuration Register + addressOffset: 44 + size: 32 + fields: + - name: CORE_0_ENTRY_12_ADDR + description: Core_0 Entry 12 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_0_ENTRY_13_ADDR + description: Core_0 Entry 13 address configuration Register + addressOffset: 48 + size: 32 + fields: + - name: CORE_0_ENTRY_13_ADDR + description: Core_0 Entry 13 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_0_ENTRY_CHECK + description: Core_0 Entry check configuration Register + addressOffset: 124 + size: 32 + resetValue: 2 + fields: + - name: CORE_0_ENTRY_CHECK + description: This filed is used to enable entry address check + bitOffset: 1 + bitWidth: 13 + access: read-write + - register: + name: Core_0_STATUSTABLE1 + description: Status register of world switch of entry 1 + addressOffset: 128 + size: 32 + fields: + - name: CORE_0_FROM_WORLD_1 + description: This bit is used to confirm world before enter entry 1 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_FROM_ENTRY_1 + description: This filed is used to confirm in which entry before enter entry 1 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_0_CURRENT_1 + description: This bit is used to confirm whether the current state is in entry 1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_0_STATUSTABLE2 + description: Status register of world switch of entry 2 + addressOffset: 132 + size: 32 + fields: + - name: CORE_0_FROM_WORLD_2 + description: This bit is used to confirm world before enter entry 2 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_FROM_ENTRY_2 + description: This filed is used to confirm in which entry before enter entry 2 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_0_CURRENT_2 + description: This bit is used to confirm whether the current state is in entry 2 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_0_STATUSTABLE3 + description: Status register of world switch of entry 3 + addressOffset: 136 + size: 32 + fields: + - name: CORE_0_FROM_WORLD_3 + description: This bit is used to confirm world before enter entry 3 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_FROM_ENTRY_3 + description: This filed is used to confirm in which entry before enter entry 3 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_0_CURRENT_3 + description: This bit is used to confirm whether the current state is in entry 3 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_0_STATUSTABLE4 + description: Status register of world switch of entry 4 + addressOffset: 140 + size: 32 + fields: + - name: CORE_0_FROM_WORLD_4 + description: This bit is used to confirm world before enter entry 4 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_FROM_ENTRY_4 + description: This filed is used to confirm in which entry before enter entry 4 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_0_CURRENT_4 + description: This bit is used to confirm whether the current state is in entry 4 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_0_STATUSTABLE5 + description: Status register of world switch of entry 5 + addressOffset: 144 + size: 32 + fields: + - name: CORE_0_FROM_WORLD_5 + description: This bit is used to confirm world before enter entry 5 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_FROM_ENTRY_5 + description: This filed is used to confirm in which entry before enter entry 5 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_0_CURRENT_5 + description: This bit is used to confirm whether the current state is in entry 5 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_0_STATUSTABLE6 + description: Status register of world switch of entry 6 + addressOffset: 148 + size: 32 + fields: + - name: CORE_0_FROM_WORLD_6 + description: This bit is used to confirm world before enter entry 6 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_FROM_ENTRY_6 + description: This filed is used to confirm in which entry before enter entry 6 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_0_CURRENT_6 + description: This bit is used to confirm whether the current state is in entry 6 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_0_STATUSTABLE7 + description: Status register of world switch of entry 7 + addressOffset: 152 + size: 32 + fields: + - name: CORE_0_FROM_WORLD_7 + description: This bit is used to confirm world before enter entry 7 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_FROM_ENTRY_7 + description: This filed is used to confirm in which entry before enter entry 7 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_0_CURRENT_7 + description: This bit is used to confirm whether the current state is in entry 7 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_0_STATUSTABLE8 + description: Status register of world switch of entry 8 + addressOffset: 156 + size: 32 + fields: + - name: CORE_0_FROM_WORLD_8 + description: This bit is used to confirm world before enter entry 8 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_FROM_ENTRY_8 + description: This filed is used to confirm in which entry before enter entry 8 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_0_CURRENT_8 + description: This bit is used to confirm whether the current state is in entry 8 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_0_STATUSTABLE9 + description: Status register of world switch of entry 9 + addressOffset: 160 + size: 32 + fields: + - name: CORE_0_FROM_WORLD_9 + description: This bit is used to confirm world before enter entry 9 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_FROM_ENTRY_9 + description: This filed is used to confirm in which entry before enter entry 9 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_0_CURRENT_9 + description: This bit is used to confirm whether the current state is in entry 9 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_0_STATUSTABLE10 + description: Status register of world switch of entry 10 + addressOffset: 164 + size: 32 + fields: + - name: CORE_0_FROM_WORLD_10 + description: This bit is used to confirm world before enter entry 10 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_FROM_ENTRY_10 + description: This filed is used to confirm in which entry before enter entry 10 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_0_CURRENT_10 + description: This bit is used to confirm whether the current state is in entry 10 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_0_STATUSTABLE11 + description: Status register of world switch of entry 11 + addressOffset: 168 + size: 32 + fields: + - name: CORE_0_FROM_WORLD_11 + description: This bit is used to confirm world before enter entry 11 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_FROM_ENTRY_11 + description: This filed is used to confirm in which entry before enter entry 11 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_0_CURRENT_11 + description: This bit is used to confirm whether the current state is in entry 11 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_0_STATUSTABLE12 + description: Status register of world switch of entry 12 + addressOffset: 172 + size: 32 + fields: + - name: CORE_0_FROM_WORLD_12 + description: This bit is used to confirm world before enter entry 12 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_FROM_ENTRY_12 + description: This filed is used to confirm in which entry before enter entry 12 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_0_CURRENT_12 + description: This bit is used to confirm whether the current state is in entry 12 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_0_STATUSTABLE13 + description: Status register of world switch of entry 13 + addressOffset: 176 + size: 32 + fields: + - name: CORE_0_FROM_WORLD_13 + description: This bit is used to confirm world before enter entry 13 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_0_FROM_ENTRY_13 + description: This filed is used to confirm in which entry before enter entry 13 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_0_CURRENT_13 + description: This bit is used to confirm whether the current state is in entry 13 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_0_STATUSTABLE_CURRENT + description: Status register of statustable current + addressOffset: 252 + size: 32 + fields: + - name: CORE_0_STATUSTABLE_CURRENT + description: "This field is used to quickly read and rewrite the current field of all STATUSTABLE registers,for example,bit 1 represents the current field of STATUSTABLE1,bit2 represents the current field of STATUSTABLE2" + bitOffset: 1 + bitWidth: 13 + access: read-write + - register: + name: Core_0_MESSAGE_ADDR + description: Clear writer_buffer write address configuration register + addressOffset: 256 + size: 32 + fields: + - name: CORE_0_MESSAGE_ADDR + description: This field is used to set address that need to write when enter WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_0_MESSAGE_MAX + description: Clear writer_buffer write number configuration register + addressOffset: 260 + size: 32 + fields: + - name: CORE_0_MESSAGE_MAX + description: This filed is used to set the max value of clear write_buffer + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: Core_0_MESSAGE_PHASE + description: Clear writer_buffer status register + addressOffset: 264 + size: 32 + fields: + - name: CORE_0_MESSAGE_MATCH + description: This bit indicates whether the check is successful + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_0_MESSAGE_EXPECT + description: This field indicates the data to be written next time + bitOffset: 1 + bitWidth: 4 + access: read-only + - name: CORE_0_MESSAGE_DATAPHASE + description: "If this bit is 1, it means that is checking clear write_buffer operation,and is checking data" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CORE_0_MESSAGE_ADDRESSPHASE + description: "If this bit is 1, it means that is checking clear write_buffer operation,and is checking address." + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: Core_0_World_TRIGGER_ADDR + description: Core_0 trigger address configuration Register + addressOffset: 320 + size: 32 + fields: + - name: CORE_0_WORLD_TRIGGER_ADDR + description: "This field is used to configure the entry address from WORLD0 to WORLD1,when the CPU executes to this address,switch to WORLD1" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_0_World_PREPARE + description: Core_0 prepare world configuration Register + addressOffset: 324 + size: 32 + fields: + - name: CORE_0_WORLD_PREPARE + description: "This field to used to set world to enter, 2'b01 means WORLD0, 2'b10 means WORLD1" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: Core_0_World_UPDATE + description: Core_0 configuration update register + addressOffset: 328 + size: 32 + fields: + - name: CORE_0_UPDATE + description: "This field is used to update configuration completed, can write any value,the hardware only checks the write operation of this register and does not case about its value" + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: Core_0_World_Cancel + description: Core_0 configuration cancel register + addressOffset: 332 + size: 32 + fields: + - name: CORE_0_WORLD_CANCEL + description: "This field is used to cancel switch world configuration,if the trigger address and update configuration complete,use this register to cancel world switch, jujst need write any value,the hardware only checks the write operation of this register and does not case about its value" + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: Core_0_World_IRam0 + description: Core_0 Iram0 world register + addressOffset: 336 + size: 32 + fields: + - name: CORE_0_WORLD_IRAM0 + description: this field is used to read current world of Iram0 bus + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: Core_0_World_DRam0_PIF + description: Core_0 dram0 and PIF world register + addressOffset: 340 + size: 32 + fields: + - name: CORE_0_WORLD_DRAM0_PIF + description: this field is used to read current world of Dram0 bus and PIF bus + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: Core_0_World_Phase + description: Core_0 world status register + addressOffset: 344 + size: 32 + fields: + - name: CORE_0_WORLD_PHASE + description: "This bit indicates whether is preparing to switch to WORLD1, 1 means value." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: Core_0_NMI_MASK_ENABLE + description: Core_0 NMI mask enable register + addressOffset: 384 + size: 32 + fields: + - name: CORE_0_NMI_MASK_ENABLE + description: "this field is used to set NMI mask,it can write any value,when write this register,the hardware start masking NMI interrupt" + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: Core_0_NMI_MASK_TRIGGER_ADDR + description: Core_0 NMI mask trigger address register + addressOffset: 388 + size: 32 + fields: + - name: CORE_0_NMI_MASK_TRIGGER_ADDR + description: "this field to used to set trigger address, when CPU executes to this address,NMI mask automatically fails" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_0_NMI_MASK_DISABLE + description: Core_0 NMI mask disable register + addressOffset: 392 + size: 32 + fields: + - name: CORE_0_NMI_MASK_DISABLE + description: "this field is used to disable NMI mask,it will not take effect immediately,only when the CPU executes to the trigger address will it start to cancel NMI mask" + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: Core_0_NMI_MASK_CANCLE + description: Core_0 NMI mask disable register + addressOffset: 396 + size: 32 + fields: + - name: CORE_0_NMI_MASK_CANCEL + description: this field is used to cancel NMI mask disable function. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: Core_0_NMI_MASK + description: Core_0 NMI mask register + addressOffset: 400 + size: 32 + fields: + - name: CORE_0_NMI_MASK + description: "this bit is used to mask NMI interrupt,it can directly mask NMI interrupt" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: Core_0_NMI_MASK_PHASE + description: Core_0 NMI mask phase register + addressOffset: 404 + size: 32 + fields: + - name: CORE_0_NMI_MASK_PHASE + description: "this bit is used to indicates whether the NMI interrupt is being masked, 1 means NMI interrupt is being masked" + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: Core_1_ENTRY_1_ADDR + description: Core_1 Entry 1 address configuration Register + addressOffset: 1024 + size: 32 + fields: + - name: CORE_1_ENTRY_1_ADDR + description: Core_1 Entry 1 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_1_ENTRY_2_ADDR + description: Core_1 Entry 2 address configuration Register + addressOffset: 1028 + size: 32 + fields: + - name: CORE_1_ENTRY_2_ADDR + description: Core_1 Entry 2 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_1_ENTRY_3_ADDR + description: Core_1 Entry 3 address configuration Register + addressOffset: 1032 + size: 32 + fields: + - name: CORE_1_ENTRY_3_ADDR + description: Core_1 Entry 3 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_1_ENTRY_4_ADDR + description: Core_1 Entry 4 address configuration Register + addressOffset: 1036 + size: 32 + fields: + - name: CORE_1_ENTRY_4_ADDR + description: Core_1 Entry 4 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_1_ENTRY_5_ADDR + description: Core_1 Entry 5 address configuration Register + addressOffset: 1040 + size: 32 + fields: + - name: CORE_1_ENTRY_5_ADDR + description: Core_1 Entry 5 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_1_ENTRY_6_ADDR + description: Core_1 Entry 6 address configuration Register + addressOffset: 1044 + size: 32 + fields: + - name: CORE_1_ENTRY_6_ADDR + description: Core_1 Entry 6 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_1_ENTRY_7_ADDR + description: Core_1 Entry 7 address configuration Register + addressOffset: 1048 + size: 32 + fields: + - name: CORE_1_ENTRY_7_ADDR + description: Core_1 Entry 7 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_1_ENTRY_8_ADDR + description: Core_1 Entry 8 address configuration Register + addressOffset: 1052 + size: 32 + fields: + - name: CORE_1_ENTRY_8_ADDR + description: Core_1 Entry 8 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_1_ENTRY_9_ADDR + description: Core_1 Entry 9 address configuration Register + addressOffset: 1056 + size: 32 + fields: + - name: CORE_1_ENTRY_9_ADDR + description: Core_1 Entry 9 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_1_ENTRY_10_ADDR + description: Core_1 Entry 10 address configuration Register + addressOffset: 1060 + size: 32 + fields: + - name: CORE_1_ENTRY_10_ADDR + description: Core_1 Entry 10 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_1_ENTRY_11_ADDR + description: Core_1 Entry 11 address configuration Register + addressOffset: 1064 + size: 32 + fields: + - name: CORE_1_ENTRY_11_ADDR + description: Core_1 Entry 11 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_1_ENTRY_12_ADDR + description: Core_1 Entry 12 address configuration Register + addressOffset: 1068 + size: 32 + fields: + - name: CORE_1_ENTRY_12_ADDR + description: Core_1 Entry 12 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_1_ENTRY_13_ADDR + description: Core_1 Entry 13 address configuration Register + addressOffset: 1072 + size: 32 + fields: + - name: CORE_1_ENTRY_13_ADDR + description: Core_1 Entry 13 address from WORLD1 to WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_1_ENTRY_CHECK + description: Core_1 Entry check configuration Register + addressOffset: 1148 + size: 32 + resetValue: 2 + fields: + - name: CORE_1_ENTRY_CHECK + description: This filed is used to enable entry address check + bitOffset: 1 + bitWidth: 13 + access: read-write + - register: + name: Core_1_STATUSTABLE1 + description: Status register of world switch of entry 1 + addressOffset: 1152 + size: 32 + fields: + - name: CORE_1_FROM_WORLD_1 + description: This bit is used to confirm world before enter entry 1 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_1_FROM_ENTRY_1 + description: This filed is used to confirm in which entry before enter entry 1 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_1_CURRENT_1 + description: This bit is used to confirm whether the current state is in entry 1 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_1_STATUSTABLE2 + description: Status register of world switch of entry 2 + addressOffset: 1156 + size: 32 + fields: + - name: CORE_1_FROM_WORLD_2 + description: This bit is used to confirm world before enter entry 2 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_1_FROM_ENTRY_2 + description: This filed is used to confirm in which entry before enter entry 2 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_1_CURRENT_2 + description: This bit is used to confirm whether the current state is in entry 2 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_1_STATUSTABLE3 + description: Status register of world switch of entry 3 + addressOffset: 1160 + size: 32 + fields: + - name: CORE_1_FROM_WORLD_3 + description: This bit is used to confirm world before enter entry 3 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_1_FROM_ENTRY_3 + description: This filed is used to confirm in which entry before enter entry 3 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_1_CURRENT_3 + description: This bit is used to confirm whether the current state is in entry 3 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_1_STATUSTABLE4 + description: Status register of world switch of entry 4 + addressOffset: 1164 + size: 32 + fields: + - name: CORE_1_FROM_WORLD_4 + description: This bit is used to confirm world before enter entry 4 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_1_FROM_ENTRY_4 + description: This filed is used to confirm in which entry before enter entry 4 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_1_CURRENT_4 + description: This bit is used to confirm whether the current state is in entry 4 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_1_STATUSTABLE5 + description: Status register of world switch of entry 5 + addressOffset: 1168 + size: 32 + fields: + - name: CORE_1_FROM_WORLD_5 + description: This bit is used to confirm world before enter entry 5 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_1_FROM_ENTRY_5 + description: This filed is used to confirm in which entry before enter entry 5 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_1_CURRENT_5 + description: This bit is used to confirm whether the current state is in entry 5 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_1_STATUSTABLE6 + description: Status register of world switch of entry 6 + addressOffset: 1172 + size: 32 + fields: + - name: CORE_1_FROM_WORLD_6 + description: This bit is used to confirm world before enter entry 6 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_1_FROM_ENTRY_6 + description: This filed is used to confirm in which entry before enter entry 6 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_1_CURRENT_6 + description: This bit is used to confirm whether the current state is in entry 6 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_1_STATUSTABLE7 + description: Status register of world switch of entry 7 + addressOffset: 1176 + size: 32 + fields: + - name: CORE_1_FROM_WORLD_7 + description: This bit is used to confirm world before enter entry 7 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_1_FROM_ENTRY_7 + description: This filed is used to confirm in which entry before enter entry 7 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_1_CURRENT_7 + description: This bit is used to confirm whether the current state is in entry 7 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_1_STATUSTABLE8 + description: Status register of world switch of entry 8 + addressOffset: 1180 + size: 32 + fields: + - name: CORE_1_FROM_WORLD_8 + description: This bit is used to confirm world before enter entry 8 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_1_FROM_ENTRY_8 + description: This filed is used to confirm in which entry before enter entry 8 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_1_CURRENT_8 + description: This bit is used to confirm whether the current state is in entry 8 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_1_STATUSTABLE9 + description: Status register of world switch of entry 9 + addressOffset: 1184 + size: 32 + fields: + - name: CORE_1_FROM_WORLD_9 + description: This bit is used to confirm world before enter entry 9 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_1_FROM_ENTRY_9 + description: This filed is used to confirm in which entry before enter entry 9 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_1_CURRENT_9 + description: This bit is used to confirm whether the current state is in entry 9 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_1_STATUSTABLE10 + description: Status register of world switch of entry 10 + addressOffset: 1188 + size: 32 + fields: + - name: CORE_1_FROM_WORLD_10 + description: This bit is used to confirm world before enter entry 10 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_1_FROM_ENTRY_10 + description: This filed is used to confirm in which entry before enter entry 10 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_1_CURRENT_10 + description: This bit is used to confirm whether the current state is in entry 10 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_1_STATUSTABLE11 + description: Status register of world switch of entry 11 + addressOffset: 1192 + size: 32 + fields: + - name: CORE_1_FROM_WORLD_11 + description: This bit is used to confirm world before enter entry 11 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_1_FROM_ENTRY_11 + description: This filed is used to confirm in which entry before enter entry 11 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_1_CURRENT_11 + description: This bit is used to confirm whether the current state is in entry 11 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_1_STATUSTABLE12 + description: Status register of world switch of entry 12 + addressOffset: 1196 + size: 32 + fields: + - name: CORE_1_FROM_WORLD_12 + description: This bit is used to confirm world before enter entry 12 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_1_FROM_ENTRY_12 + description: This filed is used to confirm in which entry before enter entry 12 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_1_CURRENT_12 + description: This bit is used to confirm whether the current state is in entry 12 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_1_STATUSTABLE13 + description: Status register of world switch of entry 13 + addressOffset: 1200 + size: 32 + fields: + - name: CORE_1_FROM_WORLD_13 + description: This bit is used to confirm world before enter entry 13 + bitOffset: 0 + bitWidth: 1 + access: read-write + - name: CORE_1_FROM_ENTRY_13 + description: This filed is used to confirm in which entry before enter entry 13 + bitOffset: 1 + bitWidth: 4 + access: read-write + - name: CORE_1_CURRENT_13 + description: This bit is used to confirm whether the current state is in entry 13 + bitOffset: 5 + bitWidth: 1 + access: read-write + - register: + name: Core_1_STATUSTABLE_CURRENT + description: Status register of statustable current + addressOffset: 1276 + size: 32 + fields: + - name: CORE_1_STATUSTABLE_CURRENT + description: "This field is used to quickly read and rewrite the current field of all STATUSTABLE registers,for example,bit 1 represents the current field of STATUSTABLE1" + bitOffset: 1 + bitWidth: 13 + access: read-write + - register: + name: Core_1_MESSAGE_ADDR + description: Clear writer_buffer write address configuration register + addressOffset: 1280 + size: 32 + fields: + - name: CORE_1_MESSAGE_ADDR + description: This field is used to set address that need to write when enter WORLD0 + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_1_MESSAGE_MAX + description: Clear writer_buffer write number configuration register + addressOffset: 1284 + size: 32 + fields: + - name: CORE_1_MESSAGE_MAX + description: This filed is used to set the max value of clear write_buffer + bitOffset: 0 + bitWidth: 4 + access: read-write + - register: + name: Core_1_MESSAGE_PHASE + description: Clear writer_buffer status register + addressOffset: 1288 + size: 32 + fields: + - name: CORE_1_MESSAGE_MATCH + description: This bit indicates whether the check is successful + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: CORE_1_MESSAGE_EXPECT + description: This field indicates the data to be written next time + bitOffset: 1 + bitWidth: 4 + access: read-only + - name: CORE_1_MESSAGE_DATAPHASE + description: "If this bit is 1, it means that is checking clear write_buffer operation, and is checking data" + bitOffset: 5 + bitWidth: 1 + access: read-only + - name: CORE_1_MESSAGE_ADDRESSPHASE + description: "If this bit is 1, it means that is checking clear write_buffer operation, and is checking address." + bitOffset: 6 + bitWidth: 1 + access: read-only + - register: + name: Core_1_World_TRIGGER_ADDR + description: Core_1 trigger address configuration Register + addressOffset: 1344 + size: 32 + fields: + - name: CORE_1_WORLD_TRIGGER_ADDR + description: "This field is used to configure the entry address from WORLD0 to WORLD1,when the CPU executes to this address,switch to WORLD1" + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_1_World_PREPARE + description: Core_1 prepare world configuration Register + addressOffset: 1348 + size: 32 + fields: + - name: CORE_1_WORLD_PREPARE + description: "This field to used to set world to enter,2'b01 means WORLD0, 2'b10 means WORLD1" + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: Core_1_World_UPDATE + description: Core_1 configuration update register + addressOffset: 1352 + size: 32 + fields: + - name: CORE_1_UPDATE + description: "This field is used to update configuration completed, can write any value,the hardware only checks the write operation of this register and does not case about its value" + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: Core_1_World_Cancel + description: Core_1 configuration cancel register + addressOffset: 1356 + size: 32 + fields: + - name: CORE_1_WORLD_CANCEL + description: "This field is used to cancel switch world configuration,if the trigger address and update configuration complete,can use this register to cancel world switch. can write any value, the hardware only checks the write operation of this register and does not case about its value" + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: Core_1_World_IRam0 + description: Core_1 Iram0 world register + addressOffset: 1360 + size: 32 + fields: + - name: CORE_1_WORLD_IRAM0 + description: this field is used to read current world of Iram0 bus + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: Core_1_World_DRam0_PIF + description: Core_1 dram0 and PIF world register + addressOffset: 1364 + size: 32 + fields: + - name: CORE_1_WORLD_DRAM0_PIF + description: this field is used to read current world of Dram0 bus and PIF bus + bitOffset: 0 + bitWidth: 2 + access: read-write + - register: + name: Core_1_World_Phase + description: Core_0 world status register + addressOffset: 1368 + size: 32 + fields: + - name: CORE_1_WORLD_PHASE + description: "This bit indicates whether is preparing to switch to WORLD1,1 means value." + bitOffset: 0 + bitWidth: 1 + access: read-only + - register: + name: Core_1_NMI_MASK_ENABLE + description: Core_1 NMI mask enable register + addressOffset: 1408 + size: 32 + fields: + - name: CORE_1_NMI_MASK_ENABLE + description: "this field is used to set NMI mask, it can write any value, when write this register,the hardware start masking NMI interrupt" + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: Core_1_NMI_MASK_TRIGGER_ADDR + description: Core_1 NMI mask trigger addr register + addressOffset: 1412 + size: 32 + fields: + - name: CORE_1_NMI_MASK_TRIGGER_ADDR + description: this field to used to set trigger address + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: Core_1_NMI_MASK_DISABLE + description: Core_1 NMI mask disable register + addressOffset: 1416 + size: 32 + fields: + - name: CORE_1_NMI_MASK_DISABLE + description: "this field is used to disable NMI mask, it will not take effect immediately,only when the CPU executes to the trigger address will it start to cancel NMI mask" + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: Core_1_NMI_MASK_CANCLE + description: Core_1 NMI mask disable register + addressOffset: 1420 + size: 32 + fields: + - name: CORE_1_NMI_MASK_CANCEL + description: this field is used to cancel NMI mask disable function. + bitOffset: 0 + bitWidth: 32 + access: write-only + - register: + name: Core_1_NMI_MASK + description: Core_1 NMI mask register + addressOffset: 1424 + size: 32 + fields: + - name: CORE_1_NMI_MASK + description: "this bit is used to mask NMI interrupt,it can directly mask NMI interrupt" + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: Core_1_NMI_MASK_PHASE + description: Core_1 NMI mask phase register + addressOffset: 1428 + size: 32 + fields: + - name: CORE_1_NMI_MASK_PHASE + description: "this bit is used to indicates whether the NMI interrupt is being masked, 1 means NMI interrupt is being masked" + bitOffset: 0 + bitWidth: 1 + access: read-only + - name: XTS_AES + description: XTS-AES-128 Flash Encryption + groupName: XTS_AES + baseAddress: 1611448320 + addressBlock: + - offset: 0 + size: 96 + usage: registers + registers: + - register: + dim: 16 + dimIncrement: 4 + name: PLAIN_%s + description: Plaintext register %s + addressOffset: 0 + size: 32 + fields: + - name: PLAIN + description: Stores the nth 32-bit piece of plaintext. + bitOffset: 0 + bitWidth: 32 + access: read-write + - register: + name: LINESIZE + description: XTS-AES line-size register + addressOffset: 64 + size: 32 + fields: + - name: LINESIZE + description: Configures the data size of one encryption. + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: DESTINATION + description: XTS-AES destination register + addressOffset: 68 + size: 32 + fields: + - name: DESTINATION + description: "Configures the type of the external memory. Currently, it must be set to 0, as the Manual Encryption block only supports flash encryption. Errors may occurs if users write 1. 0:flash. 1: external RAM." + bitOffset: 0 + bitWidth: 1 + access: read-write + - register: + name: PHYSICAL_ADDRESS + description: physical address + addressOffset: 72 + size: 32 + fields: + - name: PHYSICAL_ADDRESS + description: "Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes. If linesize is 64-byte, the physical address should be aligned of 64 bytes." + bitOffset: 0 + bitWidth: 30 + access: read-write + - register: + name: TRIGGER + description: XTS-AES trigger register + addressOffset: 76 + size: 32 + fields: + - name: TRIGGER + description: Write 1 to activate manual encryption. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: RELEASE + description: XTS-AES release control register + addressOffset: 80 + size: 32 + fields: + - name: RELEASE + description: Write 1 to grant SPI1 access to encrypted result. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: DESTROY + description: XTS-AES destroy control register + addressOffset: 84 + size: 32 + fields: + - name: DESTROY + description: Write 1 to destroy encrypted result. + bitOffset: 0 + bitWidth: 1 + access: write-only + - register: + name: STATE + description: XTS-AES status register + addressOffset: 88 + size: 32 + fields: + - name: STATE + description: "Those bits indicates the status of the Manual Encryption block. 0X0 (XTS_AES_IDLE): idle. 0X1 (XTS_AES_BUSY): busy with encryption. 0X2 (XTS_AES_DONE): encryption is completed, but the encrypted result is not accessible to SPI. 0X3 (XTS_AES_AVAILABLE) encrypted result is accessible and available to SPI." + bitOffset: 0 + bitWidth: 2 + access: read-only + - register: + name: DATE + description: XTS-AES version control register + addressOffset: 92 + size: 32 + resetValue: 538968337 + fields: + - name: DATE + description: Manual Encryption block version information. + bitOffset: 0 + bitWidth: 30 + access: read-write diff --git a/xtask/Cargo.lock b/xtask/Cargo.lock index cd2dfa311a..52a2a3ecb1 100644 --- a/xtask/Cargo.lock +++ b/xtask/Cargo.lock @@ -915,9 +915,9 @@ dependencies = [ [[package]] name = "svdtools" -version = "0.3.12" +version = "0.3.13" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "ac38de8b530923beb460bcab78e0ec5f3b5e4aa0fc209aa700d5a7080b41a3c2" +checksum = "bccbfd634e9fa3c724098e952883b3924f25ab55c98f507596737d4710bbed67" dependencies = [ "anyhow", "clap", diff --git a/xtask/Cargo.toml b/xtask/Cargo.toml index 879f57eaad..2be9867ddc 100644 --- a/xtask/Cargo.toml +++ b/xtask/Cargo.toml @@ -13,5 +13,5 @@ log = "0.4.20" semver = "1.0.21" strum = { version = "0.26.1", features = ["derive"] } svd2rust = { version = "0.32.0", default-features = false } -svdtools = "0.3.12" +svdtools = "0.3.13" toml_edit = "0.22.4" diff --git a/xtask/src/main.rs b/xtask/src/main.rs index 6aa6bfcb8a..3ef8b089ee 100644 --- a/xtask/src/main.rs +++ b/xtask/src/main.rs @@ -10,7 +10,9 @@ use anyhow::{Error, Result}; use clap::{Parser, Subcommand, ValueEnum}; use strum::{Display, EnumIter, IntoEnumIterator}; use svd2rust::{ - config::{IdentFormats, IdentFormatsTheme}, util::IdentFormat, Config, Target + config::{IdentFormats, IdentFormatsTheme}, + util::IdentFormat, + Config, Target, }; use svdtools::{html::html_cli::svd2html, patch::Config as PatchConfig}; use toml_edit::Document; @@ -67,6 +69,13 @@ enum Commands { chips: Vec, }, + /// Patches and generates SVD-like YAML + SvdYaml { + /// Package(s) to target + #[arg(value_enum, default_values_t = Chip::iter())] + chips: Vec, + }, + /// Generate the specified package(s) /// /// Additionally patches the releavant SVD(s) prior to generating the @@ -130,6 +139,10 @@ fn main() -> Result<()> { .iter() .try_for_each(|chip| patch_svd(&workspace, chip)), + Commands::SvdYaml { chips } => chips + .iter() + .try_for_each(|chip| generate_yaml(&workspace, chip)), + Commands::Generate { chips } => chips .iter() .try_for_each(|chip: &Chip| generate_package(&workspace, chip)), @@ -182,6 +195,27 @@ fn patch_svd(workspace: &Path, chip: &Chip) -> Result<()> { Ok(()) } +fn generate_yaml(workspace: &Path, chip: &Chip) -> Result<()> { + use svdtools::convert::convert_cli::{convert, InputFormat, OutputFormat, ParserConfig}; + patch_svd(workspace, chip)?; + let svd_path = workspace.join(chip.to_string()).join("svd"); + let from = svd_path.join(format!("{chip}.svd")); + let to = svd_path.join(format!("{chip}.svd.yaml")); + let parser_config = ParserConfig { + expand: false, + expand_properties: false, + ignore_enums: false, + }; + convert( + &from, + &to, + Some(InputFormat::Xml), + Some(OutputFormat::Yaml), + parser_config, + None, + ) +} + fn generate_package(workspace: &Path, chip: &Chip) -> Result<()> { // Patch the SVD prior to generating the package: patch_svd(workspace, chip)?; @@ -222,7 +256,10 @@ fn generate_package(workspace: &Path, chip: &Chip) -> Result<()> { _ => IdentFormats::default_theme(), }; ident_formats.insert("enum_name".into(), IdentFormat::default().constant_case()); - ident_formats.insert("enum_read_name".into(), IdentFormat::default().constant_case()); + ident_formats.insert( + "enum_read_name".into(), + IdentFormat::default().constant_case(), + ); ident_formats.insert("enum_value".into(), IdentFormat::default().pascal_case()); ident_formats.extend(config.ident_formats.drain()); config.ident_formats = ident_formats;