From 14dc5d40a52f7efac07393d0a53623fc231f8f77 Mon Sep 17 00:00:00 2001
From: malsheimer <michael.alsheimer@solectrix.de>
Date: Thu, 20 Apr 2023 23:43:51 +0200
Subject: [PATCH] tied PSLVERR output to low ('0' - no error) in APB2LB
 template

---
 corsair/templates/apb2lb_vhdl.j2 | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/corsair/templates/apb2lb_vhdl.j2 b/corsair/templates/apb2lb_vhdl.j2
index 79b6e19..d61d926 100644
--- a/corsair/templates/apb2lb_vhdl.j2
+++ b/corsair/templates/apb2lb_vhdl.j2
@@ -59,7 +59,7 @@ begin
 {% macro apb_core() %}
 -- APB interface
 prdata  <= rdata;
-pslverr <= '1'; -- always OKAY
+pslverr <= '0'; -- always OKAY
 pready  <= wready when (psel='1' and penable='1' and pwrite='1') else
            rvalid when (psel='1' and pwrite='0' and penable='1') else
            '1';