Prove that generated Verilog/VHDL is equivalent

[esynr3z]

Single source is used for any HDL generation, but Verilog and VHDL modules stored as different jinja templates. This is quite error prone, because always during any fix/enhancement both types of templates has to be changed.

Need to formally prove that all HDL generators for different languages always produce equivalent RTL output. This can be done with eqy from Yosys toolchain.

Additional benefit of this is that formal verification is a free synthesis check, which is also important for every produced HDL.