From 153c3b015f53c15bbf659f281e0db25602412665 Mon Sep 17 00:00:00 2001 From: Dmitry Murzinov Date: Tue, 5 Mar 2024 19:35:56 +0400 Subject: [PATCH 1/4] Add asciidoc template name support --- corsair/__main__.py | 2 +- corsair/generators.py | 7 +++++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/corsair/__main__.py b/corsair/__main__.py index 3ab6c45..1335dcb 100755 --- a/corsair/__main__.py +++ b/corsair/__main__.py @@ -81,7 +81,7 @@ def generate_templates(format): targets.update(corsair.generators.Python(path="sw/regs.py").make_target('py')) targets.update(corsair.generators.CHeader(path="sw/regs.h").make_target('c_header')) targets.update(corsair.generators.Markdown(path="doc/regs.md", image_dir="md_img").make_target('md_doc')) - targets.update(corsair.generators.Asciidoc(path="doc/regs.adoc", image_dir="adoc_img").make_target('asciidoc_doc')) + targets.update(corsair.generators.Asciidoc(template="regmap_asciidoc.j2",path="doc/regs.adoc", image_dir="adoc_img").make_target('asciidoc_doc')) # create templates if format == 'txt': diff --git a/corsair/generators.py b/corsair/generators.py index 339b488..09b1b3f 100755 --- a/corsair/generators.py +++ b/corsair/generators.py @@ -539,6 +539,8 @@ class Asciidoc(Generator, Jinja2, Wavedrom): :param rmap: Register map object :type rmap: :class:`corsair.RegisterMap` + :param template: Name of template file + :type template: str :param path: Path to the output file :type path: str :param title: Document title @@ -551,9 +553,10 @@ class Asciidoc(Generator, Jinja2, Wavedrom): :type print_conventions: bool """ - def __init__(self, rmap=None, path='regs.adoc', title='Register map', + def __init__(self, rmap=None, template='regmap_asciidoc.j2', path='regs.adoc', title='Register map', print_images=True, image_dir="regs_img", print_conventions=True, **args): super().__init__(rmap, **args) + self.template = template self.path = path self.title = title self.print_images = print_images @@ -565,7 +568,7 @@ def generate(self): # validate parameters self.validate() # prepare jinja2 - j2_template = 'regmap_asciidoc.j2' + j2_template = self.template j2_vars = {} j2_vars['corsair_ver'] = __version__ j2_vars['rmap'] = self.rmap From 45cabf3035c103c7236b5080ad4ae00a6759804b Mon Sep 17 00:00:00 2001 From: Dmitry Murzinov Date: Tue, 5 Mar 2024 19:49:37 +0400 Subject: [PATCH 2/4] Add verilog template name support --- corsair/__main__.py | 2 +- corsair/generators.py | 7 +++++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/corsair/__main__.py b/corsair/__main__.py index 1335dcb..3297ed6 100755 --- a/corsair/__main__.py +++ b/corsair/__main__.py @@ -74,7 +74,7 @@ def generate_templates(format): # targets targets = {} - targets.update(corsair.generators.Verilog(path="hw/regs.v").make_target('v_module')) + targets.update(corsair.generators.Verilog(template="regmap_verilog.j2",path="hw/regs.v").make_target('v_module')) targets.update(corsair.generators.Vhdl(path="hw/regs.vhd").make_target('vhdl_module')) targets.update(corsair.generators.VerilogHeader(path="hw/regs.vh").make_target('v_header')) targets.update(corsair.generators.SystemVerilogPackage(path="hw/regs_pkg.sv").make_target('sv_pkg')) diff --git a/corsair/generators.py b/corsair/generators.py index 09b1b3f..779d987 100755 --- a/corsair/generators.py +++ b/corsair/generators.py @@ -235,6 +235,8 @@ class Verilog(Generator, Jinja2): :param rmap: Register map object :type rmap: :class:`corsair.RegisterMap` + :param template: Name of template file + :type template: str :param path: Path to the output file :type path: str :param read_filler: Numeric value to return if wrong address was read @@ -243,8 +245,9 @@ class Verilog(Generator, Jinja2): :type interface: str """ - def __init__(self, rmap=None, path='regs.v', read_filler=0, interface='axil', **args): + def __init__(self, rmap=None, template='regmap_verilog.j2', path='regs.v', read_filler=0, interface='axil', **args): super().__init__(rmap, **args) + self.template = template self.path = path self.read_filler = read_filler self.interface = interface @@ -258,7 +261,7 @@ def generate(self): # validate parameters self.validate() # prepare jinja2 - j2_template = 'regmap_verilog.j2' + j2_template = self.template j2_vars = {} j2_vars['corsair_ver'] = __version__ j2_vars['rmap'] = self.rmap From ead65e6420290c5b2dd38c545b5ea516c3500169 Mon Sep 17 00:00:00 2001 From: Dmitry Murzinov Date: Tue, 5 Mar 2024 20:03:15 +0400 Subject: [PATCH 3/4] Update docs for PR 55 and 56 --- docs/config.rst | 55 ++++++++++++++++++++++++++----------------------- 1 file changed, 29 insertions(+), 26 deletions(-) diff --git a/docs/config.rst b/docs/config.rst index ceddc31..5b5f830 100755 --- a/docs/config.rst +++ b/docs/config.rst @@ -186,23 +186,25 @@ Parameter Default Description Verilog ------- -+-----------------+------------+-----------------------------------------------------+ -| Parameter | Default | Description | -+=================+============+=====================================================+ -| ``path`` | ``regs.v`` | Path to the output file | -+-----------------+------------+-----------------------------------------------------+ -| ``read_filler`` | 0 | Numeric value to return if wrong address was read | -+-----------------+------------+-----------------------------------------------------+ -| ``interface`` | ``axil`` | Register map bus protocol | -| | +-----------+-----------------------------------------+ -| | | ``axil`` | AXI4-Lite | -| | +-----------+-----------------------------------------+ -| | | ``amm`` | Avalon-MM | -| | +-----------+-----------------------------------------+ -| | | ``apb`` | APB4 | -| | +-----------+-----------------------------------------+ -| | | ``lb`` | Custom LocalBus interface | -+-----------------+------------+-----------+-----------------------------------------+ ++-----------------+-----------------------+-----------------------------------------------------+ +| Parameter | Default | Description | ++=================+=======================+=====================================================+ +| ``path`` | ``regs.v`` | Path to the output file | ++-----------------+-----------------------+-----------------------------------------------------+ +| ``read_filler`` | 0 | Numeric value to return if wrong address was read | ++-----------------+-----------------------+-----------------------------------------------------+ +| ``interface`` | ``axil`` | Register map bus protocol | +| | +-----------+-----------------------------------------+ +| | | ``axil`` | AXI4-Lite | +| | +-----------+-----------------------------------------+ +| | | ``amm`` | Avalon-MM | +| | +-----------+-----------------------------------------+ +| | | ``apb`` | APB4 | +| | +-----------+-----------------------------------------+ +| | | ``lb`` | Custom LocalBus interface | ++-----------------+-----------------------+-----------+-----------------------------------------+ +| ``template`` | ``regmap_verilog.j2`` | Template name | ++-----------------+-----------------------+-----------------------------------------------------+ Vhdl ---- @@ -265,15 +267,16 @@ Parameter Default Description Asciidoc -------- -===================== ================ ================================================================ -Parameter Default Description -===================== ================ ================================================================ -``path`` ``regs.md`` Path to the output file -``title`` ``Register map`` Document title -``print_images`` ``True`` Enable generating images for bit fields of a register -``image_dir`` ``regs_img`` Path to directory where all images will be saved -``print_conventions`` ``True`` Enable generating table with register access modes explained -===================== ================ ================================================================ +===================== ====================== ================================================================ +Parameter Default Description +===================== ====================== ================================================================ +``path`` ``regs.md`` Path to the output file +``title`` ``Register map`` Document title +``print_images`` ``True`` Enable generating images for bit fields of a register +``image_dir`` ``regs_img`` Path to directory where all images will be saved +``print_conventions`` ``True`` Enable generating table with register access modes explained +``template`` ``regmap_asciidoc.j2`` Template name +===================== ====================== ================================================================ Python ------ From 893555cce0532d153da73c6fd7bb44e5ca5937d3 Mon Sep 17 00:00:00 2001 From: Dmitry Murzinov Date: Tue, 5 Mar 2024 20:12:13 +0400 Subject: [PATCH 4/4] Fix pep8speaksfor PR57 --- corsair/__main__.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/corsair/__main__.py b/corsair/__main__.py index 3297ed6..c6eb561 100755 --- a/corsair/__main__.py +++ b/corsair/__main__.py @@ -74,14 +74,15 @@ def generate_templates(format): # targets targets = {} - targets.update(corsair.generators.Verilog(template="regmap_verilog.j2",path="hw/regs.v").make_target('v_module')) + targets.update(corsair.generators.Verilog(template="regmap_verilog.j2", path="hw/regs.v").make_target('v_module')) targets.update(corsair.generators.Vhdl(path="hw/regs.vhd").make_target('vhdl_module')) targets.update(corsair.generators.VerilogHeader(path="hw/regs.vh").make_target('v_header')) targets.update(corsair.generators.SystemVerilogPackage(path="hw/regs_pkg.sv").make_target('sv_pkg')) targets.update(corsair.generators.Python(path="sw/regs.py").make_target('py')) targets.update(corsair.generators.CHeader(path="sw/regs.h").make_target('c_header')) targets.update(corsair.generators.Markdown(path="doc/regs.md", image_dir="md_img").make_target('md_doc')) - targets.update(corsair.generators.Asciidoc(template="regmap_asciidoc.j2",path="doc/regs.adoc", image_dir="adoc_img").make_target('asciidoc_doc')) + targets.update(corsair.generators.Asciidoc(template="regmap_asciidoc.j2", path="doc/regs.adoc", + image_dir="adoc_img").make_target('asciidoc_doc')) # create templates if format == 'txt':