Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Docs update for PR#55 PR#56 #57

Open
wants to merge 4 commits into
base: master
Choose a base branch
from
Open

Docs update for PR#55 PR#56 #57

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
4 commits
Select commit Hold shift + click to select a range
153c3b0
Add asciidoc template name support
iDoka Mar 5, 2024
45cabf3
Add verilog template name support
iDoka Mar 5, 2024
ead65e6
Update docs for PR 55 and 56
iDoka Mar 5, 2024
893555c
Fix pep8speaksfor PR57
iDoka Mar 5, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
5 changes: 3 additions & 2 deletions corsair/__main__.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -74,14 +74,15 @@ def generate_templates(format):

# targets
targets = {}
targets.update(corsair.generators.Verilog(path="hw/regs.v").make_target('v_module'))
targets.update(corsair.generators.Verilog(template="regmap_verilog.j2", path="hw/regs.v").make_target('v_module'))
targets.update(corsair.generators.Vhdl(path="hw/regs.vhd").make_target('vhdl_module'))
targets.update(corsair.generators.VerilogHeader(path="hw/regs.vh").make_target('v_header'))
targets.update(corsair.generators.SystemVerilogPackage(path="hw/regs_pkg.sv").make_target('sv_pkg'))
targets.update(corsair.generators.Python(path="sw/regs.py").make_target('py'))
targets.update(corsair.generators.CHeader(path="sw/regs.h").make_target('c_header'))
targets.update(corsair.generators.Markdown(path="doc/regs.md", image_dir="md_img").make_target('md_doc'))
targets.update(corsair.generators.Asciidoc(path="doc/regs.adoc", image_dir="adoc_img").make_target('asciidoc_doc'))
targets.update(corsair.generators.Asciidoc(template="regmap_asciidoc.j2", path="doc/regs.adoc",
image_dir="adoc_img").make_target('asciidoc_doc'))

# create templates
if format == 'txt':
Expand Down
14 changes: 10 additions & 4 deletions corsair/generators.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -235,6 +235,8 @@ class Verilog(Generator, Jinja2):

:param rmap: Register map object
:type rmap: :class:`corsair.RegisterMap`
:param template: Name of template file
:type template: str
:param path: Path to the output file
:type path: str
:param read_filler: Numeric value to return if wrong address was read
Expand All @@ -243,8 +245,9 @@ class Verilog(Generator, Jinja2):
:type interface: str
"""

def __init__(self, rmap=None, path='regs.v', read_filler=0, interface='axil', **args):
def __init__(self, rmap=None, template='regmap_verilog.j2', path='regs.v', read_filler=0, interface='axil', **args):
super().__init__(rmap, **args)
self.template = template
self.path = path
self.read_filler = read_filler
self.interface = interface
Expand All @@ -258,7 +261,7 @@ def generate(self):
# validate parameters
self.validate()
# prepare jinja2
j2_template = 'regmap_verilog.j2'
j2_template = self.template
j2_vars = {}
j2_vars['corsair_ver'] = __version__
j2_vars['rmap'] = self.rmap
Expand Down Expand Up @@ -539,6 +542,8 @@ class Asciidoc(Generator, Jinja2, Wavedrom):

:param rmap: Register map object
:type rmap: :class:`corsair.RegisterMap`
:param template: Name of template file
:type template: str
:param path: Path to the output file
:type path: str
:param title: Document title
Expand All @@ -551,9 +556,10 @@ class Asciidoc(Generator, Jinja2, Wavedrom):
:type print_conventions: bool
"""

def __init__(self, rmap=None, path='regs.adoc', title='Register map',
def __init__(self, rmap=None, template='regmap_asciidoc.j2', path='regs.adoc', title='Register map',
print_images=True, image_dir="regs_img", print_conventions=True, **args):
super().__init__(rmap, **args)
self.template = template
self.path = path
self.title = title
self.print_images = print_images
Expand All @@ -565,7 +571,7 @@ def generate(self):
# validate parameters
self.validate()
# prepare jinja2
j2_template = 'regmap_asciidoc.j2'
j2_template = self.template
j2_vars = {}
j2_vars['corsair_ver'] = __version__
j2_vars['rmap'] = self.rmap
Expand Down
55 changes: 29 additions & 26 deletions docs/config.rst
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -186,23 +186,25 @@ Parameter Default Description

Verilog
-------
+-----------------+------------+-----------------------------------------------------+
| Parameter | Default | Description |
+=================+============+=====================================================+
| ``path`` | ``regs.v`` | Path to the output file |
+-----------------+------------+-----------------------------------------------------+
| ``read_filler`` | 0 | Numeric value to return if wrong address was read |
+-----------------+------------+-----------------------------------------------------+
| ``interface`` | ``axil`` | Register map bus protocol |
| | +-----------+-----------------------------------------+
| | | ``axil`` | AXI4-Lite |
| | +-----------+-----------------------------------------+
| | | ``amm`` | Avalon-MM |
| | +-----------+-----------------------------------------+
| | | ``apb`` | APB4 |
| | +-----------+-----------------------------------------+
| | | ``lb`` | Custom LocalBus interface |
+-----------------+------------+-----------+-----------------------------------------+
+-----------------+-----------------------+-----------------------------------------------------+
| Parameter | Default | Description |
+=================+=======================+=====================================================+
| ``path`` | ``regs.v`` | Path to the output file |
+-----------------+-----------------------+-----------------------------------------------------+
| ``read_filler`` | 0 | Numeric value to return if wrong address was read |
+-----------------+-----------------------+-----------------------------------------------------+
| ``interface`` | ``axil`` | Register map bus protocol |
| | +-----------+-----------------------------------------+
| | | ``axil`` | AXI4-Lite |
| | +-----------+-----------------------------------------+
| | | ``amm`` | Avalon-MM |
| | +-----------+-----------------------------------------+
| | | ``apb`` | APB4 |
| | +-----------+-----------------------------------------+
| | | ``lb`` | Custom LocalBus interface |
+-----------------+-----------------------+-----------+-----------------------------------------+
| ``template`` | ``regmap_verilog.j2`` | Template name |
+-----------------+-----------------------+-----------------------------------------------------+

Vhdl
----
Expand Down Expand Up @@ -265,15 +267,16 @@ Parameter Default Description

Asciidoc
--------
===================== ================ ================================================================
Parameter Default Description
===================== ================ ================================================================
``path`` ``regs.md`` Path to the output file
``title`` ``Register map`` Document title
``print_images`` ``True`` Enable generating images for bit fields of a register
``image_dir`` ``regs_img`` Path to directory where all images will be saved
``print_conventions`` ``True`` Enable generating table with register access modes explained
===================== ================ ================================================================
===================== ====================== ================================================================
Parameter Default Description
===================== ====================== ================================================================
``path`` ``regs.md`` Path to the output file
``title`` ``Register map`` Document title
``print_images`` ``True`` Enable generating images for bit fields of a register
``image_dir`` ``regs_img`` Path to directory where all images will be saved
``print_conventions`` ``True`` Enable generating table with register access modes explained
``template`` ``regmap_asciidoc.j2`` Template name
===================== ====================== ================================================================

Python
------
Expand Down