From e10cbf3cb2b6d9803ff783dcd5aeaf06eb1192b2 Mon Sep 17 00:00:00 2001 From: benjjuk Date: Thu, 29 Aug 2024 13:43:36 +0100 Subject: [PATCH] Bugfix Verilog header template The Verilog header generation was using the register address instead of the bitfield mask, meaning that the *_MASK constants were not usable. --- corsair/templates/verilog_header.j2 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/corsair/templates/verilog_header.j2 b/corsair/templates/verilog_header.j2 index b27f40f..df13a72 100755 --- a/corsair/templates/verilog_header.j2 +++ b/corsair/templates/verilog_header.j2 @@ -29,7 +29,7 @@ // {{ reg.name }}.{{ bf.name }} - {{ bf.description }} `define {{ module_prefix()|upper }}{{ reg.name.upper() }}_{{ bf.name.upper() }}_WIDTH {{ bf.width }} `define {{ module_prefix()|upper }}{{ reg.name.upper() }}_{{ bf.name.upper() }}_LSB {{ bf.lsb }} -`define {{ module_prefix()|upper }}{{ reg.name.upper() }}_{{ bf.name.upper() }}_MASK {{ "%d'h%x" % (config['data_width'], reg.address) }} +`define {{ module_prefix()|upper }}{{ reg.name.upper() }}_{{ bf.name.upper() }}_MASK {{ "%d'h%x" % (config['data_width'], bf.mask) }} `define {{ module_prefix()|upper }}{{ reg.name.upper() }}_{{ bf.name.upper() }}_RESET {{ "%d'h%x" % (bf.width, bf.reset) }} {% for enum in bf %} `define {{ module_prefix()|upper }}{{ reg.name.upper() }}_{{ bf.name.upper() }}_{{ enum.name.upper() }} {{ "%d'h%x" % (bf.width, enum.value) }} //{{ enum.description }} @@ -38,4 +38,4 @@ {% endfor %} {% endfor %} -`endif // __{{ file_name.upper() }}_VH \ No newline at end of file +`endif // __{{ file_name.upper() }}_VH