From 02a77b1be9b35e654054424a0263d19d5e13c2f3 Mon Sep 17 00:00:00 2001
From: Martijn Bastiaan <martijn@qbaylogic.com>
Date: Sun, 21 Jul 2024 08:22:31 +0200
Subject: [PATCH 01/16] Add `pyproject.toml` (PEP 518)

---
 pyproject.toml | 3 +++
 1 file changed, 3 insertions(+)
 create mode 100644 pyproject.toml

diff --git a/pyproject.toml b/pyproject.toml
new file mode 100644
index 0000000..28a13ef
--- /dev/null
+++ b/pyproject.toml
@@ -0,0 +1,3 @@
+[build-system]
+requires = ["setuptools", "GitPython"]
+build-backend = "setuptools.build_meta"

From 500bb32854a1efcfe6de50f356a88c92c5503c0d Mon Sep 17 00:00:00 2001
From: Martijn Bastiaan <martijn@qbaylogic.com>
Date: Sun, 21 Jul 2024 08:23:18 +0200
Subject: [PATCH 02/16] Allow source only installations

Previously, `pip install corsair --no-binary :all:` would fail due to
`setup.py` critically relying on `.git` being present. This patch will
detect a missing `.git` and assume a PyPI/source installation.
---
 setup.py | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/setup.py b/setup.py
index 6d1d42c..c5bb056 100644
--- a/setup.py
+++ b/setup.py
@@ -8,7 +8,13 @@
 def git_version(version):
     """Return version with local version identifier."""
     import git
-    repo = git.Repo('.git')
+
+    try:
+        repo = git.Repo('.git')
+    except git.NoSuchPathError:
+        # Not in a git repo, assume install through PyPI / source distribution
+        return version
+
     repo.git.status()
     # assert versions are increasing
     latest_tag = repo.git.describe(

From ef26877de762c9dcb64b84f4ead6e1c67a3a9236 Mon Sep 17 00:00:00 2001
From: Aleksander Los <Losiek@users.noreply.github.com>
Date: Wed, 24 Jul 2024 14:29:11 +0200
Subject: [PATCH 03/16] Fix the error that occurs when there are no tags
 present in the repository (#1)

---
 setup.py | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/setup.py b/setup.py
index c5bb056..a602c7a 100644
--- a/setup.py
+++ b/setup.py
@@ -17,8 +17,12 @@ def git_version(version):
 
     repo.git.status()
     # assert versions are increasing
-    latest_tag = repo.git.describe(
-        match='v[0-9]*', tags=True, abbrev=0)
+    try:
+        latest_tag = repo.git.describe(
+            match='v[0-9]*', tags=True, abbrev=0)
+    except git.exc.GitCommandError:
+        # No tags found
+        latest_tag = version
     assert parse_version(latest_tag) <= parse_version(version), (
         latest_tag, version)
     sha = repo.head.commit.hexsha[:8]

From a7f46682a81d218ca39b32ea210eb4595d0e8b28 Mon Sep 17 00:00:00 2001
From: ST de Feber <st.de.feber@gmail.com>
Date: Fri, 27 Sep 2024 13:37:51 +0200
Subject: [PATCH 04/16] Fixed Avavlon reads

The CoCoTb Avalon master driver and corsair do not agree with one and
other.

The driver removes the addres one a read pulse has been asserted (1
clock cycle) while the hdl of corsair expects it to remain stable for at
least one more cycle.
This has been fixed by clocking in the address at a read pulse and use
that for the read process.
---
 corsair/templates/amm2lb_verilog.j2 | 7 +++++++
 corsair/templates/amm2lb_vhdl.j2    | 9 ++++++++-
 corsair/templates/regmap_verilog.j2 | 2 +-
 corsair/templates/regmap_vhdl.j2    | 4 ++--
 4 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/corsair/templates/amm2lb_verilog.j2 b/corsair/templates/amm2lb_verilog.j2
index e0dd6e1..c81fbe1 100755
--- a/corsair/templates/amm2lb_verilog.j2
+++ b/corsair/templates/amm2lb_verilog.j2
@@ -78,6 +78,13 @@ wire              ren;
     end
   end
 
+  reg {{ range_decl(config['data_width'] - 1) }} raddr_int;
+  {{ always_begin(sig='raddr_int', width=config['data_width'], init=read_filler
+  )}} if (read) begin
+        raddr_int <= address;
+      end
+  end
+
   assign ren = ren_int;
 {% endmacro %}
 {{ amm_core() }}
diff --git a/corsair/templates/amm2lb_vhdl.j2 b/corsair/templates/amm2lb_vhdl.j2
index 32fc58d..49cf2bd 100644
--- a/corsair/templates/amm2lb_vhdl.j2
+++ b/corsair/templates/amm2lb_vhdl.j2
@@ -95,6 +95,7 @@ signal raddr  : std_logic_vector(ADDR_W-1 downto 0);
 signal ren    : std_logic;
     {% endif %}
 signal ren_int   : std_logic;
+signal raddr_int : std_logic_vector(ADDR_W-1 downto 0);
 {% endmacro %}
 {{ amm_signals() }}
 begin
@@ -120,8 +121,14 @@ wstrb <= byteenable;
     end if;
 {{ process_end() }}
 
+{{ process_begin("raddr_int", "(others => '0')") }}
+    if (read = '1') then
+        raddr_int <= address;
+    end if;
+{{ process_end() }}
+
 ren <= ren_int;
 
 {% endmacro %}
 {{ amm_core() }}
-end arch_imp;
\ No newline at end of file
+end arch_imp;
diff --git a/corsair/templates/regmap_verilog.j2 b/corsair/templates/regmap_verilog.j2
index 559754f..98fe8e0 100755
--- a/corsair/templates/regmap_verilog.j2
+++ b/corsair/templates/regmap_verilog.j2
@@ -422,7 +422,7 @@ assign wready = 1'b1;
 reg {{ range_decl(config['data_width'] - 1) }} rdata_ff;
 {{ always_begin(sig='rdata_ff', width=config['data_width'], init=read_filler
 )}} if (ren) begin
-        case (raddr)
+        case (raddr_int)
 {% for reg in rmap %}
             {{ literal(reg.address, config['address_width']) }}: rdata_ff <= {{ sig_csr_rdata(reg) }};
 {% endfor %}
diff --git a/corsair/templates/regmap_vhdl.j2 b/corsair/templates/regmap_vhdl.j2
index 642c4dd..f0dc131 100644
--- a/corsair/templates/regmap_vhdl.j2
+++ b/corsair/templates/regmap_vhdl.j2
@@ -532,10 +532,10 @@ wready <= '1';
 {% set loop_ns = namespace(first_reg = True) %}
 {% for reg in rmap %}
     {% if loop_ns.first_reg %}
-        if raddr = {{ literal(reg.address, "ADDR_W", width_is_param=1)}} then {{ literal_comment(reg.address) }}
+        if raddr_int = {{ literal(reg.address, "ADDR_W", width_is_param=1)}} then {{ literal_comment(reg.address) }}
             rdata_ff <= {{ sig_csr_rdata(reg) }};
     {% else %}
-        elsif raddr = {{ literal(reg.address, "ADDR_W", width_is_param=1)}} then {{ literal_comment(reg.address) }}
+        elsif raddr_int = {{ literal(reg.address, "ADDR_W", width_is_param=1)}} then {{ literal_comment(reg.address) }}
             rdata_ff <= {{ sig_csr_rdata(reg) }};
     {% endif %}
     {% set loop_ns.first_reg = False %}

From ed562e090c985b9d5778ec4482e4aaf490f44112 Mon Sep 17 00:00:00 2001
From: ST de Feber <st.de.feber@gmail.com>
Date: Fri, 27 Sep 2024 15:26:15 +0200
Subject: [PATCH 05/16] Fixed reset value in of radd_int in j2 file

---
 corsair/templates/amm2lb_verilog.j2 | 69 ++++++++++++++++++++++++++++-
 corsair/templates/regmap_verilog.j2 | 18 ++++++++
 corsair/templates/regmap_vhdl.j2    | 25 +++++++++++
 3 files changed, 110 insertions(+), 2 deletions(-)

diff --git a/corsair/templates/amm2lb_verilog.j2 b/corsair/templates/amm2lb_verilog.j2
index c81fbe1..2292636 100755
--- a/corsair/templates/amm2lb_verilog.j2
+++ b/corsair/templates/amm2lb_verilog.j2
@@ -3,6 +3,71 @@
 // Avalon-MM to Local Bus bridge
 //
 
+{# MACRO #}
+{#- vector range for select operations #}
+{% macro range(msb, lsb, is_vector=true) %}
+    {% if is_vector %}
+        {% if msb == lsb %}
+[{{ msb }}]
+        {%- else %}
+[{{ msb }}:{{ lsb }}]
+        {%- endif %}
+    {%- endif %}
+{%- endmacro %}
+{#- literal #}
+{% macro literal(val, width=1) %}
+    {% if width == 1 %}
+1'b{{ val }}
+    {%- else %}
+{{ width}}'h{{ '%x' % val }}
+    {%- endif %}
+{%- endmacro %}
+
+{#- special literal for all zeros #}
+{% macro zeros(width=1) %}
+    {% if width == 1 %}
+1'b0
+    {%- else %}
+{{ width }}'h0
+    {%- endif %}
+{%- endmacro %}
+
+{#- special literal for all ones #}
+{% macro ones(width=1) %}
+    {% if width == 1 %}
+1'b1
+    {%- else %}
+{{ "{%d{1'b1}}" % width }}
+    {%- endif %}
+{%- endmacro %}
+
+{% macro range_decl(msb, is_vector=true) %}
+    {% if is_vector %}
+[{{ msb }}:0]
+    {%- endif %}
+{%- endmacro %}
+
+{#- 'always' header with reset logic #}
+{% macro always_begin(sig='', width=1, init=0) %}
+    {% set rst_type = config['register_reset']%}
+    {% if rst_type == 'sync_pos' %}
+always @(posedge clk) begin
+    if (rst) begin
+    {% elif rst_type == 'sync_neg' %}
+always @(posedge clk) begin
+    if (!rst) begin
+    {% elif rst_type == 'async_pos' %}
+always @(posedge clk or posedge rst) begin
+    if (rst) begin
+    {% elif rst_type == 'async_neg' %}
+always @(posedge clk or negedge rst) begin
+    if (!rst) begin
+    {% endif %}
+        {{ sig }} <= {{ literal(init, width) }};
+    end else
+{%- endmacro %}
+
+
 module {{ module_name }} #(
     parameter ADDR_W = {{ config['address_width'] }},
     parameter DATA_W = {{ config['data_width'] }},
@@ -78,8 +143,8 @@ wire              ren;
     end
   end
 
-  reg {{ range_decl(config['data_width'] - 1) }} raddr_int;
-  {{ always_begin(sig='raddr_int', width=config['data_width'], init=read_filler
+  reg {{ range_decl(config['address_width'] - 1) }} raddr_int;
+  {{ always_begin(sig='raddr_int', width=config['address_width'], init=0
   )}} if (read) begin
         raddr_int <= address;
       end
diff --git a/corsair/templates/regmap_verilog.j2 b/corsair/templates/regmap_verilog.j2
index 98fe8e0..ff009d4 100755
--- a/corsair/templates/regmap_verilog.j2
+++ b/corsair/templates/regmap_verilog.j2
@@ -420,6 +420,8 @@ assign wready = 1'b1;
 // Read address decoder
 //------------------------------------------------------------------------------
 reg {{ range_decl(config['data_width'] - 1) }} rdata_ff;
+
+{% if interface == 'amm' %}
 {{ always_begin(sig='rdata_ff', width=config['data_width'], init=read_filler
 )}} if (ren) begin
         case (raddr_int)
@@ -432,6 +434,22 @@ reg {{ range_decl(config['data_width'] - 1) }} rdata_ff;
         rdata_ff <= {{ literal(read_filler, config['data_width']) }};
     end
 end
+{% else %}
+{{ always_begin(sig='rdata_ff', width=config['data_width'], init=read_filler
+)}} if (ren) begin
+        case (raddr)
+{% for reg in rmap %}
+            {{ literal(reg.address, config['address_width']) }}: rdata_ff <= {{ sig_csr_rdata(reg) }};
+{% endfor %}
+            default: rdata_ff <= {{ literal(read_filler, config['data_width']) }};
+        endcase
+    end else begin
+        rdata_ff <= {{ literal(read_filler, config['data_width']) }};
+    end
+end
+{% endif %}
+
+
 assign rdata = rdata_ff;
 
 //------------------------------------------------------------------------------
diff --git a/corsair/templates/regmap_vhdl.j2 b/corsair/templates/regmap_vhdl.j2
index f0dc131..0cffc94 100644
--- a/corsair/templates/regmap_vhdl.j2
+++ b/corsair/templates/regmap_vhdl.j2
@@ -527,6 +527,7 @@ wready <= '1';
 --------------------------------------------------------------------------------
 -- Read address decoder
 --------------------------------------------------------------------------------
+{% if interface == 'amm' %}
 {{ process_begin(sig='rdata_ff', width=config['data_width'], init=read_filler)}}
     if (ren = '1') then
 {% set loop_ns = namespace(first_reg = True) %}
@@ -547,6 +548,30 @@ wready <= '1';
         rdata_ff <= {{ literal(read_filler, config['data_width']) }}; {{ literal_comment(read_filler) }}
     end if;
 {{ process_end() }}
+{% else %}
+{{ process_begin(sig='rdata_ff', width=config['data_width'], init=read_filler)}}
+    if (ren = '1') then
+{% set loop_ns = namespace(first_reg = True) %}
+{% for reg in rmap %}
+    {% if loop_ns.first_reg %}
+        if raddr = {{ literal(reg.address, "ADDR_W", width_is_param=1)}} then {{ literal_comment(reg.address) }}
+            rdata_ff <= {{ sig_csr_rdata(reg) }};
+    {% else %}
+        elsif raddr = {{ literal(reg.address, "ADDR_W", width_is_param=1)}} then {{ literal_comment(reg.address) }}
+            rdata_ff <= {{ sig_csr_rdata(reg) }};
+    {% endif %}
+    {% set loop_ns.first_reg = False %}
+{% endfor %}
+        else 
+            rdata_ff <= {{ literal(read_filler, config['data_width']) }}; {{ literal_comment(read_filler) }}
+        end if;
+    else
+        rdata_ff <= {{ literal(read_filler, config['data_width']) }}; {{ literal_comment(read_filler) }}
+    end if;
+{{ process_end() }}
+
+{% endif %}
+
 rdata <= rdata_ff;
 
 --------------------------------------------------------------------------------

From 268172682bbd523d1ab96bb10ee1240ccb799587 Mon Sep 17 00:00:00 2001
From: stdefeber <st.de.feber@gmail.com>
Date: Thu, 3 Oct 2024 07:47:03 +0200
Subject: [PATCH 06/16] Added debug statement to find reason of failing test

---
 tests/hdl/test_rmap/tb_ro.sv | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/tests/hdl/test_rmap/tb_ro.sv b/tests/hdl/test_rmap/tb_ro.sv
index 6a82c09..5b6a8fc 100755
--- a/tests/hdl/test_rmap/tb_ro.sv
+++ b/tests/hdl/test_rmap/tb_ro.sv
@@ -4,7 +4,8 @@ module tb_ro;
 
 // Test environment with DUT and bridge to LocalBus
 `include "env.svh"
-
+`define DBG 1
+    
 // Test body
 int errors = 0;
 logic [ADDR_W-1:0] addr;
@@ -14,6 +15,8 @@ logic [STRB_W-1:0] strb;
 task test_ro_i;
     $display("%0t, Start RO+I tests!", $time);
     addr = CSR_REGRO_ADDR;
+    `ifdef DBG
+        $display("address %0x", addr)
     // read
     mst.read(addr, data);
     if (data[CSR_REGRO_BFI_LSB+:CSR_REGRO_BFI_WIDTH] != 0)

From b50d76ce3ca37cf16ff49cb80e2fac626f26850f Mon Sep 17 00:00:00 2001
From: stdefeber <st.de.feber@gmail.com>
Date: Thu, 3 Oct 2024 07:59:08 +0200
Subject: [PATCH 07/16] Fixed typo

---
 tests/hdl/test_rmap/tb_ro.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/hdl/test_rmap/tb_ro.sv b/tests/hdl/test_rmap/tb_ro.sv
index 5b6a8fc..9467728 100755
--- a/tests/hdl/test_rmap/tb_ro.sv
+++ b/tests/hdl/test_rmap/tb_ro.sv
@@ -16,7 +16,7 @@ task test_ro_i;
     $display("%0t, Start RO+I tests!", $time);
     addr = CSR_REGRO_ADDR;
     `ifdef DBG
-        $display("address %0x", addr)
+        $display("address %0x", addr);
     // read
     mst.read(addr, data);
     if (data[CSR_REGRO_BFI_LSB+:CSR_REGRO_BFI_WIDTH] != 0)

From bb40030fd9df8e881fb1efe5460a1f0aecd25485 Mon Sep 17 00:00:00 2001
From: stdefeber <st.de.feber@gmail.com>
Date: Thu, 3 Oct 2024 08:45:49 +0200
Subject: [PATCH 08/16] A ifdef needs a endif :(

---
 tests/hdl/test_rmap/tb_ro.sv | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tests/hdl/test_rmap/tb_ro.sv b/tests/hdl/test_rmap/tb_ro.sv
index 9467728..dbf13c2 100755
--- a/tests/hdl/test_rmap/tb_ro.sv
+++ b/tests/hdl/test_rmap/tb_ro.sv
@@ -17,6 +17,7 @@ task test_ro_i;
     addr = CSR_REGRO_ADDR;
     `ifdef DBG
         $display("address %0x", addr);
+    `endif
     // read
     mst.read(addr, data);
     if (data[CSR_REGRO_BFI_LSB+:CSR_REGRO_BFI_WIDTH] != 0)

From 1a3fe114d203468991da250cb201577ddb7ebe9a Mon Sep 17 00:00:00 2001
From: stdefeber <st.de.feber@gmail.com>
Date: Thu, 3 Oct 2024 08:53:18 +0200
Subject: [PATCH 09/16] More debug statements

---
 tests/hdl/test_rmap/tb_ro.sv | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/tests/hdl/test_rmap/tb_ro.sv b/tests/hdl/test_rmap/tb_ro.sv
index dbf13c2..bbe60a2 100755
--- a/tests/hdl/test_rmap/tb_ro.sv
+++ b/tests/hdl/test_rmap/tb_ro.sv
@@ -21,20 +21,29 @@ task test_ro_i;
     // read
     mst.read(addr, data);
     if (data[CSR_REGRO_BFI_LSB+:CSR_REGRO_BFI_WIDTH] != 0)
+    begin    
         errors++;
+        $display("%0t, Expected 0, got %0x", data);
+    end    
     // update hardware value
     @(posedge clk);
     csr_regro_bfi_in = 100;
     // read again
     mst.read(addr, data);
     if (data[CSR_REGRO_BFI_LSB+:CSR_REGRO_BFI_WIDTH] != 100)
+    begin    
         errors++;
+        $display("%0t, Expected 100, got %0x", data);
+    end    
     // write has no effect
     data = 200 << CSR_REGRO_BFI_LSB;
     mst.write(addr, data);
     mst.read(addr, data);
     if (data[CSR_REGRO_BFI_LSB+:CSR_REGRO_BFI_WIDTH] != 100)
+    begin
         errors++;
+        $display("%0t, Expected 100, got %0x", data);
+    end    
     $display("%0t, %0d errors", $time, errors);
 endtask
 

From b2cc6c732291c58d16a18581644f8c5ede785d47 Mon Sep 17 00:00:00 2001
From: stdefeber <st.de.feber@gmail.com>
Date: Thu, 3 Oct 2024 09:00:07 +0200
Subject: [PATCH 10/16] Forgot $time

---
 tests/hdl/test_rmap/tb_ro.sv | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/tests/hdl/test_rmap/tb_ro.sv b/tests/hdl/test_rmap/tb_ro.sv
index bbe60a2..e377cc6 100755
--- a/tests/hdl/test_rmap/tb_ro.sv
+++ b/tests/hdl/test_rmap/tb_ro.sv
@@ -23,7 +23,7 @@ task test_ro_i;
     if (data[CSR_REGRO_BFI_LSB+:CSR_REGRO_BFI_WIDTH] != 0)
     begin    
         errors++;
-        $display("%0t, Expected 0, got %0x", data);
+        $display("%0t, Expected 0, got %0x", $time, data);
     end    
     // update hardware value
     @(posedge clk);
@@ -33,7 +33,7 @@ task test_ro_i;
     if (data[CSR_REGRO_BFI_LSB+:CSR_REGRO_BFI_WIDTH] != 100)
     begin    
         errors++;
-        $display("%0t, Expected 100, got %0x", data);
+        $display("%0t, Expected 100, got %0x", $time, data);
     end    
     // write has no effect
     data = 200 << CSR_REGRO_BFI_LSB;
@@ -42,7 +42,7 @@ task test_ro_i;
     if (data[CSR_REGRO_BFI_LSB+:CSR_REGRO_BFI_WIDTH] != 100)
     begin
         errors++;
-        $display("%0t, Expected 100, got %0x", data);
+        $display("%0t, Expected 100, got %0x", $time, data);
     end    
     $display("%0t, %0d errors", $time, errors);
 endtask

From 8e230b8235269d3b96720c9c9c26b499b695723e Mon Sep 17 00:00:00 2001
From: stdefeber <st.de.feber@gmail.com>
Date: Thu, 3 Oct 2024 09:26:02 +0200
Subject: [PATCH 11/16] Archiving artifacts

---
 .github/workflows/test-on-push.yml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/.github/workflows/test-on-push.yml b/.github/workflows/test-on-push.yml
index ed7bae6..8845429 100644
--- a/.github/workflows/test-on-push.yml
+++ b/.github/workflows/test-on-push.yml
@@ -28,3 +28,10 @@ jobs:
     - name: Test package
       run: |
         pytest -v -n auto
+    - name: Archive build artifacts
+        uses: actions/upload-artifact@v4
+        with:
+          name: "debug"
+          path: |
+            /tmp
+          retention-days: 2

From 6c142e63ed7dad33aa29e45b1a78dced40a88a76 Mon Sep 17 00:00:00 2001
From: stdefeber <st.de.feber@gmail.com>
Date: Thu, 3 Oct 2024 09:32:48 +0200
Subject: [PATCH 12/16] Stroring artifacts p.2

---
 .github/workflows/test-on-push.yml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/test-on-push.yml b/.github/workflows/test-on-push.yml
index 8845429..ac75ae2 100644
--- a/.github/workflows/test-on-push.yml
+++ b/.github/workflows/test-on-push.yml
@@ -28,8 +28,8 @@ jobs:
     - name: Test package
       run: |
         pytest -v -n auto
-    - name: Archive build artifacts
-        uses: actions/upload-artifact@v4
+    - name: "Archive build artifacts"
+        uses: upload-artifact@v3.2.1-node20
         with:
           name: "debug"
           path: |

From 0c49575a666f48de4d236487bcbfae1785d18670 Mon Sep 17 00:00:00 2001
From: stdefeber <st.de.feber@gmail.com>
Date: Thu, 3 Oct 2024 09:36:26 +0200
Subject: [PATCH 13/16] Download artifact

---
 .github/workflows/test-on-push.yml | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/.github/workflows/test-on-push.yml b/.github/workflows/test-on-push.yml
index ac75ae2..96da846 100644
--- a/.github/workflows/test-on-push.yml
+++ b/.github/workflows/test-on-push.yml
@@ -28,10 +28,10 @@ jobs:
     - name: Test package
       run: |
         pytest -v -n auto
-    - name: "Archive build artifacts"
-        uses: upload-artifact@v3.2.1-node20
+    - name: Archive build artifacts
+        uses: actions/download-artifact@v4
         with:
           name: "debug"
-          path: |
+          path:
             /tmp
           retention-days: 2

From a1529728831993396f1605ed6c60ab6c0583f7e9 Mon Sep 17 00:00:00 2001
From: stdefeber <st.de.feber@gmail.com>
Date: Thu, 3 Oct 2024 09:40:33 +0200
Subject: [PATCH 14/16] Download artifacts p.3

---
 .github/workflows/test-on-push.yml | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/.github/workflows/test-on-push.yml b/.github/workflows/test-on-push.yml
index 96da846..7c488ef 100644
--- a/.github/workflows/test-on-push.yml
+++ b/.github/workflows/test-on-push.yml
@@ -28,10 +28,8 @@ jobs:
     - name: Test package
       run: |
         pytest -v -n auto
-    - name: Archive build artifacts
-        uses: actions/download-artifact@v4
+    - name: Upload build artifact
+        uses: actions/upload-artifact@v3
         with:
-          name: "debug"
-          path:
-            /tmp
-          retention-days: 2
+          name: build-output
+          path: build/output.txt

From 2bdb960e3d0f6e7f53fb938fe7a89d36b5bc2600 Mon Sep 17 00:00:00 2001
From: stdefeber <st.de.feber@gmail.com>
Date: Thu, 3 Oct 2024 09:46:47 +0200
Subject: [PATCH 15/16] Identation error

---
 .github/workflows/test-on-push.yml | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/.github/workflows/test-on-push.yml b/.github/workflows/test-on-push.yml
index 7c488ef..d67cf28 100644
--- a/.github/workflows/test-on-push.yml
+++ b/.github/workflows/test-on-push.yml
@@ -29,7 +29,7 @@ jobs:
       run: |
         pytest -v -n auto
     - name: Upload build artifact
-        uses: actions/upload-artifact@v3
-        with:
-          name: build-output
-          path: build/output.txt
+      uses: actions/upload-artifact@v3
+      with:
+        name: build-output
+        path: /tmp

From 4b5ee7a4a8d6332ddb34e21a24a9ace8a0d37ef4 Mon Sep 17 00:00:00 2001
From: stdefeber <st.de.feber@gmail.com>
Date: Thu, 3 Oct 2024 09:57:53 +0200
Subject: [PATCH 16/16] Making sure it uploads even if there is a failure

---
 .github/workflows/test-on-push.yml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/.github/workflows/test-on-push.yml b/.github/workflows/test-on-push.yml
index d67cf28..6bab4dd 100644
--- a/.github/workflows/test-on-push.yml
+++ b/.github/workflows/test-on-push.yml
@@ -29,7 +29,8 @@ jobs:
       run: |
         pytest -v -n auto
     - name: Upload build artifact
-      uses: actions/upload-artifact@v3
+      if: always()
+      uses: actions/upload-artifact@v4
       with:
         name: build-output
         path: /tmp