This is a small and delibaretly kept simple verilog project to be realised in a "rideshare" open source ASIC organised by Tiny Tapeout. The aim is to make the most simple project as a first step, however this can also work as a debugging tool if the internal arrangements are known.
16 inputs are chaotically hooked onto 8 logic gates driving the outputs. If the connections are known, one can very easily test and verify one's setup. If they are not known, one can play a guessing game of what gate is connected to which inputs. It can also be used as a small demonstration of how semiconductors work, for example at trade shows, open door days etc.
You will need the Tiny Tapeout 6 PCB. See the Tiny Tapeout documentation.
TinyTapeout is an educational project that aims to make it easier and cheaper than ever to get your digital designs manufactured on a real chip. Each run, one or more tiles can be bought on the overall chip and filled with custom designs.
To learn more and get started yourself, visit https://tinytapeout.com and/or Join the community.