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minor if statement fix in SPI_master.v docs #30: Commit 7d1e1e4 pushed by faramire
April 18, 2024 18:35 1m 11s main
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April 18, 2024 18:35 1m 11s
expanded SPI setup, updated SPI_master.v docs #29: Commit 6ad47f5 pushed by faramire
April 18, 2024 18:31 1m 8s main
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April 18, 2024 18:31 1m 8s
rewrote entire SPI code docs #28: Commit 9e11362 pushed by faramire
April 18, 2024 16:44 1m 10s main
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April 18, 2024 16:44 1m 10s
trying to pass gds 3 docs #27: Commit 1ce1fc1 pushed by faramire
April 17, 2024 14:30 1m 13s main
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April 17, 2024 14:30 1m 13s
removved multidriven output docs #26: Commit 0ee4610 pushed by faramire
April 17, 2024 04:21 1m 10s main
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April 17, 2024 04:21 1m 10s
trying to pass gds 2 docs #25: Commit b0a239a pushed by faramire
April 17, 2024 04:07 1m 33s main
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April 17, 2024 04:07 1m 33s
trying to pass gds 1 docs #24: Commit 34e0896 pushed by faramire
April 17, 2024 03:34 1m 11s main
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April 17, 2024 03:34 1m 11s
removing file listings docs #23: Commit b51a316 pushed by faramire
April 17, 2024 03:05 1m 6s main
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April 17, 2024 03:05 1m 6s
consolidated all verilog into one file docs #22: Commit e564806 pushed by faramire
April 17, 2024 03:01 23s main
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April 17, 2024 03:01 23s
pleasing yosys docs #21: Commit 9f3d635 pushed by faramire
April 17, 2024 02:53 1m 24s main
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April 17, 2024 02:53 1m 24s
hey, it's compiling! docs #20: Commit 3ba7bf3 pushed by faramire
April 17, 2024 02:22 1m 6s main
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April 17, 2024 02:22 1m 6s
first full SPI implementation attempt docs #19: Commit ef8d742 pushed by faramire
April 17, 2024 02:06 1m 39s main
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April 17, 2024 02:06 1m 39s
trying something new docs #18: Commit 4ac5fab pushed by faramire
April 17, 2024 00:03 1m 51s main
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April 17, 2024 00:03 1m 51s
some attempts at an SPI master docs #17: Commit 11a5cd4 pushed by faramire
April 11, 2024 22:22 1m 19s main
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April 11, 2024 22:22 1m 19s
cleanup docs #16: Commit ba7c0c2 pushed by faramire
April 5, 2024 00:51 1m 18s main
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April 5, 2024 00:51 1m 18s
missed a comma docs #15: Commit 6dae66b pushed by faramire
April 4, 2024 23:16 1m 7s main
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April 4, 2024 23:16 1m 7s
Added documentation and a separate reset docs #14: Commit 6d267c1 pushed by faramire
April 4, 2024 23:13 1m 39s main
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April 4, 2024 23:13 1m 39s
top module had slightly wrong name docs #13: Commit 2c6f077 pushed by faramire
April 4, 2024 22:49 1m 10s main
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April 4, 2024 22:49 1m 10s
switch from default file to own verilog, tests should now fail docs #12: Commit 3faf59a pushed by faramire
April 4, 2024 18:28 25s main
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April 4, 2024 18:28 25s
fixed counter enable chaining docs #11: Commit 272850e pushed by faramire
April 1, 2024 23:27 1m 33s main
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April 1, 2024 23:27 1m 33s
filled counter_chain.v, updated info.yaml, fixes here and there docs #10: Commit 098d969 pushed by faramire
April 1, 2024 23:02 1m 8s main
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April 1, 2024 23:02 1m 8s
major rewrites of nearly all modules docs #9: Commit fb0328e pushed by faramire
April 1, 2024 21:46 1m 56s main
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April 1, 2024 21:46 1m 56s
minor math errors fixed in clockdivider.v and counter10.v docs #8: Commit c66d9c0 pushed by faramire
April 1, 2024 19:38 1m 15s main
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April 1, 2024 19:38 1m 15s
fixed tb.v referencing the wrong top module docs #7: Commit 7b71fc1 pushed by faramire
March 4, 2024 11:03 1m 12s main
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March 4, 2024 11:03 1m 12s
Updated description in info.yaml docs #6: Commit 25678e9 pushed by faramire
March 4, 2024 11:01 1m 10s main
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March 4, 2024 11:01 1m 10s