From 19d867968f3e6f5a607bff92d2a6c3783a03e782 Mon Sep 17 00:00:00 2001 From: faramire Date: Fri, 19 Apr 2024 03:18:00 +0200 Subject: [PATCH] icestick bugfixes --- icestick/build.sh | 8 + icestick/clockDividerIce.v | 26 + icestick/icestick.pcf | 10 +- icestick/stopwatch.bin | Bin 0 -> 32220 bytes icestick/stopwatch.blif | 1725 +++++++++++ icestick/stopwatch.txt | 5659 ++++++++++++++++++++++++++++++++++++ icestick/tb_icestick.v | 40 +- 7 files changed, 7433 insertions(+), 35 deletions(-) create mode 100644 icestick/build.sh create mode 100644 icestick/clockDividerIce.v create mode 100644 icestick/stopwatch.bin create mode 100644 icestick/stopwatch.blif create mode 100644 icestick/stopwatch.txt diff --git a/icestick/build.sh b/icestick/build.sh new file mode 100644 index 0000000..44e5c41 --- /dev/null +++ b/icestick/build.sh @@ -0,0 +1,8 @@ + +yosys -p "synth_ice40 -blif stopwatch.blif" tb_icestick.v + +arachne-pnr -d 1k -p icestick.pcf stopwatch.blif -o stopwatch.txt + +icepack stopwatch.txt stopwatch.bin + +iceprog stopwatch.bin diff --git a/icestick/clockDividerIce.v b/icestick/clockDividerIce.v new file mode 100644 index 0000000..54ea953 --- /dev/null +++ b/icestick/clockDividerIce.v @@ -0,0 +1,26 @@ +module clockDividerIce ( + input wire clk_in, // input clock 12 MHz + input wire ena, + input wire res, // reset, active low + output reg clk_out // output clock 1 MHz +); + + reg[2:0] counter; + parameter div = 6; // 12 MHz / 12 = 1 MHz, 50% duty cycle => 1/2 of that + + + always @(posedge clk_in) begin + if (!res) begin // reset + counter <= 3'b0; + clk_out <= 1'b0; + end else if (ena) begin + if (counter < (div-1)) begin // count up + counter <= counter + 1; + end else begin // reset counter and invert output + counter <= 3'b0; + clk_out <= ~clk_out; + end + end + end + +endmodule //clockDividerIce diff --git a/icestick/icestick.pcf b/icestick/icestick.pcf index 260230c..b353439 100644 --- a/icestick/icestick.pcf +++ b/icestick/icestick.pcf @@ -1,10 +1,10 @@ set_io CLK_IN 21 -set_io o_stopwatch_enabled 95 -set_io o_display_enabled 96 -set_io o_mosi 97 -set_io o_cs 98 -set_io o_sck 99 +set_io l_stopwatch_enabled 95 +set_io l_display_enabled 96 +set_io l_mosi 97 +set_io l_cs 98 +set_io l_sck 99 set_io i_board_reset 119 set_io i_button_start_stop 118 diff --git a/icestick/stopwatch.bin b/icestick/stopwatch.bin new file mode 100644 index 0000000000000000000000000000000000000000..9bb0578aec6760fcca858d28abd37454a6ee1e55 GIT binary patch literal 32220 zcmeHP3y>VedH#E5Zg=mrciIytp*OA5Sz6;mtnG`0v4BP-sxy%CQC7@D#M;0`yd3I` zDHjR}^vRMzj#8Wi*usxwRSrdhlW@2a%2Yu-2LeNZEZK1q5fpoa%L0O9P8A4*P*MKB zXJ&UEJr6xN+1&oHJ^$nDzq|kbyQgP%Pe%Zb-1gvow_O6PZ71-n*hM$N*k*ukU<`Cr z&?%2kXB}U4U2W=RNoUaM^aFK!<$4iR(a-A~rRg*-D^4AuE=HPzYJl z^nq%65&0&c#<{U{VDXM+(9cLvJX%Q{ZG~Sk{0T~sV;dDewrZ_f{s(F;UAhMz2XSw-B5B^){tS7ors(xG6D9o`_Pfm^Vvg3X-{XbI(+zj=rZSP>Xp93yL`K zRFa4o+e7#SnpdJU%aw~}+D;@TAjB9QuOzqwCebQ5ZW?VHQkq8KYI0?;aY5HO!eh%~ zqc~KA#pO7Nt3L}M-}kJnyDJBmPy(Iux@KIdQE!B+jdb+0kY7y!<}{t$Tjyuru#Uqp5?#2TV(Q?JM9NN(|x=+oXH>F zD87&pDEjz|4+-fmjf6@a=ANGKOeO%Dre)^!*#>UfoqJ2odOD7~O7lOJOR2+ z^HLf3jlaAC8Lot+!gwNIlSzPv&07A8`$a=aV2rg}?;1(4qbVyw1-zedH9$r6;Xe{9U}$C#Ysc}c}gA^}cCznfqW8X-`6jaQg z^<8W(ckOd;3ChcvL91UH``Mj1;lfOt@y=0ID|hyWmxSVCi=moh>b#e`m|n5sGIkazFTZfhSQo(X>rWxpkkn5-4Z$j$9x&h=Lr}qi-=c?+ zgHKUjE`xXOX9l1w^+hkgwD{f4o-S~8qE`SmS#j7}!0Z#|E1rBI;gC{@i4*|tmkweM z{4Yybiv()S@i;Y1pK4rQ5*%R3W%mm_@emuEmt@2vtJ>AOSC zLeK%=1e5cI`{d-M0elii#M6g#s3%h_X?jkdOm_!hv$b7!HEzPmHOl2=yKAk3@ulW{ zy-`KGD|3z~vkb(B*7{vas-hboHc~FlRAz#x1Jc}?=PN!~2!QizS@RN8-CsL)^Ui%W z)AXP(^FKPWL>&)|=hW)55hVAj}Z4^x&lgcmn zc?+!JlJE3Sd8#L27}7rMAFj{?0g4kgMQY=;t3A zK|LyTR9IpINVrwm*4@FHVdp-04a~kDqM{8j%R9g*H(`kK#)T|(SGhc^?Lh#+*4m{Y z)JA|yVqmn_?BF!OM}AY1rkx56VFz;UOY9*u4R2NUIF}rtX9q7xtZ=akUB7~B z3jo!~r-s?6X)Uyf8X)bxC8?Ap~rX%y74ap$7Snu?_%F(;MF zn-ivoT$X^1tJQ-;_PJD>@TBMWD%ekK!7_1FJrK-Gd{aELq>x?EKa5`_p9PnXRdC?u zH8SYZb4OPL+v5^n4%RW)MmaX*0KZ?y0O3Nr5es-Ca33elw4#{2oSGQ$scGgUwSwE# zuPceup32ts-0bb^vLRtXMwf8vW9zKA{W4=)#|*2gnmn~WTO(324xlF^E~`Ismk~=F z;S`X3BG5>4&!1-p3@|tLbp4IcTKQ=uSQB^k4~wvh+Di82Ft3%yIH+j%T8$PJ*;g84DM^fHFLROyhAdM>~h z4GXJK#UCC?NXbk06$t+5BALv=5}yAnom^mE+6mY~`4jydTixCFD84^V$V)H=Rcf|# zA@RjY0`c-ieP~9P4=4P}!*!7JIpRLv&obec=K6&QZ&db2bb7_olu(Cj6`m9-0AYPp z-o7lV(`mS)lsa2L=gu}|l$P3*_UjZ&_S*VgQVUYb0|d#dmy#L8xmk-qn8W5@0Y@*Ggd_kWfft#m} z|9LR+o3*5B%Z&+p^@`DY(-z;UpStQX-TaY-@0W|lAoa3x{wtS{N?%1kd-|*k zDKGoBVJ~yAV#U2=)a9kI({g`toCB+1+;PPVf8qDz<2z;z`lO!z37?eA?y%9$<1iFa zoE{82v~7z6Z69b_q{04mL^~LKlpC}K4cw*DL$=2zU)gKVZQ7pqqxR^Ck`*X5;C zkl275(XoDG#eMZ{R z>J5$B-V9nrA6)xv{1@I0JjT6a&Wrd<)GXA!Z!(ihqvO0Q=Zz4cUYxO`-b!>IMheLg~Lfo-lTRqEuJ70WVm zrJ@LV2#aMnNA?1uei^nzWOF~M%=U{@CZ_-&Rdp*5VB{5-R9FCmm>M?zmrOJ#7RdQ{ zI=dwvS+ahjj9vDAOiOegOY*mDWjpBmy@4LQ@Xzkyn3#7TnES&Cr;Z-i&h|ZdwZJvr z-;PH(tP(?bYuNfPg8H^*{Uvq`$WgQ6!vi$%;;E8W8L@gY<`#GLV5*x;#Qi3tQE}fF zhXG_|q5BTGp${>JRiapO!+2+&BnCe*#M*4?9M`>m#wxzOpm+dJM9}e->poXULlR9; z@)#fgiA(~atz;h{#Nfye*mxqeRHU0O{?>gN9;LES$9b2<{{>6Kfxt9dddL}Lx7mD( zrujk=sys0Tcic$2a4K*bRe9_M_L4d(l08Uej?cbkZFj2iflLwkcB@IHi24vppHR3b zDNYb~LA$Y)r1JbLK3kzbo5j>+F?yx8lZ-)|*%0ggAh^75i8OEpXPBH61xY3Er7}v) zPV8m0!nD%(!#(8#=TqL|`=>$OqR@{{>eav6+F$Ry%sx5pZk;|Eotgi^k5Y#HPQoAI zkIU0rMZ`rDA`?!5O5S;fvxS!>jSbJqwyI&k?n}qh8mJ$nr#Rz`6?jS(u4MEN`t(uO9Rg-@E1 z!~%S^*ATsFFz>mcB=O4e6Q&P&(_>x(P6hfB+#y39!wRoKKO2dG>$^UBI zKjJG|{X34;+QgX-Ts>8h$;YP=feL>(V;1uW(2?ezYk*0!>Trex2`PW_c*2) zN$MqGXWqWFihsaAuwrzVs;Ua!WZ!#Ez<^zn85SLfFWxLOe9_mBea1%snc8(cHt~E< zop4^dMC(XYtppJ@gf*1wI7L}WBJfDPG>#XJpG4v_pHA5lrLTU?$46LqMUoz0O(c@_ zy;TBFhpZD5B$>9I~X#q+jCm(yc4#YU8&nl9((c;y|=jI{yNb zpxXuHYgEQk-Udsm`A*4A^uY0hv_+^(Lg9>;Cr*!?OmEO>;*+LS`z1*UX{6kty@G?@$a_yR8HMUbH{(Hb?X?bz8rqDG(QjN3{+DT)1lExnhj z{tXA!KcbT%psVim@;<5ItTuPF`om?@$yR4)FILsN)}}tpmCC;}0);$&mp|iAaQ$S6 zW!QsO&M9s1v{4Cdvg~{~^3QTLRE%>4!kgBmbaPY0olBv#;?2IiFyUK=>Zp;9R$m?- zP63?uCi}8hcLrqN0FEQA+3vXtIF>wQ`o4xd7T)zJ>h+23)i>M!`Ow@keKl0f70Gvl6nR85KHDfd*cpDTa2v_sH0O7XN{ z<3@qsi@oveXgo$)SWgedXvT)Z*8-#Qs*N}d#$@(KUM9Z(XMZYiSj5IqVWGwG)Hrc_ zMdGfGA3YU7ZhP$zmO7RC~Zp5pO*-yl|Ru*eh&#TlEcf>bjk z9onyg^KJs!4Vy6u{M882qE-Z25tvpH*bK6@4NR*UZw zK 1/2 of that + assign l_mosi = o_mosi; + assign l_cs = o_cs; + assign l_sck = o_sck; + assign l_stopwatch_enabled = o_stopwatch_enabled; + assign l_display_enabled = o_display_enabled; - - always @(posedge clk_in) begin - if (!res) begin // reset - counter <= 3'b0; - clk_out <= 1'b0; - end else if (ena) begin - if (counter < (div-1)) begin // count up - counter <= counter + 1; - end else begin // reset counter and invert output - counter <= 3'b0; - clk_out <= ~clk_out; - end - end - end - -endmodule //clockDividerIce +endmodule // ice_stopwatch