From aef4e0cd0e83eada7bbcaf292afea802ee65f060 Mon Sep 17 00:00:00 2001 From: faramire Date: Fri, 19 Apr 2024 18:59:44 +0200 Subject: [PATCH] added debug outputs to the icestick version --- icestick/icestick.pcf | 8 ++++-- icestick/stopwatch_top_icestick.v | 42 ++++++++++++++++++++++--------- icestick/tb_icestick.v | 9 +++++-- src/stopwatch_top.v | 28 ++++++++++++++------- 4 files changed, 62 insertions(+), 25 deletions(-) diff --git a/icestick/icestick.pcf b/icestick/icestick.pcf index b353439..a6e3aff 100644 --- a/icestick/icestick.pcf +++ b/icestick/icestick.pcf @@ -14,5 +14,9 @@ set_io i_button_reset 116 set_io o_mosi 114 set_io o_cs 113 set_io o_sck 112 -set_io o_stopwatch_enabled 44 -set_io o_display_enabled 45 +set_io o_stopwatch_enabled 48 +set_io o_display_enabled 56 + +set_io state0 44 +set_io state1 45 +set_io state2 47 diff --git a/icestick/stopwatch_top_icestick.v b/icestick/stopwatch_top_icestick.v index 717f2ed..eff4293 100644 --- a/icestick/stopwatch_top_icestick.v +++ b/icestick/stopwatch_top_icestick.v @@ -13,7 +13,9 @@ module tt_um_faramire_stopwatch ( output wire [7:0] uio_oe, // IOs: Enable path (active high: 0=input, 1=output) input wire ena, // will go high when the design is enabled input wire clk, // clock - input wire rst_n // reset_n - low to reset + input wire rst_n, // reset_n - low to reset + + output wire [2:0] state_wrapper ); // All output pins must be assigned. If not used, assign to 0. assign uio_out = 0; @@ -82,7 +84,9 @@ module tt_um_faramire_stopwatch ( .ces_0X (w_ces_0X), .Mosi (uo_out[0]), // MOSI on out 0 .Cs (uo_out[1]), // CS on out 1 - .Clk_SPI (uo_out[2]) // CLK on out 3 + .Clk_SPI (uo_out[2]), // CLK on out 3 + + .state_wrapper(state_wrapper) ); endmodule // tt_um_faramire_stopwatch @@ -286,7 +290,9 @@ module SPI_wrapper ( output wire Mosi, output reg Cs, - output wire Clk_SPI + output wire Clk_SPI, + + output wire [2:0] state_wrapper ); // FSM @@ -300,12 +306,15 @@ module SPI_wrapper ( reg [15:0] word_out; reg [2:0] digit_count; + reg [4:0] wait_count; wire send_reported; wire ready_reported; reg reset_master; reg sent_ON; reg sent_BCD; + assign state_wrapper = state; + always @(posedge clk) begin // controlling FSM if (!res) begin // active low reset Cs <= 1; @@ -338,6 +347,7 @@ module SPI_wrapper ( if (ready_reported == 1) begin word_out <= 16'b0000_1001_1111_1111; // address = decode mode, data = BCD for all digit_count <= 3'b000; + wait_count <= 5'b0; Cs <= 0; sent_BCD <= 1; end @@ -348,19 +358,22 @@ module SPI_wrapper ( end // SETUP IDLE: begin - if (clk_div & ena) begin // wait for the 100Hz clock to get high + if (clk_div & ena & ready_reported) begin // wait for the 100Hz clock to get high digit_count <= 3'b000; + wait_count <= 5'b0; state <= TRANSFER; + wait_count <= 5'b00000; end end // IDLE TRANSFER: begin - if (ready_reported == 1) begin // wait for TX ready + //if (ready_reported == 1) begin // wait for TX ready case(digit_count) 3'b000: begin // ces_0X word_out <= {8'b0000_0001, 8'b0000_0000 | {4'b0000, ces_0X}}; // send the 16-bit word Cs <= 0; // pull CS low to initiate send + wait_count <= 5'b0; digit_count <= 3'b001; // advance the position counter state <= WAIT; end @@ -368,6 +381,7 @@ module SPI_wrapper ( 3'b001: begin // ces_X0 word_out <= {8'b0000_0010, 8'b0000_0000 | {4'b0000, ces_X0}}; Cs <= 0; + wait_count <= 5'b0; digit_count <= 3'b010; state <= WAIT; end @@ -375,6 +389,7 @@ module SPI_wrapper ( 3'b010: begin // sec_0X word_out <= {8'b0000_0011, 8'b1000_0000 | {4'b0000, sec_0X}}; Cs <= 0; + wait_count <= 5'b0; digit_count <= 3'b011; state <= WAIT; end @@ -382,6 +397,7 @@ module SPI_wrapper ( 3'b011: begin // sec_X0 word_out <= {8'b0000_0100, 8'b0000_0000 | {5'b00000, sec_X0}}; Cs <= 0; + wait_count <= 5'b0; digit_count <= 3'b100; state <= WAIT; end @@ -389,6 +405,7 @@ module SPI_wrapper ( 3'b100: begin // min_0X word_out <= {8'b0000_0101, 8'b1000_0000 | {4'b0000, min_0X}}; Cs <= 0; + wait_count <= 5'b0; digit_count <= 3'b101; state <= WAIT; end @@ -396,26 +413,27 @@ module SPI_wrapper ( 3'b101: begin // min_X0 word_out <= {8'b0000_0110, 8'b0000_0000 | {5'b00000, min_X0}}; Cs <= 0; + wait_count <= 5'b0; digit_count <= 3'b110; state <= WAIT; end 3'b110: begin // once send has been complete and CS is high again, switch state + //wait_count <= 5'b0; state <= DONE; end default:digit_count <= 3'b000; endcase - - end else if (send_reported == 1) begin // once data has been send, pull CS high - Cs <= 1; - end + //end end // TRANSFER WAIT: begin - if (send_reported == 1) begin - Cs <= 1; - state <= TRANSFER; + if (ready_reported == 1) begin + if (wait_count == 5'b11111) begin + state <= TRANSFER; + end + wait_count <= wait_count + 1; end end diff --git a/icestick/tb_icestick.v b/icestick/tb_icestick.v index 67c501f..663dc99 100644 --- a/icestick/tb_icestick.v +++ b/icestick/tb_icestick.v @@ -24,7 +24,11 @@ module ice_stopwatch( output wire l_cs, output wire l_sck, output wire l_stopwatch_enabled, - output wire l_display_enabled + output wire l_display_enabled, + + output wire state0, + output wire state1, + output wire state2 ); wire clk_tt; @@ -49,7 +53,8 @@ module ice_stopwatch( .uio_oe(), .ena(1'b1), .clk(clk_tt), - .rst_n(i_board_reset) + .rst_n(i_board_reset), + .state_wrapper({state0, state1, state2}) ); assign l_mosi = o_mosi; diff --git a/src/stopwatch_top.v b/src/stopwatch_top.v index 717f2ed..59701e5 100644 --- a/src/stopwatch_top.v +++ b/src/stopwatch_top.v @@ -300,6 +300,7 @@ module SPI_wrapper ( reg [15:0] word_out; reg [2:0] digit_count; + reg [4:0] wait_count; wire send_reported; wire ready_reported; reg reset_master; @@ -324,6 +325,7 @@ module SPI_wrapper ( if (ready_reported == 1) begin word_out <= 16'b0000_1100_0000_0001; // address = shutdown mode, data = device on digit_count <= 3'b000; + wait_count <= 5'b0; Cs <= 0; sent_ON <= 1; end @@ -338,6 +340,7 @@ module SPI_wrapper ( if (ready_reported == 1) begin word_out <= 16'b0000_1001_1111_1111; // address = decode mode, data = BCD for all digit_count <= 3'b000; + wait_count <= 5'b0; Cs <= 0; sent_BCD <= 1; end @@ -348,19 +351,21 @@ module SPI_wrapper ( end // SETUP IDLE: begin - if (clk_div & ena) begin // wait for the 100Hz clock to get high + if (clk_div & ena & ready_reported) begin // wait for the 100Hz clock to get high digit_count <= 3'b000; + wait_count <= 5'b0; state <= TRANSFER; end end // IDLE TRANSFER: begin - if (ready_reported == 1) begin // wait for TX ready + //if (ready_reported == 1) begin // wait for TX ready case(digit_count) 3'b000: begin // ces_0X word_out <= {8'b0000_0001, 8'b0000_0000 | {4'b0000, ces_0X}}; // send the 16-bit word Cs <= 0; // pull CS low to initiate send + wait_count <= 5'b0; digit_count <= 3'b001; // advance the position counter state <= WAIT; end @@ -368,6 +373,7 @@ module SPI_wrapper ( 3'b001: begin // ces_X0 word_out <= {8'b0000_0010, 8'b0000_0000 | {4'b0000, ces_X0}}; Cs <= 0; + wait_count <= 5'b0; digit_count <= 3'b010; state <= WAIT; end @@ -375,6 +381,7 @@ module SPI_wrapper ( 3'b010: begin // sec_0X word_out <= {8'b0000_0011, 8'b1000_0000 | {4'b0000, sec_0X}}; Cs <= 0; + wait_count <= 5'b0; digit_count <= 3'b011; state <= WAIT; end @@ -382,6 +389,7 @@ module SPI_wrapper ( 3'b011: begin // sec_X0 word_out <= {8'b0000_0100, 8'b0000_0000 | {5'b00000, sec_X0}}; Cs <= 0; + wait_count <= 5'b0; digit_count <= 3'b100; state <= WAIT; end @@ -389,6 +397,7 @@ module SPI_wrapper ( 3'b100: begin // min_0X word_out <= {8'b0000_0101, 8'b1000_0000 | {4'b0000, min_0X}}; Cs <= 0; + wait_count <= 5'b0; digit_count <= 3'b101; state <= WAIT; end @@ -396,26 +405,27 @@ module SPI_wrapper ( 3'b101: begin // min_X0 word_out <= {8'b0000_0110, 8'b0000_0000 | {5'b00000, min_X0}}; Cs <= 0; + wait_count <= 5'b0; digit_count <= 3'b110; state <= WAIT; end 3'b110: begin // once send has been complete and CS is high again, switch state + //wait_count <= 5'b0; state <= DONE; end default:digit_count <= 3'b000; endcase - - end else if (send_reported == 1) begin // once data has been send, pull CS high - Cs <= 1; - end + //end end // TRANSFER WAIT: begin - if (send_reported == 1) begin - Cs <= 1; - state <= TRANSFER; + if (ready_reported == 1) begin + if (wait_count == 5'b11111) begin + state <= TRANSFER; + end + wait_count <= wait_count + 1; end end