diff --git a/hls4ml/backends/vivado_accelerator/supported_boards.json b/hls4ml/backends/vivado_accelerator/supported_boards.json index 1279ec22d..0b597762c 100644 --- a/hls4ml/backends/vivado_accelerator/supported_boards.json +++ b/hls4ml/backends/vivado_accelerator/supported_boards.json @@ -11,6 +11,12 @@ "python_drivers": {"axi_stream": "axi_stream_driver.py"}, "c_drivers": {} }, + "vcu128": { + "part": "xcvu37p-fsvh2892-2L-e", + "tcl_scripts": {"axi_master": "axi_master_design.tcl"}, + "python_drivers": {}, + "c_drivers": { "axi_master": "axi_master_design.c"} + }, "alveo-u50": { "part": "xcu50-fsvh2104-2-e", "tcl_scripts": {"axi_stream": "axi_stream_design.tcl"}, diff --git a/hls4ml/templates/vivado_accelerator/vcu128/Readme.md b/hls4ml/templates/vivado_accelerator/vcu128/Readme.md new file mode 100755 index 000000000..d371e06bf --- /dev/null +++ b/hls4ml/templates/vivado_accelerator/vcu128/Readme.md @@ -0,0 +1 @@ +Branch for adding VCU128 board support to hls4ml. Added and tested with Vivado 2019.1 diff --git a/hls4ml/templates/vivado_accelerator/vcu128/c_drivers/sdk/Makefile b/hls4ml/templates/vivado_accelerator/vcu128/c_drivers/sdk/Makefile new file mode 100755 index 000000000..03ab9b8de --- /dev/null +++ b/hls4ml/templates/vivado_accelerator/vcu128/c_drivers/sdk/Makefile @@ -0,0 +1,33 @@ +DESIGN := design_1 + +help: + @echo "INFO: make to show targets" +.PHONY: help + +--setup: + xsct ./setup.tcl $(DESIGN) +.PHONY: --setup + +sdk: --setup + rm -f $(DESIGN)_standalone/src/helloworld.c + cd $(DESIGN)_standalone/src && ln -s ../../common/main.c main.c + cd $(DESIGN)_standalone/src && ln -s ../../common/data.h data.h +.PHONY: sdk + +gui: + xsdk --workspace . & +.PHONY: gui + +clean: + rm -rf $(DESIGN)_platform + rm -rf $(DESIGN)_standalone + rm -rf $(DESIGN)_standalone_bsp + rm -rf RemoteSystemsTempFiles + rm -rf .Xil + rm -rf .metadata + rm -f *.log +.PHONY: clean + +ultraclean: clean + rm -rf hdf/*.hdf +.PHONY: ultraclean diff --git a/hls4ml/templates/vivado_accelerator/vcu128/c_drivers/sdk/common/main.c b/hls4ml/templates/vivado_accelerator/vcu128/c_drivers/sdk/common/main.c new file mode 100755 index 000000000..84e3aa3d0 --- /dev/null +++ b/hls4ml/templates/vivado_accelerator/vcu128/c_drivers/sdk/common/main.c @@ -0,0 +1,350 @@ +/** + * + * Set Heap Size in ldscript.ld to 0x1000000 (16MB) + * + */ + +#include "xmyproject_axi.h" /* TODO: design-dependent name */ +#include "stdio.h" /* PRINTF */ +#include "unistd.h" /* sleep */ +#include "stdlib.h" +#include "malloc.h" +#include "assert.h" +#include "xil_io.h" /* peripheral read/write wrappers */ +#include "platform.h" /* platform init/cleanup functions */ +#include "xil_cache.h" /* enable/disable caches etc */ +#include "xil_printf.h" /* UART debug print functions */ +#include "xparameters.h" /* peripherals base addresses */ +#include "xtmrctr.h" /* timer, Xilinx IP Timer Counter */ + +#include "data.h" + +/*#define EEMBC_POWER 1 + +#ifdef EEMBC_POWER +#include "xgpio.h" /* AXI GPIO drivers */ + +/*#define PIN 0x01 +#define GPIO_PMOD_PIN_DEVICE_ID XPAR_GPIO_0_DEVICE_ID + +#define set_pin_high(InstancePtr, Mask) \ + XGpio_DiscreteWrite(InstancePtr, 1, Mask) + +#define set_pin_low(InstancePtr, Mask) \ + XGpio_DiscreteClear(InstancePtr, 1, Mask) + +XGpio Gpio; +#endif +*/ + +//#define __DEBUG__ + +#define MAX_PRINT_ELEMENTS (16) + +#define PRINTF printf + +const unsigned INPUT_N_ELEMENTS = N_SAMPLES * N_X_INPUTS; +const unsigned OUTPUT_N_ELEMENTS = N_SAMPLES * N_Y_OUTPUTS; + +#if 1 +/* Accelerator verification */ +#define REFERENCE_OUTPUTS data_y_hls_outputs +#else +/* Accelerator validation */ +#define REFERENCE_OUTPUTS data_y_outputs +//#define REFERENCE_OUTPUTS data_y_keras_outputs +#endif + +unsigned get_max(float *data, unsigned n_elements) { + float max_value = 0.0; + unsigned max_index = 0; + for (unsigned i = 0; i < n_elements; i++) + if (data[i] >= max_value) { + max_index = i; + max_value = data[i]; + } + return max_index; +} + +float *inputs_mem = NULL; +float *outputs_mem = NULL; +float *reference_mem = NULL; + +/* Accelerator configuration */ +XMyproject_axi accelerator; /* TODO: design-dependent name */ +XMyproject_axi_Config *accelerator_cfg; /* TODO: design-dependent name */ + +/* Accelerator initialization routine */ +void init_accelerators() { + PRINTF("INFO: Initializing accelerator\r\n"); + accelerator_cfg = XMyproject_axi_LookupConfig(XPAR_MYPROJECT_AXI_0_DEVICE_ID); /* TODO: design-dependent name */ + if (accelerator_cfg) { + int status = XMyproject_axi_CfgInitialize(&accelerator, accelerator_cfg); /* TODO: design-dependent name */ + if (status != XST_SUCCESS) { + PRINTF("ERROR: Initializing accelerator\r\n"); + } + } +} + +/* Reference implementation of the accelerator in software */ +int sw_reference_implementation(float *sw_inputs_mem, float *sw_outputs_mem, unsigned n_samples, unsigned n_X_inputs, unsigned n_y_ouputs) { +#ifdef __DEBUG__ + PRINTF("INFO: Reference outputs are pre-compiled. It would be nice to run a software model here.\r\n"); +#endif + /* See data.h for inputs and outputs */ + for (unsigned i = 0; i < n_samples * n_y_ouputs; i++) { + sw_outputs_mem[i] = REFERENCE_OUTPUTS[i]; + } + return 0; +} + +/* Profiling utilities */ +static XTmrCtr TimerCounterInst; +#define TMRCTR_DEVICE_ID XPAR_TMRCTR_0_DEVICE_ID +#define TIMER_CNTR_0 0 +#define TIMER_CNTR_1 1 + +void start_64b_counter() { + XTmrCtr_Start(&TimerCounterInst, TIMER_CNTR_0); + XTmrCtr_Start(&TimerCounterInst, TIMER_CNTR_1); +} + +void stop_64b_counter() { + XTmrCtr_Stop(&TimerCounterInst, TIMER_CNTR_0); + XTmrCtr_Stop(&TimerCounterInst, TIMER_CNTR_1); +} + +u64 get_64b_counter_value() { + //printf("bytes %u\n\r", sizeof(u64)); + u64 lo_counter = XTmrCtr_GetValue(&TimerCounterInst, TIMER_CNTR_0); + u64 hi_counter = XTmrCtr_GetValue(&TimerCounterInst, TIMER_CNTR_1); + u64 counter = (hi_counter << 32) | lo_counter; + //printf("INFO: hi = %lu, lo = %lu, total = %lu\n\r", hi_counter, lo_counter, counter); + return counter; +} + +#if 0 +double get_elapsed_time(u64 clk_start, u64 clk_stop) { + return ((clk_stop-clk_start) * (1.0/XPAR_AXI_TIMER_MCU_CLOCK_FREQ_HZ)); +} +#endif + +float get_elapsed_time_ns(u64 clks) { + return clks * 1000000000.0/XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ; +} + + +/* Dump data to the console */ +void dump_data(const char* label, float* data, unsigned n_samples, unsigned feature_count) { + PRINTF("INFO: %s[%u][%u]:\r\n", label, n_samples, feature_count); + /* Print at most MAX_PRINT_ELEMENTS */ + for (unsigned i = 0; i < n_samples && i < MAX_PRINT_ELEMENTS; i++) { + PRINTF("INFO: [%u] ", i); + for (unsigned j = 0; j < feature_count; j++) { + unsigned index = i * feature_count + j; + PRINTF("%f ", data[index]); + } + PRINTF("\r\n"); + } +} + +/* The top of the hill :-) */ +int main(int argc, char** argv) { + + int status; + u64 calibration_time; + double __attribute__ ((unused)) sw_elapsed = 0; + u64 hw_elapsed = 0; + u64 cache_elapsed = 0; + unsigned hw_errors; + + char __attribute__ ((unused)) dummy; /* dummy input */ + + /* Initialize platform (uart and caches) */ + init_platform(); + + PRINTF("\r\n"); + PRINTF("INFO: ==================================================\r\n"); + PRINTF("INFO: XMyproject_axi (w/ polling)\r\n"); /* TODO: design-dependent name */ + PRINTF("INFO: ==================================================\r\n"); + + init_accelerators(); + + /* Timer Counter */ + status = XTmrCtr_Initialize(&TimerCounterInst, TMRCTR_DEVICE_ID); + if (status != XST_SUCCESS){ + print("ERROR: Timer counter initialization failed \r\n"); + return status; + } + + XTmrCtr_SetOptions(&TimerCounterInst, TIMER_CNTR_0, + XTC_AUTO_RELOAD_OPTION | + XTC_CASCADE_MODE_OPTION); + + print("INFO: Timer counter initialized\r\n"); + + inputs_mem = malloc(INPUT_N_ELEMENTS * sizeof(float)); + outputs_mem = malloc(OUTPUT_N_ELEMENTS * sizeof(float)); + reference_mem = malloc(OUTPUT_N_ELEMENTS * sizeof(float)); + + /* Calibration */ + start_64b_counter(); + sleep(1); + stop_64b_counter(); + calibration_time = get_64b_counter_value(); + PRINTF("INFO: Time calibration for one second (%lf sec, %llu clk)\r\n", get_elapsed_time_ns(calibration_time), calibration_time); + + /* Initialize memory */ + PRINTF("INFO: Initialize memory\r\n"); + PRINTF("INFO: - Samples count: %u\r\n", N_SAMPLES); /* Same as dst_SAMPLE_COUNT */ + PRINTF("INFO: - Inputs count: %u\r\n", N_X_INPUTS); + PRINTF("INFO: - Outputs count: %u\r\n", N_Y_OUTPUTS); + PRINTF("INFO: - Data size: %u B\r\n", sizeof(float)); + PRINTF("INFO: - Total input size: %u B, %.2f KB, %.2f MB\r\n", N_X_INPUTS * N_SAMPLES * sizeof(float), (N_X_INPUTS * N_SAMPLES * sizeof(float)) / (float)1024, (N_X_INPUTS * N_SAMPLES * sizeof(float)) / (float)(1024*1024)); + PRINTF("INFO: - Total output size: %u B, %.2f KB, %.2f MB\r\n", N_Y_OUTPUTS * N_SAMPLES * sizeof(float), (N_Y_OUTPUTS * N_SAMPLES * sizeof(float)) / (float)1024, (N_Y_OUTPUTS * N_SAMPLES * sizeof(float)) / (float)(1024*1024)); + + // Set Heap Size in ldscript.ld to 0x1000000 (16MB) + //malloc_stats(); + + for (int i = 0; i < INPUT_N_ELEMENTS; i++) { + inputs_mem[i] = data_X_inputs[i]; + } + for (int i = 0; i < OUTPUT_N_ELEMENTS; i++) { + outputs_mem[i] = 0x0; + } + + /* ****** SW REFERENCE ****** */ + PRINTF("INFO: ==================================================\r\n"); + PRINTF("INFO: Start SW reference implementation\r\n"); + start_64b_counter(); + sw_reference_implementation(inputs_mem, reference_mem, N_SAMPLES, N_X_INPUTS, N_Y_OUTPUTS); + stop_64b_counter(); + sw_elapsed = get_64b_counter_value(); + PRINTF("INFO: ==================================================\r\n"); + PRINTF("INFO: Press any key to start:\r\n"); + dummy = inbyte(); + //PRINTF("INFO:"); + + /* ****** HW ACCELERATOR ****** */ + PRINTF("INFO: Start HW accelerator\r\n"); + start_64b_counter(); + Xil_DCacheFlushRange((UINTPTR)inputs_mem, INPUT_N_ELEMENTS * sizeof(float)); + Xil_DCacheFlushRange((UINTPTR)outputs_mem, OUTPUT_N_ELEMENTS * sizeof(float)); + Xil_DCacheFlushRange((UINTPTR)reference_mem, OUTPUT_N_ELEMENTS * sizeof(float)); + stop_64b_counter(); + cache_elapsed = get_64b_counter_value(); + + for (unsigned j = 0; j < N_SAMPLES; j++) { + float *inputs_mem_i = inputs_mem + j * N_X_INPUTS; + float *outputs_mem_i = outputs_mem + j * N_Y_OUTPUTS; + + /* Configure the accelerator */ + start_64b_counter(); + XMyproject_axi_Set_in_r(&accelerator, (unsigned)inputs_mem_i); /* TODO: design-dependent name */ + XMyproject_axi_Set_out_r(&accelerator, (unsigned)outputs_mem_i); /* TODO: design-dependent name */ + + XMyproject_axi_Start(&accelerator); /* TODO: design-dependent name */ + + /* Polling */ + while (!XMyproject_axi_IsDone(&accelerator)); /* TODO: design-dependent name */ + + /* Get error status */ + //hw_flags = XMyproject_axi_Get_return(&accelerator); /* TODO: design-dependent name */ + stop_64b_counter(); + hw_elapsed += get_64b_counter_value(); + } + + start_64b_counter(); + Xil_DCacheFlushRange((UINTPTR)outputs_mem, OUTPUT_N_ELEMENTS * sizeof(float)); + stop_64b_counter(); + cache_elapsed += get_64b_counter_value(); + + PRINTF("INFO: HW accelerator done!\r\n"); + + /* ****** VALIDATION ****** */ + PRINTF("INFO: ================== Verification ==================\r\n"); +#ifdef __DEBUG__ + PRINTF("INFO: Dump data\r\n"); + dump_data("inputs_mem", inputs_mem, N_SAMPLES, N_X_INPUTS); + dump_data("outputs_mem", outputs_mem, N_SAMPLES, N_Y_OUTPUTS); + dump_data("reference_mem", reference_mem, N_SAMPLES, N_Y_OUTPUTS); +#endif + +#ifdef __DEBUG__ + PRINTF("INFO: SW execution time: %f sec\r\n", sw_elapsed); +#endif + PRINTF("INFO: HW-acceleration exec. time (%d inferences):\r\n", N_SAMPLES); + PRINTF("INFO: - total %f sec\r\n", get_elapsed_time_ns(hw_elapsed)); + PRINTF("INFO: - per-inference %.12f sec (%f ns)\r\n", get_elapsed_time_ns(hw_elapsed) / (N_SAMPLES), (get_elapsed_time_ns(hw_elapsed)*1000.0) / (N_SAMPLES)); + PRINTF("INFO: Cache flush time: %f sec\r\n", get_elapsed_time_ns(cache_elapsed)); +#ifdef __DEBUG__ + PRINTF("INFO: HW/SW speedup (the software is fake so this does not count...): %.2f X\r\n", (sw_elapsed >= (hw_elapsed+cache_elapsed))?(sw_elapsed/(hw_elapsed+cache_elapsed)):-((hw_elapsed+cache_elapsed)/sw_elapsed)); +#endif + + hw_errors = 0; +#if 1 + /* Accelerator verification */ + for (int i = 0; i < OUTPUT_N_ELEMENTS; i++) { + if (outputs_mem[i] != reference_mem[i]) { + PRINTF("ERROR: [%d]: Accelerator HW %f != SW %f\r\n", i, outputs_mem[i], reference_mem[i]); + hw_errors++; + } + } + PRINTF("INFO: Total errors = %d (out of %d elements)\r\n", hw_errors, OUTPUT_N_ELEMENTS); + if (hw_errors > 0) + PRINTF("INFO: Verification: FAIL\r\n"); + else + PRINTF("INFO: Verification: PASS!\r\n"); +#else + /* Accelerator validation */ + for (unsigned s = 0; s < N_SAMPLES; s++) { + unsigned ref_digit = get_max(reference_mem + s * N_Y_OUTPUTS, N_Y_OUTPUTS); + unsigned hw_digit = get_max(outputs_mem + s * N_Y_OUTPUTS, N_Y_OUTPUTS); + if (hw_digit != ref_digit) { +#ifdef __DEBUG__ + PRINTF("ERROR: [%d]: Accelerator HW %u != SW %u\r\n", s, hw_digit, ref_digit); +#endif + hw_errors++; + } + } + float error_rate = (hw_errors / (float)(N_SAMPLES)) * 100.0; + float accuracy = 100 - ((hw_errors / (float)(N_SAMPLES)) * 100.0); + PRINTF("INFO: Total errors = %d (out of %d digits)\r\n", hw_errors, N_SAMPLES); + PRINTF("INFO: Error rate = %.2f %%\r\n", error_rate); + PRINTF("INFO: Accuracy = %.2f %%\r\n", accuracy); +#endif + + PRINTF("INFO: ==================================================\r\n"); + + +#ifdef EEMBC_POWER + /* Initialize the GPIO driver */ + status = XGpio_Initialize(&Gpio, GPIO_PMOD_PIN_DEVICE_ID); + if (status != XST_SUCCESS) { + xil_printf("GPIO Initialization Failed\r\n"); + return XST_FAILURE; + } + + set_pin_low(&Gpio, PIN); + + PRINTF("INFO: Connect logic analyzer to the pin 3 of Pmod D\r\n"); + PRINTF("INFO: Press any key to start:\r\n"); + dummy = inbyte(); + + /* Loop forever */ + for (unsigned i; i < 100; i++) { + set_pin_high(&Gpio, PIN); + + sleep(1); + + set_pin_low(&Gpio, PIN); + + sleep(1); + } +#endif + + cleanup_platform(); + + return 0; +} + diff --git a/hls4ml/templates/vivado_accelerator/vcu128/c_drivers/sdk/setup.tcl b/hls4ml/templates/vivado_accelerator/vcu128/c_drivers/sdk/setup.tcl new file mode 100755 index 000000000..383bf39cf --- /dev/null +++ b/hls4ml/templates/vivado_accelerator/vcu128/c_drivers/sdk/setup.tcl @@ -0,0 +1,14 @@ +# See +# https://www.xilinx.com/html_docs/xilinx2019_1/SDK_Doc/xsct/intro/xsct_introduction.html + +setws . +if { $::argc == 1 } { + set myproject [lindex $::argv 0] + createhw -name ${myproject}\_platform -hwspec ../hdf/${myproject}\_wrapper.hdf + createapp -name ${myproject}\_standalone -app {Hello World} -proc microblaze_mcu -hwproject ${myproject}\_platform -os standalone + configapp -app ${myproject}\_standalone build-config release + #configapp -app ${myproject}\_standalone -add linker-misc {-Wl,--defsym=_HEAP_SIZE=0x1000000} + #configapp -app ${myproject}\_standalone -add linker-misc {-Wl,--defsym=_STACK_SIZE=0x40000} + projects -build + #configapp -app ${myproject}\_standalone -add define-compiler-symbols {FLAG=VALUE} +} diff --git a/hls4ml/templates/vivado_accelerator/vcu128/tcl_scripts/axi_master_design.tcl b/hls4ml/templates/vivado_accelerator/vcu128/tcl_scripts/axi_master_design.tcl new file mode 100755 index 000000000..a0540bcb5 --- /dev/null +++ b/hls4ml/templates/vivado_accelerator/vcu128/tcl_scripts/axi_master_design.tcl @@ -0,0 +1,537 @@ + +################################################################ +# +# MIT License +# +# Copyright (c) 2022 University of Sherbrooke +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# The above copyright notice and this permission notice shall be included in all +# copies or substantial portions of the Software. +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# Author : Mehdi Rahimifar +# Last update : 2022-08-25 +# Description : This contains the tcl scripts to generate the right block design for VCU128 and the accelerator from hls4ml in Vivado +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + + + +set tcldir [file dirname [info script]] +source [file join $tcldir project.tcl] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source design_1_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + + + +set project_name "project_1" +set design_name "design_1" +set hls_solution_name "solution1" +#set acc_name "${myproject}_axi" +set part_name "xcvu37p-fsvh2892-2L-e" +set board_name "xilinx.com:vcu128:part0:1.0" + + + + + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 ${myproject}_vivado_accelerator -part xcvu37p-fsvh2892-2L-e -force + set_property BOARD_PART xilinx.com:vcu128:part0:1.0 [current_project] +} + + + + +# Setup IP repo +set_property ip_repo_paths ${myproject}_prj/${hls_solution_name}/impl/ip [current_project] +#set_property ip_repo_paths /home/subnugler/Desktop/MICROBLAZE_TEST/Microblaze/myproject_prj/${hls_solution_name}/impl/ip [current_project] +update_ip_catalog + + + + + + +#CHANGED HERE!!!!!!!!!!! + +# CHANGE DESIGN NAME HERE +#variable design_name +#set design_name design_1 + + + + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:smartconnect:1.0\ +xilinx.com:ip:axi_timer:2.0\ +xilinx.com:ip:axi_uart16550:2.0\ +xilinx.com:ip:clk_wiz:6.0\ +xilinx.com:ip:ddr4:2.2\ +xilinx.com:ip:mdm:3.2\ +xilinx.com:ip:microblaze:11.0\ +xilinx.com:hls:myproject_axi:1.0\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:lmb_bram_if_cntlr:4.0\ +xilinx.com:ip:lmb_v10:3.0\ +xilinx.com:ip:blk_mem_gen:8.4\ +" + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + +# Hierarchical cell: microblaze_0_local_memory +proc create_hier_cell_microblaze_0_local_memory { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_microblaze_0_local_memory() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 DLMB + + create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 ILMB + + + # Create pins + create_bd_pin -dir I -type clk LMB_Clk + create_bd_pin -dir I -type rst SYS_Rst + + # Create instance: dlmb_bram_if_cntlr, and set properties + set dlmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_bram_if_cntlr ] + set_property -dict [ list \ + CONFIG.C_ECC {0} \ + ] $dlmb_bram_if_cntlr + + # Create instance: dlmb_v10, and set properties + set dlmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb_v10 ] + + # Create instance: ilmb_bram_if_cntlr, and set properties + set ilmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_bram_if_cntlr ] + set_property -dict [ list \ + CONFIG.C_ECC {0} \ + ] $ilmb_bram_if_cntlr + + # Create instance: ilmb_v10, and set properties + set ilmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb_v10 ] + + # Create instance: lmb_bram, and set properties + set lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 lmb_bram ] + set_property -dict [ list \ + CONFIG.Memory_Type {True_Dual_Port_RAM} \ + CONFIG.use_bram_block {BRAM_Controller} \ + ] $lmb_bram + + # Create interface connections + connect_bd_intf_net -intf_net microblaze_0_dlmb [get_bd_intf_pins DLMB] [get_bd_intf_pins dlmb_v10/LMB_M] + connect_bd_intf_net -intf_net microblaze_0_dlmb_bus [get_bd_intf_pins dlmb_bram_if_cntlr/SLMB] [get_bd_intf_pins dlmb_v10/LMB_Sl_0] + connect_bd_intf_net -intf_net microblaze_0_dlmb_cntlr [get_bd_intf_pins dlmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTA] + connect_bd_intf_net -intf_net microblaze_0_ilmb [get_bd_intf_pins ILMB] [get_bd_intf_pins ilmb_v10/LMB_M] + connect_bd_intf_net -intf_net microblaze_0_ilmb_bus [get_bd_intf_pins ilmb_bram_if_cntlr/SLMB] [get_bd_intf_pins ilmb_v10/LMB_Sl_0] + connect_bd_intf_net -intf_net microblaze_0_ilmb_cntlr [get_bd_intf_pins ilmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTB] + + # Create port connections + connect_bd_net -net SYS_Rst_1 [get_bd_pins SYS_Rst] [get_bd_pins dlmb_bram_if_cntlr/LMB_Rst] [get_bd_pins dlmb_v10/SYS_Rst] [get_bd_pins ilmb_bram_if_cntlr/LMB_Rst] [get_bd_pins ilmb_v10/SYS_Rst] + connect_bd_net -net microblaze_0_Clk [get_bd_pins LMB_Clk] [get_bd_pins dlmb_bram_if_cntlr/LMB_Clk] [get_bd_pins dlmb_v10/LMB_Clk] [get_bd_pins ilmb_bram_if_cntlr/LMB_Clk] [get_bd_pins ilmb_v10/LMB_Clk] + + # Restore current instance + current_bd_instance $oldCurInst +} + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set ddr4_sdram [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_sdram ] + + set default_100mhz_clk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 default_100mhz_clk ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {100000000} \ + ] $default_100mhz_clk + + set rs232_uart_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 rs232_uart_0 ] + + + # Create ports + set dummy_port_in [ create_bd_port -dir I -type rst dummy_port_in ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $dummy_port_in + + # Create instance: axi_smc, and set properties + set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ] + set_property -dict [ list \ + CONFIG.NUM_CLKS {2} \ + CONFIG.NUM_SI {4} \ + ] $axi_smc + + # Create instance: axi_timer_0, and set properties + set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ] + + # Create instance: axi_uart16550_0, and set properties + set axi_uart16550_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uart16550:2.0 axi_uart16550_0 ] + set_property -dict [ list \ + CONFIG.UART_BOARD_INTERFACE {rs232_uart_0} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $axi_uart16550_0 + + # Create instance: clk_wiz_0, and set properties + set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ] + set_property -dict [ list \ + CONFIG.CLKOUT1_JITTER {166.057} \ + CONFIG.CLKOUT1_PHASE_ERROR {298.404} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125.000} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {125.000} \ + CONFIG.RESET_BOARD_INTERFACE {Custom} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $clk_wiz_0 + + # Create instance: ddr4_0, and set properties + set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ] + set_property -dict [ list \ + CONFIG.C0_CLOCK_BOARD_INTERFACE {default_100mhz_clk} \ + CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram} \ + CONFIG.RESET_BOARD_INTERFACE {dummy_port_in} \ + ] $ddr4_0 + + # Create instance: mdm_1, and set properties + set mdm_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 mdm_1 ] + + # Create instance: microblaze_0, and set properties + set microblaze_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:11.0 microblaze_0 ] + set_property -dict [ list \ + CONFIG.C_ADDR_TAG_BITS {16} \ + CONFIG.C_CACHE_BYTE_SIZE {32768} \ + CONFIG.C_DCACHE_ADDR_TAG {16} \ + CONFIG.C_DCACHE_BYTE_SIZE {32768} \ + CONFIG.C_DCACHE_USE_WRITEBACK {1} \ + CONFIG.C_DEBUG_ENABLED {1} \ + CONFIG.C_DIV_ZERO_EXCEPTION {1} \ + CONFIG.C_D_AXI {1} \ + CONFIG.C_D_LMB {1} \ + CONFIG.C_FPU_EXCEPTION {1} \ + CONFIG.C_ICACHE_LINE_LEN {8} \ + CONFIG.C_ICACHE_STREAMS {1} \ + CONFIG.C_ICACHE_VICTIMS {8} \ + CONFIG.C_ILL_OPCODE_EXCEPTION {1} \ + CONFIG.C_I_LMB {1} \ + CONFIG.C_MMU_ZONES {2} \ + CONFIG.C_M_AXI_D_BUS_EXCEPTION {1} \ + CONFIG.C_M_AXI_I_BUS_EXCEPTION {1} \ + CONFIG.C_NUMBER_OF_PC_BRK {2} \ + CONFIG.C_NUMBER_OF_RD_ADDR_BRK {1} \ + CONFIG.C_NUMBER_OF_WR_ADDR_BRK {1} \ + CONFIG.C_OPCODE_0x0_ILLEGAL {1} \ + CONFIG.C_PVR {2} \ + CONFIG.C_UNALIGNED_EXCEPTIONS {1} \ + CONFIG.C_USE_BARREL {1} \ + CONFIG.C_USE_DCACHE {1} \ + CONFIG.C_USE_DIV {1} \ + CONFIG.C_USE_FPU {1} \ + CONFIG.C_USE_HW_MUL {2} \ + CONFIG.C_USE_ICACHE {1} \ + CONFIG.C_USE_MMU {3} \ + CONFIG.C_USE_MSR_INSTR {1} \ + CONFIG.C_USE_PCMP_INSTR {1} \ + CONFIG.G_TEMPLATE_LIST {10} \ + CONFIG.G_USE_EXCEPTIONS {1} \ + ] $microblaze_0 + + # Create instance: microblaze_0_axi_periph, and set properties + set microblaze_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 microblaze_0_axi_periph ] + set_property -dict [ list \ + CONFIG.NUM_MI {4} \ + ] $microblaze_0_axi_periph + + # Create instance: microblaze_0_local_memory + create_hier_cell_microblaze_0_local_memory [current_bd_instance .] microblaze_0_local_memory + + # Create instance: myproject_axi_0, and set properties + set myproject_axi_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:myproject_axi:1.0 myproject_axi_0 ] + + # Create instance: rst_clk_wiz_0_100M, and set properties + set rst_clk_wiz_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_clk_wiz_0_100M ] + set_property -dict [ list \ + CONFIG.RESET_BOARD_INTERFACE {Custom} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $rst_clk_wiz_0_100M + + # Create instance: rst_ddr4_0_333M, and set properties + set rst_ddr4_0_333M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ddr4_0_333M ] + + # Create interface connections + connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_smc/M00_AXI] [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI] + connect_bd_intf_net -intf_net axi_uart16550_0_UART [get_bd_intf_ports rs232_uart_0] [get_bd_intf_pins axi_uart16550_0/UART] + connect_bd_intf_net -intf_net ddr4_0_C0_DDR4 [get_bd_intf_ports ddr4_sdram] [get_bd_intf_pins ddr4_0/C0_DDR4] + connect_bd_intf_net -intf_net default_100mhz_clk_1 [get_bd_intf_ports default_100mhz_clk] [get_bd_intf_pins ddr4_0/C0_SYS_CLK] + connect_bd_intf_net -intf_net microblaze_0_M_AXI_DC [get_bd_intf_pins axi_smc/S00_AXI] [get_bd_intf_pins microblaze_0/M_AXI_DC] + connect_bd_intf_net -intf_net microblaze_0_M_AXI_DP [get_bd_intf_pins microblaze_0/M_AXI_DP] [get_bd_intf_pins microblaze_0_axi_periph/S00_AXI] + connect_bd_intf_net -intf_net microblaze_0_M_AXI_IC [get_bd_intf_pins axi_smc/S01_AXI] [get_bd_intf_pins microblaze_0/M_AXI_IC] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M00_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M00_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M01_AXI [get_bd_intf_pins axi_uart16550_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M01_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M02_AXI [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL] [get_bd_intf_pins microblaze_0_axi_periph/M02_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M03_AXI [get_bd_intf_pins microblaze_0_axi_periph/M03_AXI] [get_bd_intf_pins myproject_axi_0/s_axi_CTRL_BUS] + connect_bd_intf_net -intf_net microblaze_0_debug [get_bd_intf_pins mdm_1/MBDEBUG_0] [get_bd_intf_pins microblaze_0/DEBUG] + connect_bd_intf_net -intf_net microblaze_0_dlmb_1 [get_bd_intf_pins microblaze_0/DLMB] [get_bd_intf_pins microblaze_0_local_memory/DLMB] + connect_bd_intf_net -intf_net microblaze_0_ilmb_1 [get_bd_intf_pins microblaze_0/ILMB] [get_bd_intf_pins microblaze_0_local_memory/ILMB] + connect_bd_intf_net -intf_net myproject_axi_0_m_axi_IN_BUS [get_bd_intf_pins axi_smc/S02_AXI] [get_bd_intf_pins myproject_axi_0/m_axi_IN_BUS] + connect_bd_intf_net -intf_net myproject_axi_0_m_axi_OUT_BUS [get_bd_intf_pins axi_smc/S03_AXI] [get_bd_intf_pins myproject_axi_0/m_axi_OUT_BUS] + + # Create port connections + connect_bd_net -net clk_wiz_0_locked [get_bd_pins clk_wiz_0/locked] [get_bd_pins rst_clk_wiz_0_100M/dcm_locked] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk [get_bd_pins axi_smc/aclk] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins ddr4_0/c0_ddr4_ui_clk] [get_bd_pins microblaze_0_axi_periph/M02_ACLK] [get_bd_pins rst_ddr4_0_333M/slowest_sync_clk] + connect_bd_net -net ddr4_0_c0_ddr4_ui_clk_sync_rst [get_bd_pins clk_wiz_0/reset] [get_bd_pins ddr4_0/c0_ddr4_ui_clk_sync_rst] [get_bd_pins rst_clk_wiz_0_100M/ext_reset_in] [get_bd_pins rst_ddr4_0_333M/ext_reset_in] + connect_bd_net -net dummy_port_in_1 [get_bd_ports dummy_port_in] [get_bd_pins ddr4_0/sys_rst] + connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mdm_1/Debug_SYS_Rst] [get_bd_pins rst_clk_wiz_0_100M/mb_debug_sys_rst] + connect_bd_net -net microblaze_0_Clk [get_bd_pins axi_smc/aclk1] [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins axi_uart16550_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins microblaze_0/Clk] [get_bd_pins microblaze_0_axi_periph/ACLK] [get_bd_pins microblaze_0_axi_periph/M00_ACLK] [get_bd_pins microblaze_0_axi_periph/M01_ACLK] [get_bd_pins microblaze_0_axi_periph/M03_ACLK] [get_bd_pins microblaze_0_axi_periph/S00_ACLK] [get_bd_pins microblaze_0_local_memory/LMB_Clk] [get_bd_pins myproject_axi_0/ap_clk] [get_bd_pins rst_clk_wiz_0_100M/slowest_sync_clk] + connect_bd_net -net rst_clk_wiz_0_100M_bus_struct_reset [get_bd_pins microblaze_0_local_memory/SYS_Rst] [get_bd_pins rst_clk_wiz_0_100M/bus_struct_reset] + connect_bd_net -net rst_clk_wiz_0_100M_mb_reset [get_bd_pins microblaze_0/Reset] [get_bd_pins rst_clk_wiz_0_100M/mb_reset] + connect_bd_net -net rst_clk_wiz_0_100M_peripheral_aresetn [get_bd_pins axi_smc/aresetn] [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins axi_uart16550_0/s_axi_aresetn] [get_bd_pins microblaze_0_axi_periph/ARESETN] [get_bd_pins microblaze_0_axi_periph/M00_ARESETN] [get_bd_pins microblaze_0_axi_periph/M01_ARESETN] [get_bd_pins microblaze_0_axi_periph/M03_ARESETN] [get_bd_pins microblaze_0_axi_periph/S00_ARESETN] [get_bd_pins myproject_axi_0/ap_rst_n] [get_bd_pins rst_clk_wiz_0_100M/peripheral_aresetn] + connect_bd_net -net rst_ddr4_0_333M_peripheral_aresetn [get_bd_pins ddr4_0/c0_ddr4_aresetn] [get_bd_pins microblaze_0_axi_periph/M02_ARESETN] [get_bd_pins rst_ddr4_0_333M/peripheral_aresetn] + + # Create address segments + assign_bd_address -offset 0x41C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] -force + assign_bd_address -offset 0x44A00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_uart16550_0/S_AXI/Reg] -force + assign_bd_address -offset 0x80000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x80000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x44B00000 -range 0x00100000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP_CTRL/C0_REG] -force + assign_bd_address -offset 0x00000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem] -force + assign_bd_address -offset 0x00000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem] -force + assign_bd_address -offset 0x44A10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs myproject_axi_0/s_axi_CTRL_BUS/Reg] -force + assign_bd_address -offset 0x80000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces myproject_axi_0/Data_m_axi_IN_BUS] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + assign_bd_address -offset 0x80000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces myproject_axi_0/Data_m_axi_OUT_BUS] [get_bd_addr_segs ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] -force + + + # Restore current instance + current_bd_instance $oldCurInst + + validate_bd_design + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + +############################################################################################################# + +#WRAP THE MODEL + +make_wrapper -files [get_files ./${myproject}_vivado_accelerator/project_1.srcs/sources_1/bd/design_1/design_1.bd] -top + +add_files -norecurse ./${myproject}_vivado_accelerator/project_1.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v + +reset_run impl_1 +reset_run synth_1 +launch_runs impl_1 -to_step write_bitstream -jobs 6 +wait_on_run -timeout 360 impl_1 + +#open_run impl_1 +report_utilization -file util.rpt -hierarchical -hierarchical_percentages + + + + + + + + + + + + + + + + + diff --git a/hls4ml/templates/vivado_accelerator/vcu128/verilog_wrappers/design_1_wrapper.v b/hls4ml/templates/vivado_accelerator/vcu128/verilog_wrappers/design_1_wrapper.v new file mode 100755 index 000000000..aa944e12a --- /dev/null +++ b/hls4ml/templates/vivado_accelerator/vcu128/verilog_wrappers/design_1_wrapper.v @@ -0,0 +1,92 @@ +//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov 6 21:39:14 MST 2019 +//Date : Wed Oct 5 16:49:36 2022 +//Host : subnugler running 64-bit Ubuntu 22.04.1 LTS +//Command : generate_target design_1_wrapper.bd +//Design : design_1_wrapper +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +module design_1_wrapper + (ddr4_sdram_act_n, + ddr4_sdram_adr, + ddr4_sdram_ba, + ddr4_sdram_bg, + ddr4_sdram_ck_c, + ddr4_sdram_ck_t, + ddr4_sdram_cke, + ddr4_sdram_cs_n, + ddr4_sdram_dm_n, + ddr4_sdram_dq, + ddr4_sdram_dqs_c, + ddr4_sdram_dqs_t, + ddr4_sdram_odt, + ddr4_sdram_reset_n, + default_100mhz_clk_clk_n, + default_100mhz_clk_clk_p, + dummy_port_in, + rs232_uart_0_rxd, + rs232_uart_0_txd); + output ddr4_sdram_act_n; + output [16:0]ddr4_sdram_adr; + output [1:0]ddr4_sdram_ba; + output ddr4_sdram_bg; + output ddr4_sdram_ck_c; + output ddr4_sdram_ck_t; + output ddr4_sdram_cke; + output [1:0]ddr4_sdram_cs_n; + inout [8:0]ddr4_sdram_dm_n; + inout [71:0]ddr4_sdram_dq; + inout [8:0]ddr4_sdram_dqs_c; + inout [8:0]ddr4_sdram_dqs_t; + output ddr4_sdram_odt; + output ddr4_sdram_reset_n; + input default_100mhz_clk_clk_n; + input default_100mhz_clk_clk_p; + input dummy_port_in; + input rs232_uart_0_rxd; + output rs232_uart_0_txd; + + wire ddr4_sdram_act_n; + wire [16:0]ddr4_sdram_adr; + wire [1:0]ddr4_sdram_ba; + wire ddr4_sdram_bg; + wire ddr4_sdram_ck_c; + wire ddr4_sdram_ck_t; + wire ddr4_sdram_cke; + wire [1:0]ddr4_sdram_cs_n; + wire [8:0]ddr4_sdram_dm_n; + wire [71:0]ddr4_sdram_dq; + wire [8:0]ddr4_sdram_dqs_c; + wire [8:0]ddr4_sdram_dqs_t; + wire ddr4_sdram_odt; + wire ddr4_sdram_reset_n; + wire default_100mhz_clk_clk_n; + wire default_100mhz_clk_clk_p; + wire dummy_port_in; + wire rs232_uart_0_rxd; + wire rs232_uart_0_txd; + + design_1 design_1_i + (.ddr4_sdram_act_n(ddr4_sdram_act_n), + .ddr4_sdram_adr(ddr4_sdram_adr), + .ddr4_sdram_ba(ddr4_sdram_ba), + .ddr4_sdram_bg(ddr4_sdram_bg), + .ddr4_sdram_ck_c(ddr4_sdram_ck_c), + .ddr4_sdram_ck_t(ddr4_sdram_ck_t), + .ddr4_sdram_cke(ddr4_sdram_cke), + .ddr4_sdram_cs_n(ddr4_sdram_cs_n), + .ddr4_sdram_dm_n(ddr4_sdram_dm_n), + .ddr4_sdram_dq(ddr4_sdram_dq), + .ddr4_sdram_dqs_c(ddr4_sdram_dqs_c), + .ddr4_sdram_dqs_t(ddr4_sdram_dqs_t), + .ddr4_sdram_odt(ddr4_sdram_odt), + .ddr4_sdram_reset_n(ddr4_sdram_reset_n), + .default_100mhz_clk_clk_n(default_100mhz_clk_clk_n), + .default_100mhz_clk_clk_p(default_100mhz_clk_clk_p), + .dummy_port_in(dummy_port_in), + .rs232_uart_0_rxd(rs232_uart_0_rxd), + .rs232_uart_0_txd(rs232_uart_0_txd)); +endmodule