simd: Assume VLEN length of RISC-V as 128

Signed-off-by: Hiroshi Hatake <[email protected]>
fluent · Dec 17, 2024 · 2b094f5 · 2b094f5
1 parent 9e1a594
commit 2b094f5
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/include/fluent-bit/flb_simd.h b/include/fluent-bit/flb_simd.h
@@ -76,7 +76,9 @@ typedef uint32x4_t flb_vector32;
 #define FLB_SIMD_RVV
 typedef vuint8m1_t flb_vector8;
 typedef vuint32m1_t flb_vector32;
-#define RVV_VEC_INST_LEN 16
+
+/* Currently, VLEN is assumed to 128. */
+#define RVV_VEC_INST_LEN (128 / 8) /* 16 */
 
 #else
 /*