From 2b094f5b17e91c6f51096062ed8d169d9742027f Mon Sep 17 00:00:00 2001 From: Hiroshi Hatake Date: Tue, 17 Dec 2024 11:08:09 +0900 Subject: [PATCH] simd: Assume VLEN length of RISC-V as 128 Signed-off-by: Hiroshi Hatake --- include/fluent-bit/flb_simd.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/fluent-bit/flb_simd.h b/include/fluent-bit/flb_simd.h index 68a50913273..a0fa3f3b32b 100644 --- a/include/fluent-bit/flb_simd.h +++ b/include/fluent-bit/flb_simd.h @@ -76,7 +76,9 @@ typedef uint32x4_t flb_vector32; #define FLB_SIMD_RVV typedef vuint8m1_t flb_vector8; typedef vuint32m1_t flb_vector32; -#define RVV_VEC_INST_LEN 16 + +/* Currently, VLEN is assumed to 128. */ +#define RVV_VEC_INST_LEN (128 / 8) /* 16 */ #else /*