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b16.lyx16
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#LyX 1.6.5 created this file. For more info see http://www.lyx.org/
\lyxformat 345
\begin_document
\begin_header
\textclass literate-article
\begin_preamble
\usepackage[dvips,colorlinks=true,linkcolor=blue]{hyperref}
\DeclareGraphicsExtensions{.pdf}
\end_preamble
\use_default_options false
\language american
\inputencoding auto
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\font_sans default
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\font_sc false
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\font_tt_scale 100
\graphics default
\paperfontsize default
\spacing single
\use_hyperref false
\papersize a4paper
\use_geometry true
\use_amsmath 1
\use_esint 0
\cite_engine basic
\use_bibtopic false
\paperorientation portrait
\leftmargin 36pt
\topmargin 1in
\rightmargin 36pt
\bottommargin 1in
\secnumdepth 3
\tocdepth 3
\paragraph_separation indent
\defskip medskip
\quotes_language english
\papercolumns 2
\papersides 1
\paperpagestyle fancy
\tracking_changes false
\output_changes false
\author ""
\author ""
\end_header
\begin_body
\begin_layout Title
b16 Documentation
\end_layout
\begin_layout Author
\noun on
Bernd Paysan
\end_layout
\begin_layout Standard
\begin_inset ERT
status collapsed
\begin_layout Plain Layout
\backslash
lhead{
\end_layout
\end_inset
b16 Documentation
\begin_inset ERT
status collapsed
\begin_layout Plain Layout
}
\backslash
chead{
\end_layout
\end_inset
\noun on
Bernd Paysan
\noun default
\begin_inset ERT
status collapsed
\begin_layout Plain Layout
}
\end_layout
\end_inset
\end_layout
\begin_layout Abstract
This article presents architecture and implementation of the b16 stack processor.
This processor is inspired by
\noun on
Chuck Moore'
\noun default
s newest Forth processors.
The minimalistic design fits into small FPGAs and ASICs and is ideally
suited for applications that need both control and calculations.
The factor is shifted towards control to save space.
The synthesizible implementation uses Verilog.
\end_layout
\begin_layout Section*
Introduction
\end_layout
\begin_layout Standard
Minimalistic CPUs can be used in many designs.
A state machine often is too complicated and too difficult to develop,
when there are more than a few states.
A program with subroutines can perform a lot more complex tasks, and is
easier to develop at the same time.
Also, ROM and RAM blocks occupy much less place on silicon than
\begin_inset Quotes eld
\end_inset
random logic
\begin_inset Quotes erd
\end_inset
.
That's also valid for FPGAs, where
\begin_inset Quotes eld
\end_inset
block RAM
\begin_inset Quotes erd
\end_inset
is---in contrast to logic elements---plenty.
\end_layout
\begin_layout Standard
The architecture is inspired by the c18 from
\noun on
Chuck Moore
\noun default
\begin_inset CommandInset citation
LatexCommand cite
key "c18"
\end_inset
.
The exact instruction mix is different; it also differs from the standard
b16 core.
Also, this architecture is byte-addressed.
\end_layout
\begin_layout Standard
A word about Verilog: Verilog is a C-like language, but tailored for the
purpose to simulate logic, and to write synthesizible code.
Variables are bits and bit vectors, and assignments are typically non-blocking,
i.e.
on assignments first all right sides are computed, and the left sides are
modified afterwards.
Also, Verilog has events, like changing of values or clock edges, and blocks
can wait on them.
\end_layout
\begin_layout Section
Architectural Overview
\end_layout
\begin_layout Standard
The core components are
\end_layout
\begin_layout Itemize
An ALU
\end_layout
\begin_layout Itemize
A data stack with top and next of stack (T and N) as inputs for the ALU
\end_layout
\begin_layout Itemize
A return stack
\end_layout
\begin_layout Itemize
An instruction pointer P
\end_layout
\begin_layout Itemize
An address mux
\family typewriter
addr
\family default
, to address external memory
\end_layout
\begin_layout Itemize
An instruction latch I
\end_layout
\begin_layout Standard
Figure
\begin_inset CommandInset ref
LatexCommand ref
reference "blockdiagram"
\end_inset
shows a block diagram.
\end_layout
\begin_layout Standard
\begin_inset Float figure
wide false
sideways false
status open
\begin_layout Plain Layout
\align center
\begin_inset Graphics
filename b16-small.pdf
width 100col%
\end_inset
\end_layout
\begin_layout Plain Layout
\begin_inset Caption
\begin_layout Plain Layout
Block Diagram
\begin_inset CommandInset label
LatexCommand label
name "blockdiagram"
\end_inset
\end_layout
\end_inset
\end_layout
\end_inset
\end_layout
\begin_layout Subsection
Register
\end_layout
\begin_layout Standard
In addition to the standard Forth machine registers there are control registers
for external RAM (
\family typewriter
rd
\family default
and
\family typewriter
wr
\family default
), stack pointers (
\family typewriter
sp
\family default
and
\family typewriter
rp
\family default
), and a carry
\family typewriter
c
\family default
.
For consistency with Chuck Moores' nomenclature, violating most coding
style guidelines, the Forth machine registers are single-letter variables
in upper case.
Since the source code is a LyX document, you can use the
\begin_inset Quotes eld
\end_inset
search whole word
\begin_inset Quotes erd
\end_inset
mode to find them easily, and they also show up on top of the signal list
during simulation.
\end_layout
\begin_layout Standard
\begin_inset VSpace medskip
\end_inset
\end_layout
\begin_layout Standard
\align center
\begin_inset Tabular
<lyxtabular version="3" rows="9" columns="2">
<features>
<column alignment="center" valignment="top" width="0pt">
<column alignment="left" valignment="top" width="0pt">
<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
\emph on
Name
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\begin_inset Text
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\emph on
Function
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\end_inset
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<row>
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\begin_inset Text
\begin_layout Plain Layout
T
\end_layout
\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Top of Stack
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\end_inset
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<row>
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\begin_inset Text
\begin_layout Plain Layout
I
\end_layout
\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Instruction Bundle
\end_layout
\end_inset
</cell>
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<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
P
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\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Program Counter
\end_layout
\end_inset
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<row>
<cell alignment="center" valignment="top" topline="true" leftline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
R
\end_layout
\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
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Top of Returnstack
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<row>
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\begin_inset Text
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state
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\begin_inset Text
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Processor State
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<row>
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\begin_inset Text
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sp
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\begin_inset Text
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Stack Pointer
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<row>
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\begin_inset Text
\begin_layout Plain Layout
rp
\end_layout
\end_inset
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<cell alignment="center" valignment="top" topline="true" leftline="true" rightline="true" usebox="none">
\begin_inset Text
\begin_layout Plain Layout
Return Stack Pointer
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<row>
<cell alignment="center" valignment="top" topline="true" bottomline="true" leftline="true" usebox="none">
\begin_inset Text
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c
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\begin_inset Text
\begin_layout Plain Layout
Carry Flag
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\end_inset
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</row>
</lyxtabular>
\end_inset
\end_layout
\begin_layout Standard
\begin_inset VSpace medskip
\end_inset
\end_layout
\begin_layout Scrap
<<register declarations>>=
\begin_inset Newline newline
\end_inset
reg [sdep-1:0] sp;
\begin_inset Newline newline
\end_inset
reg [rdep-1:0] rp;
\begin_inset Newline newline
\end_inset
\begin_inset Newline newline
\end_inset
reg `L T, I, P, R;
\begin_inset Newline newline
\end_inset
reg [1:0] state;
\begin_inset Newline newline
\end_inset
reg c;
\begin_inset Newline newline
\end_inset
@
\end_layout
\begin_layout Standard
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status collapsed
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\end_layout
\end_inset
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\end_layout
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<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
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\end_layout
\end_inset
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<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
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exec
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\end_inset
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<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
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goto
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\end_inset
</cell>
<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
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ret
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\end_inset
</cell>
<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
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gz
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\end_inset
</cell>
<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
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gnz
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\end_inset
</cell>
<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
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gc
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\end_inset
</cell>
<cell alignment="center" valignment="top" bottomline="true" rightline="true" usebox="none">
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gnc
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\end_inset
</cell>
<cell alignment="left" valignment="top" bottomline="true" rightline="true" usebox="none">
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\emph on
for slot 3
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\end_inset
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<row>
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8
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\end_inset
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xor
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\end_inset
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com
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\end_inset
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and
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or
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+
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\end_layout
\end_inset
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\end_inset
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<row>
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10
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\end_inset
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!+
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\end_inset
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<cell alignment="center" valignment="top" rightline="true" usebox="none">
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@+
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\end_inset
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<cell alignment="center" valignment="top" rightline="true" usebox="none">
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@
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\end_inset
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<cell alignment="center" valignment="top" rightline="true" usebox="none">
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lit
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\end_inset
</cell>
<cell alignment="center" valignment="top" rightline="true" usebox="none">
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