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Copy pathFE_Qsys_AD1939_Audio_Mini_hw.tcl
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FE_Qsys_AD1939_Audio_Mini_hw.tcl
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# TCL File Generated by Component Editor 18.0
# Fri May 01 02:55:58 MDT 2020
# DO NOT MODIFY
#
# FE_Qsys_AD1939_Audio_Mini_v1 "FE_Qsys_AD1939_Audio_Mini_v1" v1.0
# 2020.05.01.02:55:58
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module FE_Qsys_AD1939_Audio_Mini_v1
#
set_module_property DESCRIPTION ""
set_module_property NAME FE_Qsys_AD1939_Audio_Mini
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME FE_Qsys_AD1939_Audio_Mini
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
set_module_property GROUP "FPGA Open Speech Tools"
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL AD1939_hps_audio_mini
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file AD1939_hps_audio_mini_v1.vhd VHDL PATH AD1939_hps_audio_mini.vhd TOP_LEVEL_FILE
add_fileset_file Parallel2Serial_32bits.vhd VHDL PATH ../serdes/Parallel2Serial_32bits.vhd
add_fileset_file Serial2Parallel_32bits.vhd VHDL PATH ../serdes/Serial2Parallel_32bits.vhd
add_fileset_file ad1939_pkg.vhd VHDL PATH ad1939_pkg.vhd
#
# parameters
#
#
# module assignments
#
set_module_assignment embeddedsw.dts.compatible dev,fe-audio-mini
set_module_assignment embeddedsw.dts.group audio-mini
set_module_assignment embeddedsw.dts.vendor fe
#
# display items
#
#
# connection point sys_clk
#
add_interface sys_clk clock end
set_interface_property sys_clk clockRate 0
set_interface_property sys_clk ENABLED true
set_interface_property sys_clk EXPORT_OF ""
set_interface_property sys_clk PORT_NAME_MAP ""
set_interface_property sys_clk CMSIS_SVD_VARIABLES ""
set_interface_property sys_clk SVD_ADDRESS_GROUP ""
add_interface_port sys_clk sys_clk clk Input 1
#
# connection point sys_reset
#
add_interface sys_reset reset end
set_interface_property sys_reset associatedClock sys_clk
set_interface_property sys_reset synchronousEdges DEASSERT
set_interface_property sys_reset ENABLED true
set_interface_property sys_reset EXPORT_OF ""
set_interface_property sys_reset PORT_NAME_MAP ""
set_interface_property sys_reset CMSIS_SVD_VARIABLES ""
set_interface_property sys_reset SVD_ADDRESS_GROUP ""
add_interface_port sys_reset sys_reset reset Input 1
#
# connection point clk_abclk
#
add_interface clk_abclk clock end
set_interface_property clk_abclk clockRate 0
set_interface_property clk_abclk ENABLED true
set_interface_property clk_abclk EXPORT_OF ""
set_interface_property clk_abclk PORT_NAME_MAP ""
set_interface_property clk_abclk CMSIS_SVD_VARIABLES ""
set_interface_property clk_abclk SVD_ADDRESS_GROUP ""
add_interface_port clk_abclk AD1939_ADC_ABCLK clk Input 1
#
# connection point clk_alrclk
#
add_interface clk_alrclk clock end
set_interface_property clk_alrclk clockRate 0
set_interface_property clk_alrclk ENABLED true
set_interface_property clk_alrclk EXPORT_OF ""
set_interface_property clk_alrclk PORT_NAME_MAP ""
set_interface_property clk_alrclk CMSIS_SVD_VARIABLES ""
set_interface_property clk_alrclk SVD_ADDRESS_GROUP ""
add_interface_port clk_alrclk AD1939_ADC_ALRCLK clk Input 1
#
# connection point Line_In
#
add_interface Line_In avalon_streaming start
set_interface_property Line_In associatedClock sys_clk
set_interface_property Line_In associatedReset sys_reset
set_interface_property Line_In dataBitsPerSymbol 24
set_interface_property Line_In errorDescriptor ""
set_interface_property Line_In firstSymbolInHighOrderBits true
set_interface_property Line_In maxChannel 1
set_interface_property Line_In readyLatency 0
set_interface_property Line_In ENABLED true
set_interface_property Line_In EXPORT_OF ""
set_interface_property Line_In PORT_NAME_MAP ""
set_interface_property Line_In CMSIS_SVD_VARIABLES ""
set_interface_property Line_In SVD_ADDRESS_GROUP ""
add_interface_port Line_In AD1939_ADC_channel channel Output 1
add_interface_port Line_In AD1939_ADC_data data Output 24
add_interface_port Line_In AD1939_ADC_valid valid Output 1
#
# connection point Headphone_Out
#
add_interface Headphone_Out avalon_streaming end
set_interface_property Headphone_Out associatedClock sys_clk
set_interface_property Headphone_Out associatedReset sys_reset
set_interface_property Headphone_Out dataBitsPerSymbol 24
set_interface_property Headphone_Out errorDescriptor ""
set_interface_property Headphone_Out firstSymbolInHighOrderBits true
set_interface_property Headphone_Out maxChannel 1
set_interface_property Headphone_Out readyLatency 0
set_interface_property Headphone_Out ENABLED true
set_interface_property Headphone_Out EXPORT_OF ""
set_interface_property Headphone_Out PORT_NAME_MAP ""
set_interface_property Headphone_Out CMSIS_SVD_VARIABLES ""
set_interface_property Headphone_Out SVD_ADDRESS_GROUP ""
add_interface_port Headphone_Out AD1939_DAC_channel channel Input 1
add_interface_port Headphone_Out AD1939_DAC_data data Input 24
add_interface_port Headphone_Out AD1939_DAC_valid valid Input 1
#
# connection point connect_to_AD1939
#
add_interface connect_to_AD1939 conduit end
set_interface_property connect_to_AD1939 associatedClock clk_abclk
set_interface_property connect_to_AD1939 associatedReset sys_reset
set_interface_property connect_to_AD1939 ENABLED true
set_interface_property connect_to_AD1939 EXPORT_OF ""
set_interface_property connect_to_AD1939 PORT_NAME_MAP ""
set_interface_property connect_to_AD1939 CMSIS_SVD_VARIABLES ""
set_interface_property connect_to_AD1939 SVD_ADDRESS_GROUP ""
add_interface_port connect_to_AD1939 AD1939_ADC_ASDATA2 asdata2 Input 1
add_interface_port connect_to_AD1939 AD1939_DAC_DBCLK dbclk Output 1
add_interface_port connect_to_AD1939 AD1939_DAC_DLRCLK dlrclk Output 1
add_interface_port connect_to_AD1939 AD1939_DAC_DSDATA1 dsdata1 Output 1