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Copy pathFE_NCP5623B_hw.tcl
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FE_NCP5623B_hw.tcl
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# TCL File Generated by Component Editor 18.0
# Mon Mar 16 12:43:46 MDT 2020
# DO NOT MODIFY
#
# FE_NCP5623B "FE_NCP5623B" v1.0
# 2020.03.16.12:43:46
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module FE_NCP5623B
#
set_module_property DESCRIPTION ""
set_module_property NAME FE_NCP5623B
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME FE_NCP5623B
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
set_module_property GROUP "FPGA Open Speech Tools"
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL FE_NCP5623B
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file FE_NCP5623B_v1.vhd VHDL PATH FE_NCP5623B_v1.vhd TOP_LEVEL_FILE
#
# parameters
#
#
# display items
#
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock sys_clk
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset reset_n reset_n Input 1
#
# connection point rgb_input
#
add_interface rgb_input avalon_streaming end
set_interface_property rgb_input associatedClock sys_clk
set_interface_property rgb_input associatedReset reset
set_interface_property rgb_input dataBitsPerSymbol 16
set_interface_property rgb_input errorDescriptor ""
set_interface_property rgb_input firstSymbolInHighOrderBits true
set_interface_property rgb_input maxChannel 0
set_interface_property rgb_input readyLatency 0
set_interface_property rgb_input ENABLED true
set_interface_property rgb_input EXPORT_OF ""
set_interface_property rgb_input PORT_NAME_MAP ""
set_interface_property rgb_input CMSIS_SVD_VARIABLES ""
set_interface_property rgb_input SVD_ADDRESS_GROUP ""
add_interface_port rgb_input rgb_input_data data Input 16
add_interface_port rgb_input rgb_input_error error Input 2
add_interface_port rgb_input rgb_input_valid valid Input 1
#
# connection point sys_clk
#
add_interface sys_clk clock end
set_interface_property sys_clk clockRate 0
set_interface_property sys_clk ENABLED true
set_interface_property sys_clk EXPORT_OF ""
set_interface_property sys_clk PORT_NAME_MAP ""
set_interface_property sys_clk CMSIS_SVD_VARIABLES ""
set_interface_property sys_clk SVD_ADDRESS_GROUP ""
add_interface_port sys_clk sys_clk clk Input 1
#
# connection point i2c_component_conduit
#
add_interface i2c_component_conduit conduit end
set_interface_property i2c_component_conduit associatedClock ""
set_interface_property i2c_component_conduit associatedReset ""
set_interface_property i2c_component_conduit ENABLED true
set_interface_property i2c_component_conduit EXPORT_OF ""
set_interface_property i2c_component_conduit PORT_NAME_MAP ""
set_interface_property i2c_component_conduit CMSIS_SVD_VARIABLES ""
set_interface_property i2c_component_conduit SVD_ADDRESS_GROUP ""
add_interface_port i2c_component_conduit i2c_enable_out i2c_enable_out Output 1
add_interface_port i2c_component_conduit i2c_address_out i2c_address_out Output 7
add_interface_port i2c_component_conduit i2c_rdwr_out i2c_rdwr_out Output 1
add_interface_port i2c_component_conduit i2c_data_write_out i2c_data_write_out Output 8
add_interface_port i2c_component_conduit i2c_bsy_in i2c_bsy_in Input 1
add_interface_port i2c_component_conduit i2c_data_read_in i2c_data_read_in Input 8
add_interface_port i2c_component_conduit i2c_req_out i2c_req_out Output 1
add_interface_port i2c_component_conduit i2c_rdy_in i2c_rdy_in Input 1