diff --git a/gf180/diode.py b/gf180/diode.py index 471752d..2f42075 100644 --- a/gf180/diode.py +++ b/gf180/diode.py @@ -321,7 +321,6 @@ def diode_nd2ps( @gf.cell def diode_pd2nw( - layout, la: float = 0.1, wa: float = 0.1, cw: float = 0.1, @@ -642,17 +641,16 @@ def diode_nw2ps( p_label: str = "", n_label: str = "", ) -> gf.Component: - """ - Usage:- - used to draw 3.3V Nwell/Psub diode by specifying parameters - Arguments:- - la : Float of diff length (anode) - wa : Float of diff width (anode) - cw : Float of Cathode width - volt : String of operating voltage of the diode [3.3V, 5V/6V] + """used to draw 3.3V Nwell/Psub diode by specifying parameters + + Args: + la: anode length. + wa: anode width. + cw: cathode width. + volt: operating voltage of the diode [3.3V, 5V/6V] """ - c = gf.Component("diode_nw2ps_dev") + c = gf.Component() comp_spacing: float = 0.48 np_enc_comp: float = 0.16 @@ -778,17 +776,20 @@ def diode_pw2dw( n_label: str = "", ) -> gf.Component: """ - Usage:- - used to draw LVPWELL/DNWELL diode by specifying parameters - Arguments:- - layout : Object of layout - la : Float of diff length (anode) - wa : Float of diff width (anode) - cw : Float of cathode width - volt : String of operating voltage of the diode [3.3V, 5V/6V] + used to draw LVPWELL/DNWELL diode by specifying parameters + + Args: + la: anode length. + wa: anode width. + cw: cathode width. + volt: operating voltage of the diode [3.3V, 5V/6V] + pcmpgr: if True, pcmpgr will be added. + label: if True, labels will be added. + p_label: p contact label. + n_label: n contact label. """ - c = gf.Component("diode_pw2dw_dev") + c = gf.Component() comp_spacing: float = 0.48 np_enc_comp: float = 0.16 @@ -1086,16 +1087,20 @@ def diode_dw2ps( p_label: str = "", n_label: str = "", ) -> gf.Component: - """ - Usage:- - used to draw LVPWELL/DNWELL diode by specifying parameters - Arguments:- - la : Float of diff length (anode) - wa : Float of diff width (anode) - volt : String of operating voltage of the diode [3.3V, 5V/6V] + """used to draw LVPWELL/DNWELL diode by specifying parameters + + Args: + la: anode length. + wa: anode width. + cw: cathode width. + volt: operating voltage of the diode [3.3V, 5V/6V]. + pcmpgr: True if pwell guardring is required. + label: True if labels are required. + p_label: label for pwell. + n_label: label for nwell. """ - c = gf.Component("diode_dw2ps_dev") + c = gf.Component() if volt == "5/6V": dn_enc_ncmp = 0.66 @@ -1886,5 +1891,6 @@ def sc_anode_strap(size: Float2 = (0.1, 0.1)) -> gf.Component: if __name__ == "__main__": - c = sc_diode() + # c = sc_diode() + c = diode_pd2nw() c.show() diff --git a/gf180/guardring.py b/gf180/guardring.py index 94828cd..c08a94b 100644 --- a/gf180/guardring.py +++ b/gf180/guardring.py @@ -1,9 +1,11 @@ +from functools import partial + import gdsfactory as gf from gf180.layers import LAYER, layer from gf180.via_generator import via_generator -dn_rect = gf.partial(gf.components.rectangle, layer=LAYER.dnwell) +dn_rect = partial(gf.components.rectangle, layer=LAYER.dnwell) @gf.cell diff --git a/pyproject.toml b/pyproject.toml index d4eb809..1317e7a 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -14,7 +14,7 @@ classifiers = [ "Operating System :: OS Independent" ] dependencies = [ - "gdsfactory[cad]>=7.1.1,<7.2.0" + "gdsfactory[cad]>=7.4.6,<7.5.0" ] description = "GlobalFoundries 180nm MCU" keywords = ["python"] diff --git a/tests/gds_ref/cap_mim.gds b/tests/gds_ref/cap_mim.gds new file mode 100644 index 0000000..fd986cc Binary files /dev/null and b/tests/gds_ref/cap_mim.gds differ diff --git a/tests/test_components/test_pdk_settings_cap_mim_.yml b/tests/test_components/test_pdk_settings_cap_mim_.yml new file mode 100644 index 0000000..a93f0de --- /dev/null +++ b/tests/test_components/test_pdk_settings_cap_mim_.yml @@ -0,0 +1,26 @@ +name: cap_mim +ports: {} +settings: + changed: {} + child: null + default: + bot_label: '' + label: false + lc: 2 + metal_level: M4 + mim_option: A + top_label: '' + wc: 2 + full: + bot_label: '' + label: false + lc: 2 + metal_level: M4 + mim_option: A + top_label: '' + wc: 2 + function_name: cap_mim + info: {} + info_version: 2 + module: gf180.cap_mim + name: cap_mim diff --git a/tests/test_components/test_pdk_settings_cap_mos_.yml b/tests/test_components/test_pdk_settings_cap_mos_.yml index 005ff47..99daf45 100644 --- a/tests/test_components/test_pdk_settings_cap_mos_.yml +++ b/tests/test_components/test_pdk_settings_cap_mos_.yml @@ -4,21 +4,21 @@ settings: changed: {} child: null default: - deepnwell: 0 + deepnwell: false g_label: '' - label: 0 + label: false lc: 0.1 - pcmpgr: 0 + pcmpgr: false sd_label: '' type: cap_nmos volt: 3.3V wc: 0.1 full: - deepnwell: 0 + deepnwell: false g_label: '' - label: 0 + label: false lc: 0.1 - pcmpgr: 0 + pcmpgr: false sd_label: '' type: cap_nmos volt: 3.3V diff --git a/tests/test_components/test_pdk_settings_cap_mos_inst_.yml b/tests/test_components/test_pdk_settings_cap_mos_inst_.yml index ef57c71..299518a 100644 --- a/tests/test_components/test_pdk_settings_cap_mos_inst_.yml +++ b/tests/test_components/test_pdk_settings_cap_mos_inst_.yml @@ -14,7 +14,7 @@ settings: implant_layer: - 32 - 0 - label: 0 + label: false lc: 0.1 pl_ext: 0.1 pl_l: 0.1 @@ -30,7 +30,7 @@ settings: implant_layer: - 32 - 0 - label: 0 + label: false lc: 0.1 pl_ext: 0.1 pl_l: 0.1 diff --git a/tests/test_components/test_pdk_settings_diode_dw2ps_.yml b/tests/test_components/test_pdk_settings_diode_dw2ps_.yml index 579a014..9b2375b 100644 --- a/tests/test_components/test_pdk_settings_diode_dw2ps_.yml +++ b/tests/test_components/test_pdk_settings_diode_dw2ps_.yml @@ -6,19 +6,19 @@ settings: default: cw: 0.1 la: 0.1 - label: 0 + label: false n_label: '' p_label: '' - pcmpgr: 0 + pcmpgr: false volt: 3.3V wa: 0.1 full: cw: 0.1 la: 0.1 - label: 0 + label: false n_label: '' p_label: '' - pcmpgr: 0 + pcmpgr: false volt: 3.3V wa: 0.1 function_name: diode_dw2ps diff --git a/tests/test_components/test_pdk_settings_diode_nd2ps_.yml b/tests/test_components/test_pdk_settings_diode_nd2ps_.yml index f1f7350..07ac9ec 100644 --- a/tests/test_components/test_pdk_settings_diode_nd2ps_.yml +++ b/tests/test_components/test_pdk_settings_diode_nd2ps_.yml @@ -5,22 +5,22 @@ settings: child: null default: cw: 0.1 - deepnwell: 0 + deepnwell: false la: 0.1 - label: 0 + label: false n_label: '' p_label: '' - pcmpgr: 0 + pcmpgr: false volt: 3.3V wa: 0.1 full: cw: 0.1 - deepnwell: 0 + deepnwell: false la: 0.1 - label: 0 + label: false n_label: '' p_label: '' - pcmpgr: 0 + pcmpgr: false volt: 3.3V wa: 0.1 function_name: diode_nd2ps diff --git a/tests/test_components/test_pdk_settings_diode_nw2ps_.yml b/tests/test_components/test_pdk_settings_diode_nw2ps_.yml index 9fe5d87..7ee3817 100644 --- a/tests/test_components/test_pdk_settings_diode_nw2ps_.yml +++ b/tests/test_components/test_pdk_settings_diode_nw2ps_.yml @@ -6,7 +6,7 @@ settings: default: cw: 0.1 la: 0.1 - label: 0 + label: false n_label: '' p_label: '' volt: 3.3V @@ -14,7 +14,7 @@ settings: full: cw: 0.1 la: 0.1 - label: 0 + label: false n_label: '' p_label: '' volt: 3.3V diff --git a/tests/test_components/test_pdk_settings_diode_pw2dw_.yml b/tests/test_components/test_pdk_settings_diode_pw2dw_.yml index 4dcfe32..f90aa35 100644 --- a/tests/test_components/test_pdk_settings_diode_pw2dw_.yml +++ b/tests/test_components/test_pdk_settings_diode_pw2dw_.yml @@ -6,19 +6,19 @@ settings: default: cw: 0.1 la: 0.1 - label: 0 + label: false n_label: '' p_label: '' - pcmpgr: 0 + pcmpgr: false volt: 3.3V wa: 0.1 full: cw: 0.1 la: 0.1 - label: 0 + label: false n_label: '' p_label: '' - pcmpgr: 0 + pcmpgr: false volt: 3.3V wa: 0.1 function_name: diode_pw2dw diff --git a/tests/test_components/test_pdk_settings_labels_gen_.yml b/tests/test_components/test_pdk_settings_labels_gen_.yml index 1235c87..9f314c1 100644 --- a/tests/test_components/test_pdk_settings_labels_gen_.yml +++ b/tests/test_components/test_pdk_settings_labels_gen_.yml @@ -5,25 +5,25 @@ settings: child: null default: index: 0 + label: false + label_str: '' + label_valid_len: 1 labels: null layer: - 34 - 10 - label: 0 - label_str: '' - label_valid_len: 1 position: - 0.1 - 0.1 full: index: 0 + label: false + label_str: '' + label_valid_len: 1 labels: null layer: - 34 - 10 - label: 0 - label_str: '' - label_valid_len: 1 position: - 0.1 - 0.1 diff --git a/tests/test_components/test_pdk_settings_nfet_.yml b/tests/test_components/test_pdk_settings_nfet_.yml index 0c6ee3f..61b5f10 100644 --- a/tests/test_components/test_pdk_settings_nfet_.yml +++ b/tests/test_components/test_pdk_settings_nfet_.yml @@ -13,10 +13,10 @@ settings: inter_sd_l: 0.24 interdig: 0 l_gate: 0.28 - label: 0 + label: false nf: 1 patt: '' - patt_label: 0 + patt_label: false pcmpgr: 0 sd_con_col: 1 sd_label: [] @@ -33,10 +33,10 @@ settings: inter_sd_l: 0.24 interdig: 0 l_gate: 0.28 - label: 0 + label: false nf: 1 patt: '' - patt_label: 0 + patt_label: false pcmpgr: 0 sd_con_col: 1 sd_label: [] diff --git a/tests/test_components/test_pdk_settings_nfet_06v0_nvt_.yml b/tests/test_components/test_pdk_settings_nfet_06v0_nvt_.yml index 695c377..cb6fe53 100644 --- a/tests/test_components/test_pdk_settings_nfet_06v0_nvt_.yml +++ b/tests/test_components/test_pdk_settings_nfet_06v0_nvt_.yml @@ -12,10 +12,10 @@ settings: inter_sd_l: 0.24 interdig: 0 l_gate: 1.8 - label: 0 + label: false nf: 1 patt: '' - patt_label: 0 + patt_label: false sd_con_col: 1 sd_label: [] sub_label: '' @@ -29,10 +29,10 @@ settings: inter_sd_l: 0.24 interdig: 0 l_gate: 1.8 - label: 0 + label: false nf: 1 patt: '' - patt_label: 0 + patt_label: false sd_con_col: 1 sd_label: [] sub_label: '' diff --git a/tests/test_components/test_pdk_settings_nfet_deep_nwell_.yml b/tests/test_components/test_pdk_settings_nfet_deep_nwell_.yml index 29e4040..9460f25 100644 --- a/tests/test_components/test_pdk_settings_nfet_deep_nwell_.yml +++ b/tests/test_components/test_pdk_settings_nfet_deep_nwell_.yml @@ -4,23 +4,23 @@ settings: changed: {} child: null default: - deepnwell: 0 + deepnwell: false grw: 0.36 inst_size: - 0.1 - 0.1 inst_xmin: 0.1 inst_ymin: 0.1 - pcmpgr: 0 + pcmpgr: false full: - deepnwell: 0 + deepnwell: false grw: 0.36 inst_size: - 0.1 - 0.1 inst_xmin: 0.1 inst_ymin: 0.1 - pcmpgr: 0 + pcmpgr: false function_name: nfet_deep_nwell info: {} info_version: 2 diff --git a/tests/test_components/test_pdk_settings_nplus_res_.yml b/tests/test_components/test_pdk_settings_nplus_res_.yml index d27f136..e1bfeda 100644 --- a/tests/test_components/test_pdk_settings_nplus_res_.yml +++ b/tests/test_components/test_pdk_settings_nplus_res_.yml @@ -4,25 +4,25 @@ settings: changed: {} child: null default: - deepnwell: 0 + deepnwell: false l_res: 0.1 - label: 0 - pcmpgr: 0 + label: false + pcmpgr: false r0_label: '' r1_label: '' res_type: nplus_s - sub: 0 + sub: false sub_label: '' w_res: 0.1 full: - deepnwell: 0 + deepnwell: false l_res: 0.1 - label: 0 - pcmpgr: 0 + label: false + pcmpgr: false r0_label: '' r1_label: '' res_type: nplus_s - sub: 0 + sub: false sub_label: '' w_res: 0.1 function_name: nplus_res diff --git a/tests/test_components/test_pdk_settings_npolyf_res_.yml b/tests/test_components/test_pdk_settings_npolyf_res_.yml index 74d3309..610ffca 100644 --- a/tests/test_components/test_pdk_settings_npolyf_res_.yml +++ b/tests/test_components/test_pdk_settings_npolyf_res_.yml @@ -4,20 +4,20 @@ settings: changed: {} child: null default: - deepnwell: 0 + deepnwell: false l_res: 0.1 - label: 0 - pcmpgr: 0 + label: false + pcmpgr: false r0_label: '' r1_label: '' res_type: npolyf_s sub_label: '' w_res: 0.1 full: - deepnwell: 0 + deepnwell: false l_res: 0.1 - label: 0 - pcmpgr: 0 + label: false + pcmpgr: false r0_label: '' r1_label: '' res_type: npolyf_s diff --git a/tests/test_components/test_pdk_settings_pfet_deep_nwell_.yml b/tests/test_components/test_pdk_settings_pfet_deep_nwell_.yml index 8d1ede9..6945f73 100644 --- a/tests/test_components/test_pdk_settings_pfet_deep_nwell_.yml +++ b/tests/test_components/test_pdk_settings_pfet_deep_nwell_.yml @@ -4,7 +4,7 @@ settings: changed: {} child: null default: - deepnwell: 0 + deepnwell: false enc_size: - 0.1 - 0.1 @@ -12,9 +12,9 @@ settings: enc_ymin: 0.1 grw: 0.36 nw_enc_pcmp: 0.1 - pcmpgr: 0 + pcmpgr: false full: - deepnwell: 0 + deepnwell: false enc_size: - 0.1 - 0.1 @@ -22,7 +22,7 @@ settings: enc_ymin: 0.1 grw: 0.36 nw_enc_pcmp: 0.1 - pcmpgr: 0 + pcmpgr: false function_name: pfet_deep_nwell info: {} info_version: 2 diff --git a/tests/test_components/test_pdk_settings_plus_res_inst_.yml b/tests/test_components/test_pdk_settings_plus_res_inst_.yml index b42f932..70434eb 100644 --- a/tests/test_components/test_pdk_settings_plus_res_inst_.yml +++ b/tests/test_components/test_pdk_settings_plus_res_inst_.yml @@ -10,11 +10,11 @@ settings: cmp_res_ext: 0.1 con_enc: 0.1 l_res: 0.1 - label: 0 + label: false r0_label: '' r1_label: '' res_type: nplus_s - sub: 0 + sub: false sub_imp_layer: - 31 - 0 @@ -27,11 +27,11 @@ settings: cmp_res_ext: 0.1 con_enc: 0.1 l_res: 0.1 - label: 0 + label: false r0_label: '' r1_label: '' res_type: nplus_s - sub: 0 + sub: false sub_imp_layer: - 31 - 0 diff --git a/tests/test_components/test_pdk_settings_polyf_res_inst_.yml b/tests/test_components/test_pdk_settings_polyf_res_inst_.yml index 996883b..a124d76 100644 --- a/tests/test_components/test_pdk_settings_polyf_res_inst_.yml +++ b/tests/test_components/test_pdk_settings_polyf_res_inst_.yml @@ -6,7 +6,7 @@ settings: default: con_enc: 0.1 l_res: 0.1 - label: 0 + label: false pl_imp_layer: - 32 - 0 @@ -22,7 +22,7 @@ settings: full: con_enc: 0.1 l_res: 0.1 - label: 0 + label: false pl_imp_layer: - 32 - 0 diff --git a/tests/test_components/test_pdk_settings_pplus_res_.yml b/tests/test_components/test_pdk_settings_pplus_res_.yml index d20b80b..f40441c 100644 --- a/tests/test_components/test_pdk_settings_pplus_res_.yml +++ b/tests/test_components/test_pdk_settings_pplus_res_.yml @@ -4,25 +4,25 @@ settings: changed: {} child: null default: - deepnwell: 0 + deepnwell: false l_res: 0.1 - label: 0 - pcmpgr: 0 + label: false + pcmpgr: false r0_label: '' r1_label: '' res_type: pplus_s - sub: 0 + sub: false sub_label: '' w_res: 0.1 full: - deepnwell: 0 + deepnwell: false l_res: 0.1 - label: 0 - pcmpgr: 0 + label: false + pcmpgr: false r0_label: '' r1_label: '' res_type: pplus_s - sub: 0 + sub: false sub_label: '' w_res: 0.1 function_name: pplus_res diff --git a/tests/test_components/test_pdk_settings_ppolyf_res_.yml b/tests/test_components/test_pdk_settings_ppolyf_res_.yml index f2dee56..3af7ad5 100644 --- a/tests/test_components/test_pdk_settings_ppolyf_res_.yml +++ b/tests/test_components/test_pdk_settings_ppolyf_res_.yml @@ -4,20 +4,20 @@ settings: changed: {} child: null default: - deepnwell: 0 + deepnwell: false l_res: 0.1 - label: 0 - pcmpgr: 0 + label: false + pcmpgr: false r0_label: '' r1_label: '' res_type: ppolyf_s sub_label: '' w_res: 0.1 full: - deepnwell: 0 + deepnwell: false l_res: 0.1 - label: 0 - pcmpgr: 0 + label: false + pcmpgr: false r0_label: '' r1_label: '' res_type: ppolyf_s diff --git a/tests/test_components/test_pdk_settings_ppolyf_u_high_Rs_res_.yml b/tests/test_components/test_pdk_settings_ppolyf_u_high_Rs_res_.yml index c413d81..cc79cda 100644 --- a/tests/test_components/test_pdk_settings_ppolyf_u_high_Rs_res_.yml +++ b/tests/test_components/test_pdk_settings_ppolyf_u_high_Rs_res_.yml @@ -4,20 +4,20 @@ settings: changed: {} child: null default: - deepnwell: 0 + deepnwell: false l_res: 0.42 - label: 0 - pcmpgr: 0 + label: false + pcmpgr: false r0_label: '' r1_label: '' sub_label: '' volt: 3.3V w_res: 0.42 full: - deepnwell: 0 + deepnwell: false l_res: 0.42 - label: 0 - pcmpgr: 0 + label: false + pcmpgr: false r0_label: '' r1_label: '' sub_label: '' diff --git a/tests/test_components/test_pdk_settings_res_.yml b/tests/test_components/test_pdk_settings_res_.yml index cf72bd0..5575679 100644 --- a/tests/test_components/test_pdk_settings_res_.yml +++ b/tests/test_components/test_pdk_settings_res_.yml @@ -5,14 +5,14 @@ settings: child: null default: l_res: 0.1 - label: 0 + label: false r0_label: '' r1_label: '' res_type: rm1 w_res: 0.1 full: l_res: 0.1 - label: 0 + label: false r0_label: '' r1_label: '' res_type: rm1 diff --git a/tests/test_components/test_pdk_settings_sc_diode_.yml b/tests/test_components/test_pdk_settings_sc_diode_.yml index 1926c6c..d2787ff 100644 --- a/tests/test_components/test_pdk_settings_sc_diode_.yml +++ b/tests/test_components/test_pdk_settings_sc_diode_.yml @@ -6,20 +6,20 @@ settings: default: cw: 0.1 la: 0.1 - label: 0 + label: false m: 1 n_label: '' p_label: '' - pcmpgr: 0 + pcmpgr: false wa: 0.1 full: cw: 0.1 la: 0.1 - label: 0 + label: false m: 1 n_label: '' p_label: '' - pcmpgr: 0 + pcmpgr: false wa: 0.1 function_name: sc_diode info: {} diff --git a/tests/test_components/test_pdk_settings_well_res_.yml b/tests/test_components/test_pdk_settings_well_res_.yml index a614c55..4eb5464 100644 --- a/tests/test_components/test_pdk_settings_well_res_.yml +++ b/tests/test_components/test_pdk_settings_well_res_.yml @@ -5,8 +5,8 @@ settings: child: null default: l_res: 0.42 - label: 0 - pcmpgr: 0 + label: false + pcmpgr: false r0_label: '' r1_label: '' res_type: nwell @@ -14,8 +14,8 @@ settings: w_res: 0.42 full: l_res: 0.42 - label: 0 - pcmpgr: 0 + label: false + pcmpgr: false r0_label: '' r1_label: '' res_type: nwell