From 4ce89e4df339a3ea8bb9a1b087b2b50989f8885d Mon Sep 17 00:00:00 2001
From: Glen Nicholls <Glen.Nicholls@kratosdefense.com>
Date: Tue, 12 Nov 2019 16:38:46 -0700
Subject: [PATCH 1/8] Adding snippets per ghdl/ghdl-language-server/issues/32

---
 vscode-client/snippets.vhdl.json | 317 ++++++++++++++++++++++++++++---
 1 file changed, 287 insertions(+), 30 deletions(-)

diff --git a/vscode-client/snippets.vhdl.json b/vscode-client/snippets.vhdl.json
index 3bed3c8..411eb71 100644
--- a/vscode-client/snippets.vhdl.json
+++ b/vscode-client/snippets.vhdl.json
@@ -2,77 +2,334 @@
 	"Library": {
 		"prefix": "library",
 		"body": [ "library ${1:ieee};"],
-		"description": "library"
+		"description": "keyword: library"
 	},
 	"Use": {
 		"prefix": "use",
 		"body": [ "use ${1:ieee.std_logic_1164}.all;"],
-		"description": "use clause"
+		"description": "keyword: use"
+	},
+	"Context": {
+		"prefix": "context 2008",
+		"body": [ "context ${1:ieee}.${2:ieee_std_context};"],
+		"description": "keyword: context (vhdl 2008)"
+	},
+	"Others": {
+		"prefix": ["others"],
+		"body": ["(others => ${1:<value>})${2|,;|}"],
+		"description": "keyword: others"
+	},
+	"Elsif": {
+		"prefix": "elsif",
+		"body": [
+			"elsif ${1:expression} then",
+			"\t$0"
+		],
+		"description": "keyword: elsif"
+	},
+	"Elsif Generate 2008": {
+		"prefix": "elsif_generate_2008",
+		"body": [
+			"elsif ${1:expression} generate",
+			"\t${2}"
+		],
+		"description": "keyword: elsif generate (vhdl 2008)"
+	},
+	"When": {
+		"prefix": "when",
+		"body": [
+			"when ${1:signal} =>",
+			"\t$0"
+		],
+		"description": "keyword: when"
+	},
+
+
+	"IEEE Libraries": {
+		"prefix": "library ieee",
+		"body": [
+			"library ieee;",
+			"use std_logic_1164.all;",
+			"use numeric_std.all;",
+			"use math_real.all;"
+		],
+		"description": "<TODO>: declare common IEEE libraries"
+	},
+	"IEEE Libraries 2008": {
+		"prefix": "library ieee 2008",
+		"body": [
+			"library ieee;",
+			"text ieee.ieee_std_context;",
+			"use math_real.all;"
+		],
+		"description": "<TODO>: declare common IEEE libraries (vhdl 2008)"
+	},
+
+
+	"Component": {
+		"prefix":"component",
+		"body": [
+			"component ${1:entity} is",
+			"\tgeneric (",
+			"\t\t${2:generics}",
+			"\t);",
+			"\tport (",
+			"\t\t${3:clk   : in std_logic;}",
+			"\t\t${4:reset : in std_logic}",
+			"\t\t$0",
+			"\t);",
+			"end component;"
+		],
+		"description": "instantiation: component declaration"
 	},
 	"Entity": {
 	"prefix": "entity",
 		"body": [
 			"entity ${1:$TM_FILENAME_BASE} is",
-			"  port (${2:ports});",
-		    "end ${1};"
+			"\tgeneric (",
+			"\t\t${2:generics}",
+			"\t);",
+			"\tport (",
+			"\t\t${3:clk   : in std_logic;}",
+			"\t\t${4:reset : in std_logic}",
+			"\t\t$0",
+			"\t);",
+		    "end entity;"
 		],
-		"description": "entity"
+		"description": "instantiation: entity"
 	},
 	"Architecture": {
 		"prefix": "architecture",
 		"body": [
 			"architecture ${1:behav} of ${2:$TM_FILENAME_BASE} is",
 			"begin",
-			"end ${1};"
+			"end architecture;"
+		],
+		"description": "instantiation: architecture"
+	},
+
+
+	"If": {
+		"prefix": "if",
+		"body": [
+			"if ${1:expression} then",
+			"\t$0",
+			"end if;"
+		],
+		"description": "block: if"
+	},
+	"If/Else": {
+		"prefix": "if/else",
+		"body": [
+			"if ${1:expression} then",
+			"\t${2}",
+			"else",
+			"\t$0",
+			"end if;"
+		],
+		"description": "block: if/else"
+	},
+	"If Generate": {
+		"prefix": "if_generate",
+		"body": [
+			"gen_${1:generateName} : if ${2:expression} generate",
+			"\t$0",
+			"end generate;"
+		],
+		"description": "block: if generate"
+	},
+	"If/Else Generate 2008": {
+		"prefix": "if/else_generate_2008",
+		"body": [
+			"gen_${1:generateName} : if ${2:expression} generate",
+			"\t\t${3}",
+			"\telse generate",
+			"\t\t$0",
+			"end generate;"
+		],
+		"description": "block: if/else generate (vhdl 2008)"
+	},
+	"For": {
+		"prefix": "for",
+		"body": [
+			"for ${1:i} in ${2:0} ${3|to,downto|} ${4} loop",
+			"\t$0",
+			"end loop;"
+		],
+		"description": "block: for generate"
+	},
+	"For Generate": {
+		"prefix": "for_generate",
+		"body": [
+			"gen_loop_${1:generateName} : for ${2:i} in ${3:0} ${4|to,downto|} ${5} generate",
+			"\t$0",
+			"end generate;"
+		],
+		"description": "block: for generate loop (vhdl 2008)"
+	},
+	"While": {
+		"prefix": "while",
+		"body": [
+			"while ${1:expression} loop",
+			"\t$0",
+			"end loop;"
+		],
+		"description": "block: while loop"
+	},
+	"Case": {
+		"prefix": "case",
+		"body": [
+			"case ${1:select} is",
+			"\twhen ${2:value} =>",
+			"\t\t${3}",
+			"\twhen others =>",
+			"\t\t$0",
+			"end case;"
+		],
+		"description": "block: case"
+	},
+	"Case Generate 2008": {
+		"prefix": "case_generate_2008",
+		"body": [
+			"gen_${1:generateName} : case ${1:select} generate",
+			"\twhen ${2:value} =>",
+			"\t\t${3}",
+			"\twhen others =>",
+			"\t\t$0",
+			"end generate;"
+		],
+		"description": "block: case generate (vhdl 2008)"
+	},
+	"Block": {
+		"prefix": "block",
+		"body": [
+			"blk_${1:blockName} : block",
+			"begin",
+			"\t$0",
+			"end block;"
 		],
-		"description": "architecture"
+		"description": "block: block"
 	},
 	"Process": {
 		"prefix": "process",
 		"body": [
 			"process",
 			"begin",
+			"\t$0",
 			"end process;"
-		]
+		],
+		"description": "block: simple process"
+	},
+	"Async Process": {
+		"prefix": "process_asynchronous",
+		"body": [
+			"process (${1:clk}, ${2:reset})",
+			"begin",
+			"\tif ${2} = ${3|'1','0'|} then",
+			"\telsif rising_edge(${1}) then",
+			"\t\t$0",
+			"\tend if;",
+			"end process;"
+		],
+		"description": "block: asynchronous process"
+	},
+	"Clocked Process": {
+		"prefix": ["process_clocked"],
+		"body": [
+			"process (${1:clk})",
+			"begin",
+			"\tif rising_edge(${1}) then",
+			"\t\tif ${2:reset} = ${3|'1','0'|} then",
+			"\t\t\t$0",
+			"\t\telse",
+			"\t\t\t$0",
+			"\t\tend if;",
+			"\tend if;",
+			"end process;"
+		],
+		"description": "block: clocked process"
+	},
+	"Function": {
+		"prefix": "function",
+		"body": [
+			"function ${1:name} (${2:params}) return ${3:type} is",
+			"begin",
+			"\t$0",
+			"end function;"
+		],
+		"description": "block: function body"
 	},
 	"Procedure": {
 		"prefix": "procedure",
 		"body": [
 			"procedure ${1:name} (${2:params}) is",
 			"begin",
-			"end ${1};"
+			"\t$0",
+			"end procedure;"
 		],
-		"description": "procedure body"
+		"description": "block: procedure body"
 	},
 	"Package": {
 		"prefix": "package",
 		"body": [
 			"package ${1:name} is",
-			"end ${1};"
+			"end package;"
 		],
-		"description": "package declaration"
+		"description": "block: package declaration"
 	},
-	"PackageBody": {
-		"prefix": "package",
+	"Package Body": {
+		"prefix": "package_body",
 		"body": [
 			"package body ${1:name} is",
-			"end ${1};"
+			"end package;"
 		],
-		"description": "package body"
+		"description": "block: package body"
 	},
-	"Component": {
-		"prefix":"component",
-		"body": [
-		"component ${1:entity} is",
-		"	generic(",
-		"		${2:generics}",
-		"	);",
-		"	port(",
-		"		${3:ports}",
-		"	);",
-		"end component;"
-		],
-		"description": "component declaration"
+	"Natural Range": {
+		"prefix": "natural_range",
+		"body": [ "natural range<>" ],
+		"description": "block: natural range"
+	},
+
+
+	"Real": {
+		"prefix": "real",
+		"body": [ "real${1|, := ,;|}" ],
+		"description": "type: real"
+	},
+	"Integer": {
+		"prefix": "integer",
+		"body": [ "integer${1|, := ,;|}" ],
+		"description": "type: integer"
+	},
+	"Natural": {
+		"prefix": "natural",
+		"body": [ "natural${1|, := ,;|}" ],
+		"description": "type: natural"
+	},
+	"Positive": {
+		"prefix": "positive",
+		"body": [ "positive${1|, := ,;|}" ],
+		"description": "type: positive"
+	},
+	"Standard Logic": {
+		"prefix": ["std_logic", "sl"],
+		"body": [ "std_logic${1|, := ,;|}" ],
+		"description": "type: std_logic"
+	},
+	"Standard Logic Vector": {
+		"prefix": ["std_logic_vector", "slv"],
+		"body": [ "std_logic_vector(${1} ${2|downto,to|} ${3})${4|, := ,;|}" ],
+		"description": "type: std_logic_vector"
+	},
+	"Signed": {
+		"prefix": "signed",
+		"body": [ "signed(${1} ${2|downto,to|} ${3})${4|, := ,;|}" ],
+		"description": "type: signed"
+	},
+	"Unsigned": {
+		"prefix": "unsigned",
+		"body": [ "unsigned(${1} ${2|downto,to|} ${3})${4|,;|}" ],
+		"description": "type: unsigned"
 	}
 }
-

From 899e3b39418ce291c9a2292800f88f845b14d995 Mon Sep 17 00:00:00 2001
From: Glen Nicholls <Glen.Nicholls@kratosdefense.com>
Date: Tue, 12 Nov 2019 18:58:59 -0700
Subject: [PATCH 2/8] more snippets added for
 ghdl/ghdl-language-server/issues/32

---
 vscode-client/snippets.vhdl.json | 222 +++++++++++++++++++++++--------
 1 file changed, 170 insertions(+), 52 deletions(-)

diff --git a/vscode-client/snippets.vhdl.json b/vscode-client/snippets.vhdl.json
index 411eb71..0591033 100644
--- a/vscode-client/snippets.vhdl.json
+++ b/vscode-client/snippets.vhdl.json
@@ -2,67 +2,147 @@
 	"Library": {
 		"prefix": "library",
 		"body": [ "library ${1:ieee};"],
-		"description": "keyword: library"
+		"description": "library declaration"
+	},
+	"Library TextIO": {
+		"prefix": "library_textio",
+		"body": [
+			"library std;",
+			"use std.textio.all;"
+		],
+		"description": "TextIO library declaration"
+	},
+	"IEEE Libraries": {
+		"prefix": "library_ieee",
+		"body": [
+			"library ieee;",
+			"use ieee.std_logic_1164.all;",
+			"use ieee.numeric_std.all;",
+			"use ieee.math_real.all;"
+		],
+		"description": "common IEEE libraries declaration"
+	},
+	"IEEE Libraries 2008": {
+		"prefix": "library_ieee_2008",
+		"body": [
+			"library ieee;",
+			"text ieee.ieee_std_context;",
+			"use ieee.math_real.all;"
+		],
+		"description": "common IEEE libraries declaration with 2008 standard context (vhdl 2008)"
 	},
 	"Use": {
 		"prefix": "use",
-		"body": [ "use ${1:ieee.std_logic_1164}.all;"],
-		"description": "keyword: use"
+		"body": [ "use ${1:lib.pkg}.all;"],
+		"description": "use clause"
+	},
+	"Use IEEE Package": {
+		"prefix": "use_ieee",
+		"body": [ "use ieee.${1|$std_logic_1164,std_logic_textio,numeric_std,math_real,math_complex|}.all;"],
+		"description": "use clause IEEE standard package (std_logic_1164,std_logic_textio,numeric_std,math_real,math_complex)"
 	},
-	"Context": {
-		"prefix": "context 2008",
-		"body": [ "context ${1:ieee}.${2:ieee_std_context};"],
-		"description": "keyword: context (vhdl 2008)"
+	"Context 2008": {
+		"prefix": "context_2008",
+		"body": [ "context ${1:lib.context};"],
+		"description": "context clause (vhdl 2008)"
+	},
+	"Context IEEE 2008": {
+		"prefix": "context_ieee_2008",
+		"body": [ "context ieee.${1|ieee_bit_context,ieee_std_context|};"],
+		"description": "context clause for IEEE standard contexts (ieee_bit_context,ieee_std_context) (vhdl 2008)"
 	},
 	"Others": {
 		"prefix": ["others"],
 		"body": ["(others => ${1:<value>})${2|,;|}"],
-		"description": "keyword: others"
+		"description": "others keyword"
 	},
-	"Elsif": {
-		"prefix": "elsif",
+	"When": {
+		"prefix": "when",
 		"body": [
-			"elsif ${1:expression} then",
+			"when ${1:value} =>",
 			"\t$0"
 		],
-		"description": "keyword: elsif"
+		"description": "when statement"
 	},
-	"Elsif Generate 2008": {
-		"prefix": "elsif_generate_2008",
+	"When Else": {
+		"prefix": "when_else",
 		"body": [
-			"elsif ${1:expression} generate",
-			"\t${2}"
+			"${1:signal} <= ${2:first_value} when ${3:expression}",
+			"\telse ${4:final_value};"
 		],
-		"description": "keyword: elsif generate (vhdl 2008)"
+		"description": "concurrent when else statement"
 	},
-	"When": {
-		"prefix": "when",
+	"With Select": {
+		"prefix": ["select", "with_select"],
 		"body": [
-			"when ${1:signal} =>",
-			"\t$0"
+			"with ${1:select} select",
+			"\t${2:signal} <= ${3:first_value} when ${4:select_value},",
+			"\t\t${5:last_value} when others;"
 		],
-		"description": "keyword: when"
+		"description": "concurrent with select statement"
 	},
-
-
-	"IEEE Libraries": {
-		"prefix": "library ieee",
+	"Alias": {
+		"prefix": "alias",
+		"body": [ "alias ${1:alias_name} : ${2:alias_type} is ${3:object_name};" ],
+		"description": "alias declaration"
+	},
+	"Alias External Name 2008": {
+		"prefix": "alias_external_name_2008",
 		"body": [
-			"library ieee;",
-			"use std_logic_1164.all;",
-			"use numeric_std.all;",
-			"use math_real.all;"
+			"alias ${1:name} is",
+			"\t<< ${2|signal,variable,constant|} ${3:path.to.signal.name} : ${4:type} >>;"
 		],
-		"description": "<TODO>: declare common IEEE libraries"
+		"description": "hierarchical signal declaration (vhdl 2008). NOTE: for standard types (SLV, unsighed, signed, etc.), no range needs to be specified"
 	},
-	"IEEE Libraries 2008": {
-		"prefix": "library ieee 2008",
+	"Attribute": {
+		"prefix": ["attribute", "'"],
+		"body": [ "'${1|high,low,left,right,range,reverse_range,length,event|}" ],
+		"description": "synthesizable attributes (high,low,left,right,range,reverse_range,length,event)"
+	},
+	"Array Type": {
+		"prefix": "array",
+		"body": [ "type ${1:type_name} is array (${2:natural range<>}) of ${3:element_type};" ],
+		"description": "synthesizable attributes (high,low,left,right,range,reverse_range,length,event)"
+	},
+	"Assert Statement": {
+		"prefix": "assert",
 		"body": [
-			"library ieee;",
-			"text ieee.ieee_std_context;",
-			"use math_real.all;"
+			"assert ${1:expression}",
+			"\treport \"${2:string}\"",
+			"\tseverity ${3|note,warning,error,failure|}"
+		 ],
+		"description": "assert statement"
+	},
+	"Constant": {
+		"prefix": "constant",
+		"body": [ "constant ${1:name} : ${2:type} := ${3:default_value};" ],
+		"description": "constant declaration"
+	},
+	"File": {
+		"prefix": "file",
+		"body": [ "file ${1:name} : text is ${2|in,out|} \"${3:file_name}\";" ],
+		"description": "constant declaration"
+	},
+	// TODO: somehow incorporate standard types
+	"Signal": {
+		"prefix": "signal",
+		"body": [ "signal ${1:name} : ${2:type} := ${3:default_value};" ],
+		"description": "signal declaration"
+	},
+	"Variable": {
+		"prefix": "variable",
+		"body": [ "variable ${1:name} : ${2:type} := ${3:default_value};" ],
+		"description": "variable declaration"
+	},
+	// TODO: should record just insert cursor instead of aiding user in filling in signals
+	"Record Type": {
+		"prefix": "record",
+		"body": [
+			"type ${1:name} is record",
+			"\t${2:signal_name} : ${3:type};",
+			"end record;"
 		],
-		"description": "<TODO>: declare common IEEE libraries (vhdl 2008)"
+		"description": "record declaration"
 	},
 
 
@@ -82,6 +162,7 @@
 		],
 		"description": "instantiation: component declaration"
 	},
+	// TODO: configuration
 	"Entity": {
 	"prefix": "entity",
 		"body": [
@@ -107,8 +188,19 @@
 		],
 		"description": "instantiation: architecture"
 	},
+	"Block": {
+		"prefix": "block",
+		"body": [
+			"blk_${1:blockName} : block ${2|,optional_guard_expression|}",
+			"begin",
+			"\t$0",
+			"end block;"
+		],
+		"description": "block: block"
+	},
 
 
+	// TODO: package generic vhdl 2008
 	"If": {
 		"prefix": "if",
 		"body": [
@@ -129,6 +221,14 @@
 		],
 		"description": "block: if/else"
 	},
+	"Elsif": {
+		"prefix": "elsif",
+		"body": [
+			"elsif ${1:expression} then",
+			"\t$0"
+		],
+		"description": "keyword: elsif"
+	},
 	"If Generate": {
 		"prefix": "if_generate",
 		"body": [
@@ -149,10 +249,18 @@
 		],
 		"description": "block: if/else generate (vhdl 2008)"
 	},
+	"Elsif Generate 2008": {
+		"prefix": "elsif_generate_2008",
+		"body": [
+			"elsif ${1:expression} generate",
+			"\t${2}"
+		],
+		"description": "keyword: elsif generate (vhdl 2008)"
+	},
 	"For": {
 		"prefix": "for",
 		"body": [
-			"for ${1:i} in ${2:0} ${3|to,downto|} ${4} loop",
+			"${1|,${2:optional_label}|}for ${3:i} in ${4|${5:user_range},$5 to $6, $5 downto $6|} loop",
 			"\t$0",
 			"end loop;"
 		],
@@ -161,7 +269,7 @@
 	"For Generate": {
 		"prefix": "for_generate",
 		"body": [
-			"gen_loop_${1:generateName} : for ${2:i} in ${3:0} ${4|to,downto|} ${5} generate",
+			"gen_loop_${1:generateName} : for ${2:i} in ${3|${4:user_range},$4 to $5,$4 downto $5|} generate",
 			"\t$0",
 			"end generate;"
 		],
@@ -183,7 +291,7 @@
 			"\twhen ${2:value} =>",
 			"\t\t${3}",
 			"\twhen others =>",
-			"\t\t$0",
+			"\t\t${4:null}",
 			"end case;"
 		],
 		"description": "block: case"
@@ -195,32 +303,32 @@
 			"\twhen ${2:value} =>",
 			"\t\t${3}",
 			"\twhen others =>",
-			"\t\t$0",
+			"\t\t${4:null}",
 			"end generate;"
 		],
 		"description": "block: case generate (vhdl 2008)"
 	},
-	"Block": {
-		"prefix": "block",
+	"Process Combinatorial": {
+		"prefix": "process_combinatorial",
 		"body": [
-			"blk_${1:blockName} : block",
+			"process ${1|,(${2:sensitvity_list})|}",
 			"begin",
 			"\t$0",
-			"end block;"
+			"end process;"
 		],
-		"description": "block: block"
+		"description": "block: combinatorial process"
 	},
-	"Process": {
-		"prefix": "process",
+	"Process Combinatorial 2008": {
+		"prefix": "process_combinatorial_2008",
 		"body": [
-			"process",
+			"process (all)",
 			"begin",
 			"\t$0",
 			"end process;"
 		],
-		"description": "block: simple process"
+		"description": "block: combinatorial process (vhdl 2008)"
 	},
-	"Async Process": {
+	"Process Asynchronous": {
 		"prefix": "process_asynchronous",
 		"body": [
 			"process (${1:clk}, ${2:reset})",
@@ -233,7 +341,7 @@
 		],
 		"description": "block: asynchronous process"
 	},
-	"Clocked Process": {
+	"Process Clocked": {
 		"prefix": ["process_clocked"],
 		"body": [
 			"process (${1:clk})",
@@ -317,11 +425,21 @@
 		"body": [ "std_logic${1|, := ,;|}" ],
 		"description": "type: std_logic"
 	},
+	"Standard ULogic": {
+		"prefix": ["std_ulogic", "sul"],
+		"body": [ "std_ulogic${1|, := ,;|}" ],
+		"description": "type: std_ulogic"
+	},
 	"Standard Logic Vector": {
 		"prefix": ["std_logic_vector", "slv"],
 		"body": [ "std_logic_vector(${1} ${2|downto,to|} ${3})${4|, := ,;|}" ],
 		"description": "type: std_logic_vector"
 	},
+	"Standard ULogic Vector": {
+		"prefix": ["std_ulogic_vector", "sulv"],
+		"body": [ "std_ulogic_vector(${1} ${2|downto,to|} ${3})${4|, := ,;|}" ],
+		"description": "type: std_ulogic_vector"
+	},
 	"Signed": {
 		"prefix": "signed",
 		"body": [ "signed(${1} ${2|downto,to|} ${3})${4|, := ,;|}" ],

From 1cde94f9c789d7dcfa5566f3b2fddba2542c2f63 Mon Sep 17 00:00:00 2001
From: Glen Nicholls <Glen.Nicholls@kratosdefense.com>
Date: Wed, 13 Nov 2019 22:08:49 -0700
Subject: [PATCH 3/8] fixed bugs in snippets and added todos

---
 vscode-client/snippets.vhdl.json | 301 +++++++++++++++++++------------
 1 file changed, 182 insertions(+), 119 deletions(-)

diff --git a/vscode-client/snippets.vhdl.json b/vscode-client/snippets.vhdl.json
index 0591033..567c4ba 100644
--- a/vscode-client/snippets.vhdl.json
+++ b/vscode-client/snippets.vhdl.json
@@ -1,14 +1,23 @@
 {
+	// TODO: add examples to anything that isn't obvious
+	// TODO: configuration (might be too annoying)
+	// ? alphabetize
+	// TODO: package generic vhdl 2008
+
 	"Library": {
 		"prefix": "library",
-		"body": [ "library ${1:ieee};"],
+		"body": [
+			"library ${1:ieee};",
+			"$0"
+		],
 		"description": "library declaration"
 	},
 	"Library TextIO": {
 		"prefix": "library_textio",
 		"body": [
 			"library std;",
-			"use std.textio.all;"
+			"use std.textio.all;",
+			"$0"
 		],
 		"description": "TextIO library declaration"
 	},
@@ -18,7 +27,8 @@
 			"library ieee;",
 			"use ieee.std_logic_1164.all;",
 			"use ieee.numeric_std.all;",
-			"use ieee.math_real.all;"
+			"use ieee.math_real.all;",
+			"$0"
 		],
 		"description": "common IEEE libraries declaration"
 	},
@@ -26,82 +36,115 @@
 		"prefix": "library_ieee_2008",
 		"body": [
 			"library ieee;",
-			"text ieee.ieee_std_context;",
-			"use ieee.math_real.all;"
+			"context ieee.ieee_std_context;",
+			"use ieee.math_real.all;",
+			"$0"
 		],
 		"description": "common IEEE libraries declaration with 2008 standard context (vhdl 2008)"
 	},
 	"Use": {
 		"prefix": "use",
-		"body": [ "use ${1:lib.pkg}.all;"],
+		"body": [
+			"use ${1:lib.pkg}.all;",
+			"$0"
+		],
 		"description": "use clause"
 	},
+	// TODO: move this up into library_ieee inst and give user option to include any of these
 	"Use IEEE Package": {
 		"prefix": "use_ieee",
-		"body": [ "use ieee.${1|$std_logic_1164,std_logic_textio,numeric_std,math_real,math_complex|}.all;"],
+		"body": [
+			"use ieee.${1|std_logic_1164,std_logic_textio,numeric_std,math_real,math_complex|}.all;",
+			"$0"
+		],
 		"description": "use clause IEEE standard package (std_logic_1164,std_logic_textio,numeric_std,math_real,math_complex)"
 	},
 	"Context 2008": {
 		"prefix": "context_2008",
-		"body": [ "context ${1:lib.context};"],
+		"body": [
+			"context ${1:lib.context_name};",
+			"$0"
+		],
 		"description": "context clause (vhdl 2008)"
 	},
 	"Context IEEE 2008": {
 		"prefix": "context_ieee_2008",
-		"body": [ "context ieee.${1|ieee_bit_context,ieee_std_context|};"],
+		"body": [
+			"context ieee.${1|ieee_bit_context,ieee_std_context|};",
+			"$0"
+		],
 		"description": "context clause for IEEE standard contexts (ieee_bit_context,ieee_std_context) (vhdl 2008)"
 	},
+	// FIXME: this needs to allow second option with space/;
 	"Others": {
 		"prefix": ["others"],
-		"body": ["(others => ${1:<value>})${2|,;|}"],
+		"body": [
+			"(others => ${1:<value>})${2| ,;|}",
+			"$0"
+		],
 		"description": "others keyword"
 	},
 	"When": {
 		"prefix": "when",
 		"body": [
-			"when ${1:value} =>",
+			"when ${1:others} =>",
 			"\t$0"
 		],
 		"description": "when statement"
 	},
+	// TODO: figure out how to column align when else after <= column
 	"When Else": {
 		"prefix": "when_else",
 		"body": [
 			"${1:signal} <= ${2:first_value} when ${3:expression}",
-			"\telse ${4:final_value};"
+			"\telse ${4:final_value};",
+			"$0"
 		],
 		"description": "concurrent when else statement"
 	},
+	// TODO: figure out how to column align with select after <= column
 	"With Select": {
 		"prefix": ["select", "with_select"],
 		"body": [
 			"with ${1:select} select",
 			"\t${2:signal} <= ${3:first_value} when ${4:select_value},",
-			"\t\t${5:last_value} when others;"
+			"\t\t${5:last_value} when others;",
+			"$0"
 		],
 		"description": "concurrent with select statement"
 	},
+	// TODO: add example
 	"Alias": {
 		"prefix": "alias",
-		"body": [ "alias ${1:alias_name} : ${2:alias_type} is ${3:object_name};" ],
+		"body": [
+			"alias ${1:alias_name} : ${2:alias_type} is ${3:object_name};",
+			"$0"
+		],
 		"description": "alias declaration"
 	},
+	// TODO: add example
+	// ? are signal/variable/constant all valid for external names
 	"Alias External Name 2008": {
 		"prefix": "alias_external_name_2008",
 		"body": [
 			"alias ${1:name} is",
-			"\t<< ${2|signal,variable,constant|} ${3:path.to.signal.name} : ${4:type} >>;"
+			"\t<< ${2|signal,variable,constant|} ${3:path.to.signal.name} : ${4:type} >>;",
+			"$0"
 		],
 		"description": "hierarchical signal declaration (vhdl 2008). NOTE: for standard types (SLV, unsighed, signed, etc.), no range needs to be specified"
 	},
+	// ! cannot use ' since it auto-closes
 	"Attribute": {
 		"prefix": ["attribute", "'"],
-		"body": [ "'${1|high,low,left,right,range,reverse_range,length,event|}" ],
+		"body": [ "'${1|high,low,left,right,range,reverse_range,length,event|}$0" ],
 		"description": "synthesizable attributes (high,low,left,right,range,reverse_range,length,event)"
 	},
 	"Array Type": {
 		"prefix": "array",
-		"body": [ "type ${1:type_name} is array (${2:natural range<>}) of ${3:element_type};" ],
+		"body": [
+			"type ${1:type_name} is array (${2:natural range<>}) of ${3:element_type};",
+			"$0"
+		],
 		"description": "synthesizable attributes (high,low,left,right,range,reverse_range,length,event)"
 	},
 	"Assert Statement": {
@@ -109,29 +152,42 @@
 		"body": [
 			"assert ${1:expression}",
 			"\treport \"${2:string}\"",
-			"\tseverity ${3|note,warning,error,failure|}"
+			"\tseverity ${3|note,warning,error,failure|};",
+			"$0"
 		 ],
 		"description": "assert statement"
 	},
 	"Constant": {
 		"prefix": "constant",
-		"body": [ "constant ${1:name} : ${2:type} := ${3:default_value};" ],
+		"body": [
+			"constant ${1:name} : ${2:type} := ${3:default_value};",
+			"$0"
+		],
 		"description": "constant declaration"
 	},
 	"File": {
 		"prefix": "file",
-		"body": [ "file ${1:name} : text is ${2|in,out|} \"${3:file_name}\";" ],
+		"body": [
+			"file ${1:name} : text is ${2|in,out|} \"${3:file_name}\";",
+			"$0"
+		],
 		"description": "constant declaration"
 	},
-	// TODO: somehow incorporate standard types
+	// TODO: report VSC bug that snippets are unavailable to select while filling out a snippet
 	"Signal": {
 		"prefix": "signal",
-		"body": [ "signal ${1:name} : ${2:type} := ${3:default_value};" ],
+		"body": [
+			"signal ${1:name} : ${2:type} := ${3:default_value};",
+			"$0"
+		],
 		"description": "signal declaration"
 	},
 	"Variable": {
 		"prefix": "variable",
-		"body": [ "variable ${1:name} : ${2:type} := ${3:default_value};" ],
+		"body": [
+			"variable ${1:name} : ${2:type} := ${3:default_value};",
+			"$0"
+		],
 		"description": "variable declaration"
 	},
 	// TODO: should record just insert cursor instead of aiding user in filling in signals
@@ -140,6 +196,7 @@
 		"body": [
 			"type ${1:name} is record",
 			"\t${2:signal_name} : ${3:type};",
+			"\t$0",
 			"end record;"
 		],
 		"description": "record declaration"
@@ -149,20 +206,20 @@
 	"Component": {
 		"prefix":"component",
 		"body": [
-			"component ${1:entity} is",
+			"component ${1:comp_name} is",
 			"\tgeneric (",
 			"\t\t${2:generics}",
 			"\t);",
 			"\tport (",
 			"\t\t${3:clk   : in std_logic;}",
-			"\t\t${4:reset : in std_logic}",
+			"\t\t${4:reset : in std_logic;}",
 			"\t\t$0",
 			"\t);",
 			"end component;"
 		],
-		"description": "instantiation: component declaration"
+		"description": "component declaration"
 	},
-	// TODO: configuration
+	// TODO: fill in notes
 	"Entity": {
 	"prefix": "entity",
 		"body": [
@@ -172,35 +229,36 @@
 			"\t);",
 			"\tport (",
 			"\t\t${3:clk   : in std_logic;}",
-			"\t\t${4:reset : in std_logic}",
+			"\t\t${4:reset : in std_logic;}",
 			"\t\t$0",
 			"\t);",
-		    "end entity;"
+			"end entity;"
 		],
-		"description": "instantiation: entity"
+		"description": "entity declaration"
 	},
 	"Architecture": {
 		"prefix": "architecture",
 		"body": [
 			"architecture ${1:behav} of ${2:$TM_FILENAME_BASE} is",
+			"\t$0",
 			"begin",
 			"end architecture;"
 		],
-		"description": "instantiation: architecture"
+		"description": "architecture declaration"
 	},
+	// TODO: test fix to allow no guard expression
 	"Block": {
 		"prefix": "block",
 		"body": [
-			"blk_${1:blockName} : block ${2|,optional_guard_expression|}",
+			"blk_${1:blockName} : block ${2| ,optional_guard_expression|}",
 			"begin",
 			"\t$0",
 			"end block;"
 		],
-		"description": "block: block"
+		"description": "block instantiation"
 	},
 
 
-	// TODO: package generic vhdl 2008
 	"If": {
 		"prefix": "if",
 		"body": [
@@ -208,18 +266,7 @@
 			"\t$0",
 			"end if;"
 		],
-		"description": "block: if"
-	},
-	"If/Else": {
-		"prefix": "if/else",
-		"body": [
-			"if ${1:expression} then",
-			"\t${2}",
-			"else",
-			"\t$0",
-			"end if;"
-		],
-		"description": "block: if/else"
+		"description": "if block"
 	},
 	"Elsif": {
 		"prefix": "elsif",
@@ -227,53 +274,61 @@
 			"elsif ${1:expression} then",
 			"\t$0"
 		],
-		"description": "keyword: elsif"
+		"description": "elsif block"
 	},
-	"If Generate": {
-		"prefix": "if_generate",
+	"Else": {
+		"prefix": "else",
 		"body": [
-			"gen_${1:generateName} : if ${2:expression} generate",
-			"\t$0",
-			"end generate;"
+			"else",
+			"\t$0"
 		],
-		"description": "block: if generate"
+		"description": "if/else block"
 	},
-	"If/Else Generate 2008": {
-		"prefix": "if/else_generate_2008",
+	// ? should these be changed instead to generate_if, generate_for, etc so the snippet
+	// suggestions aren't overwhelming when typing if
+	"If Generate": {
+		"prefix": "generate_if",
 		"body": [
 			"gen_${1:generateName} : if ${2:expression} generate",
-			"\t\t${3}",
-			"\telse generate",
-			"\t\t$0",
+			"\t$0",
 			"end generate;"
 		],
-		"description": "block: if/else generate (vhdl 2008)"
+		"description": "if generate instantiation"
 	},
 	"Elsif Generate 2008": {
-		"prefix": "elsif_generate_2008",
+		"prefix": "generate_elsif_2008",
 		"body": [
 			"elsif ${1:expression} generate",
-			"\t${2}"
+			"\t$0"
+		],
+		"description": "elsif generate instantiation (vhdl 2008)"
+	},
+	"Else Generate 2008": {
+		"prefix": "generate_else_2008",
+		"body": [
+			"\telse generate",
+			"\t\t$0"
 		],
-		"description": "keyword: elsif generate (vhdl 2008)"
+		"description": "else generate instantiation (vhdl 2008)"
 	},
+	// TODO: open VSC enhancement to allow for user selections ($x) within or (${1||}) selection
 	"For": {
 		"prefix": "for",
 		"body": [
-			"${1|,${2:optional_label}|}for ${3:i} in ${4|${5:user_range},$5 to $6, $5 downto $6|} loop",
+			"for ${1:i} in ${2:range} loop",
 			"\t$0",
 			"end loop;"
 		],
-		"description": "block: for generate"
+		"description": "for loop block"
 	},
 	"For Generate": {
-		"prefix": "for_generate",
+		"prefix": "generate_for",
 		"body": [
-			"gen_loop_${1:generateName} : for ${2:i} in ${3|${4:user_range},$4 to $5,$4 downto $5|} generate",
+			"gen_loop_${1:generateName} : for ${2:i} in ${3:range} generate",
 			"\t$0",
 			"end generate;"
 		],
-		"description": "block: for generate loop (vhdl 2008)"
+		"description": "for generate loop instantiation (vhdl 2008)"
 	},
 	"While": {
 		"prefix": "while",
@@ -282,41 +337,39 @@
 			"\t$0",
 			"end loop;"
 		],
-		"description": "block: while loop"
+		"description": "while loop block"
 	},
 	"Case": {
 		"prefix": "case",
 		"body": [
 			"case ${1:select} is",
-			"\twhen ${2:value} =>",
-			"\t\t${3}",
-			"\twhen others =>",
-			"\t\t${4:null}",
+			"\twhen ${2:others} =>",
+			"\t\t${3:null;}",
+			"\t$0",
 			"end case;"
 		],
-		"description": "block: case"
+		"description": "case block"
 	},
 	"Case Generate 2008": {
-		"prefix": "case_generate_2008",
+		"prefix": "generate_case_2008",
 		"body": [
 			"gen_${1:generateName} : case ${1:select} generate",
-			"\twhen ${2:value} =>",
-			"\t\t${3}",
-			"\twhen others =>",
-			"\t\t${4:null}",
+			"\twhen ${2:others} =>",
+			"\t\t${3:null;}",
+			"\t$0",
 			"end generate;"
 		],
-		"description": "block: case generate (vhdl 2008)"
+		"description": "case generate instantiation (vhdl 2008)"
 	},
 	"Process Combinatorial": {
 		"prefix": "process_combinatorial",
 		"body": [
-			"process ${1|,(${2:sensitvity_list})|}",
+			"process (${1:sensitivity_list})",
 			"begin",
 			"\t$0",
 			"end process;"
 		],
-		"description": "block: combinatorial process"
+		"description": "combinatorial process block"
 	},
 	"Process Combinatorial 2008": {
 		"prefix": "process_combinatorial_2008",
@@ -326,36 +379,37 @@
 			"\t$0",
 			"end process;"
 		],
-		"description": "block: combinatorial process (vhdl 2008)"
+		"description": "combinatorial process block (vhdl 2008)"
 	},
 	"Process Asynchronous": {
 		"prefix": "process_asynchronous",
 		"body": [
 			"process (${1:clk}, ${2:reset})",
 			"begin",
-			"\tif ${2} = ${3|'1','0'|} then",
-			"\telsif rising_edge(${1}) then",
+			"\tif $2 = ${3|'1','0'|} then",
+			"\t\t$4",
+			"\telsif rising_edge($1) then",
 			"\t\t$0",
 			"\tend if;",
 			"end process;"
 		],
-		"description": "block: asynchronous process"
+		"description": "asynchronous process block"
 	},
 	"Process Clocked": {
 		"prefix": ["process_clocked"],
 		"body": [
 			"process (${1:clk})",
 			"begin",
-			"\tif rising_edge(${1}) then",
+			"\tif rising_edge($1) then",
 			"\t\tif ${2:reset} = ${3|'1','0'|} then",
-			"\t\t\t$0",
+			"\t\t\t$4",
 			"\t\telse",
 			"\t\t\t$0",
 			"\t\tend if;",
 			"\tend if;",
 			"end process;"
 		],
-		"description": "block: clocked process"
+		"description": "clocked process block"
 	},
 	"Function": {
 		"prefix": "function",
@@ -365,7 +419,7 @@
 			"\t$0",
 			"end function;"
 		],
-		"description": "block: function body"
+		"description": "function body declaration"
 	},
 	"Procedure": {
 		"prefix": "procedure",
@@ -375,79 +429,88 @@
 			"\t$0",
 			"end procedure;"
 		],
-		"description": "block: procedure body"
+		"description": "procedure body declaration"
 	},
 	"Package": {
 		"prefix": "package",
 		"body": [
 			"package ${1:name} is",
+			"\t$0",
 			"end package;"
 		],
-		"description": "block: package declaration"
+		"description": "package declaration"
 	},
 	"Package Body": {
 		"prefix": "package_body",
 		"body": [
 			"package body ${1:name} is",
+			"\t$0",
 			"end package;"
 		],
-		"description": "block: package body"
+		"description": "package body declaration"
 	},
 	"Natural Range": {
 		"prefix": "natural_range",
 		"body": [ "natural range<>" ],
-		"description": "block: natural range"
+		"description": "natural range statement"
 	},
 
 
-	"Real": {
-		"prefix": "real",
-		"body": [ "real${1|, := ,;|}" ],
-		"description": "type: real"
-	},
-	"Integer": {
-		"prefix": "integer",
-		"body": [ "integer${1|, := ,;|}" ],
-		"description": "type: integer"
-	},
-	"Natural": {
-		"prefix": "natural",
-		"body": [ "natural${1|, := ,;|}" ],
-		"description": "type: natural"
-	},
-	"Positive": {
-		"prefix": "positive",
-		"body": [ "positive${1|, := ,;|}" ],
-		"description": "type: positive"
-	},
+	// TODO: bring these back once we can have or selection without a space
+	// TODO: open VSC bug about or selection for doing nothing still requires the editor insert a space or character
+	//"Real": {
+	//	"prefix": "real",
+	//	"body": [ "real${1|, := ,;|}" ],
+	//	"description": "type: real"
+	//},
+	//"Integer": {
+	//	"prefix": "integer",
+	//	"body": [ "integer${1|, := ,;|}" ],
+	//	"description": "type: integer"
+	//},
+	//"Natural": {
+	//	"prefix": "natural",
+	//	"body": [ "natural${1|, := ,;|}" ],
+	//	"description": "type: natural"
+	//},
+	//"Positive": {
+	//	"prefix": "positive",
+	//	"body": [ "positive${1|, := ,;|}" ],
+	//	"description": "type: positive"
+	//},
 	"Standard Logic": {
 		"prefix": ["std_logic", "sl"],
-		"body": [ "std_logic${1|, := ,;|}" ],
+		"body": [ "std_logic${1| := ,;|}$0" ],
+		"description": "type: std_logic"
+	},
+	"Standard Logic Type": {
+		"prefix": ["std_logic", "sl"],
+		"body": [ "std_logic${1| := ,;|}$0" ],
 		"description": "type: std_logic"
 	},
 	"Standard ULogic": {
 		"prefix": ["std_ulogic", "sul"],
-		"body": [ "std_ulogic${1|, := ,;|}" ],
+		"body": [ "std_ulogic${1| := ,;|}$0" ],
 		"description": "type: std_ulogic"
 	},
 	"Standard Logic Vector": {
 		"prefix": ["std_logic_vector", "slv"],
-		"body": [ "std_logic_vector(${1} ${2|downto,to|} ${3})${4|, := ,;|}" ],
+		"body": [ "std_logic_vector($1 ${2|downto,to|} $3)${4| := ,;|}$0" ],
 		"description": "type: std_logic_vector"
 	},
 	"Standard ULogic Vector": {
 		"prefix": ["std_ulogic_vector", "sulv"],
-		"body": [ "std_ulogic_vector(${1} ${2|downto,to|} ${3})${4|, := ,;|}" ],
+		"body": [ "std_ulogic_vector($1 ${2|downto,to|} $3)${4| := ,;|}$0" ],
 		"description": "type: std_ulogic_vector"
 	},
 	"Signed": {
 		"prefix": "signed",
-		"body": [ "signed(${1} ${2|downto,to|} ${3})${4|, := ,;|}" ],
+		"body": [ "signed($1 ${2|downto,to|} $3)${4| := ,;|}$0" ],
 		"description": "type: signed"
 	},
 	"Unsigned": {
 		"prefix": "unsigned",
-		"body": [ "unsigned(${1} ${2|downto,to|} ${3})${4|,;|}" ],
+		"body": [ "unsigned(${1} ${2|downto,to|} ${3})${4| := ,;|}$0" ],
 		"description": "type: unsigned"
 	}
 }

From fd7fdc540e6e9fc8823f64fe926524a4dcc31469 Mon Sep 17 00:00:00 2001
From: Glen Nicholls <Glen.Nicholls@kratosdefense.com>
Date: Wed, 13 Nov 2019 22:27:07 -0700
Subject: [PATCH 4/8] moved todos for #32 and removed attributes since typing
 that word takes longer than just writing it manually

---
 vscode-client/snippets.vhdl.json | 55 ++++++--------------------------
 1 file changed, 9 insertions(+), 46 deletions(-)

diff --git a/vscode-client/snippets.vhdl.json b/vscode-client/snippets.vhdl.json
index 567c4ba..d9fcd18 100644
--- a/vscode-client/snippets.vhdl.json
+++ b/vscode-client/snippets.vhdl.json
@@ -3,6 +3,11 @@
 	// TODO: configuration (might be too annoying)
 	// ? alphabetize
 	// TODO: package generic vhdl 2008
+	// TODO: open VSC enhancement to allow for user selections ($x) within or (${1||}) selection
+	// TODO: open VSC bug about or selection for doing nothing still requires the editor insert a space or character
+	// TODO: add notes/examples to descriptions
+	// TODO: figure out how to column align with snippets such that when new lines are made for things like when/else
+	//       or with select, cursor for next line is aligned with <=
 
 	"Library": {
 		"prefix": "library",
@@ -78,10 +83,7 @@
 	// FIXME: this needs to allow second option with space/;
 	"Others": {
 		"prefix": ["others"],
-		"body": [
-			"(others => ${1:<value>})${2| ,;|}",
-			"$0"
-		],
+		"body": [ "(others => ${1:<value>})${2| ,;|}$0" ],
 		"description": "others keyword"
 	},
 	"When": {
@@ -92,7 +94,6 @@
 		],
 		"description": "when statement"
 	},
-	// TODO: figure out how to column align when else after <= column
 	"When Else": {
 		"prefix": "when_else",
 		"body": [
@@ -102,7 +103,6 @@
 		],
 		"description": "concurrent when else statement"
 	},
-	// TODO: figure out how to column align with select after <= column
 	"With Select": {
 		"prefix": ["select", "with_select"],
 		"body": [
@@ -113,7 +113,6 @@
 		],
 		"description": "concurrent with select statement"
 	},
-	// TODO: add example
 	"Alias": {
 		"prefix": "alias",
 		"body": [
@@ -122,7 +121,6 @@
 		],
 		"description": "alias declaration"
 	},
-	// TODO: add example
 	// ? are signal/variable/constant all valid for external names
 	"Alias External Name 2008": {
 		"prefix": "alias_external_name_2008",
@@ -133,12 +131,6 @@
 		],
 		"description": "hierarchical signal declaration (vhdl 2008). NOTE: for standard types (SLV, unsighed, signed, etc.), no range needs to be specified"
 	},
-	// ! cannot use ' since it auto-closes
-	"Attribute": {
-		"prefix": ["attribute", "'"],
-		"body": [ "'${1|high,low,left,right,range,reverse_range,length,event|}$0" ],
-		"description": "synthesizable attributes (high,low,left,right,range,reverse_range,length,event)"
-	},
 	"Array Type": {
 		"prefix": "array",
 		"body": [
@@ -173,7 +165,6 @@
 		],
 		"description": "constant declaration"
 	},
-	// TODO: report VSC bug that snippets are unavailable to select while filling out a snippet
 	"Signal": {
 		"prefix": "signal",
 		"body": [
@@ -190,7 +181,6 @@
 		],
 		"description": "variable declaration"
 	},
-	// TODO: should record just insert cursor instead of aiding user in filling in signals
 	"Record Type": {
 		"prefix": "record",
 		"body": [
@@ -219,7 +209,6 @@
 		],
 		"description": "component declaration"
 	},
-	// TODO: fill in notes
 	"Entity": {
 	"prefix": "entity",
 		"body": [
@@ -246,7 +235,6 @@
 		],
 		"description": "architecture declaration"
 	},
-	// TODO: test fix to allow no guard expression
 	"Block": {
 		"prefix": "block",
 		"body": [
@@ -282,10 +270,8 @@
 			"else",
 			"\t$0"
 		],
-		"description": "if/else block"
+		"description": "else block"
 	},
-	// ? should these be changed instead to generate_if, generate_for, etc so the snippet
-	// suggestions aren't overwhelming when typing if
 	"If Generate": {
 		"prefix": "generate_if",
 		"body": [
@@ -311,7 +297,6 @@
 		],
 		"description": "else generate instantiation (vhdl 2008)"
 	},
-	// TODO: open VSC enhancement to allow for user selections ($x) within or (${1||}) selection
 	"For": {
 		"prefix": "for",
 		"body": [
@@ -434,7 +419,7 @@
 	"Package": {
 		"prefix": "package",
 		"body": [
-			"package ${1:name} is",
+			"package ${1:$TM_FILENAME_BASE} is",
 			"\t$0",
 			"end package;"
 		],
@@ -443,7 +428,7 @@
 	"Package Body": {
 		"prefix": "package_body",
 		"body": [
-			"package body ${1:name} is",
+			"package body ${1:$TM_FILENAME_BASE} is",
 			"\t$0",
 			"end package;"
 		],
@@ -456,28 +441,6 @@
 	},
 
 
-	// TODO: bring these back once we can have or selection without a space
-	// TODO: open VSC bug about or selection for doing nothing still requires the editor insert a space or character
-	//"Real": {
-	//	"prefix": "real",
-	//	"body": [ "real${1|, := ,;|}" ],
-	//	"description": "type: real"
-	//},
-	//"Integer": {
-	//	"prefix": "integer",
-	//	"body": [ "integer${1|, := ,;|}" ],
-	//	"description": "type: integer"
-	//},
-	//"Natural": {
-	//	"prefix": "natural",
-	//	"body": [ "natural${1|, := ,;|}" ],
-	//	"description": "type: natural"
-	//},
-	//"Positive": {
-	//	"prefix": "positive",
-	//	"body": [ "positive${1|, := ,;|}" ],
-	//	"description": "type: positive"
-	//},
 	"Standard Logic": {
 		"prefix": ["std_logic", "sl"],
 		"body": [ "std_logic${1| := ,;|}$0" ],

From 9b5adc93dfb6f5a13784ef0182562ed20eea3d84 Mon Sep 17 00:00:00 2001
From: Glen Nicholls <Glen.Nicholls@kratosdefense.com>
Date: Thu, 14 Nov 2019 18:53:03 -0700
Subject: [PATCH 5/8] organizing a bit and moving snippets to multiple files

---
 vscode-client/package.json                    |  12 +-
 .../{ => snippets}/snippets.vhdl.json         | 108 ------------------
 .../snippets/snippets.vhdl.libraries.json     |  72 ++++++++++++
 .../snippets/snippets.vhdl.types.json         |  37 ++++++
 .../syntaxes.vhdl.tmLanguage.json             |   0
 5 files changed, 119 insertions(+), 110 deletions(-)
 rename vscode-client/{ => snippets}/snippets.vhdl.json (74%)
 create mode 100644 vscode-client/snippets/snippets.vhdl.libraries.json
 create mode 100644 vscode-client/snippets/snippets.vhdl.types.json
 rename vscode-client/{ => syntaxes}/syntaxes.vhdl.tmLanguage.json (100%)

diff --git a/vscode-client/package.json b/vscode-client/package.json
index b8a277d..38ffab4 100644
--- a/vscode-client/package.json
+++ b/vscode-client/package.json
@@ -39,13 +39,21 @@
 			{
 				"language": "vhdl",
 				"scopeName": "source.vhdl",
-				"path": "./syntaxes.vhdl.tmLanguage.json"
+				"path": "./syntaxes/syntaxes.vhdl.tmLanguage.json"
 			}
 		],
 		"snippets": [
 			{
 				"language": "vhdl",
-				"path": "./snippets.vhdl.json"
+				"path": "./snippets/snippets.vhdl.json"
+			},
+			{
+				"language": "vhdl",
+				"path": "./snippets/snippets.vhdl.libraries.json"
+			},
+			{
+				"language": "vhdl",
+				"path": "./snippets/snippets.vhdl.types.json"
 			}
 		],
 		"commands": [
diff --git a/vscode-client/snippets.vhdl.json b/vscode-client/snippets/snippets.vhdl.json
similarity index 74%
rename from vscode-client/snippets.vhdl.json
rename to vscode-client/snippets/snippets.vhdl.json
index d9fcd18..abe341d 100644
--- a/vscode-client/snippets.vhdl.json
+++ b/vscode-client/snippets/snippets.vhdl.json
@@ -9,77 +9,6 @@
 	// TODO: figure out how to column align with snippets such that when new lines are made for things like when/else
 	//       or with select, cursor for next line is aligned with <=
 
-	"Library": {
-		"prefix": "library",
-		"body": [
-			"library ${1:ieee};",
-			"$0"
-		],
-		"description": "library declaration"
-	},
-	"Library TextIO": {
-		"prefix": "library_textio",
-		"body": [
-			"library std;",
-			"use std.textio.all;",
-			"$0"
-		],
-		"description": "TextIO library declaration"
-	},
-	"IEEE Libraries": {
-		"prefix": "library_ieee",
-		"body": [
-			"library ieee;",
-			"use ieee.std_logic_1164.all;",
-			"use ieee.numeric_std.all;",
-			"use ieee.math_real.all;",
-			"$0"
-		],
-		"description": "common IEEE libraries declaration"
-	},
-	"IEEE Libraries 2008": {
-		"prefix": "library_ieee_2008",
-		"body": [
-			"library ieee;",
-			"context ieee.ieee_std_context;",
-			"use ieee.math_real.all;",
-			"$0"
-		],
-		"description": "common IEEE libraries declaration with 2008 standard context (vhdl 2008)"
-	},
-	"Use": {
-		"prefix": "use",
-		"body": [
-			"use ${1:lib.pkg}.all;",
-			"$0"
-		],
-		"description": "use clause"
-	},
-	// TODO: move this up into library_ieee inst and give user option to include any of these
-	"Use IEEE Package": {
-		"prefix": "use_ieee",
-		"body": [
-			"use ieee.${1|std_logic_1164,std_logic_textio,numeric_std,math_real,math_complex|}.all;",
-			"$0"
-		],
-		"description": "use clause IEEE standard package (std_logic_1164,std_logic_textio,numeric_std,math_real,math_complex)"
-	},
-	"Context 2008": {
-		"prefix": "context_2008",
-		"body": [
-			"context ${1:lib.context_name};",
-			"$0"
-		],
-		"description": "context clause (vhdl 2008)"
-	},
-	"Context IEEE 2008": {
-		"prefix": "context_ieee_2008",
-		"body": [
-			"context ieee.${1|ieee_bit_context,ieee_std_context|};",
-			"$0"
-		],
-		"description": "context clause for IEEE standard contexts (ieee_bit_context,ieee_std_context) (vhdl 2008)"
-	},
 	// FIXME: this needs to allow second option with space/;
 	"Others": {
 		"prefix": ["others"],
@@ -438,42 +367,5 @@
 		"prefix": "natural_range",
 		"body": [ "natural range<>" ],
 		"description": "natural range statement"
-	},
-
-
-	"Standard Logic": {
-		"prefix": ["std_logic", "sl"],
-		"body": [ "std_logic${1| := ,;|}$0" ],
-		"description": "type: std_logic"
-	},
-	"Standard Logic Type": {
-		"prefix": ["std_logic", "sl"],
-		"body": [ "std_logic${1| := ,;|}$0" ],
-		"description": "type: std_logic"
-	},
-	"Standard ULogic": {
-		"prefix": ["std_ulogic", "sul"],
-		"body": [ "std_ulogic${1| := ,;|}$0" ],
-		"description": "type: std_ulogic"
-	},
-	"Standard Logic Vector": {
-		"prefix": ["std_logic_vector", "slv"],
-		"body": [ "std_logic_vector($1 ${2|downto,to|} $3)${4| := ,;|}$0" ],
-		"description": "type: std_logic_vector"
-	},
-	"Standard ULogic Vector": {
-		"prefix": ["std_ulogic_vector", "sulv"],
-		"body": [ "std_ulogic_vector($1 ${2|downto,to|} $3)${4| := ,;|}$0" ],
-		"description": "type: std_ulogic_vector"
-	},
-	"Signed": {
-		"prefix": "signed",
-		"body": [ "signed($1 ${2|downto,to|} $3)${4| := ,;|}$0" ],
-		"description": "type: signed"
-	},
-	"Unsigned": {
-		"prefix": "unsigned",
-		"body": [ "unsigned(${1} ${2|downto,to|} ${3})${4| := ,;|}$0" ],
-		"description": "type: unsigned"
 	}
 }
diff --git a/vscode-client/snippets/snippets.vhdl.libraries.json b/vscode-client/snippets/snippets.vhdl.libraries.json
new file mode 100644
index 0000000..880560c
--- /dev/null
+++ b/vscode-client/snippets/snippets.vhdl.libraries.json
@@ -0,0 +1,72 @@
+{
+	"Library": {
+		"prefix": "library",
+		"body": [
+			"library ${1:ieee};",
+			"$0"
+		],
+		"description": "library declaration"
+	},
+	"Library IEEE": {
+		"prefix": "library_ieee",
+		"body": [
+			"library ieee;",
+			"use ieee.std_logic_1164.all;",
+			"use ieee.numeric_std.all;",
+			"use ieee.math_real.all;",
+			"$0"
+		],
+		"description": "common IEEE libraries declaration"
+	},
+	"Library IEEE 2008": {
+		"prefix": "library_ieee_2008",
+		"body": [
+			"library ieee;",
+			"context ieee.ieee_std_context;",
+			"use ieee.math_real.all;",
+			"$0"
+		],
+		"description": "common IEEE libraries declaration with 2008 standard context (vhdl 2008)"
+	},
+	"Library TextIO": {
+		"prefix": "library_textio",
+		"body": [
+			"library std;",
+			"use std.textio.all;",
+			"$0"
+		],
+		"description": "TextIO library declaration"
+	},
+	"Use": {
+		"prefix": "use",
+		"body": [
+			"use ${1:lib.pkg}.all;",
+			"$0"
+		],
+		"description": "use clause"
+	},
+	"Use IEEE Package": {
+		"prefix": "use_ieee",
+		"body": [
+			"use ieee.${1|std_logic_1164,std_logic_textio,numeric_std,math_real,math_complex|}.all;",
+			"$0"
+		],
+		"description": "use clause IEEE standard package (std_logic_1164,std_logic_textio,numeric_std,math_real,math_complex)"
+	},
+	"Context 2008": {
+		"prefix": "context_2008",
+		"body": [
+			"context ${1:lib.context_name};",
+			"$0"
+		],
+		"description": "context clause (vhdl 2008)"
+	},
+	"Context IEEE 2008": {
+		"prefix": "context_ieee_2008",
+		"body": [
+			"context ieee.${1|ieee_bit_context,ieee_std_context|};",
+			"$0"
+		],
+		"description": "context clause for IEEE standard contexts (ieee_bit_context,ieee_std_context) (vhdl 2008)"
+	},
+}
diff --git a/vscode-client/snippets/snippets.vhdl.types.json b/vscode-client/snippets/snippets.vhdl.types.json
new file mode 100644
index 0000000..fc9fe75
--- /dev/null
+++ b/vscode-client/snippets/snippets.vhdl.types.json
@@ -0,0 +1,37 @@
+{
+	"Standard Logic": {
+		"prefix": ["std_logic", "sl"],
+		"body": [ "std_logic${1| := ,;|}$0" ],
+		"description": "std_logic type"
+	},
+	"Standard Logic Type": {
+		"prefix": ["std_logic", "sl"],
+		"body": [ "std_logic${1| := ,;|}$0" ],
+		"description": "std_logic type"
+	},
+	"Standard ULogic": {
+		"prefix": ["std_ulogic", "sul"],
+		"body": [ "std_ulogic${1| := ,;|}$0" ],
+		"description": "std_ulogic type"
+	},
+	"Standard Logic Vector": {
+		"prefix": ["std_logic_vector", "slv"],
+		"body": [ "std_logic_vector($1 ${2|downto,to|} $3)${4| := ,;|}$0" ],
+		"description": "std_logic_vector type"
+	},
+	"Standard ULogic Vector": {
+		"prefix": ["std_ulogic_vector", "sulv"],
+		"body": [ "std_ulogic_vector($1 ${2|downto,to|} $3)${4| := ,;|}$0" ],
+		"description": "std_ulogic_vector type"
+	},
+	"Signed": {
+		"prefix": "signed",
+		"body": [ "signed($1 ${2|downto,to|} $3)${4| := ,;|}$0" ],
+		"description": "signed type"
+	},
+	"Unsigned": {
+		"prefix": "unsigned",
+		"body": [ "unsigned(${1} ${2|downto,to|} ${3})${4| := ,;|}$0" ],
+		"description": "unsigned type"
+	}
+}
diff --git a/vscode-client/syntaxes.vhdl.tmLanguage.json b/vscode-client/syntaxes/syntaxes.vhdl.tmLanguage.json
similarity index 100%
rename from vscode-client/syntaxes.vhdl.tmLanguage.json
rename to vscode-client/syntaxes/syntaxes.vhdl.tmLanguage.json

From 8ae5ce5d99752f92a86337f9b11e987d6d479906 Mon Sep 17 00:00:00 2001
From: Glen Nicholls <Glen.Nicholls@kratosdefense.com>
Date: Thu, 14 Nov 2019 19:49:54 -0700
Subject: [PATCH 6/8] moved snippets to seperate files based on logical
 ordering and updated package.json

---
 vscode-client/package.json                    |  14 +-
 vscode-client/snippets/snippets.generate.json |  47 +++
 .../snippets/snippets.vhdl.declaration.json   | 164 ++++++++
 .../snippets/snippets.vhdl.interface.json     |  74 ++++
 vscode-client/snippets/snippets.vhdl.json     | 371 ------------------
 ...raries.json => snippets.vhdl.library.json} |   2 +-
 .../snippets/snippets.vhdl.logic.json         | 118 ++++++
 .../snippets/snippets.vhdl.types.json         |  37 --
 8 files changed, 415 insertions(+), 412 deletions(-)
 create mode 100644 vscode-client/snippets/snippets.generate.json
 create mode 100644 vscode-client/snippets/snippets.vhdl.declaration.json
 create mode 100644 vscode-client/snippets/snippets.vhdl.interface.json
 delete mode 100644 vscode-client/snippets/snippets.vhdl.json
 rename vscode-client/snippets/{snippets.vhdl.libraries.json => snippets.vhdl.library.json} (93%)
 create mode 100644 vscode-client/snippets/snippets.vhdl.logic.json
 delete mode 100644 vscode-client/snippets/snippets.vhdl.types.json

diff --git a/vscode-client/package.json b/vscode-client/package.json
index 38ffab4..6a03749 100644
--- a/vscode-client/package.json
+++ b/vscode-client/package.json
@@ -45,15 +45,23 @@
 		"snippets": [
 			{
 				"language": "vhdl",
-				"path": "./snippets/snippets.vhdl.json"
+				"path": "./snippets/snippets.vhdl.generate.json"
 			},
 			{
 				"language": "vhdl",
-				"path": "./snippets/snippets.vhdl.libraries.json"
+				"path": "./snippets/snippets.vhdl.declaration.json"
 			},
 			{
 				"language": "vhdl",
-				"path": "./snippets/snippets.vhdl.types.json"
+				"path": "./snippets/snippets.vhdl.interface.json"
+			},
+			{
+				"language": "vhdl",
+				"path": "./snippets/snippets.vhdl.library.json"
+			},
+			{
+				"language": "vhdl",
+				"path": "./snippets/snippets.vhdl.locic.json"
 			}
 		],
 		"commands": [
diff --git a/vscode-client/snippets/snippets.generate.json b/vscode-client/snippets/snippets.generate.json
new file mode 100644
index 0000000..aeab149
--- /dev/null
+++ b/vscode-client/snippets/snippets.generate.json
@@ -0,0 +1,47 @@
+{
+	"Generate Case 2008": {
+		"prefix": "generate_case_2008",
+		"body": [
+			"gen_${1:generateName} : case ${1:select} generate",
+			"\twhen ${2:others} =>",
+			"\t\t${3:null;}",
+			"\t$0",
+			"end generate;"
+		],
+		"description": "case generate instantiation (vhdl 2008)"
+	},
+	"Generate If": {
+		"prefix": "generate_if",
+		"body": [
+			"gen_${1:generateName} : if ${2:expression} generate",
+			"\t$0",
+			"end generate;"
+		],
+		"description": "if generate instantiation"
+	},
+	"Generate Elsif 2008": {
+		"prefix": "generate_elsif_2008",
+		"body": [
+			"elsif ${1:expression} generate",
+			"\t$0"
+		],
+		"description": "elsif generate instantiation (vhdl 2008)"
+	},
+	"Generate Else 2008": {
+		"prefix": "generate_else_2008",
+		"body": [
+			"\telse generate",
+			"\t\t$0"
+		],
+		"description": "else generate instantiation (vhdl 2008)"
+	},
+	"Generate For": {
+		"prefix": "generate_for",
+		"body": [
+			"gen_loop_${1:generateName} : for ${2:i} in ${3:range} generate",
+			"\t$0",
+			"end generate;"
+		],
+		"description": "for generate loop instantiation (vhdl 2008)"
+	}
+}
diff --git a/vscode-client/snippets/snippets.vhdl.declaration.json b/vscode-client/snippets/snippets.vhdl.declaration.json
new file mode 100644
index 0000000..6a10beb
--- /dev/null
+++ b/vscode-client/snippets/snippets.vhdl.declaration.json
@@ -0,0 +1,164 @@
+{
+	// TODO: open VSC enhancement to allow for user selections ($x) within or (${1||}) selection
+	// TODO: open VSC bug about or selection for doing nothing still requires the editor insert a space or character
+	// TODO: figure out how to column align with snippets such that when new lines are made for things like when/else
+	//       or with select, cursor for next line is aligned with <=
+	// TODO: all types from ieee fixed/floating point packages
+	"Alias": {
+		"prefix": "alias",
+		"body": [
+			"alias ${1:alias_name} : ${2:alias_type} is ${3:object_name};",
+			"$0"
+		],
+		"description": "alias declaration"
+	},
+	// ? are signal/variable/constant all valid for external names
+	"Alias External Name 2008": {
+		"prefix": "alias_external_name_2008",
+		"body": [
+			"alias ${1:name} is",
+			"\t<< ${2|signal,variable,constant|} ${3:path.to.signal.name} : ${4:type} >>;",
+			"$0"
+		],
+		"description": "hierarchical signal declaration (vhdl 2008). NOTE: for standard types (SLV, unsighed, signed, etc.), no range needs to be specified"
+	},
+	"Array": {
+		"prefix": "array",
+		"body": [
+			"type ${1:type_name} is array (${2:natural range<>}) of ${3:element_type};",
+			"$0"
+		],
+		"description": "synthesizable attributes (high,low,left,right,range,reverse_range,length,event)"
+	},
+	"Assert": {
+		"prefix": "assert",
+		"body": [
+			"assert ${1:expression}",
+			"\treport \"${2:string}\"",
+			"\tseverity ${3|note,warning,error,failure|};",
+			"$0"
+		 ],
+		"description": "assert declaration"
+	},
+	"Constant": {
+		"prefix": "constant",
+		"body": [
+			"constant ${1:name} : ${2:type} := ${3:default_value};",
+			"$0"
+		],
+		"description": "constant declaration"
+	},
+	"Function": {
+		"prefix": "function",
+		"body": [
+			"function ${1:name} (${2:params}) return ${3:type} is",
+			"begin",
+			"\t$0",
+			"end function;"
+		],
+		"description": "function body declaration"
+	},
+	"Natural Range": {
+		"prefix": "natural_range",
+		"body": [ "natural range<>" ],
+		"description": "natural range declaration"
+	},
+	"Others": {
+		"prefix": ["others"],
+		"body": [ "(others => ${1:<value>})${2| ,;|}$0" ],
+		"description": "others declaration"
+	},
+	"Procedure": {
+		"prefix": "procedure",
+		"body": [
+			"procedure ${1:name} (${2:params}) is",
+			"begin",
+			"\t$0",
+			"end procedure;"
+		],
+		"description": "procedure body declaration"
+	},
+	"Record Type": {
+		"prefix": "record",
+		"body": [
+			"type ${1:name} is record",
+			"\t${2:signal_name} : ${3:type};",
+			"\t$0",
+			"end record;"
+		],
+		"description": "record declaration"
+	},
+	"Signal": {
+		"prefix": "signal",
+		"body": [
+			"signal ${1:name} : ${2:type} := ${3:default_value};",
+			"$0"
+		],
+		"description": "signal declaration"
+	},
+	"Signed": {
+		"prefix": "signed",
+		"body": [ "signed($1 ${2|downto,to|} $3)${4| := ,;|}$0" ],
+		"description": "signed declaration"
+	},
+	"Standard Logic": {
+		"prefix": ["std_logic", "sl"],
+		"body": [ "std_logic${1| := ,;|}$0" ],
+		"description": "std_logic declaration"
+	},
+	"Standard ULogic": {
+		"prefix": ["std_ulogic", "sul"],
+		"body": [ "std_ulogic${1| := ,;|}$0" ],
+		"description": "std_ulogic declaration"
+	},
+	"Standard Logic Vector": {
+		"prefix": ["std_logic_vector", "slv"],
+		"body": [ "std_logic_vector($1 ${2|downto,to|} $3)${4| := ,;|}$0" ],
+		"description": "std_logic_vector declaration"
+	},
+	"Standard ULogic Vector": {
+		"prefix": ["std_ulogic_vector", "sulv"],
+		"body": [ "std_ulogic_vector($1 ${2|downto,to|} $3)${4| := ,;|}$0" ],
+		"description": "std_ulogic_vector declaration"
+	},
+	"Unsigned": {
+		"prefix": "unsigned",
+		"body": [ "unsigned(${1} ${2|downto,to|} ${3})${4| := ,;|}$0" ],
+		"description": "unsigned declaration"
+	},
+	"When": {
+		"prefix": "when",
+		"body": [
+			"when ${1:others} =>",
+			"\t$0"
+		],
+		"description": "when declaration"
+	},
+	"When Else": {
+		"prefix": "when_else",
+		"body": [
+			"${1:signal} <= ${2:first_value} when ${3:expression}",
+			"\telse ${4:final_value};",
+			"$0"
+		],
+		"description": "concurrent when else declaration"
+	},
+	"With Select": {
+		"prefix": ["select", "with_select"],
+		"body": [
+			"with ${1:select} select",
+			"\t${2:signal} <= ${3:first_value} when ${4:select_value},",
+			"\t\t${5:last_value} when others;",
+			"$0"
+		],
+		"description": "concurrent with select declaration"
+	},
+	"Variable": {
+		"prefix": "variable",
+		"body": [
+			"variable ${1:name} : ${2:type} := ${3:default_value};",
+			"$0"
+		],
+		"description": "variable declaration"
+	}
+}
diff --git a/vscode-client/snippets/snippets.vhdl.interface.json b/vscode-client/snippets/snippets.vhdl.interface.json
new file mode 100644
index 0000000..3d993d1
--- /dev/null
+++ b/vscode-client/snippets/snippets.vhdl.interface.json
@@ -0,0 +1,74 @@
+{
+	// TODO: package generics
+	// TODO: configuration
+	"Architecture Interface": {
+		"prefix": "architecture",
+		"body": [
+			"architecture ${1:behav} of ${2:$TM_FILENAME_BASE} is",
+			"\t$0",
+			"begin",
+			"end architecture;"
+		],
+		"description": "architecture interface"
+	},
+	"Block Interface": {
+		"prefix": "block",
+		"body": [
+			"blk_${1:blockName} : block ${2| ,optional_guard_expression|}",
+			"begin",
+			"\t$0",
+			"end block;"
+		],
+		"description": "block interface"
+	},
+	"Component Interface": {
+		"prefix":"component",
+		"body": [
+			"component ${1:comp_name} is",
+			"\tgeneric (",
+			"\t\t${2:generics}",
+			"\t);",
+			"\tport (",
+			"\t\t${3:clk   : in std_logic;}",
+			"\t\t${4:reset : in std_logic;}",
+			"\t\t$0",
+			"\t);",
+			"end component;"
+		],
+		"description": "component interface"
+	},
+	"Entity Interface": {
+	"prefix": "entity",
+		"body": [
+			"entity ${1:$TM_FILENAME_BASE} is",
+			"\tgeneric (",
+			"\t\t${2:generics}",
+			"\t);",
+			"\tport (",
+			"\t\t${3:clk   : in std_logic;}",
+			"\t\t${4:reset : in std_logic;}",
+			"\t\t$0",
+			"\t);",
+			"end entity;"
+		],
+		"description": "entity interface"
+	},
+	"Package Interface": {
+		"prefix": "package",
+		"body": [
+			"package ${1:$TM_FILENAME_BASE} is",
+			"\t$0",
+			"end package;"
+		],
+		"description": "package interface"
+	},
+	"Package Body Interface": {
+		"prefix": "package_body",
+		"body": [
+			"package body ${1:$TM_FILENAME_BASE} is",
+			"\t$0",
+			"end package;"
+		],
+		"description": "package body interface"
+	}
+}
diff --git a/vscode-client/snippets/snippets.vhdl.json b/vscode-client/snippets/snippets.vhdl.json
deleted file mode 100644
index abe341d..0000000
--- a/vscode-client/snippets/snippets.vhdl.json
+++ /dev/null
@@ -1,371 +0,0 @@
-{
-	// TODO: add examples to anything that isn't obvious
-	// TODO: configuration (might be too annoying)
-	// ? alphabetize
-	// TODO: package generic vhdl 2008
-	// TODO: open VSC enhancement to allow for user selections ($x) within or (${1||}) selection
-	// TODO: open VSC bug about or selection for doing nothing still requires the editor insert a space or character
-	// TODO: add notes/examples to descriptions
-	// TODO: figure out how to column align with snippets such that when new lines are made for things like when/else
-	//       or with select, cursor for next line is aligned with <=
-
-	// FIXME: this needs to allow second option with space/;
-	"Others": {
-		"prefix": ["others"],
-		"body": [ "(others => ${1:<value>})${2| ,;|}$0" ],
-		"description": "others keyword"
-	},
-	"When": {
-		"prefix": "when",
-		"body": [
-			"when ${1:others} =>",
-			"\t$0"
-		],
-		"description": "when statement"
-	},
-	"When Else": {
-		"prefix": "when_else",
-		"body": [
-			"${1:signal} <= ${2:first_value} when ${3:expression}",
-			"\telse ${4:final_value};",
-			"$0"
-		],
-		"description": "concurrent when else statement"
-	},
-	"With Select": {
-		"prefix": ["select", "with_select"],
-		"body": [
-			"with ${1:select} select",
-			"\t${2:signal} <= ${3:first_value} when ${4:select_value},",
-			"\t\t${5:last_value} when others;",
-			"$0"
-		],
-		"description": "concurrent with select statement"
-	},
-	"Alias": {
-		"prefix": "alias",
-		"body": [
-			"alias ${1:alias_name} : ${2:alias_type} is ${3:object_name};",
-			"$0"
-		],
-		"description": "alias declaration"
-	},
-	// ? are signal/variable/constant all valid for external names
-	"Alias External Name 2008": {
-		"prefix": "alias_external_name_2008",
-		"body": [
-			"alias ${1:name} is",
-			"\t<< ${2|signal,variable,constant|} ${3:path.to.signal.name} : ${4:type} >>;",
-			"$0"
-		],
-		"description": "hierarchical signal declaration (vhdl 2008). NOTE: for standard types (SLV, unsighed, signed, etc.), no range needs to be specified"
-	},
-	"Array Type": {
-		"prefix": "array",
-		"body": [
-			"type ${1:type_name} is array (${2:natural range<>}) of ${3:element_type};",
-			"$0"
-		],
-		"description": "synthesizable attributes (high,low,left,right,range,reverse_range,length,event)"
-	},
-	"Assert Statement": {
-		"prefix": "assert",
-		"body": [
-			"assert ${1:expression}",
-			"\treport \"${2:string}\"",
-			"\tseverity ${3|note,warning,error,failure|};",
-			"$0"
-		 ],
-		"description": "assert statement"
-	},
-	"Constant": {
-		"prefix": "constant",
-		"body": [
-			"constant ${1:name} : ${2:type} := ${3:default_value};",
-			"$0"
-		],
-		"description": "constant declaration"
-	},
-	"File": {
-		"prefix": "file",
-		"body": [
-			"file ${1:name} : text is ${2|in,out|} \"${3:file_name}\";",
-			"$0"
-		],
-		"description": "constant declaration"
-	},
-	"Signal": {
-		"prefix": "signal",
-		"body": [
-			"signal ${1:name} : ${2:type} := ${3:default_value};",
-			"$0"
-		],
-		"description": "signal declaration"
-	},
-	"Variable": {
-		"prefix": "variable",
-		"body": [
-			"variable ${1:name} : ${2:type} := ${3:default_value};",
-			"$0"
-		],
-		"description": "variable declaration"
-	},
-	"Record Type": {
-		"prefix": "record",
-		"body": [
-			"type ${1:name} is record",
-			"\t${2:signal_name} : ${3:type};",
-			"\t$0",
-			"end record;"
-		],
-		"description": "record declaration"
-	},
-
-
-	"Component": {
-		"prefix":"component",
-		"body": [
-			"component ${1:comp_name} is",
-			"\tgeneric (",
-			"\t\t${2:generics}",
-			"\t);",
-			"\tport (",
-			"\t\t${3:clk   : in std_logic;}",
-			"\t\t${4:reset : in std_logic;}",
-			"\t\t$0",
-			"\t);",
-			"end component;"
-		],
-		"description": "component declaration"
-	},
-	"Entity": {
-	"prefix": "entity",
-		"body": [
-			"entity ${1:$TM_FILENAME_BASE} is",
-			"\tgeneric (",
-			"\t\t${2:generics}",
-			"\t);",
-			"\tport (",
-			"\t\t${3:clk   : in std_logic;}",
-			"\t\t${4:reset : in std_logic;}",
-			"\t\t$0",
-			"\t);",
-			"end entity;"
-		],
-		"description": "entity declaration"
-	},
-	"Architecture": {
-		"prefix": "architecture",
-		"body": [
-			"architecture ${1:behav} of ${2:$TM_FILENAME_BASE} is",
-			"\t$0",
-			"begin",
-			"end architecture;"
-		],
-		"description": "architecture declaration"
-	},
-	"Block": {
-		"prefix": "block",
-		"body": [
-			"blk_${1:blockName} : block ${2| ,optional_guard_expression|}",
-			"begin",
-			"\t$0",
-			"end block;"
-		],
-		"description": "block instantiation"
-	},
-
-
-	"If": {
-		"prefix": "if",
-		"body": [
-			"if ${1:expression} then",
-			"\t$0",
-			"end if;"
-		],
-		"description": "if block"
-	},
-	"Elsif": {
-		"prefix": "elsif",
-		"body": [
-			"elsif ${1:expression} then",
-			"\t$0"
-		],
-		"description": "elsif block"
-	},
-	"Else": {
-		"prefix": "else",
-		"body": [
-			"else",
-			"\t$0"
-		],
-		"description": "else block"
-	},
-	"If Generate": {
-		"prefix": "generate_if",
-		"body": [
-			"gen_${1:generateName} : if ${2:expression} generate",
-			"\t$0",
-			"end generate;"
-		],
-		"description": "if generate instantiation"
-	},
-	"Elsif Generate 2008": {
-		"prefix": "generate_elsif_2008",
-		"body": [
-			"elsif ${1:expression} generate",
-			"\t$0"
-		],
-		"description": "elsif generate instantiation (vhdl 2008)"
-	},
-	"Else Generate 2008": {
-		"prefix": "generate_else_2008",
-		"body": [
-			"\telse generate",
-			"\t\t$0"
-		],
-		"description": "else generate instantiation (vhdl 2008)"
-	},
-	"For": {
-		"prefix": "for",
-		"body": [
-			"for ${1:i} in ${2:range} loop",
-			"\t$0",
-			"end loop;"
-		],
-		"description": "for loop block"
-	},
-	"For Generate": {
-		"prefix": "generate_for",
-		"body": [
-			"gen_loop_${1:generateName} : for ${2:i} in ${3:range} generate",
-			"\t$0",
-			"end generate;"
-		],
-		"description": "for generate loop instantiation (vhdl 2008)"
-	},
-	"While": {
-		"prefix": "while",
-		"body": [
-			"while ${1:expression} loop",
-			"\t$0",
-			"end loop;"
-		],
-		"description": "while loop block"
-	},
-	"Case": {
-		"prefix": "case",
-		"body": [
-			"case ${1:select} is",
-			"\twhen ${2:others} =>",
-			"\t\t${3:null;}",
-			"\t$0",
-			"end case;"
-		],
-		"description": "case block"
-	},
-	"Case Generate 2008": {
-		"prefix": "generate_case_2008",
-		"body": [
-			"gen_${1:generateName} : case ${1:select} generate",
-			"\twhen ${2:others} =>",
-			"\t\t${3:null;}",
-			"\t$0",
-			"end generate;"
-		],
-		"description": "case generate instantiation (vhdl 2008)"
-	},
-	"Process Combinatorial": {
-		"prefix": "process_combinatorial",
-		"body": [
-			"process (${1:sensitivity_list})",
-			"begin",
-			"\t$0",
-			"end process;"
-		],
-		"description": "combinatorial process block"
-	},
-	"Process Combinatorial 2008": {
-		"prefix": "process_combinatorial_2008",
-		"body": [
-			"process (all)",
-			"begin",
-			"\t$0",
-			"end process;"
-		],
-		"description": "combinatorial process block (vhdl 2008)"
-	},
-	"Process Asynchronous": {
-		"prefix": "process_asynchronous",
-		"body": [
-			"process (${1:clk}, ${2:reset})",
-			"begin",
-			"\tif $2 = ${3|'1','0'|} then",
-			"\t\t$4",
-			"\telsif rising_edge($1) then",
-			"\t\t$0",
-			"\tend if;",
-			"end process;"
-		],
-		"description": "asynchronous process block"
-	},
-	"Process Clocked": {
-		"prefix": ["process_clocked"],
-		"body": [
-			"process (${1:clk})",
-			"begin",
-			"\tif rising_edge($1) then",
-			"\t\tif ${2:reset} = ${3|'1','0'|} then",
-			"\t\t\t$4",
-			"\t\telse",
-			"\t\t\t$0",
-			"\t\tend if;",
-			"\tend if;",
-			"end process;"
-		],
-		"description": "clocked process block"
-	},
-	"Function": {
-		"prefix": "function",
-		"body": [
-			"function ${1:name} (${2:params}) return ${3:type} is",
-			"begin",
-			"\t$0",
-			"end function;"
-		],
-		"description": "function body declaration"
-	},
-	"Procedure": {
-		"prefix": "procedure",
-		"body": [
-			"procedure ${1:name} (${2:params}) is",
-			"begin",
-			"\t$0",
-			"end procedure;"
-		],
-		"description": "procedure body declaration"
-	},
-	"Package": {
-		"prefix": "package",
-		"body": [
-			"package ${1:$TM_FILENAME_BASE} is",
-			"\t$0",
-			"end package;"
-		],
-		"description": "package declaration"
-	},
-	"Package Body": {
-		"prefix": "package_body",
-		"body": [
-			"package body ${1:$TM_FILENAME_BASE} is",
-			"\t$0",
-			"end package;"
-		],
-		"description": "package body declaration"
-	},
-	"Natural Range": {
-		"prefix": "natural_range",
-		"body": [ "natural range<>" ],
-		"description": "natural range statement"
-	}
-}
diff --git a/vscode-client/snippets/snippets.vhdl.libraries.json b/vscode-client/snippets/snippets.vhdl.library.json
similarity index 93%
rename from vscode-client/snippets/snippets.vhdl.libraries.json
rename to vscode-client/snippets/snippets.vhdl.library.json
index 880560c..a543068 100644
--- a/vscode-client/snippets/snippets.vhdl.libraries.json
+++ b/vscode-client/snippets/snippets.vhdl.library.json
@@ -48,7 +48,7 @@
 	"Use IEEE Package": {
 		"prefix": "use_ieee",
 		"body": [
-			"use ieee.${1|std_logic_1164,std_logic_textio,numeric_std,math_real,math_complex|}.all;",
+			"use ieee.${1|std_logic_1164,std_logic_textio,numeric_std,numeric_bit,math_real,math_complex|}.all;",
 			"$0"
 		],
 		"description": "use clause IEEE standard package (std_logic_1164,std_logic_textio,numeric_std,math_real,math_complex)"
diff --git a/vscode-client/snippets/snippets.vhdl.logic.json b/vscode-client/snippets/snippets.vhdl.logic.json
new file mode 100644
index 0000000..bc1cd77
--- /dev/null
+++ b/vscode-client/snippets/snippets.vhdl.logic.json
@@ -0,0 +1,118 @@
+{
+	"Case": {
+		"prefix": "case",
+		"body": [
+			"case ${1:select} is",
+			"\twhen ${2:others} =>",
+			"\t\t${3:null;}",
+			"\t$0",
+			"end case;"
+		],
+		"description": "case block"
+	},
+	"If": {
+		"prefix": "if",
+		"body": [
+			"if ${1:expression} then",
+			"\t$0",
+			"end if;"
+		],
+		"description": "if block"
+	},
+	"Elsif": {
+		"prefix": "elsif",
+		"body": [
+			"elsif ${1:expression} then",
+			"\t$0"
+		],
+		"description": "elsif block"
+	},
+	"Else": {
+		"prefix": "else",
+		"body": [
+			"else",
+			"\t$0"
+		],
+		"description": "else block"
+	},
+	"For": {
+		"prefix": "for",
+		"body": [
+			"for ${1:i} in ${2:range} loop",
+			"\t$0",
+			"end loop;"
+		],
+		"description": "for loop block"
+	},
+	"Process Asynchronous": {
+		"prefix": "process_asynchronous",
+		"body": [
+			"process (${1:clk}, ${2:reset})",
+			"begin",
+			"\tif $2 = ${3|'1','0'|} then",
+			"\t\t$4",
+			"\telsif rising_edge($1) then",
+			"\t\t$0",
+			"\tend if;",
+			"end process;"
+		],
+		"description": "asynchronous process block"
+	},
+	"Process Synchronous": {
+		"prefix": ["process_synchronous"],
+		"body": [
+			"process (${1:clk})",
+			"begin",
+			"\tif rising_edge($1) then",
+			"\t\tif ${2:reset} = ${3|'1','0'|} then",
+			"\t\t\t$4",
+			"\t\telse",
+			"\t\t\t$0",
+			"\t\tend if;",
+			"\tend if;",
+			"end process;"
+		],
+		"description": "clocked process block"
+	},
+	"Process Clocked": {
+		"prefix": ["process_clocked"],
+		"body": [
+			"process (${1:clk})",
+			"begin",
+			"\tif rising_edge($1) then",
+			"\t\t$0",
+			"\tend if;",
+			"end process;"
+		],
+		"description": "clocked process block"
+	},
+	"Process Combinatorial": {
+		"prefix": "process_combinatorial",
+		"body": [
+			"process (${1:sensitivity_list})",
+			"begin",
+			"\t$0",
+			"end process;"
+		],
+		"description": "combinatorial process block"
+	},
+	"Process Combinatorial 2008": {
+		"prefix": "process_combinatorial_2008",
+		"body": [
+			"process (all)",
+			"begin",
+			"\t$0",
+			"end process;"
+		],
+		"description": "combinatorial process block (vhdl 2008)"
+	},
+	"While": {
+		"prefix": "while",
+		"body": [
+			"while ${1:expression} loop",
+			"\t$0",
+			"end loop;"
+		],
+		"description": "while loop block"
+	}
+}
diff --git a/vscode-client/snippets/snippets.vhdl.types.json b/vscode-client/snippets/snippets.vhdl.types.json
deleted file mode 100644
index fc9fe75..0000000
--- a/vscode-client/snippets/snippets.vhdl.types.json
+++ /dev/null
@@ -1,37 +0,0 @@
-{
-	"Standard Logic": {
-		"prefix": ["std_logic", "sl"],
-		"body": [ "std_logic${1| := ,;|}$0" ],
-		"description": "std_logic type"
-	},
-	"Standard Logic Type": {
-		"prefix": ["std_logic", "sl"],
-		"body": [ "std_logic${1| := ,;|}$0" ],
-		"description": "std_logic type"
-	},
-	"Standard ULogic": {
-		"prefix": ["std_ulogic", "sul"],
-		"body": [ "std_ulogic${1| := ,;|}$0" ],
-		"description": "std_ulogic type"
-	},
-	"Standard Logic Vector": {
-		"prefix": ["std_logic_vector", "slv"],
-		"body": [ "std_logic_vector($1 ${2|downto,to|} $3)${4| := ,;|}$0" ],
-		"description": "std_logic_vector type"
-	},
-	"Standard ULogic Vector": {
-		"prefix": ["std_ulogic_vector", "sulv"],
-		"body": [ "std_ulogic_vector($1 ${2|downto,to|} $3)${4| := ,;|}$0" ],
-		"description": "std_ulogic_vector type"
-	},
-	"Signed": {
-		"prefix": "signed",
-		"body": [ "signed($1 ${2|downto,to|} $3)${4| := ,;|}$0" ],
-		"description": "signed type"
-	},
-	"Unsigned": {
-		"prefix": "unsigned",
-		"body": [ "unsigned(${1} ${2|downto,to|} ${3})${4| := ,;|}$0" ],
-		"description": "unsigned type"
-	}
-}

From 0ef984e29e2acea978143011a7a5436e6cb73280 Mon Sep 17 00:00:00 2001
From: Glen Nicholls <Glen.Nicholls@kratosdefense.com>
Date: Thu, 14 Nov 2019 20:21:46 -0700
Subject: [PATCH 7/8] re-organized before merging with master for #32

---
 vscode-client/snippets/snippets.generate.json | 36 +++++------
 .../snippets/snippets.vhdl.declaration.json   | 39 +-----------
 .../snippets/snippets.vhdl.interface.json     | 63 +++++++++++++++++--
 .../snippets/snippets.vhdl.library.json       |  2 +-
 .../snippets/snippets.vhdl.logic.json         | 39 +++++++++++-
 5 files changed, 115 insertions(+), 64 deletions(-)

diff --git a/vscode-client/snippets/snippets.generate.json b/vscode-client/snippets/snippets.generate.json
index aeab149..df398fd 100644
--- a/vscode-client/snippets/snippets.generate.json
+++ b/vscode-client/snippets/snippets.generate.json
@@ -1,4 +1,22 @@
 {
+	"Generate If": {
+		"prefix": "generate_if",
+		"body": [
+			"gen_${1:generateName} : if ${2:expression} generate",
+			"\t$0",
+			"end generate;"
+		],
+		"description": "if generate instantiation"
+	},
+	"Generate For": {
+		"prefix": "generate_for",
+		"body": [
+			"gen_loop_${1:generateName} : for ${2:i} in ${3:range} generate",
+			"\t$0",
+			"end generate;"
+		],
+		"description": "for generate loop instantiation (vhdl 2008)"
+	},
 	"Generate Case 2008": {
 		"prefix": "generate_case_2008",
 		"body": [
@@ -10,15 +28,6 @@
 		],
 		"description": "case generate instantiation (vhdl 2008)"
 	},
-	"Generate If": {
-		"prefix": "generate_if",
-		"body": [
-			"gen_${1:generateName} : if ${2:expression} generate",
-			"\t$0",
-			"end generate;"
-		],
-		"description": "if generate instantiation"
-	},
 	"Generate Elsif 2008": {
 		"prefix": "generate_elsif_2008",
 		"body": [
@@ -34,14 +43,5 @@
 			"\t\t$0"
 		],
 		"description": "else generate instantiation (vhdl 2008)"
-	},
-	"Generate For": {
-		"prefix": "generate_for",
-		"body": [
-			"gen_loop_${1:generateName} : for ${2:i} in ${3:range} generate",
-			"\t$0",
-			"end generate;"
-		],
-		"description": "for generate loop instantiation (vhdl 2008)"
 	}
 }
diff --git a/vscode-client/snippets/snippets.vhdl.declaration.json b/vscode-client/snippets/snippets.vhdl.declaration.json
index 6a10beb..309e016 100644
--- a/vscode-client/snippets/snippets.vhdl.declaration.json
+++ b/vscode-client/snippets/snippets.vhdl.declaration.json
@@ -30,16 +30,6 @@
 		],
 		"description": "synthesizable attributes (high,low,left,right,range,reverse_range,length,event)"
 	},
-	"Assert": {
-		"prefix": "assert",
-		"body": [
-			"assert ${1:expression}",
-			"\treport \"${2:string}\"",
-			"\tseverity ${3|note,warning,error,failure|};",
-			"$0"
-		 ],
-		"description": "assert declaration"
-	},
 	"Constant": {
 		"prefix": "constant",
 		"body": [
@@ -78,7 +68,7 @@
 		],
 		"description": "procedure body declaration"
 	},
-	"Record Type": {
+	"Record": {
 		"prefix": "record",
 		"body": [
 			"type ${1:name} is record",
@@ -126,33 +116,6 @@
 		"body": [ "unsigned(${1} ${2|downto,to|} ${3})${4| := ,;|}$0" ],
 		"description": "unsigned declaration"
 	},
-	"When": {
-		"prefix": "when",
-		"body": [
-			"when ${1:others} =>",
-			"\t$0"
-		],
-		"description": "when declaration"
-	},
-	"When Else": {
-		"prefix": "when_else",
-		"body": [
-			"${1:signal} <= ${2:first_value} when ${3:expression}",
-			"\telse ${4:final_value};",
-			"$0"
-		],
-		"description": "concurrent when else declaration"
-	},
-	"With Select": {
-		"prefix": ["select", "with_select"],
-		"body": [
-			"with ${1:select} select",
-			"\t${2:signal} <= ${3:first_value} when ${4:select_value},",
-			"\t\t${5:last_value} when others;",
-			"$0"
-		],
-		"description": "concurrent with select declaration"
-	},
 	"Variable": {
 		"prefix": "variable",
 		"body": [
diff --git a/vscode-client/snippets/snippets.vhdl.interface.json b/vscode-client/snippets/snippets.vhdl.interface.json
index 3d993d1..c89ee18 100644
--- a/vscode-client/snippets/snippets.vhdl.interface.json
+++ b/vscode-client/snippets/snippets.vhdl.interface.json
@@ -1,7 +1,7 @@
 {
 	// TODO: package generics
 	// TODO: configuration
-	"Architecture Interface": {
+	"Architecture": {
 		"prefix": "architecture",
 		"body": [
 			"architecture ${1:behav} of ${2:$TM_FILENAME_BASE} is",
@@ -11,7 +11,7 @@
 		],
 		"description": "architecture interface"
 	},
-	"Block Interface": {
+	"Block": {
 		"prefix": "block",
 		"body": [
 			"blk_${1:blockName} : block ${2| ,optional_guard_expression|}",
@@ -21,7 +21,22 @@
 		],
 		"description": "block interface"
 	},
-	"Component Interface": {
+	"Component": {
+		"prefix":"component",
+		"body": [
+			"${1:instanceName}_inst: ${2:entity work.compName}",
+			"\tgeneric map (",
+			"\t\t${3:generics}",
+			"\t)",
+			"\tport map (",
+			"\t\t${4:clk   => clk,}",
+			"\t\t${5:reset => reset,}",
+			"\t\t$0",
+			"\t);"
+		],
+		"description": "component instantiation"
+	},
+	"Component": {
 		"prefix":"component",
 		"body": [
 			"component ${1:comp_name} is",
@@ -37,7 +52,7 @@
 		],
 		"description": "component interface"
 	},
-	"Entity Interface": {
+	"Entity": {
 	"prefix": "entity",
 		"body": [
 			"entity ${1:$TM_FILENAME_BASE} is",
@@ -53,7 +68,25 @@
 		],
 		"description": "entity interface"
 	},
-	"Package Interface": {
+	"Generic": {
+		"prefix": "generic",
+		"body": [
+			"generic (",
+			"\t${2:generics}",
+			");"
+		],
+		"description": "generic interface"
+	},
+	"Generic Map": {
+		"prefix": "generic_map",
+		"body": [
+			"generic map (",
+			"\t${2:generics}",
+			")"
+		],
+		"description": "generic map interface"
+	},
+	"Package": {
 		"prefix": "package",
 		"body": [
 			"package ${1:$TM_FILENAME_BASE} is",
@@ -62,7 +95,7 @@
 		],
 		"description": "package interface"
 	},
-	"Package Body Interface": {
+	"Package Body": {
 		"prefix": "package_body",
 		"body": [
 			"package body ${1:$TM_FILENAME_BASE} is",
@@ -70,5 +103,23 @@
 			"end package;"
 		],
 		"description": "package body interface"
+	},
+	"Port": {
+		"prefix": "port",
+		"body": [
+			"port (",
+			"\t${2:ports}",
+			");"
+		],
+		"description": "port interface"
+	},
+	"Port Map": {
+		"prefix": "port_map",
+		"body": [
+			"port map (",
+			"\t${2:ports}",
+			");"
+		],
+		"description": "port map interface"
 	}
 }
diff --git a/vscode-client/snippets/snippets.vhdl.library.json b/vscode-client/snippets/snippets.vhdl.library.json
index a543068..a8f46c1 100644
--- a/vscode-client/snippets/snippets.vhdl.library.json
+++ b/vscode-client/snippets/snippets.vhdl.library.json
@@ -68,5 +68,5 @@
 			"$0"
 		],
 		"description": "context clause for IEEE standard contexts (ieee_bit_context,ieee_std_context) (vhdl 2008)"
-	},
+	}
 }
diff --git a/vscode-client/snippets/snippets.vhdl.logic.json b/vscode-client/snippets/snippets.vhdl.logic.json
index bc1cd77..252cc58 100644
--- a/vscode-client/snippets/snippets.vhdl.logic.json
+++ b/vscode-client/snippets/snippets.vhdl.logic.json
@@ -1,8 +1,18 @@
 {
+	"Assert": {
+		"prefix": "assert",
+		"body": [
+			"assert ${1:expression}",
+			"\treport \"${2:string}\"",
+			"\tseverity ${3|note,warning,error,failure|};",
+			"$0"
+		 ],
+		"description": "assert declaration"
+	},
 	"Case": {
 		"prefix": "case",
 		"body": [
-			"case ${1:select} is",
+			"case ${1:sel} is",
 			"\twhen ${2:others} =>",
 			"\t\t${3:null;}",
 			"\t$0",
@@ -106,6 +116,23 @@
 		],
 		"description": "combinatorial process block (vhdl 2008)"
 	},
+	"When": {
+		"prefix": "when",
+		"body": [
+			"when ${1:others} =>",
+			"\t$0"
+		],
+		"description": "when declaration"
+	},
+	"When Else": {
+		"prefix": "when_else",
+		"body": [
+			"${1:signal} <= ${2:first_value} when ${3:expression}",
+			"\telse ${4:final_value};",
+			"$0"
+		],
+		"description": "concurrent when else declaration"
+	},
 	"While": {
 		"prefix": "while",
 		"body": [
@@ -114,5 +141,15 @@
 			"end loop;"
 		],
 		"description": "while loop block"
+	},
+	"With Select": {
+		"prefix": ["select", "with_select"],
+		"body": [
+			"with ${1:sel} select",
+			"\t${2:signal} <= ${3:first_value} when ${4:select_value},",
+			"\t\t${5:last_value} when others;",
+			"$0"
+		],
+		"description": "concurrent with select declaration"
 	}
 }

From 7e7e374e1af8dec6af5ad87e9c54988c255416ab Mon Sep 17 00:00:00 2001
From: Glen Nicholls <Glen.Nicholls@kratosdefense.com>
Date: Thu, 14 Nov 2019 20:32:58 -0700
Subject: [PATCH 8/8] fixed file name issue and duplicate snippet in interface

---
 vscode-client/package.json                    |  6 ++--
 ...erate.json => snippets.vhdl.generate.json} |  0
 .../snippets/snippets.vhdl.interface.json     | 30 +++++++++----------
 3 files changed, 18 insertions(+), 18 deletions(-)
 rename vscode-client/snippets/{snippets.generate.json => snippets.vhdl.generate.json} (100%)

diff --git a/vscode-client/package.json b/vscode-client/package.json
index 6a03749..af9da82 100644
--- a/vscode-client/package.json
+++ b/vscode-client/package.json
@@ -45,11 +45,11 @@
 		"snippets": [
 			{
 				"language": "vhdl",
-				"path": "./snippets/snippets.vhdl.generate.json"
+				"path": "./snippets/snippets.vhdl.declaration.json"
 			},
 			{
 				"language": "vhdl",
-				"path": "./snippets/snippets.vhdl.declaration.json"
+				"path": "./snippets/snippets.vhdl.generate.json"
 			},
 			{
 				"language": "vhdl",
@@ -61,7 +61,7 @@
 			},
 			{
 				"language": "vhdl",
-				"path": "./snippets/snippets.vhdl.locic.json"
+				"path": "./snippets/snippets.vhdl.logic.json"
 			}
 		],
 		"commands": [
diff --git a/vscode-client/snippets/snippets.generate.json b/vscode-client/snippets/snippets.vhdl.generate.json
similarity index 100%
rename from vscode-client/snippets/snippets.generate.json
rename to vscode-client/snippets/snippets.vhdl.generate.json
diff --git a/vscode-client/snippets/snippets.vhdl.interface.json b/vscode-client/snippets/snippets.vhdl.interface.json
index c89ee18..ddf4089 100644
--- a/vscode-client/snippets/snippets.vhdl.interface.json
+++ b/vscode-client/snippets/snippets.vhdl.interface.json
@@ -21,21 +21,6 @@
 		],
 		"description": "block interface"
 	},
-	"Component": {
-		"prefix":"component",
-		"body": [
-			"${1:instanceName}_inst: ${2:entity work.compName}",
-			"\tgeneric map (",
-			"\t\t${3:generics}",
-			"\t)",
-			"\tport map (",
-			"\t\t${4:clk   => clk,}",
-			"\t\t${5:reset => reset,}",
-			"\t\t$0",
-			"\t);"
-		],
-		"description": "component instantiation"
-	},
 	"Component": {
 		"prefix":"component",
 		"body": [
@@ -52,6 +37,21 @@
 		],
 		"description": "component interface"
 	},
+	"Component Instantiation": {
+		"prefix":"component_instantiation",
+		"body": [
+			"${1:instanceName}_inst: ${2:entity work.compName}",
+			"\tgeneric map (",
+			"\t\t${3:generics}",
+			"\t)",
+			"\tport map (",
+			"\t\t${4:clk   => clk,}",
+			"\t\t${5:reset => reset,}",
+			"\t\t$0",
+			"\t);"
+		],
+		"description": "component instantiation"
+	},
 	"Entity": {
 	"prefix": "entity",
 		"body": [