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Issues: ghdl/ghdl-yosys-plugin
Feature suggestion: add a
ghdl_write_vhdl
command to yosys ...
#112
opened Apr 22, 2020 by
rlee287
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The project Keccak_PPL has several VHDL compilation issues (Fails to synthesize).
#190
opened Sep 17, 2023 by
alaindargelas
Another case of "wire not found for $posedge" - related to async resets?
#164
opened Jan 5, 2022 by
robinsonb5
VHDL to Verilog conversion with yosys-ghdl-plugin -- how to perserve signal names
#153
opened Aug 10, 2021 by
71GA
Mixed synthesis with a Verilog top-level fails when parameters are specified
#136
opened Oct 11, 2020 by
rodrigomelo9
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