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| 1 | +// Copyright 2021 The Go Authors. All rights reserved. |
| 2 | +// Use of this source code is governed by a BSD-style |
| 3 | +// license that can be found in the LICENSE file. |
| 4 | + |
| 5 | +// +build arm64 |
| 6 | +// +build android |
| 7 | + |
| 8 | +package cpu |
| 9 | + |
| 10 | +// HWCAP/HWCAP2 bits. These are exposed by Linux. |
| 11 | +const ( |
| 12 | + hwcap_FP = 1 << 0 |
| 13 | + hwcap_ASIMD = 1 << 1 |
| 14 | + hwcap_EVTSTRM = 1 << 2 |
| 15 | + hwcap_AES = 1 << 3 |
| 16 | + hwcap_PMULL = 1 << 4 |
| 17 | + hwcap_SHA1 = 1 << 5 |
| 18 | + hwcap_SHA2 = 1 << 6 |
| 19 | + hwcap_CRC32 = 1 << 7 |
| 20 | + hwcap_ATOMICS = 1 << 8 |
| 21 | + hwcap_FPHP = 1 << 9 |
| 22 | + hwcap_ASIMDHP = 1 << 10 |
| 23 | + hwcap_CPUID = 1 << 11 |
| 24 | + hwcap_ASIMDRDM = 1 << 12 |
| 25 | + hwcap_JSCVT = 1 << 13 |
| 26 | + hwcap_FCMA = 1 << 14 |
| 27 | + hwcap_LRCPC = 1 << 15 |
| 28 | + hwcap_DCPOP = 1 << 16 |
| 29 | + hwcap_SHA3 = 1 << 17 |
| 30 | + hwcap_SM3 = 1 << 18 |
| 31 | + hwcap_SM4 = 1 << 19 |
| 32 | + hwcap_ASIMDDP = 1 << 20 |
| 33 | + hwcap_SHA512 = 1 << 21 |
| 34 | + hwcap_SVE = 1 << 22 |
| 35 | + hwcap_ASIMDFHM = 1 << 23 |
| 36 | +) |
| 37 | + |
| 38 | +func osInit() { |
| 39 | + if err := readHWCAP(); err != nil { |
| 40 | + // failed to read /proc/self/auxv, try reading registers directly |
| 41 | + readARM64Registers() |
| 42 | + return |
| 43 | + } |
| 44 | + |
| 45 | + // Use HWCap information since reading aarch64 system registers |
| 46 | + // is not supported in user space on older linux kernels. |
| 47 | + ARM64.HasFP = isSet(hwCap, hwcap_FP) |
| 48 | + ARM64.HasASIMD = isSet(hwCap, hwcap_ASIMD) |
| 49 | + ARM64.HasEVTSTRM = isSet(hwCap, hwcap_EVTSTRM) |
| 50 | + ARM64.HasAES = isSet(hwCap, hwcap_AES) |
| 51 | + ARM64.HasPMULL = isSet(hwCap, hwcap_PMULL) |
| 52 | + ARM64.HasSHA1 = isSet(hwCap, hwcap_SHA1) |
| 53 | + ARM64.HasSHA2 = isSet(hwCap, hwcap_SHA2) |
| 54 | + ARM64.HasCRC32 = isSet(hwCap, hwcap_CRC32) |
| 55 | + ARM64.HasFPHP = isSet(hwCap, hwcap_FPHP) |
| 56 | + ARM64.HasASIMDHP = isSet(hwCap, hwcap_ASIMDHP) |
| 57 | + ARM64.HasASIMDRDM = isSet(hwCap, hwcap_ASIMDRDM) |
| 58 | + ARM64.HasJSCVT = isSet(hwCap, hwcap_JSCVT) |
| 59 | + ARM64.HasFCMA = isSet(hwCap, hwcap_FCMA) |
| 60 | + ARM64.HasLRCPC = isSet(hwCap, hwcap_LRCPC) |
| 61 | + ARM64.HasDCPOP = isSet(hwCap, hwcap_DCPOP) |
| 62 | + ARM64.HasSHA3 = isSet(hwCap, hwcap_SHA3) |
| 63 | + ARM64.HasSM3 = isSet(hwCap, hwcap_SM3) |
| 64 | + ARM64.HasSM4 = isSet(hwCap, hwcap_SM4) |
| 65 | + ARM64.HasASIMDDP = isSet(hwCap, hwcap_ASIMDDP) |
| 66 | + ARM64.HasSHA512 = isSet(hwCap, hwcap_SHA512) |
| 67 | + ARM64.HasSVE = isSet(hwCap, hwcap_SVE) |
| 68 | + ARM64.HasASIMDFHM = isSet(hwCap, hwcap_ASIMDFHM) |
| 69 | + |
| 70 | + // The Samsung S9+ kernel reports support for atomics, but not all cores |
| 71 | + // actually support them, resulting in SIGILL. See issue #28431. |
| 72 | + // TODO(elias.naur): Only disable the optimization on bad chipsets on android. |
| 73 | + ARM64.HasATOMICS = false |
| 74 | +} |
| 75 | + |
| 76 | +func isSet(hwc uint, value uint) bool { |
| 77 | + return hwc&value != 0 |
| 78 | +} |
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