diff --git a/src/idmap.rs b/src/idmap.rs index 3cb5d94..40318e0 100644 --- a/src/idmap.rs +++ b/src/idmap.rs @@ -9,7 +9,7 @@ use crate::{ paging::{ attributes::Attributes, deallocate, Constraints, Descriptor, MemoryRegion, PageTable, - PhysicalAddress, Translation, TranslationRegime, VaRange, VirtualAddress, + PhysicalAddress, Translation, VaRange, VirtualAddress, }, MapError, Mapping, }; @@ -65,7 +65,7 @@ impl Translation for IdTranslation { /// ```no_run /// use aarch64_paging::{ /// idmap::IdMap, -/// paging::{attributes::AttributesEl1, MemoryRegion, TranslationRegime}, +/// paging::{attributes::AttributesEl1, MemoryRegion}, /// }; /// /// const ASID: usize = 1; @@ -74,7 +74,7 @@ impl Translation for IdTranslation { /// AttributesEl1::ATTRIBUTE_INDEX_1.union(AttributesEl1::INNER_SHAREABLE); /// /// // Create a new EL1 page table with identity mapping. -/// let mut idmap = IdMap::new(ASID, ROOT_LEVEL, TranslationRegime::El1And0); +/// let mut idmap = IdMap::new(ASID, ROOT_LEVEL); /// // Map a 2 MiB region of memory as read-write. /// idmap /// .map_range( @@ -122,15 +122,9 @@ pub struct IdMap { impl IdMap { /// Creates a new identity-mapping page table with the given ASID and root level. - pub fn new(asid: usize, rootlevel: usize, translation_regime: TranslationRegime) -> Self { + pub fn new(asid: usize, rootlevel: usize) -> Self { Self { - mapping: Mapping::new( - IdTranslation, - asid, - rootlevel, - translation_regime, - VaRange::Lower, - ), + mapping: Mapping::new(IdTranslation, asid, rootlevel, VaRange::Lower), } } @@ -356,7 +350,7 @@ mod tests { #[test] fn map_valid() { // A single byte at the start of the address space. - let mut idmap = IdMap::new(1, 1, TranslationRegime::El1And0); + let mut idmap = IdMap::new(1, 1); // SAFETY: This doesn't actually activate the page table in tests, it just treats it as // active for the sake of BBM rules. unsafe { @@ -371,7 +365,7 @@ mod tests { ); // Two pages at the start of the address space. - let mut idmap = IdMap::new(1, 1, TranslationRegime::El1And0); + let mut idmap = IdMap::new(1, 1); // SAFETY: This doesn't actually activate the page table in tests, it just treats it as // active for the sake of BBM rules. unsafe { @@ -386,7 +380,7 @@ mod tests { ); // A single byte at the end of the address space. - let mut idmap = IdMap::new(1, 1, TranslationRegime::El1And0); + let mut idmap = IdMap::new(1, 1); // SAFETY: This doesn't actually activate the page table in tests, it just treats it as // active for the sake of BBM rules. unsafe { @@ -404,7 +398,7 @@ mod tests { ); // Two pages, on the boundary between two subtables. - let mut idmap = IdMap::new(1, 1, TranslationRegime::El1And0); + let mut idmap = IdMap::new(1, 1); // SAFETY: This doesn't actually activate the page table in tests, it just treats it as // active for the sake of BBM rules. unsafe { @@ -419,7 +413,7 @@ mod tests { ); // The entire valid address space. - let mut idmap = IdMap::new(1, 1, TranslationRegime::El1And0); + let mut idmap = IdMap::new(1, 1); // SAFETY: This doesn't actually activate the page table in tests, it just treats it as // active for the sake of BBM rules. unsafe { @@ -437,7 +431,7 @@ mod tests { #[test] fn map_break_before_make() { const BLOCK_SIZE: usize = PAGE_SIZE << BITS_PER_LEVEL; - let mut idmap = IdMap::new(1, 1, TranslationRegime::El1And0); + let mut idmap = IdMap::new(1, 1); idmap .map_range_with_constraints( &MemoryRegion::new(BLOCK_SIZE, 2 * BLOCK_SIZE), @@ -460,7 +454,7 @@ mod tests { Ok(()) ); - let mut idmap = IdMap::new(1, 1, TranslationRegime::El1And0); + let mut idmap = IdMap::new(1, 1); idmap .map_range( &MemoryRegion::new(BLOCK_SIZE, 2 * BLOCK_SIZE), @@ -600,7 +594,7 @@ mod tests { #[test] fn map_out_of_range() { - let mut idmap = IdMap::new(1, 1, TranslationRegime::El1And0); + let mut idmap = IdMap::new(1, 1); // One byte, just past the edge of the valid range. assert_eq!( @@ -629,7 +623,7 @@ mod tests { } fn make_map() -> IdMap { - let mut idmap = IdMap::new(1, 1, TranslationRegime::El1And0); + let mut idmap = IdMap::new(1, 1); idmap .map_range( &MemoryRegion::new(0, PAGE_SIZE * 2), @@ -701,7 +695,7 @@ mod tests { #[test] fn breakup_invalid_block() { const BLOCK_RANGE: usize = 0x200000; - let mut idmap = IdMap::new(1, 1, TranslationRegime::El1And0); + let mut idmap = IdMap::new(1, 1); // SAFETY: This doesn't actually activate the page table in tests, it just treats it as // active for the sake of BBM rules. unsafe { @@ -740,7 +734,7 @@ mod tests { /// When an unmapped entry is split into a table, all entries should be zero. #[test] fn split_table_zero() { - let mut idmap = IdMap::new(1, 1, TranslationRegime::El1And0); + let mut idmap = IdMap::new(1, 1); idmap .map_range( diff --git a/src/lib.rs b/src/lib.rs index d7a0db3..1af53d9 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -19,7 +19,7 @@ //! # #[cfg(feature = "alloc")] { //! use aarch64_paging::{ //! idmap::IdMap, -//! paging::{attributes::AttributesEl1, MemoryRegion, TranslationRegime}, +//! paging::{attributes::AttributesEl1, MemoryRegion}, //! }; //! //! const ASID: usize = 1; @@ -28,7 +28,7 @@ //! AttributesEl1::ATTRIBUTE_INDEX_1.union(AttributesEl1::INNER_SHAREABLE); //! //! // Create a new EL1 page table with identity mapping. -//! let mut idmap = IdMap::new(ASID, ROOT_LEVEL, TranslationRegime::El1And0); +//! let mut idmap = IdMap::new(ASID, ROOT_LEVEL); //! // Map a 2 MiB region of memory as read-write. //! idmap //! .map_range( @@ -68,8 +68,8 @@ use core::arch::asm; use core::fmt::{self, Display, Formatter}; use paging::{ attributes::{Attributes, CommonAttributes}, - Constraints, Descriptor, MemoryRegion, PhysicalAddress, RootTable, Translation, - TranslationRegime, VaRange, VirtualAddress, + Constraints, Descriptor, MemoryRegion, PhysicalAddress, RootTable, Translation, VaRange, + VirtualAddress, }; /// An error attempting to map some range in the page table. @@ -131,18 +131,15 @@ pub struct Mapping, A: Attributes> { impl, A: Attributes> Mapping { /// Creates a new page table with the given ASID, root level and translation mapping. - pub fn new( - translation: T, - asid: usize, - rootlevel: usize, - translation_regime: TranslationRegime, - va_range: VaRange, - ) -> Self { - if !translation_regime.supports_asid() && asid != 0 { - panic!("{:?} doesn't support ASID, must be 0.", translation_regime); + pub fn new(translation: T, asid: usize, rootlevel: usize, va_range: VaRange) -> Self { + if !A::TRANSLATION_REGIME.supports_asid() && asid != 0 { + panic!( + "{:?} doesn't support ASID, must be 0.", + A::TRANSLATION_REGIME + ); } Self { - root: RootTable::new(translation, rootlevel, translation_regime, va_range), + root: RootTable::new(translation, rootlevel, va_range), asid, previous_ttbr: None, } @@ -539,25 +536,13 @@ mod tests { #[test] #[should_panic] fn no_el2_asid() { - Mapping::::new( - IdTranslation, - 1, - 1, - TranslationRegime::El2, - VaRange::Lower, - ); + Mapping::::new(IdTranslation, 1, 1, VaRange::Lower); } #[cfg(feature = "alloc")] #[test] #[should_panic] fn no_el3_asid() { - Mapping::::new( - IdTranslation, - 1, - 1, - TranslationRegime::El3, - VaRange::Lower, - ); + Mapping::::new(IdTranslation, 1, 1, VaRange::Lower); } } diff --git a/src/linearmap.rs b/src/linearmap.rs index 0172b33..0722588 100644 --- a/src/linearmap.rs +++ b/src/linearmap.rs @@ -9,8 +9,7 @@ use crate::{ paging::{ attributes::Attributes, deallocate, is_aligned, Constraints, Descriptor, MemoryRegion, - PageTable, PhysicalAddress, Translation, TranslationRegime, VaRange, VirtualAddress, - PAGE_SIZE, + PageTable, PhysicalAddress, Translation, VaRange, VirtualAddress, PAGE_SIZE, }, MapError, Mapping, }; @@ -115,21 +114,9 @@ impl LinearMap { /// `va + offset`. /// /// The `offset` must be a multiple of [`PAGE_SIZE`]; if not this will panic. - pub fn new( - asid: usize, - rootlevel: usize, - offset: isize, - translation_regime: TranslationRegime, - va_range: VaRange, - ) -> Self { + pub fn new(asid: usize, rootlevel: usize, offset: isize, va_range: VaRange) -> Self { Self { - mapping: Mapping::new( - LinearTranslation::new(offset), - asid, - rootlevel, - translation_regime, - va_range, - ), + mapping: Mapping::new(LinearTranslation::new(offset), asid, rootlevel, va_range), } } @@ -365,7 +352,7 @@ mod tests { #[test] fn map_valid() { // A single byte at the start of the address space. - let mut pagetable = LinearMap::new(1, 1, 4096, TranslationRegime::El1And0, VaRange::Lower); + let mut pagetable = LinearMap::new(1, 1, 4096, VaRange::Lower); assert_eq!( pagetable.map_range( &MemoryRegion::new(0, 1), @@ -375,7 +362,7 @@ mod tests { ); // Two pages at the start of the address space. - let mut pagetable = LinearMap::new(1, 1, 4096, TranslationRegime::El1And0, VaRange::Lower); + let mut pagetable = LinearMap::new(1, 1, 4096, VaRange::Lower); assert_eq!( pagetable.map_range( &MemoryRegion::new(0, PAGE_SIZE * 2), @@ -385,7 +372,7 @@ mod tests { ); // A single byte at the end of the address space. - let mut pagetable = LinearMap::new(1, 1, 4096, TranslationRegime::El1And0, VaRange::Lower); + let mut pagetable = LinearMap::new(1, 1, 4096, VaRange::Lower); assert_eq!( pagetable.map_range( &MemoryRegion::new( @@ -400,13 +387,7 @@ mod tests { // The entire valid address space. Use an offset that is a multiple of the level 2 block // size to avoid mapping everything as pages as that is really slow. const LEVEL_2_BLOCK_SIZE: usize = PAGE_SIZE << BITS_PER_LEVEL; - let mut pagetable = LinearMap::new( - 1, - 1, - LEVEL_2_BLOCK_SIZE as isize, - TranslationRegime::El1And0, - VaRange::Lower, - ); + let mut pagetable = LinearMap::new(1, 1, LEVEL_2_BLOCK_SIZE as isize, VaRange::Lower); assert_eq!( pagetable.map_range( &MemoryRegion::new(0, MAX_ADDRESS_FOR_ROOT_LEVEL_1), @@ -419,13 +400,7 @@ mod tests { #[test] fn map_valid_negative_offset() { // A single byte which maps to IPA 0. - let mut pagetable = LinearMap::new( - 1, - 1, - -(PAGE_SIZE as isize), - TranslationRegime::El1And0, - VaRange::Lower, - ); + let mut pagetable = LinearMap::new(1, 1, -(PAGE_SIZE as isize), VaRange::Lower); assert_eq!( pagetable.map_range( &MemoryRegion::new(PAGE_SIZE, PAGE_SIZE + 1), @@ -435,13 +410,7 @@ mod tests { ); // Two pages at the start of the address space. - let mut pagetable = LinearMap::new( - 1, - 1, - -(PAGE_SIZE as isize), - TranslationRegime::El1And0, - VaRange::Lower, - ); + let mut pagetable = LinearMap::new(1, 1, -(PAGE_SIZE as isize), VaRange::Lower); assert_eq!( pagetable.map_range( &MemoryRegion::new(PAGE_SIZE, PAGE_SIZE * 3), @@ -451,13 +420,7 @@ mod tests { ); // A single byte at the end of the address space. - let mut pagetable = LinearMap::new( - 1, - 1, - -(PAGE_SIZE as isize), - TranslationRegime::El1And0, - VaRange::Lower, - ); + let mut pagetable = LinearMap::new(1, 1, -(PAGE_SIZE as isize), VaRange::Lower); assert_eq!( pagetable.map_range( &MemoryRegion::new( @@ -472,13 +435,7 @@ mod tests { // The entire valid address space. Use an offset that is a multiple of the level 2 block // size to avoid mapping everything as pages as that is really slow. const LEVEL_2_BLOCK_SIZE: usize = PAGE_SIZE << BITS_PER_LEVEL; - let mut pagetable = LinearMap::new( - 1, - 1, - -(LEVEL_2_BLOCK_SIZE as isize), - TranslationRegime::El1And0, - VaRange::Lower, - ); + let mut pagetable = LinearMap::new(1, 1, -(LEVEL_2_BLOCK_SIZE as isize), VaRange::Lower); assert_eq!( pagetable.map_range( &MemoryRegion::new(LEVEL_2_BLOCK_SIZE, MAX_ADDRESS_FOR_ROOT_LEVEL_1), @@ -490,7 +447,7 @@ mod tests { #[test] fn map_out_of_range() { - let mut pagetable = LinearMap::new(1, 1, 4096, TranslationRegime::El1And0, VaRange::Lower); + let mut pagetable = LinearMap::new(1, 1, 4096, VaRange::Lower); // One byte, just past the edge of the valid range. assert_eq!( @@ -520,7 +477,7 @@ mod tests { #[test] fn map_invalid_offset() { - let mut pagetable = LinearMap::new(1, 1, -4096, TranslationRegime::El1And0, VaRange::Lower); + let mut pagetable = LinearMap::new(1, 1, -4096, VaRange::Lower); // One byte, with an offset which would map it to a negative IPA. assert_eq!( @@ -632,8 +589,7 @@ mod tests { #[test] fn block_mapping() { // Test that block mapping is used when the PA is appropriately aligned... - let mut pagetable = - LinearMap::new(1, 1, 1 << 30, TranslationRegime::El1And0, VaRange::Lower); + let mut pagetable = LinearMap::new(1, 1, 1 << 30, VaRange::Lower); pagetable .map_range( &MemoryRegion::new(0, 1 << 30), @@ -646,8 +602,7 @@ mod tests { ); // ...but not when it is not. - let mut pagetable = - LinearMap::new(1, 1, 1 << 29, TranslationRegime::El1And0, VaRange::Lower); + let mut pagetable = LinearMap::new(1, 1, 1 << 29, VaRange::Lower); pagetable .map_range( &MemoryRegion::new(0, 1 << 30), @@ -661,7 +616,7 @@ mod tests { } fn make_map() -> LinearMap { - let mut lmap = LinearMap::new(1, 1, 4096, TranslationRegime::El1And0, VaRange::Lower); + let mut lmap = LinearMap::new(1, 1, 4096, VaRange::Lower); // Mapping VA range 0x0 - 0x2000 to PA range 0x1000 - 0x3000 lmap.map_range(&MemoryRegion::new(0, PAGE_SIZE * 2), NORMAL_CACHEABLE) .unwrap(); @@ -712,7 +667,7 @@ mod tests { fn breakup_invalid_block() { const BLOCK_RANGE: usize = 0x200000; - let mut lmap = LinearMap::new(1, 1, 0x1000, TranslationRegime::El1And0, VaRange::Lower); + let mut lmap = LinearMap::new(1, 1, 0x1000, VaRange::Lower); lmap.map_range( &MemoryRegion::new(0, BLOCK_RANGE), NORMAL_CACHEABLE | AttributesEl1::NON_GLOBAL | AttributesEl1::SWFLAG_0, diff --git a/src/paging.rs b/src/paging.rs index 5d63627..e6d3890 100644 --- a/src/paging.rs +++ b/src/paging.rs @@ -261,7 +261,6 @@ pub struct RootTable, A: Attributes> { table: PageTableWithLevel, translation: T, pa: PhysicalAddress, - translation_regime: TranslationRegime, va_range: VaRange, } @@ -271,19 +270,14 @@ impl, A: Attributes> RootTable { /// The level must be between 0 and 3; level -1 (for 52-bit addresses with LPA2) is not /// currently supported by this library. The value of `TCR_EL1.T0SZ` must be set appropriately /// to match. - pub fn new( - mut translation: T, - level: usize, - translation_regime: TranslationRegime, - va_range: VaRange, - ) -> Self { + pub fn new(mut translation: T, level: usize, va_range: VaRange) -> Self { if level > LEAF_LEVEL { panic!("Invalid root table level {}.", level); } - if !translation_regime.supports_asid() && va_range != VaRange::Lower { + if !A::TRANSLATION_REGIME.supports_asid() && va_range != VaRange::Lower { panic!( "{:?} doesn't have an upper virtual address range.", - translation_regime + A::TRANSLATION_REGIME ); } let (table, pa) = PageTableWithLevel::new(&mut translation, level); @@ -291,7 +285,6 @@ impl, A: Attributes> RootTable { table, translation, pa, - translation_regime, va_range, } } @@ -340,11 +333,6 @@ impl, A: Attributes> RootTable { self.va_range } - /// Returns the translation regime for which this table is intended. - pub fn translation_regime(&self) -> TranslationRegime { - self.translation_regime - } - /// Returns a reference to the translation used for this page table. pub fn translation(&self) -> &T { &self.translation @@ -1108,23 +1096,13 @@ mod tests { #[test] #[should_panic] fn no_el2_ttbr1() { - RootTable::::new( - IdTranslation, - 1, - TranslationRegime::El2, - VaRange::Upper, - ); + RootTable::::new(IdTranslation, 1, VaRange::Upper); } #[cfg(feature = "alloc")] #[test] #[should_panic] fn no_el3_ttbr1() { - RootTable::::new( - IdTranslation, - 1, - TranslationRegime::El3, - VaRange::Upper, - ); + RootTable::::new(IdTranslation, 1, VaRange::Upper); } } diff --git a/src/target.rs b/src/target.rs index 160837e..7f8c251 100644 --- a/src/target.rs +++ b/src/target.rs @@ -31,7 +31,6 @@ use zerocopy::AsBytes; /// let mut map = RootTable::new( /// TargetAllocator::new(0x1_0000), /// ROOT_LEVEL, -/// TranslationRegime::El1And0, /// VaRange::Lower, /// ); /// map.map_range( @@ -143,20 +142,13 @@ impl Translation for TargetAllocator { #[cfg(all(test, feature = "zerocopy"))] mod tests { use super::*; - use crate::paging::{ - attributes::AttributesEl1, Constraints, MemoryRegion, RootTable, TranslationRegime, VaRange, - }; + use crate::paging::{attributes::AttributesEl1, Constraints, MemoryRegion, RootTable, VaRange}; const ROOT_LEVEL: usize = 1; #[test] fn map_one_page() { - let mut map = RootTable::new( - TargetAllocator::new(0x1_0000), - ROOT_LEVEL, - TranslationRegime::El1And0, - VaRange::Lower, - ); + let mut map = RootTable::new(TargetAllocator::new(0x1_0000), ROOT_LEVEL, VaRange::Lower); map.map_range( &MemoryRegion::new(0x0, 0x1000), PhysicalAddress(0x4_2000),