diff --git a/hw/core-v-mini-mcu/ao_peripheral_subsystem.sv b/hw/core-v-mini-mcu/ao_peripheral_subsystem.sv index e4392223e..504fed223 100644 --- a/hw/core-v-mini-mcu/ao_peripheral_subsystem.sv +++ b/hw/core-v-mini-mcu/ao_peripheral_subsystem.sv @@ -120,8 +120,8 @@ module ao_peripheral_subsystem output reg_req_t ext_peripheral_slave_req_o, input reg_rsp_t ext_peripheral_slave_resp_i, - input logic ext_dma_slot_0_i, - input logic ext_dma_slot_1_i + input logic ext_dma_slot_tx_i, + input logic ext_dma_slot_rx_i ); import core_v_mini_mcu_pkg::*; @@ -374,8 +374,8 @@ module ao_peripheral_subsystem assign dma_trigger_slots[2] = spi_flash_rx_valid; assign dma_trigger_slots[3] = spi_flash_tx_ready; assign dma_trigger_slots[4] = i2s_rx_valid_i; - assign dma_trigger_slots[5] = ext_dma_slot_0_i; - assign dma_trigger_slots[6] = ext_dma_slot_1_i; + assign dma_trigger_slots[5] = ext_dma_slot_tx_i; + assign dma_trigger_slots[6] = ext_dma_slot_rx_i; dma #( .reg_req_t (reg_pkg::reg_req_t), diff --git a/hw/core-v-mini-mcu/core_v_mini_mcu.sv b/hw/core-v-mini-mcu/core_v_mini_mcu.sv index cced77fac..3b86b0954 100644 --- a/hw/core-v-mini-mcu/core_v_mini_mcu.sv +++ b/hw/core-v-mini-mcu/core_v_mini_mcu.sv @@ -317,8 +317,8 @@ module core_v_mini_mcu output logic [31:0] exit_value_o, - input logic ext_dma_slot_0_i, - input logic ext_dma_slot_1_i + input logic ext_dma_slot_tx_i, + input logic ext_dma_slot_rx_i ); import core_v_mini_mcu_pkg::*; @@ -632,8 +632,8 @@ module core_v_mini_mcu .i2s_rx_valid_i(i2s_rx_valid), .ext_peripheral_slave_req_o, .ext_peripheral_slave_resp_i, - .ext_dma_slot_0_i, - .ext_dma_slot_1_i + .ext_dma_slot_tx_i, + .ext_dma_slot_rx_i ); peripheral_subsystem peripheral_subsystem_i ( diff --git a/hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl b/hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl index 8dd7188ec..4dcfc0f01 100644 --- a/hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl +++ b/hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl @@ -71,8 +71,8 @@ ${pad.core_v_mini_mcu_interface} output logic [31:0] exit_value_o, - input logic ext_dma_slot_0_i, - input logic ext_dma_slot_1_i + input logic ext_dma_slot_tx_i, + input logic ext_dma_slot_rx_i ); import core_v_mini_mcu_pkg::*; @@ -384,8 +384,8 @@ ${pad.core_v_mini_mcu_interface} .i2s_rx_valid_i(i2s_rx_valid), .ext_peripheral_slave_req_o, .ext_peripheral_slave_resp_i, - .ext_dma_slot_0_i, - .ext_dma_slot_1_i + .ext_dma_slot_tx_i, + .ext_dma_slot_rx_i ); peripheral_subsystem peripheral_subsystem_i ( diff --git a/hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv b/hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv index 7a5b91bdd..7fea99863 100644 --- a/hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv +++ b/hw/fpga/xilinx_core_v_mini_mcu_wrapper.sv @@ -192,8 +192,8 @@ module xilinx_core_v_mini_mcu_wrapper .i2s_sck_io(i2s_sck_io), .i2s_ws_io(i2s_ws_io), .i2s_sd_io(i2s_sd_io), - .ext_dma_slot_0_i, - .ext_dma_slot_1_i, + .ext_dma_slot_tx_i, + .ext_dma_slot_rx_i, ); assign exit_value_o = exit_value[0]; diff --git a/hw/ip/i2s/data/i2s.hjson b/hw/ip/i2s/data/i2s.hjson index 95b1e3be4..3a2f01317 100644 --- a/hw/ip/i2s/data/i2s.hjson +++ b/hw/ip/i2s/data/i2s.hjson @@ -109,7 +109,7 @@ hwext: "true" hwre: "true" fields: [ - { bits: "31:0", name: "RXDATA", desc: "latest rx data if DATA_READY flag is set", hwaccess: "hrw"} + { bits: "31:0", name: "RXDATA", desc: "latest rx data if DATA_READY flag is set" } ] } diff --git a/hw/ip/i2s/rtl/i2s.sv b/hw/ip/i2s/rtl/i2s.sv index aa101e62a..80735eca8 100644 --- a/hw/ip/i2s/rtl/i2s.sv +++ b/hw/ip/i2s/rtl/i2s.sv @@ -98,7 +98,6 @@ module i2s #( ); - // Core logic i2s_core #( .MaxWordWidth(MaxWordWidth), diff --git a/hw/ip_examples/iffifo/data/iffifo.hjson b/hw/ip_examples/iffifo/data/iffifo.hjson index 07a769228..ffc162783 100644 --- a/hw/ip_examples/iffifo/data/iffifo.hjson +++ b/hw/ip_examples/iffifo/data/iffifo.hjson @@ -2,47 +2,35 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -{ name: "iffifo", - clock_primary: "clk_i", +{ name: "iffifo" + clock_primary: "clk_i" bus_interfaces: [ { protocol: "reg_iface", direction: "device" } ], - regwidth: "32", + regwidth: 32 registers: [ - { name: "DUMMYR", - desc: "Does nothing.", - swaccess: "rw", - hwaccess: "hro", + + { name: "FIFO_OUT" + desc: "Data coming from the FIFO (Fifo Output/Software RX)." + swaccess: "ro" + hwaccess: "hrw" # required for RE signal + hwext: "true" # required for RE signal + hwre: "true" # Used to emulate a window behaviour fields: [ - { bits: "31:0", name: "DUMMY", desc: "Does nothing." } + { bits: "31:0", name: "FIFO_OUT", desc: "" } ] - }, - { name: "DUMMYW", - desc: "Does nothing.", - swaccess: "ro", - hwaccess: "hrw", + } + + { name: "FIFO_IN" + desc: "Data sent to the FIFO (Fifo Input/Software TX)." + hwaccess: "hro" + swaccess: "rw" # required for QE signal + hwqe: "true" # Used to emulate a window behaviour fields: [ - { bits: "31:0", name: "DUMMY", desc: "Does nothing." } + { bits: "31:0", name: "FIFO_IN", desc: "" } ] - }, - { window: { - name: "FIFO_OUT", - items: "1", - validbits: "32", - desc: '''Data coming from the FIFO (Fifo Output/Software RX) - ''' - swaccess: "ro" - } - } - { window: { - name: "FIFO_IN", - items: "1", - validbits: "32", - desc: '''Data sent to the FIFO (Fifo Input/Software TX) - ''' - swaccess: "wo" - } } + ] } diff --git a/hw/ip_examples/iffifo/iffifo.core b/hw/ip_examples/iffifo/iffifo.core index f70205f8e..f0e234634 100644 --- a/hw/ip_examples/iffifo/iffifo.core +++ b/hw/ip_examples/iffifo/iffifo.core @@ -18,7 +18,6 @@ filesets: - rtl/iffifo_reg_pkg.sv - rtl/iffifo_reg_top.sv - rtl/iffifo.sv - - rtl/iffifo_window.sv file_type: systemVerilogSource targets: diff --git a/hw/ip_examples/iffifo/iffifo_gen.sh b/hw/ip_examples/iffifo/iffifo_gen.sh index 2d6f3b594..45cc8f1cc 100755 --- a/hw/ip_examples/iffifo/iffifo_gen.sh +++ b/hw/ip_examples/iffifo/iffifo_gen.sh @@ -6,9 +6,3 @@ echo "Generating RTL" ${PYTHON} ../../vendor/pulp_platform_register_interface/vendor/lowrisc_opentitan/util/regtool.py -r -t rtl data/iffifo.hjson echo "Generating SW" ${PYTHON} ../../vendor/pulp_platform_register_interface/vendor/lowrisc_opentitan/util/regtool.py --cdefines -o ../../../sw/device/lib/drivers/iffifo/iffifo_regs.h data/iffifo.hjson - -echo -e "" -echo -e "" -echo -e ' \033[5m !!! \033[0m \033[1mIn rtl/iffifo_reg_top.sv, replace "logic [0:0] reg_steer;" by "logic [1:0] reg_steer;" \033[5m !!! \033[0m \033[0m' -echo -e "" -echo -e "" diff --git a/hw/ip_examples/iffifo/rtl/iffifo.sv b/hw/ip_examples/iffifo/rtl/iffifo.sv index 3708a2021..af141b8f8 100644 --- a/hw/ip_examples/iffifo/rtl/iffifo.sv +++ b/hw/ip_examples/iffifo/rtl/iffifo.sv @@ -21,14 +21,15 @@ module iffifo #( import iffifo_reg_pkg::*; - logic pop, push; - logic [WIDTH-1:0] fifin, fifout; + iffifo_reg2hw_t reg2hw; + iffifo_hw2reg_t hw2reg; + + logic [WIDTH-1:0] fifout; assign iffifo_in_ready_o = 1; assign iffifo_out_valid_o = 1; - reg_req_t [1:0] fifo_win_h2d; - reg_rsp_t [1:0] fifo_win_d2h; + assign hw2reg.fifo_out.d = fifout + 1; iffifo_reg_top #( .reg_req_t(reg_req_t), @@ -36,16 +37,13 @@ module iffifo #( ) iffifo_reg_top_i ( .clk_i, .rst_ni, - .reg2hw(), - .hw2reg(), + .reg2hw, + .hw2reg, .reg_req_i, .reg_rsp_o, - .reg_req_win_o(fifo_win_h2d), - .reg_rsp_win_i(fifo_win_d2h), .devmode_i(1'b0) ); - fifo_v3 #( .DEPTH(DEPTH), .DATA_WIDTH(WIDTH) @@ -57,25 +55,10 @@ module iffifo #( .full_o(), .empty_o(), .usage_o(), - .data_i(fifin), - .push_i(push), + .data_i(reg2hw.fifo_in.q), + .push_i(reg2hw.fifo_in.qe), .data_o(fifout), - .pop_i(pop) - ); - - iffifo_window #( - .reg_req_t(reg_req_t), - .reg_rsp_t(reg_rsp_t) - ) u_window ( - .rx_win_i (fifo_win_h2d[0]), - .rx_win_o (fifo_win_d2h[0]), - .tx_win_i (fifo_win_h2d[1]), - .tx_win_o (fifo_win_d2h[1]), - .tx_data_o (fifin), - .tx_be_o (), - .tx_valid_o(push), - .rx_data_i (fifout), - .rx_ready_o(pop) + .pop_i(reg2hw.fifo_out.re) ); endmodule : iffifo diff --git a/hw/ip_examples/iffifo/rtl/iffifo_reg_pkg.sv b/hw/ip_examples/iffifo/rtl/iffifo_reg_pkg.sv index a83c3c522..cee9d72ef 100644 --- a/hw/ip_examples/iffifo/rtl/iffifo_reg_pkg.sv +++ b/hw/ip_examples/iffifo/rtl/iffifo_reg_pkg.sv @@ -7,52 +7,52 @@ package iffifo_reg_pkg; // Address widths within the block - parameter int BlockAw = 4; + parameter int BlockAw = 3; //////////////////////////// // Typedefs for registers // //////////////////////////// - typedef struct packed {logic [31:0] q;} iffifo_reg2hw_dummyr_reg_t; - - typedef struct packed {logic [31:0] q;} iffifo_reg2hw_dummyw_reg_t; + typedef struct packed { + logic [31:0] q; + logic re; + } iffifo_reg2hw_fifo_out_reg_t; typedef struct packed { - logic [31:0] d; - logic de; - } iffifo_hw2reg_dummyw_reg_t; + logic [31:0] q; + logic qe; + } iffifo_reg2hw_fifo_in_reg_t; + + typedef struct packed {logic [31:0] d;} iffifo_hw2reg_fifo_out_reg_t; // Register -> HW type typedef struct packed { - iffifo_reg2hw_dummyr_reg_t dummyr; // [63:32] - iffifo_reg2hw_dummyw_reg_t dummyw; // [31:0] + iffifo_reg2hw_fifo_out_reg_t fifo_out; // [65:33] + iffifo_reg2hw_fifo_in_reg_t fifo_in; // [32:0] } iffifo_reg2hw_t; // HW -> register type typedef struct packed { - iffifo_hw2reg_dummyw_reg_t dummyw; // [32:0] + iffifo_hw2reg_fifo_out_reg_t fifo_out; // [31:0] } iffifo_hw2reg_t; // Register offsets - parameter logic [BlockAw-1:0] IFFIFO_DUMMYR_OFFSET = 4'h0; - parameter logic [BlockAw-1:0] IFFIFO_DUMMYW_OFFSET = 4'h4; + parameter logic [BlockAw-1:0] IFFIFO_FIFO_OUT_OFFSET = 3'h0; + parameter logic [BlockAw-1:0] IFFIFO_FIFO_IN_OFFSET = 3'h4; - // Window parameters - parameter logic [BlockAw-1:0] IFFIFO_FIFO_OUT_OFFSET = 4'h8; - parameter int unsigned IFFIFO_FIFO_OUT_SIZE = 'h4; - parameter logic [BlockAw-1:0] IFFIFO_FIFO_IN_OFFSET = 4'hc; - parameter int unsigned IFFIFO_FIFO_IN_SIZE = 'h4; + // Reset values for hwext registers and their fields + parameter logic [31:0] IFFIFO_FIFO_OUT_RESVAL = 32'h0; // Register index typedef enum int { - IFFIFO_DUMMYR, - IFFIFO_DUMMYW + IFFIFO_FIFO_OUT, + IFFIFO_FIFO_IN } iffifo_id_e; // Register width information to check illegal writes parameter logic [3:0] IFFIFO_PERMIT[2] = '{ - 4'b1111, // index[0] IFFIFO_DUMMYR - 4'b1111 // index[1] IFFIFO_DUMMYW + 4'b1111, // index[0] IFFIFO_FIFO_OUT + 4'b1111 // index[1] IFFIFO_FIFO_IN }; endpackage diff --git a/hw/ip_examples/iffifo/rtl/iffifo_reg_top.sv b/hw/ip_examples/iffifo/rtl/iffifo_reg_top.sv index 9cd8d44cd..7b7d33cb7 100644 --- a/hw/ip_examples/iffifo/rtl/iffifo_reg_top.sv +++ b/hw/ip_examples/iffifo/rtl/iffifo_reg_top.sv @@ -10,20 +10,15 @@ module iffifo_reg_top #( parameter type reg_req_t = logic, parameter type reg_rsp_t = logic, - parameter int AW = 4 + parameter int AW = 3 ) ( input logic clk_i, input logic rst_ni, input reg_req_t reg_req_i, output reg_rsp_t reg_rsp_o, - - // Output port for window - output reg_req_t [2-1:0] reg_req_win_o, - input reg_rsp_t [2-1:0] reg_rsp_win_i, - // To HW output iffifo_reg_pkg::iffifo_reg2hw_t reg2hw, // Write - input iffifo_reg_pkg::iffifo_hw2reg_t hw2reg, // Read + input iffifo_reg_pkg::iffifo_hw2reg_t hw2reg, // Read // Config @@ -53,48 +48,8 @@ module iffifo_reg_top #( reg_rsp_t reg_intf_rsp; - logic [1:0] reg_steer; - - reg_req_t [3-1:0] reg_intf_demux_req; - reg_rsp_t [3-1:0] reg_intf_demux_rsp; - - // demux connection - assign reg_intf_req = reg_intf_demux_req[2]; - assign reg_intf_demux_rsp[2] = reg_intf_rsp; - - assign reg_req_win_o[0] = reg_intf_demux_req[0]; - assign reg_intf_demux_rsp[0] = reg_rsp_win_i[0]; - assign reg_req_win_o[1] = reg_intf_demux_req[1]; - assign reg_intf_demux_rsp[1] = reg_rsp_win_i[1]; - - // Create Socket_1n - reg_demux #( - .NoPorts(3), - .req_t (reg_req_t), - .rsp_t (reg_rsp_t) - ) i_reg_demux ( - .clk_i, - .rst_ni, - .in_req_i(reg_req_i), - .in_rsp_o(reg_rsp_o), - .out_req_o(reg_intf_demux_req), - .out_rsp_i(reg_intf_demux_rsp), - .in_select_i(reg_steer) - ); - - - // Create steering logic - always_comb begin - reg_steer = 2; // Default set to register - - // TODO: Can below codes be unique case () inside ? - if (reg_req_i.addr[AW-1:0] >= 8 && reg_req_i.addr[AW-1:0] < 12) begin - reg_steer = 0; - end - if (reg_req_i.addr[AW-1:0] >= 12) begin - reg_steer = 1; - end - end + assign reg_intf_req = reg_req_i; + assign reg_rsp_o = reg_intf_rsp; assign reg_we = reg_intf_req.valid & reg_intf_req.write; @@ -113,62 +68,53 @@ module iffifo_reg_top #( // Define SW related signals // Format: __{wd|we|qs} // or _{wd|we|qs} if field == 1 or 0 - logic [31:0] dummyr_qs; - logic [31:0] dummyr_wd; - logic dummyr_we; - logic [31:0] dummyw_qs; + logic [31:0] fifo_out_qs; + logic fifo_out_re; + logic [31:0] fifo_in_qs; + logic [31:0] fifo_in_wd; + logic fifo_in_we; // Register instances - // R[dummyr]: V(False) + // R[fifo_out]: V(True) + + prim_subreg_ext #( + .DW(32) + ) u_fifo_out ( + .re (fifo_out_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.fifo_out.d), + .qre(reg2hw.fifo_out.re), + .qe (), + .q (reg2hw.fifo_out.q), + .qs (fifo_out_qs) + ); + + + // R[fifo_in]: V(False) prim_subreg #( .DW (32), .SWACCESS("RW"), .RESVAL (32'h0) - ) u_dummyr ( + ) u_fifo_in ( .clk_i (clk_i), .rst_ni(rst_ni), // from register interface - .we(dummyr_we), - .wd(dummyr_wd), + .we(fifo_in_we), + .wd(fifo_in_wd), // from internal hardware .de(1'b0), .d ('0), // to internal hardware - .qe(), - .q (reg2hw.dummyr.q), - - // to register interface (read) - .qs(dummyr_qs) - ); - - - // R[dummyw]: V(False) - - prim_subreg #( - .DW (32), - .SWACCESS("RO"), - .RESVAL (32'h0) - ) u_dummyw ( - .clk_i (clk_i), - .rst_ni(rst_ni), - - .we(1'b0), - .wd('0), - - // from internal hardware - .de(hw2reg.dummyw.de), - .d (hw2reg.dummyw.d), - - // to internal hardware - .qe(), - .q (reg2hw.dummyw.q), + .qe(reg2hw.fifo_in.qe), + .q (reg2hw.fifo_in.q), // to register interface (read) - .qs(dummyw_qs) + .qs(fifo_in_qs) ); @@ -177,8 +123,8 @@ module iffifo_reg_top #( logic [1:0] addr_hit; always_comb begin addr_hit = '0; - addr_hit[0] = (reg_addr == IFFIFO_DUMMYR_OFFSET); - addr_hit[1] = (reg_addr == IFFIFO_DUMMYW_OFFSET); + addr_hit[0] = (reg_addr == IFFIFO_FIFO_OUT_OFFSET); + addr_hit[1] = (reg_addr == IFFIFO_FIFO_IN_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0; @@ -190,19 +136,21 @@ module iffifo_reg_top #( (addr_hit[1] & (|(IFFIFO_PERMIT[1] & ~reg_be))))); end - assign dummyr_we = addr_hit[0] & reg_we & !reg_error; - assign dummyr_wd = reg_wdata[31:0]; + assign fifo_out_re = addr_hit[0] & reg_re & !reg_error; + + assign fifo_in_we = addr_hit[1] & reg_we & !reg_error; + assign fifo_in_wd = reg_wdata[31:0]; // Read data return always_comb begin reg_rdata_next = '0; unique case (1'b1) addr_hit[0]: begin - reg_rdata_next[31:0] = dummyr_qs; + reg_rdata_next[31:0] = fifo_out_qs; end addr_hit[1]: begin - reg_rdata_next[31:0] = dummyw_qs; + reg_rdata_next[31:0] = fifo_in_qs; end default: begin @@ -226,13 +174,12 @@ module iffifo_reg_top #( endmodule module iffifo_reg_top_intf #( - parameter int AW = 4, + parameter int AW = 3, localparam int DW = 32 ) ( input logic clk_i, input logic rst_ni, REG_BUS.in regbus_slave, - REG_BUS.out regbus_win_mst[2-1:0], // To HW output iffifo_reg_pkg::iffifo_reg2hw_t reg2hw, // Write input iffifo_reg_pkg::iffifo_hw2reg_t hw2reg, // Read @@ -257,13 +204,6 @@ module iffifo_reg_top_intf #( `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave) `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp) - reg_bus_req_t s_reg_win_req[2-1:0]; - reg_bus_rsp_t s_reg_win_rsp[2-1:0]; - for (genvar i = 0; i < 2; i++) begin : gen_assign_window_structs - `REG_BUS_ASSIGN_TO_REQ(s_reg_win_req[i], regbus_win_mst[i]) - `REG_BUS_ASSIGN_FROM_RSP(regbus_win_mst[i], s_reg_win_rsp[i]) - end - iffifo_reg_top #( @@ -275,8 +215,6 @@ module iffifo_reg_top_intf #( .rst_ni, .reg_req_i(s_reg_req), .reg_rsp_o(s_reg_rsp), - .reg_req_win_o(s_reg_win_req), - .reg_rsp_win_i(s_reg_win_rsp), .reg2hw, // Write .hw2reg, // Read .devmode_i diff --git a/hw/ip_examples/iffifo/rtl/iffifo_window.sv b/hw/ip_examples/iffifo/rtl/iffifo_window.sv deleted file mode 100644 index 22650dd84..000000000 --- a/hw/ip_examples/iffifo/rtl/iffifo_window.sv +++ /dev/null @@ -1,65 +0,0 @@ -// Copyright 2023 EPFL -// Solderpad Hardware License, Version 2.1, see LICENSE.md for details. -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Author: Pierre Guillod , EPFL, STI-SEL -// Date: 18.10.2023 -// -// Adapted from the SPI host IP, under the Apache-2.0 License, -// copyright lowRISC contributors. - -`include "common_cells/assertions.svh" - -module iffifo_window #( - parameter type reg_req_t = logic, - parameter type reg_rsp_t = logic -) ( - input reg_req_t rx_win_i, - output reg_rsp_t rx_win_o, - input reg_req_t tx_win_i, - output reg_rsp_t tx_win_o, - output logic [31:0] tx_data_o, - output logic [ 3:0] tx_be_o, - output logic tx_valid_o, - input [31:0] rx_data_i, - output logic rx_ready_o -); - - localparam int AW = iffifo_reg_pkg::BlockAw; - - logic [AW-1:0] tx_addr; - // Only support reads/writes to the data fifo window - logic tx_win_error; - assign tx_win_error = (tx_win_i.write == 1'b0) && - (tx_addr != iffifo_reg_pkg::IFFIFO_FIFO_IN_OFFSET); - - logic [AW-1:0] rx_addr; - // Only support reads/writes to the data fifo window - logic rx_win_error; - assign rx_win_error = (rx_win_i.write == 1'b1) && - (rx_addr != iffifo_reg_pkg::IFFIFO_FIFO_OUT_OFFSET); - - // Check that our regbus data is 32 bit wide - `ASSERT_INIT(RegbusTXIs32Bit, $bits(tx_win_i.wdata) == 32) - `ASSERT_INIT(RegbusRXIs32Bit, $bits(rx_win_i.wdata) == 32) - - // We are already a regbus, so no stateful adapter should be needed here - // TODO @(paulsc, zarubaf): check this assumption! - // Request - assign rx_ready_o = rx_win_i.valid & ~rx_win_i.write; // read-enable - assign rx_win_o.rdata = rx_data_i; - // Response: always ready, else over/underflow error reported in regfile - assign rx_win_o.error = rx_win_error; - assign rx_win_o.ready = 1'b1; - assign rx_addr = rx_win_i.addr; - - assign tx_valid_o = tx_win_i.valid & tx_win_i.write; // write-enable - assign tx_data_o = tx_win_i.wdata; - assign tx_be_o = tx_win_i.wstrb; - // Response: always ready, else over/underflow error reported in regfile - assign tx_win_o.error = tx_win_error; - assign tx_win_o.rdata = 32'h0; - assign tx_win_o.ready = 1'b1; - assign tx_addr = tx_win_i.addr; - -endmodule : iffifo_window diff --git a/hw/system/x_heep_system.sv.tpl b/hw/system/x_heep_system.sv.tpl index 60c78a3b8..c88bdacad 100644 --- a/hw/system/x_heep_system.sv.tpl +++ b/hw/system/x_heep_system.sv.tpl @@ -48,8 +48,8 @@ module x_heep_system output logic [31:0] exit_value_o, - input logic ext_dma_slot_0_i, - input logic ext_dma_slot_1_i, + input logic ext_dma_slot_tx_i, + input logic ext_dma_slot_rx_i, // eXtension interface if_xif.cpu_compressed xif_compressed_if, @@ -141,8 +141,8 @@ ${pad.core_v_mini_mcu_bonding} .external_ram_banks_set_retentive_no, .external_subsystem_clkgate_en_no, .exit_value_o, - .ext_dma_slot_0_i, - .ext_dma_slot_1_i + .ext_dma_slot_tx_i, + .ext_dma_slot_rx_i ); pad_ring pad_ring_i ( diff --git a/sw/applications/example_iffifo/main.c b/sw/applications/example_iffifo/main.c index 383ca32a0..e1fd6f973 100644 --- a/sw/applications/example_iffifo/main.c +++ b/sw/applications/example_iffifo/main.c @@ -47,7 +47,7 @@ int compare_print_fifo_array(void) { for (int i = 0; i < 3; i+=1) { PRINTF("%d",from_fifo[i]); if(i != 3-1) {PRINTF(", ");}; - if (to_fifo[i] != from_fifo[i]) {++errors;} + if (to_fifo[i]+1 != from_fifo[i]) {++errors;} } PRINTF("}\n"); return errors; diff --git a/sw/device/lib/drivers/iffifo/iffifo_regs.h b/sw/device/lib/drivers/iffifo/iffifo_regs.h index b1ea8b834..974a3bea7 100644 --- a/sw/device/lib/drivers/iffifo/iffifo_regs.h +++ b/sw/device/lib/drivers/iffifo/iffifo_regs.h @@ -16,20 +16,12 @@ extern "C" { // Register width #define IFFIFO_PARAM_REG_WIDTH 32 -// Does nothing. -#define IFFIFO_DUMMYR_REG_OFFSET 0x0 +// Data coming from the FIFO (Fifo Output/Software RX). +#define IFFIFO_FIFO_OUT_REG_OFFSET 0x0 -// Does nothing. -#define IFFIFO_DUMMYW_REG_OFFSET 0x4 +// Data sent to the FIFO (Fifo Input/Software TX). +#define IFFIFO_FIFO_IN_REG_OFFSET 0x4 -// Memory area: Data coming from the FIFO (Fifo Output/Software RX) -#define IFFIFO_FIFO_OUT_REG_OFFSET 0x8 -#define IFFIFO_FIFO_OUT_SIZE_WORDS 1 -#define IFFIFO_FIFO_OUT_SIZE_BYTES 4 -// Memory area: Data sent to the FIFO (Fifo Input/Software TX) -#define IFFIFO_FIFO_IN_REG_OFFSET 0xc -#define IFFIFO_FIFO_IN_SIZE_WORDS 1 -#define IFFIFO_FIFO_IN_SIZE_BYTES 4 #ifdef __cplusplus } // extern "C" #endif diff --git a/tb/testharness.sv b/tb/testharness.sv index 96927d3e4..79585431a 100644 --- a/tb/testharness.sv +++ b/tb/testharness.sv @@ -252,8 +252,8 @@ module testharness #( .external_subsystem_rst_no(external_subsystem_rst_n), .external_ram_banks_set_retentive_no(external_ram_banks_set_retentive_n), .external_subsystem_clkgate_en_no(external_subsystem_clkgate_en_n), - .ext_dma_slot_0_i(iffifo_in_ready), - .ext_dma_slot_1_i(iffifo_out_valid) + .ext_dma_slot_tx_i(iffifo_in_ready), + .ext_dma_slot_rx_i(iffifo_out_valid) ); // Testbench external bus