Use the section names like namespaces

[tsvi]

I have an issue though with the way it (doesn't) analyze namespaces. In my Systemverilog code, I have 2 packages that have a class named driver. Moreover as they both inherit from uvm_driver, they hold the same functions: build_phase, connect_phase.

At first I gave the section names the same hierarchy as the code namespace. So I had
my_project/event_package
my_project/host_package
event_package/driver
host_package/driver

But this caused some confusion when building the TOC, as event_package/driver held driver/constraint_x but in the TOC, it would be under host_package/driver.

So I renamed the sections which is a shame, but I devided as long as the section NAME would hold the actual name of the class this would be OK.

So now, none of the code/comments hyperlinks driver which I can live with. But some of the code obviously references the functions and again I have the same issue: Both calls to build_phase hyperlinks to the same class. Although they should reference separate classes.