diff --git a/content/items/peakrdl.md b/content/items/peakrdl.md new file mode 100644 index 00000000..baad2758 --- /dev/null +++ b/content/items/peakrdl.md @@ -0,0 +1,51 @@ +--- +title: "PeakRDL" +description: "Control & Status register (CSR) automation toolchain" +authors: + - Alex Mykyta +links: + gh: "SystemRDL/PeakRDL" + docs: "https://peakrdl.readthedocs.io" +tags: + - SystemRDL + - code-generator + - Python + - configuration-register + - csr + - verilog + - systemverilog + - documentation + - UVM-reg + - RTL + - abstract +categories: + - "Tools:CSR Automation" +licenses: + - GPL-3.0 +active: + from: 2018 +talk: 241 +--- + +PeakRDL is a free and open-source control & status register (CSR) automation +toolchain. This project provides a command-line tool that unifies many aspects of register automation centered around the SystemRDL register description language. + +This tool can: + +* Process SystemRDL 2.0 register descriptions. +* Import & export IP-XACT XML. +* Generate synthesizable SystemVerilog RTL register blocks using APB, AXI4-Lite, Avalon, and other interfaces. +* Create rich and dynamic HTML documentation. +* Build a UVM register model abstraction layer. +* Generate C headers for software. +* ... or be extended with your own plugin to generate other outputs + +## References + +- [SystemRDL Compiler]({{< ref "/items/systemrdl-compiler" >}} "SystemRDL Compiler") +- [PeakRDL-cheader](https://github.com/SystemRDL/PeakRDL-cheader) +- [PeakRDL-html](https://github.com/SystemRDL/PeakRDL-html) +- [PeakRDL-ipxact](https://github.com/SystemRDL/PeakRDL-ipxact) +- [PeakRDL-regblock](https://github.com/SystemRDL/PeakRDL-regblock) +- [PeakRDL-systemrdl](https://github.com/SystemRDL/PeakRDL-systemrdl) +- [PeakRDL-uvm](https://github.com/SystemRDL/PeakRDL-uvm) diff --git a/content/items/systemrdl-compiler.md b/content/items/systemrdl-compiler.md new file mode 100644 index 00000000..4fd933a6 --- /dev/null +++ b/content/items/systemrdl-compiler.md @@ -0,0 +1,38 @@ +--- +title: "SystemRDL Compiler" +description: "SystemRDL language compiler front-end" +authors: + - Alex Mykyta +links: + gh: "SystemRDL/systemrdl-compiler" + docs: "https://systemrdl-compiler.readthedocs.io" +tags: + - SystemRDL + - language-model + - parser + - compiler + - code-generator + - Python + - configuration-register + - csr +categories: + - "Tools:CSR Automation" +licenses: + - MIT +active: + from: 2017 +talk: 241 +--- + +SystemRDL is a domain specific language used to describe control/status +registers (CSR) that define a hardware/software boundary for hardware +peripherals. By describing the structure of a CSR in SystemRDL, one can create a single source of truth specification for CSR automation and code generation. + +The `systemrdl-compiler` project implements a generic compiler front-end for +Accellera's [SystemRDL 2.0](http://accellera.org/downloads/standards/systemrdl) +register description language. The goal of this project is to provide a free and +open compiler that lowers the barrier to entry to using an industry standard +register description language. + +By providing an elaborated register model that is easy to traverse and query, +it should be far easier to write custom register space view generators. diff --git a/static/logos/peakrdl.png b/static/logos/peakrdl.png new file mode 100644 index 00000000..05dc5037 Binary files /dev/null and b/static/logos/peakrdl.png differ diff --git a/static/logos/systemrdl-compiler.png b/static/logos/systemrdl-compiler.png new file mode 100644 index 00000000..05dc5037 Binary files /dev/null and b/static/logos/systemrdl-compiler.png differ