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Add support for manual_override of standard cells.
Lint #511: Commit 2ce5bd0 pushed by QuantamHD
September 18, 2023 19:52 18s main
September 18, 2023 19:52 18s
Adding structured stat output.
Lint #510: Commit c27e11f pushed by QuantamHD
September 18, 2023 19:51 16s main
September 18, 2023 19:51 16s
Improve control over pin placement.
Lint #509: Pull request #192 opened by mithro
September 18, 2023 19:39 13s mithro:improve-pin-placement
September 18, 2023 19:39 13s
Adding autoname and opt_clean -purge Yosys pass to synth.tcl
Lint #508: Commit 21e294b pushed by QuantamHD
September 18, 2023 19:36 15s main
September 18, 2023 19:36 15s
Adding support for synth.tcl to read SystemVerilog files using Surelog.
Lint #507: Pull request #191 synchronize by mithro
September 18, 2023 19:23 15s mithro:surelog
September 18, 2023 19:23 15s
Export def during place and route.
Lint #505: Pull request #190 opened by mithro
September 18, 2023 19:08 12s mithro:export-def
September 18, 2023 19:08 12s
Add support for manual_override of standard cells.
Lint #504: Pull request #189 opened by mithro
September 18, 2023 19:00 13s mithro:manual_override
September 18, 2023 19:00 13s
Give don't use cells to Yosys.
Lint #503: Pull request #188 opened by mithro
September 18, 2023 18:50 18s mithro:dont-use-args
September 18, 2023 18:50 18s
Adding structured stat output.
Lint #502: Pull request #187 opened by mithro
September 18, 2023 18:44 19s mithro:yosys-struct-stats
September 18, 2023 18:44 19s
Fix spelling mistake in report_power.bzl.
Lint #501: Pull request #186 opened by mithro
September 18, 2023 18:36 17s mithro:spelling-fix
September 18, 2023 18:36 17s
dependency_support/com_icarus_iverilog: bump version
Lint #500: Pull request #184 opened by proppy
September 14, 2023 18:28 13s proppy:bump-iverilog
September 14, 2023 18:28 13s
Adding autoname and opt_clean -purge Yosys pass to synth.tcl
Lint #499: Pull request #183 opened by mithro
September 13, 2023 00:43 15s mithro:autoname
September 13, 2023 00:43 15s