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Merge pull request #339 from hdl/autoname_fix
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Fixes out of memory error with larger RTL blocks
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QuantamHD authored Jul 25, 2024
2 parents 72906cc + 60b5cda commit 649d03e
Showing 1 changed file with 0 additions and 3 deletions.
3 changes: 0 additions & 3 deletions synthesis/synth.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -61,7 +61,6 @@ yosys delete {*/t:$print}
# useful names. At this stage it is mainly flipflops created by the `proc`
# pass.
yosys opt_clean -purge
yosys autoname

yosys synth -top $top

Expand All @@ -70,7 +69,6 @@ yosys synth -top $top
# This should be done before techmapping where things can be converted
# dramatically and having useful names is helpful for debugging.
yosys opt_clean -purge
yosys autoname

# Technology mapping of adders
if {[info exists ::env(ADDER_MAPPING)] && [file isfile $::env(ADDER_MAPPING)]} {
Expand Down Expand Up @@ -115,7 +113,6 @@ if {[info exists ::env(TIEHI_CELL_AND_PORT)] && [info exists ::env(TIELO_CELL_AN
# useful names. At this stage it is anything generated by the techmapping
# passes.
yosys opt_clean -purge
yosys autoname

# write synthesized design
set output $::env(OUTPUT)
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