From 7eca73f8208563a66874c7fb1232f4027caa51e4 Mon Sep 17 00:00:00 2001 From: Tim Ansell Date: Mon, 27 Nov 2023 15:46:45 -0800 Subject: [PATCH] Add multiple corners. Add targets for fast, typical and slow corners (currently only support CCS model, but should be very easy to extend to NLDM in the future). Signed-off-by: Tim Ansell --- .../asap7.bzl | 41 ++++++- .../bundled.BUILD.bazel | 8 ++ .../common.bzl | 8 ++ flows/asap7.bzl | 112 +++++++++--------- 4 files changed, 114 insertions(+), 55 deletions(-) diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.bzl b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.bzl index e9480145..d69020f1 100644 --- a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.bzl +++ b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.bzl @@ -139,8 +139,15 @@ def asap7_cells_files(name = None, rev = None, tracks = None, vt = None, has_gds # Library configuration # ------------------------------------------------------------------------ - asap7_cell_library( + # Default library is slow-slow corner using CCS + native.alias( name = "asap7-sc{tracks}_rev{rev}_{vt_long}".format(**args), + actual = ":asap7-sc{tracks}_rev{rev}_{vt_long}-ccs_ss".format(**args), + + ) + # CCS delay model + asap7_cell_library( + name = "asap7-sc{tracks}_rev{rev}_{vt_long}-ccs_ss".format(**args), srcs = [ ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lib7z".format(**args), #":asap7-srams-sc{tracks}_rev{rev}-lib7z".format(**args), @@ -155,6 +162,38 @@ def asap7_cells_files(name = None, rev = None, tracks = None, vt = None, has_gds "//visibility:public", ], ) + asap7_cell_library( + name = "asap7-sc{tracks}_rev{rev}_{vt_long}-ccs_tt".format(**args), + srcs = [ + ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lib7z".format(**args), + #":asap7-srams-sc{tracks}_rev{rev}-lib7z".format(**args), + ], + cell_lef = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lef".format(**args), + platform_gds = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-gds".format(**args), + default_corner_delay_model = "ccs", + default_corner_swing = "TT", + openroad_configuration = ":open_road-asap7-sc{tracks}_rev{rev}_{vt_long}".format(**args), + tech_lef = ":asap7-misc-sc{tracks}_rev{rev}-lef".format(**args), + visibility = [ + "//visibility:public", + ], + ) + asap7_cell_library( + name = "asap7-sc{tracks}_rev{rev}_{vt_long}-ccs_ff".format(**args), + srcs = [ + ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lib7z".format(**args), + #":asap7-srams-sc{tracks}_rev{rev}-lib7z".format(**args), + ], + cell_lef = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lef".format(**args), + platform_gds = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-gds".format(**args), + default_corner_delay_model = "ccs", + default_corner_swing = "FF", + openroad_configuration = ":open_road-asap7-sc{tracks}_rev{rev}_{vt_long}".format(**args), + tech_lef = ":asap7-misc-sc{tracks}_rev{rev}-lef".format(**args), + visibility = [ + "//visibility:public", + ], + ) def _asap7_cell_library_impl(ctx): liberty_files = [file for file in ctx.files.srcs if file.extension == "7z"] diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel index 9a2ade9c..3042f6f3 100644 --- a/dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel @@ -241,3 +241,11 @@ filegroup( name = "asap7-misc-sc7p5t_rev28_4x-lef", srcs = ["techlef_misc/asap7_tech_4x_201209.lef"], ) + +# Default rev28 cell library is the RVT library using slow-slow corner with CCS +# modeling. +alias( + name = "asap7-cells-sc7p5t_rev28", + actual = ":asap7-cells-sc7p5t_rev28_rvt-ccs_ss", +) + diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_28/common.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/common.bzl index 5cb41ea0..1c14f472 100644 --- a/dependency_support/org_theopenroadproject_asap7sc7p5t_28/common.bzl +++ b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/common.bzl @@ -32,3 +32,11 @@ filegroup( name = "asap7-misc-sc7p5t_rev28_4x-lef", srcs = ["techlef_misc/asap7_tech_4x_201209.lef"], ) + +# Default rev28 cell library is the RVT library using slow-slow corner with CCS +# modeling. +alias( + name = "asap7-cells-sc7p5t_rev28", + actual = ":asap7-cells-sc7p5t_rev28_rvt-ccs_ss", +) + diff --git a/flows/asap7.bzl b/flows/asap7.bzl index bfedcb67..bed81311 100644 --- a/flows/asap7.bzl +++ b/flows/asap7.bzl @@ -20,7 +20,7 @@ load("//place_and_route:build_defs.bzl", "place_and_route") load("//static_timing:build_defs.bzl", "run_opensta") load("//synthesis:build_defs.bzl", "synthesize_rtl") -def asap7_targets(name, target, rev, tracks, vt, has_gds = True, size = 20): +def asap7_targets(name, target, rev, tracks, vt, has_gds = True, size = 20, corners = ('ccs_ss', 'ccs_tt', 'ccs_ff')): """Generate targets for a quick basic ASAP7 flow. Args: @@ -31,70 +31,74 @@ def asap7_targets(name, target, rev, tracks, vt, has_gds = True, size = 20): vt: VT type ("rvt", "lvt", "slvt"). has_gds: Cells have GDS layouts. size: Size of the die in microns. + corners: List of corners to generate rules for (default is `ccs_ss`, `ccs_tt`, `ccs_ff`). """ if rev not in [26, 27, 28]: fail("Invalid rev {}".format(repr(rev))) if tracks not in ["7p5t", "6t"]: fail("Invalid rev {}".format(repr(tracks))) - a = { - "name": target, - "tracks": tracks, - "rev": rev, - "vt": vt, - } + # TODO: Add the NLDM support once it works with OpenROAD. + for corner in corners: + a = { + "name": target, + "tracks": tracks, + "rev": rev, + "vt": vt, + "corn": corner, + } - synthesize_rtl( - name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth".format(**a), - standard_cells = "@org_theopenroadproject_asap7sc{tracks}_{rev}//:asap7-sc{tracks}_rev{rev}_{vt}".format(**a), - target_clock_period_pico_seconds = 10000, - top_module = "counter", - deps = [ - ":{name}".format(**a), - ], - ) - build_test( - name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth".format(**a), - targets = [ - ":{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth".format(**a), - ], - ) - - run_opensta( - name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth_sta".format(**a), - synth_target = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth".format(**a), - ) - build_test( - name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth_sta".format(**a), - targets = [ - ":{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth".format(**a), - ], - ) + synthesize_rtl( + name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a), + standard_cells = "@org_theopenroadproject_asap7sc{tracks}_{rev}//:asap7-sc{tracks}_rev{rev}_{vt}-{corn}".format(**a), + target_clock_period_pico_seconds = 10000, + top_module = "counter", + deps = [ + ":{name}".format(**a), + ], + ) + build_test( + name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a), + targets = [ + ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a), + ], + ) - place_and_route( - name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}-place_and_route".format(**a), - core_padding_microns = 1, - die_height_microns = size, - die_width_microns = size, - placement_density = "0.65", - sdc = "constraint.sdc", - synthesized_rtl = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth".format(**a), - ) - build_test( - name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}-place_and_route".format(**a), - targets = [ - ":{name}-asap7-sc{tracks}_rev{rev}_{vt}-place_and_route".format(**a), - ], - ) + run_opensta( + name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth_sta".format(**a), + synth_target = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a), + ) + build_test( + name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth_sta".format(**a), + targets = [ + ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a), + ], + ) - if has_gds: - gds_write( - name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}-gds".format(**a), - implemented_rtl = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}-place_and_route".format(**a), + place_and_route( + name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-place_and_route".format(**a), + core_padding_microns = 1, + die_height_microns = size, + die_width_microns = size, + placement_density = "0.65", + sdc = "constraint.sdc", + synthesized_rtl = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a), ) build_test( - name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}-gds".format(**a), + name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-place_and_route".format(**a), targets = [ - ":{name}-asap7-sc{tracks}_rev{rev}_{vt}-gds".format(**a), + ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-place_and_route".format(**a), ], ) + + if has_gds: + gds_write( + name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-gds".format(**a), + implemented_rtl = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-place_and_route".format(**a), + ) + build_test( + name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-gds".format(**a), + targets = [ + ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-gds".format(**a), + ], + )