synthesis: tests: counter: enable ASAP7 physical design sample

Signed-off-by: Pawel Czarnecki <[email protected]>
hdl · Sep 7, 2023 · 7fd311e · 7fd311e
1 parent 7052778
commit 7fd311e
Show file tree

Hide file tree

Showing 2 changed files with 32 additions and 0 deletions.
diff --git a/synthesis/tests/BUILD b/synthesis/tests/BUILD
@@ -66,9 +66,25 @@ run_opensta(
     synth_target = ":verilog_counter_asap7_synth",
 )
 
+gds_write(
+    name = "counter_asap7_asic",
+    implemented_rtl = ":counter_asap7_place_and_route",
+)
+
+place_and_route(
+    name = "counter_asap7_place_and_route",
+    core_padding_microns = 1,
+    die_height_microns = 20,
+    die_width_microns = 20,
+    placement_density = "0.65",
+    sdc = "constraint.sdc",
+    synthesized_rtl = ":verilog_counter_asap7_synth",
+)
+
 synthesize_rtl(
     name = "verilog_counter_asap7_synth",
     standard_cells = "@org_theopenroadproject_asap7//:asap7_rvt_1x",
+    target_clock_period_pico_seconds = 10000,
     top_module = "counter",
     deps = [
         ":verilog_counter",

diff --git a/synthesis/tests/constraint.sdc b/synthesis/tests/constraint.sdc
@@ -0,0 +1,16 @@
+current_design counter
+
+set clk_name  core_clock
+set clk_port_name clk
+set clk_period 10000
+set clk_io_pct 0.2
+
+set clk_port [get_ports $clk_port_name]
+
+create_clock -name $clk_name -period $clk_period  $clk_port
+
+set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+
+set_input_delay  [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
+set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
+