From 1c77601bd51aa16906a26e248cce7751914b4f5e Mon Sep 17 00:00:00 2001 From: Josh Varga Date: Fri, 23 Aug 2024 17:22:21 +0000 Subject: [PATCH 1/4] Adds ability to set verilog defines on the synthesize_rtl rule --- synthesis/build_defs.bzl | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/synthesis/build_defs.bzl b/synthesis/build_defs.bzl index 8581eea5..3c1d5432 100644 --- a/synthesis/build_defs.bzl +++ b/synthesis/build_defs.bzl @@ -137,6 +137,9 @@ def _synthesize_design_impl(ctx): for dont_use_pattern in or_config.do_not_use_cell_list: dont_use_args += " -dont_use {} ".format(dont_use_pattern) + if ctx.attr.verilog_defines: + for define in ctx.attr.verilog_defines: + args.add(define) script_env_files = { "ABC_SCRIPT": abc_script, "ADDITIONAL_LIBERTIES": additional_liberty_files, @@ -343,6 +346,9 @@ synthesize_rtl = rule( "top_module": attr.string( default = "top", ), + "verilog_defines": attr.string_list( + doc = "Verilog defines to pass to the synthesis tool.", + ), "yosys_tool": attr.label( default = Label("@at_clifford_yosys//:yosys"), executable = True, From e899a3e3750633aa7ce8ba669daca7017fd73148 Mon Sep 17 00:00:00 2001 From: Ethan Mahintorabi Date: Fri, 23 Aug 2024 18:40:54 +0000 Subject: [PATCH 2/4] Allows liberty cells to be manually instantiated in a netlist Signed-off-by: Ethan Mahintorabi --- synthesis/build_defs.bzl | 3 +++ synthesis/synth.tcl | 10 ++++++++++ 2 files changed, 13 insertions(+) diff --git a/synthesis/build_defs.bzl b/synthesis/build_defs.bzl index 3c1d5432..add02d6b 100644 --- a/synthesis/build_defs.bzl +++ b/synthesis/build_defs.bzl @@ -140,6 +140,8 @@ def _synthesize_design_impl(ctx): if ctx.attr.verilog_defines: for define in ctx.attr.verilog_defines: args.add(define) + + standard_cell_black_box = ctx.actions.declare_file("{}_stdcells_blackbox.v".format(ctx.attr.name)) script_env_files = { "ABC_SCRIPT": abc_script, "ADDITIONAL_LIBERTIES": additional_liberty_files, @@ -150,6 +152,7 @@ def _synthesize_design_impl(ctx): "OUTPUT": output_file, "TOP": ctx.attr.top_module, "UHDM_FLIST": uhdm_flist, + "STANDARD_CELL_BLACK_BOX": standard_cell_black_box, } if ctx.attr.target_clock_period_pico_seconds: diff --git a/synthesis/synth.tcl b/synthesis/synth.tcl index d41a10c9..7bf3e142 100644 --- a/synthesis/synth.tcl +++ b/synthesis/synth.tcl @@ -12,6 +12,16 @@ yosys -import +set all_liberties [split $::env(ADDITIONAL_LIBERTIES) ","] +lappend all_liberties $::env(LIBERTY) + +# create liberty blackbox so cells can be manually created. +foreach lib $all_liberties { + read_liberty -lib -overwrite $lib +} + +write_verilog -blackboxes $::env(STANDARD_CELL_BLACK_BOX) + # read design set srcs_flist_path $::env(FLIST) set srcs_flist_file [open $srcs_flist_path "r"] From 778ef2d3e70cd31959aa2d49978d4f72b3036aae Mon Sep 17 00:00:00 2001 From: Ethan Mahintorabi Date: Fri, 23 Aug 2024 18:44:13 +0000 Subject: [PATCH 3/4] lint fix Signed-off-by: Ethan Mahintorabi --- synthesis/build_defs.bzl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/synthesis/build_defs.bzl b/synthesis/build_defs.bzl index add02d6b..ace3522c 100644 --- a/synthesis/build_defs.bzl +++ b/synthesis/build_defs.bzl @@ -150,9 +150,9 @@ def _synthesize_design_impl(ctx): "FLIST": verilog_flist, "LIBERTY": default_liberty_file, "OUTPUT": output_file, + "STANDARD_CELL_BLACK_BOX": standard_cell_black_box, "TOP": ctx.attr.top_module, "UHDM_FLIST": uhdm_flist, - "STANDARD_CELL_BLACK_BOX": standard_cell_black_box, } if ctx.attr.target_clock_period_pico_seconds: From 1411c9975abd99345c14af9230f4614f4110624b Mon Sep 17 00:00:00 2001 From: Ethan Mahintorabi Date: Fri, 23 Aug 2024 19:11:25 +0000 Subject: [PATCH 4/4] fixes copy and paste typos Signed-off-by: Ethan Mahintorabi --- synthesis/build_defs.bzl | 2 +- synthesis/synth.tcl | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/synthesis/build_defs.bzl b/synthesis/build_defs.bzl index ace3522c..1305c3ee 100644 --- a/synthesis/build_defs.bzl +++ b/synthesis/build_defs.bzl @@ -184,7 +184,7 @@ def _synthesize_design_impl(ctx): env[k] = v ctx.actions.run( - outputs = [output_file, log_file], + outputs = [output_file, log_file, standard_cell_black_box], inputs = inputs, arguments = [args], executable = ctx.executable.yosys_tool, diff --git a/synthesis/synth.tcl b/synthesis/synth.tcl index 7bf3e142..54463121 100644 --- a/synthesis/synth.tcl +++ b/synthesis/synth.tcl @@ -27,6 +27,7 @@ set srcs_flist_path $::env(FLIST) set srcs_flist_file [open $srcs_flist_path "r"] set srcs_flist_data [read $srcs_flist_file] set srcs [split $srcs_flist_data "\n"] +set srcs [linsert $srcs 0 $::env(STANDARD_CELL_BLACK_BOX)] puts $srcs foreach src $srcs { # Skip empty lines, including the implict one after the last \n delimiter