From 854829347c46baa689e78ee22f9914ca70f34def Mon Sep 17 00:00:00 2001 From: Ethan Mahintorabi Date: Sat, 2 Nov 2024 16:13:20 +0000 Subject: [PATCH] reformat bzl Signed-off-by: Ethan Mahintorabi --- synthesis/build_defs.bzl | 2 +- verilog/defs.bzl | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/synthesis/build_defs.bzl b/synthesis/build_defs.bzl index d1dbde21..f20b427e 100644 --- a/synthesis/build_defs.bzl +++ b/synthesis/build_defs.bzl @@ -221,7 +221,7 @@ def _synthesize_design_impl(ctx): data = [], deps = [], tags = [], - )] + )], ), ] diff --git a/verilog/defs.bzl b/verilog/defs.bzl index 82f43cf1..07b9d342 100644 --- a/verilog/defs.bzl +++ b/verilog/defs.bzl @@ -3,12 +3,12 @@ load( ":providers.bzl", _VerilogInfo = "VerilogInfo", - _verilog_library = "verilog_library", _make_dag_entry = "make_dag_entry", _make_verilog_info = "make_verilog_info", + _verilog_library = "verilog_library", ) VerilogInfo = _VerilogInfo verilog_library = _verilog_library make_dag_entry = _make_dag_entry -make_verilog_info = _make_verilog_info \ No newline at end of file +make_verilog_info = _make_verilog_info