diff --git a/dependency_support/org_theopenroadproject_asap7/asap7sc6t_rev26.bzl b/dependency_support/org_theopenroadproject_asap7/asap7sc6t_rev26.bzl new file mode 100644 index 00000000..bf02e6b9 --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7/asap7sc6t_rev26.bzl @@ -0,0 +1,264 @@ +# Copyright 2022 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" ASAP7 "rev 26" 6 track standard cell library (with SRAM blocks). """ + +# Layouts for GDS generation +# ------------------------------------------------------------------------ + +# Standard cells +filegroup( + name = "gds_cells_rvt", + srcs = ["asap7sc6t_26/GDS/asap7sc6t_26_R.gds"], + visibility = [":data_visibility"], +) + +filegroup( + name = "gds_cells_lvt", + srcs = ["asap7sc6t_26/GDS/asap7sc6t_26_L.gds"], + visibility = [":data_visibility"], +) + +filegroup( + name = "gds_cells_slvt", + srcs = ["asap7sc6t_26/GDS/asap7sc6t_26_SL.gds"], + visibility = [":data_visibility"], +) + +# SRAM +filegroup( + name = "gds_sram", + srcs = ["asap7sc6t_26/GDS/asap7sc6t_26_SRAM.gds"], + visibility = [":data_visibility"], +) + +# Timing information (in compressed Liberty format) for synthesis and static +# timing analysis (STA). +# ------------------------------------------------------------------------ + +# Standard cells +filegroup( + name = "libgz_cells_rvt", + srcs = glob(["asap7sc6t_26/LIB/CCS/*RVT*.lib.gz"]), + visibility = [":data_visibility"], +) + +filegroup( + name = "libgz_cells_lvt", + srcs = glob(["asap7sc6t_26/LIB/CCS/*LVT*.lib.gz"]), + visibility = [":data_visibility"], +) + +filegroup( + name = "libgz_cells_slvt", + srcs = glob(["asap7sc6t_26/LIB/CCS/*SLVT*.lib.gz"]), + visibility = [":data_visibility"], +) + +# SRAM +filegroup( + name = "libgz_sram", + srcs = glob(["asap7sc6t_26/LIB/CCS/*SRAM*.lib.gz"]), + visibility = [":data_visibility"], +) + +# FIXME: What about NLDM liberty? + +# Verilog models for digital simulation and logical equivalence +# ------------------------------------------------------------------------ + +# Standard cells +filegroup( + name = "v_cells_rvt", + srcs = [ + "asap7sc6t_26/Verilog/asap7sc7p5t_CKINVDC_RVT_TT_210930.v", + "asap7sc6t_26/Verilog/asap7sc7p5t_AO_RVT_TT_210930.v", + "asap7sc6t_26/Verilog/asap7sc7p5t_INVBUF_RVT_TT_210930.v", + "asap7sc6t_26/Verilog/asap7sc7p5t_OA_RVT_TT_210930.v", + "asap7sc6t_26/Verilog/asap7sc7p5t_SEQ_RVT_TT_210930.v", + "asap7sc6t_26/Verilog/asap7sc7p5t_SIMPLE_RVT_TT_210930.v", + ], + visibility = [":data_visibility"], +) + +filegroup( + name = "v_cells_lvt", + srcs = [ + "asap7sc6t_26/Verilog/asap7sc7p5t_CKINVDC_LVT_TT_210930.v", + "asap7sc6t_26/Verilog/asap7sc7p5t_AO_LVT_TT_210930.v", + "asap7sc6t_26/Verilog/asap7sc7p5t_INVBUF_LVT_TT_210930.v", + "asap7sc6t_26/Verilog/asap7sc7p5t_OA_LVT_TT_210930.v", + "asap7sc6t_26/Verilog/asap7sc7p5t_SEQ_LVT_TT_210930.v", + "asap7sc6t_26/Verilog/asap7sc7p5t_SIMPLE_LVT_TT_210930.v", + ], + visibility = [":data_visibility"], +) + +filegroup( + name = "v_cells_slvt", + srcs = [ + "asap7sc6t_26/Verilog/asap7sc7p5t_CKINVDC_SLVT_TT_210930.v", + "asap7sc6t_26/Verilog/asap7sc7p5t_AO_SLVT_TT_210930.v", + "asap7sc6t_26/Verilog/asap7sc7p5t_INVBUF_SLVT_TT_210930.v", + "asap7sc6t_26/Verilog/asap7sc7p5t_OA_SLVT_TT_210930.v", + "asap7sc6t_26/Verilog/asap7sc7p5t_SEQ_SLVT_TT_210930.v", + "asap7sc6t_26/Verilog/asap7sc7p5t_SIMPLE_SLVT_TT_210930.v", + ], + visibility = [":data_visibility"], +) + +# SRAM +filegroup( + name = "v_sram", + srcs = [ + "asap7sc6t_26/Verilog/asap7sc7p5t_CKINVDC_SRAM_TT_210930.v", + "asap7sc6t_26/Verilog/asap7sc7p5t_AO_SRAM_TT_210930.v", + "asap7sc6t_26/Verilog/asap7sc7p5t_INVBUF_SRAM_TT_210930.v", + "asap7sc6t_26/Verilog/asap7sc7p5t_OA_SRAM_TT_210930.v", + "asap7sc6t_26/Verilog/asap7sc7p5t_SEQ_SRAM_TT_210930.v", + "asap7sc6t_26/Verilog/asap7sc7p5t_SIMPLE_SRAM_TT_210930.v", + ], + visibility = [":data_visibility"], +) + +# CDL models for LVS checking +# ------------------------------------------------------------------------ + +# Standard cells +filegroup( + name = "lvs_cells_rvt", + srcs = ["asap7sc6t_26/CDL/LVS/asap7sc6t_26_R.cdl"], + visibility = [":data_visibility"], +) + +filegroup( + name = "lvs_cells_lvt", + srcs = ["asap7sc6t_26/CDL/LVS/asap7sc6t_26_L.cdl"], + visibility = [":data_visibility"], +) + +filegroup( + name = "lvs_cells_slvt", + srcs = ["asap7sc6t_26/CDL/LVS/asap7sc6t_26_SL.cdl"], + visibility = [":data_visibility"], +) + +# SRAM +filegroup( + name = "lvs_sram", + srcs = ["asap7sc6t_26/CDL/LVS/asap7sc6t_26_SRAM.cdl"], + visibility = [":data_visibility"], +) + +# CDL models for Spice simulation +# ------------------------------------------------------------------------ + +# Standard cells +filegroup( + name = "spice_cells_rvt", + srcs = ["asap7sc6t_26/CDL/xAct3D_extracted/asap7sc6t_26_L_211010.sp"], + visibility = [":data_visibility"], +) + +filegroup( + name = "spice_cells_lvt", + srcs = ["asap7sc6t_26/CDL/xAct3D_extracted/asap7sc6t_26_R_211010.sp"], + visibility = [":data_visibility"], +) + +filegroup( + name = "spice_cells_slvt", + srcs = ["asap7sc6t_26/CDL/xAct3D_extracted/asap7sc6t_26_SL_211010.sp"], + visibility = [":data_visibility"], +) + +# SRAM +filegroup( + name = "spice_sram", + srcs = ["asap7sc6t_26/CDL/xAct3D_extracted/asap7sc6t_26_SRAM_211010.sp"], + visibility = [":data_visibility"], +) + +# Place and route +# ------------------------------------------------------------------------ + +# Standard cells +filegroup( + name = "lef_cells_rvt", + srcs = ["asap7sc6t_26/LEF/asap7sc6t_26_R_1x_210923b.lef"], + visibility = [":data_visibility"], +) + +filegroup( + name = "lef_cells_lvt", + srcs = ["asap7sc6t_26/LEF/asap7sc6t_26_L_1x_210923b.lef"], + visibility = [":data_visibility"], +) + +filegroup( + name = "lef_cells_slvt", + srcs = ["asap7sc6t_26/LEF/asap7sc6t_26_SL_1x_210923b.lef"], + visibility = [":data_visibility"], +) + +# SRAM +filegroup( + name = "lef_sram", + srcs = ["asap7sc6t_26/LEF/asap7sc6t_26_SRAM_1x_210923b.lef"], + visibility = [":data_visibility"], +) + +# Misc cells +# FIXME: Where is the 1x techlef? +#filegroup( +# name = "lef_tech", +# srcs = ["asap7sc6t_26/techlef_misc/asap7_tech_1x_201209.lef"], +# visibility = [":data_visibility"], +#) + +# Alternative cells scaled up to 4x their original size. +# -------------------------------------------------------------------- + +# Standard cells +filegroup( + name = "lef_cells_4x_rvt", + srcs = ["asap7sc6t_26/LEF/scaled/asap7sc6t_26_R_4x_210923b.lef"], + visibility = [":data_visibility"], +) + +filegroup( + name = "lef_cells_4x_lvt", + srcs = ["asap7sc6t_26/LEF/scaled/asap7sc6t_26_L_4x_210923b.lef"], + visibility = [":data_visibility"], +) + +filegroup( + name = "lef_cells_4x_slvt", + srcs = ["asap7sc6t_26/LEF/scaled/asap7sc6t_26_SL_4x_210923b.lef"], + visibility = [":data_visibility"], +) + +# SRAM +filegroup( + name = "lef_sram_4x", + srcs = ["asap7sc6t_26/LEF/scaled/asap7sc6t_26_SRAM_4x_210923b.lef"], + visibility = [":data_visibility"], +) + +# Misc cell layouts for place and route +filegroup( + name = "lef_tech_4x", + srcs = ["asap7sc6t_26/techlef_misc/asap7_tech_4x_201209.lef"], + visibility = [":data_visibility"], +) diff --git a/dependency_support/org_theopenroadproject_asap7/asap7sc7p5t_rev27.bzl b/dependency_support/org_theopenroadproject_asap7/asap7sc7p5t_rev27.bzl new file mode 100644 index 00000000..7b8ac4c5 --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7/asap7sc7p5t_rev27.bzl @@ -0,0 +1,239 @@ +# Copyright 2022 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" ASAP7 "rev 27" 7.5 track standard cell library with SRAM blocks. """ + +# Layouts for GDS generation +# ------------------------------------------------------------------------ + +# Standard cells +filegroup( + name = "gds_cells_rvt", + srcs = ["asap7sc7p5t_27/GDS/asap7sc7p5t_27_R_201211.gds"], + visibility = [":data_visibility"], +) + +# rev 27 is missing GDS files for lvt, slvt and SRAM. + + +# Timing information (in compressed Liberty format) for synthesis and static +# timing analysis (STA). +# ------------------------------------------------------------------------ + +# Standard cells +filegroup( + name = "libgz_cells_rvt", + srcs = glob(["asap7sc7p5t_27/LIB/CCS/*RVT*.lib.gz"]), + visibility = [":data_visibility"], +) + +filegroup( + name = "libgz_cells_lvt", + srcs = glob(["asap7sc7p5t_27/LIB/CCS/*LVT*.lib.gz"]), + visibility = [":data_visibility"], +) + +filegroup( + name = "libgz_cells_slvt", + srcs = glob(["asap7sc7p5t_27/LIB/CCS/*SLVT*.lib.gz"]), + visibility = [":data_visibility"], +) + +# SRAM +filegroup( + name = "libgz_sram", + srcs = glob(["asap7sc7p5t_27/LIB/CCS/*SRAM*.lib.gz"]), + visibility = [":data_visibility"], +) + +# FIXME: What about NLDM liberty? + +# Verilog models for digital simulation and logical equivalence +# ------------------------------------------------------------------------ + +# Standard cells +filegroup( + name = "v_cells_rvt", + srcs = [ + "asap7sc7p5t_27/Verilog/asap7sc7p5t_AO_RVT_TT_210930.v", + "asap7sc7p5t_27/Verilog/asap7sc7p5t_INVBUF_RVT_TT_210930.v", + "asap7sc7p5t_27/Verilog/asap7sc7p5t_OA_RVT_TT_210930.v", + "asap7sc7p5t_27/Verilog/asap7sc7p5t_SEQ_RVT_TT_210930.v", + "asap7sc7p5t_27/Verilog/asap7sc7p5t_SIMPLE_RVT_TT_210930.v", + ], + visibility = [":data_visibility"], +) + +filegroup( + name = "v_cells_lvt", + srcs = [ + "asap7sc7p5t_27/Verilog/asap7sc7p5t_AO_LVT_TT_210930.v", + "asap7sc7p5t_27/Verilog/asap7sc7p5t_INVBUF_LVT_TT_210930.v", + "asap7sc7p5t_27/Verilog/asap7sc7p5t_OA_LVT_TT_210930.v", + "asap7sc7p5t_27/Verilog/asap7sc7p5t_SEQ_LVT_TT_210930.v", + "asap7sc7p5t_27/Verilog/asap7sc7p5t_SIMPLE_LVT_TT_210930.v", + ], + visibility = [":data_visibility"], +) + +filegroup( + name = "v_cells_slvt", + srcs = [ + "asap7sc7p5t_27/Verilog/asap7sc7p5t_AO_SLVT_TT_210930.v", + "asap7sc7p5t_27/Verilog/asap7sc7p5t_INVBUF_SLVT_TT_210930.v", + "asap7sc7p5t_27/Verilog/asap7sc7p5t_OA_SLVT_TT_210930.v", + "asap7sc7p5t_27/Verilog/asap7sc7p5t_SEQ_SLVT_TT_210930.v", + "asap7sc7p5t_27/Verilog/asap7sc7p5t_SIMPLE_SLVT_TT_210930.v", + ], + visibility = [":data_visibility"], +) + +# SRAM +filegroup( + name = "v_sram", + srcs = [ + "asap7sc7p5t_27/Verilog/asap7sc7p5t_AO_SRAM_TT_210930.v", + "asap7sc7p5t_27/Verilog/asap7sc7p5t_INVBUF_SRAM_TT_210930.v", + "asap7sc7p5t_27/Verilog/asap7sc7p5t_OA_SRAM_TT_210930.v", + "asap7sc7p5t_27/Verilog/asap7sc7p5t_SEQ_SRAM_TT_210930.v", + "asap7sc7p5t_27/Verilog/asap7sc7p5t_SIMPLE_SRAM_TT_210930.v", + ], + visibility = [":data_visibility"], +) + +# CDL models for LVS checking +# ------------------------------------------------------------------------ + +# Standard cells +filegroup( + name = "lvs_cells_rvt", + srcs = ["asap7sc7p5t_27/CDL/LVS/asap7sc7p5t_27_R.cdl"], + visibility = [":data_visibility"], +) + +filegroup( + name = "lvs_cells_lvt", + srcs = ["asap7sc7p5t_27/CDL/LVS/asap7sc7p5t_27_L.cdl"], + visibility = [":data_visibility"], +) + +filegroup( + name = "lvs_cells_slvt", + srcs = ["asap7sc7p5t_27/CDL/LVS/asap7sc7p5t_27_SL.cdl"], + visibility = [":data_visibility"], +) + +# SRAM +filegroup( + name = "lvs_sram", + srcs = ["asap7sc7p5t_27/CDL/LVS/asap7sc7p5t_27_SRAM.cdl"], + visibility = [":data_visibility"], +) + +# CDL models for Spice simulation +# ------------------------------------------------------------------------ + +# Standard cells +filegroup( + name = "spice_cells_rvt", + srcs = ["asap7sc7p5t_27/CDL/xAct3D_extracted/asap7sc7p5t_27_L_201024.sp"], + visibility = [":data_visibility"], +) + +filegroup( + name = "spice_cells_lvt", + srcs = ["asap7sc7p5t_27/CDL/xAct3D_extracted/asap7sc7p5t_27_R_201024.sp"], + visibility = [":data_visibility"], +) + +filegroup( + name = "spice_cells_slvt", + srcs = ["asap7sc7p5t_27/CDL/xAct3D_extracted/asap7sc7p5t_27_SL_201024.sp"], + visibility = [":data_visibility"], +) + +# SRAM +filegroup( + name = "spice_sram", + srcs = ["asap7sc7p5t_27/CDL/xAct3D_extracted/asap7sc7p5t_27_SRAM_201024.sp"], + visibility = [":data_visibility"], +) + +# Place and route +# ------------------------------------------------------------------------ + +# Standard cells +filegroup( + name = "lef_cells_rvt", + srcs = ["asap7sc7p5t_27/LEF/asap7sc7p5t_27_R_1x_201211.lef"], + visibility = [":data_visibility"], +) + +filegroup( + name = "lef_cells_lvt", + srcs = ["asap7sc7p5t_27/LEF/asap7sc7p5t_27_L_1x_201211.lef"], + visibility = [":data_visibility"], +) + +filegroup( + name = "lef_cells_slvt", + srcs = ["asap7sc7p5t_27/LEF/asap7sc7p5t_27_SL_1x_201211.lef"], + visibility = [":data_visibility"], +) + +# SRAM +filegroup( + name = "lef_sram", + srcs = ["asap7sc7p5t_27/LEF/asap7sc7p5t_27_SRAM_1x_201211.lef"], + visibility = [":data_visibility"], +) + +# Misc cells +# rev 27 is missing a 1x techlef + +# Alternative cells scaled up to 4x their original size. +# -------------------------------------------------------------------- + +# Standard cells +filegroup( + name = "lef_cells_4x_rvt", + srcs = ["asap7sc7p5t_27/LEF/scaled/asap7sc7p5t_27_R_4x_201211.lef"], + visibility = [":data_visibility"], +) + +filegroup( + name = "lef_cells_4x_lvt", + srcs = ["asap7sc7p5t_27/LEF/scaled/asap7sc7p5t_27_L_4x_201211.lef"], + visibility = [":data_visibility"], +) + +filegroup( + name = "lef_cells_4x_slvt", + srcs = ["asap7sc7p5t_27/LEF/scaled/asap7sc7p5t_27_SL_4x_201211.lef"], + visibility = [":data_visibility"], +) + +# SRAM +filegroup( + name = "lef_sram_4x", + srcs = ["asap7sc7p5t_27/LEF/scaled/asap7sc7p5t_27_SRAM_4x_201211.lef"], + visibility = [":data_visibility"], +) + +# Misc cells +filegroup( + name = "lef_tech_4x", + srcs = ["asap7sc7p5t_27/techlef_misc/asap7_tech_4x_201209.lef"], + visibility = [":data_visibility"], +) diff --git a/dependency_support/org_theopenroadproject_asap7/asap7sc7p5t_rev28.bzl b/dependency_support/org_theopenroadproject_asap7/asap7sc7p5t_rev28.bzl new file mode 100644 index 00000000..c5af5a4b --- /dev/null +++ b/dependency_support/org_theopenroadproject_asap7/asap7sc7p5t_rev28.bzl @@ -0,0 +1,263 @@ +# Copyright 2022 Google LLC +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" ASAP7 "rev 28" 7.5 track standard cell library with SRAM blocks. """ + +# Layouts for GDS generation +# ------------------------------------------------------------------------ + +# Standard cells +filegroup( + name = "gds_cells_rvt", + srcs = ["asap7sc7p5t_28/GDS/asap7sc7p5t_28_R_220121a.gds"], + visibility = [":data_visibility"], +) + +filegroup( + name = "gds_cells_lvt", + srcs = ["asap7sc7p5t_28/GDS/asap7sc7p5t_28_L_220121a.gds"], + visibility = [":data_visibility"], +) + +filegroup( + name = "gds_cells_slvt", + srcs = ["asap7sc7p5t_28/GDS/asap7sc7p5t_28_SL_220121a.gds"], + visibility = [":data_visibility"], +) + +# SRAM +filegroup( + name = "gds_sram", + srcs = ["asap7sc7p5t_28/GDS/asap7sc7p5t_28_SRAM_220121a.gds"], + visibility = [":data_visibility"], +) + +# Timing information (in compressed Liberty format) for synthesis and static +# timing analysis (STA). +# ------------------------------------------------------------------------ + +# Standard cells +filegroup( + name = "libgz_cells_rvt", + srcs = glob(["asap7sc7p5t_28/LIB/CCS/*RVT*.lib.gz"]), + visibility = [":data_visibility"], +) + +filegroup( + name = "libgz_cells_lvt", + srcs = glob(["asap7sc7p5t_28/LIB/CCS/*LVT*.lib.gz"]), + visibility = [":data_visibility"], +) + +filegroup( + name = "libgz_cells_slvt", + srcs = glob(["asap7sc7p5t_28/LIB/CCS/*SLVT*.lib.gz"]), + visibility = [":data_visibility"], +) + +# SRAM +filegroup( + name = "libgz_sram", + srcs = glob(["asap7sc7p5t_28/LIB/CCS/*SRAM*.lib.gz"]), + visibility = [":data_visibility"], +) + +# FIXME: What about NLDM liberty? + +# Verilog models for digital simulation and logical equivalence +# ------------------------------------------------------------------------ + +# Standard cells +filegroup( + name = "v_cells_rvt", + srcs = [ + # No CKINVDC + "asap7sc7p5t_28/Verilog/asap7sc7p5t_AO_RVT_TT_201020.v", + "asap7sc7p5t_28/Verilog/asap7sc7p5t_INVBUF_RVT_TT_201020.v", + "asap7sc7p5t_28/Verilog/asap7sc7p5t_OA_RVT_TT_201020.v", + "asap7sc7p5t_28/Verilog/asap7sc7p5t_SEQ_RVT_TT_201020.v", + "asap7sc7p5t_28/Verilog/asap7sc7p5t_SIMPLE_RVT_TT_201020.v", + ], + visibility = [":data_visibility"], +) + +filegroup( + name = "v_cells_lvt", + srcs = [ + # No CKINVDC + "asap7sc7p5t_28/Verilog/asap7sc7p5t_AO_LVT_TT_201020.v", + "asap7sc7p5t_28/Verilog/asap7sc7p5t_INVBUF_LVT_TT_201020.v", + "asap7sc7p5t_28/Verilog/asap7sc7p5t_OA_LVT_TT_201020.v", + "asap7sc7p5t_28/Verilog/asap7sc7p5t_SEQ_LVT_TT_201020.v", + "asap7sc7p5t_28/Verilog/asap7sc7p5t_SIMPLE_LVT_TT_201020.v", + ], + visibility = [":data_visibility"], +) + +filegroup( + name = "v_cells_slvt", + srcs = [ + # No CKINVDC + "asap7sc7p5t_28/Verilog/asap7sc7p5t_AO_SLVT_TT_201020.v", + "asap7sc7p5t_28/Verilog/asap7sc7p5t_INVBUF_SLVT_TT_201020.v", + "asap7sc7p5t_28/Verilog/asap7sc7p5t_OA_SLVT_TT_201020.v", + "asap7sc7p5t_28/Verilog/asap7sc7p5t_SEQ_SLVT_TT_201020.v", + "asap7sc7p5t_28/Verilog/asap7sc7p5t_SIMPLE_SLVT_TT_201020.v", + ], + visibility = [":data_visibility"], +) + +# SRAM +filegroup( + name = "v_sram", + srcs = [ + # No CKINVDC + "asap7sc7p5t_28/Verilog/asap7sc7p5t_AO_SRAM_TT_201020.v", + "asap7sc7p5t_28/Verilog/asap7sc7p5t_INVBUF_SRAM_TT_201020.v", + "asap7sc7p5t_28/Verilog/asap7sc7p5t_OA_SRAM_TT_201020.v", + "asap7sc7p5t_28/Verilog/asap7sc7p5t_SEQ_SRAM_TT_201020.v", + "asap7sc7p5t_28/Verilog/asap7sc7p5t_SIMPLE_SRAM_TT_201020.v", + ], + visibility = [":data_visibility"], +) + +# CDL models for LVS checking +# ------------------------------------------------------------------------ + +# Standard cells +filegroup( + name = "lvs_cells_rvt", + srcs = ["asap7sc7p5t_28/CDL/LVS/asap7sc7p5t_28_R.cdl"], + visibility = [":data_visibility"], +) + +filegroup( + name = "lvs_cells_lvt", + srcs = ["asap7sc7p5t_28/CDL/LVS/asap7sc7p5t_28_L.cdl"], + visibility = [":data_visibility"], +) + +filegroup( + name = "lvs_cells_slvt", + srcs = ["asap7sc7p5t_28/CDL/LVS/asap7sc7p5t_28_SL.cdl"], + visibility = [":data_visibility"], +) + +# SRAM +filegroup( + name = "lvs_sram", + srcs = ["asap7sc7p5t_28/CDL/LVS/asap7sc7p5t_28_SRAM.cdl"], + visibility = [":data_visibility"], +) + +# CDL models for Spice simulation +# ------------------------------------------------------------------------ + +# Standard cells +filegroup( + name = "spice_cells_rvt", + srcs = ["asap7sc7p5t_28/CDL/xAct3D_extracted/asap7sc7p5t_28_L.sp"], + visibility = [":data_visibility"], +) + +filegroup( + name = "spice_cells_lvt", + srcs = ["asap7sc7p5t_28/CDL/xAct3D_extracted/asap7sc7p5t_28_R.sp"], + visibility = [":data_visibility"], +) + +filegroup( + name = "spice_cells_slvt", + srcs = ["asap7sc7p5t_28/CDL/xAct3D_extracted/asap7sc7p5t_28_SL.sp"], + visibility = [":data_visibility"], +) + +# SRAM +filegroup( + name = "spice_sram", + srcs = ["asap7sc7p5t_28/CDL/xAct3D_extracted/asap7sc7p5t_28_SRAM.sp"], + visibility = [":data_visibility"], +) + +# Place and route +# ------------------------------------------------------------------------ + +# Standard cells +filegroup( + name = "lef_cells_rvt", + srcs = ["asap7sc7p5t_28/LEF/asap7sc7p5t_28_R_1x_220121a.lef"], + visibility = [":data_visibility"], +) + +filegroup( + name = "lef_cells_lvt", + srcs = ["asap7sc7p5t_28/LEF/asap7sc7p5t_28_L_1x_220121a.lef"], + visibility = [":data_visibility"], +) + +filegroup( + name = "lef_cells_slvt", + srcs = ["asap7sc7p5t_28/LEF/asap7sc7p5t_28_SL_1x_220121a.lef"], + visibility = [":data_visibility"], +) + +# SRAM +filegroup( + name = "lef_sram", + srcs = ["asap7sc7p5t_28/LEF/asap7sc7p5t_28_SRAM_1x_220121a.lef"], + visibility = [":data_visibility"], +) + +# Misc cells +filegroup( + name = "lef_tech", + srcs = ["asap7sc7p5t_28/techlef_misc/asap7_tech_1x_201209.lef"], + visibility = [":data_visibility"], +) + +# Alternative cells scaled up to 4x their original size. +# -------------------------------------------------------------------- + +# Standard cells +filegroup( + name = "lef_cells_4x_rvt", + srcs = ["asap7sc7p5t_28/LEF/scaled/asap7sc7p5t_28_R_4x_201211.lef"], + visibility = [":data_visibility"], +) + +filegroup( + name = "lef_cells_4x_lvt", + srcs = ["asap7sc7p5t_28/LEF/scaled/asap7sc7p5t_28_L_4x_201211.lef"], + visibility = [":data_visibility"], +) + +filegroup( + name = "lef_cells_4x_slvt", + srcs = ["asap7sc7p5t_28/LEF/scaled/asap7sc7p5t_28_SL_4x_201211.lef"], + visibility = [":data_visibility"], +) + +# SRAM +filegroup( + name = "lef_sram_4x", + srcs = ["asap7sc7p5t_28/LEF/scaled/asap7sc7p5t_28_SRAM_4x_201211.lef"], + visibility = [":data_visibility"], +) + +# Misc cells +filegroup( + name = "lef_tech_4x", + srcs = ["asap7sc7p5t_28/techlef_misc/asap7_tech_4x_201209.lef"], + visibility = [":data_visibility"], +) diff --git a/dependency_support/org_theopenroadproject_asap7/bundled.BUILD.bazel b/dependency_support/org_theopenroadproject_asap7/bundled.BUILD.bazel index fd08494e..79a9a4ac 100644 --- a/dependency_support/org_theopenroadproject_asap7/bundled.BUILD.bazel +++ b/dependency_support/org_theopenroadproject_asap7/bundled.BUILD.bazel @@ -12,13 +12,38 @@ # See the License for the specific language governing permissions and # limitations under the License. -"""Arizona State University 7nm PDK""" +""" ASAP7 -- Arizona State University 7nm "predictive" PDK + +The PDK has RVT, LVT and SLVT based transistors. + +The ASAP7 PDK currently provides 3 standard cell libraries; + * Two revisions (rev 27 and rev 28) of a 7.5 track library + * One revision (rev 26) of a 6 track library + +The libraries provide 3 corners, + * FF - fast + * TT - typical + * SS - slow + +These libraries are mapped to each of the transistor types; + * RVT -> R + * LVT -> L + * SLVT -> SL + +It also provides "4x scaled" versions of these libraries. These versions reuse +the same timing information but have their sizes scaled up. + +By default if not otherwise explicitly specified the default selection will be +the 7.5 track library using RVT transistors and slow corner. +""" load("@rules_hdl//pdk:open_road_configuration.bzl", "open_road_pdk_configuration") load("@rules_hdl//dependency_support/org_theopenroadproject_asap7:asap7.bzl", "asap7_cell_library") +# FIXME - Use the asap7scXXXX.bzl files. + asap7_cell_library( - name = "asap7_rvt_1x", + name = "asap7_rvt_tt", srcs = glob(["asap7sc7p5t_28/LIB/CCS/*.lib.gz"]), cell_lef = "asap7sc7p5t_28/LEF/asap7sc7p5t_28_R_1x_220121a.lef", cell_type = "RVT",