From a8e242ce2340cf3e0552ae9f2535f9af688fbc77 Mon Sep 17 00:00:00 2001 From: Tim Ansell Date: Mon, 18 Sep 2023 11:49:12 -0700 Subject: [PATCH] Give don't use cells to Yosys. Signed-off-by: Tim Ansell --- synthesis/build_defs.bzl | 7 +++++++ synthesis/synth.tcl | 4 ++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/synthesis/build_defs.bzl b/synthesis/build_defs.bzl index 14b1b460..383acae4 100644 --- a/synthesis/build_defs.bzl +++ b/synthesis/build_defs.bzl @@ -112,12 +112,19 @@ def _synthesize_design_impl(ctx): args.add_all("-l", [log_file]) # put output in log file args.add_all("-c", [synth_tcl]) # run synthesis tcl script + dont_use_args = "" + or_config = ctx.attr.standard_cells[StandardCellInfo].open_road_configuration + if or_config: + for dont_use_pattern in or_config.do_not_use_cell_list: + dont_use_args += " -dont_use {} ".format(dont_use_pattern) + script_env_files = { "FLIST": verilog_flist, "UHDM_FLIST": uhdm_flist, "TOP": ctx.attr.top_module, "OUTPUT": output_file, "LIBERTY": default_liberty_file, + "DONT_USE_ARGS": dont_use_args, } if ctx.attr.target_clock_period_pico_seconds: diff --git a/synthesis/synth.tcl b/synthesis/synth.tcl index 969a6298..a02c9681 100644 --- a/synthesis/synth.tcl +++ b/synthesis/synth.tcl @@ -72,9 +72,9 @@ set liberty $::env(LIBERTY) dfflibmap -liberty $liberty if { [info exists ::env(CLOCK_PERIOD) ] } { - abc -liberty $liberty -dff -g aig -D $::env(CLOCK_PERIOD) + abc -liberty $liberty -dff -g aig -D $::env(CLOCK_PERIOD) {*}$::env(DONT_USE_ARGS) } else { - abc -liberty $liberty -dff -g aig + abc -liberty $liberty -dff -g aig {*}$::env(DONT_USE_ARGS) } # Remove internal only aliases for public nets and then give created instances