Add multiple corners.

Add targets for fast, typical and slow corners (currently only support CCS model, but should be very easy to extend to NLDM in the future). Signed-off-by: Tim Ansell <[email protected]>
hdl · Nov 28, 2023 · d8576ff · d8576ff
1 parent 313819d
commit d8576ff
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diff --git a/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.bzl b/dependency_support/org_theopenroadproject_asap7_pdk_r1p7/asap7.bzl
@@ -139,8 +139,18 @@ def asap7_cells_files(name = None, rev = None, tracks = None, vt = None, has_gds
 
     # Library configuration
     # ------------------------------------------------------------------------
-    asap7_cell_library(
+    # Default library is slow-slow corner using CCS
+    native.alias(
         name = "asap7-sc{tracks}_rev{rev}_{vt_long}".format(**args),
+        actual = ":asap7-sc{tracks}_rev{rev}_{vt_long}-ccs_ss".format(**args),
+        visibility = [
+            "//visibility:public",
+        ],
+    )
+
+    # CCS delay model
+    asap7_cell_library(
+        name = "asap7-sc{tracks}_rev{rev}_{vt_long}-ccs_ss".format(**args),
         srcs = [
             ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lib7z".format(**args),
             #":asap7-srams-sc{tracks}_rev{rev}-lib7z".format(**args),
@@ -155,6 +165,38 @@ def asap7_cells_files(name = None, rev = None, tracks = None, vt = None, has_gds
             "//visibility:public",
         ],
     )
+    asap7_cell_library(
+        name = "asap7-sc{tracks}_rev{rev}_{vt_long}-ccs_tt".format(**args),
+        srcs = [
+            ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lib7z".format(**args),
+            #":asap7-srams-sc{tracks}_rev{rev}-lib7z".format(**args),
+        ],
+        cell_lef = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lef".format(**args),
+        platform_gds = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-gds".format(**args),
+        default_corner_delay_model = "ccs",
+        default_corner_swing = "TT",
+        openroad_configuration = ":open_road-asap7-sc{tracks}_rev{rev}_{vt_long}".format(**args),
+        tech_lef = ":asap7-misc-sc{tracks}_rev{rev}-lef".format(**args),
+        visibility = [
+            "//visibility:public",
+        ],
+    )
+    asap7_cell_library(
+        name = "asap7-sc{tracks}_rev{rev}_{vt_long}-ccs_ff".format(**args),
+        srcs = [
+            ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lib7z".format(**args),
+            #":asap7-srams-sc{tracks}_rev{rev}-lib7z".format(**args),
+        ],
+        cell_lef = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-lef".format(**args),
+        platform_gds = ":asap7-cells-sc{tracks}_rev{rev}_{vt_long}-gds".format(**args),
+        default_corner_delay_model = "ccs",
+        default_corner_swing = "FF",
+        openroad_configuration = ":open_road-asap7-sc{tracks}_rev{rev}_{vt_long}".format(**args),
+        tech_lef = ":asap7-misc-sc{tracks}_rev{rev}-lef".format(**args),
+        visibility = [
+            "//visibility:public",
+        ],
+    )
 
 def _asap7_cell_library_impl(ctx):
     liberty_files = [file for file in ctx.files.srcs if file.extension == "7z"]

diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/bundled.BUILD.bazel b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/bundled.BUILD.bazel
@@ -215,7 +215,7 @@ filegroup(
 # Library configuration
 # ------------------------------------------------------------------------
 asap7_cell_library(
-    name = "asap7-sc7p5t_rev27_rvt_4x",
+    name = "asap7-sc7p5t_rev27_rvt_4x-ccs_ss",
     srcs = [
         ":asap7-cells-sc7p5t_rev27_rvt_4x-lib7z",
         #	":asap7-srams-sc7p5t_rev27_4x-lib7z",
@@ -231,6 +231,14 @@ asap7_cell_library(
     ],
 )
 
+alias(
+    name = "asap7-sc7p5t_rev27_rvt_4x",
+    actual = ":asap7-sc7p5t_rev27_rvt_4x-ccs_ss",
+    visibility = [
+        "//visibility:public",
+    ],
+)
+
 # OpenROAD configuration
 # ------------------------------------------------------------------------
 open_road_pdk_configuration(

diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_27/cells-rvt_4x.bzl
@@ -62,7 +62,7 @@ filegroup(
 # Library configuration
 # ------------------------------------------------------------------------
 asap7_cell_library(
-    name = "asap7-sc7p5t_rev27_rvt_4x",
+    name = "asap7-sc7p5t_rev27_rvt_4x-ccs_ss",
     srcs = [
         ":asap7-cells-sc7p5t_rev27_rvt_4x-lib7z",
         #	":asap7-srams-sc7p5t_rev27_4x-lib7z",
@@ -78,6 +78,14 @@ asap7_cell_library(
     ],
 )
 
+alias(
+    name = "asap7-sc7p5t_rev27_rvt_4x",
+    actual = ":asap7-sc7p5t_rev27_rvt_4x-ccs_ss",
+    visibility = [
+        "//visibility:public",
+    ],
+)
+
 # OpenROAD configuration
 # ------------------------------------------------------------------------
 open_road_pdk_configuration(

diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/bundled.BUILD.bazel
@@ -241,3 +241,10 @@ filegroup(
     name = "asap7-misc-sc7p5t_rev28_4x-lef",
     srcs = ["techlef_misc/asap7_tech_4x_201209.lef"],
 )
+
+# Default rev28 cell library is the RVT library using slow-slow corner with CCS
+# modeling.
+alias(
+    name = "asap7-cells-sc7p5t_rev28",
+    actual = ":asap7-cells-sc7p5t_rev28_rvt-ccs_ss",
+)
diff --git a/dependency_support/org_theopenroadproject_asap7sc7p5t_28/common.bzl b/dependency_support/org_theopenroadproject_asap7sc7p5t_28/common.bzl
@@ -32,3 +32,10 @@ filegroup(
     name = "asap7-misc-sc7p5t_rev28_4x-lef",
     srcs = ["techlef_misc/asap7_tech_4x_201209.lef"],
 )
+
+# Default rev28 cell library is the RVT library using slow-slow corner with CCS
+# modeling.
+alias(
+    name = "asap7-cells-sc7p5t_rev28",
+    actual = ":asap7-cells-sc7p5t_rev28_rvt-ccs_ss",
+)
diff --git a/flows/asap7.bzl b/flows/asap7.bzl
@@ -20,7 +20,7 @@ load("//place_and_route:build_defs.bzl", "place_and_route")
 load("//static_timing:build_defs.bzl", "run_opensta")
 load("//synthesis:build_defs.bzl", "synthesize_rtl")
 
-def asap7_targets(name, target, rev, tracks, vt, has_gds = True, size = 20):
+def asap7_targets(name, target, rev, tracks, vt, has_gds = True, size = 20, corners = ("ccs_ss", "ccs_tt", "ccs_ff")):
     """Generate targets for a quick basic ASAP7 flow.
 
     Args:
@@ -31,70 +31,74 @@ def asap7_targets(name, target, rev, tracks, vt, has_gds = True, size = 20):
       vt: VT type ("rvt", "lvt", "slvt").
       has_gds: Cells have GDS layouts.
       size: Size of the die in microns.
+      corners: List of corners to generate rules for (default is `ccs_ss`, `ccs_tt`, `ccs_ff`).
     """
     if rev not in [26, 27, 28]:
         fail("Invalid rev {}".format(repr(rev)))
     if tracks not in ["7p5t", "6t"]:
         fail("Invalid rev {}".format(repr(tracks)))
 
-    a = {
-        "name": target,
-        "tracks": tracks,
-        "rev": rev,
-        "vt": vt,
-    }
+    # TODO: Add the NLDM support once it works with OpenROAD.
+    for corner in corners:
+        a = {
+            "name": target,
+            "tracks": tracks,
+            "rev": rev,
+            "vt": vt,
+            "corn": corner,
+        }
 
-    synthesize_rtl(
-        name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth".format(**a),
-        standard_cells = "@org_theopenroadproject_asap7sc{tracks}_{rev}//:asap7-sc{tracks}_rev{rev}_{vt}".format(**a),
-        target_clock_period_pico_seconds = 10000,
-        top_module = "counter",
-        deps = [
-            ":{name}".format(**a),
-        ],
-    )
-    build_test(
-        name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth".format(**a),
-        targets = [
-            ":{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth".format(**a),
-        ],
-    )
-
-    run_opensta(
-        name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth_sta".format(**a),
-        synth_target = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth".format(**a),
-    )
-    build_test(
-        name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth_sta".format(**a),
-        targets = [
-            ":{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth".format(**a),
-        ],
-    )
+        synthesize_rtl(
+            name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a),
+            standard_cells = "@org_theopenroadproject_asap7sc{tracks}_{rev}//:asap7-sc{tracks}_rev{rev}_{vt}-{corn}".format(**a),
+            target_clock_period_pico_seconds = 10000,
+            top_module = "counter",
+            deps = [
+                ":{name}".format(**a),
+            ],
+        )
+        build_test(
+            name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a),
+            targets = [
+                ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a),
+            ],
+        )
 
-    place_and_route(
-        name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}-place_and_route".format(**a),
-        core_padding_microns = 1,
-        die_height_microns = size,
-        die_width_microns = size,
-        placement_density = "0.65",
-        sdc = "constraint.sdc",
-        synthesized_rtl = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}-synth".format(**a),
-    )
-    build_test(
-        name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}-place_and_route".format(**a),
-        targets = [
-            ":{name}-asap7-sc{tracks}_rev{rev}_{vt}-place_and_route".format(**a),
-        ],
-    )
+        run_opensta(
+            name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth_sta".format(**a),
+            synth_target = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a),
+        )
+        build_test(
+            name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth_sta".format(**a),
+            targets = [
+                ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a),
+            ],
+        )
 
-    if has_gds:
-        gds_write(
-            name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}-gds".format(**a),
-            implemented_rtl = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}-place_and_route".format(**a),
+        place_and_route(
+            name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-place_and_route".format(**a),
+            core_padding_microns = 1,
+            die_height_microns = size,
+            die_width_microns = size,
+            placement_density = "0.65",
+            sdc = "constraint.sdc",
+            synthesized_rtl = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-synth".format(**a),
         )
         build_test(
-            name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}-gds".format(**a),
+            name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-place_and_route".format(**a),
             targets = [
-                ":{name}-asap7-sc{tracks}_rev{rev}_{vt}-gds".format(**a),
+                ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-place_and_route".format(**a),
             ],
         )
+
+        if has_gds:
+            gds_write(
+                name = "{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-gds".format(**a),
+                implemented_rtl = ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-place_and_route".format(**a),
+            )
+            build_test(
+                name = "build-{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-gds".format(**a),
+                targets = [
+                    ":{name}-asap7-sc{tracks}_rev{rev}_{vt}_{corn}-gds".format(**a),
+                ],
+            )
diff --git a/synthesis/tests/BUILD b/synthesis/tests/BUILD
@@ -148,6 +148,7 @@ asap7_targets(
 asap7_targets(
     name = "verilog_counter-asap7-sc7p5t_rev27_rvt_4x",
     size = 2000,
+    corners = ["ccs_ss"],
     has_gds = False,  # No GDS for the 4x cells
     rev = 27,
     target = "verilog_counter",