From dba80698fd09938aa354ed63598085cd05dca690 Mon Sep 17 00:00:00 2001
From: Tim Ansell <tansell@google.com>
Date: Mon, 18 Sep 2023 12:19:57 -0700
Subject: [PATCH] Adding support for `synth.tcl` to read SystemVerilog files
 using Surelog.

Signed-off-by: Tim Ansell <tansell@google.com>
---
 synthesis/synth.tcl | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/synthesis/synth.tcl b/synthesis/synth.tcl
index 0e2b1237..f094424f 100644
--- a/synthesis/synth.tcl
+++ b/synthesis/synth.tcl
@@ -21,7 +21,11 @@ foreach src $srcs {
     # Skip empty lines, including the implict one after the last \n delimiter
     # for files that end with a newline.
     if {$src eq ""} continue
-    yosys read_verilog -sv -defer $src
+    if {[info exists ::env(USE_SURELOG_FRONTEND)]} {
+      yosys read_systemverilog $src
+    } else {
+      yosys read_verilog -sv -defer $src
+    }
 }
 
 # read UHDM designs