Add Verilator

[mithro]

I think there is some stuff in https://github.com/google/xls/tree/main/xls/build_rules ?

[umarcor]

Ref: hdl.github.io/awesome/items/verilator

[kkiningh]

I have some rules I would be happy to contribute. See https://github.com/kkiningh/rules_verilator

[umarcor]

@kkiningh that's nice!

@mithro, any guidelines about the structure you want to use in this repo?

[QuantamHD]

I think the first thing we need to get going is a VerilogInfo provider. The benefit of that is all rules can target it for physical processing. That's how I've been formatting it within Google.

Possibly something based around https://github.com/alainmarcel/UHDM

[umarcor]

@QuantamHD, was that comment meant to be posted here? It seems to be related to Verilog (#15) and/or SystemVerilog (#16) rather than Verilator...

[QuantamHD]

For example the verible rule set in question defines a VerilogInfo as https://github.com/kkiningh/rules_verilator/blob/master/verilator/defs.bzl#L12

I think what I'd like to see is an authoritative provider other rules can target or consume; Verilog or not within this repo. HDLInfo or something related. We can provide the transitive src resolution etc. so that other rules don't need to deal with it as much. I just want a solid foundation so that we can add useful tools such that we can get solid compatibility with all the tools.

[kkiningh]

@agoessling has been doing some work in this direction in his rules_verilog repo. The corresponding provider is VerilogModuleInfo and it should be supported in rules_verilator already.

[QuantamHD]

Awesome! I'm glad there's something out there we can build around. Thanks for the tip @kkiningh.

[agoessling]

@QuantamHD VerilogModuleInfo is currently used in:

• rules_verilator
• rules_symbiyosys
• rules_vivado

Currently it is quite basic and only provides sources and the top module name. The idea being this can be shared between many tools and users only need to define their module structure once.

[mithro]

@agoessling - Would love to have your help in building this out.

[agoessling]

What is "this"?

[QuantamHD]

"this" is a project that is supposed to be a one stop shop for doing hardware dev with bazel.

So that includes

Having rules that take can RTL and be chained to emit GDSII (Sky130/FOSS-PDKs), but that can also be used to target FPGAs and soft CPUs. We want to take advantage of RBE to accelerate verification with massively parallel clusters. Using the open source community's tools like Yosys, OpenROAD, Verilator, Surelog etc.

My vision of this is that we enable bazel test //mychip/... and bazel build //mychip:gds and in 10 minutes you have verified and emitted a fabricatable design even for the most complex designs.

[per-gron]

@QuantamHD I think it could be inspiring and generally useful if you added basically what you wrote in that last comment to the top level README.md :-)