diff --git a/vivado/README.md b/vivado/README.md
index 211b8e92..ad11aadc 100644
--- a/vivado/README.md
+++ b/vivado/README.md
@@ -159,6 +159,8 @@ vivado_write_bitstream(
 
 It has the optional argument `write_bitstream_tcl_template` which by default loads [write_bitstream.tcl.template](write_bitstream.tcl.template). This can be modified.
 
+Optionally set `with_xsa = True` to generate the `.xsa` file.
+
 ## xsim_test
 
 Executes a test bench using the vivado simulator, xsim.
diff --git a/vivado/defs.bzl b/vivado/defs.bzl
index eaf96826..be481703 100644
--- a/vivado/defs.bzl
+++ b/vivado/defs.bzl
@@ -591,14 +591,25 @@ def _vivado_write_bitstream_impl(ctx):
 
     checkpoint_in = ctx.attr.checkpoint[VivadoRoutingCheckpointInfo].checkpoint
 
+    outputs = [bitstream]
+
+    if ctx.attr.with_xsa:
+        with_xsa_str = "1"
+        xsa_out = ctx.actions.declare_file("{}.xsa".format(ctx.label.name))
+        xsa_path = xsa_out.path
+        outputs.append(xsa_out)
+    else:
+        with_xsa_str = "0"
+        xsa_path = "nothing.xsa"
+
     substitutions = {
         "{{THREADS}}": "{}".format(ctx.attr.threads),
         "{{CHECKPOINT_IN}}": checkpoint_in.path,
         "{{BITSTREAM}}": bitstream.path,
+        "{{WRITE_XSA}}": with_xsa_str,
+        "{{XSA_PATH}}": xsa_path,
     }
 
-    outputs = [bitstream]
-
     default_info = run_tcl_template(
         ctx,
         ctx.file.write_bitstream_template,
@@ -627,6 +638,10 @@ vivado_write_bitstream = rule(
             doc = "Threads to pass to vivado which defines the amount of parallelism.",
             default = 8,
         ),
+        "with_xsa": attr.bool(
+            doc = "Generate xsa too",
+            default = False,
+        ),
         "write_bitstream_template": attr.label(
             doc = "The write bitstream tcl template",
             default = "@rules_hdl//vivado:write_bitstream.tcl.template",
@@ -638,7 +653,7 @@ vivado_write_bitstream = rule(
     ],
 )
 
-def vivado_flow(name, module, module_top, part_number, xilinx_env, tags = [], ip_blocks = []):
+def vivado_flow(name, module, module_top, part_number, xilinx_env, tags = [], ip_blocks = [], with_xsa=False):
     """Runs the entire bitstream flow as a convenience macro.
 
     Args:
@@ -649,6 +664,7 @@ def vivado_flow(name, module, module_top, part_number, xilinx_env, tags = [], ip
         xilinx_env: The shell script to setup the Xilinx/vivado environment.
         tags: Optional tags to use for the rules.
         ip_blocks: Optional ip blocks to include in a design.
+        with_xsa: Also generate the xsa file.
     """
     vivado_synthesize(
         name = "{}_synth".format(name),
@@ -693,6 +709,7 @@ def vivado_flow(name, module, module_top, part_number, xilinx_env, tags = [], ip
         checkpoint = "{}_route".format(name),
         xilinx_env = xilinx_env,
         tags = tags,
+        with_xsa = with_xsa,
     )
 
 def _xsim_test_impl(ctx):
diff --git a/vivado/write_bitstream.tcl.template b/vivado/write_bitstream.tcl.template
index 0efbcf14..6d2038ea 100644
--- a/vivado/write_bitstream.tcl.template
+++ b/vivado/write_bitstream.tcl.template
@@ -6,6 +6,9 @@ puts "Post Route WNS = $WNS"
 
 if {$WNS >= 0} {
     write_bitstream -force {{BITSTREAM}}
+    if {{{WRITE_XSA}}} {
+        write_hw_platform -fixed -include_bit -force -file {{XSA_PATH}}
+    }
 } else {
     puts "Failed to make timing, refusing to make bitstream"
 }