From 8fc3e8dbd63a649256daf15734520539808b034d Mon Sep 17 00:00:00 2001 From: Stephen Tridgell Date: Wed, 6 Sep 2023 16:12:23 +1000 Subject: [PATCH 1/2] Add XSA generation to write_bitstream --- vivado/README.md | 2 ++ vivado/defs.bzl | 21 ++++++++++++++++++--- vivado/write_bitstream.tcl.template | 3 +++ 3 files changed, 23 insertions(+), 3 deletions(-) diff --git a/vivado/README.md b/vivado/README.md index 211b8e92..ad11aadc 100644 --- a/vivado/README.md +++ b/vivado/README.md @@ -159,6 +159,8 @@ vivado_write_bitstream( It has the optional argument `write_bitstream_tcl_template` which by default loads [write_bitstream.tcl.template](write_bitstream.tcl.template). This can be modified. +Optionally set `with_xsa = True` to generate the `.xsa` file. + ## xsim_test Executes a test bench using the vivado simulator, xsim. diff --git a/vivado/defs.bzl b/vivado/defs.bzl index eaf96826..c3eb9493 100644 --- a/vivado/defs.bzl +++ b/vivado/defs.bzl @@ -438,7 +438,7 @@ vivado_placement = rule( ], ) -def _vivado_place_optimize_impl(ctx): +def _vivado_place_optimi outputs = [bitstream]ze_impl(ctx): placement_checkpoint = ctx.actions.declare_file("{}.dcp".format(ctx.label.name)) timing_summary_report = ctx.actions.declare_file("{}_timing.rpt".format(ctx.label.name)) util_report = ctx.actions.declare_file("{}_util.rpt".format(ctx.label.name)) @@ -591,14 +591,25 @@ def _vivado_write_bitstream_impl(ctx): checkpoint_in = ctx.attr.checkpoint[VivadoRoutingCheckpointInfo].checkpoint + outputs = [bitstream] + + if ctx.with_xsa: + with_xsa_str = "1" + xsa_out = ctx.actions.declare_file("{}.xsa".format(ctx.label.name)) + xsa_path = xsa_out.path + outputs.append(xsa_out) + else: + with_xsa_str = "0" + xsa_path = "nothing.xsa" + substitutions = { "{{THREADS}}": "{}".format(ctx.attr.threads), "{{CHECKPOINT_IN}}": checkpoint_in.path, "{{BITSTREAM}}": bitstream.path, + "{{WRITE_XSA}}": with_xsa_str, + "{{XSA_PATH}}": xsa_path, } - outputs = [bitstream] - default_info = run_tcl_template( ctx, ctx.file.write_bitstream_template, @@ -627,6 +638,10 @@ vivado_write_bitstream = rule( doc = "Threads to pass to vivado which defines the amount of parallelism.", default = 8, ), + "with_xsa": attr.bool( + doc = "Generate xsa too", + default = False, + ), "write_bitstream_template": attr.label( doc = "The write bitstream tcl template", default = "@rules_hdl//vivado:write_bitstream.tcl.template", diff --git a/vivado/write_bitstream.tcl.template b/vivado/write_bitstream.tcl.template index 0efbcf14..6d2038ea 100644 --- a/vivado/write_bitstream.tcl.template +++ b/vivado/write_bitstream.tcl.template @@ -6,6 +6,9 @@ puts "Post Route WNS = $WNS" if {$WNS >= 0} { write_bitstream -force {{BITSTREAM}} + if {{{WRITE_XSA}}} { + write_hw_platform -fixed -include_bit -force -file {{XSA_PATH}} + } } else { puts "Failed to make timing, refusing to make bitstream" } From 5d8c0d5b29fbd478dbc217e55fca1d9562f3102f Mon Sep 17 00:00:00 2001 From: Stephen Tridgell Date: Wed, 6 Sep 2023 16:19:30 +1000 Subject: [PATCH 2/2] Add xsa option to vivado flow too. --- vivado/defs.bzl | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/vivado/defs.bzl b/vivado/defs.bzl index c3eb9493..be481703 100644 --- a/vivado/defs.bzl +++ b/vivado/defs.bzl @@ -438,7 +438,7 @@ vivado_placement = rule( ], ) -def _vivado_place_optimi outputs = [bitstream]ze_impl(ctx): +def _vivado_place_optimize_impl(ctx): placement_checkpoint = ctx.actions.declare_file("{}.dcp".format(ctx.label.name)) timing_summary_report = ctx.actions.declare_file("{}_timing.rpt".format(ctx.label.name)) util_report = ctx.actions.declare_file("{}_util.rpt".format(ctx.label.name)) @@ -593,7 +593,7 @@ def _vivado_write_bitstream_impl(ctx): outputs = [bitstream] - if ctx.with_xsa: + if ctx.attr.with_xsa: with_xsa_str = "1" xsa_out = ctx.actions.declare_file("{}.xsa".format(ctx.label.name)) xsa_path = xsa_out.path @@ -653,7 +653,7 @@ vivado_write_bitstream = rule( ], ) -def vivado_flow(name, module, module_top, part_number, xilinx_env, tags = [], ip_blocks = []): +def vivado_flow(name, module, module_top, part_number, xilinx_env, tags = [], ip_blocks = [], with_xsa=False): """Runs the entire bitstream flow as a convenience macro. Args: @@ -664,6 +664,7 @@ def vivado_flow(name, module, module_top, part_number, xilinx_env, tags = [], ip xilinx_env: The shell script to setup the Xilinx/vivado environment. tags: Optional tags to use for the rules. ip_blocks: Optional ip blocks to include in a design. + with_xsa: Also generate the xsa file. """ vivado_synthesize( name = "{}_synth".format(name), @@ -708,6 +709,7 @@ def vivado_flow(name, module, module_top, part_number, xilinx_env, tags = [], ip checkpoint = "{}_route".format(name), xilinx_env = xilinx_env, tags = tags, + with_xsa = with_xsa, ) def _xsim_test_impl(ctx):