diff --git a/synthesis/synth.tcl b/synthesis/synth.tcl
index 0e2b1237..41be32ba 100644
--- a/synthesis/synth.tcl
+++ b/synthesis/synth.tcl
@@ -46,8 +46,22 @@ hierarchy -check -top $top
 yosys proc -nomux
 yosys proc_mux
 yosys flatten
+
+# Remove internal only aliases for public nets and then give created instances
+# useful names. At this stage it is mainly flipflops created by the `proc`
+# pass.
+yosys opt_clean -purge
+yosys autoname
+
 yosys synth -top $top
 
+# Remove internal only aliases for public nets and then give created instances
+# useful names. At this stage it is all the other synthesizable constructs.
+# This should be done before techmapping where things can be converted
+# dramatically and having useful names is helpful for debugging.
+yosys opt_clean -purge
+yosys autoname
+
 # mapping to liberty
 set liberty $::env(LIBERTY)
 dfflibmap -liberty $liberty
@@ -58,6 +72,12 @@ if { [info exists ::env(CLOCK_PERIOD) ] } {
   abc -liberty $liberty -dff -g aig
 }
 
+# Remove internal only aliases for public nets and then give created instances
+# useful names. At this stage it is anything generated by the techmapping
+# passes.
+yosys opt_clean -purge
+yosys autoname
+
 # write synthesized design
 set output $::env(OUTPUT)
 write_verilog $output