From 17345bea7cffaeab35963bd1c22875a112f3f970 Mon Sep 17 00:00:00 2001 From: tcal-x Date: Fri, 13 Oct 2023 15:00:15 -0700 Subject: [PATCH 1/2] Add a line to synth.tcl to remove Yosys $print cells. Signed-off-by: tcal-x --- synthesis/synth.tcl | 3 +++ 1 file changed, 3 insertions(+) diff --git a/synthesis/synth.tcl b/synthesis/synth.tcl index a02c9681..ace891fb 100644 --- a/synthesis/synth.tcl +++ b/synthesis/synth.tcl @@ -52,6 +52,9 @@ yosys proc -nomux yosys proc_mux yosys flatten +# Remove $print cells. +yosys delete {*/t:$print} + # Remove internal only aliases for public nets and then give created instances # useful names. At this stage it is mainly flipflops created by the `proc` # pass. From 45752ca803ee197c0b589368c328c07156c785df Mon Sep 17 00:00:00 2001 From: tcal-x Date: Mon, 16 Oct 2023 15:00:00 -0700 Subject: [PATCH 2/2] Add comment: why we're deleting $print cells. Signed-off-by: tcal-x --- synthesis/synth.tcl | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/synthesis/synth.tcl b/synthesis/synth.tcl index ace891fb..3186f288 100644 --- a/synthesis/synth.tcl +++ b/synthesis/synth.tcl @@ -52,7 +52,9 @@ yosys proc -nomux yosys proc_mux yosys flatten -# Remove $print cells. +# Remove $print cells. These cells represent Verilog $display() tasks. +# Some place and route tools cannot handle these in the output Verilog, +# so remove them here. yosys delete {*/t:$print} # Remove internal only aliases for public nets and then give created instances