From 75268363d75c62d8bbcb6ae04e49aa108d3f751c Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Wed, 10 Jan 2024 13:09:04 -0800 Subject: [PATCH] Add memory usage options to place and route step. OpenROAD uses ~6->8g of memory for place and route for these tests and bazel recommends using 2x the value. Signed-off-by: Tim 'mithro' Ansell --- tests/BUILD | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/tests/BUILD b/tests/BUILD index bfe56e85..dd33e288 100644 --- a/tests/BUILD +++ b/tests/BUILD @@ -74,6 +74,9 @@ place_and_route( core_padding_microns = 20, die_height_microns = 200, die_width_microns = 200, + exec_properties = dict( + mem = "16g", + ), placement_density = "0.7", synthesized_rtl = ":verilog_adder-synth", ) @@ -84,6 +87,9 @@ place_and_route( core_padding_microns = 20, die_height_microns = 200, die_width_microns = 200, + exec_properties = dict( + mem = "16g", + ), placement_density = "0.7", sdc = "constraint.sdc", synthesized_rtl = ":verilog_counter-synth", @@ -120,12 +126,18 @@ place_and_route( EXTRA_ARGS = { "verilog_counter": { "place_and_route": dict( + exec_properties = dict( + mem = "16g", + ), sdc = "constraint.sdc", ), }, "verilog_adder": { "place_and_route": dict( clock_period = None, # Combinational only design + exec_properties = dict( + mem = "16g", + ), ), }, }