sim/icarus: use multiline block syntax for the summary string

sim/icarus/meta.yaml

@@ -57,4 +57,9 @@ about:
   home: http://iverilog.icarus.com/
   license: GPLv2
   license_file: COPYING
-  summary: 'Icarus Verilog (iverilog) is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. For synthesis, the compiler generates netlists in the desired format.'
+  summary: |
+    Icarus Verilog (iverilog) is a Verilog simulation and synthesis tool.
+    It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format.
+    For batch simulation, the compiler can generate an intermediate form called vvp assembly.
+    This intermediate form is executed by the ``vvp'' command.
+    For synthesis, the compiler generates netlists in the desired format.'