From 3aa424bfd01adb93c0035dc6aef411e278accf72 Mon Sep 17 00:00:00 2001 From: Unai Martinez-Corral Date: Thu, 17 Feb 2022 09:27:59 +0100 Subject: [PATCH 1/2] sim/icarus: remove redundant tests from build script --- sim/icarus/build.sh | 3 --- 1 file changed, 3 deletions(-) diff --git a/sim/icarus/build.sh b/sim/icarus/build.sh index 3dbad0ff..15632154 100644 --- a/sim/icarus/build.sh +++ b/sim/icarus/build.sh @@ -10,6 +10,3 @@ sh ./autoconf.sh make -j$CPU_COUNT make install - -$PREFIX/bin/iverilog -V -$PREFIX/bin/iverilog -h || true From 07d973d25128e75f303f51e805810c14f9413ffe Mon Sep 17 00:00:00 2001 From: Unai Martinez-Corral Date: Thu, 17 Feb 2022 09:29:05 +0100 Subject: [PATCH 2/2] sim/icarus: use multiline block syntax for the summary string --- sim/icarus/meta.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/sim/icarus/meta.yaml b/sim/icarus/meta.yaml index 06124a5d..40a1a26f 100644 --- a/sim/icarus/meta.yaml +++ b/sim/icarus/meta.yaml @@ -57,4 +57,9 @@ about: home: http://iverilog.icarus.com/ license: GPLv2 license_file: COPYING - summary: 'Icarus Verilog (iverilog) is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. For synthesis, the compiler generates netlists in the desired format.' + summary: | + Icarus Verilog (iverilog) is a Verilog simulation and synthesis tool. + It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. + For batch simulation, the compiler can generate an intermediate form called vvp assembly. + This intermediate form is executed by the ``vvp'' command. + For synthesis, the compiler generates netlists in the desired format.'