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I was reviewing hdl/pyHDLParser#10 which looked to fix something here in Symbolator with is_array not working. But I believe @kammoh's change more suitably belongs here. is_array expects a string so perhaps the following code should be passing in p.data_type.name?
def reformat_array_params(vo):
'''Convert array ranges to Verilog style'''
for p in vo.ports:
# Replace VHDL downto and to
- data_type = p.data_type.replace(' downto ', ':').replace(' to ', '\u2799')+ data_type = p.data_type.name.replace(' downto ', ':').replace(' to ', '\u2799')
# Convert to Verilog style array syntax
data_type = re.sub(r'([^(]+)\((.*)\)$', r'\1[\2]', data_type)
I imagine there's input that breaks data_type passed into is_array in make_section for a similar dynamic typing reason. I'll leave @kammoh to explain the is_array failure further. I get correct is_array output with this test case.
I was reviewing hdl/pyHDLParser#10 which looked to fix something here in Symbolator with
is_array
not working. But I believe @kammoh's change more suitably belongs here.is_array
expects a string so perhaps the following code should be passing inp.data_type.name
?symbolator/symbolator.py
Line 306 in 3f02d90
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