DDR4 Controller

[hughperkins]

We need a DDR4 Controller, to manage global memory, which sits in DDR chips, separate from the main GPU chip.

The DDR4 Controller will be used to copy data to and from the GPU global memory, in order to populate shared memory, caches and similar on the GPU chip itself; and in order for the GPU to be able to write data back to global memory. For now, we will assume that all communications are with a single GPU Controller module on the GPU die. For example, we will assume for now that any data copied from mainboard main memory to GPU global memory will pass via the GPU controller.

What we need for VeriGPU:

• comprehensive verification, ideally including formal verification
• clear documentation on how to use and integrate with VeriGPU
  • how to use the interface to write to GPU global memory?
  • how to use the interface to read from GPU global memory?
• ideally, a PR that integrates the DDR4 controller into VeriGPU

Bear in mind that tape-out at 5nm costs $250M or so, so we want things to work first time. Therefore verification is important :)

[mithro]

You might find the following resources interesting;

Google has continued to work heavily with Antmicro to push forward the state of open source memory controller solutions. Our current focus has been around making sure we are able to explore current issues around RowHammer. See the following links;

• https://opensource.googleblog.com/2021/11/Open%20source%20DDR%20controller%20framework%20for%20mitigating%20Rowhammer.html
• https://cfp.openpower.foundation/summit2021/talk/C9Q3GS/
• https://antmicro.com/blog/2021/04/lpddr4-test-platform/
• https://security.googleblog.com/2021/05/introducing-half-double-new-hammering.html
• https://github.com/antmicro/litex-rowhammer-tester
• https://litex-rowhammer-tester.readthedocs.io/en/latest/
• https://github.com/antmicro/lpddr4-testbed
• https://github.com/antmicro/lpddr4-test-board
• https://github.com/antmicro/data-center-dram-tester
• https://github.com/enjoy-digital/litedram

While the memory controller is being actively developed on FPGAs, we have also started work on making sure that it can also be used in ASIC solutions. The current plan is to do tape outs of this controller in both SKY130 and GF12LP technologies in 2022 using only open source tooling like OpenROAD for the digital blocks. This means we will also need open source PHYs to make this possible and are actively working to build out that area too.

Also take a look at https://github.com/waviousllc/wav-lpddr-hw

[mithro]

There are also multiple examples of integrating LiteDRAM into non-Migen designs (like MicroWatt).