Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

你好，跑了一下，少了很多模块，比如xil_defualtlib.mult16，xil_defualtlib.im_in。这些东西从哪里找，请问能上传一下么 #2

Open
GaoYiMng opened this issue Mar 23, 2018 · 4 comments
Open

你好，跑了一下，少了很多模块，比如xil_defualtlib.mult16，xil_defualtlib.im_in。这些东西从哪里找，请问能上传一下么 #2

GaoYiMng opened this issue Mar 23, 2018 · 4 comments

Comments

@GaoYiMng
Copy link

No description provided.

@Stiles123
Copy link

还有一些包括： bias_mult2 , ind_conc_in , conv_ram等模块也没有，想知道这代表着什么

@hunterlew
Copy link
Owner

朋友之前没接触FPGA开发？这些是ISE中的IP核呀

@nobody163
Copy link

xil_defualtlib.im_in,请问一下这个用哪个核呀？

@nobody163
Copy link

最好能把所有用到核的参数给一下，谢谢了~

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
4 participants
@hunterlew @nobody163 @Stiles123 @GaoYiMng