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si4468.c
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/*
* This is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* The software is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU Radio; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include "ch.h"
#include "hal.h"
#include "nanovna.h"
#include <math.h>
#include "si4432.h"
#include "spi.h"
#pragma GCC push_options
#pragma GCC optimize ("O2")
//#define __USE_FRR_FOR_RSSI__
// Define for use hardware SPI mode
#define USE_HARDWARE_SPI_MODE
// 10MHz clock
#define SI4432_10MHZ 10000000U
// !!!! FROM ili9341.c for disable it !!!!
//#define LCD_CS_HIGH palSetPad(GPIOB, GPIOB_LCD_CS)
// Not use delays for CS
#if 1
#define SI_CS_DELAY
#define PE_CS_DELAY
#define ADF_CS_DELAY
#else
#define SI_CS_DELAY {__asm("NOP");__asm("NOP");__asm("NOP");__asm("NOP");}
#define PE_CS_DELAY {__asm("NOP");__asm("NOP");__asm("NOP");__asm("NOP");}
#define ADF_CS_DELAY {__asm("NOP");__asm("NOP");__asm("NOP");__asm("NOP");}
#endif
#define SI_CS_LOW {palClearLine(LINE_RX_SEL);SI_CS_DELAY;}
#define SI_CS_HIGH {SI_CS_DELAY;palSetLine(LINE_RX_SEL);}
#define SI_SDN_LOW palClearLine(LINE_RX_SDN);
#define SI_SDN_HIGH palSetLine(LINE_RX_SDN);
// Hardware or software SPI use
#ifdef USE_HARDWARE_SPI_MODE
#define SI4432_SPI SPI1
// Check device SPI clock speed
#if STM32_PCLK2 > 48000000 // 48 or 72M MCU
// On 72M MCU STM32_PCLK2 = 72M, SPI = 72M/4 = 18M
//#define SI4432_SPI_SPEED SPI_BR_DIV4
#define SI4432_SPI_SPEED SPI_BR_DIV8
#else
// On 48M MCU STM32_PCLK2 = 48M, SPI = 48M/2 = 24M
//#define SI4432_SPI_SPEED SPI_BR_DIV2
#define SI4432_SPI_SPEED SPI_BR_DIV4
#endif
//#define ADF_SPI_SPEED SPI_BR_DIV64
//#define ADF_SPI_SPEED SPI_BR_DIV32
#define ADF_SPI_SPEED SPI_BR_DIV2
#define PE4302_HW_SHIFT true
#define PE_SPI_SPEED SPI_BR_DIV8
#define PE_SW_DELAY 2
static uint32_t old_spi_settings;
#else
static uint32_t new_port_moder;
#endif
static uint32_t old_port_moder;
#define SPI1_CLK_HIGH palSetPad(GPIOB, GPIOB_SPI_SCLK)
#define SPI1_CLK_LOW palClearPad(GPIOB, GPIOB_SPI_SCLK)
#define SPI1_SDI_HIGH palSetPad(GPIOB, GPIOB_SPI_MOSI)
#define SPI1_SDI_LOW palClearPad(GPIOB, GPIOB_SPI_MOSI)
#define SPI1_RESET palClearPort(GPIOB, (1<<GPIOB_SPI_SCLK)|(1<<GPIOB_SPI_MOSI))
#define SPI1_SDO ((palReadPort(GPIOB)>>GPIOB_SPI_MISO)&1)
#define SPI1_portSDO (palReadPort(GPIOB)&(1<<GPIOB_SPI_MISO))
#ifdef __PE4302__
#define CS_PE_HIGH {PE_CS_DELAY;palSetLine(LINE_PE_SEL);}
#define CS_PE_LOW {PE_CS_DELAY;palClearLine(LINE_PE_SEL);}
#endif
//#define MAXLOG 1024
//unsigned char SI4432_logging[MAXLOG];
//volatile int log_index = 0;
//#define SI4432_log(X) { if (log_index < MAXLOG) SI4432_logging[log_index++] = X; }
#define SI4432_log(X)
void start_SI4432_SPI_mode(void){
#ifdef USE_HARDWARE_SPI_MODE
old_spi_settings = SI4432_SPI->CR1;
SPI_BR_SET(SI4432_SPI, SI4432_SPI_SPEED);
#else
// Init legs mode for software bitbang
old_port_moder = GPIOB->MODER;
new_port_moder = old_port_moder & ~(PIN_MODE_ANALOG(GPIOB_SPI_SCLK)|PIN_MODE_ANALOG(GPIOB_SPI_MISO)|PIN_MODE_ANALOG(GPIOB_SPI_MOSI));
new_port_moder|= PIN_MODE_OUTPUT(GPIOB_SPI_SCLK)|PIN_MODE_INPUT(GPIOB_SPI_MISO)|PIN_MODE_OUTPUT(GPIOB_SPI_MOSI);
GPIOB->MODER = new_port_moder;
// Pull down SPI
SPI1_SDI_LOW;
SPI1_CLK_LOW;
#endif
}
void stop_SI4432_SPI_mode(void){
#ifdef USE_HARDWARE_SPI_MODE
SI4432_SPI->CR1 = old_spi_settings;
#else
// Restore hardware SPI
GPIOB->MODER = old_port_moder;
#endif
}
void start_PE4312_SPI_mode(void){
// Init legs mode for software bitbang
old_spi_settings = SI4432_SPI->CR1;
old_port_moder = GPIOB->MODER;
uint32_t new_port_moder = old_port_moder & ~(PIN_MODE_ANALOG(GPIOB_SPI_SCLK)|PIN_MODE_ANALOG(GPIOB_SPI_MISO)|PIN_MODE_ANALOG(GPIOB_SPI_MOSI));
new_port_moder|= PIN_MODE_OUTPUT(GPIOB_SPI_SCLK)|PIN_MODE_INPUT(GPIOB_SPI_MISO)|PIN_MODE_OUTPUT(GPIOB_SPI_MOSI);
GPIOB->MODER = new_port_moder;
// Pull down SPI
SPI1_SDI_LOW;
SPI1_CLK_LOW;
}
void stop_PE4312_SPI_mode(void){
// Restore hardware SPI
GPIOB->MODER = old_port_moder;
SI4432_SPI->CR1 = old_spi_settings;
}
#if 0
static void software_shiftOut(uint8_t val)
{
SI4432_log(SI4432_Sel);
SI4432_log(val);
uint8_t i = 0;
do {
if (val & 0x80)
SPI1_SDI_HIGH;
my_microsecond_delay(PE_SW_DELAY);
SPI1_CLK_HIGH;
my_microsecond_delay(PE_SW_DELAY);
SPI1_RESET;
val<<=1;
}while((++i) & 0x07);
}
#endif
static void shiftOut(uint8_t val)
{
#ifdef USE_HARDWARE_SPI_MODE
while (SPI_TX_IS_NOT_EMPTY(SI4432_SPI));
SPI_WRITE_8BIT(SI4432_SPI, val);
while (SPI_IS_BUSY(SI4432_SPI)) // drop rx and wait tx
(void)SPI_READ_8BIT(SI4432_SPI);
#else
SI4432_log(SI4432_Sel);
SI4432_log(val);
uint8_t i = 0;
do {
SPI1_SDI_HIGH;
SPI1_CLK_HIGH;
SPI1_RESET;
val<<=1;
}while((++i) & 0x07);
#endif
}
static uint8_t shiftIn(void)
{
#ifdef USE_HARDWARE_SPI_MODE
// while (SPI_TX_IS_NOT_EMPTY(SI4432_SPI));
SPI_WRITE_8BIT(SI4432_SPI, 0xFF);
while (SPI_RX_IS_EMPTY(SI4432_SPI)) ; // drop rx and wait tx
return SPI_READ_8BIT(SI4432_SPI);
#else
uint32_t value = 0;
uint8_t i = 0;
do {
value<<=1;
SPI1_CLK_HIGH;
value|=SPI1_portSDO;
SPI1_CLK_LOW;
}while((++i) & 0x07);
return value>>GPIOB_SPI_MISO;
#endif
}
uint32_t SI4432_step_delay = 1500;
uint32_t SI4432_offset_delay = 1500;
#define MINIMUM_WAIT_FOR_RSSI 280
//------------PE4302 -----------------------------------------------
#ifdef __PE4302__
void PE4302_init(void) {
CS_PE_LOW;
}
static unsigned char old_attenuation = 255;
bool PE4302_Write_Byte(unsigned char DATA )
{
// if (old_attenuation == DATA) /// Must always have same execution time
// return false;
old_attenuation = DATA;
#ifdef __ARW621__
DATA = DATA << 1;
#endif
#if PE4302_HW_SHIFT
set_SPI_mode(SPI_MODE_SI);
if (SI4432_SPI_SPEED != PE_SPI_SPEED)
SPI_BR_SET(SI4432_SPI, PE_SPI_SPEED);
SPI_WRITE_8BIT(SI4432_SPI, DATA);
while (SPI_IS_BUSY(SI4432_SPI));
#else // Run PE4312 in SW mode to avoid disturbances
set_SPI_mode(SPI_MODE_PE);
software_shiftOut(DATA);
#endif
CS_PE_HIGH;
my_microsecond_delay(PE_SW_DELAY);
CS_PE_LOW;
my_microsecond_delay(PE_SW_DELAY);
#if PE4302_HW_SHIFT
if (SI4432_SPI_SPEED != PE_SPI_SPEED)
SPI_BR_SET(SI4432_SPI, SI4432_SPI_SPEED);
#endif
return true;
}
#endif
//------------------------------- ADF4351 -------------------------------------
#define bitRead(value, bit) (((value) >> (bit)) & 0x01)
#define bitSet(value, bit) ((value) |= (1UL << (bit)))
#define bitClear(value, bit) ((value) &= ~(1UL << (bit)))
#define bitWrite(value, bit, bitvalue) ((bitvalue) ? bitSet(value, bit) : bitClear(value, bit))
#define maskedWrite(reg, bit, mask, value) (reg) &= ~(((uint32_t)mask) << (bit)); (reg) |= ((((uint32_t) (value)) & ((uint32_t)mask)) << (bit));
freq_t local_setting_frequency_30mhz_x100 = 3000000000;
#define CS_ADF0_HIGH {palSetLine(LINE_LO_SEL);ADF_CS_DELAY;}
#define CS_ADF1_HIGH {ADF_CS_DELAY;palSetLine(LINE_LO_SEL);}
#define CS_ADF0_LOW {palClearLine(LINE_LO_SEL);ADF_CS_DELAY;}
#define CS_ADF1_LOW {ADF_CS_DELAY;palClearLine(LINE_LO_SEL);}
#define CS_ADF_LOW(ch) {palClearLine(ch);ADF_CS_DELAY;}
#define CS_ADF_HIGH(ch) {ADF_CS_DELAY;palSetLine(ch);}
uint32_t registers[6] = {0xC88000, 0x8008011, 0x1800C642, 0x48963,0xA5003C , 0x580005} ; //10 MHz ref
uint32_t old_registers[6];
int debug = 0;
ioline_t ADF4351_LE[2] = { LINE_LO_SEL, LINE_LO_SEL};
//int ADF4351_Mux = 7;
bool ADF4351_frequency_changed = false;
//#define DEBUG(X) // Serial.print( X )
//#define DEBUGLN(X) Serial.println( X )
//#define DEBUGFLN(X,Y) Serial.println( X,Y )
//#define DEBUGF(X,Y) Serial.print( X,Y )
#define DEBUG(X)
#define DEBUGLN(X)
#define XTAL 300000000
uint64_t PFDRFout[6] = {XTAL,XTAL,XTAL,10000000,10000000,10000000}; //Reference freq in MHz
int64_t
ADF4350_modulo = 0, // Linked to spur table!!!!!
target_freq;
int old_R = 0;
#ifdef __SI5351__
#include "si5351.h"
#else
int si5351_available = false;
#endif
void ADF4351_Setup(void)
{
// palSetPadMode(GPIOA, 1, PAL_MODE_OUTPUT_PUSHPULL );
// palSetPadMode(GPIOA, 2, PAL_MODE_OUTPUT_PUSHPULL );
local_setting_frequency_30mhz_x100 = config.setting_frequency_30mhz;
#ifdef __SI5351__
si5351_available = si5351_init();
if (si5351_available)
si5351_set_frequency(0, 30000000, 0);
si5351_available = false; // Don't use shifting
#endif
// SPI3_CLK_HIGH;
// SPI3_SDI_HIGH;
CS_ADF0_HIGH;
// CS_ADF1_HIGH;
// bitSet (registers[2], 17); // R set to 8
// bitClear (registers[2], 14); // R set to 8
// while(1) {
//
ADF4351_R_counter(1);
ADF4351_CP(0);
ADF4351_fastlock(1); // Fastlock enabled
ADF4351_csr(1); //Cycle slip enabled
ADF4351_set_frequency(0,200000000);
ADF4351_mux(2); // No led
// ADF4351_mux(6); // Show lock on led
}
void ADF4351_WriteRegister32(int channel, const uint32_t value)
{
// Select chip
CS_ADF_LOW(ADF4351_LE[channel]);
// Send 32 bit register
#if 1
SPI_WRITE_8BIT(SI4432_SPI, (value >> 24));
SPI_WRITE_8BIT(SI4432_SPI, (value >> 16));
SPI_WRITE_8BIT(SI4432_SPI, (value >> 8));
SPI_WRITE_8BIT(SI4432_SPI, (value >> 0));
while (SPI_IS_BUSY(SI4432_SPI)); // drop rx and wait tx
#else
shiftOut((value >> 24) & 0xFF);
shiftOut((value >> 16) & 0xFF);
shiftOut((value >> 8) & 0xFF);
shiftOut((value >> 0) & 0xFF);
#endif
// unselect
CS_ADF_HIGH(ADF4351_LE[channel]);
}
void ADF4351_Set(int channel)
{
#if 0
for (int i = 5; i >= 0; i--) {
if (registers[i] != old_registers[i])
goto update;
}
return;
update:
#endif
set_SPI_mode(SPI_MODE_SI);
if (SI4432_SPI_SPEED != ADF_SPI_SPEED)
SPI_BR_SET(SI4432_SPI, ADF_SPI_SPEED);
for (int i = 5; i >= 0; i--) {
#if 0
if (i == 0 || registers[i] != old_registers[i])
#endif
ADF4351_WriteRegister32(channel, registers[i]);
old_registers[i] = registers[i];
}
if (SI4432_SPI_SPEED != ADF_SPI_SPEED)
SPI_BR_SET(SI4432_SPI, SI4432_SPI_SPEED);
}
static freq_t prev_actual_freq = 0;
void ADF4351_force_refresh(void) {
prev_actual_freq = 0;
for (int i = 5; i >= 0; i--)
old_registers[i] = 0;
}
void ADF4351_modulo(int m)
{
ADF4350_modulo = m;
// ADF4351_set_frequency(0, (uint64_t)prev_actual_freq);
}
uint64_t ADF4351_set_frequency(int channel, uint64_t freq) // freq / 10Hz
{
uint64_t actual_freq = ADF4351_prepare_frequency(channel,freq);
if (actual_freq != prev_actual_freq) {
ADF4351_frequency_changed = true;
ADF4351_Set(channel);
prev_actual_freq = actual_freq;
}
return actual_freq;
}
void ADF4351_spur_mode(int S)
{
bitWrite(registers[2], 29, S & 1);
bitWrite(registers[2], 30, S & 2);
ADF4351_Set(0);
}
void ADF4351_R_counter(int R)
{
if (R == old_R)
return;
old_R = R;
int dbl = false;
if (R < 0) {
dbl = true;
R = -R;
}
if (R<1)
return;
bitWrite(registers[2], 25, dbl); // Reference doubler
for (int channel=0; channel < 6; channel++) {
PFDRFout[channel] = (local_setting_frequency_30mhz_x100 * (dbl?2:1)) / R;
}
maskedWrite(registers[2],14, 0x3FF, R);
// ADF4351_Set(0); // Let next frequency set do the writing
// ADF4351_force_refresh();
clear_frequency_cache(); // When R changes the possible frequencies will change
}
void ADF4351_recalculate_PFDRFout(void){
int local_r = old_R;
old_R = -1;
local_setting_frequency_30mhz_x100 = config.setting_frequency_30mhz;
ADF4351_R_counter(local_r);
}
#ifdef __SI5351__
static int shifted = -2;
#define SHIFT_MUL 31
#define SHIFT_DIV 29
#define SHIFT_FACTOR 100000
void ADF4350_shift_ref(int f) {
if (f == shifted)
return;
shifted = false;
local_setting_frequency_30mhz_x100 = config.setting_frequency_30mhz;
if (shifted) {
local_setting_frequency_30mhz_x100 = (local_setting_frequency_30mhz_x100 * SHIFT_MUL) / SHIFT_DIV;
}
if (si5351_available && shifted)
si5351_set_int_mul_div(0, SHIFT_MUL, SHIFT_DIV, 0);
else
si5351_set_int_mul_div(0, 30, 30, 0);
ADF4351_recalculate_PFDRFout();
shifted = f;
}
#endif
void ADF4351_mux(int R)
{
maskedWrite(registers[2],26, 0x7, R);
// registers[2] &= ~(((uint32_t) 0x7) << 26);
// registers[2] |= (((uint32_t)R & 0x07) << 26);
ADF4351_Set(0);
}
void ADF4351_csr(int c)
{
maskedWrite(registers[3],18, 0x1, c);
// registers[3] &= ~(((uint32_t) 0x1) << 18);
// registers[3] |= (((uint32_t)c & 0x01) << 18);
ADF4351_Set(0);
}
void ADF4351_fastlock(int c)
{
maskedWrite(registers[3],15, 0x3, c);
// registers[3] &= ~(((uint32_t) 0x3) << 15);
// registers[3] |= (((uint32_t)c & 0x03) << 15);
ADF4351_Set(0);
}
void ADF4351_CP(int p)
{
maskedWrite(registers[2],9, 0xF, p);
// registers[2] &= ~(((uint32_t)0xF) << 9);
// registers[2] |= (((uint32_t) p) << 9);
ADF4351_Set(0);
}
void ADF4351_drive(int p)
{
if (((registers[4] >> 3) & 0x03 ) == (p & 0x03))
return;
maskedWrite(registers[4],3, 0x3, p);
// p &= 0x03;
// registers[4] &= ~(((uint32_t)0x3) << 3);
// registers[4] |= (((uint32_t) p) << 3);
ADF4351_Set(0);
my_microsecond_delay(1000);
}
void ADF4351_aux_drive(int p)
{
if (((registers[4] >> 6) & 0x03 ) == (p & 0x03))
return;
maskedWrite(registers[4],6, 0x3, p);
// p &= 0x03;
// registers[4] &= ~(((uint32_t)0x3) << 6);
// registers[4] |= (((uint32_t) p) << 6);
ADF4351_Set(0);
}
#if 0
static uint32_t gcd(uint32_t x, uint32_t y)
{
uint32_t z;
while (y != 0) {
z = x % y;
x = y;
y = z;
}
return x;
}
#endif
uint64_t ADF4351_prepare_frequency(int channel, uint64_t freq) // freq / 10Hz
{
uint32_t output_divider;
target_freq = freq;
if (freq >= 2200000000) {
output_divider = 1 * FREQ_MULTIPLIER;
bitWrite (registers[4], 22, 0);
bitWrite (registers[4], 21, 0);
bitWrite (registers[4], 20, 0);
} else if (freq >= 1100000000) {
output_divider = 2 * FREQ_MULTIPLIER;
bitWrite (registers[4], 22, 0);
bitWrite (registers[4], 21, 0);
bitWrite (registers[4], 20, 1);
} else if (freq >= 550000000) {
output_divider = 4 * FREQ_MULTIPLIER;
bitWrite (registers[4], 22, 0);
bitWrite (registers[4], 21, 1);
bitWrite (registers[4], 20, 0);
} else if (freq >= 275000000) {
output_divider = 8 * FREQ_MULTIPLIER;
bitWrite (registers[4], 22, 0);
bitWrite (registers[4], 21, 1);
bitWrite (registers[4], 20, 1);
} else { // > 137500000
output_divider = 16 * FREQ_MULTIPLIER;
bitWrite (registers[4], 22, 1);
bitWrite (registers[4], 21, 0);
bitWrite (registers[4], 20, 0);
}
uint32_t PFDR = (uint32_t)PFDRFout[channel];
uint32_t MOD = ADF4350_modulo;
if (MOD == 0)
MOD = 60;
uint32_t MOD_X2 = MOD<<1;
uint32_t INTA_F = ((freq * (uint64_t)output_divider) * (uint64_t)MOD_X2/ PFDR) + 1;
uint32_t INTA = INTA_F / MOD_X2;
uint32_t FRAC = (INTA_F - INTA * MOD_X2)>>1;
if (FRAC >= MOD) {
FRAC -= MOD;
INTA++;
}
#if 0 // No visible performance improvement
uint32_t reduce = gcd(MOD, FRAC);
if (reduce>1) {
FRAC /= reduce;
MOD /= reduce;
if (MOD == 1)
MOD=2;
}
#endif
uint64_t actual_freq = ((uint64_t)PFDR *(INTA * MOD +FRAC))/output_divider / MOD;
#if 0 // Only for debugging
int max_delta = PFDRFout[channel]/output_divider/MOD/100;
if (actual_freq < freq - max_delta || actual_freq > freq + max_delta ){
while(1)
my_microsecond_delay(10);
}
max_delta = freq - actual_freq;
if (max_delta > 200000 || max_delta < -200000 || freq == 0) {
while(1)
my_microsecond_delay(10);
}
if (FRAC >= MOD ){
while(1)
my_microsecond_delay(10);
}
#endif
bitWrite (registers[4], 10, 1); // Mute till lock detect
registers[0] = 0;
registers[0] = INTA << 15; // OK
registers[0] = registers[0] + (FRAC << 3);
if (MOD == 1) MOD = 2;
registers[1] = 0;
registers[1] = MOD << 3;
registers[1] |= 1 ; // restore register address "001"
registers[1] |= 1 << 15; // Set PHASE to 1
bitSet (registers[1], 27); // Prescaler at 8/9
return actual_freq;
}
void ADF4351_enable(int s)
{
if (bitRead(registers[4],11) != (s & 0x01))
return;
if (s)
bitClear(registers[4], 11); // Inverse logic!!!!!
else
bitSet(registers[4], 11);
ADF4351_Set(0);
osalThreadSleepMilliseconds(10);
}
void ADF4351_enable_aux_out(int s)
{
if (bitRead(registers[4],8) == (s & 0x01))
return;
if (s) {
bitSet(registers[4], 8);
maskedWrite(registers[4],6, 0x3, 3); // Max drive aux out
} else
bitClear(registers[4], 8);
ADF4351_Set(0);
osalThreadSleepMilliseconds(10);
}
void ADF4351_enable_out(int s)
{
if (bitRead(registers[4],5) == (s & 0x01))
return;
if (s) {
bitClear(registers[4], 11); // Disable VCO power down
bitClear(registers[2], 5); // Disable power down
bitSet(registers[4], 5); // Enable output
} else {
bitClear(registers[4], 5); // Disable output
bitSet(registers[2], 5); // Enable power down
bitSet(registers[4], 11); // Enable VCO power down
}
ADF4351_Set(0);
osalThreadSleepMilliseconds(1);
}
// ------------------------------ SI4468 -------------------------------------
bool SI4463_frequency_changed = false;
bool SI4463_offset_changed = false;
int SI4463_offset_value = 0;
uint8_t SI4463_rbw_selected = 0;
static int SI4463_band = -1;
//static freq_t SI4463_prev_freq = 0;
//static float SI4463_step_size = 100; // Will be recalculated once used
static uint8_t SI4463_channel = 0;
static uint8_t SI4463_in_tx_mode = false;
//int SI4463_R = 5;
static int SI4463_output_level = 0x20;
static si446x_state_t SI4463_get_state(void);
static int SI4463_set_state(si446x_state_t);
#define SI4463_READ_CTS (palReadLine(LINE_RX_CTS))
#define SI4463_CTS_TIMEOUT 10000000
#ifdef __WAIT_CTS_WHILE_SLEEPING__
extern volatile int sleep;
#if 0
#define SI4463_WAIT_CTS while (!SI4463_READ_CTS) {\
if (sleep) {\
CS_PE_HIGH;\
__WFI();\
CS_PE_LOW;\
} \
};
#else
inline int SI4463_wait_CTS(void) {
int t=0;
while (!SI4463_READ_CTS) {
t++;
if (t >=SI4463_CTS_TIMEOUT)
return -1;
}
return 0;
}
#define SI4463_WAIT_CTS SI4463_wait_CTS()
//#define SI4463_WAIT_CTS {int t=0; while (!SI4463_READ_CTS) { t++; if (t >=SI4463_CTS_TIMEOUT) ili9341_drawstring("SI4486 deadlock", 0,20);} }
#endif
#else
#define SI4463_WAIT_CTS while (!SI4463_READ_CTS) ;
#endif
#if 0 // not used
static void SI4463_write_byte(uint8_t ADR, uint8_t DATA)
{
set_SPI_mode(SPI_MODE_SI);
SI_CS_LOW;
ADR |= 0x80 ; // RW = 1
shiftOut( ADR );
shiftOut( DATA );
SI_CS_HIGH;
}
static void SI4463_write_buffer(uint8_t ADR, uint8_t *DATA, int len)
{
set_SPI_mode(SPI_MODE_SI);
SI_CS_LOW;
ADR |= 0x80 ; // RW = 1
shiftOut( ADR );
while (len-- > 0)
shiftOut( *(DATA++) );
SI_CS_HIGH;
}
#endif
static uint8_t SI4463_read_byte( uint8_t ADR )
{
uint8_t DATA ;
set_SPI_mode(SPI_MODE_SI);
SI_CS_LOW;
shiftOut( ADR );
DATA = shiftIn();
SI_CS_HIGH;
return DATA ;
}
#ifdef NOTUSED
static uint8_t SI4463_get_response(void* buff, uint8_t len)
{
uint8_t cts = 0;
// set_SPI_mode(SPI_MODE_SI);
cts = SI4463_READ_CTS;
if (!cts) {
return false;
}
// __disable_irq();
SI_CS_LOW;
shiftOut( SI446X_CMD_READ_CMD_BUFF );
cts = (shiftIn() == 0xFF);
if (cts)
{
// Get response data
for(uint8_t i=0;i<len;i++) {
((uint8_t*)buff)[i] = shiftIn();
}
}
SI_CS_HIGH;
// __enable_irq();
return cts;
}
#endif
void SI4463_do_first_api(void* data, uint8_t len, void* out, uint8_t outLen)
{
uint8_t *ptr = (uint8_t *)data;
set_SPI_mode(SPI_MODE_SI);
// SI4463_WAIT_CTS; // Wait for CTS
SI_CS_LOW;
#if 1 // Inline transfer
while (len--){
while (SPI_TX_IS_NOT_EMPTY(SI4432_SPI));
SPI_WRITE_8BIT(SI4432_SPI, *ptr++);
}
while (SPI_IS_BUSY(SI4432_SPI));
#else
while (len--)
shiftOut(*ptr++); // (pgm_read_byte(&((uint8_t*)data)[i]));
#endif
SI_CS_HIGH;
if(out == NULL) return; // If we have an output buffer then read command response into it
while (SPI_RX_IS_NOT_EMPTY(SI4432_SPI))
(void)SPI_READ_8BIT(SI4432_SPI); // Remove lingering bytes from SPI RX buffer
SI4463_WAIT_CTS; // Wait for CTS
SI_CS_LOW;
#if 1
SPI_WRITE_8BIT(SI4432_SPI, SI446X_CMD_READ_CMD_BUFF);
SPI_WRITE_8BIT(SI4432_SPI, 0xFF);
while (SPI_IS_BUSY(SI4432_SPI));
SPI_READ_16BIT(SI4432_SPI); // drop SI446X_CMD_READ_CMD_BUFF and CTS 0xFF
#else
shiftOut( SI446X_CMD_READ_CMD_BUFF );
shiftIn(); // Should always be 0xFF
#endif
// Get response data
ptr = (uint8_t *)out;
while (outLen--){
#if 1 // Inline transfer
SPI_WRITE_8BIT(SI4432_SPI, 0xFF);
while (SPI_RX_IS_EMPTY(SI4432_SPI)); //wait rx data in buffer
*ptr++ = SPI_READ_8BIT(SI4432_SPI);
#else
*ptr++ = shiftIn();
#endif
}
SI_CS_HIGH;
}
int SI4463_do_api(void* data, uint8_t len, void* out, uint8_t outLen)
{
uint8_t *ptr = (uint8_t *)data;
set_SPI_mode(SPI_MODE_SI);
if (SI4463_WAIT_CTS) return -1; // Wait for CTS
SI_CS_LOW;
#if 1 // Inline transfer
while (len--){
while (SPI_TX_IS_NOT_EMPTY(SI4432_SPI));
SPI_WRITE_8BIT(SI4432_SPI, *ptr++);
}
while (SPI_IS_BUSY(SI4432_SPI));
#else
while (len--)
shiftOut(*ptr++); // (pgm_read_byte(&((uint8_t*)data)[i]));
#endif
SI_CS_HIGH;
if(out == NULL) return 0; // If we have an output buffer then read command response into it
while (SPI_RX_IS_NOT_EMPTY(SI4432_SPI))
(void)SPI_READ_8BIT(SI4432_SPI); // Remove lingering bytes from SPI RX buffer
if (SI4463_WAIT_CTS) return -1; // Wait for CTS
SI_CS_LOW;
#if 1
SPI_WRITE_8BIT(SI4432_SPI, SI446X_CMD_READ_CMD_BUFF);
SPI_WRITE_8BIT(SI4432_SPI, 0xFF);
while (SPI_IS_BUSY(SI4432_SPI));
SPI_READ_16BIT(SI4432_SPI); // drop SI446X_CMD_READ_CMD_BUFF and CTS 0xFF
#else
shiftOut( SI446X_CMD_READ_CMD_BUFF );
shiftIn(); // Should always be 0xFF
#endif
// Get response data
ptr = (uint8_t *)out;
while (outLen--){
#if 1 // Inline transfer
SPI_WRITE_8BIT(SI4432_SPI, 0xFF);
while (SPI_RX_IS_EMPTY(SI4432_SPI)); //wait rx data in buffer
*ptr++ = SPI_READ_8BIT(SI4432_SPI);
#else
*ptr++ = shiftIn();
#endif
}
SI_CS_HIGH;
return 0;
}
#ifdef notused
static void SI4463_set_properties(uint16_t prop, void* values, uint8_t len)
{
// len must not be greater than 12
uint8_t data[16] = {
SI446X_CMD_SET_PROPERTY,
(uint8_t)(prop>>8),
len,
(uint8_t)prop
};
// Copy values into data, starting at index 4
memcpy(data + 4, values, len);
SI4463_do_api(data, len + 4, NULL, 0);
}
#endif
#include "si446x_cmd.h"
#include "radio_config_Si4468_undef.h"
#undef RADIO_CONFIGURATION_DATA_ARRAY
#include "radio_config_Si4468_default.h"
// Used in RBW setting
#define GLOBAL_GPIO_PIN_CFG 0x13, 0x07, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00
#define GLOBAL_CLK_CFG 0x11, 0x00, 0x01, 0x01, 0x00
// ---------------------------------------------------------------------------------------------------- v ------------ RSSI control byte
#define GLOBAL_RF_MODEM_RAW_CONTROL 0x11, 0x20, 0x0A, 0x45, 0x03, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x10, 0x40
//0x11 SI446X_CMD_SET_PROPERTY
//0x20 SI446X_PROP_GROUP_MODEM
//0x0A 10 Count
//0x45 Start register
//0x03 [0x45] MODEM_RAW_CONTROL
//0x00 [0x46] RAWEYE[10:8]
//0x00 [0x47] RAWEYE[7:0]
//0x01 [0x48] MODEM_ANT_DIV_MODE
//0x00 [0x49] MODEM_ANT_DIV_CONTROL
//0xFF [0x4A] MODEM_RSSI_THRESH
//0x06 [0x4B] MODEM_RSSI_JUMP_THRESH
//0x18 [0x4C] MODEM_RSSI_CONTROL
//0x10 [0x4D] MODEM_RSSI_CONTROL2
//0x40 [0x4E] MODEM_RSSI_COMP
// -----------------------------------------------------------------------------------------------------^ --------------
#define GLOBAL_RF_MODEM_AGC_CONTROL 0x11, 0x20, 0x01, 0x35, 0xF1 // Override AGC gain increase
#undef RF_MODEM_AGC_CONTROL_1
#define RF_MODEM_AGC_CONTROL_1 GLOBAL_RF_MODEM_AGC_CONTROL
#undef RF_MODEM_AGC_WINDOW_SIZE_12_1
//#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x07, 0x07, 0x80, 0x02, 0x4C, 0xCD, 0x00, 0x27, 0x0C, 0x84, 0x23
#define RF_MODEM_AGC_WINDOW_SIZE_12_1 0x11, 0x20, 0x0C, 0x38, 0x11, 0x07, 0x07, 0x80, 0x1C, 0x4C, 0xCD, 0x00, 0x27, 0x0C, 0x84, 0x23
#undef RF_GPIO_PIN_CFG
#define RF_GPIO_PIN_CFG GLOBAL_GPIO_PIN_CFG
#undef RF_GLOBAL_CLK_CFG_1
#define RF_GLOBAL_CLK_CFG_1 GLOBAL_CLK_CFG
// Remember to change RF_MODEM_AFC_LIMITER_1_3_1 !!!!!!!!!
static const uint8_t SI4468_config[] = RADIO_CONFIGURATION_DATA_ARRAY;
// Set new state
static int SI4463_set_state(si446x_state_t newState)
{
uint8_t data[] = {
SI446X_CMD_CHANGE_STATE,
newState
};
return SI4463_do_api(data, sizeof(data), NULL, 0);
}
static uint8_t gpio_state[5] = {
SI446X_GPIO_MODE_DIV_CLK,
SI446X_GPIO_MODE_CTS,
SI446X_GPIO_MODE_DONOTHING,
SI446X_GPIO_MODE_DONOTHING,
SI446X_GPIO_MODE_DRIVE1
};
int SI4463_refresh_gpio(void)
{
uint8_t data2[] = {
SI446X_CMD_GPIO_PIN_CFG,
gpio_state[0], // GPIO[0]
gpio_state[1], // GPIO[1]
gpio_state[2], // GPIO[2] // High
gpio_state[3], // GPIO[3] // TX/RX
gpio_state[4], // NIRQ // Direct
0, // SDO
0 // GEN_CONFIG
};
return SI4463_do_api(data2, sizeof(data2), NULL, 0);
}
void SI4463_set_gpio(int i, int s)
{
if (gpio_state[i] == s)
return;
gpio_state[i] = s;
#if 0 // debug gpio
gpio_state[2] = 3;
gpio_state[3] = 2;
#endif
SI4463_refresh_gpio();
}
#if 0
static void SI4463_clear_FIFO(void)
{
// 'static const' saves 20 bytes of flash here, but uses 2 bytes of RAM
static const uint8_t clearFifo[] = {
SI446X_CMD_FIFO_INFO,
SI446X_FIFO_CLEAR_RX | SI446X_FIFO_CLEAR_TX