From 507e10ccb404999737c375b210724d4cc0bad2fa Mon Sep 17 00:00:00 2001 From: Subhampal9 <122683549+Subhampal9@users.noreply.github.com> Date: Fri, 13 Dec 2024 10:39:20 +0530 Subject: [PATCH] adding more flexibility for without tie option --- .../glayout/glayout/flow/blocks/elementary/FVF/fvf.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/openfasoc/generators/glayout/glayout/flow/blocks/elementary/FVF/fvf.py b/openfasoc/generators/glayout/glayout/flow/blocks/elementary/FVF/fvf.py index 0bf6c63ae..ce1b83c0d 100644 --- a/openfasoc/generators/glayout/glayout/flow/blocks/elementary/FVF/fvf.py +++ b/openfasoc/generators/glayout/glayout/flow/blocks/elementary/FVF/fvf.py @@ -137,9 +137,10 @@ def flipped_voltage_follower( top_level << straight_route(pdk, fet_1_ref.ports["multiplier_0_drain_W"], drain_1_via.ports["bottom_met_E"]) top_level << c_route(pdk, drain_1_via.ports["top_met_S"], gate_2_via.ports["top_met_S"], extension=1.2*max(width[0],width[1]), cglayer="met2") top_level << straight_route(pdk, fet_2_ref.ports["multiplier_0_gate_E"], gate_2_via.ports["bottom_met_W"]) - - top_level << straight_route(pdk, fet_2_ref.ports["multiplier_0_source_W"], fet_2_ref.ports["tie_W_top_met_W"], glayer1=tie_layers2[1], width=0.2*sd_rmult, fullbottom=True) - + try: + top_level << straight_route(pdk, fet_2_ref.ports["multiplier_0_source_W"], fet_2_ref.ports["tie_W_top_met_W"], glayer1=tie_layers2[1], width=0.2*sd_rmult, fullbottom=True) + except: + pass #Renaming Ports top_level.add_ports(fet_1_ref.get_ports_list(), prefix="A_") top_level.add_ports(fet_2_ref.get_ports_list(), prefix="B_")