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gbt15.C
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gbt15.C
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/*************************************************************
* program name: gbt15.c *
* use parallel EPP/SPP port to r/w game boy cartridge *
* *
* ai[]=0 w a[7..0] *
* ai[]=1 w a[15..8] *
* ai[]=2 w control d7=rs,d6=spp,d1=xwe_en,d0=cs_en *
* ai[]=3 r/w data *
* *
* MBC1 *
* R/W A000~BFFF RAM SWITCHING BANK(256Kbit) 4 BANKS OF 8Kbyte *
* R 4000~7FFF ROM SWITCHING BANK(4Mbit) 32 BANKS OF 128Kbit *
* W 2000~3FFF SET ROM BANK (5 BIT) *
* R 0000~3FFF FIX ROM BANK 0 *
* W 4000~5FFF SET RAM BANK (2 BIT) *
* W 0000~1FFF SET 0A ENABLE RAM BANK *
* *
* MBC2 *
* R/W A000~BFFF 512 X 4 BIT RAM *
* R 4000~7FFF ROM SWITCHING BANK(2Mbit) 16 BANKS OF 128Kbit *
* W 2100 SET ROM BANK (4 BIT) *
* R 0000~3FFF FIX ROM BANK 0 *
* W 0000 SET 0A ENABLE RAM BANK *
* *
* MBC5 *
* R/W A000~BFFF RAM SWITCHING BANK(1Mbit) 16 BANKS OF 64 Kbit *
* R 4000~7FFF ROM SWITCHING BANK(64Mbit) 512 BANKS OF 128Kbit *
* W 3000~3FFF SET ROM BANK1(BANK Q8) TOTAL 9 BIT *
* W 2000~2FFF SET ROM BANK0(BANK Q7~Q0) *
* R 0000~3FFF FIX ROM BANK 0 *
* W 4000~7FFF SET RAM BANK (4 BIT) *
* W 0000~1FFF SET 0A ENABLE RAM BANK *
* *
*************************************************************/
#include <dos.h>
#include <stdio.h>
#include <stdlib.h>
#include <io.h>
#include <dir.h>
#include <string.h>
#define ai port_b
#define data port_c
#define trans_size 32768
//#define set_ai_write outportb(port_a,5); // ninit=1, nwrite=0
#define set_data_read outportb(port_a,0); // nastb=1,nib_sel=0,ndstb=1,nwrite=1
#define set_data_write outportb(port_a,1); // nastb=1,nib_sel=0,ndstb=1,nwrite=0
//#define set_data_write outportb(port_a,1); // ninit=0, nwrite=0
//#define set_data_read outportb(port_a,0); // ninit=0, nwrite=1
#define set_normal outportb(port_a,4); // ninit=1, nwrite=1
#define retry_time 3;
unsigned long time_out;
unsigned int port[2];
unsigned char port_no;
unsigned int port_8,port_9,port_a,port_b,port_c;
unsigned int bank,bank_size;
unsigned long maxfilesize;
char *file_name=NULL;
unsigned char cmd,eeprom_type; // command
FILE *fptr;
union mix_buffer {
unsigned char buffer[32768];
unsigned int bufferx[16384];
}mix;
unsigned int i,j,idx,gcrc;
unsigned char temp,mbc1_exp;
unsigned long filesize;
unsigned char header_ok,cart_type,rom_size,ram_size,sram_bank_num;
char port_type=0; // 0=epp, 1=spp
char epp_spp=0;
char pocket_camera=0; // 0=not pocket camera sram(1Mbits)
/**************************************
* Subroutine *
**************************************/
void disp_buffer(unsigned int disp_len)
{
int i,j,x,y;
for (i=0; i<disp_len ; i++)
{
if ((i & 0xf)==0)
printf("%04x : ",i&0xfff0);
if ((i & 0xf)==8)
printf("- ");
printf("%02x ",mix.buffer[i]);
if ((i & 0xf)==0xf)
{
printf("-> ");
for (j=0; j<16 ; j++)
{
if (mix.buffer[(i&0xfff0)+j]<0x20 || mix.buffer[(i&0xfff0)+j]>0x80)
printf (".");
else
printf ("%c",mix.buffer[(i&0xfff0)+j]);
}
printf("\n");
}
}
y=disp_len&0xf;
if (y) /* not equal 16*?? */
{
for (x=y;x<16;x++)
{
if ((x & 0xf)==8)
printf("- ");
printf(" ");
if ((x & 0xf)==0xf)
{
printf("-> ");
for (j=0; j<y ; j++)
{
if (mix.buffer[(i&0xfff0)+j]<0x20 || mix.buffer[(i&0xfff0)+j]>0x80)
printf (".");
else
printf ("%c",mix.buffer[(i&0xfff0)+j]);
}
printf("\n");
}
}
}
}
/*void port_set_read(void)
{
outportb(port_a,0); // nastb=1,nib_sel=0,ndstb=1,nwrite=1
}
void port_set_write(void)
{
outportb(port_a,1); // nastb=1,nib_sel=0,ndstb=1,nwrite=0
}*/
void spp_set_ai(unsigned char _ai)
{
set_data_write
// outportb(port_a,1); // nastb=1,nib_sel=0,ndstb=1,nwrite=0
outportb(port_8,_ai); // put ai at data bus
outportb(port_a,9); // nastb=0,nib_sel=0,ndstb=1,nwrite=0
outportb(port_a,1); // nastb=1,nib_sel=0,ndstb=1,nwrite=0
// nastb ~~~~|___|~~~~
}
void spp_write_data(unsigned char _data)
{
// outportb(port_a,1); // nastb=1,nib_sel=0,ndstb=1,nwrite=0
outportb(port_8,_data); // put data at data bus
outportb(port_a,3); // nastb=1,nib_sel=0,ndstb=0,nwrite=0
outportb(port_a,1); // nastb=1,nib_sel=0,ndstb=1,nwrite=0
// ndstb ~~~~|___|~~~~
}
void spp_set_ai_data(unsigned char _ai,unsigned char _data)
{
spp_set_ai(_ai);
spp_write_data(_data);
}
char spp_read_data(void)
{
char low_nibble,high_nibble,temp;
set_data_read
outportb(port_a,2); // nastb=1,nib_sel=0,ndstb=0,nwrite=1
low_nibble=inportb(port_9);
outportb(port_a,6); // nastb=1,nib_sel=1,ndstb=0,nwrite=1
high_nibble=inportb(port_9);
outportb(port_a,0); // nastb=1,nib_sel=0,ndstb=1,nwrite=1
// nibble_sel ___|~~~ and ndstb ~~~~|___|~~~~
temp=(((high_nibble<<1)&0xf0)|((low_nibble>>3)&0x0f));
// printf("temp=%x",temp);
return(temp);
}
void epp_set_ai(unsigned char _ai)
{
set_data_write
outportb(ai,_ai);
}
void epp_set_ai_data(unsigned char _ai,unsigned char _data)
{
epp_set_ai(_ai);
set_data_write
outportb(data,_data);
}
void set_ai(unsigned char _ai)
{
set_data_write
if (port_type)
spp_set_ai(_ai);
else
epp_set_ai(_ai);
}
void set_ai_data(unsigned char _ai,unsigned char _data)
{
if (port_type)
spp_set_ai_data(_ai,_data); // spp mode
else
epp_set_ai_data(_ai,_data); // epp mode
}
void write_data(unsigned char _data)
{
if (port_type)
spp_write_data(_data); // spp write data
else
outportb(data,_data); // epp write data
}
unsigned char read_data(void)
{
if (port_type){
return(spp_read_data()); // spp read data
}
else{
return(inportb(data)); // epp read data
}
}
void init_port(void)
{
outportb(port_9,1); // clear EPP time flag
set_ai_data(2,0); // rst=0, wei=0(dis.), rdi=0(dis.)
set_ai_data(2,0x80); // rst=1, wei=0(dis.), rdi=0(dis.)
}
void end_port(void)
{
set_ai_data(2,0); // rst=0, wei=0(dis.), rdi=0(dis.)
set_normal // ninit=1, nWrite=1
}
unsigned char write_32k_file(void)
{
if (fwrite((char *)mix.buffer,sizeof(char),trans_size,fptr)!=trans_size)
{
fclose(fptr); /* write data error */
return(1);
}
// printf(".");
return(0);
}
unsigned char read_8k_file()
{
if (fread((char *)mix.buffer,sizeof(char),0x2000,fptr)!=0x2000)
{
printf("read error!!!\07\n");
fclose(fptr); /* read data error */
return(1);
}
// printf(".");
return(0);
}
unsigned char read_16k_file()
{
if (fread((char *)mix.buffer,sizeof(char),0x4000,fptr)!=0x4000)
{
printf("read error!!!\07\n");
fclose(fptr); /* read data error */
return(1);
}
// printf(".");
return(0);
}
unsigned char read_32k_file()
{
if (fread((char *)mix.buffer,sizeof(char),trans_size,fptr)!=trans_size)
{
printf("read error!!!\07\n");
fclose(fptr); /* read data error */
return(1);
}
printf(".");
return(0);
}
void set_adr(unsigned int adr) // *****
{
//unsigned char temp;
set_ai_data(0,(adr & 0xff)); // a[7..0]
set_ai_data(1,((adr>>8) & 0xff)); // a[15..8]
set_ai(3);
set_data_read // ninit=0, nWrite=1
}
int write_file_32k(void)
{
if (fwrite((char *)mix.buffer,sizeof(char),trans_size,fptr)!=trans_size)
{
fclose(fptr); /* write data error */
return(-1);
}
printf(".");
return(0);
}
char write_file_xxk(unsigned int write_size)
{
if (fwrite((char *)mix.buffer,sizeof(char),write_size,fptr)!=write_size)
{
fclose(fptr); /* write data error */
return(-1);
}
printf(".");
return(0);
}
void set_bank(unsigned int adr,unsigned char bank)
{
// printf("adr=%x bank=%x\n",adr,bank);
set_ai_data(2,0x80); // disable inc
set_ai_data(0,(adr & 0xff)); // a[7..0]
set_ai_data(1,((adr>>8) & 0x7f)); // a[15..8]
set_ai_data(3,bank); // write bank no
set_data_read // ninit=0, nWrite=1
}
void set_rom_bank(unsigned char bank)
{
// cart_type <4 is MCB1, other is MCB2
if (cart_type < 4)
set_bank(0x2000,bank); // for MCB1
else
set_bank(0x2100,bank); // for MCB2
}
void delay_10us()
{
long x;
for (x=0;x<0x2000;x++);
}
void delay_100us()
{
long x;
for (x=0;x<0x10000;x++);
}
void delay_20ms()
{
long x;
for (x=0;x<0xfffff;x++);
}
void out_byte_eeprom(unsigned char d)
{
set_ai_data(2,0x82); // wei enable
set_ai(3); // default write mode
// set_data_read // ninit=0, nWrite=1
set_data_write
write_data(d); // out data
// outportb(data,d); // out data
set_ai_data(2,0x80); // wei disable
set_ai(3); // default write mode
}
void out_byte(unsigned char d)
{
set_ai(3);
// set_data_read // ninit=0, nWrite=1
set_data_write
write_data(d); // out data
// outportb(data,d); // out data
}
void out_data(unsigned char h,unsigned char m,unsigned char l,unsigned char d)
{
// ai[]=2 w control d7=rs,d1=xwe_en,d0=cs_en
h=((h<<2)|(m>>6))&0x1f; // maximum bank is 1f
if (h)
m=(m & 0x3f)|0x40; // >bank 0
else
m=m & 0x3f; // bank 0
set_adr(0x2000); // write 2000:h
set_data_write
write_data(h); // set rom bank value
// outportb(data,h); // set rom bank value
set_ai_data(1,m); // a[15..8]
set_ai_data(0,l); // a[7..0]
out_byte_eeprom(d); // write data to eeprom
}
void out_adr2_data(unsigned long adr,unsigned char d) // address shift 1 bit
{
unsigned char h,m,l;
set_ai_data(2,0x80); // disable wr/rd inc.
adr<<=1; // adr x 2
l=adr & 0xff; // a7~a0
m=(adr>>8) & 0x3f; // a13~a8
h=(adr>>14) & 0xff; // a21~a13
if (h)
m|=0x40; // >bank 0
set_adr(0x2000); // write 2000:h
set_data_write
write_data(h); // set rom bank value
// outportb(data,h); // set rom bank value
set_ai_data(1,m); // a[15..8]
set_ai_data(0,l); // a[7..0]
out_byte_eeprom(d); // write data to eeprom
}
void out_adr_data(unsigned long adr,unsigned char d) // real address
{
unsigned char xh,h,m,l;
set_ai_data(2,0x80); // disable wr/rd inc.
l=adr & 0xff; // a7~a0
m=(adr>>8) & 0x3f; // a13~a8
h=(adr>>14) & 0xff; // a21~a13
xh=(adr>>22) & 0x7; // max. 256Mbit
if (h|xh)
m|=0x40; // >bank 0
set_adr(0x3000); // write 3000:sh
set_data_write
write_data(xh); // set rom bank extend value
set_adr(0x2000); // write 2000:h
set_data_write
write_data(h); // set rom bank value
// outportb(data,h); // set rom bank value
set_ai_data(1,m); // a[15..8]
set_ai_data(0,l); // a[7..0]
out_byte_eeprom(d); // write data to eeprom
}
void set_adr_long(unsigned long adr) // real address
{
unsigned char xh,h,m,l;
set_ai_data(2,0x80); // disable wr/rd inc.
l=adr & 0xff; // a7~a0
m=(adr>>8) & 0x3f; // a13~a8
h=(adr>>14) & 0xff; // a21~a13
xh=(adr>>22) & 0x7; // max. 256Mbit
if (h|xh)
m|=0x40; // >bank 0
set_adr(0x3000); // write 3000:sh
set_data_write
write_data(xh); // set rom bank extend value
set_adr(0x2000); // write 2000:h
set_data_write
write_data(h); // set rom bank value
// outportb(data,h); // set rom bank value
set_ai_data(1,m); // a[15..8]
set_ai_data(0,l); // a[7..0]
}
unsigned char read_byte(void)
{
set_ai(3); // default write mode
set_data_read // ninit=0, nWrite=1
return (read_data());
// return (inportb(data));
}
void enable_protection(void)
{
// set_bank(0x2000,0); // set bank 0
out_data(0,0x55,0x55,0xaa); /* adr2,adr1,adr0,data 05555:aa */
out_data(0,0x2a,0xaa,0x55);
out_data(0,0x55,0x55,0xa0);
}
void disable_protection(void)
{
out_data(0,0x55,0x55,0xaa); /* adr2,adr1,adr0,data 05555:aa */
out_data(0,0x2a,0xaa,0x55);
out_data(0,0x55,0x55,0x80);
out_data(0,0x55,0x55,0xaa);
out_data(0,0x2a,0xaa,0x55);
out_data(0,0x55,0x55,0x20);
delay_20ms();
}
int data_polling_data(unsigned char last_data)
{
unsigned char loop;
unsigned long timeout=0;
// delay_10us(); // call delay
loop = 1;
while ((timeout<0x07ffffff) && (loop))
{
if (((read_byte() ^ last_data) & 0x80)==0) // end wait
loop = 0; // ready to exit the while loop
timeout++;
}
// printf("timeout = %x\n",timeout);
return(loop);
}
int data_polling(void)
{
unsigned char loop,predata,currdata;
unsigned long timeout=0;
// delay_10us(); // call delay
loop = 1;
predata = read_byte() & 0x40;
while ((timeout<0x07ffffff) && (loop))
{
currdata = read_byte() & 0x40;
if (predata == currdata)
loop = 0; // ready to exit the while loop
predata = currdata;
timeout++;
}
// printf("timeout = %x\n",timeout);
return(loop);
}
void reset_to_read(void) // return to read mode
{
out_adr2_data(0x5555,0xaa); // 5555:aa adr2,adr1,adr0,data
out_adr2_data(0x2aaa,0x55); // 2aaa:55
out_adr2_data(0x5555,0xf0); // 5555:f0
}
void read_status_reg_cmd(void)
{
out_adr2_data(0x5555,0xaa); // 5555:aa adr2,adr1,adr0,data
out_adr2_data(0x2aaa,0x55); // 2aaa:55
out_adr2_data(0x5555,0x70); // 5555:70
}
char wait_status(void)
{
unsigned temp;
temp=read_byte(); // read first status byte
// printf("temp=%x ",temp);
while ((temp & 0xfc)!=0x80){
// printf("temp=%x ",temp);
if ((temp & 0x20)==0x20){
printf("Fail in erase!!!\07\n");
return(-1);
}
if ((temp & 0x10)==0x10){
printf("Fail in program!!!\07\n");
return(-2);
}
temp=read_data();
// temp=inportb(data);
}
// reset_to_read();
return(0);
}
char mx_erase(void)
{
out_adr2_data(0x5555,0xaa); // 5555:aa adr2,adr1,adr0,data
out_adr2_data(0x2aaa,0x55); // 2aaa:55
out_adr2_data(0x5555,0x80); // 5555:80
out_adr2_data(0x5555,0xaa); // 5555:aa
out_adr2_data(0x2aaa,0x55); // 2aaa:55
out_adr2_data(0x5555,0x10); // 5555:10
delay_100us();
// read_status_reg_cmd(); // send read status reg. cmd
if(wait_status()==0){
reset_to_read();
printf("erase ok\n");
return(0);
}
else{
reset_to_read();
printf("erase error!!!\07\n");
return(-1);
}
}
char win_erase(void)
{
out_data(0,0x55,0x55,0xaa); /* adr2,adr1,adr0,data 05555:aa */
out_data(0,0x2a,0xaa,0x55);
out_data(0,0x55,0x55,0x80);
out_data(0,0x55,0x55,0xaa);
out_data(0,0x2a,0xaa,0x55);
out_data(0,0x55,0x55,0x10);
delay_20ms();
if (data_polling()){
printf("erase error!!!\n");
return(-1);
}
else{
printf("erase ok!\n");
return(0);
}
}
unsigned char intel_read_status(void)
{
out_adr_data(0,0x70); // read status command
return(read_byte());
}
char intel_check_status(void)
{
time_out=0x8000;
while (!(intel_read_status() & 0x80)){
time_out--;
if (time_out==0){
printf("Intel read status time out\n");
printf("status = %x\n",intel_read_status());
out_adr_data(0,0x50); // clear status register
return(-1);
}
}
return(0);
}
char intel_block_erase(unsigned long block){
time_out=0x8000;
while ((intel_read_status())!=0x80){
time_out--;
if (time_out==0){
printf("Intel Block erase time out\n");
printf("status = %x\n",intel_read_status());
return(-1);
}
}
out_adr_data(block,0x20); // Block erase
out_adr_data(block,0xd0); // write confirm
time_out=0x8000;
while (!(intel_read_status() & 0x80)){
time_out--;
if (time_out==0){
printf("Intel Block erase time out at %lx\n",block);
printf("status = %x\n",intel_read_status());
out_adr_data(block,0x50); // clear status register
printf("status = %x\n",intel_read_status());
return(-1);
}
}
if ((intel_read_status())==0x80){
printf("e");
return(0);
}
else{
printf("Intel Block erase error at %lx\n",block);
printf("status = %x\n",intel_read_status());
out_adr_data(block,0x50); // clear status register
printf("status = %x\n",intel_read_status());
out_adr_data(0x0000,0xff); // read array
return(-1);
}
}
char intel_erase(void)
{
unsigned long block;
for (block=0;block<64;block++){
if (intel_block_erase(block*0x20000))
return(-1); // something error
}
printf("\nErase completed\n");
return(0);
}
char erase(void)
{
if (eeprom_type==4)
return(win_erase());
if (eeprom_type==16)
return(mx_erase());
if (eeprom_type==64)
return(intel_erase());
printf("eeprom type error!\07\n");
return(-1);
}
char sector_erase(unsigned long sector)
{
unsigned char temp;
out_adr2_data(0x5555,0xaa); // 5555:aa adr2,adr1,adr0,data
out_adr2_data(0x2aaa,0x55); // 2aaa:55
out_adr2_data(0x5555,0x80); // 5555:80
out_adr2_data(0x5555,0xaa); // 5555:aa
out_adr2_data(0x2aaa,0x55); // 2aaa:55
out_adr2_data(sector,0x30); // sector:30
delay_100us();
// read_status_reg_cmd(); // send read status reg. cmd
if(wait_status()==0){
// reset_to_read();
// printf("erase ok\n");
printf("s");
return(0);
}
else{
reset_to_read();
printf("sector erase error!!!\07\n");
return(-1);
}
}
void mx_id(void)
{
out_adr2_data(0x5555,0xaa); /* softwave product ID entry */
out_adr2_data(0x2aaa,0x55); /* adr2,adr1,adr0,data */
out_adr2_data(0x5555,0x90); /* adr2,adr1,adr0,data */
// delay_10us();
set_adr(0); /* adr2,adr1,adr0 */
printf("Manufacturer Code : %x\n",read_byte());
set_adr(2); /* adr2,adr1,adr0 */
printf("Device Code : %x\n",read_byte());
set_adr(4); /* adr2,adr1,adr0 */
printf("First 16k protection Code : %x\n",read_byte());
reset_to_read(); // reset to read mode
}
void win_id(void)
{
out_data(0,0x55,0x55,0xaa); /* softwave product ID entry */
out_data(0,0x2a,0xaa,0x55); /* adr2,adr1,adr0,data */
out_data(0,0x55,0x55,0x80); /* adr2,adr1,adr0,data */
out_data(0,0x55,0x55,0xaa); /* adr2,adr1,adr0,data */
out_data(0,0x2a,0xaa,0x55); /* adr2,adr1,adr0,data */
out_data(0,0x55,0x55,0x60); /* adr2,adr1,adr0,data */
delay_10us();
set_adr(0); /* adr2,adr1,adr0 */
printf("Manufacturer Code : %x\n",read_byte());
set_adr(1); /* adr2,adr1,adr0 */
printf("Device Code : %x\n",read_byte());
// set_adr(2); /* adr2,adr1,adr0 */
// printf("First 16k protection Code : %x\n",read_byte());
// set_bank(0x2000,0x1f);
// set_adr(0x7ff2); /* adr2,adr1,adr0=0x7fff2 */
// printf("Last 16k protection Code : %x\n",read_byte());
out_data(0,0x55,0x55,0xaa); /* softwave product ID exit */
out_data(0,0x2a,0xaa,0x55); /* adr2,adr1,adr0,data */
out_data(0,0x55,0x55,0xf0); /* adr2,adr1,adr0,data */
}
void intel_id(void)
{
out_adr_data(0,0x98); // Read Query
for (i=0;i<128;i+=2){
set_adr(i); /* adr2,adr1,adr0 */
mix.buffer[i/2]=read_byte();
}
// disp_buffer(64);
printf("Manufacture Code = %x\n",mix.buffer[0]);
printf("Device Code = %x\n",mix.buffer[1]);
}
void disp_id(void)
{
if (eeprom_type==4)
win_id();
if (eeprom_type==16)
mx_id();
if (eeprom_type==64)
intel_id();
}
void out_adr_data_32k(unsigned int adr,unsigned char data)
{
set_adr(adr); // write adr:data
out_byte_eeprom(data); // write data to eeprom
}
char check_eeprom(void)
{
// check 4M flash
// out_data(0,0x55,0x55,0xaa); /* softwave product ID entry */
// out_data(0,0x2a,0xaa,0x55); /* adr2,adr1,adr0,data */
// out_data(0,0x55,0x55,0x80); /* adr2,adr1,adr0,data */
// out_data(0,0x55,0x55,0xaa); /* adr2,adr1,adr0,data */
// out_data(0,0x2a,0xaa,0x55); /* adr2,adr1,adr0,data */
// out_data(0,0x55,0x55,0x60); /* adr2,adr1,adr0,data */
out_adr_data_32k(0x5555,0xaa); // softwave product ID entry
out_adr_data_32k(0x2aaa,0x55);
out_adr_data_32k(0x5555,0x80);
out_adr_data_32k(0x5555,0xaa);
out_adr_data_32k(0x2aaa,0x55);
out_adr_data_32k(0x5555,0x60);
delay_10us();
set_adr(0); /* adr2,adr1,adr0 */
// printf("Manufacturer Code : %x\n",read_byte());
if (read_byte()!=0xda) goto check_16m;
set_adr(1); /* adr2,adr1,adr0 */
// printf("Device Code : %x\n",read_byte());
if (read_byte()!=0x46) goto check_16m;
// out_data(0,0x55,0x55,0xaa); /* softwave product ID exit */
// out_data(0,0x2a,0xaa,0x55); /* adr2,adr1,adr0,data */
// out_data(0,0x55,0x55,0xf0); /* adr2,adr1,adr0,data */
out_adr_data_32k(0x5555,0xaa); /* softwave product ID exit */
out_adr_data_32k(0x2aaa,0x55); /* adr2,adr1,adr0,data */
out_adr_data_32k(0x5555,0xf0); /* adr2,adr1,adr0,data */
eeprom_type=4; // windbond 4M flash
return(0);
// 16M flash
check_16m:
out_adr2_data(0x5555,0xaa); /* 5555:aa softwave product ID entry */
out_adr2_data(0x2aaa,0x55); /* 2aaa:55 adr2,adr1,adr0,data */
out_adr2_data(0x5555,0x90); /* 5555:90 adr2,adr1,adr0,data */
// delay_10us();
set_adr(0); /* adr2,adr1,adr0 */
// printf("Manufacturer Code : %x\n",read_byte());
if (read_byte()!=0xc2){
reset_to_read();
goto check_64m;
// return(1);
}
set_adr(2); /* adr2,adr1,adr0 */
// printf("Device Code : %x\n",read_byte());
if (read_byte()!=0xf1){
reset_to_read();
goto check_64m;
// return(1);
}
reset_to_read(); // reset to read mode
eeprom_type=16; // MX 16M flash
return(0);
check_64m:
init_port();
out_adr_data(0x0000,0x98); // Read Query
for (i=0;i<128;i+=2){
set_adr(i); /* adr2,adr1,adr0 */
mix.buffer[i/2]=read_byte();
}
// disp_buffer(64);
if (mix.buffer[0]==0x89 && mix.buffer[1]==0x15 &&
mix.buffer[0x10]=='Q' && mix.buffer[0x11]=='R' &&
mix.buffer[0x12]=='Y'){
eeprom_type=64;
out_adr_data(0x0000,0xff); // read array
return(0);
}
else{
return(1);
}
}
void set_sram_bank(unsigned char bank)
{
set_adr(0x4000); // set sram adr
out_byte(bank); // sram bank 0
}
void read_eeprom_16k(unsigned int bank_16k)
{
printf("r");
idx=0;
if (mbc1_exp){
set_bank(0x6000,0); // for MCB1 expand bank
if ((bank_16k & 0x1f)==0){
set_sram_bank((bank_16k>>5) & 0x3); // use sram bank intend rom bank
// printf("^");
}
bank_16k=bank_16k& 0x1f;
}
set_bank(0x2000,bank_16k); // for MCB1 16k bank
for (j=0;j<64;j++){ // 16k bytes = 64 x 256 bytes
if (bank_16k)
set_ai_data(1,(j|0x40)); // set adr[15..8]
else
set_ai_data(1,j); // a[15..0]
set_ai_data(0,0); // a[7..0]
set_ai_data(2,0x81); // enable read inc.
set_ai(3); // read/write data
set_data_read
for (i=0;i<256;i++) { // page=256
// set_ai_data(0,i); // a[7..0]
// mix.buffer[idx+i]=read_byte();
mix.buffer[idx+i]=read_data();
// mix.buffer[idx+i]=inportb(data);
}
idx=idx+256;
}
// printf(" ok\n");
}
char verify_eeprom_16k(unsigned int bank_16k)
{
printf("v");
idx=0;
if (mbc1_exp){
set_bank(0x6000,0); // for MCB1 expand bank
if ((bank_16k & 0x1f)==0){
set_sram_bank((bank_16k>>5) & 0x3); // use sram bank intend rom bank
// printf("^");
}
bank_16k=bank_16k& 0x1f;
}
set_bank(0x3000,(bank_16k>>8)&0xff); // for MCB1 16k bank
set_bank(0x2000,bank_16k & 0xff); // for MCB1 16k bank
for (j=0;j<64;j++){ // 16k bytes = 64 x 256 bytes
if (bank_16k)
set_ai_data(1,(j|0x40)); /* set adr[15..8] */
else
set_ai_data(1,j);
set_ai_data(0,0); // a[7..0]
set_ai_data(2,0x81); // enable read inc.
set_ai(3); // read/write data
set_data_read
for (i=0;i<256;i++) {
temp=read_data();
// temp=inportb(data);
if(temp!=mix.buffer[idx+i]) {
//init_port();
printf(" error at %lx!\07\n",(bank_16k*16384)+(j*256)+i);
return(-1);
}
}
idx=idx+256;
}
// printf(" ok\n");
return(0);
}
void set_page_write(void) // start page write command
{
out_adr2_data(0x5555,0xaa); // 5555:aa adr2,adr1,adr0,data
out_adr2_data(0x2aaa,0x55); // 2aaa:55
out_adr2_data(0x5555,0xa0); // 5555:a0
}
char page_write_128(unsigned int bank_16k,unsigned char hi_lo)
{
unsigned char retry,temp,verify_ok;
retry=retry_time;
while(retry){
set_page_write(); // each page is 128 bytes
set_bank(0x2000,bank_16k); // for MCB1 16k bank
if (bank_16k)
set_ai_data(1,(j|0x40)); // set adr[15..8]
else
set_ai_data(1,j);
set_ai_data(0,hi_lo); // a[7..0]
set_ai_data(2,0x83); // enable flash write inc.
set_ai(3); // read/write data
for (i=0;i<128;i++){
// outportb(port_8,mix.buffer[idx+i]);
// outportb(port_a,0x03); // ndstb=0
// outportb(port_a,0x01); // ndstb=1
write_data(mix.buffer[idx+i]);// write data to eeprom
// outportb(data,mix.buffer[idx+i]);// write data to eeprom
}
set_ai_data(2,0x80); // disable wr/rd inc.
delay_10us();
// delay_20ms();
// set_ai_data(1,0x00); // ce=lo
// set_ai_data(0,hi_lo|0x7f); // point to last address
if (wait_status()){
printf("write error !!!\n");
return(-1);
}