Custom Board output issue

[Luigi90900]

I have been working on a board that is similar to the Wii Dual in layout and nearly identical in pinout (I was hoping to use the same firmware build settings when generating the firmware) The board powers up and the LED comes on flashing for a few seconds before turning solid, but there is no output from any pin on the FPGA in either state. I'm not sure what could be causing that problem so I'm unsure of where to troubleshoot. This is my first FPGA project so I am a bit of a moron when it comes to this stuff.

It is connected to the Wii AVE-RVL through some short wires because I don't have a flex cable like the Wii Dual, and the signals reach the pins on the FPGA. Checking every output with an oscilloscope shows zero activity. The only pin that seems to do something is the LED pin.

[ikorb]

It's hard for me to diagnose something like this, but the initial LED flashing may just be the FPGA trying to configure itself. Check if the FPGA actually reports a successful configuration on the DONE pin.

[Luigi90900]

The Done pin does go high. I can see the activity on the SPI bus as well. I figure something about the way I built the firmware isn't working quite right, but I'm not sure what that could be.

[Luigi90900]

In case it matters, I programmed the flash indirectly through the FPGA's JTAG interface following Xilinx's documentation from the .mcs file in the latest release. The flash is a M25PE40, rather than a P40, but I made sure to select the correct part when flashing with impact. When programmed, the verification passes and it shows the FPGA was programmed successfully.

[ikorb]

Unfortunately debugging this will not be easy, At this point it could be caused by a lot of things and the regular output signals are not sufficient to determine the cause - your specific problem could be anything from a missing/misconnected 54MHz clock, non-locking PLLs due to a "dirty" 54MHz signal, missing syncs due to a misconnected VData signal, missing/miscompiled ZPU code, problems with the startup delay (requires BClock) etc. etc.

Since you can do custom builds, your best bet is probably to selectively route some signals to external pins to scope them. Good candidates for that would be the "Locked" signal from ClockGen, the ZPU Reset signal, some low bit from the ZPU ROM address bus, HSync/VSync from the output of gcdv_decoder and possibly more depending on the results.

[Luigi90900]

Thanks for the help, I'll start checking things there.

[Luigi90900]

Just to clarify some things, what signals are necessary for the board to output video? Obviously you need Data 0-7, 54 MHz, and CSel. But are the I2S lines also needed?

[ikorb]

54MHz clock, VData 0-7, CSel and BClock are required - the last one is used to delay the actual startup a bit because the 54MHz clock signal takes some time to become stable on Wii and without delay the PLL would sometimes fail to lock.

[jmsunseri]

What FGPA chip did you go with? I was thinking about making something based on the Spartan-7 using GC Dual as a template but simplified closer to an internal Pluto II mod.

[Luigi90900]

I used the Spartan 3A XC3S200A

[Luigi90900]

I changed some of the pin definitions, so I had to recompile the bitstream, but you should be able to use the existing ones if you don't change anything like that.

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On Thu, Jul 27, 2023 at 10:11 PM Justin Sunseri ***@***.***> wrote: did you need to modify any of the HDL or were you able to use one of the existing ones? If so which one? — Reply to this email directly, view it on GitHub <#94 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AIX5ATICCCUQWMVRAHBRZ5DXSMNVTANCNFSM5Z4Q3BCA> . You are receiving this because you authored the thread.Message ID: ***@***.***>